Tue, 26 Nov 2013 18:38:19 -0800
8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
Summary: Use new nodes for loadFence/storeFence intrinsics in C2.
Reviewed-by: kvn, dholmes
1 //
2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
25 // X86 Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
186 %}
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
201 #define __ _masm.
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
230 // Offset hacking within calls.
231 static int pre_call_resets_size() {
232 int size = 0;
233 Compile* C = Compile::current();
234 if (C->in_24_bit_fp_mode()) {
235 size += 6; // fldcw
236 }
237 if (C->max_vector_size() > 16) {
238 size += 3; // vzeroupper
239 }
240 return size;
241 }
243 static int preserve_SP_size() {
244 return 2; // op, rm(reg/reg)
245 }
247 // !!!!! Special hack to get all type of calls to specify the byte offset
248 // from the start of the call to the point where the return address
249 // will point.
250 int MachCallStaticJavaNode::ret_addr_offset() {
251 int offset = 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points
252 if (_method_handle_invoke)
253 offset += preserve_SP_size();
254 return offset;
255 }
257 int MachCallDynamicJavaNode::ret_addr_offset() {
258 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points
259 }
261 static int sizeof_FFree_Float_Stack_All = -1;
263 int MachCallRuntimeNode::ret_addr_offset() {
264 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
265 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
266 }
268 // Indicate if the safepoint node needs the polling page as an input.
269 // Since x86 does have absolute addressing, it doesn't.
270 bool SafePointNode::needs_polling_address_input() {
271 return false;
272 }
274 //
275 // Compute padding required for nodes which need alignment
276 //
278 // The address of the call instruction needs to be 4-byte aligned to
279 // ensure that it does not span a cache line so that it can be patched.
280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
281 current_offset += pre_call_resets_size(); // skip fldcw, if any
282 current_offset += 1; // skip call opcode byte
283 return round_to(current_offset, alignment_required()) - current_offset;
284 }
286 // The address of the call instruction needs to be 4-byte aligned to
287 // ensure that it does not span a cache line so that it can be patched.
288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
289 current_offset += pre_call_resets_size(); // skip fldcw, if any
290 current_offset += preserve_SP_size(); // skip mov rbp, rsp
291 current_offset += 1; // skip call opcode byte
292 return round_to(current_offset, alignment_required()) - current_offset;
293 }
295 // The address of the call instruction needs to be 4-byte aligned to
296 // ensure that it does not span a cache line so that it can be patched.
297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
298 current_offset += pre_call_resets_size(); // skip fldcw, if any
299 current_offset += 5; // skip MOV instruction
300 current_offset += 1; // skip call opcode byte
301 return round_to(current_offset, alignment_required()) - current_offset;
302 }
304 // EMIT_RM()
305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
306 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
307 cbuf.insts()->emit_int8(c);
308 }
310 // EMIT_CC()
311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
312 unsigned char c = (unsigned char)( f1 | f2 );
313 cbuf.insts()->emit_int8(c);
314 }
316 // EMIT_OPCODE()
317 void emit_opcode(CodeBuffer &cbuf, int code) {
318 cbuf.insts()->emit_int8((unsigned char) code);
319 }
321 // EMIT_OPCODE() w/ relocation information
322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
323 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
324 emit_opcode(cbuf, code);
325 }
327 // EMIT_D8()
328 void emit_d8(CodeBuffer &cbuf, int d8) {
329 cbuf.insts()->emit_int8((unsigned char) d8);
330 }
332 // EMIT_D16()
333 void emit_d16(CodeBuffer &cbuf, int d16) {
334 cbuf.insts()->emit_int16(d16);
335 }
337 // EMIT_D32()
338 void emit_d32(CodeBuffer &cbuf, int d32) {
339 cbuf.insts()->emit_int32(d32);
340 }
342 // emit 32 bit value and construct relocation entry from relocInfo::relocType
343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
344 int format) {
345 cbuf.relocate(cbuf.insts_mark(), reloc, format);
346 cbuf.insts()->emit_int32(d32);
347 }
349 // emit 32 bit value and construct relocation entry from RelocationHolder
350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
351 int format) {
352 #ifdef ASSERT
353 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
354 assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
355 }
356 #endif
357 cbuf.relocate(cbuf.insts_mark(), rspec, format);
358 cbuf.insts()->emit_int32(d32);
359 }
361 // Access stack slot for load or store
362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
363 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
364 if( -128 <= disp && disp <= 127 ) {
365 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
366 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
367 emit_d8 (cbuf, disp); // Displacement // R/M byte
368 } else {
369 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
370 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
371 emit_d32(cbuf, disp); // Displacement // R/M byte
372 }
373 }
375 // rRegI ereg, memory mem) %{ // emit_reg_mem
376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
377 // There is no index & no scale, use form without SIB byte
378 if ((index == 0x4) &&
379 (scale == 0) && (base != ESP_enc)) {
380 // If no displacement, mode is 0x0; unless base is [EBP]
381 if ( (displace == 0) && (base != EBP_enc) ) {
382 emit_rm(cbuf, 0x0, reg_encoding, base);
383 }
384 else { // If 8-bit displacement, mode 0x1
385 if ((displace >= -128) && (displace <= 127)
386 && (disp_reloc == relocInfo::none) ) {
387 emit_rm(cbuf, 0x1, reg_encoding, base);
388 emit_d8(cbuf, displace);
389 }
390 else { // If 32-bit displacement
391 if (base == -1) { // Special flag for absolute address
392 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
393 // (manual lies; no SIB needed here)
394 if ( disp_reloc != relocInfo::none ) {
395 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
396 } else {
397 emit_d32 (cbuf, displace);
398 }
399 }
400 else { // Normal base + offset
401 emit_rm(cbuf, 0x2, reg_encoding, base);
402 if ( disp_reloc != relocInfo::none ) {
403 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
404 } else {
405 emit_d32 (cbuf, displace);
406 }
407 }
408 }
409 }
410 }
411 else { // Else, encode with the SIB byte
412 // If no displacement, mode is 0x0; unless base is [EBP]
413 if (displace == 0 && (base != EBP_enc)) { // If no displacement
414 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 }
417 else { // If 8-bit displacement, mode 0x1
418 if ((displace >= -128) && (displace <= 127)
419 && (disp_reloc == relocInfo::none) ) {
420 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, base);
422 emit_d8(cbuf, displace);
423 }
424 else { // If 32-bit displacement
425 if (base == 0x04 ) {
426 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
427 emit_rm(cbuf, scale, index, 0x04);
428 } else {
429 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
430 emit_rm(cbuf, scale, index, base);
431 }
432 if ( disp_reloc != relocInfo::none ) {
433 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
444 if( dst_encoding == src_encoding ) {
445 // reg-reg copy, use an empty encoding
446 } else {
447 emit_opcode( cbuf, 0x8B );
448 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
449 }
450 }
452 void emit_cmpfp_fixup(MacroAssembler& _masm) {
453 Label exit;
454 __ jccb(Assembler::noParity, exit);
455 __ pushf();
456 //
457 // comiss/ucomiss instructions set ZF,PF,CF flags and
458 // zero OF,AF,SF for NaN values.
459 // Fixup flags by zeroing ZF,PF so that compare of NaN
460 // values returns 'less than' result (CF is set).
461 // Leave the rest of flags unchanged.
462 //
463 // 7 6 5 4 3 2 1 0
464 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
465 // 0 0 1 0 1 0 1 1 (0x2B)
466 //
467 __ andl(Address(rsp, 0), 0xffffff2b);
468 __ popf();
469 __ bind(exit);
470 }
472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
473 Label done;
474 __ movl(dst, -1);
475 __ jcc(Assembler::parity, done);
476 __ jcc(Assembler::below, done);
477 __ setb(Assembler::notEqual, dst);
478 __ movzbl(dst, dst);
479 __ bind(done);
480 }
483 //=============================================================================
484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
486 int Compile::ConstantTable::calculate_table_base_offset() const {
487 return 0; // absolute addressing, no offset
488 }
490 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
491 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
492 ShouldNotReachHere();
493 }
495 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
496 // Empty encoding
497 }
499 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
500 return 0;
501 }
503 #ifndef PRODUCT
504 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
505 st->print("# MachConstantBaseNode (empty encoding)");
506 }
507 #endif
510 //=============================================================================
511 #ifndef PRODUCT
512 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
513 Compile* C = ra_->C;
515 int framesize = C->frame_slots() << LogBytesPerInt;
516 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
517 // Remove wordSize for return addr which is already pushed.
518 framesize -= wordSize;
520 if (C->need_stack_bang(framesize)) {
521 framesize -= wordSize;
522 st->print("# stack bang");
523 st->print("\n\t");
524 st->print("PUSH EBP\t# Save EBP");
525 if (framesize) {
526 st->print("\n\t");
527 st->print("SUB ESP, #%d\t# Create frame",framesize);
528 }
529 } else {
530 st->print("SUB ESP, #%d\t# Create frame",framesize);
531 st->print("\n\t");
532 framesize -= wordSize;
533 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
534 }
536 if (VerifyStackAtCalls) {
537 st->print("\n\t");
538 framesize -= wordSize;
539 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
540 }
542 if( C->in_24_bit_fp_mode() ) {
543 st->print("\n\t");
544 st->print("FLDCW \t# load 24 bit fpu control word");
545 }
546 if (UseSSE >= 2 && VerifyFPU) {
547 st->print("\n\t");
548 st->print("# verify FPU stack (must be clean on entry)");
549 }
551 #ifdef ASSERT
552 if (VerifyStackAtCalls) {
553 st->print("\n\t");
554 st->print("# stack alignment check");
555 }
556 #endif
557 st->cr();
558 }
559 #endif
562 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
563 Compile* C = ra_->C;
564 MacroAssembler _masm(&cbuf);
566 int framesize = C->frame_slots() << LogBytesPerInt;
568 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
570 C->set_frame_complete(cbuf.insts_size());
572 if (C->has_mach_constant_base_node()) {
573 // NOTE: We set the table base offset here because users might be
574 // emitted before MachConstantBaseNode.
575 Compile::ConstantTable& constant_table = C->constant_table();
576 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
577 }
578 }
580 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
581 return MachNode::size(ra_); // too many variables; just compute it the hard way
582 }
584 int MachPrologNode::reloc() const {
585 return 0; // a large enough number
586 }
588 //=============================================================================
589 #ifndef PRODUCT
590 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
591 Compile *C = ra_->C;
592 int framesize = C->frame_slots() << LogBytesPerInt;
593 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
594 // Remove two words for return addr and rbp,
595 framesize -= 2*wordSize;
597 if (C->max_vector_size() > 16) {
598 st->print("VZEROUPPER");
599 st->cr(); st->print("\t");
600 }
601 if (C->in_24_bit_fp_mode()) {
602 st->print("FLDCW standard control word");
603 st->cr(); st->print("\t");
604 }
605 if (framesize) {
606 st->print("ADD ESP,%d\t# Destroy frame",framesize);
607 st->cr(); st->print("\t");
608 }
609 st->print_cr("POPL EBP"); st->print("\t");
610 if (do_polling() && C->is_method_compilation()) {
611 st->print("TEST PollPage,EAX\t! Poll Safepoint");
612 st->cr(); st->print("\t");
613 }
614 }
615 #endif
617 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
618 Compile *C = ra_->C;
620 if (C->max_vector_size() > 16) {
621 // Clear upper bits of YMM registers when current compiled code uses
622 // wide vectors to avoid AVX <-> SSE transition penalty during call.
623 MacroAssembler masm(&cbuf);
624 masm.vzeroupper();
625 }
626 // If method set FPU control word, restore to standard control word
627 if (C->in_24_bit_fp_mode()) {
628 MacroAssembler masm(&cbuf);
629 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
630 }
632 int framesize = C->frame_slots() << LogBytesPerInt;
633 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
634 // Remove two words for return addr and rbp,
635 framesize -= 2*wordSize;
637 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
639 if (framesize >= 128) {
640 emit_opcode(cbuf, 0x81); // add SP, #framesize
641 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
642 emit_d32(cbuf, framesize);
643 } else if (framesize) {
644 emit_opcode(cbuf, 0x83); // add SP, #framesize
645 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
646 emit_d8(cbuf, framesize);
647 }
649 emit_opcode(cbuf, 0x58 | EBP_enc);
651 if (do_polling() && C->is_method_compilation()) {
652 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
653 emit_opcode(cbuf,0x85);
654 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
655 emit_d32(cbuf, (intptr_t)os::get_polling_page());
656 }
657 }
659 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
660 Compile *C = ra_->C;
661 // If method set FPU control word, restore to standard control word
662 int size = C->in_24_bit_fp_mode() ? 6 : 0;
663 if (C->max_vector_size() > 16) size += 3; // vzeroupper
664 if (do_polling() && C->is_method_compilation()) size += 6;
666 int framesize = C->frame_slots() << LogBytesPerInt;
667 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
668 // Remove two words for return addr and rbp,
669 framesize -= 2*wordSize;
671 size++; // popl rbp,
673 if (framesize >= 128) {
674 size += 6;
675 } else {
676 size += framesize ? 3 : 0;
677 }
678 return size;
679 }
681 int MachEpilogNode::reloc() const {
682 return 0; // a large enough number
683 }
685 const Pipeline * MachEpilogNode::pipeline() const {
686 return MachNode::pipeline_class();
687 }
689 int MachEpilogNode::safepoint_offset() const { return 0; }
691 //=============================================================================
693 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
694 static enum RC rc_class( OptoReg::Name reg ) {
696 if( !OptoReg::is_valid(reg) ) return rc_bad;
697 if (OptoReg::is_stack(reg)) return rc_stack;
699 VMReg r = OptoReg::as_VMReg(reg);
700 if (r->is_Register()) return rc_int;
701 if (r->is_FloatRegister()) {
702 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
703 return rc_float;
704 }
705 assert(r->is_XMMRegister(), "must be");
706 return rc_xmm;
707 }
709 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
710 int opcode, const char *op_str, int size, outputStream* st ) {
711 if( cbuf ) {
712 emit_opcode (*cbuf, opcode );
713 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
714 #ifndef PRODUCT
715 } else if( !do_size ) {
716 if( size != 0 ) st->print("\n\t");
717 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
718 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
719 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
720 } else { // FLD, FST, PUSH, POP
721 st->print("%s [ESP + #%d]",op_str,offset);
722 }
723 #endif
724 }
725 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
726 return size+3+offset_size;
727 }
729 // Helper for XMM registers. Extra opcode bits, limited syntax.
730 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
731 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
732 if (cbuf) {
733 MacroAssembler _masm(cbuf);
734 if (reg_lo+1 == reg_hi) { // double move?
735 if (is_load) {
736 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
737 } else {
738 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
739 }
740 } else {
741 if (is_load) {
742 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
743 } else {
744 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
745 }
746 }
747 #ifndef PRODUCT
748 } else if (!do_size) {
749 if (size != 0) st->print("\n\t");
750 if (reg_lo+1 == reg_hi) { // double move?
751 if (is_load) st->print("%s %s,[ESP + #%d]",
752 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
753 Matcher::regName[reg_lo], offset);
754 else st->print("MOVSD [ESP + #%d],%s",
755 offset, Matcher::regName[reg_lo]);
756 } else {
757 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
758 Matcher::regName[reg_lo], offset);
759 else st->print("MOVSS [ESP + #%d],%s",
760 offset, Matcher::regName[reg_lo]);
761 }
762 #endif
763 }
764 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
765 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
766 return size+5+offset_size;
767 }
770 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
771 int src_hi, int dst_hi, int size, outputStream* st ) {
772 if (cbuf) {
773 MacroAssembler _masm(cbuf);
774 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
775 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
776 as_XMMRegister(Matcher::_regEncode[src_lo]));
777 } else {
778 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
779 as_XMMRegister(Matcher::_regEncode[src_lo]));
780 }
781 #ifndef PRODUCT
782 } else if (!do_size) {
783 if (size != 0) st->print("\n\t");
784 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
785 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
786 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
787 } else {
788 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
789 }
790 } else {
791 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
792 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
793 } else {
794 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
795 }
796 }
797 #endif
798 }
799 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
800 // Only MOVAPS SSE prefix uses 1 byte.
801 int sz = 4;
802 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
803 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
804 return size + sz;
805 }
807 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
808 int src_hi, int dst_hi, int size, outputStream* st ) {
809 // 32-bit
810 if (cbuf) {
811 MacroAssembler _masm(cbuf);
812 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
813 as_Register(Matcher::_regEncode[src_lo]));
814 #ifndef PRODUCT
815 } else if (!do_size) {
816 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
817 #endif
818 }
819 return 4;
820 }
823 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
824 int src_hi, int dst_hi, int size, outputStream* st ) {
825 // 32-bit
826 if (cbuf) {
827 MacroAssembler _masm(cbuf);
828 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
829 as_XMMRegister(Matcher::_regEncode[src_lo]));
830 #ifndef PRODUCT
831 } else if (!do_size) {
832 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
833 #endif
834 }
835 return 4;
836 }
838 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
839 if( cbuf ) {
840 emit_opcode(*cbuf, 0x8B );
841 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
842 #ifndef PRODUCT
843 } else if( !do_size ) {
844 if( size != 0 ) st->print("\n\t");
845 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
846 #endif
847 }
848 return size+2;
849 }
851 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
852 int offset, int size, outputStream* st ) {
853 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
854 if( cbuf ) {
855 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
856 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
857 #ifndef PRODUCT
858 } else if( !do_size ) {
859 if( size != 0 ) st->print("\n\t");
860 st->print("FLD %s",Matcher::regName[src_lo]);
861 #endif
862 }
863 size += 2;
864 }
866 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
867 const char *op_str;
868 int op;
869 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
870 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
871 op = 0xDD;
872 } else { // 32-bit store
873 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
874 op = 0xD9;
875 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
876 }
878 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
879 }
881 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
882 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
883 int src_hi, int dst_hi, uint ireg, outputStream* st);
885 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
886 int stack_offset, int reg, uint ireg, outputStream* st);
888 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
889 int dst_offset, uint ireg, outputStream* st) {
890 int calc_size = 0;
891 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
892 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
893 switch (ireg) {
894 case Op_VecS:
895 calc_size = 3+src_offset_size + 3+dst_offset_size;
896 break;
897 case Op_VecD:
898 calc_size = 3+src_offset_size + 3+dst_offset_size;
899 src_offset += 4;
900 dst_offset += 4;
901 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
902 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
903 calc_size += 3+src_offset_size + 3+dst_offset_size;
904 break;
905 case Op_VecX:
906 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
907 break;
908 case Op_VecY:
909 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
910 break;
911 default:
912 ShouldNotReachHere();
913 }
914 if (cbuf) {
915 MacroAssembler _masm(cbuf);
916 int offset = __ offset();
917 switch (ireg) {
918 case Op_VecS:
919 __ pushl(Address(rsp, src_offset));
920 __ popl (Address(rsp, dst_offset));
921 break;
922 case Op_VecD:
923 __ pushl(Address(rsp, src_offset));
924 __ popl (Address(rsp, dst_offset));
925 __ pushl(Address(rsp, src_offset+4));
926 __ popl (Address(rsp, dst_offset+4));
927 break;
928 case Op_VecX:
929 __ movdqu(Address(rsp, -16), xmm0);
930 __ movdqu(xmm0, Address(rsp, src_offset));
931 __ movdqu(Address(rsp, dst_offset), xmm0);
932 __ movdqu(xmm0, Address(rsp, -16));
933 break;
934 case Op_VecY:
935 __ vmovdqu(Address(rsp, -32), xmm0);
936 __ vmovdqu(xmm0, Address(rsp, src_offset));
937 __ vmovdqu(Address(rsp, dst_offset), xmm0);
938 __ vmovdqu(xmm0, Address(rsp, -32));
939 break;
940 default:
941 ShouldNotReachHere();
942 }
943 int size = __ offset() - offset;
944 assert(size == calc_size, "incorrect size calculattion");
945 return size;
946 #ifndef PRODUCT
947 } else if (!do_size) {
948 switch (ireg) {
949 case Op_VecS:
950 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
951 "popl [rsp + #%d]",
952 src_offset, dst_offset);
953 break;
954 case Op_VecD:
955 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
956 "popq [rsp + #%d]\n\t"
957 "pushl [rsp + #%d]\n\t"
958 "popq [rsp + #%d]",
959 src_offset, dst_offset, src_offset+4, dst_offset+4);
960 break;
961 case Op_VecX:
962 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
963 "movdqu xmm0, [rsp + #%d]\n\t"
964 "movdqu [rsp + #%d], xmm0\n\t"
965 "movdqu xmm0, [rsp - #16]",
966 src_offset, dst_offset);
967 break;
968 case Op_VecY:
969 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
970 "vmovdqu xmm0, [rsp + #%d]\n\t"
971 "vmovdqu [rsp + #%d], xmm0\n\t"
972 "vmovdqu xmm0, [rsp - #32]",
973 src_offset, dst_offset);
974 break;
975 default:
976 ShouldNotReachHere();
977 }
978 #endif
979 }
980 return calc_size;
981 }
983 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
984 // Get registers to move
985 OptoReg::Name src_second = ra_->get_reg_second(in(1));
986 OptoReg::Name src_first = ra_->get_reg_first(in(1));
987 OptoReg::Name dst_second = ra_->get_reg_second(this );
988 OptoReg::Name dst_first = ra_->get_reg_first(this );
990 enum RC src_second_rc = rc_class(src_second);
991 enum RC src_first_rc = rc_class(src_first);
992 enum RC dst_second_rc = rc_class(dst_second);
993 enum RC dst_first_rc = rc_class(dst_first);
995 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
997 // Generate spill code!
998 int size = 0;
1000 if( src_first == dst_first && src_second == dst_second )
1001 return size; // Self copy, no move
1003 if (bottom_type()->isa_vect() != NULL) {
1004 uint ireg = ideal_reg();
1005 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1006 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
1007 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1008 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1009 // mem -> mem
1010 int src_offset = ra_->reg2offset(src_first);
1011 int dst_offset = ra_->reg2offset(dst_first);
1012 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
1013 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1014 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
1015 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1016 int stack_offset = ra_->reg2offset(dst_first);
1017 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
1018 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
1019 int stack_offset = ra_->reg2offset(src_first);
1020 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1021 } else {
1022 ShouldNotReachHere();
1023 }
1024 }
1026 // --------------------------------------
1027 // Check for mem-mem move. push/pop to move.
1028 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1029 if( src_second == dst_first ) { // overlapping stack copy ranges
1030 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1031 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1032 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1033 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1034 }
1035 // move low bits
1036 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1037 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1038 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1039 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1040 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1041 }
1042 return size;
1043 }
1045 // --------------------------------------
1046 // Check for integer reg-reg copy
1047 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1048 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1050 // Check for integer store
1051 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1052 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1054 // Check for integer load
1055 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1056 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1058 // Check for integer reg-xmm reg copy
1059 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1060 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1061 "no 64 bit integer-float reg moves" );
1062 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1063 }
1064 // --------------------------------------
1065 // Check for float reg-reg copy
1066 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1067 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1068 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1069 if( cbuf ) {
1071 // Note the mucking with the register encode to compensate for the 0/1
1072 // indexing issue mentioned in a comment in the reg_def sections
1073 // for FPR registers many lines above here.
1075 if( src_first != FPR1L_num ) {
1076 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1077 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1078 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1079 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1080 } else {
1081 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1082 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1083 }
1084 #ifndef PRODUCT
1085 } else if( !do_size ) {
1086 if( size != 0 ) st->print("\n\t");
1087 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1088 else st->print( "FST %s", Matcher::regName[dst_first]);
1089 #endif
1090 }
1091 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1092 }
1094 // Check for float store
1095 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1096 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1097 }
1099 // Check for float load
1100 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1101 int offset = ra_->reg2offset(src_first);
1102 const char *op_str;
1103 int op;
1104 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1105 op_str = "FLD_D";
1106 op = 0xDD;
1107 } else { // 32-bit load
1108 op_str = "FLD_S";
1109 op = 0xD9;
1110 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1111 }
1112 if( cbuf ) {
1113 emit_opcode (*cbuf, op );
1114 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1115 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1116 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1117 #ifndef PRODUCT
1118 } else if( !do_size ) {
1119 if( size != 0 ) st->print("\n\t");
1120 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1121 #endif
1122 }
1123 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1124 return size + 3+offset_size+2;
1125 }
1127 // Check for xmm reg-reg copy
1128 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1129 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1130 (src_first+1 == src_second && dst_first+1 == dst_second),
1131 "no non-adjacent float-moves" );
1132 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1133 }
1135 // Check for xmm reg-integer reg copy
1136 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1137 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1138 "no 64 bit float-integer reg moves" );
1139 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1140 }
1142 // Check for xmm store
1143 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1144 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1145 }
1147 // Check for float xmm load
1148 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1149 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1150 }
1152 // Copy from float reg to xmm reg
1153 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1154 // copy to the top of stack from floating point reg
1155 // and use LEA to preserve flags
1156 if( cbuf ) {
1157 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1158 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1159 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1160 emit_d8(*cbuf,0xF8);
1161 #ifndef PRODUCT
1162 } else if( !do_size ) {
1163 if( size != 0 ) st->print("\n\t");
1164 st->print("LEA ESP,[ESP-8]");
1165 #endif
1166 }
1167 size += 4;
1169 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1171 // Copy from the temp memory to the xmm reg.
1172 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1174 if( cbuf ) {
1175 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1176 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1177 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1178 emit_d8(*cbuf,0x08);
1179 #ifndef PRODUCT
1180 } else if( !do_size ) {
1181 if( size != 0 ) st->print("\n\t");
1182 st->print("LEA ESP,[ESP+8]");
1183 #endif
1184 }
1185 size += 4;
1186 return size;
1187 }
1189 assert( size > 0, "missed a case" );
1191 // --------------------------------------------------------------------
1192 // Check for second bits still needing moving.
1193 if( src_second == dst_second )
1194 return size; // Self copy; no move
1195 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1197 // Check for second word int-int move
1198 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1199 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1201 // Check for second word integer store
1202 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1203 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1205 // Check for second word integer load
1206 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1207 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1210 Unimplemented();
1211 }
1213 #ifndef PRODUCT
1214 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1215 implementation( NULL, ra_, false, st );
1216 }
1217 #endif
1219 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1220 implementation( &cbuf, ra_, false, NULL );
1221 }
1223 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1224 return implementation( NULL, ra_, true, NULL );
1225 }
1228 //=============================================================================
1229 #ifndef PRODUCT
1230 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1231 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1232 int reg = ra_->get_reg_first(this);
1233 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1234 }
1235 #endif
1237 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1238 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1239 int reg = ra_->get_encode(this);
1240 if( offset >= 128 ) {
1241 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1242 emit_rm(cbuf, 0x2, reg, 0x04);
1243 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1244 emit_d32(cbuf, offset);
1245 }
1246 else {
1247 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1248 emit_rm(cbuf, 0x1, reg, 0x04);
1249 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1250 emit_d8(cbuf, offset);
1251 }
1252 }
1254 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1255 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1256 if( offset >= 128 ) {
1257 return 7;
1258 }
1259 else {
1260 return 4;
1261 }
1262 }
1264 //=============================================================================
1265 #ifndef PRODUCT
1266 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1267 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1268 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1269 st->print_cr("\tNOP");
1270 st->print_cr("\tNOP");
1271 if( !OptoBreakpoint )
1272 st->print_cr("\tNOP");
1273 }
1274 #endif
1276 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1277 MacroAssembler masm(&cbuf);
1278 #ifdef ASSERT
1279 uint insts_size = cbuf.insts_size();
1280 #endif
1281 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1282 masm.jump_cc(Assembler::notEqual,
1283 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1284 /* WARNING these NOPs are critical so that verified entry point is properly
1285 aligned for patching by NativeJump::patch_verified_entry() */
1286 int nops_cnt = 2;
1287 if( !OptoBreakpoint ) // Leave space for int3
1288 nops_cnt += 1;
1289 masm.nop(nops_cnt);
1291 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1292 }
1294 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1295 return OptoBreakpoint ? 11 : 12;
1296 }
1299 //=============================================================================
1300 uint size_exception_handler() {
1301 // NativeCall instruction size is the same as NativeJump.
1302 // exception handler starts out as jump and can be patched to
1303 // a call be deoptimization. (4932387)
1304 // Note that this value is also credited (in output.cpp) to
1305 // the size of the code section.
1306 return NativeJump::instruction_size;
1307 }
1309 // Emit exception handler code. Stuff framesize into a register
1310 // and call a VM stub routine.
1311 int emit_exception_handler(CodeBuffer& cbuf) {
1313 // Note that the code buffer's insts_mark is always relative to insts.
1314 // That's why we must use the macroassembler to generate a handler.
1315 MacroAssembler _masm(&cbuf);
1316 address base =
1317 __ start_a_stub(size_exception_handler());
1318 if (base == NULL) return 0; // CodeBuffer::expand failed
1319 int offset = __ offset();
1320 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1321 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1322 __ end_a_stub();
1323 return offset;
1324 }
1326 uint size_deopt_handler() {
1327 // NativeCall instruction size is the same as NativeJump.
1328 // exception handler starts out as jump and can be patched to
1329 // a call be deoptimization. (4932387)
1330 // Note that this value is also credited (in output.cpp) to
1331 // the size of the code section.
1332 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1333 }
1335 // Emit deopt handler code.
1336 int emit_deopt_handler(CodeBuffer& cbuf) {
1338 // Note that the code buffer's insts_mark is always relative to insts.
1339 // That's why we must use the macroassembler to generate a handler.
1340 MacroAssembler _masm(&cbuf);
1341 address base =
1342 __ start_a_stub(size_exception_handler());
1343 if (base == NULL) return 0; // CodeBuffer::expand failed
1344 int offset = __ offset();
1345 InternalAddress here(__ pc());
1346 __ pushptr(here.addr());
1348 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1349 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1350 __ end_a_stub();
1351 return offset;
1352 }
1354 int Matcher::regnum_to_fpu_offset(int regnum) {
1355 return regnum - 32; // The FP registers are in the second chunk
1356 }
1358 // This is UltraSparc specific, true just means we have fast l2f conversion
1359 const bool Matcher::convL2FSupported(void) {
1360 return true;
1361 }
1363 // Is this branch offset short enough that a short branch can be used?
1364 //
1365 // NOTE: If the platform does not provide any short branch variants, then
1366 // this method should return false for offset 0.
1367 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1368 // The passed offset is relative to address of the branch.
1369 // On 86 a branch displacement is calculated relative to address
1370 // of a next instruction.
1371 offset -= br_size;
1373 // the short version of jmpConUCF2 contains multiple branches,
1374 // making the reach slightly less
1375 if (rule == jmpConUCF2_rule)
1376 return (-126 <= offset && offset <= 125);
1377 return (-128 <= offset && offset <= 127);
1378 }
1380 const bool Matcher::isSimpleConstant64(jlong value) {
1381 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1382 return false;
1383 }
1385 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1386 const bool Matcher::init_array_count_is_in_bytes = false;
1388 // Threshold size for cleararray.
1389 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1391 // Needs 2 CMOV's for longs.
1392 const int Matcher::long_cmove_cost() { return 1; }
1394 // No CMOVF/CMOVD with SSE/SSE2
1395 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1397 // Does the CPU require late expand (see block.cpp for description of late expand)?
1398 const bool Matcher::require_postalloc_expand = false;
1400 // Should the Matcher clone shifts on addressing modes, expecting them to
1401 // be subsumed into complex addressing expressions or compute them into
1402 // registers? True for Intel but false for most RISCs
1403 const bool Matcher::clone_shift_expressions = true;
1405 // Do we need to mask the count passed to shift instructions or does
1406 // the cpu only look at the lower 5/6 bits anyway?
1407 const bool Matcher::need_masked_shift_count = false;
1409 bool Matcher::narrow_oop_use_complex_address() {
1410 ShouldNotCallThis();
1411 return true;
1412 }
1414 bool Matcher::narrow_klass_use_complex_address() {
1415 ShouldNotCallThis();
1416 return true;
1417 }
1420 // Is it better to copy float constants, or load them directly from memory?
1421 // Intel can load a float constant from a direct address, requiring no
1422 // extra registers. Most RISCs will have to materialize an address into a
1423 // register first, so they would do better to copy the constant from stack.
1424 const bool Matcher::rematerialize_float_constants = true;
1426 // If CPU can load and store mis-aligned doubles directly then no fixup is
1427 // needed. Else we split the double into 2 integer pieces and move it
1428 // piece-by-piece. Only happens when passing doubles into C code as the
1429 // Java calling convention forces doubles to be aligned.
1430 const bool Matcher::misaligned_doubles_ok = true;
1433 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1434 // Get the memory operand from the node
1435 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1436 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1437 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1438 uint opcnt = 1; // First operand
1439 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1440 while( idx >= skipped+num_edges ) {
1441 skipped += num_edges;
1442 opcnt++; // Bump operand count
1443 assert( opcnt < numopnds, "Accessing non-existent operand" );
1444 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1445 }
1447 MachOper *memory = node->_opnds[opcnt];
1448 MachOper *new_memory = NULL;
1449 switch (memory->opcode()) {
1450 case DIRECT:
1451 case INDOFFSET32X:
1452 // No transformation necessary.
1453 return;
1454 case INDIRECT:
1455 new_memory = new (C) indirect_win95_safeOper( );
1456 break;
1457 case INDOFFSET8:
1458 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1459 break;
1460 case INDOFFSET32:
1461 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1462 break;
1463 case INDINDEXOFFSET:
1464 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1465 break;
1466 case INDINDEXSCALE:
1467 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1468 break;
1469 case INDINDEXSCALEOFFSET:
1470 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1471 break;
1472 case LOAD_LONG_INDIRECT:
1473 case LOAD_LONG_INDOFFSET32:
1474 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1475 return;
1476 default:
1477 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1478 return;
1479 }
1480 node->_opnds[opcnt] = new_memory;
1481 }
1483 // Advertise here if the CPU requires explicit rounding operations
1484 // to implement the UseStrictFP mode.
1485 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1487 // Are floats conerted to double when stored to stack during deoptimization?
1488 // On x32 it is stored with convertion only when FPU is used for floats.
1489 bool Matcher::float_in_double() { return (UseSSE == 0); }
1491 // Do ints take an entire long register or just half?
1492 const bool Matcher::int_in_long = false;
1494 // Return whether or not this register is ever used as an argument. This
1495 // function is used on startup to build the trampoline stubs in generateOptoStub.
1496 // Registers not mentioned will be killed by the VM call in the trampoline, and
1497 // arguments in those registers not be available to the callee.
1498 bool Matcher::can_be_java_arg( int reg ) {
1499 if( reg == ECX_num || reg == EDX_num ) return true;
1500 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1501 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1502 return false;
1503 }
1505 bool Matcher::is_spillable_arg( int reg ) {
1506 return can_be_java_arg(reg);
1507 }
1509 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1510 // Use hardware integer DIV instruction when
1511 // it is faster than a code which use multiply.
1512 // Only when constant divisor fits into 32 bit
1513 // (min_jint is excluded to get only correct
1514 // positive 32 bit values from negative).
1515 return VM_Version::has_fast_idiv() &&
1516 (divisor == (int)divisor && divisor != min_jint);
1517 }
1519 // Register for DIVI projection of divmodI
1520 RegMask Matcher::divI_proj_mask() {
1521 return EAX_REG_mask();
1522 }
1524 // Register for MODI projection of divmodI
1525 RegMask Matcher::modI_proj_mask() {
1526 return EDX_REG_mask();
1527 }
1529 // Register for DIVL projection of divmodL
1530 RegMask Matcher::divL_proj_mask() {
1531 ShouldNotReachHere();
1532 return RegMask();
1533 }
1535 // Register for MODL projection of divmodL
1536 RegMask Matcher::modL_proj_mask() {
1537 ShouldNotReachHere();
1538 return RegMask();
1539 }
1541 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1542 return EBP_REG_mask();
1543 }
1545 const RegMask Matcher::mathExactI_result_proj_mask() {
1546 return EAX_REG_mask();
1547 }
1549 const RegMask Matcher::mathExactL_result_proj_mask() {
1550 ShouldNotReachHere();
1551 return RegMask();
1552 }
1554 const RegMask Matcher::mathExactI_flags_proj_mask() {
1555 return INT_FLAGS_mask();
1556 }
1558 // Returns true if the high 32 bits of the value is known to be zero.
1559 bool is_operand_hi32_zero(Node* n) {
1560 int opc = n->Opcode();
1561 if (opc == Op_AndL) {
1562 Node* o2 = n->in(2);
1563 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1564 return true;
1565 }
1566 }
1567 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1568 return true;
1569 }
1570 return false;
1571 }
1573 %}
1575 //----------ENCODING BLOCK-----------------------------------------------------
1576 // This block specifies the encoding classes used by the compiler to output
1577 // byte streams. Encoding classes generate functions which are called by
1578 // Machine Instruction Nodes in order to generate the bit encoding of the
1579 // instruction. Operands specify their base encoding interface with the
1580 // interface keyword. There are currently supported four interfaces,
1581 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1582 // operand to generate a function which returns its register number when
1583 // queried. CONST_INTER causes an operand to generate a function which
1584 // returns the value of the constant when queried. MEMORY_INTER causes an
1585 // operand to generate four functions which return the Base Register, the
1586 // Index Register, the Scale Value, and the Offset Value of the operand when
1587 // queried. COND_INTER causes an operand to generate six functions which
1588 // return the encoding code (ie - encoding bits for the instruction)
1589 // associated with each basic boolean condition for a conditional instruction.
1590 // Instructions specify two basic values for encoding. They use the
1591 // ins_encode keyword to specify their encoding class (which must be one of
1592 // the class names specified in the encoding block), and they use the
1593 // opcode keyword to specify, in order, their primary, secondary, and
1594 // tertiary opcode. Only the opcode sections which a particular instruction
1595 // needs for encoding need to be specified.
1596 encode %{
1597 // Build emit functions for each basic byte or larger field in the intel
1598 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1599 // code in the enc_class source block. Emit functions will live in the
1600 // main source block for now. In future, we can generalize this by
1601 // adding a syntax that specifies the sizes of fields in an order,
1602 // so that the adlc can build the emit functions automagically
1604 // Emit primary opcode
1605 enc_class OpcP %{
1606 emit_opcode(cbuf, $primary);
1607 %}
1609 // Emit secondary opcode
1610 enc_class OpcS %{
1611 emit_opcode(cbuf, $secondary);
1612 %}
1614 // Emit opcode directly
1615 enc_class Opcode(immI d8) %{
1616 emit_opcode(cbuf, $d8$$constant);
1617 %}
1619 enc_class SizePrefix %{
1620 emit_opcode(cbuf,0x66);
1621 %}
1623 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1624 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1625 %}
1627 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1628 emit_opcode(cbuf,$opcode$$constant);
1629 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1630 %}
1632 enc_class mov_r32_imm0( rRegI dst ) %{
1633 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1634 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1635 %}
1637 enc_class cdq_enc %{
1638 // Full implementation of Java idiv and irem; checks for
1639 // special case as described in JVM spec., p.243 & p.271.
1640 //
1641 // normal case special case
1642 //
1643 // input : rax,: dividend min_int
1644 // reg: divisor -1
1645 //
1646 // output: rax,: quotient (= rax, idiv reg) min_int
1647 // rdx: remainder (= rax, irem reg) 0
1648 //
1649 // Code sequnce:
1650 //
1651 // 81 F8 00 00 00 80 cmp rax,80000000h
1652 // 0F 85 0B 00 00 00 jne normal_case
1653 // 33 D2 xor rdx,edx
1654 // 83 F9 FF cmp rcx,0FFh
1655 // 0F 84 03 00 00 00 je done
1656 // normal_case:
1657 // 99 cdq
1658 // F7 F9 idiv rax,ecx
1659 // done:
1660 //
1661 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1662 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1663 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1664 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1665 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1666 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1667 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1668 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1669 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1670 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1671 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1672 // normal_case:
1673 emit_opcode(cbuf,0x99); // cdq
1674 // idiv (note: must be emitted by the user of this rule)
1675 // normal:
1676 %}
1678 // Dense encoding for older common ops
1679 enc_class Opc_plus(immI opcode, rRegI reg) %{
1680 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1681 %}
1684 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1685 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1686 // Check for 8-bit immediate, and set sign extend bit in opcode
1687 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1688 emit_opcode(cbuf, $primary | 0x02);
1689 }
1690 else { // If 32-bit immediate
1691 emit_opcode(cbuf, $primary);
1692 }
1693 %}
1695 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1696 // Emit primary opcode and set sign-extend bit
1697 // Check for 8-bit immediate, and set sign extend bit in opcode
1698 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1699 emit_opcode(cbuf, $primary | 0x02); }
1700 else { // If 32-bit immediate
1701 emit_opcode(cbuf, $primary);
1702 }
1703 // Emit r/m byte with secondary opcode, after primary opcode.
1704 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1705 %}
1707 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1708 // Check for 8-bit immediate, and set sign extend bit in opcode
1709 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1710 $$$emit8$imm$$constant;
1711 }
1712 else { // If 32-bit immediate
1713 // Output immediate
1714 $$$emit32$imm$$constant;
1715 }
1716 %}
1718 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1719 // Emit primary opcode and set sign-extend bit
1720 // Check for 8-bit immediate, and set sign extend bit in opcode
1721 int con = (int)$imm$$constant; // Throw away top bits
1722 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1723 // Emit r/m byte with secondary opcode, after primary opcode.
1724 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1725 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1726 else emit_d32(cbuf,con);
1727 %}
1729 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1730 // Emit primary opcode and set sign-extend bit
1731 // Check for 8-bit immediate, and set sign extend bit in opcode
1732 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1733 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1734 // Emit r/m byte with tertiary opcode, after primary opcode.
1735 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1736 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1737 else emit_d32(cbuf,con);
1738 %}
1740 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1741 emit_cc(cbuf, $secondary, $dst$$reg );
1742 %}
1744 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1745 int destlo = $dst$$reg;
1746 int desthi = HIGH_FROM_LOW(destlo);
1747 // bswap lo
1748 emit_opcode(cbuf, 0x0F);
1749 emit_cc(cbuf, 0xC8, destlo);
1750 // bswap hi
1751 emit_opcode(cbuf, 0x0F);
1752 emit_cc(cbuf, 0xC8, desthi);
1753 // xchg lo and hi
1754 emit_opcode(cbuf, 0x87);
1755 emit_rm(cbuf, 0x3, destlo, desthi);
1756 %}
1758 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1759 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1760 %}
1762 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1763 $$$emit8$primary;
1764 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1765 %}
1767 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1768 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1769 emit_d8(cbuf, op >> 8 );
1770 emit_d8(cbuf, op & 255);
1771 %}
1773 // emulate a CMOV with a conditional branch around a MOV
1774 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1775 // Invert sense of branch from sense of CMOV
1776 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1777 emit_d8( cbuf, $brOffs$$constant );
1778 %}
1780 enc_class enc_PartialSubtypeCheck( ) %{
1781 Register Redi = as_Register(EDI_enc); // result register
1782 Register Reax = as_Register(EAX_enc); // super class
1783 Register Recx = as_Register(ECX_enc); // killed
1784 Register Resi = as_Register(ESI_enc); // sub class
1785 Label miss;
1787 MacroAssembler _masm(&cbuf);
1788 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1789 NULL, &miss,
1790 /*set_cond_codes:*/ true);
1791 if ($primary) {
1792 __ xorptr(Redi, Redi);
1793 }
1794 __ bind(miss);
1795 %}
1797 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1798 MacroAssembler masm(&cbuf);
1799 int start = masm.offset();
1800 if (UseSSE >= 2) {
1801 if (VerifyFPU) {
1802 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1803 }
1804 } else {
1805 // External c_calling_convention expects the FPU stack to be 'clean'.
1806 // Compiled code leaves it dirty. Do cleanup now.
1807 masm.empty_FPU_stack();
1808 }
1809 if (sizeof_FFree_Float_Stack_All == -1) {
1810 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1811 } else {
1812 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1813 }
1814 %}
1816 enc_class Verify_FPU_For_Leaf %{
1817 if( VerifyFPU ) {
1818 MacroAssembler masm(&cbuf);
1819 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1820 }
1821 %}
1823 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1824 // This is the instruction starting address for relocation info.
1825 cbuf.set_insts_mark();
1826 $$$emit8$primary;
1827 // CALL directly to the runtime
1828 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1829 runtime_call_Relocation::spec(), RELOC_IMM32 );
1831 if (UseSSE >= 2) {
1832 MacroAssembler _masm(&cbuf);
1833 BasicType rt = tf()->return_type();
1835 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1836 // A C runtime call where the return value is unused. In SSE2+
1837 // mode the result needs to be removed from the FPU stack. It's
1838 // likely that this function call could be removed by the
1839 // optimizer if the C function is a pure function.
1840 __ ffree(0);
1841 } else if (rt == T_FLOAT) {
1842 __ lea(rsp, Address(rsp, -4));
1843 __ fstp_s(Address(rsp, 0));
1844 __ movflt(xmm0, Address(rsp, 0));
1845 __ lea(rsp, Address(rsp, 4));
1846 } else if (rt == T_DOUBLE) {
1847 __ lea(rsp, Address(rsp, -8));
1848 __ fstp_d(Address(rsp, 0));
1849 __ movdbl(xmm0, Address(rsp, 0));
1850 __ lea(rsp, Address(rsp, 8));
1851 }
1852 }
1853 %}
1856 enc_class pre_call_resets %{
1857 // If method sets FPU control word restore it here
1858 debug_only(int off0 = cbuf.insts_size());
1859 if (ra_->C->in_24_bit_fp_mode()) {
1860 MacroAssembler _masm(&cbuf);
1861 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1862 }
1863 if (ra_->C->max_vector_size() > 16) {
1864 // Clear upper bits of YMM registers when current compiled code uses
1865 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1866 MacroAssembler _masm(&cbuf);
1867 __ vzeroupper();
1868 }
1869 debug_only(int off1 = cbuf.insts_size());
1870 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction");
1871 %}
1873 enc_class post_call_FPU %{
1874 // If method sets FPU control word do it here also
1875 if (Compile::current()->in_24_bit_fp_mode()) {
1876 MacroAssembler masm(&cbuf);
1877 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1878 }
1879 %}
1881 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1882 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1883 // who we intended to call.
1884 cbuf.set_insts_mark();
1885 $$$emit8$primary;
1886 if (!_method) {
1887 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1888 runtime_call_Relocation::spec(), RELOC_IMM32 );
1889 } else if (_optimized_virtual) {
1890 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1891 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1892 } else {
1893 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1894 static_call_Relocation::spec(), RELOC_IMM32 );
1895 }
1896 if (_method) { // Emit stub for static call.
1897 CompiledStaticCall::emit_to_interp_stub(cbuf);
1898 }
1899 %}
1901 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1902 MacroAssembler _masm(&cbuf);
1903 __ ic_call((address)$meth$$method);
1904 %}
1906 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1907 int disp = in_bytes(Method::from_compiled_offset());
1908 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1910 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1911 cbuf.set_insts_mark();
1912 $$$emit8$primary;
1913 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1914 emit_d8(cbuf, disp); // Displacement
1916 %}
1918 // Following encoding is no longer used, but may be restored if calling
1919 // convention changes significantly.
1920 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1921 //
1922 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1923 // // int ic_reg = Matcher::inline_cache_reg();
1924 // // int ic_encode = Matcher::_regEncode[ic_reg];
1925 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1926 // // int imo_encode = Matcher::_regEncode[imo_reg];
1927 //
1928 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1929 // // // so we load it immediately before the call
1930 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1931 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1932 //
1933 // // xor rbp,ebp
1934 // emit_opcode(cbuf, 0x33);
1935 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1936 //
1937 // // CALL to interpreter.
1938 // cbuf.set_insts_mark();
1939 // $$$emit8$primary;
1940 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1941 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1942 // %}
1944 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1945 $$$emit8$primary;
1946 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1947 $$$emit8$shift$$constant;
1948 %}
1950 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1951 // Load immediate does not have a zero or sign extended version
1952 // for 8-bit immediates
1953 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1954 $$$emit32$src$$constant;
1955 %}
1957 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1958 // Load immediate does not have a zero or sign extended version
1959 // for 8-bit immediates
1960 emit_opcode(cbuf, $primary + $dst$$reg);
1961 $$$emit32$src$$constant;
1962 %}
1964 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1965 // Load immediate does not have a zero or sign extended version
1966 // for 8-bit immediates
1967 int dst_enc = $dst$$reg;
1968 int src_con = $src$$constant & 0x0FFFFFFFFL;
1969 if (src_con == 0) {
1970 // xor dst, dst
1971 emit_opcode(cbuf, 0x33);
1972 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1973 } else {
1974 emit_opcode(cbuf, $primary + dst_enc);
1975 emit_d32(cbuf, src_con);
1976 }
1977 %}
1979 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1980 // Load immediate does not have a zero or sign extended version
1981 // for 8-bit immediates
1982 int dst_enc = $dst$$reg + 2;
1983 int src_con = ((julong)($src$$constant)) >> 32;
1984 if (src_con == 0) {
1985 // xor dst, dst
1986 emit_opcode(cbuf, 0x33);
1987 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1988 } else {
1989 emit_opcode(cbuf, $primary + dst_enc);
1990 emit_d32(cbuf, src_con);
1991 }
1992 %}
1995 // Encode a reg-reg copy. If it is useless, then empty encoding.
1996 enc_class enc_Copy( rRegI dst, rRegI src ) %{
1997 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1998 %}
2000 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
2001 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2002 %}
2004 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
2005 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2006 %}
2008 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2009 $$$emit8$primary;
2010 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2011 %}
2013 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2014 $$$emit8$secondary;
2015 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2016 %}
2018 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2019 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2020 %}
2022 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2023 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2024 %}
2026 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2027 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2028 %}
2030 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2031 // Output immediate
2032 $$$emit32$src$$constant;
2033 %}
2035 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
2036 // Output Float immediate bits
2037 jfloat jf = $src$$constant;
2038 int jf_as_bits = jint_cast( jf );
2039 emit_d32(cbuf, jf_as_bits);
2040 %}
2042 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
2043 // Output Float immediate bits
2044 jfloat jf = $src$$constant;
2045 int jf_as_bits = jint_cast( jf );
2046 emit_d32(cbuf, jf_as_bits);
2047 %}
2049 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2050 // Output immediate
2051 $$$emit16$src$$constant;
2052 %}
2054 enc_class Con_d32(immI src) %{
2055 emit_d32(cbuf,$src$$constant);
2056 %}
2058 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2059 // Output immediate memory reference
2060 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2061 emit_d32(cbuf, 0x00);
2062 %}
2064 enc_class lock_prefix( ) %{
2065 if( os::is_MP() )
2066 emit_opcode(cbuf,0xF0); // [Lock]
2067 %}
2069 // Cmp-xchg long value.
2070 // Note: we need to swap rbx, and rcx before and after the
2071 // cmpxchg8 instruction because the instruction uses
2072 // rcx as the high order word of the new value to store but
2073 // our register encoding uses rbx,.
2074 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2076 // XCHG rbx,ecx
2077 emit_opcode(cbuf,0x87);
2078 emit_opcode(cbuf,0xD9);
2079 // [Lock]
2080 if( os::is_MP() )
2081 emit_opcode(cbuf,0xF0);
2082 // CMPXCHG8 [Eptr]
2083 emit_opcode(cbuf,0x0F);
2084 emit_opcode(cbuf,0xC7);
2085 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2086 // XCHG rbx,ecx
2087 emit_opcode(cbuf,0x87);
2088 emit_opcode(cbuf,0xD9);
2089 %}
2091 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2092 // [Lock]
2093 if( os::is_MP() )
2094 emit_opcode(cbuf,0xF0);
2096 // CMPXCHG [Eptr]
2097 emit_opcode(cbuf,0x0F);
2098 emit_opcode(cbuf,0xB1);
2099 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2100 %}
2102 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2103 int res_encoding = $res$$reg;
2105 // MOV res,0
2106 emit_opcode( cbuf, 0xB8 + res_encoding);
2107 emit_d32( cbuf, 0 );
2108 // JNE,s fail
2109 emit_opcode(cbuf,0x75);
2110 emit_d8(cbuf, 5 );
2111 // MOV res,1
2112 emit_opcode( cbuf, 0xB8 + res_encoding);
2113 emit_d32( cbuf, 1 );
2114 // fail:
2115 %}
2117 enc_class set_instruction_start( ) %{
2118 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2119 %}
2121 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2122 int reg_encoding = $ereg$$reg;
2123 int base = $mem$$base;
2124 int index = $mem$$index;
2125 int scale = $mem$$scale;
2126 int displace = $mem$$disp;
2127 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2128 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2129 %}
2131 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2132 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2133 int base = $mem$$base;
2134 int index = $mem$$index;
2135 int scale = $mem$$scale;
2136 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2137 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2138 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2139 %}
2141 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2142 int r1, r2;
2143 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2144 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2145 emit_opcode(cbuf,0x0F);
2146 emit_opcode(cbuf,$tertiary);
2147 emit_rm(cbuf, 0x3, r1, r2);
2148 emit_d8(cbuf,$cnt$$constant);
2149 emit_d8(cbuf,$primary);
2150 emit_rm(cbuf, 0x3, $secondary, r1);
2151 emit_d8(cbuf,$cnt$$constant);
2152 %}
2154 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2155 emit_opcode( cbuf, 0x8B ); // Move
2156 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2157 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2158 emit_d8(cbuf,$primary);
2159 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2160 emit_d8(cbuf,$cnt$$constant-32);
2161 }
2162 emit_d8(cbuf,$primary);
2163 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2164 emit_d8(cbuf,31);
2165 %}
2167 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2168 int r1, r2;
2169 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2170 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2172 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2173 emit_rm(cbuf, 0x3, r1, r2);
2174 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2175 emit_opcode(cbuf,$primary);
2176 emit_rm(cbuf, 0x3, $secondary, r1);
2177 emit_d8(cbuf,$cnt$$constant-32);
2178 }
2179 emit_opcode(cbuf,0x33); // XOR r2,r2
2180 emit_rm(cbuf, 0x3, r2, r2);
2181 %}
2183 // Clone of RegMem but accepts an extra parameter to access each
2184 // half of a double in memory; it never needs relocation info.
2185 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2186 emit_opcode(cbuf,$opcode$$constant);
2187 int reg_encoding = $rm_reg$$reg;
2188 int base = $mem$$base;
2189 int index = $mem$$index;
2190 int scale = $mem$$scale;
2191 int displace = $mem$$disp + $disp_for_half$$constant;
2192 relocInfo::relocType disp_reloc = relocInfo::none;
2193 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2194 %}
2196 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2197 //
2198 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2199 // and it never needs relocation information.
2200 // Frequently used to move data between FPU's Stack Top and memory.
2201 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2202 int rm_byte_opcode = $rm_opcode$$constant;
2203 int base = $mem$$base;
2204 int index = $mem$$index;
2205 int scale = $mem$$scale;
2206 int displace = $mem$$disp;
2207 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2208 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2209 %}
2211 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2212 int rm_byte_opcode = $rm_opcode$$constant;
2213 int base = $mem$$base;
2214 int index = $mem$$index;
2215 int scale = $mem$$scale;
2216 int displace = $mem$$disp;
2217 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2218 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2219 %}
2221 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2222 int reg_encoding = $dst$$reg;
2223 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2224 int index = 0x04; // 0x04 indicates no index
2225 int scale = 0x00; // 0x00 indicates no scale
2226 int displace = $src1$$constant; // 0x00 indicates no displacement
2227 relocInfo::relocType disp_reloc = relocInfo::none;
2228 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2229 %}
2231 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2232 // Compare dst,src
2233 emit_opcode(cbuf,0x3B);
2234 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2235 // jmp dst < src around move
2236 emit_opcode(cbuf,0x7C);
2237 emit_d8(cbuf,2);
2238 // move dst,src
2239 emit_opcode(cbuf,0x8B);
2240 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2241 %}
2243 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2244 // Compare dst,src
2245 emit_opcode(cbuf,0x3B);
2246 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2247 // jmp dst > src around move
2248 emit_opcode(cbuf,0x7F);
2249 emit_d8(cbuf,2);
2250 // move dst,src
2251 emit_opcode(cbuf,0x8B);
2252 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2253 %}
2255 enc_class enc_FPR_store(memory mem, regDPR src) %{
2256 // If src is FPR1, we can just FST to store it.
2257 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2258 int reg_encoding = 0x2; // Just store
2259 int base = $mem$$base;
2260 int index = $mem$$index;
2261 int scale = $mem$$scale;
2262 int displace = $mem$$disp;
2263 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2264 if( $src$$reg != FPR1L_enc ) {
2265 reg_encoding = 0x3; // Store & pop
2266 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2267 emit_d8( cbuf, 0xC0-1+$src$$reg );
2268 }
2269 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2270 emit_opcode(cbuf,$primary);
2271 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2272 %}
2274 enc_class neg_reg(rRegI dst) %{
2275 // NEG $dst
2276 emit_opcode(cbuf,0xF7);
2277 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2278 %}
2280 enc_class setLT_reg(eCXRegI dst) %{
2281 // SETLT $dst
2282 emit_opcode(cbuf,0x0F);
2283 emit_opcode(cbuf,0x9C);
2284 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2285 %}
2287 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2288 int tmpReg = $tmp$$reg;
2290 // SUB $p,$q
2291 emit_opcode(cbuf,0x2B);
2292 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2293 // SBB $tmp,$tmp
2294 emit_opcode(cbuf,0x1B);
2295 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2296 // AND $tmp,$y
2297 emit_opcode(cbuf,0x23);
2298 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2299 // ADD $p,$tmp
2300 emit_opcode(cbuf,0x03);
2301 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2302 %}
2304 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2305 // TEST shift,32
2306 emit_opcode(cbuf,0xF7);
2307 emit_rm(cbuf, 0x3, 0, ECX_enc);
2308 emit_d32(cbuf,0x20);
2309 // JEQ,s small
2310 emit_opcode(cbuf, 0x74);
2311 emit_d8(cbuf, 0x04);
2312 // MOV $dst.hi,$dst.lo
2313 emit_opcode( cbuf, 0x8B );
2314 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2315 // CLR $dst.lo
2316 emit_opcode(cbuf, 0x33);
2317 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2318 // small:
2319 // SHLD $dst.hi,$dst.lo,$shift
2320 emit_opcode(cbuf,0x0F);
2321 emit_opcode(cbuf,0xA5);
2322 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2323 // SHL $dst.lo,$shift"
2324 emit_opcode(cbuf,0xD3);
2325 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2326 %}
2328 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2329 // TEST shift,32
2330 emit_opcode(cbuf,0xF7);
2331 emit_rm(cbuf, 0x3, 0, ECX_enc);
2332 emit_d32(cbuf,0x20);
2333 // JEQ,s small
2334 emit_opcode(cbuf, 0x74);
2335 emit_d8(cbuf, 0x04);
2336 // MOV $dst.lo,$dst.hi
2337 emit_opcode( cbuf, 0x8B );
2338 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2339 // CLR $dst.hi
2340 emit_opcode(cbuf, 0x33);
2341 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2342 // small:
2343 // SHRD $dst.lo,$dst.hi,$shift
2344 emit_opcode(cbuf,0x0F);
2345 emit_opcode(cbuf,0xAD);
2346 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2347 // SHR $dst.hi,$shift"
2348 emit_opcode(cbuf,0xD3);
2349 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2350 %}
2352 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2353 // TEST shift,32
2354 emit_opcode(cbuf,0xF7);
2355 emit_rm(cbuf, 0x3, 0, ECX_enc);
2356 emit_d32(cbuf,0x20);
2357 // JEQ,s small
2358 emit_opcode(cbuf, 0x74);
2359 emit_d8(cbuf, 0x05);
2360 // MOV $dst.lo,$dst.hi
2361 emit_opcode( cbuf, 0x8B );
2362 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2363 // SAR $dst.hi,31
2364 emit_opcode(cbuf, 0xC1);
2365 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2366 emit_d8(cbuf, 0x1F );
2367 // small:
2368 // SHRD $dst.lo,$dst.hi,$shift
2369 emit_opcode(cbuf,0x0F);
2370 emit_opcode(cbuf,0xAD);
2371 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2372 // SAR $dst.hi,$shift"
2373 emit_opcode(cbuf,0xD3);
2374 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2375 %}
2378 // ----------------- Encodings for floating point unit -----------------
2379 // May leave result in FPU-TOS or FPU reg depending on opcodes
2380 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2381 $$$emit8$primary;
2382 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2383 %}
2385 // Pop argument in FPR0 with FSTP ST(0)
2386 enc_class PopFPU() %{
2387 emit_opcode( cbuf, 0xDD );
2388 emit_d8( cbuf, 0xD8 );
2389 %}
2391 // !!!!! equivalent to Pop_Reg_F
2392 enc_class Pop_Reg_DPR( regDPR dst ) %{
2393 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2394 emit_d8( cbuf, 0xD8+$dst$$reg );
2395 %}
2397 enc_class Push_Reg_DPR( regDPR dst ) %{
2398 emit_opcode( cbuf, 0xD9 );
2399 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2400 %}
2402 enc_class strictfp_bias1( regDPR dst ) %{
2403 emit_opcode( cbuf, 0xDB ); // FLD m80real
2404 emit_opcode( cbuf, 0x2D );
2405 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2406 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2407 emit_opcode( cbuf, 0xC8+$dst$$reg );
2408 %}
2410 enc_class strictfp_bias2( regDPR dst ) %{
2411 emit_opcode( cbuf, 0xDB ); // FLD m80real
2412 emit_opcode( cbuf, 0x2D );
2413 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2414 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2415 emit_opcode( cbuf, 0xC8+$dst$$reg );
2416 %}
2418 // Special case for moving an integer register to a stack slot.
2419 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2420 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2421 %}
2423 // Special case for moving a register to a stack slot.
2424 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2425 // Opcode already emitted
2426 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2427 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2428 emit_d32(cbuf, $dst$$disp); // Displacement
2429 %}
2431 // Push the integer in stackSlot 'src' onto FP-stack
2432 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2433 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2434 %}
2436 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2437 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2438 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2439 %}
2441 // Same as Pop_Mem_F except for opcode
2442 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2443 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2444 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2445 %}
2447 enc_class Pop_Reg_FPR( regFPR dst ) %{
2448 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2449 emit_d8( cbuf, 0xD8+$dst$$reg );
2450 %}
2452 enc_class Push_Reg_FPR( regFPR dst ) %{
2453 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2454 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2455 %}
2457 // Push FPU's float to a stack-slot, and pop FPU-stack
2458 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2459 int pop = 0x02;
2460 if ($src$$reg != FPR1L_enc) {
2461 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2462 emit_d8( cbuf, 0xC0-1+$src$$reg );
2463 pop = 0x03;
2464 }
2465 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2466 %}
2468 // Push FPU's double to a stack-slot, and pop FPU-stack
2469 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2470 int pop = 0x02;
2471 if ($src$$reg != FPR1L_enc) {
2472 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2473 emit_d8( cbuf, 0xC0-1+$src$$reg );
2474 pop = 0x03;
2475 }
2476 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2477 %}
2479 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2480 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2481 int pop = 0xD0 - 1; // -1 since we skip FLD
2482 if ($src$$reg != FPR1L_enc) {
2483 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2484 emit_d8( cbuf, 0xC0-1+$src$$reg );
2485 pop = 0xD8;
2486 }
2487 emit_opcode( cbuf, 0xDD );
2488 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2489 %}
2492 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2493 // load dst in FPR0
2494 emit_opcode( cbuf, 0xD9 );
2495 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2496 if ($src$$reg != FPR1L_enc) {
2497 // fincstp
2498 emit_opcode (cbuf, 0xD9);
2499 emit_opcode (cbuf, 0xF7);
2500 // swap src with FPR1:
2501 // FXCH FPR1 with src
2502 emit_opcode(cbuf, 0xD9);
2503 emit_d8(cbuf, 0xC8-1+$src$$reg );
2504 // fdecstp
2505 emit_opcode (cbuf, 0xD9);
2506 emit_opcode (cbuf, 0xF6);
2507 }
2508 %}
2510 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2511 MacroAssembler _masm(&cbuf);
2512 __ subptr(rsp, 8);
2513 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2514 __ fld_d(Address(rsp, 0));
2515 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2516 __ fld_d(Address(rsp, 0));
2517 %}
2519 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2520 MacroAssembler _masm(&cbuf);
2521 __ subptr(rsp, 4);
2522 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2523 __ fld_s(Address(rsp, 0));
2524 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2525 __ fld_s(Address(rsp, 0));
2526 %}
2528 enc_class Push_ResultD(regD dst) %{
2529 MacroAssembler _masm(&cbuf);
2530 __ fstp_d(Address(rsp, 0));
2531 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2532 __ addptr(rsp, 8);
2533 %}
2535 enc_class Push_ResultF(regF dst, immI d8) %{
2536 MacroAssembler _masm(&cbuf);
2537 __ fstp_s(Address(rsp, 0));
2538 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2539 __ addptr(rsp, $d8$$constant);
2540 %}
2542 enc_class Push_SrcD(regD src) %{
2543 MacroAssembler _masm(&cbuf);
2544 __ subptr(rsp, 8);
2545 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2546 __ fld_d(Address(rsp, 0));
2547 %}
2549 enc_class push_stack_temp_qword() %{
2550 MacroAssembler _masm(&cbuf);
2551 __ subptr(rsp, 8);
2552 %}
2554 enc_class pop_stack_temp_qword() %{
2555 MacroAssembler _masm(&cbuf);
2556 __ addptr(rsp, 8);
2557 %}
2559 enc_class push_xmm_to_fpr1(regD src) %{
2560 MacroAssembler _masm(&cbuf);
2561 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2562 __ fld_d(Address(rsp, 0));
2563 %}
2565 enc_class Push_Result_Mod_DPR( regDPR src) %{
2566 if ($src$$reg != FPR1L_enc) {
2567 // fincstp
2568 emit_opcode (cbuf, 0xD9);
2569 emit_opcode (cbuf, 0xF7);
2570 // FXCH FPR1 with src
2571 emit_opcode(cbuf, 0xD9);
2572 emit_d8(cbuf, 0xC8-1+$src$$reg );
2573 // fdecstp
2574 emit_opcode (cbuf, 0xD9);
2575 emit_opcode (cbuf, 0xF6);
2576 }
2577 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2578 // // FSTP FPR$dst$$reg
2579 // emit_opcode( cbuf, 0xDD );
2580 // emit_d8( cbuf, 0xD8+$dst$$reg );
2581 %}
2583 enc_class fnstsw_sahf_skip_parity() %{
2584 // fnstsw ax
2585 emit_opcode( cbuf, 0xDF );
2586 emit_opcode( cbuf, 0xE0 );
2587 // sahf
2588 emit_opcode( cbuf, 0x9E );
2589 // jnp ::skip
2590 emit_opcode( cbuf, 0x7B );
2591 emit_opcode( cbuf, 0x05 );
2592 %}
2594 enc_class emitModDPR() %{
2595 // fprem must be iterative
2596 // :: loop
2597 // fprem
2598 emit_opcode( cbuf, 0xD9 );
2599 emit_opcode( cbuf, 0xF8 );
2600 // wait
2601 emit_opcode( cbuf, 0x9b );
2602 // fnstsw ax
2603 emit_opcode( cbuf, 0xDF );
2604 emit_opcode( cbuf, 0xE0 );
2605 // sahf
2606 emit_opcode( cbuf, 0x9E );
2607 // jp ::loop
2608 emit_opcode( cbuf, 0x0F );
2609 emit_opcode( cbuf, 0x8A );
2610 emit_opcode( cbuf, 0xF4 );
2611 emit_opcode( cbuf, 0xFF );
2612 emit_opcode( cbuf, 0xFF );
2613 emit_opcode( cbuf, 0xFF );
2614 %}
2616 enc_class fpu_flags() %{
2617 // fnstsw_ax
2618 emit_opcode( cbuf, 0xDF);
2619 emit_opcode( cbuf, 0xE0);
2620 // test ax,0x0400
2621 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2622 emit_opcode( cbuf, 0xA9 );
2623 emit_d16 ( cbuf, 0x0400 );
2624 // // // This sequence works, but stalls for 12-16 cycles on PPro
2625 // // test rax,0x0400
2626 // emit_opcode( cbuf, 0xA9 );
2627 // emit_d32 ( cbuf, 0x00000400 );
2628 //
2629 // jz exit (no unordered comparison)
2630 emit_opcode( cbuf, 0x74 );
2631 emit_d8 ( cbuf, 0x02 );
2632 // mov ah,1 - treat as LT case (set carry flag)
2633 emit_opcode( cbuf, 0xB4 );
2634 emit_d8 ( cbuf, 0x01 );
2635 // sahf
2636 emit_opcode( cbuf, 0x9E);
2637 %}
2639 enc_class cmpF_P6_fixup() %{
2640 // Fixup the integer flags in case comparison involved a NaN
2641 //
2642 // JNP exit (no unordered comparison, P-flag is set by NaN)
2643 emit_opcode( cbuf, 0x7B );
2644 emit_d8 ( cbuf, 0x03 );
2645 // MOV AH,1 - treat as LT case (set carry flag)
2646 emit_opcode( cbuf, 0xB4 );
2647 emit_d8 ( cbuf, 0x01 );
2648 // SAHF
2649 emit_opcode( cbuf, 0x9E);
2650 // NOP // target for branch to avoid branch to branch
2651 emit_opcode( cbuf, 0x90);
2652 %}
2654 // fnstsw_ax();
2655 // sahf();
2656 // movl(dst, nan_result);
2657 // jcc(Assembler::parity, exit);
2658 // movl(dst, less_result);
2659 // jcc(Assembler::below, exit);
2660 // movl(dst, equal_result);
2661 // jcc(Assembler::equal, exit);
2662 // movl(dst, greater_result);
2664 // less_result = 1;
2665 // greater_result = -1;
2666 // equal_result = 0;
2667 // nan_result = -1;
2669 enc_class CmpF_Result(rRegI dst) %{
2670 // fnstsw_ax();
2671 emit_opcode( cbuf, 0xDF);
2672 emit_opcode( cbuf, 0xE0);
2673 // sahf
2674 emit_opcode( cbuf, 0x9E);
2675 // movl(dst, nan_result);
2676 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2677 emit_d32( cbuf, -1 );
2678 // jcc(Assembler::parity, exit);
2679 emit_opcode( cbuf, 0x7A );
2680 emit_d8 ( cbuf, 0x13 );
2681 // movl(dst, less_result);
2682 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2683 emit_d32( cbuf, -1 );
2684 // jcc(Assembler::below, exit);
2685 emit_opcode( cbuf, 0x72 );
2686 emit_d8 ( cbuf, 0x0C );
2687 // movl(dst, equal_result);
2688 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2689 emit_d32( cbuf, 0 );
2690 // jcc(Assembler::equal, exit);
2691 emit_opcode( cbuf, 0x74 );
2692 emit_d8 ( cbuf, 0x05 );
2693 // movl(dst, greater_result);
2694 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2695 emit_d32( cbuf, 1 );
2696 %}
2699 // Compare the longs and set flags
2700 // BROKEN! Do Not use as-is
2701 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2702 // CMP $src1.hi,$src2.hi
2703 emit_opcode( cbuf, 0x3B );
2704 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2705 // JNE,s done
2706 emit_opcode(cbuf,0x75);
2707 emit_d8(cbuf, 2 );
2708 // CMP $src1.lo,$src2.lo
2709 emit_opcode( cbuf, 0x3B );
2710 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2711 // done:
2712 %}
2714 enc_class convert_int_long( regL dst, rRegI src ) %{
2715 // mov $dst.lo,$src
2716 int dst_encoding = $dst$$reg;
2717 int src_encoding = $src$$reg;
2718 encode_Copy( cbuf, dst_encoding , src_encoding );
2719 // mov $dst.hi,$src
2720 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2721 // sar $dst.hi,31
2722 emit_opcode( cbuf, 0xC1 );
2723 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2724 emit_d8(cbuf, 0x1F );
2725 %}
2727 enc_class convert_long_double( eRegL src ) %{
2728 // push $src.hi
2729 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2730 // push $src.lo
2731 emit_opcode(cbuf, 0x50+$src$$reg );
2732 // fild 64-bits at [SP]
2733 emit_opcode(cbuf,0xdf);
2734 emit_d8(cbuf, 0x6C);
2735 emit_d8(cbuf, 0x24);
2736 emit_d8(cbuf, 0x00);
2737 // pop stack
2738 emit_opcode(cbuf, 0x83); // add SP, #8
2739 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2740 emit_d8(cbuf, 0x8);
2741 %}
2743 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2744 // IMUL EDX:EAX,$src1
2745 emit_opcode( cbuf, 0xF7 );
2746 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2747 // SAR EDX,$cnt-32
2748 int shift_count = ((int)$cnt$$constant) - 32;
2749 if (shift_count > 0) {
2750 emit_opcode(cbuf, 0xC1);
2751 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2752 emit_d8(cbuf, shift_count);
2753 }
2754 %}
2756 // this version doesn't have add sp, 8
2757 enc_class convert_long_double2( eRegL src ) %{
2758 // push $src.hi
2759 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2760 // push $src.lo
2761 emit_opcode(cbuf, 0x50+$src$$reg );
2762 // fild 64-bits at [SP]
2763 emit_opcode(cbuf,0xdf);
2764 emit_d8(cbuf, 0x6C);
2765 emit_d8(cbuf, 0x24);
2766 emit_d8(cbuf, 0x00);
2767 %}
2769 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2770 // Basic idea: long = (long)int * (long)int
2771 // IMUL EDX:EAX, src
2772 emit_opcode( cbuf, 0xF7 );
2773 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2774 %}
2776 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2777 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2778 // MUL EDX:EAX, src
2779 emit_opcode( cbuf, 0xF7 );
2780 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2781 %}
2783 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2784 // Basic idea: lo(result) = lo(x_lo * y_lo)
2785 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2786 // MOV $tmp,$src.lo
2787 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2788 // IMUL $tmp,EDX
2789 emit_opcode( cbuf, 0x0F );
2790 emit_opcode( cbuf, 0xAF );
2791 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2792 // MOV EDX,$src.hi
2793 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2794 // IMUL EDX,EAX
2795 emit_opcode( cbuf, 0x0F );
2796 emit_opcode( cbuf, 0xAF );
2797 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2798 // ADD $tmp,EDX
2799 emit_opcode( cbuf, 0x03 );
2800 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2801 // MUL EDX:EAX,$src.lo
2802 emit_opcode( cbuf, 0xF7 );
2803 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2804 // ADD EDX,ESI
2805 emit_opcode( cbuf, 0x03 );
2806 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2807 %}
2809 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2810 // Basic idea: lo(result) = lo(src * y_lo)
2811 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2812 // IMUL $tmp,EDX,$src
2813 emit_opcode( cbuf, 0x6B );
2814 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2815 emit_d8( cbuf, (int)$src$$constant );
2816 // MOV EDX,$src
2817 emit_opcode(cbuf, 0xB8 + EDX_enc);
2818 emit_d32( cbuf, (int)$src$$constant );
2819 // MUL EDX:EAX,EDX
2820 emit_opcode( cbuf, 0xF7 );
2821 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2822 // ADD EDX,ESI
2823 emit_opcode( cbuf, 0x03 );
2824 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2825 %}
2827 enc_class long_div( eRegL src1, eRegL src2 ) %{
2828 // PUSH src1.hi
2829 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2830 // PUSH src1.lo
2831 emit_opcode(cbuf, 0x50+$src1$$reg );
2832 // PUSH src2.hi
2833 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2834 // PUSH src2.lo
2835 emit_opcode(cbuf, 0x50+$src2$$reg );
2836 // CALL directly to the runtime
2837 cbuf.set_insts_mark();
2838 emit_opcode(cbuf,0xE8); // Call into runtime
2839 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2840 // Restore stack
2841 emit_opcode(cbuf, 0x83); // add SP, #framesize
2842 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2843 emit_d8(cbuf, 4*4);
2844 %}
2846 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2847 // PUSH src1.hi
2848 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2849 // PUSH src1.lo
2850 emit_opcode(cbuf, 0x50+$src1$$reg );
2851 // PUSH src2.hi
2852 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2853 // PUSH src2.lo
2854 emit_opcode(cbuf, 0x50+$src2$$reg );
2855 // CALL directly to the runtime
2856 cbuf.set_insts_mark();
2857 emit_opcode(cbuf,0xE8); // Call into runtime
2858 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2859 // Restore stack
2860 emit_opcode(cbuf, 0x83); // add SP, #framesize
2861 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2862 emit_d8(cbuf, 4*4);
2863 %}
2865 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2866 // MOV $tmp,$src.lo
2867 emit_opcode(cbuf, 0x8B);
2868 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2869 // OR $tmp,$src.hi
2870 emit_opcode(cbuf, 0x0B);
2871 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2872 %}
2874 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2875 // CMP $src1.lo,$src2.lo
2876 emit_opcode( cbuf, 0x3B );
2877 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2878 // JNE,s skip
2879 emit_cc(cbuf, 0x70, 0x5);
2880 emit_d8(cbuf,2);
2881 // CMP $src1.hi,$src2.hi
2882 emit_opcode( cbuf, 0x3B );
2883 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2884 %}
2886 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2887 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2888 emit_opcode( cbuf, 0x3B );
2889 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2890 // MOV $tmp,$src1.hi
2891 emit_opcode( cbuf, 0x8B );
2892 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2893 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2894 emit_opcode( cbuf, 0x1B );
2895 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2896 %}
2898 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2899 // XOR $tmp,$tmp
2900 emit_opcode(cbuf,0x33); // XOR
2901 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2902 // CMP $tmp,$src.lo
2903 emit_opcode( cbuf, 0x3B );
2904 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2905 // SBB $tmp,$src.hi
2906 emit_opcode( cbuf, 0x1B );
2907 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2908 %}
2910 // Sniff, sniff... smells like Gnu Superoptimizer
2911 enc_class neg_long( eRegL dst ) %{
2912 emit_opcode(cbuf,0xF7); // NEG hi
2913 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2914 emit_opcode(cbuf,0xF7); // NEG lo
2915 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2916 emit_opcode(cbuf,0x83); // SBB hi,0
2917 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2918 emit_d8 (cbuf,0 );
2919 %}
2922 // Because the transitions from emitted code to the runtime
2923 // monitorenter/exit helper stubs are so slow it's critical that
2924 // we inline both the stack-locking fast-path and the inflated fast path.
2925 //
2926 // See also: cmpFastLock and cmpFastUnlock.
2927 //
2928 // What follows is a specialized inline transliteration of the code
2929 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2930 // another option would be to emit TrySlowEnter and TrySlowExit methods
2931 // at startup-time. These methods would accept arguments as
2932 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2933 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2934 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2935 // In practice, however, the # of lock sites is bounded and is usually small.
2936 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2937 // if the processor uses simple bimodal branch predictors keyed by EIP
2938 // Since the helper routines would be called from multiple synchronization
2939 // sites.
2940 //
2941 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2942 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2943 // to those specialized methods. That'd give us a mostly platform-independent
2944 // implementation that the JITs could optimize and inline at their pleasure.
2945 // Done correctly, the only time we'd need to cross to native could would be
2946 // to park() or unpark() threads. We'd also need a few more unsafe operators
2947 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2948 // (b) explicit barriers or fence operations.
2949 //
2950 // TODO:
2951 //
2952 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2953 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2954 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2955 // the lock operators would typically be faster than reifying Self.
2956 //
2957 // * Ideally I'd define the primitives as:
2958 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2959 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2960 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
2961 // Instead, we're stuck with a rather awkward and brittle register assignments below.
2962 // Furthermore the register assignments are overconstrained, possibly resulting in
2963 // sub-optimal code near the synchronization site.
2964 //
2965 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
2966 // Alternately, use a better sp-proximity test.
2967 //
2968 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
2969 // Either one is sufficient to uniquely identify a thread.
2970 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
2971 //
2972 // * Intrinsify notify() and notifyAll() for the common cases where the
2973 // object is locked by the calling thread but the waitlist is empty.
2974 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
2975 //
2976 // * use jccb and jmpb instead of jcc and jmp to improve code density.
2977 // But beware of excessive branch density on AMD Opterons.
2978 //
2979 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
2980 // or failure of the fast-path. If the fast-path fails then we pass
2981 // control to the slow-path, typically in C. In Fast_Lock and
2982 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
2983 // will emit a conditional branch immediately after the node.
2984 // So we have branches to branches and lots of ICC.ZF games.
2985 // Instead, it might be better to have C2 pass a "FailureLabel"
2986 // into Fast_Lock and Fast_Unlock. In the case of success, control
2987 // will drop through the node. ICC.ZF is undefined at exit.
2988 // In the case of failure, the node will branch directly to the
2989 // FailureLabel
2992 // obj: object to lock
2993 // box: on-stack box address (displaced header location) - KILLED
2994 // rax,: tmp -- KILLED
2995 // scr: tmp -- KILLED
2996 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
2998 Register objReg = as_Register($obj$$reg);
2999 Register boxReg = as_Register($box$$reg);
3000 Register tmpReg = as_Register($tmp$$reg);
3001 Register scrReg = as_Register($scr$$reg);
3003 // Ensure the register assignents are disjoint
3004 guarantee (objReg != boxReg, "") ;
3005 guarantee (objReg != tmpReg, "") ;
3006 guarantee (objReg != scrReg, "") ;
3007 guarantee (boxReg != tmpReg, "") ;
3008 guarantee (boxReg != scrReg, "") ;
3009 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3011 MacroAssembler masm(&cbuf);
3013 if (_counters != NULL) {
3014 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3015 }
3016 if (EmitSync & 1) {
3017 // set box->dhw = unused_mark (3)
3018 // Force all sync thru slow-path: slow_enter() and slow_exit()
3019 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3020 masm.cmpptr (rsp, (int32_t)0) ;
3021 } else
3022 if (EmitSync & 2) {
3023 Label DONE_LABEL ;
3024 if (UseBiasedLocking) {
3025 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3026 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3027 }
3029 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3030 masm.orptr (tmpReg, 0x1);
3031 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3032 if (os::is_MP()) { masm.lock(); }
3033 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3034 masm.jcc(Assembler::equal, DONE_LABEL);
3035 // Recursive locking
3036 masm.subptr(tmpReg, rsp);
3037 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3038 masm.movptr(Address(boxReg, 0), tmpReg);
3039 masm.bind(DONE_LABEL) ;
3040 } else {
3041 // Possible cases that we'll encounter in fast_lock
3042 // ------------------------------------------------
3043 // * Inflated
3044 // -- unlocked
3045 // -- Locked
3046 // = by self
3047 // = by other
3048 // * biased
3049 // -- by Self
3050 // -- by other
3051 // * neutral
3052 // * stack-locked
3053 // -- by self
3054 // = sp-proximity test hits
3055 // = sp-proximity test generates false-negative
3056 // -- by other
3057 //
3059 Label IsInflated, DONE_LABEL, PopDone ;
3061 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3062 // order to reduce the number of conditional branches in the most common cases.
3063 // Beware -- there's a subtle invariant that fetch of the markword
3064 // at [FETCH], below, will never observe a biased encoding (*101b).
3065 // If this invariant is not held we risk exclusion (safety) failure.
3066 if (UseBiasedLocking && !UseOptoBiasInlining) {
3067 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3068 }
3070 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3071 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3072 masm.jccb (Assembler::notZero, IsInflated) ;
3074 // Attempt stack-locking ...
3075 masm.orptr (tmpReg, 0x1);
3076 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3077 if (os::is_MP()) { masm.lock(); }
3078 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3079 if (_counters != NULL) {
3080 masm.cond_inc32(Assembler::equal,
3081 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3082 }
3083 masm.jccb (Assembler::equal, DONE_LABEL);
3085 // Recursive locking
3086 masm.subptr(tmpReg, rsp);
3087 masm.andptr(tmpReg, 0xFFFFF003 );
3088 masm.movptr(Address(boxReg, 0), tmpReg);
3089 if (_counters != NULL) {
3090 masm.cond_inc32(Assembler::equal,
3091 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3092 }
3093 masm.jmp (DONE_LABEL) ;
3095 masm.bind (IsInflated) ;
3097 // The object is inflated.
3098 //
3099 // TODO-FIXME: eliminate the ugly use of manifest constants:
3100 // Use markOopDesc::monitor_value instead of "2".
3101 // use markOop::unused_mark() instead of "3".
3102 // The tmpReg value is an objectMonitor reference ORed with
3103 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3104 // objectmonitor pointer by masking off the "2" bit or we can just
3105 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3106 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3107 //
3108 // I use the latter as it avoids AGI stalls.
3109 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3110 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3111 //
3112 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3114 // boxReg refers to the on-stack BasicLock in the current frame.
3115 // We'd like to write:
3116 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3117 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3118 // additional latency as we have another ST in the store buffer that must drain.
3120 if (EmitSync & 8192) {
3121 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3122 masm.get_thread (scrReg) ;
3123 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3124 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3125 if (os::is_MP()) { masm.lock(); }
3126 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3127 } else
3128 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3129 masm.movptr(scrReg, boxReg) ;
3130 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3132 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3133 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3134 // prefetchw [eax + Offset(_owner)-2]
3135 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3136 }
3138 if ((EmitSync & 64) == 0) {
3139 // Optimistic form: consider XORL tmpReg,tmpReg
3140 masm.movptr(tmpReg, NULL_WORD) ;
3141 } else {
3142 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3143 // Test-And-CAS instead of CAS
3144 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3145 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3146 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3147 }
3149 // Appears unlocked - try to swing _owner from null to non-null.
3150 // Ideally, I'd manifest "Self" with get_thread and then attempt
3151 // to CAS the register containing Self into m->Owner.
3152 // But we don't have enough registers, so instead we can either try to CAS
3153 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3154 // we later store "Self" into m->Owner. Transiently storing a stack address
3155 // (rsp or the address of the box) into m->owner is harmless.
3156 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3157 if (os::is_MP()) { masm.lock(); }
3158 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3159 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3160 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3161 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3162 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3163 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3165 // If the CAS fails we can either retry or pass control to the slow-path.
3166 // We use the latter tactic.
3167 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3168 // If the CAS was successful ...
3169 // Self has acquired the lock
3170 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3171 // Intentional fall-through into DONE_LABEL ...
3172 } else {
3173 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3174 masm.movptr(boxReg, tmpReg) ;
3176 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3177 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3178 // prefetchw [eax + Offset(_owner)-2]
3179 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3180 }
3182 if ((EmitSync & 64) == 0) {
3183 // Optimistic form
3184 masm.xorptr (tmpReg, tmpReg) ;
3185 } else {
3186 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3187 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3188 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3189 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3190 }
3192 // Appears unlocked - try to swing _owner from null to non-null.
3193 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3194 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3195 masm.get_thread (scrReg) ;
3196 if (os::is_MP()) { masm.lock(); }
3197 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3199 // If the CAS fails we can either retry or pass control to the slow-path.
3200 // We use the latter tactic.
3201 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3202 // If the CAS was successful ...
3203 // Self has acquired the lock
3204 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3205 // Intentional fall-through into DONE_LABEL ...
3206 }
3208 // DONE_LABEL is a hot target - we'd really like to place it at the
3209 // start of cache line by padding with NOPs.
3210 // See the AMD and Intel software optimization manuals for the
3211 // most efficient "long" NOP encodings.
3212 // Unfortunately none of our alignment mechanisms suffice.
3213 masm.bind(DONE_LABEL);
3215 // Avoid branch-to-branch on AMD processors
3216 // This appears to be superstition.
3217 if (EmitSync & 32) masm.nop() ;
3220 // At DONE_LABEL the icc ZFlag is set as follows ...
3221 // Fast_Unlock uses the same protocol.
3222 // ZFlag == 1 -> Success
3223 // ZFlag == 0 -> Failure - force control through the slow-path
3224 }
3225 %}
3227 // obj: object to unlock
3228 // box: box address (displaced header location), killed. Must be EAX.
3229 // rbx,: killed tmp; cannot be obj nor box.
3230 //
3231 // Some commentary on balanced locking:
3232 //
3233 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3234 // Methods that don't have provably balanced locking are forced to run in the
3235 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3236 // The interpreter provides two properties:
3237 // I1: At return-time the interpreter automatically and quietly unlocks any
3238 // objects acquired the current activation (frame). Recall that the
3239 // interpreter maintains an on-stack list of locks currently held by
3240 // a frame.
3241 // I2: If a method attempts to unlock an object that is not held by the
3242 // the frame the interpreter throws IMSX.
3243 //
3244 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3245 // B() doesn't have provably balanced locking so it runs in the interpreter.
3246 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3247 // is still locked by A().
3248 //
3249 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3250 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3251 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3252 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3254 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3256 Register objReg = as_Register($obj$$reg);
3257 Register boxReg = as_Register($box$$reg);
3258 Register tmpReg = as_Register($tmp$$reg);
3260 guarantee (objReg != boxReg, "") ;
3261 guarantee (objReg != tmpReg, "") ;
3262 guarantee (boxReg != tmpReg, "") ;
3263 guarantee (boxReg == as_Register(EAX_enc), "") ;
3264 MacroAssembler masm(&cbuf);
3266 if (EmitSync & 4) {
3267 // Disable - inhibit all inlining. Force control through the slow-path
3268 masm.cmpptr (rsp, 0) ;
3269 } else
3270 if (EmitSync & 8) {
3271 Label DONE_LABEL ;
3272 if (UseBiasedLocking) {
3273 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3274 }
3275 // classic stack-locking code ...
3276 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3277 masm.testptr(tmpReg, tmpReg) ;
3278 masm.jcc (Assembler::zero, DONE_LABEL) ;
3279 if (os::is_MP()) { masm.lock(); }
3280 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3281 masm.bind(DONE_LABEL);
3282 } else {
3283 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3285 // Critically, the biased locking test must have precedence over
3286 // and appear before the (box->dhw == 0) recursive stack-lock test.
3287 if (UseBiasedLocking && !UseOptoBiasInlining) {
3288 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3289 }
3291 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3292 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3293 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3295 masm.testptr(tmpReg, 0x02) ; // Inflated?
3296 masm.jccb (Assembler::zero, Stacked) ;
3298 masm.bind (Inflated) ;
3299 // It's inflated.
3300 // Despite our balanced locking property we still check that m->_owner == Self
3301 // as java routines or native JNI code called by this thread might
3302 // have released the lock.
3303 // Refer to the comments in synchronizer.cpp for how we might encode extra
3304 // state in _succ so we can avoid fetching EntryList|cxq.
3305 //
3306 // I'd like to add more cases in fast_lock() and fast_unlock() --
3307 // such as recursive enter and exit -- but we have to be wary of
3308 // I$ bloat, T$ effects and BP$ effects.
3309 //
3310 // If there's no contention try a 1-0 exit. That is, exit without
3311 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3312 // we detect and recover from the race that the 1-0 exit admits.
3313 //
3314 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3315 // before it STs null into _owner, releasing the lock. Updates
3316 // to data protected by the critical section must be visible before
3317 // we drop the lock (and thus before any other thread could acquire
3318 // the lock and observe the fields protected by the lock).
3319 // IA32's memory-model is SPO, so STs are ordered with respect to
3320 // each other and there's no need for an explicit barrier (fence).
3321 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3323 masm.get_thread (boxReg) ;
3324 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3325 // prefetchw [ebx + Offset(_owner)-2]
3326 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3327 }
3329 // Note that we could employ various encoding schemes to reduce
3330 // the number of loads below (currently 4) to just 2 or 3.
3331 // Refer to the comments in synchronizer.cpp.
3332 // In practice the chain of fetches doesn't seem to impact performance, however.
3333 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3334 // Attempt to reduce branch density - AMD's branch predictor.
3335 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3336 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3337 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3338 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3339 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3340 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3341 masm.jmpb (DONE_LABEL) ;
3342 } else {
3343 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3344 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3345 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3346 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3347 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3348 masm.jccb (Assembler::notZero, CheckSucc) ;
3349 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3350 masm.jmpb (DONE_LABEL) ;
3351 }
3353 // The Following code fragment (EmitSync & 65536) improves the performance of
3354 // contended applications and contended synchronization microbenchmarks.
3355 // Unfortunately the emission of the code - even though not executed - causes regressions
3356 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3357 // with an equal number of never-executed NOPs results in the same regression.
3358 // We leave it off by default.
3360 if ((EmitSync & 65536) != 0) {
3361 Label LSuccess, LGoSlowPath ;
3363 masm.bind (CheckSucc) ;
3365 // Optional pre-test ... it's safe to elide this
3366 if ((EmitSync & 16) == 0) {
3367 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3368 masm.jccb (Assembler::zero, LGoSlowPath) ;
3369 }
3371 // We have a classic Dekker-style idiom:
3372 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3373 // There are a number of ways to implement the barrier:
3374 // (1) lock:andl &m->_owner, 0
3375 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3376 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3377 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3378 // (2) If supported, an explicit MFENCE is appealing.
3379 // In older IA32 processors MFENCE is slower than lock:add or xchg
3380 // particularly if the write-buffer is full as might be the case if
3381 // if stores closely precede the fence or fence-equivalent instruction.
3382 // In more modern implementations MFENCE appears faster, however.
3383 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3384 // The $lines underlying the top-of-stack should be in M-state.
3385 // The locked add instruction is serializing, of course.
3386 // (4) Use xchg, which is serializing
3387 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3388 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3389 // The integer condition codes will tell us if succ was 0.
3390 // Since _succ and _owner should reside in the same $line and
3391 // we just stored into _owner, it's likely that the $line
3392 // remains in M-state for the lock:orl.
3393 //
3394 // We currently use (3), although it's likely that switching to (2)
3395 // is correct for the future.
3397 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3398 if (os::is_MP()) {
3399 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3400 masm.mfence();
3401 } else {
3402 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3403 }
3404 }
3405 // Ratify _succ remains non-null
3406 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3407 masm.jccb (Assembler::notZero, LSuccess) ;
3409 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3410 if (os::is_MP()) { masm.lock(); }
3411 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3412 masm.jccb (Assembler::notEqual, LSuccess) ;
3413 // Since we're low on registers we installed rsp as a placeholding in _owner.
3414 // Now install Self over rsp. This is safe as we're transitioning from
3415 // non-null to non=null
3416 masm.get_thread (boxReg) ;
3417 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3418 // Intentional fall-through into LGoSlowPath ...
3420 masm.bind (LGoSlowPath) ;
3421 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3422 masm.jmpb (DONE_LABEL) ;
3424 masm.bind (LSuccess) ;
3425 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3426 masm.jmpb (DONE_LABEL) ;
3427 }
3429 masm.bind (Stacked) ;
3430 // It's not inflated and it's not recursively stack-locked and it's not biased.
3431 // It must be stack-locked.
3432 // Try to reset the header to displaced header.
3433 // The "box" value on the stack is stable, so we can reload
3434 // and be assured we observe the same value as above.
3435 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3436 if (os::is_MP()) { masm.lock(); }
3437 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3438 // Intention fall-thru into DONE_LABEL
3441 // DONE_LABEL is a hot target - we'd really like to place it at the
3442 // start of cache line by padding with NOPs.
3443 // See the AMD and Intel software optimization manuals for the
3444 // most efficient "long" NOP encodings.
3445 // Unfortunately none of our alignment mechanisms suffice.
3446 if ((EmitSync & 65536) == 0) {
3447 masm.bind (CheckSucc) ;
3448 }
3449 masm.bind(DONE_LABEL);
3451 // Avoid branch to branch on AMD processors
3452 if (EmitSync & 32768) { masm.nop() ; }
3453 }
3454 %}
3457 enc_class enc_pop_rdx() %{
3458 emit_opcode(cbuf,0x5A);
3459 %}
3461 enc_class enc_rethrow() %{
3462 cbuf.set_insts_mark();
3463 emit_opcode(cbuf, 0xE9); // jmp entry
3464 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3465 runtime_call_Relocation::spec(), RELOC_IMM32 );
3466 %}
3469 // Convert a double to an int. Java semantics require we do complex
3470 // manglelations in the corner cases. So we set the rounding mode to
3471 // 'zero', store the darned double down as an int, and reset the
3472 // rounding mode to 'nearest'. The hardware throws an exception which
3473 // patches up the correct value directly to the stack.
3474 enc_class DPR2I_encoding( regDPR src ) %{
3475 // Flip to round-to-zero mode. We attempted to allow invalid-op
3476 // exceptions here, so that a NAN or other corner-case value will
3477 // thrown an exception (but normal values get converted at full speed).
3478 // However, I2C adapters and other float-stack manglers leave pending
3479 // invalid-op exceptions hanging. We would have to clear them before
3480 // enabling them and that is more expensive than just testing for the
3481 // invalid value Intel stores down in the corner cases.
3482 emit_opcode(cbuf,0xD9); // FLDCW trunc
3483 emit_opcode(cbuf,0x2D);
3484 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3485 // Allocate a word
3486 emit_opcode(cbuf,0x83); // SUB ESP,4
3487 emit_opcode(cbuf,0xEC);
3488 emit_d8(cbuf,0x04);
3489 // Encoding assumes a double has been pushed into FPR0.
3490 // Store down the double as an int, popping the FPU stack
3491 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3492 emit_opcode(cbuf,0x1C);
3493 emit_d8(cbuf,0x24);
3494 // Restore the rounding mode; mask the exception
3495 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3496 emit_opcode(cbuf,0x2D);
3497 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3498 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3499 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3501 // Load the converted int; adjust CPU stack
3502 emit_opcode(cbuf,0x58); // POP EAX
3503 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3504 emit_d32 (cbuf,0x80000000); // 0x80000000
3505 emit_opcode(cbuf,0x75); // JNE around_slow_call
3506 emit_d8 (cbuf,0x07); // Size of slow_call
3507 // Push src onto stack slow-path
3508 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3509 emit_d8 (cbuf,0xC0-1+$src$$reg );
3510 // CALL directly to the runtime
3511 cbuf.set_insts_mark();
3512 emit_opcode(cbuf,0xE8); // Call into runtime
3513 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3514 // Carry on here...
3515 %}
3517 enc_class DPR2L_encoding( regDPR src ) %{
3518 emit_opcode(cbuf,0xD9); // FLDCW trunc
3519 emit_opcode(cbuf,0x2D);
3520 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3521 // Allocate a word
3522 emit_opcode(cbuf,0x83); // SUB ESP,8
3523 emit_opcode(cbuf,0xEC);
3524 emit_d8(cbuf,0x08);
3525 // Encoding assumes a double has been pushed into FPR0.
3526 // Store down the double as a long, popping the FPU stack
3527 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3528 emit_opcode(cbuf,0x3C);
3529 emit_d8(cbuf,0x24);
3530 // Restore the rounding mode; mask the exception
3531 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3532 emit_opcode(cbuf,0x2D);
3533 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3534 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3535 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3537 // Load the converted int; adjust CPU stack
3538 emit_opcode(cbuf,0x58); // POP EAX
3539 emit_opcode(cbuf,0x5A); // POP EDX
3540 emit_opcode(cbuf,0x81); // CMP EDX,imm
3541 emit_d8 (cbuf,0xFA); // rdx
3542 emit_d32 (cbuf,0x80000000); // 0x80000000
3543 emit_opcode(cbuf,0x75); // JNE around_slow_call
3544 emit_d8 (cbuf,0x07+4); // Size of slow_call
3545 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3546 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3547 emit_opcode(cbuf,0x75); // JNE around_slow_call
3548 emit_d8 (cbuf,0x07); // Size of slow_call
3549 // Push src onto stack slow-path
3550 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3551 emit_d8 (cbuf,0xC0-1+$src$$reg );
3552 // CALL directly to the runtime
3553 cbuf.set_insts_mark();
3554 emit_opcode(cbuf,0xE8); // Call into runtime
3555 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3556 // Carry on here...
3557 %}
3559 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3560 // Operand was loaded from memory into fp ST (stack top)
3561 // FMUL ST,$src /* D8 C8+i */
3562 emit_opcode(cbuf, 0xD8);
3563 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3564 %}
3566 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3567 // FADDP ST,src2 /* D8 C0+i */
3568 emit_opcode(cbuf, 0xD8);
3569 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3570 //could use FADDP src2,fpST /* DE C0+i */
3571 %}
3573 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3574 // FADDP src2,ST /* DE C0+i */
3575 emit_opcode(cbuf, 0xDE);
3576 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3577 %}
3579 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3580 // Operand has been loaded into fp ST (stack top)
3581 // FSUB ST,$src1
3582 emit_opcode(cbuf, 0xD8);
3583 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3585 // FDIV
3586 emit_opcode(cbuf, 0xD8);
3587 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3588 %}
3590 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3591 // Operand was loaded from memory into fp ST (stack top)
3592 // FADD ST,$src /* D8 C0+i */
3593 emit_opcode(cbuf, 0xD8);
3594 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3596 // FMUL ST,src2 /* D8 C*+i */
3597 emit_opcode(cbuf, 0xD8);
3598 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3599 %}
3602 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3603 // Operand was loaded from memory into fp ST (stack top)
3604 // FADD ST,$src /* D8 C0+i */
3605 emit_opcode(cbuf, 0xD8);
3606 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3608 // FMULP src2,ST /* DE C8+i */
3609 emit_opcode(cbuf, 0xDE);
3610 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3611 %}
3613 // Atomically load the volatile long
3614 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3615 emit_opcode(cbuf,0xDF);
3616 int rm_byte_opcode = 0x05;
3617 int base = $mem$$base;
3618 int index = $mem$$index;
3619 int scale = $mem$$scale;
3620 int displace = $mem$$disp;
3621 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3622 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3623 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3624 %}
3626 // Volatile Store Long. Must be atomic, so move it into
3627 // the FP TOS and then do a 64-bit FIST. Has to probe the
3628 // target address before the store (for null-ptr checks)
3629 // so the memory operand is used twice in the encoding.
3630 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3631 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3632 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3633 emit_opcode(cbuf,0xDF);
3634 int rm_byte_opcode = 0x07;
3635 int base = $mem$$base;
3636 int index = $mem$$index;
3637 int scale = $mem$$scale;
3638 int displace = $mem$$disp;
3639 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3640 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3641 %}
3643 // Safepoint Poll. This polls the safepoint page, and causes an
3644 // exception if it is not readable. Unfortunately, it kills the condition code
3645 // in the process
3646 // We current use TESTL [spp],EDI
3647 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3649 enc_class Safepoint_Poll() %{
3650 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3651 emit_opcode(cbuf,0x85);
3652 emit_rm (cbuf, 0x0, 0x7, 0x5);
3653 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3654 %}
3655 %}
3658 //----------FRAME--------------------------------------------------------------
3659 // Definition of frame structure and management information.
3660 //
3661 // S T A C K L A Y O U T Allocators stack-slot number
3662 // | (to get allocators register number
3663 // G Owned by | | v add OptoReg::stack0())
3664 // r CALLER | |
3665 // o | +--------+ pad to even-align allocators stack-slot
3666 // w V | pad0 | numbers; owned by CALLER
3667 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3668 // h ^ | in | 5
3669 // | | args | 4 Holes in incoming args owned by SELF
3670 // | | | | 3
3671 // | | +--------+
3672 // V | | old out| Empty on Intel, window on Sparc
3673 // | old |preserve| Must be even aligned.
3674 // | SP-+--------+----> Matcher::_old_SP, even aligned
3675 // | | in | 3 area for Intel ret address
3676 // Owned by |preserve| Empty on Sparc.
3677 // SELF +--------+
3678 // | | pad2 | 2 pad to align old SP
3679 // | +--------+ 1
3680 // | | locks | 0
3681 // | +--------+----> OptoReg::stack0(), even aligned
3682 // | | pad1 | 11 pad to align new SP
3683 // | +--------+
3684 // | | | 10
3685 // | | spills | 9 spills
3686 // V | | 8 (pad0 slot for callee)
3687 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3688 // ^ | out | 7
3689 // | | args | 6 Holes in outgoing args owned by CALLEE
3690 // Owned by +--------+
3691 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3692 // | new |preserve| Must be even-aligned.
3693 // | SP-+--------+----> Matcher::_new_SP, even aligned
3694 // | | |
3695 //
3696 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3697 // known from SELF's arguments and the Java calling convention.
3698 // Region 6-7 is determined per call site.
3699 // Note 2: If the calling convention leaves holes in the incoming argument
3700 // area, those holes are owned by SELF. Holes in the outgoing area
3701 // are owned by the CALLEE. Holes should not be nessecary in the
3702 // incoming area, as the Java calling convention is completely under
3703 // the control of the AD file. Doubles can be sorted and packed to
3704 // avoid holes. Holes in the outgoing arguments may be nessecary for
3705 // varargs C calling conventions.
3706 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3707 // even aligned with pad0 as needed.
3708 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3709 // region 6-11 is even aligned; it may be padded out more so that
3710 // the region from SP to FP meets the minimum stack alignment.
3712 frame %{
3713 // What direction does stack grow in (assumed to be same for C & Java)
3714 stack_direction(TOWARDS_LOW);
3716 // These three registers define part of the calling convention
3717 // between compiled code and the interpreter.
3718 inline_cache_reg(EAX); // Inline Cache Register
3719 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3721 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3722 cisc_spilling_operand_name(indOffset32);
3724 // Number of stack slots consumed by locking an object
3725 sync_stack_slots(1);
3727 // Compiled code's Frame Pointer
3728 frame_pointer(ESP);
3729 // Interpreter stores its frame pointer in a register which is
3730 // stored to the stack by I2CAdaptors.
3731 // I2CAdaptors convert from interpreted java to compiled java.
3732 interpreter_frame_pointer(EBP);
3734 // Stack alignment requirement
3735 // Alignment size in bytes (128-bit -> 16 bytes)
3736 stack_alignment(StackAlignmentInBytes);
3738 // Number of stack slots between incoming argument block and the start of
3739 // a new frame. The PROLOG must add this many slots to the stack. The
3740 // EPILOG must remove this many slots. Intel needs one slot for
3741 // return address and one for rbp, (must save rbp)
3742 in_preserve_stack_slots(2+VerifyStackAtCalls);
3744 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3745 // for calls to C. Supports the var-args backing area for register parms.
3746 varargs_C_out_slots_killed(0);
3748 // The after-PROLOG location of the return address. Location of
3749 // return address specifies a type (REG or STACK) and a number
3750 // representing the register number (i.e. - use a register name) or
3751 // stack slot.
3752 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3753 // Otherwise, it is above the locks and verification slot and alignment word
3754 return_addr(STACK - 1 +
3755 round_to((Compile::current()->in_preserve_stack_slots() +
3756 Compile::current()->fixed_slots()),
3757 stack_alignment_in_slots()));
3759 // Body of function which returns an integer array locating
3760 // arguments either in registers or in stack slots. Passed an array
3761 // of ideal registers called "sig" and a "length" count. Stack-slot
3762 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3763 // arguments for a CALLEE. Incoming stack arguments are
3764 // automatically biased by the preserve_stack_slots field above.
3765 calling_convention %{
3766 // No difference between ingoing/outgoing just pass false
3767 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3768 %}
3771 // Body of function which returns an integer array locating
3772 // arguments either in registers or in stack slots. Passed an array
3773 // of ideal registers called "sig" and a "length" count. Stack-slot
3774 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3775 // arguments for a CALLEE. Incoming stack arguments are
3776 // automatically biased by the preserve_stack_slots field above.
3777 c_calling_convention %{
3778 // This is obviously always outgoing
3779 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3780 %}
3782 // Location of C & interpreter return values
3783 c_return_value %{
3784 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3785 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3786 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3788 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3789 // that C functions return float and double results in XMM0.
3790 if( ideal_reg == Op_RegD && UseSSE>=2 )
3791 return OptoRegPair(XMM0b_num,XMM0_num);
3792 if( ideal_reg == Op_RegF && UseSSE>=2 )
3793 return OptoRegPair(OptoReg::Bad,XMM0_num);
3795 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3796 %}
3798 // Location of return values
3799 return_value %{
3800 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3801 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3802 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3803 if( ideal_reg == Op_RegD && UseSSE>=2 )
3804 return OptoRegPair(XMM0b_num,XMM0_num);
3805 if( ideal_reg == Op_RegF && UseSSE>=1 )
3806 return OptoRegPair(OptoReg::Bad,XMM0_num);
3807 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3808 %}
3810 %}
3812 //----------ATTRIBUTES---------------------------------------------------------
3813 //----------Operand Attributes-------------------------------------------------
3814 op_attrib op_cost(0); // Required cost attribute
3816 //----------Instruction Attributes---------------------------------------------
3817 ins_attrib ins_cost(100); // Required cost attribute
3818 ins_attrib ins_size(8); // Required size attribute (in bits)
3819 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3820 // non-matching short branch variant of some
3821 // long branch?
3822 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3823 // specifies the alignment that some part of the instruction (not
3824 // necessarily the start) requires. If > 1, a compute_padding()
3825 // function must be provided for the instruction
3827 //----------OPERANDS-----------------------------------------------------------
3828 // Operand definitions must precede instruction definitions for correct parsing
3829 // in the ADLC because operands constitute user defined types which are used in
3830 // instruction definitions.
3832 //----------Simple Operands----------------------------------------------------
3833 // Immediate Operands
3834 // Integer Immediate
3835 operand immI() %{
3836 match(ConI);
3838 op_cost(10);
3839 format %{ %}
3840 interface(CONST_INTER);
3841 %}
3843 // Constant for test vs zero
3844 operand immI0() %{
3845 predicate(n->get_int() == 0);
3846 match(ConI);
3848 op_cost(0);
3849 format %{ %}
3850 interface(CONST_INTER);
3851 %}
3853 // Constant for increment
3854 operand immI1() %{
3855 predicate(n->get_int() == 1);
3856 match(ConI);
3858 op_cost(0);
3859 format %{ %}
3860 interface(CONST_INTER);
3861 %}
3863 // Constant for decrement
3864 operand immI_M1() %{
3865 predicate(n->get_int() == -1);
3866 match(ConI);
3868 op_cost(0);
3869 format %{ %}
3870 interface(CONST_INTER);
3871 %}
3873 // Valid scale values for addressing modes
3874 operand immI2() %{
3875 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3876 match(ConI);
3878 format %{ %}
3879 interface(CONST_INTER);
3880 %}
3882 operand immI8() %{
3883 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3884 match(ConI);
3886 op_cost(5);
3887 format %{ %}
3888 interface(CONST_INTER);
3889 %}
3891 operand immI16() %{
3892 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3893 match(ConI);
3895 op_cost(10);
3896 format %{ %}
3897 interface(CONST_INTER);
3898 %}
3900 // Constant for long shifts
3901 operand immI_32() %{
3902 predicate( n->get_int() == 32 );
3903 match(ConI);
3905 op_cost(0);
3906 format %{ %}
3907 interface(CONST_INTER);
3908 %}
3910 operand immI_1_31() %{
3911 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3912 match(ConI);
3914 op_cost(0);
3915 format %{ %}
3916 interface(CONST_INTER);
3917 %}
3919 operand immI_32_63() %{
3920 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3921 match(ConI);
3922 op_cost(0);
3924 format %{ %}
3925 interface(CONST_INTER);
3926 %}
3928 operand immI_1() %{
3929 predicate( n->get_int() == 1 );
3930 match(ConI);
3932 op_cost(0);
3933 format %{ %}
3934 interface(CONST_INTER);
3935 %}
3937 operand immI_2() %{
3938 predicate( n->get_int() == 2 );
3939 match(ConI);
3941 op_cost(0);
3942 format %{ %}
3943 interface(CONST_INTER);
3944 %}
3946 operand immI_3() %{
3947 predicate( n->get_int() == 3 );
3948 match(ConI);
3950 op_cost(0);
3951 format %{ %}
3952 interface(CONST_INTER);
3953 %}
3955 // Pointer Immediate
3956 operand immP() %{
3957 match(ConP);
3959 op_cost(10);
3960 format %{ %}
3961 interface(CONST_INTER);
3962 %}
3964 // NULL Pointer Immediate
3965 operand immP0() %{
3966 predicate( n->get_ptr() == 0 );
3967 match(ConP);
3968 op_cost(0);
3970 format %{ %}
3971 interface(CONST_INTER);
3972 %}
3974 // Long Immediate
3975 operand immL() %{
3976 match(ConL);
3978 op_cost(20);
3979 format %{ %}
3980 interface(CONST_INTER);
3981 %}
3983 // Long Immediate zero
3984 operand immL0() %{
3985 predicate( n->get_long() == 0L );
3986 match(ConL);
3987 op_cost(0);
3989 format %{ %}
3990 interface(CONST_INTER);
3991 %}
3993 // Long Immediate zero
3994 operand immL_M1() %{
3995 predicate( n->get_long() == -1L );
3996 match(ConL);
3997 op_cost(0);
3999 format %{ %}
4000 interface(CONST_INTER);
4001 %}
4003 // Long immediate from 0 to 127.
4004 // Used for a shorter form of long mul by 10.
4005 operand immL_127() %{
4006 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4007 match(ConL);
4008 op_cost(0);
4010 format %{ %}
4011 interface(CONST_INTER);
4012 %}
4014 // Long Immediate: low 32-bit mask
4015 operand immL_32bits() %{
4016 predicate(n->get_long() == 0xFFFFFFFFL);
4017 match(ConL);
4018 op_cost(0);
4020 format %{ %}
4021 interface(CONST_INTER);
4022 %}
4024 // Long Immediate: low 32-bit mask
4025 operand immL32() %{
4026 predicate(n->get_long() == (int)(n->get_long()));
4027 match(ConL);
4028 op_cost(20);
4030 format %{ %}
4031 interface(CONST_INTER);
4032 %}
4034 //Double Immediate zero
4035 operand immDPR0() %{
4036 // Do additional (and counter-intuitive) test against NaN to work around VC++
4037 // bug that generates code such that NaNs compare equal to 0.0
4038 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4039 match(ConD);
4041 op_cost(5);
4042 format %{ %}
4043 interface(CONST_INTER);
4044 %}
4046 // Double Immediate one
4047 operand immDPR1() %{
4048 predicate( UseSSE<=1 && n->getd() == 1.0 );
4049 match(ConD);
4051 op_cost(5);
4052 format %{ %}
4053 interface(CONST_INTER);
4054 %}
4056 // Double Immediate
4057 operand immDPR() %{
4058 predicate(UseSSE<=1);
4059 match(ConD);
4061 op_cost(5);
4062 format %{ %}
4063 interface(CONST_INTER);
4064 %}
4066 operand immD() %{
4067 predicate(UseSSE>=2);
4068 match(ConD);
4070 op_cost(5);
4071 format %{ %}
4072 interface(CONST_INTER);
4073 %}
4075 // Double Immediate zero
4076 operand immD0() %{
4077 // Do additional (and counter-intuitive) test against NaN to work around VC++
4078 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4079 // compare equal to -0.0.
4080 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4081 match(ConD);
4083 format %{ %}
4084 interface(CONST_INTER);
4085 %}
4087 // Float Immediate zero
4088 operand immFPR0() %{
4089 predicate(UseSSE == 0 && n->getf() == 0.0F);
4090 match(ConF);
4092 op_cost(5);
4093 format %{ %}
4094 interface(CONST_INTER);
4095 %}
4097 // Float Immediate one
4098 operand immFPR1() %{
4099 predicate(UseSSE == 0 && n->getf() == 1.0F);
4100 match(ConF);
4102 op_cost(5);
4103 format %{ %}
4104 interface(CONST_INTER);
4105 %}
4107 // Float Immediate
4108 operand immFPR() %{
4109 predicate( UseSSE == 0 );
4110 match(ConF);
4112 op_cost(5);
4113 format %{ %}
4114 interface(CONST_INTER);
4115 %}
4117 // Float Immediate
4118 operand immF() %{
4119 predicate(UseSSE >= 1);
4120 match(ConF);
4122 op_cost(5);
4123 format %{ %}
4124 interface(CONST_INTER);
4125 %}
4127 // Float Immediate zero. Zero and not -0.0
4128 operand immF0() %{
4129 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4130 match(ConF);
4132 op_cost(5);
4133 format %{ %}
4134 interface(CONST_INTER);
4135 %}
4137 // Immediates for special shifts (sign extend)
4139 // Constants for increment
4140 operand immI_16() %{
4141 predicate( n->get_int() == 16 );
4142 match(ConI);
4144 format %{ %}
4145 interface(CONST_INTER);
4146 %}
4148 operand immI_24() %{
4149 predicate( n->get_int() == 24 );
4150 match(ConI);
4152 format %{ %}
4153 interface(CONST_INTER);
4154 %}
4156 // Constant for byte-wide masking
4157 operand immI_255() %{
4158 predicate( n->get_int() == 255 );
4159 match(ConI);
4161 format %{ %}
4162 interface(CONST_INTER);
4163 %}
4165 // Constant for short-wide masking
4166 operand immI_65535() %{
4167 predicate(n->get_int() == 65535);
4168 match(ConI);
4170 format %{ %}
4171 interface(CONST_INTER);
4172 %}
4174 // Register Operands
4175 // Integer Register
4176 operand rRegI() %{
4177 constraint(ALLOC_IN_RC(int_reg));
4178 match(RegI);
4179 match(xRegI);
4180 match(eAXRegI);
4181 match(eBXRegI);
4182 match(eCXRegI);
4183 match(eDXRegI);
4184 match(eDIRegI);
4185 match(eSIRegI);
4187 format %{ %}
4188 interface(REG_INTER);
4189 %}
4191 // Subset of Integer Register
4192 operand xRegI(rRegI reg) %{
4193 constraint(ALLOC_IN_RC(int_x_reg));
4194 match(reg);
4195 match(eAXRegI);
4196 match(eBXRegI);
4197 match(eCXRegI);
4198 match(eDXRegI);
4200 format %{ %}
4201 interface(REG_INTER);
4202 %}
4204 // Special Registers
4205 operand eAXRegI(xRegI reg) %{
4206 constraint(ALLOC_IN_RC(eax_reg));
4207 match(reg);
4208 match(rRegI);
4210 format %{ "EAX" %}
4211 interface(REG_INTER);
4212 %}
4214 // Special Registers
4215 operand eBXRegI(xRegI reg) %{
4216 constraint(ALLOC_IN_RC(ebx_reg));
4217 match(reg);
4218 match(rRegI);
4220 format %{ "EBX" %}
4221 interface(REG_INTER);
4222 %}
4224 operand eCXRegI(xRegI reg) %{
4225 constraint(ALLOC_IN_RC(ecx_reg));
4226 match(reg);
4227 match(rRegI);
4229 format %{ "ECX" %}
4230 interface(REG_INTER);
4231 %}
4233 operand eDXRegI(xRegI reg) %{
4234 constraint(ALLOC_IN_RC(edx_reg));
4235 match(reg);
4236 match(rRegI);
4238 format %{ "EDX" %}
4239 interface(REG_INTER);
4240 %}
4242 operand eDIRegI(xRegI reg) %{
4243 constraint(ALLOC_IN_RC(edi_reg));
4244 match(reg);
4245 match(rRegI);
4247 format %{ "EDI" %}
4248 interface(REG_INTER);
4249 %}
4251 operand naxRegI() %{
4252 constraint(ALLOC_IN_RC(nax_reg));
4253 match(RegI);
4254 match(eCXRegI);
4255 match(eDXRegI);
4256 match(eSIRegI);
4257 match(eDIRegI);
4259 format %{ %}
4260 interface(REG_INTER);
4261 %}
4263 operand nadxRegI() %{
4264 constraint(ALLOC_IN_RC(nadx_reg));
4265 match(RegI);
4266 match(eBXRegI);
4267 match(eCXRegI);
4268 match(eSIRegI);
4269 match(eDIRegI);
4271 format %{ %}
4272 interface(REG_INTER);
4273 %}
4275 operand ncxRegI() %{
4276 constraint(ALLOC_IN_RC(ncx_reg));
4277 match(RegI);
4278 match(eAXRegI);
4279 match(eDXRegI);
4280 match(eSIRegI);
4281 match(eDIRegI);
4283 format %{ %}
4284 interface(REG_INTER);
4285 %}
4287 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4288 // //
4289 operand eSIRegI(xRegI reg) %{
4290 constraint(ALLOC_IN_RC(esi_reg));
4291 match(reg);
4292 match(rRegI);
4294 format %{ "ESI" %}
4295 interface(REG_INTER);
4296 %}
4298 // Pointer Register
4299 operand anyRegP() %{
4300 constraint(ALLOC_IN_RC(any_reg));
4301 match(RegP);
4302 match(eAXRegP);
4303 match(eBXRegP);
4304 match(eCXRegP);
4305 match(eDIRegP);
4306 match(eRegP);
4308 format %{ %}
4309 interface(REG_INTER);
4310 %}
4312 operand eRegP() %{
4313 constraint(ALLOC_IN_RC(int_reg));
4314 match(RegP);
4315 match(eAXRegP);
4316 match(eBXRegP);
4317 match(eCXRegP);
4318 match(eDIRegP);
4320 format %{ %}
4321 interface(REG_INTER);
4322 %}
4324 // On windows95, EBP is not safe to use for implicit null tests.
4325 operand eRegP_no_EBP() %{
4326 constraint(ALLOC_IN_RC(int_reg_no_rbp));
4327 match(RegP);
4328 match(eAXRegP);
4329 match(eBXRegP);
4330 match(eCXRegP);
4331 match(eDIRegP);
4333 op_cost(100);
4334 format %{ %}
4335 interface(REG_INTER);
4336 %}
4338 operand naxRegP() %{
4339 constraint(ALLOC_IN_RC(nax_reg));
4340 match(RegP);
4341 match(eBXRegP);
4342 match(eDXRegP);
4343 match(eCXRegP);
4344 match(eSIRegP);
4345 match(eDIRegP);
4347 format %{ %}
4348 interface(REG_INTER);
4349 %}
4351 operand nabxRegP() %{
4352 constraint(ALLOC_IN_RC(nabx_reg));
4353 match(RegP);
4354 match(eCXRegP);
4355 match(eDXRegP);
4356 match(eSIRegP);
4357 match(eDIRegP);
4359 format %{ %}
4360 interface(REG_INTER);
4361 %}
4363 operand pRegP() %{
4364 constraint(ALLOC_IN_RC(p_reg));
4365 match(RegP);
4366 match(eBXRegP);
4367 match(eDXRegP);
4368 match(eSIRegP);
4369 match(eDIRegP);
4371 format %{ %}
4372 interface(REG_INTER);
4373 %}
4375 // Special Registers
4376 // Return a pointer value
4377 operand eAXRegP(eRegP reg) %{
4378 constraint(ALLOC_IN_RC(eax_reg));
4379 match(reg);
4380 format %{ "EAX" %}
4381 interface(REG_INTER);
4382 %}
4384 // Used in AtomicAdd
4385 operand eBXRegP(eRegP reg) %{
4386 constraint(ALLOC_IN_RC(ebx_reg));
4387 match(reg);
4388 format %{ "EBX" %}
4389 interface(REG_INTER);
4390 %}
4392 // Tail-call (interprocedural jump) to interpreter
4393 operand eCXRegP(eRegP reg) %{
4394 constraint(ALLOC_IN_RC(ecx_reg));
4395 match(reg);
4396 format %{ "ECX" %}
4397 interface(REG_INTER);
4398 %}
4400 operand eSIRegP(eRegP reg) %{
4401 constraint(ALLOC_IN_RC(esi_reg));
4402 match(reg);
4403 format %{ "ESI" %}
4404 interface(REG_INTER);
4405 %}
4407 // Used in rep stosw
4408 operand eDIRegP(eRegP reg) %{
4409 constraint(ALLOC_IN_RC(edi_reg));
4410 match(reg);
4411 format %{ "EDI" %}
4412 interface(REG_INTER);
4413 %}
4415 operand eBPRegP() %{
4416 constraint(ALLOC_IN_RC(ebp_reg));
4417 match(RegP);
4418 format %{ "EBP" %}
4419 interface(REG_INTER);
4420 %}
4422 operand eRegL() %{
4423 constraint(ALLOC_IN_RC(long_reg));
4424 match(RegL);
4425 match(eADXRegL);
4427 format %{ %}
4428 interface(REG_INTER);
4429 %}
4431 operand eADXRegL( eRegL reg ) %{
4432 constraint(ALLOC_IN_RC(eadx_reg));
4433 match(reg);
4435 format %{ "EDX:EAX" %}
4436 interface(REG_INTER);
4437 %}
4439 operand eBCXRegL( eRegL reg ) %{
4440 constraint(ALLOC_IN_RC(ebcx_reg));
4441 match(reg);
4443 format %{ "EBX:ECX" %}
4444 interface(REG_INTER);
4445 %}
4447 // Special case for integer high multiply
4448 operand eADXRegL_low_only() %{
4449 constraint(ALLOC_IN_RC(eadx_reg));
4450 match(RegL);
4452 format %{ "EAX" %}
4453 interface(REG_INTER);
4454 %}
4456 // Flags register, used as output of compare instructions
4457 operand eFlagsReg() %{
4458 constraint(ALLOC_IN_RC(int_flags));
4459 match(RegFlags);
4461 format %{ "EFLAGS" %}
4462 interface(REG_INTER);
4463 %}
4465 // Flags register, used as output of FLOATING POINT compare instructions
4466 operand eFlagsRegU() %{
4467 constraint(ALLOC_IN_RC(int_flags));
4468 match(RegFlags);
4470 format %{ "EFLAGS_U" %}
4471 interface(REG_INTER);
4472 %}
4474 operand eFlagsRegUCF() %{
4475 constraint(ALLOC_IN_RC(int_flags));
4476 match(RegFlags);
4477 predicate(false);
4479 format %{ "EFLAGS_U_CF" %}
4480 interface(REG_INTER);
4481 %}
4483 // Condition Code Register used by long compare
4484 operand flagsReg_long_LTGE() %{
4485 constraint(ALLOC_IN_RC(int_flags));
4486 match(RegFlags);
4487 format %{ "FLAGS_LTGE" %}
4488 interface(REG_INTER);
4489 %}
4490 operand flagsReg_long_EQNE() %{
4491 constraint(ALLOC_IN_RC(int_flags));
4492 match(RegFlags);
4493 format %{ "FLAGS_EQNE" %}
4494 interface(REG_INTER);
4495 %}
4496 operand flagsReg_long_LEGT() %{
4497 constraint(ALLOC_IN_RC(int_flags));
4498 match(RegFlags);
4499 format %{ "FLAGS_LEGT" %}
4500 interface(REG_INTER);
4501 %}
4503 // Float register operands
4504 operand regDPR() %{
4505 predicate( UseSSE < 2 );
4506 constraint(ALLOC_IN_RC(fp_dbl_reg));
4507 match(RegD);
4508 match(regDPR1);
4509 match(regDPR2);
4510 format %{ %}
4511 interface(REG_INTER);
4512 %}
4514 operand regDPR1(regDPR reg) %{
4515 predicate( UseSSE < 2 );
4516 constraint(ALLOC_IN_RC(fp_dbl_reg0));
4517 match(reg);
4518 format %{ "FPR1" %}
4519 interface(REG_INTER);
4520 %}
4522 operand regDPR2(regDPR reg) %{
4523 predicate( UseSSE < 2 );
4524 constraint(ALLOC_IN_RC(fp_dbl_reg1));
4525 match(reg);
4526 format %{ "FPR2" %}
4527 interface(REG_INTER);
4528 %}
4530 operand regnotDPR1(regDPR reg) %{
4531 predicate( UseSSE < 2 );
4532 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
4533 match(reg);
4534 format %{ %}
4535 interface(REG_INTER);
4536 %}
4538 // Float register operands
4539 operand regFPR() %{
4540 predicate( UseSSE < 2 );
4541 constraint(ALLOC_IN_RC(fp_flt_reg));
4542 match(RegF);
4543 match(regFPR1);
4544 format %{ %}
4545 interface(REG_INTER);
4546 %}
4548 // Float register operands
4549 operand regFPR1(regFPR reg) %{
4550 predicate( UseSSE < 2 );
4551 constraint(ALLOC_IN_RC(fp_flt_reg0));
4552 match(reg);
4553 format %{ "FPR1" %}
4554 interface(REG_INTER);
4555 %}
4557 // XMM Float register operands
4558 operand regF() %{
4559 predicate( UseSSE>=1 );
4560 constraint(ALLOC_IN_RC(float_reg));
4561 match(RegF);
4562 format %{ %}
4563 interface(REG_INTER);
4564 %}
4566 // XMM Double register operands
4567 operand regD() %{
4568 predicate( UseSSE>=2 );
4569 constraint(ALLOC_IN_RC(double_reg));
4570 match(RegD);
4571 format %{ %}
4572 interface(REG_INTER);
4573 %}
4576 //----------Memory Operands----------------------------------------------------
4577 // Direct Memory Operand
4578 operand direct(immP addr) %{
4579 match(addr);
4581 format %{ "[$addr]" %}
4582 interface(MEMORY_INTER) %{
4583 base(0xFFFFFFFF);
4584 index(0x4);
4585 scale(0x0);
4586 disp($addr);
4587 %}
4588 %}
4590 // Indirect Memory Operand
4591 operand indirect(eRegP reg) %{
4592 constraint(ALLOC_IN_RC(int_reg));
4593 match(reg);
4595 format %{ "[$reg]" %}
4596 interface(MEMORY_INTER) %{
4597 base($reg);
4598 index(0x4);
4599 scale(0x0);
4600 disp(0x0);
4601 %}
4602 %}
4604 // Indirect Memory Plus Short Offset Operand
4605 operand indOffset8(eRegP reg, immI8 off) %{
4606 match(AddP reg off);
4608 format %{ "[$reg + $off]" %}
4609 interface(MEMORY_INTER) %{
4610 base($reg);
4611 index(0x4);
4612 scale(0x0);
4613 disp($off);
4614 %}
4615 %}
4617 // Indirect Memory Plus Long Offset Operand
4618 operand indOffset32(eRegP reg, immI off) %{
4619 match(AddP reg off);
4621 format %{ "[$reg + $off]" %}
4622 interface(MEMORY_INTER) %{
4623 base($reg);
4624 index(0x4);
4625 scale(0x0);
4626 disp($off);
4627 %}
4628 %}
4630 // Indirect Memory Plus Long Offset Operand
4631 operand indOffset32X(rRegI reg, immP off) %{
4632 match(AddP off reg);
4634 format %{ "[$reg + $off]" %}
4635 interface(MEMORY_INTER) %{
4636 base($reg);
4637 index(0x4);
4638 scale(0x0);
4639 disp($off);
4640 %}
4641 %}
4643 // Indirect Memory Plus Index Register Plus Offset Operand
4644 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4645 match(AddP (AddP reg ireg) off);
4647 op_cost(10);
4648 format %{"[$reg + $off + $ireg]" %}
4649 interface(MEMORY_INTER) %{
4650 base($reg);
4651 index($ireg);
4652 scale(0x0);
4653 disp($off);
4654 %}
4655 %}
4657 // Indirect Memory Plus Index Register Plus Offset Operand
4658 operand indIndex(eRegP reg, rRegI ireg) %{
4659 match(AddP reg ireg);
4661 op_cost(10);
4662 format %{"[$reg + $ireg]" %}
4663 interface(MEMORY_INTER) %{
4664 base($reg);
4665 index($ireg);
4666 scale(0x0);
4667 disp(0x0);
4668 %}
4669 %}
4671 // // -------------------------------------------------------------------------
4672 // // 486 architecture doesn't support "scale * index + offset" with out a base
4673 // // -------------------------------------------------------------------------
4674 // // Scaled Memory Operands
4675 // // Indirect Memory Times Scale Plus Offset Operand
4676 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4677 // match(AddP off (LShiftI ireg scale));
4678 //
4679 // op_cost(10);
4680 // format %{"[$off + $ireg << $scale]" %}
4681 // interface(MEMORY_INTER) %{
4682 // base(0x4);
4683 // index($ireg);
4684 // scale($scale);
4685 // disp($off);
4686 // %}
4687 // %}
4689 // Indirect Memory Times Scale Plus Index Register
4690 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4691 match(AddP reg (LShiftI ireg scale));
4693 op_cost(10);
4694 format %{"[$reg + $ireg << $scale]" %}
4695 interface(MEMORY_INTER) %{
4696 base($reg);
4697 index($ireg);
4698 scale($scale);
4699 disp(0x0);
4700 %}
4701 %}
4703 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4704 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4705 match(AddP (AddP reg (LShiftI ireg scale)) off);
4707 op_cost(10);
4708 format %{"[$reg + $off + $ireg << $scale]" %}
4709 interface(MEMORY_INTER) %{
4710 base($reg);
4711 index($ireg);
4712 scale($scale);
4713 disp($off);
4714 %}
4715 %}
4717 //----------Load Long Memory Operands------------------------------------------
4718 // The load-long idiom will use it's address expression again after loading
4719 // the first word of the long. If the load-long destination overlaps with
4720 // registers used in the addressing expression, the 2nd half will be loaded
4721 // from a clobbered address. Fix this by requiring that load-long use
4722 // address registers that do not overlap with the load-long target.
4724 // load-long support
4725 operand load_long_RegP() %{
4726 constraint(ALLOC_IN_RC(esi_reg));
4727 match(RegP);
4728 match(eSIRegP);
4729 op_cost(100);
4730 format %{ %}
4731 interface(REG_INTER);
4732 %}
4734 // Indirect Memory Operand Long
4735 operand load_long_indirect(load_long_RegP reg) %{
4736 constraint(ALLOC_IN_RC(esi_reg));
4737 match(reg);
4739 format %{ "[$reg]" %}
4740 interface(MEMORY_INTER) %{
4741 base($reg);
4742 index(0x4);
4743 scale(0x0);
4744 disp(0x0);
4745 %}
4746 %}
4748 // Indirect Memory Plus Long Offset Operand
4749 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4750 match(AddP reg off);
4752 format %{ "[$reg + $off]" %}
4753 interface(MEMORY_INTER) %{
4754 base($reg);
4755 index(0x4);
4756 scale(0x0);
4757 disp($off);
4758 %}
4759 %}
4761 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4764 //----------Special Memory Operands--------------------------------------------
4765 // Stack Slot Operand - This operand is used for loading and storing temporary
4766 // values on the stack where a match requires a value to
4767 // flow through memory.
4768 operand stackSlotP(sRegP reg) %{
4769 constraint(ALLOC_IN_RC(stack_slots));
4770 // No match rule because this operand is only generated in matching
4771 format %{ "[$reg]" %}
4772 interface(MEMORY_INTER) %{
4773 base(0x4); // ESP
4774 index(0x4); // No Index
4775 scale(0x0); // No Scale
4776 disp($reg); // Stack Offset
4777 %}
4778 %}
4780 operand stackSlotI(sRegI reg) %{
4781 constraint(ALLOC_IN_RC(stack_slots));
4782 // No match rule because this operand is only generated in matching
4783 format %{ "[$reg]" %}
4784 interface(MEMORY_INTER) %{
4785 base(0x4); // ESP
4786 index(0x4); // No Index
4787 scale(0x0); // No Scale
4788 disp($reg); // Stack Offset
4789 %}
4790 %}
4792 operand stackSlotF(sRegF reg) %{
4793 constraint(ALLOC_IN_RC(stack_slots));
4794 // No match rule because this operand is only generated in matching
4795 format %{ "[$reg]" %}
4796 interface(MEMORY_INTER) %{
4797 base(0x4); // ESP
4798 index(0x4); // No Index
4799 scale(0x0); // No Scale
4800 disp($reg); // Stack Offset
4801 %}
4802 %}
4804 operand stackSlotD(sRegD reg) %{
4805 constraint(ALLOC_IN_RC(stack_slots));
4806 // No match rule because this operand is only generated in matching
4807 format %{ "[$reg]" %}
4808 interface(MEMORY_INTER) %{
4809 base(0x4); // ESP
4810 index(0x4); // No Index
4811 scale(0x0); // No Scale
4812 disp($reg); // Stack Offset
4813 %}
4814 %}
4816 operand stackSlotL(sRegL reg) %{
4817 constraint(ALLOC_IN_RC(stack_slots));
4818 // No match rule because this operand is only generated in matching
4819 format %{ "[$reg]" %}
4820 interface(MEMORY_INTER) %{
4821 base(0x4); // ESP
4822 index(0x4); // No Index
4823 scale(0x0); // No Scale
4824 disp($reg); // Stack Offset
4825 %}
4826 %}
4828 //----------Memory Operands - Win95 Implicit Null Variants----------------
4829 // Indirect Memory Operand
4830 operand indirect_win95_safe(eRegP_no_EBP reg)
4831 %{
4832 constraint(ALLOC_IN_RC(int_reg));
4833 match(reg);
4835 op_cost(100);
4836 format %{ "[$reg]" %}
4837 interface(MEMORY_INTER) %{
4838 base($reg);
4839 index(0x4);
4840 scale(0x0);
4841 disp(0x0);
4842 %}
4843 %}
4845 // Indirect Memory Plus Short Offset Operand
4846 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4847 %{
4848 match(AddP reg off);
4850 op_cost(100);
4851 format %{ "[$reg + $off]" %}
4852 interface(MEMORY_INTER) %{
4853 base($reg);
4854 index(0x4);
4855 scale(0x0);
4856 disp($off);
4857 %}
4858 %}
4860 // Indirect Memory Plus Long Offset Operand
4861 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4862 %{
4863 match(AddP reg off);
4865 op_cost(100);
4866 format %{ "[$reg + $off]" %}
4867 interface(MEMORY_INTER) %{
4868 base($reg);
4869 index(0x4);
4870 scale(0x0);
4871 disp($off);
4872 %}
4873 %}
4875 // Indirect Memory Plus Index Register Plus Offset Operand
4876 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4877 %{
4878 match(AddP (AddP reg ireg) off);
4880 op_cost(100);
4881 format %{"[$reg + $off + $ireg]" %}
4882 interface(MEMORY_INTER) %{
4883 base($reg);
4884 index($ireg);
4885 scale(0x0);
4886 disp($off);
4887 %}
4888 %}
4890 // Indirect Memory Times Scale Plus Index Register
4891 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4892 %{
4893 match(AddP reg (LShiftI ireg scale));
4895 op_cost(100);
4896 format %{"[$reg + $ireg << $scale]" %}
4897 interface(MEMORY_INTER) %{
4898 base($reg);
4899 index($ireg);
4900 scale($scale);
4901 disp(0x0);
4902 %}
4903 %}
4905 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4906 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4907 %{
4908 match(AddP (AddP reg (LShiftI ireg scale)) off);
4910 op_cost(100);
4911 format %{"[$reg + $off + $ireg << $scale]" %}
4912 interface(MEMORY_INTER) %{
4913 base($reg);
4914 index($ireg);
4915 scale($scale);
4916 disp($off);
4917 %}
4918 %}
4920 //----------Conditional Branch Operands----------------------------------------
4921 // Comparison Op - This is the operation of the comparison, and is limited to
4922 // the following set of codes:
4923 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4924 //
4925 // Other attributes of the comparison, such as unsignedness, are specified
4926 // by the comparison instruction that sets a condition code flags register.
4927 // That result is represented by a flags operand whose subtype is appropriate
4928 // to the unsignedness (etc.) of the comparison.
4929 //
4930 // Later, the instruction which matches both the Comparison Op (a Bool) and
4931 // the flags (produced by the Cmp) specifies the coding of the comparison op
4932 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4934 // Comparision Code
4935 operand cmpOp() %{
4936 match(Bool);
4938 format %{ "" %}
4939 interface(COND_INTER) %{
4940 equal(0x4, "e");
4941 not_equal(0x5, "ne");
4942 less(0xC, "l");
4943 greater_equal(0xD, "ge");
4944 less_equal(0xE, "le");
4945 greater(0xF, "g");
4946 overflow(0x0, "o");
4947 no_overflow(0x1, "no");
4948 %}
4949 %}
4951 // Comparison Code, unsigned compare. Used by FP also, with
4952 // C2 (unordered) turned into GT or LT already. The other bits
4953 // C0 and C3 are turned into Carry & Zero flags.
4954 operand cmpOpU() %{
4955 match(Bool);
4957 format %{ "" %}
4958 interface(COND_INTER) %{
4959 equal(0x4, "e");
4960 not_equal(0x5, "ne");
4961 less(0x2, "b");
4962 greater_equal(0x3, "nb");
4963 less_equal(0x6, "be");
4964 greater(0x7, "nbe");
4965 overflow(0x0, "o");
4966 no_overflow(0x1, "no");
4967 %}
4968 %}
4970 // Floating comparisons that don't require any fixup for the unordered case
4971 operand cmpOpUCF() %{
4972 match(Bool);
4973 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4974 n->as_Bool()->_test._test == BoolTest::ge ||
4975 n->as_Bool()->_test._test == BoolTest::le ||
4976 n->as_Bool()->_test._test == BoolTest::gt);
4977 format %{ "" %}
4978 interface(COND_INTER) %{
4979 equal(0x4, "e");
4980 not_equal(0x5, "ne");
4981 less(0x2, "b");
4982 greater_equal(0x3, "nb");
4983 less_equal(0x6, "be");
4984 greater(0x7, "nbe");
4985 overflow(0x0, "o");
4986 no_overflow(0x1, "no");
4987 %}
4988 %}
4991 // Floating comparisons that can be fixed up with extra conditional jumps
4992 operand cmpOpUCF2() %{
4993 match(Bool);
4994 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4995 n->as_Bool()->_test._test == BoolTest::eq);
4996 format %{ "" %}
4997 interface(COND_INTER) %{
4998 equal(0x4, "e");
4999 not_equal(0x5, "ne");
5000 less(0x2, "b");
5001 greater_equal(0x3, "nb");
5002 less_equal(0x6, "be");
5003 greater(0x7, "nbe");
5004 overflow(0x0, "o");
5005 no_overflow(0x1, "no");
5006 %}
5007 %}
5009 // Comparison Code for FP conditional move
5010 operand cmpOp_fcmov() %{
5011 match(Bool);
5013 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
5014 n->as_Bool()->_test._test != BoolTest::no_overflow);
5015 format %{ "" %}
5016 interface(COND_INTER) %{
5017 equal (0x0C8);
5018 not_equal (0x1C8);
5019 less (0x0C0);
5020 greater_equal(0x1C0);
5021 less_equal (0x0D0);
5022 greater (0x1D0);
5023 overflow(0x0, "o"); // not really supported by the instruction
5024 no_overflow(0x1, "no"); // not really supported by the instruction
5025 %}
5026 %}
5028 // Comparision Code used in long compares
5029 operand cmpOp_commute() %{
5030 match(Bool);
5032 format %{ "" %}
5033 interface(COND_INTER) %{
5034 equal(0x4, "e");
5035 not_equal(0x5, "ne");
5036 less(0xF, "g");
5037 greater_equal(0xE, "le");
5038 less_equal(0xD, "ge");
5039 greater(0xC, "l");
5040 overflow(0x0, "o");
5041 no_overflow(0x1, "no");
5042 %}
5043 %}
5045 //----------OPERAND CLASSES----------------------------------------------------
5046 // Operand Classes are groups of operands that are used as to simplify
5047 // instruction definitions by not requiring the AD writer to specify separate
5048 // instructions for every form of operand when the instruction accepts
5049 // multiple operand types with the same basic encoding and format. The classic
5050 // case of this is memory operands.
5052 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5053 indIndex, indIndexScale, indIndexScaleOffset);
5055 // Long memory operations are encoded in 2 instructions and a +4 offset.
5056 // This means some kind of offset is always required and you cannot use
5057 // an oop as the offset (done when working on static globals).
5058 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5059 indIndex, indIndexScale, indIndexScaleOffset);
5062 //----------PIPELINE-----------------------------------------------------------
5063 // Rules which define the behavior of the target architectures pipeline.
5064 pipeline %{
5066 //----------ATTRIBUTES---------------------------------------------------------
5067 attributes %{
5068 variable_size_instructions; // Fixed size instructions
5069 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5070 instruction_unit_size = 1; // An instruction is 1 bytes long
5071 instruction_fetch_unit_size = 16; // The processor fetches one line
5072 instruction_fetch_units = 1; // of 16 bytes
5074 // List of nop instructions
5075 nops( MachNop );
5076 %}
5078 //----------RESOURCES----------------------------------------------------------
5079 // Resources are the functional units available to the machine
5081 // Generic P2/P3 pipeline
5082 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5083 // 3 instructions decoded per cycle.
5084 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5085 // 2 ALU op, only ALU0 handles mul/div instructions.
5086 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5087 MS0, MS1, MEM = MS0 | MS1,
5088 BR, FPU,
5089 ALU0, ALU1, ALU = ALU0 | ALU1 );
5091 //----------PIPELINE DESCRIPTION-----------------------------------------------
5092 // Pipeline Description specifies the stages in the machine's pipeline
5094 // Generic P2/P3 pipeline
5095 pipe_desc(S0, S1, S2, S3, S4, S5);
5097 //----------PIPELINE CLASSES---------------------------------------------------
5098 // Pipeline Classes describe the stages in which input and output are
5099 // referenced by the hardware pipeline.
5101 // Naming convention: ialu or fpu
5102 // Then: _reg
5103 // Then: _reg if there is a 2nd register
5104 // Then: _long if it's a pair of instructions implementing a long
5105 // Then: _fat if it requires the big decoder
5106 // Or: _mem if it requires the big decoder and a memory unit.
5108 // Integer ALU reg operation
5109 pipe_class ialu_reg(rRegI dst) %{
5110 single_instruction;
5111 dst : S4(write);
5112 dst : S3(read);
5113 DECODE : S0; // any decoder
5114 ALU : S3; // any alu
5115 %}
5117 // Long ALU reg operation
5118 pipe_class ialu_reg_long(eRegL dst) %{
5119 instruction_count(2);
5120 dst : S4(write);
5121 dst : S3(read);
5122 DECODE : S0(2); // any 2 decoders
5123 ALU : S3(2); // both alus
5124 %}
5126 // Integer ALU reg operation using big decoder
5127 pipe_class ialu_reg_fat(rRegI dst) %{
5128 single_instruction;
5129 dst : S4(write);
5130 dst : S3(read);
5131 D0 : S0; // big decoder only
5132 ALU : S3; // any alu
5133 %}
5135 // Long ALU reg operation using big decoder
5136 pipe_class ialu_reg_long_fat(eRegL dst) %{
5137 instruction_count(2);
5138 dst : S4(write);
5139 dst : S3(read);
5140 D0 : S0(2); // big decoder only; twice
5141 ALU : S3(2); // any 2 alus
5142 %}
5144 // Integer ALU reg-reg operation
5145 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
5146 single_instruction;
5147 dst : S4(write);
5148 src : S3(read);
5149 DECODE : S0; // any decoder
5150 ALU : S3; // any alu
5151 %}
5153 // Long ALU reg-reg operation
5154 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5155 instruction_count(2);
5156 dst : S4(write);
5157 src : S3(read);
5158 DECODE : S0(2); // any 2 decoders
5159 ALU : S3(2); // both alus
5160 %}
5162 // Integer ALU reg-reg operation
5163 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
5164 single_instruction;
5165 dst : S4(write);
5166 src : S3(read);
5167 D0 : S0; // big decoder only
5168 ALU : S3; // any alu
5169 %}
5171 // Long ALU reg-reg operation
5172 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5173 instruction_count(2);
5174 dst : S4(write);
5175 src : S3(read);
5176 D0 : S0(2); // big decoder only; twice
5177 ALU : S3(2); // both alus
5178 %}
5180 // Integer ALU reg-mem operation
5181 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
5182 single_instruction;
5183 dst : S5(write);
5184 mem : S3(read);
5185 D0 : S0; // big decoder only
5186 ALU : S4; // any alu
5187 MEM : S3; // any mem
5188 %}
5190 // Long ALU reg-mem operation
5191 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5192 instruction_count(2);
5193 dst : S5(write);
5194 mem : S3(read);
5195 D0 : S0(2); // big decoder only; twice
5196 ALU : S4(2); // any 2 alus
5197 MEM : S3(2); // both mems
5198 %}
5200 // Integer mem operation (prefetch)
5201 pipe_class ialu_mem(memory mem)
5202 %{
5203 single_instruction;
5204 mem : S3(read);
5205 D0 : S0; // big decoder only
5206 MEM : S3; // any mem
5207 %}
5209 // Integer Store to Memory
5210 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
5211 single_instruction;
5212 mem : S3(read);
5213 src : S5(read);
5214 D0 : S0; // big decoder only
5215 ALU : S4; // any alu
5216 MEM : S3;
5217 %}
5219 // Long Store to Memory
5220 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5221 instruction_count(2);
5222 mem : S3(read);
5223 src : S5(read);
5224 D0 : S0(2); // big decoder only; twice
5225 ALU : S4(2); // any 2 alus
5226 MEM : S3(2); // Both mems
5227 %}
5229 // Integer Store to Memory
5230 pipe_class ialu_mem_imm(memory mem) %{
5231 single_instruction;
5232 mem : S3(read);
5233 D0 : S0; // big decoder only
5234 ALU : S4; // any alu
5235 MEM : S3;
5236 %}
5238 // Integer ALU0 reg-reg operation
5239 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
5240 single_instruction;
5241 dst : S4(write);
5242 src : S3(read);
5243 D0 : S0; // Big decoder only
5244 ALU0 : S3; // only alu0
5245 %}
5247 // Integer ALU0 reg-mem operation
5248 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
5249 single_instruction;
5250 dst : S5(write);
5251 mem : S3(read);
5252 D0 : S0; // big decoder only
5253 ALU0 : S4; // ALU0 only
5254 MEM : S3; // any mem
5255 %}
5257 // Integer ALU reg-reg operation
5258 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
5259 single_instruction;
5260 cr : S4(write);
5261 src1 : S3(read);
5262 src2 : S3(read);
5263 DECODE : S0; // any decoder
5264 ALU : S3; // any alu
5265 %}
5267 // Integer ALU reg-imm operation
5268 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
5269 single_instruction;
5270 cr : S4(write);
5271 src1 : S3(read);
5272 DECODE : S0; // any decoder
5273 ALU : S3; // any alu
5274 %}
5276 // Integer ALU reg-mem operation
5277 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
5278 single_instruction;
5279 cr : S4(write);
5280 src1 : S3(read);
5281 src2 : S3(read);
5282 D0 : S0; // big decoder only
5283 ALU : S4; // any alu
5284 MEM : S3;
5285 %}
5287 // Conditional move reg-reg
5288 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
5289 instruction_count(4);
5290 y : S4(read);
5291 q : S3(read);
5292 p : S3(read);
5293 DECODE : S0(4); // any decoder
5294 %}
5296 // Conditional move reg-reg
5297 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
5298 single_instruction;
5299 dst : S4(write);
5300 src : S3(read);
5301 cr : S3(read);
5302 DECODE : S0; // any decoder
5303 %}
5305 // Conditional move reg-mem
5306 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
5307 single_instruction;
5308 dst : S4(write);
5309 src : S3(read);
5310 cr : S3(read);
5311 DECODE : S0; // any decoder
5312 MEM : S3;
5313 %}
5315 // Conditional move reg-reg long
5316 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5317 single_instruction;
5318 dst : S4(write);
5319 src : S3(read);
5320 cr : S3(read);
5321 DECODE : S0(2); // any 2 decoders
5322 %}
5324 // Conditional move double reg-reg
5325 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5326 single_instruction;
5327 dst : S4(write);
5328 src : S3(read);
5329 cr : S3(read);
5330 DECODE : S0; // any decoder
5331 %}
5333 // Float reg-reg operation
5334 pipe_class fpu_reg(regDPR dst) %{
5335 instruction_count(2);
5336 dst : S3(read);
5337 DECODE : S0(2); // any 2 decoders
5338 FPU : S3;
5339 %}
5341 // Float reg-reg operation
5342 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5343 instruction_count(2);
5344 dst : S4(write);
5345 src : S3(read);
5346 DECODE : S0(2); // any 2 decoders
5347 FPU : S3;
5348 %}
5350 // Float reg-reg operation
5351 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5352 instruction_count(3);
5353 dst : S4(write);
5354 src1 : S3(read);
5355 src2 : S3(read);
5356 DECODE : S0(3); // any 3 decoders
5357 FPU : S3(2);
5358 %}
5360 // Float reg-reg operation
5361 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5362 instruction_count(4);
5363 dst : S4(write);
5364 src1 : S3(read);
5365 src2 : S3(read);
5366 src3 : S3(read);
5367 DECODE : S0(4); // any 3 decoders
5368 FPU : S3(2);
5369 %}
5371 // Float reg-reg operation
5372 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5373 instruction_count(4);
5374 dst : S4(write);
5375 src1 : S3(read);
5376 src2 : S3(read);
5377 src3 : S3(read);
5378 DECODE : S1(3); // any 3 decoders
5379 D0 : S0; // Big decoder only
5380 FPU : S3(2);
5381 MEM : S3;
5382 %}
5384 // Float reg-mem operation
5385 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5386 instruction_count(2);
5387 dst : S5(write);
5388 mem : S3(read);
5389 D0 : S0; // big decoder only
5390 DECODE : S1; // any decoder for FPU POP
5391 FPU : S4;
5392 MEM : S3; // any mem
5393 %}
5395 // Float reg-mem operation
5396 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5397 instruction_count(3);
5398 dst : S5(write);
5399 src1 : S3(read);
5400 mem : S3(read);
5401 D0 : S0; // big decoder only
5402 DECODE : S1(2); // any decoder for FPU POP
5403 FPU : S4;
5404 MEM : S3; // any mem
5405 %}
5407 // Float mem-reg operation
5408 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5409 instruction_count(2);
5410 src : S5(read);
5411 mem : S3(read);
5412 DECODE : S0; // any decoder for FPU PUSH
5413 D0 : S1; // big decoder only
5414 FPU : S4;
5415 MEM : S3; // any mem
5416 %}
5418 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5419 instruction_count(3);
5420 src1 : S3(read);
5421 src2 : S3(read);
5422 mem : S3(read);
5423 DECODE : S0(2); // any decoder for FPU PUSH
5424 D0 : S1; // big decoder only
5425 FPU : S4;
5426 MEM : S3; // any mem
5427 %}
5429 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5430 instruction_count(3);
5431 src1 : S3(read);
5432 src2 : S3(read);
5433 mem : S4(read);
5434 DECODE : S0; // any decoder for FPU PUSH
5435 D0 : S0(2); // big decoder only
5436 FPU : S4;
5437 MEM : S3(2); // any mem
5438 %}
5440 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5441 instruction_count(2);
5442 src1 : S3(read);
5443 dst : S4(read);
5444 D0 : S0(2); // big decoder only
5445 MEM : S3(2); // any mem
5446 %}
5448 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5449 instruction_count(3);
5450 src1 : S3(read);
5451 src2 : S3(read);
5452 dst : S4(read);
5453 D0 : S0(3); // big decoder only
5454 FPU : S4;
5455 MEM : S3(3); // any mem
5456 %}
5458 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5459 instruction_count(3);
5460 src1 : S4(read);
5461 mem : S4(read);
5462 DECODE : S0; // any decoder for FPU PUSH
5463 D0 : S0(2); // big decoder only
5464 FPU : S4;
5465 MEM : S3(2); // any mem
5466 %}
5468 // Float load constant
5469 pipe_class fpu_reg_con(regDPR dst) %{
5470 instruction_count(2);
5471 dst : S5(write);
5472 D0 : S0; // big decoder only for the load
5473 DECODE : S1; // any decoder for FPU POP
5474 FPU : S4;
5475 MEM : S3; // any mem
5476 %}
5478 // Float load constant
5479 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5480 instruction_count(3);
5481 dst : S5(write);
5482 src : S3(read);
5483 D0 : S0; // big decoder only for the load
5484 DECODE : S1(2); // any decoder for FPU POP
5485 FPU : S4;
5486 MEM : S3; // any mem
5487 %}
5489 // UnConditional branch
5490 pipe_class pipe_jmp( label labl ) %{
5491 single_instruction;
5492 BR : S3;
5493 %}
5495 // Conditional branch
5496 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5497 single_instruction;
5498 cr : S1(read);
5499 BR : S3;
5500 %}
5502 // Allocation idiom
5503 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5504 instruction_count(1); force_serialization;
5505 fixed_latency(6);
5506 heap_ptr : S3(read);
5507 DECODE : S0(3);
5508 D0 : S2;
5509 MEM : S3;
5510 ALU : S3(2);
5511 dst : S5(write);
5512 BR : S5;
5513 %}
5515 // Generic big/slow expanded idiom
5516 pipe_class pipe_slow( ) %{
5517 instruction_count(10); multiple_bundles; force_serialization;
5518 fixed_latency(100);
5519 D0 : S0(2);
5520 MEM : S3(2);
5521 %}
5523 // The real do-nothing guy
5524 pipe_class empty( ) %{
5525 instruction_count(0);
5526 %}
5528 // Define the class for the Nop node
5529 define %{
5530 MachNop = empty;
5531 %}
5533 %}
5535 //----------INSTRUCTIONS-------------------------------------------------------
5536 //
5537 // match -- States which machine-independent subtree may be replaced
5538 // by this instruction.
5539 // ins_cost -- The estimated cost of this instruction is used by instruction
5540 // selection to identify a minimum cost tree of machine
5541 // instructions that matches a tree of machine-independent
5542 // instructions.
5543 // format -- A string providing the disassembly for this instruction.
5544 // The value of an instruction's operand may be inserted
5545 // by referring to it with a '$' prefix.
5546 // opcode -- Three instruction opcodes may be provided. These are referred
5547 // to within an encode class as $primary, $secondary, and $tertiary
5548 // respectively. The primary opcode is commonly used to
5549 // indicate the type of machine instruction, while secondary
5550 // and tertiary are often used for prefix options or addressing
5551 // modes.
5552 // ins_encode -- A list of encode classes with parameters. The encode class
5553 // name must have been defined in an 'enc_class' specification
5554 // in the encode section of the architecture description.
5556 //----------BSWAP-Instruction--------------------------------------------------
5557 instruct bytes_reverse_int(rRegI dst) %{
5558 match(Set dst (ReverseBytesI dst));
5560 format %{ "BSWAP $dst" %}
5561 opcode(0x0F, 0xC8);
5562 ins_encode( OpcP, OpcSReg(dst) );
5563 ins_pipe( ialu_reg );
5564 %}
5566 instruct bytes_reverse_long(eRegL dst) %{
5567 match(Set dst (ReverseBytesL dst));
5569 format %{ "BSWAP $dst.lo\n\t"
5570 "BSWAP $dst.hi\n\t"
5571 "XCHG $dst.lo $dst.hi" %}
5573 ins_cost(125);
5574 ins_encode( bswap_long_bytes(dst) );
5575 ins_pipe( ialu_reg_reg);
5576 %}
5578 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5579 match(Set dst (ReverseBytesUS dst));
5580 effect(KILL cr);
5582 format %{ "BSWAP $dst\n\t"
5583 "SHR $dst,16\n\t" %}
5584 ins_encode %{
5585 __ bswapl($dst$$Register);
5586 __ shrl($dst$$Register, 16);
5587 %}
5588 ins_pipe( ialu_reg );
5589 %}
5591 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5592 match(Set dst (ReverseBytesS dst));
5593 effect(KILL cr);
5595 format %{ "BSWAP $dst\n\t"
5596 "SAR $dst,16\n\t" %}
5597 ins_encode %{
5598 __ bswapl($dst$$Register);
5599 __ sarl($dst$$Register, 16);
5600 %}
5601 ins_pipe( ialu_reg );
5602 %}
5605 //---------- Zeros Count Instructions ------------------------------------------
5607 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5608 predicate(UseCountLeadingZerosInstruction);
5609 match(Set dst (CountLeadingZerosI src));
5610 effect(KILL cr);
5612 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5613 ins_encode %{
5614 __ lzcntl($dst$$Register, $src$$Register);
5615 %}
5616 ins_pipe(ialu_reg);
5617 %}
5619 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5620 predicate(!UseCountLeadingZerosInstruction);
5621 match(Set dst (CountLeadingZerosI src));
5622 effect(KILL cr);
5624 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5625 "JNZ skip\n\t"
5626 "MOV $dst, -1\n"
5627 "skip:\n\t"
5628 "NEG $dst\n\t"
5629 "ADD $dst, 31" %}
5630 ins_encode %{
5631 Register Rdst = $dst$$Register;
5632 Register Rsrc = $src$$Register;
5633 Label skip;
5634 __ bsrl(Rdst, Rsrc);
5635 __ jccb(Assembler::notZero, skip);
5636 __ movl(Rdst, -1);
5637 __ bind(skip);
5638 __ negl(Rdst);
5639 __ addl(Rdst, BitsPerInt - 1);
5640 %}
5641 ins_pipe(ialu_reg);
5642 %}
5644 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5645 predicate(UseCountLeadingZerosInstruction);
5646 match(Set dst (CountLeadingZerosL src));
5647 effect(TEMP dst, KILL cr);
5649 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5650 "JNC done\n\t"
5651 "LZCNT $dst, $src.lo\n\t"
5652 "ADD $dst, 32\n"
5653 "done:" %}
5654 ins_encode %{
5655 Register Rdst = $dst$$Register;
5656 Register Rsrc = $src$$Register;
5657 Label done;
5658 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5659 __ jccb(Assembler::carryClear, done);
5660 __ lzcntl(Rdst, Rsrc);
5661 __ addl(Rdst, BitsPerInt);
5662 __ bind(done);
5663 %}
5664 ins_pipe(ialu_reg);
5665 %}
5667 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5668 predicate(!UseCountLeadingZerosInstruction);
5669 match(Set dst (CountLeadingZerosL src));
5670 effect(TEMP dst, KILL cr);
5672 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5673 "JZ msw_is_zero\n\t"
5674 "ADD $dst, 32\n\t"
5675 "JMP not_zero\n"
5676 "msw_is_zero:\n\t"
5677 "BSR $dst, $src.lo\n\t"
5678 "JNZ not_zero\n\t"
5679 "MOV $dst, -1\n"
5680 "not_zero:\n\t"
5681 "NEG $dst\n\t"
5682 "ADD $dst, 63\n" %}
5683 ins_encode %{
5684 Register Rdst = $dst$$Register;
5685 Register Rsrc = $src$$Register;
5686 Label msw_is_zero;
5687 Label not_zero;
5688 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5689 __ jccb(Assembler::zero, msw_is_zero);
5690 __ addl(Rdst, BitsPerInt);
5691 __ jmpb(not_zero);
5692 __ bind(msw_is_zero);
5693 __ bsrl(Rdst, Rsrc);
5694 __ jccb(Assembler::notZero, not_zero);
5695 __ movl(Rdst, -1);
5696 __ bind(not_zero);
5697 __ negl(Rdst);
5698 __ addl(Rdst, BitsPerLong - 1);
5699 %}
5700 ins_pipe(ialu_reg);
5701 %}
5703 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5704 match(Set dst (CountTrailingZerosI src));
5705 effect(KILL cr);
5707 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5708 "JNZ done\n\t"
5709 "MOV $dst, 32\n"
5710 "done:" %}
5711 ins_encode %{
5712 Register Rdst = $dst$$Register;
5713 Label done;
5714 __ bsfl(Rdst, $src$$Register);
5715 __ jccb(Assembler::notZero, done);
5716 __ movl(Rdst, BitsPerInt);
5717 __ bind(done);
5718 %}
5719 ins_pipe(ialu_reg);
5720 %}
5722 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5723 match(Set dst (CountTrailingZerosL src));
5724 effect(TEMP dst, KILL cr);
5726 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5727 "JNZ done\n\t"
5728 "BSF $dst, $src.hi\n\t"
5729 "JNZ msw_not_zero\n\t"
5730 "MOV $dst, 32\n"
5731 "msw_not_zero:\n\t"
5732 "ADD $dst, 32\n"
5733 "done:" %}
5734 ins_encode %{
5735 Register Rdst = $dst$$Register;
5736 Register Rsrc = $src$$Register;
5737 Label msw_not_zero;
5738 Label done;
5739 __ bsfl(Rdst, Rsrc);
5740 __ jccb(Assembler::notZero, done);
5741 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5742 __ jccb(Assembler::notZero, msw_not_zero);
5743 __ movl(Rdst, BitsPerInt);
5744 __ bind(msw_not_zero);
5745 __ addl(Rdst, BitsPerInt);
5746 __ bind(done);
5747 %}
5748 ins_pipe(ialu_reg);
5749 %}
5752 //---------- Population Count Instructions -------------------------------------
5754 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5755 predicate(UsePopCountInstruction);
5756 match(Set dst (PopCountI src));
5757 effect(KILL cr);
5759 format %{ "POPCNT $dst, $src" %}
5760 ins_encode %{
5761 __ popcntl($dst$$Register, $src$$Register);
5762 %}
5763 ins_pipe(ialu_reg);
5764 %}
5766 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5767 predicate(UsePopCountInstruction);
5768 match(Set dst (PopCountI (LoadI mem)));
5769 effect(KILL cr);
5771 format %{ "POPCNT $dst, $mem" %}
5772 ins_encode %{
5773 __ popcntl($dst$$Register, $mem$$Address);
5774 %}
5775 ins_pipe(ialu_reg);
5776 %}
5778 // Note: Long.bitCount(long) returns an int.
5779 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5780 predicate(UsePopCountInstruction);
5781 match(Set dst (PopCountL src));
5782 effect(KILL cr, TEMP tmp, TEMP dst);
5784 format %{ "POPCNT $dst, $src.lo\n\t"
5785 "POPCNT $tmp, $src.hi\n\t"
5786 "ADD $dst, $tmp" %}
5787 ins_encode %{
5788 __ popcntl($dst$$Register, $src$$Register);
5789 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5790 __ addl($dst$$Register, $tmp$$Register);
5791 %}
5792 ins_pipe(ialu_reg);
5793 %}
5795 // Note: Long.bitCount(long) returns an int.
5796 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5797 predicate(UsePopCountInstruction);
5798 match(Set dst (PopCountL (LoadL mem)));
5799 effect(KILL cr, TEMP tmp, TEMP dst);
5801 format %{ "POPCNT $dst, $mem\n\t"
5802 "POPCNT $tmp, $mem+4\n\t"
5803 "ADD $dst, $tmp" %}
5804 ins_encode %{
5805 //__ popcntl($dst$$Register, $mem$$Address$$first);
5806 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5807 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5808 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5809 __ addl($dst$$Register, $tmp$$Register);
5810 %}
5811 ins_pipe(ialu_reg);
5812 %}
5815 //----------Load/Store/Move Instructions---------------------------------------
5816 //----------Load Instructions--------------------------------------------------
5817 // Load Byte (8bit signed)
5818 instruct loadB(xRegI dst, memory mem) %{
5819 match(Set dst (LoadB mem));
5821 ins_cost(125);
5822 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5824 ins_encode %{
5825 __ movsbl($dst$$Register, $mem$$Address);
5826 %}
5828 ins_pipe(ialu_reg_mem);
5829 %}
5831 // Load Byte (8bit signed) into Long Register
5832 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5833 match(Set dst (ConvI2L (LoadB mem)));
5834 effect(KILL cr);
5836 ins_cost(375);
5837 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5838 "MOV $dst.hi,$dst.lo\n\t"
5839 "SAR $dst.hi,7" %}
5841 ins_encode %{
5842 __ movsbl($dst$$Register, $mem$$Address);
5843 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5844 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5845 %}
5847 ins_pipe(ialu_reg_mem);
5848 %}
5850 // Load Unsigned Byte (8bit UNsigned)
5851 instruct loadUB(xRegI dst, memory mem) %{
5852 match(Set dst (LoadUB mem));
5854 ins_cost(125);
5855 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5857 ins_encode %{
5858 __ movzbl($dst$$Register, $mem$$Address);
5859 %}
5861 ins_pipe(ialu_reg_mem);
5862 %}
5864 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5865 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5866 match(Set dst (ConvI2L (LoadUB mem)));
5867 effect(KILL cr);
5869 ins_cost(250);
5870 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5871 "XOR $dst.hi,$dst.hi" %}
5873 ins_encode %{
5874 Register Rdst = $dst$$Register;
5875 __ movzbl(Rdst, $mem$$Address);
5876 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5877 %}
5879 ins_pipe(ialu_reg_mem);
5880 %}
5882 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5883 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5884 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5885 effect(KILL cr);
5887 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5888 "XOR $dst.hi,$dst.hi\n\t"
5889 "AND $dst.lo,$mask" %}
5890 ins_encode %{
5891 Register Rdst = $dst$$Register;
5892 __ movzbl(Rdst, $mem$$Address);
5893 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5894 __ andl(Rdst, $mask$$constant);
5895 %}
5896 ins_pipe(ialu_reg_mem);
5897 %}
5899 // Load Short (16bit signed)
5900 instruct loadS(rRegI dst, memory mem) %{
5901 match(Set dst (LoadS mem));
5903 ins_cost(125);
5904 format %{ "MOVSX $dst,$mem\t# short" %}
5906 ins_encode %{
5907 __ movswl($dst$$Register, $mem$$Address);
5908 %}
5910 ins_pipe(ialu_reg_mem);
5911 %}
5913 // Load Short (16 bit signed) to Byte (8 bit signed)
5914 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5915 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5917 ins_cost(125);
5918 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5919 ins_encode %{
5920 __ movsbl($dst$$Register, $mem$$Address);
5921 %}
5922 ins_pipe(ialu_reg_mem);
5923 %}
5925 // Load Short (16bit signed) into Long Register
5926 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5927 match(Set dst (ConvI2L (LoadS mem)));
5928 effect(KILL cr);
5930 ins_cost(375);
5931 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5932 "MOV $dst.hi,$dst.lo\n\t"
5933 "SAR $dst.hi,15" %}
5935 ins_encode %{
5936 __ movswl($dst$$Register, $mem$$Address);
5937 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5938 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5939 %}
5941 ins_pipe(ialu_reg_mem);
5942 %}
5944 // Load Unsigned Short/Char (16bit unsigned)
5945 instruct loadUS(rRegI dst, memory mem) %{
5946 match(Set dst (LoadUS mem));
5948 ins_cost(125);
5949 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5951 ins_encode %{
5952 __ movzwl($dst$$Register, $mem$$Address);
5953 %}
5955 ins_pipe(ialu_reg_mem);
5956 %}
5958 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5959 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5960 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5962 ins_cost(125);
5963 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5964 ins_encode %{
5965 __ movsbl($dst$$Register, $mem$$Address);
5966 %}
5967 ins_pipe(ialu_reg_mem);
5968 %}
5970 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5971 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5972 match(Set dst (ConvI2L (LoadUS mem)));
5973 effect(KILL cr);
5975 ins_cost(250);
5976 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
5977 "XOR $dst.hi,$dst.hi" %}
5979 ins_encode %{
5980 __ movzwl($dst$$Register, $mem$$Address);
5981 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5982 %}
5984 ins_pipe(ialu_reg_mem);
5985 %}
5987 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5988 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5989 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5990 effect(KILL cr);
5992 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
5993 "XOR $dst.hi,$dst.hi" %}
5994 ins_encode %{
5995 Register Rdst = $dst$$Register;
5996 __ movzbl(Rdst, $mem$$Address);
5997 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5998 %}
5999 ins_pipe(ialu_reg_mem);
6000 %}
6002 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6003 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6004 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6005 effect(KILL cr);
6007 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6008 "XOR $dst.hi,$dst.hi\n\t"
6009 "AND $dst.lo,$mask" %}
6010 ins_encode %{
6011 Register Rdst = $dst$$Register;
6012 __ movzwl(Rdst, $mem$$Address);
6013 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6014 __ andl(Rdst, $mask$$constant);
6015 %}
6016 ins_pipe(ialu_reg_mem);
6017 %}
6019 // Load Integer
6020 instruct loadI(rRegI dst, memory mem) %{
6021 match(Set dst (LoadI mem));
6023 ins_cost(125);
6024 format %{ "MOV $dst,$mem\t# int" %}
6026 ins_encode %{
6027 __ movl($dst$$Register, $mem$$Address);
6028 %}
6030 ins_pipe(ialu_reg_mem);
6031 %}
6033 // Load Integer (32 bit signed) to Byte (8 bit signed)
6034 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6035 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6037 ins_cost(125);
6038 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6039 ins_encode %{
6040 __ movsbl($dst$$Register, $mem$$Address);
6041 %}
6042 ins_pipe(ialu_reg_mem);
6043 %}
6045 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6046 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
6047 match(Set dst (AndI (LoadI mem) mask));
6049 ins_cost(125);
6050 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6051 ins_encode %{
6052 __ movzbl($dst$$Register, $mem$$Address);
6053 %}
6054 ins_pipe(ialu_reg_mem);
6055 %}
6057 // Load Integer (32 bit signed) to Short (16 bit signed)
6058 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6059 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6061 ins_cost(125);
6062 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6063 ins_encode %{
6064 __ movswl($dst$$Register, $mem$$Address);
6065 %}
6066 ins_pipe(ialu_reg_mem);
6067 %}
6069 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6070 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6071 match(Set dst (AndI (LoadI mem) mask));
6073 ins_cost(125);
6074 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6075 ins_encode %{
6076 __ movzwl($dst$$Register, $mem$$Address);
6077 %}
6078 ins_pipe(ialu_reg_mem);
6079 %}
6081 // Load Integer into Long Register
6082 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6083 match(Set dst (ConvI2L (LoadI mem)));
6084 effect(KILL cr);
6086 ins_cost(375);
6087 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6088 "MOV $dst.hi,$dst.lo\n\t"
6089 "SAR $dst.hi,31" %}
6091 ins_encode %{
6092 __ movl($dst$$Register, $mem$$Address);
6093 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6094 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6095 %}
6097 ins_pipe(ialu_reg_mem);
6098 %}
6100 // Load Integer with mask 0xFF into Long Register
6101 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6102 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6103 effect(KILL cr);
6105 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6106 "XOR $dst.hi,$dst.hi" %}
6107 ins_encode %{
6108 Register Rdst = $dst$$Register;
6109 __ movzbl(Rdst, $mem$$Address);
6110 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6111 %}
6112 ins_pipe(ialu_reg_mem);
6113 %}
6115 // Load Integer with mask 0xFFFF into Long Register
6116 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6117 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6118 effect(KILL cr);
6120 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6121 "XOR $dst.hi,$dst.hi" %}
6122 ins_encode %{
6123 Register Rdst = $dst$$Register;
6124 __ movzwl(Rdst, $mem$$Address);
6125 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6126 %}
6127 ins_pipe(ialu_reg_mem);
6128 %}
6130 // Load Integer with 32-bit mask into Long Register
6131 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6132 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6133 effect(KILL cr);
6135 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6136 "XOR $dst.hi,$dst.hi\n\t"
6137 "AND $dst.lo,$mask" %}
6138 ins_encode %{
6139 Register Rdst = $dst$$Register;
6140 __ movl(Rdst, $mem$$Address);
6141 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6142 __ andl(Rdst, $mask$$constant);
6143 %}
6144 ins_pipe(ialu_reg_mem);
6145 %}
6147 // Load Unsigned Integer into Long Register
6148 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{
6149 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
6150 effect(KILL cr);
6152 ins_cost(250);
6153 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6154 "XOR $dst.hi,$dst.hi" %}
6156 ins_encode %{
6157 __ movl($dst$$Register, $mem$$Address);
6158 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6159 %}
6161 ins_pipe(ialu_reg_mem);
6162 %}
6164 // Load Long. Cannot clobber address while loading, so restrict address
6165 // register to ESI
6166 instruct loadL(eRegL dst, load_long_memory mem) %{
6167 predicate(!((LoadLNode*)n)->require_atomic_access());
6168 match(Set dst (LoadL mem));
6170 ins_cost(250);
6171 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6172 "MOV $dst.hi,$mem+4" %}
6174 ins_encode %{
6175 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
6176 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
6177 __ movl($dst$$Register, Amemlo);
6178 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6179 %}
6181 ins_pipe(ialu_reg_long_mem);
6182 %}
6184 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6185 // then store it down to the stack and reload on the int
6186 // side.
6187 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6188 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6189 match(Set dst (LoadL mem));
6191 ins_cost(200);
6192 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6193 "FISTp $dst" %}
6194 ins_encode(enc_loadL_volatile(mem,dst));
6195 ins_pipe( fpu_reg_mem );
6196 %}
6198 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6199 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6200 match(Set dst (LoadL mem));
6201 effect(TEMP tmp);
6202 ins_cost(180);
6203 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6204 "MOVSD $dst,$tmp" %}
6205 ins_encode %{
6206 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6207 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6208 %}
6209 ins_pipe( pipe_slow );
6210 %}
6212 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6213 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6214 match(Set dst (LoadL mem));
6215 effect(TEMP tmp);
6216 ins_cost(160);
6217 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6218 "MOVD $dst.lo,$tmp\n\t"
6219 "PSRLQ $tmp,32\n\t"
6220 "MOVD $dst.hi,$tmp" %}
6221 ins_encode %{
6222 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6223 __ movdl($dst$$Register, $tmp$$XMMRegister);
6224 __ psrlq($tmp$$XMMRegister, 32);
6225 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6226 %}
6227 ins_pipe( pipe_slow );
6228 %}
6230 // Load Range
6231 instruct loadRange(rRegI dst, memory mem) %{
6232 match(Set dst (LoadRange mem));
6234 ins_cost(125);
6235 format %{ "MOV $dst,$mem" %}
6236 opcode(0x8B);
6237 ins_encode( OpcP, RegMem(dst,mem));
6238 ins_pipe( ialu_reg_mem );
6239 %}
6242 // Load Pointer
6243 instruct loadP(eRegP dst, memory mem) %{
6244 match(Set dst (LoadP mem));
6246 ins_cost(125);
6247 format %{ "MOV $dst,$mem" %}
6248 opcode(0x8B);
6249 ins_encode( OpcP, RegMem(dst,mem));
6250 ins_pipe( ialu_reg_mem );
6251 %}
6253 // Load Klass Pointer
6254 instruct loadKlass(eRegP dst, memory mem) %{
6255 match(Set dst (LoadKlass mem));
6257 ins_cost(125);
6258 format %{ "MOV $dst,$mem" %}
6259 opcode(0x8B);
6260 ins_encode( OpcP, RegMem(dst,mem));
6261 ins_pipe( ialu_reg_mem );
6262 %}
6264 // Load Double
6265 instruct loadDPR(regDPR dst, memory mem) %{
6266 predicate(UseSSE<=1);
6267 match(Set dst (LoadD mem));
6269 ins_cost(150);
6270 format %{ "FLD_D ST,$mem\n\t"
6271 "FSTP $dst" %}
6272 opcode(0xDD); /* DD /0 */
6273 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6274 Pop_Reg_DPR(dst) );
6275 ins_pipe( fpu_reg_mem );
6276 %}
6278 // Load Double to XMM
6279 instruct loadD(regD dst, memory mem) %{
6280 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6281 match(Set dst (LoadD mem));
6282 ins_cost(145);
6283 format %{ "MOVSD $dst,$mem" %}
6284 ins_encode %{
6285 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6286 %}
6287 ins_pipe( pipe_slow );
6288 %}
6290 instruct loadD_partial(regD dst, memory mem) %{
6291 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6292 match(Set dst (LoadD mem));
6293 ins_cost(145);
6294 format %{ "MOVLPD $dst,$mem" %}
6295 ins_encode %{
6296 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6297 %}
6298 ins_pipe( pipe_slow );
6299 %}
6301 // Load to XMM register (single-precision floating point)
6302 // MOVSS instruction
6303 instruct loadF(regF dst, memory mem) %{
6304 predicate(UseSSE>=1);
6305 match(Set dst (LoadF mem));
6306 ins_cost(145);
6307 format %{ "MOVSS $dst,$mem" %}
6308 ins_encode %{
6309 __ movflt ($dst$$XMMRegister, $mem$$Address);
6310 %}
6311 ins_pipe( pipe_slow );
6312 %}
6314 // Load Float
6315 instruct loadFPR(regFPR dst, memory mem) %{
6316 predicate(UseSSE==0);
6317 match(Set dst (LoadF mem));
6319 ins_cost(150);
6320 format %{ "FLD_S ST,$mem\n\t"
6321 "FSTP $dst" %}
6322 opcode(0xD9); /* D9 /0 */
6323 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6324 Pop_Reg_FPR(dst) );
6325 ins_pipe( fpu_reg_mem );
6326 %}
6328 // Load Effective Address
6329 instruct leaP8(eRegP dst, indOffset8 mem) %{
6330 match(Set dst mem);
6332 ins_cost(110);
6333 format %{ "LEA $dst,$mem" %}
6334 opcode(0x8D);
6335 ins_encode( OpcP, RegMem(dst,mem));
6336 ins_pipe( ialu_reg_reg_fat );
6337 %}
6339 instruct leaP32(eRegP dst, indOffset32 mem) %{
6340 match(Set dst mem);
6342 ins_cost(110);
6343 format %{ "LEA $dst,$mem" %}
6344 opcode(0x8D);
6345 ins_encode( OpcP, RegMem(dst,mem));
6346 ins_pipe( ialu_reg_reg_fat );
6347 %}
6349 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6350 match(Set dst mem);
6352 ins_cost(110);
6353 format %{ "LEA $dst,$mem" %}
6354 opcode(0x8D);
6355 ins_encode( OpcP, RegMem(dst,mem));
6356 ins_pipe( ialu_reg_reg_fat );
6357 %}
6359 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6360 match(Set dst mem);
6362 ins_cost(110);
6363 format %{ "LEA $dst,$mem" %}
6364 opcode(0x8D);
6365 ins_encode( OpcP, RegMem(dst,mem));
6366 ins_pipe( ialu_reg_reg_fat );
6367 %}
6369 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6370 match(Set dst mem);
6372 ins_cost(110);
6373 format %{ "LEA $dst,$mem" %}
6374 opcode(0x8D);
6375 ins_encode( OpcP, RegMem(dst,mem));
6376 ins_pipe( ialu_reg_reg_fat );
6377 %}
6379 // Load Constant
6380 instruct loadConI(rRegI dst, immI src) %{
6381 match(Set dst src);
6383 format %{ "MOV $dst,$src" %}
6384 ins_encode( LdImmI(dst, src) );
6385 ins_pipe( ialu_reg_fat );
6386 %}
6388 // Load Constant zero
6389 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
6390 match(Set dst src);
6391 effect(KILL cr);
6393 ins_cost(50);
6394 format %{ "XOR $dst,$dst" %}
6395 opcode(0x33); /* + rd */
6396 ins_encode( OpcP, RegReg( dst, dst ) );
6397 ins_pipe( ialu_reg );
6398 %}
6400 instruct loadConP(eRegP dst, immP src) %{
6401 match(Set dst src);
6403 format %{ "MOV $dst,$src" %}
6404 opcode(0xB8); /* + rd */
6405 ins_encode( LdImmP(dst, src) );
6406 ins_pipe( ialu_reg_fat );
6407 %}
6409 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6410 match(Set dst src);
6411 effect(KILL cr);
6412 ins_cost(200);
6413 format %{ "MOV $dst.lo,$src.lo\n\t"
6414 "MOV $dst.hi,$src.hi" %}
6415 opcode(0xB8);
6416 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6417 ins_pipe( ialu_reg_long_fat );
6418 %}
6420 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6421 match(Set dst src);
6422 effect(KILL cr);
6423 ins_cost(150);
6424 format %{ "XOR $dst.lo,$dst.lo\n\t"
6425 "XOR $dst.hi,$dst.hi" %}
6426 opcode(0x33,0x33);
6427 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6428 ins_pipe( ialu_reg_long );
6429 %}
6431 // The instruction usage is guarded by predicate in operand immFPR().
6432 instruct loadConFPR(regFPR dst, immFPR con) %{
6433 match(Set dst con);
6434 ins_cost(125);
6435 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6436 "FSTP $dst" %}
6437 ins_encode %{
6438 __ fld_s($constantaddress($con));
6439 __ fstp_d($dst$$reg);
6440 %}
6441 ins_pipe(fpu_reg_con);
6442 %}
6444 // The instruction usage is guarded by predicate in operand immFPR0().
6445 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6446 match(Set dst con);
6447 ins_cost(125);
6448 format %{ "FLDZ ST\n\t"
6449 "FSTP $dst" %}
6450 ins_encode %{
6451 __ fldz();
6452 __ fstp_d($dst$$reg);
6453 %}
6454 ins_pipe(fpu_reg_con);
6455 %}
6457 // The instruction usage is guarded by predicate in operand immFPR1().
6458 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6459 match(Set dst con);
6460 ins_cost(125);
6461 format %{ "FLD1 ST\n\t"
6462 "FSTP $dst" %}
6463 ins_encode %{
6464 __ fld1();
6465 __ fstp_d($dst$$reg);
6466 %}
6467 ins_pipe(fpu_reg_con);
6468 %}
6470 // The instruction usage is guarded by predicate in operand immF().
6471 instruct loadConF(regF dst, immF con) %{
6472 match(Set dst con);
6473 ins_cost(125);
6474 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6475 ins_encode %{
6476 __ movflt($dst$$XMMRegister, $constantaddress($con));
6477 %}
6478 ins_pipe(pipe_slow);
6479 %}
6481 // The instruction usage is guarded by predicate in operand immF0().
6482 instruct loadConF0(regF dst, immF0 src) %{
6483 match(Set dst src);
6484 ins_cost(100);
6485 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6486 ins_encode %{
6487 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6488 %}
6489 ins_pipe(pipe_slow);
6490 %}
6492 // The instruction usage is guarded by predicate in operand immDPR().
6493 instruct loadConDPR(regDPR dst, immDPR con) %{
6494 match(Set dst con);
6495 ins_cost(125);
6497 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6498 "FSTP $dst" %}
6499 ins_encode %{
6500 __ fld_d($constantaddress($con));
6501 __ fstp_d($dst$$reg);
6502 %}
6503 ins_pipe(fpu_reg_con);
6504 %}
6506 // The instruction usage is guarded by predicate in operand immDPR0().
6507 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6508 match(Set dst con);
6509 ins_cost(125);
6511 format %{ "FLDZ ST\n\t"
6512 "FSTP $dst" %}
6513 ins_encode %{
6514 __ fldz();
6515 __ fstp_d($dst$$reg);
6516 %}
6517 ins_pipe(fpu_reg_con);
6518 %}
6520 // The instruction usage is guarded by predicate in operand immDPR1().
6521 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6522 match(Set dst con);
6523 ins_cost(125);
6525 format %{ "FLD1 ST\n\t"
6526 "FSTP $dst" %}
6527 ins_encode %{
6528 __ fld1();
6529 __ fstp_d($dst$$reg);
6530 %}
6531 ins_pipe(fpu_reg_con);
6532 %}
6534 // The instruction usage is guarded by predicate in operand immD().
6535 instruct loadConD(regD dst, immD con) %{
6536 match(Set dst con);
6537 ins_cost(125);
6538 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6539 ins_encode %{
6540 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6541 %}
6542 ins_pipe(pipe_slow);
6543 %}
6545 // The instruction usage is guarded by predicate in operand immD0().
6546 instruct loadConD0(regD dst, immD0 src) %{
6547 match(Set dst src);
6548 ins_cost(100);
6549 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6550 ins_encode %{
6551 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6552 %}
6553 ins_pipe( pipe_slow );
6554 %}
6556 // Load Stack Slot
6557 instruct loadSSI(rRegI dst, stackSlotI src) %{
6558 match(Set dst src);
6559 ins_cost(125);
6561 format %{ "MOV $dst,$src" %}
6562 opcode(0x8B);
6563 ins_encode( OpcP, RegMem(dst,src));
6564 ins_pipe( ialu_reg_mem );
6565 %}
6567 instruct loadSSL(eRegL dst, stackSlotL src) %{
6568 match(Set dst src);
6570 ins_cost(200);
6571 format %{ "MOV $dst,$src.lo\n\t"
6572 "MOV $dst+4,$src.hi" %}
6573 opcode(0x8B, 0x8B);
6574 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6575 ins_pipe( ialu_mem_long_reg );
6576 %}
6578 // Load Stack Slot
6579 instruct loadSSP(eRegP dst, stackSlotP src) %{
6580 match(Set dst src);
6581 ins_cost(125);
6583 format %{ "MOV $dst,$src" %}
6584 opcode(0x8B);
6585 ins_encode( OpcP, RegMem(dst,src));
6586 ins_pipe( ialu_reg_mem );
6587 %}
6589 // Load Stack Slot
6590 instruct loadSSF(regFPR dst, stackSlotF src) %{
6591 match(Set dst src);
6592 ins_cost(125);
6594 format %{ "FLD_S $src\n\t"
6595 "FSTP $dst" %}
6596 opcode(0xD9); /* D9 /0, FLD m32real */
6597 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6598 Pop_Reg_FPR(dst) );
6599 ins_pipe( fpu_reg_mem );
6600 %}
6602 // Load Stack Slot
6603 instruct loadSSD(regDPR dst, stackSlotD src) %{
6604 match(Set dst src);
6605 ins_cost(125);
6607 format %{ "FLD_D $src\n\t"
6608 "FSTP $dst" %}
6609 opcode(0xDD); /* DD /0, FLD m64real */
6610 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6611 Pop_Reg_DPR(dst) );
6612 ins_pipe( fpu_reg_mem );
6613 %}
6615 // Prefetch instructions.
6616 // Must be safe to execute with invalid address (cannot fault).
6618 instruct prefetchr0( memory mem ) %{
6619 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6620 match(PrefetchRead mem);
6621 ins_cost(0);
6622 size(0);
6623 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6624 ins_encode();
6625 ins_pipe(empty);
6626 %}
6628 instruct prefetchr( memory mem ) %{
6629 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6630 match(PrefetchRead mem);
6631 ins_cost(100);
6633 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6634 ins_encode %{
6635 __ prefetchr($mem$$Address);
6636 %}
6637 ins_pipe(ialu_mem);
6638 %}
6640 instruct prefetchrNTA( memory mem ) %{
6641 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6642 match(PrefetchRead mem);
6643 ins_cost(100);
6645 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6646 ins_encode %{
6647 __ prefetchnta($mem$$Address);
6648 %}
6649 ins_pipe(ialu_mem);
6650 %}
6652 instruct prefetchrT0( memory mem ) %{
6653 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6654 match(PrefetchRead mem);
6655 ins_cost(100);
6657 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6658 ins_encode %{
6659 __ prefetcht0($mem$$Address);
6660 %}
6661 ins_pipe(ialu_mem);
6662 %}
6664 instruct prefetchrT2( memory mem ) %{
6665 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6666 match(PrefetchRead mem);
6667 ins_cost(100);
6669 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6670 ins_encode %{
6671 __ prefetcht2($mem$$Address);
6672 %}
6673 ins_pipe(ialu_mem);
6674 %}
6676 instruct prefetchw0( memory mem ) %{
6677 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6678 match(PrefetchWrite mem);
6679 ins_cost(0);
6680 size(0);
6681 format %{ "Prefetch (non-SSE is empty encoding)" %}
6682 ins_encode();
6683 ins_pipe(empty);
6684 %}
6686 instruct prefetchw( memory mem ) %{
6687 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6688 match( PrefetchWrite mem );
6689 ins_cost(100);
6691 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6692 ins_encode %{
6693 __ prefetchw($mem$$Address);
6694 %}
6695 ins_pipe(ialu_mem);
6696 %}
6698 instruct prefetchwNTA( memory mem ) %{
6699 predicate(UseSSE>=1);
6700 match(PrefetchWrite mem);
6701 ins_cost(100);
6703 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6704 ins_encode %{
6705 __ prefetchnta($mem$$Address);
6706 %}
6707 ins_pipe(ialu_mem);
6708 %}
6710 // Prefetch instructions for allocation.
6712 instruct prefetchAlloc0( memory mem ) %{
6713 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6714 match(PrefetchAllocation mem);
6715 ins_cost(0);
6716 size(0);
6717 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6718 ins_encode();
6719 ins_pipe(empty);
6720 %}
6722 instruct prefetchAlloc( memory mem ) %{
6723 predicate(AllocatePrefetchInstr==3);
6724 match( PrefetchAllocation mem );
6725 ins_cost(100);
6727 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6728 ins_encode %{
6729 __ prefetchw($mem$$Address);
6730 %}
6731 ins_pipe(ialu_mem);
6732 %}
6734 instruct prefetchAllocNTA( memory mem ) %{
6735 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6736 match(PrefetchAllocation mem);
6737 ins_cost(100);
6739 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6740 ins_encode %{
6741 __ prefetchnta($mem$$Address);
6742 %}
6743 ins_pipe(ialu_mem);
6744 %}
6746 instruct prefetchAllocT0( memory mem ) %{
6747 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6748 match(PrefetchAllocation mem);
6749 ins_cost(100);
6751 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6752 ins_encode %{
6753 __ prefetcht0($mem$$Address);
6754 %}
6755 ins_pipe(ialu_mem);
6756 %}
6758 instruct prefetchAllocT2( memory mem ) %{
6759 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6760 match(PrefetchAllocation mem);
6761 ins_cost(100);
6763 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6764 ins_encode %{
6765 __ prefetcht2($mem$$Address);
6766 %}
6767 ins_pipe(ialu_mem);
6768 %}
6770 //----------Store Instructions-------------------------------------------------
6772 // Store Byte
6773 instruct storeB(memory mem, xRegI src) %{
6774 match(Set mem (StoreB mem src));
6776 ins_cost(125);
6777 format %{ "MOV8 $mem,$src" %}
6778 opcode(0x88);
6779 ins_encode( OpcP, RegMem( src, mem ) );
6780 ins_pipe( ialu_mem_reg );
6781 %}
6783 // Store Char/Short
6784 instruct storeC(memory mem, rRegI src) %{
6785 match(Set mem (StoreC mem src));
6787 ins_cost(125);
6788 format %{ "MOV16 $mem,$src" %}
6789 opcode(0x89, 0x66);
6790 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6791 ins_pipe( ialu_mem_reg );
6792 %}
6794 // Store Integer
6795 instruct storeI(memory mem, rRegI src) %{
6796 match(Set mem (StoreI mem src));
6798 ins_cost(125);
6799 format %{ "MOV $mem,$src" %}
6800 opcode(0x89);
6801 ins_encode( OpcP, RegMem( src, mem ) );
6802 ins_pipe( ialu_mem_reg );
6803 %}
6805 // Store Long
6806 instruct storeL(long_memory mem, eRegL src) %{
6807 predicate(!((StoreLNode*)n)->require_atomic_access());
6808 match(Set mem (StoreL mem src));
6810 ins_cost(200);
6811 format %{ "MOV $mem,$src.lo\n\t"
6812 "MOV $mem+4,$src.hi" %}
6813 opcode(0x89, 0x89);
6814 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6815 ins_pipe( ialu_mem_long_reg );
6816 %}
6818 // Store Long to Integer
6819 instruct storeL2I(memory mem, eRegL src) %{
6820 match(Set mem (StoreI mem (ConvL2I src)));
6822 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6823 ins_encode %{
6824 __ movl($mem$$Address, $src$$Register);
6825 %}
6826 ins_pipe(ialu_mem_reg);
6827 %}
6829 // Volatile Store Long. Must be atomic, so move it into
6830 // the FP TOS and then do a 64-bit FIST. Has to probe the
6831 // target address before the store (for null-ptr checks)
6832 // so the memory operand is used twice in the encoding.
6833 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6834 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6835 match(Set mem (StoreL mem src));
6836 effect( KILL cr );
6837 ins_cost(400);
6838 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6839 "FILD $src\n\t"
6840 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6841 opcode(0x3B);
6842 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6843 ins_pipe( fpu_reg_mem );
6844 %}
6846 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6847 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6848 match(Set mem (StoreL mem src));
6849 effect( TEMP tmp, KILL cr );
6850 ins_cost(380);
6851 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6852 "MOVSD $tmp,$src\n\t"
6853 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6854 ins_encode %{
6855 __ cmpl(rax, $mem$$Address);
6856 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6857 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6858 %}
6859 ins_pipe( pipe_slow );
6860 %}
6862 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6863 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6864 match(Set mem (StoreL mem src));
6865 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6866 ins_cost(360);
6867 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6868 "MOVD $tmp,$src.lo\n\t"
6869 "MOVD $tmp2,$src.hi\n\t"
6870 "PUNPCKLDQ $tmp,$tmp2\n\t"
6871 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6872 ins_encode %{
6873 __ cmpl(rax, $mem$$Address);
6874 __ movdl($tmp$$XMMRegister, $src$$Register);
6875 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6876 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6877 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6878 %}
6879 ins_pipe( pipe_slow );
6880 %}
6882 // Store Pointer; for storing unknown oops and raw pointers
6883 instruct storeP(memory mem, anyRegP src) %{
6884 match(Set mem (StoreP mem src));
6886 ins_cost(125);
6887 format %{ "MOV $mem,$src" %}
6888 opcode(0x89);
6889 ins_encode( OpcP, RegMem( src, mem ) );
6890 ins_pipe( ialu_mem_reg );
6891 %}
6893 // Store Integer Immediate
6894 instruct storeImmI(memory mem, immI src) %{
6895 match(Set mem (StoreI mem src));
6897 ins_cost(150);
6898 format %{ "MOV $mem,$src" %}
6899 opcode(0xC7); /* C7 /0 */
6900 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6901 ins_pipe( ialu_mem_imm );
6902 %}
6904 // Store Short/Char Immediate
6905 instruct storeImmI16(memory mem, immI16 src) %{
6906 predicate(UseStoreImmI16);
6907 match(Set mem (StoreC mem src));
6909 ins_cost(150);
6910 format %{ "MOV16 $mem,$src" %}
6911 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6912 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6913 ins_pipe( ialu_mem_imm );
6914 %}
6916 // Store Pointer Immediate; null pointers or constant oops that do not
6917 // need card-mark barriers.
6918 instruct storeImmP(memory mem, immP src) %{
6919 match(Set mem (StoreP mem src));
6921 ins_cost(150);
6922 format %{ "MOV $mem,$src" %}
6923 opcode(0xC7); /* C7 /0 */
6924 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6925 ins_pipe( ialu_mem_imm );
6926 %}
6928 // Store Byte Immediate
6929 instruct storeImmB(memory mem, immI8 src) %{
6930 match(Set mem (StoreB mem src));
6932 ins_cost(150);
6933 format %{ "MOV8 $mem,$src" %}
6934 opcode(0xC6); /* C6 /0 */
6935 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6936 ins_pipe( ialu_mem_imm );
6937 %}
6939 // Store CMS card-mark Immediate
6940 instruct storeImmCM(memory mem, immI8 src) %{
6941 match(Set mem (StoreCM mem src));
6943 ins_cost(150);
6944 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6945 opcode(0xC6); /* C6 /0 */
6946 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6947 ins_pipe( ialu_mem_imm );
6948 %}
6950 // Store Double
6951 instruct storeDPR( memory mem, regDPR1 src) %{
6952 predicate(UseSSE<=1);
6953 match(Set mem (StoreD mem src));
6955 ins_cost(100);
6956 format %{ "FST_D $mem,$src" %}
6957 opcode(0xDD); /* DD /2 */
6958 ins_encode( enc_FPR_store(mem,src) );
6959 ins_pipe( fpu_mem_reg );
6960 %}
6962 // Store double does rounding on x86
6963 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6964 predicate(UseSSE<=1);
6965 match(Set mem (StoreD mem (RoundDouble src)));
6967 ins_cost(100);
6968 format %{ "FST_D $mem,$src\t# round" %}
6969 opcode(0xDD); /* DD /2 */
6970 ins_encode( enc_FPR_store(mem,src) );
6971 ins_pipe( fpu_mem_reg );
6972 %}
6974 // Store XMM register to memory (double-precision floating points)
6975 // MOVSD instruction
6976 instruct storeD(memory mem, regD src) %{
6977 predicate(UseSSE>=2);
6978 match(Set mem (StoreD mem src));
6979 ins_cost(95);
6980 format %{ "MOVSD $mem,$src" %}
6981 ins_encode %{
6982 __ movdbl($mem$$Address, $src$$XMMRegister);
6983 %}
6984 ins_pipe( pipe_slow );
6985 %}
6987 // Store XMM register to memory (single-precision floating point)
6988 // MOVSS instruction
6989 instruct storeF(memory mem, regF src) %{
6990 predicate(UseSSE>=1);
6991 match(Set mem (StoreF mem src));
6992 ins_cost(95);
6993 format %{ "MOVSS $mem,$src" %}
6994 ins_encode %{
6995 __ movflt($mem$$Address, $src$$XMMRegister);
6996 %}
6997 ins_pipe( pipe_slow );
6998 %}
7000 // Store Float
7001 instruct storeFPR( memory mem, regFPR1 src) %{
7002 predicate(UseSSE==0);
7003 match(Set mem (StoreF mem src));
7005 ins_cost(100);
7006 format %{ "FST_S $mem,$src" %}
7007 opcode(0xD9); /* D9 /2 */
7008 ins_encode( enc_FPR_store(mem,src) );
7009 ins_pipe( fpu_mem_reg );
7010 %}
7012 // Store Float does rounding on x86
7013 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7014 predicate(UseSSE==0);
7015 match(Set mem (StoreF mem (RoundFloat src)));
7017 ins_cost(100);
7018 format %{ "FST_S $mem,$src\t# round" %}
7019 opcode(0xD9); /* D9 /2 */
7020 ins_encode( enc_FPR_store(mem,src) );
7021 ins_pipe( fpu_mem_reg );
7022 %}
7024 // Store Float does rounding on x86
7025 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7026 predicate(UseSSE<=1);
7027 match(Set mem (StoreF mem (ConvD2F src)));
7029 ins_cost(100);
7030 format %{ "FST_S $mem,$src\t# D-round" %}
7031 opcode(0xD9); /* D9 /2 */
7032 ins_encode( enc_FPR_store(mem,src) );
7033 ins_pipe( fpu_mem_reg );
7034 %}
7036 // Store immediate Float value (it is faster than store from FPU register)
7037 // The instruction usage is guarded by predicate in operand immFPR().
7038 instruct storeFPR_imm( memory mem, immFPR src) %{
7039 match(Set mem (StoreF mem src));
7041 ins_cost(50);
7042 format %{ "MOV $mem,$src\t# store float" %}
7043 opcode(0xC7); /* C7 /0 */
7044 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
7045 ins_pipe( ialu_mem_imm );
7046 %}
7048 // Store immediate Float value (it is faster than store from XMM register)
7049 // The instruction usage is guarded by predicate in operand immF().
7050 instruct storeF_imm( memory mem, immF src) %{
7051 match(Set mem (StoreF mem src));
7053 ins_cost(50);
7054 format %{ "MOV $mem,$src\t# store float" %}
7055 opcode(0xC7); /* C7 /0 */
7056 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7057 ins_pipe( ialu_mem_imm );
7058 %}
7060 // Store Integer to stack slot
7061 instruct storeSSI(stackSlotI dst, rRegI src) %{
7062 match(Set dst src);
7064 ins_cost(100);
7065 format %{ "MOV $dst,$src" %}
7066 opcode(0x89);
7067 ins_encode( OpcPRegSS( dst, src ) );
7068 ins_pipe( ialu_mem_reg );
7069 %}
7071 // Store Integer to stack slot
7072 instruct storeSSP(stackSlotP dst, eRegP src) %{
7073 match(Set dst src);
7075 ins_cost(100);
7076 format %{ "MOV $dst,$src" %}
7077 opcode(0x89);
7078 ins_encode( OpcPRegSS( dst, src ) );
7079 ins_pipe( ialu_mem_reg );
7080 %}
7082 // Store Long to stack slot
7083 instruct storeSSL(stackSlotL dst, eRegL src) %{
7084 match(Set dst src);
7086 ins_cost(200);
7087 format %{ "MOV $dst,$src.lo\n\t"
7088 "MOV $dst+4,$src.hi" %}
7089 opcode(0x89, 0x89);
7090 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7091 ins_pipe( ialu_mem_long_reg );
7092 %}
7094 //----------MemBar Instructions-----------------------------------------------
7095 // Memory barrier flavors
7097 instruct membar_acquire() %{
7098 match(MemBarAcquire);
7099 match(LoadFence);
7100 ins_cost(400);
7102 size(0);
7103 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7104 ins_encode();
7105 ins_pipe(empty);
7106 %}
7108 instruct membar_acquire_lock() %{
7109 match(MemBarAcquireLock);
7110 ins_cost(0);
7112 size(0);
7113 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7114 ins_encode( );
7115 ins_pipe(empty);
7116 %}
7118 instruct membar_release() %{
7119 match(MemBarRelease);
7120 match(StoreFence);
7121 ins_cost(400);
7123 size(0);
7124 format %{ "MEMBAR-release ! (empty encoding)" %}
7125 ins_encode( );
7126 ins_pipe(empty);
7127 %}
7129 instruct membar_release_lock() %{
7130 match(MemBarReleaseLock);
7131 ins_cost(0);
7133 size(0);
7134 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7135 ins_encode( );
7136 ins_pipe(empty);
7137 %}
7139 instruct membar_volatile(eFlagsReg cr) %{
7140 match(MemBarVolatile);
7141 effect(KILL cr);
7142 ins_cost(400);
7144 format %{
7145 $$template
7146 if (os::is_MP()) {
7147 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7148 } else {
7149 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7150 }
7151 %}
7152 ins_encode %{
7153 __ membar(Assembler::StoreLoad);
7154 %}
7155 ins_pipe(pipe_slow);
7156 %}
7158 instruct unnecessary_membar_volatile() %{
7159 match(MemBarVolatile);
7160 predicate(Matcher::post_store_load_barrier(n));
7161 ins_cost(0);
7163 size(0);
7164 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7165 ins_encode( );
7166 ins_pipe(empty);
7167 %}
7169 instruct membar_storestore() %{
7170 match(MemBarStoreStore);
7171 ins_cost(0);
7173 size(0);
7174 format %{ "MEMBAR-storestore (empty encoding)" %}
7175 ins_encode( );
7176 ins_pipe(empty);
7177 %}
7179 //----------Move Instructions--------------------------------------------------
7180 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7181 match(Set dst (CastX2P src));
7182 format %{ "# X2P $dst, $src" %}
7183 ins_encode( /*empty encoding*/ );
7184 ins_cost(0);
7185 ins_pipe(empty);
7186 %}
7188 instruct castP2X(rRegI dst, eRegP src ) %{
7189 match(Set dst (CastP2X src));
7190 ins_cost(50);
7191 format %{ "MOV $dst, $src\t# CastP2X" %}
7192 ins_encode( enc_Copy( dst, src) );
7193 ins_pipe( ialu_reg_reg );
7194 %}
7196 //----------Conditional Move---------------------------------------------------
7197 // Conditional move
7198 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
7199 predicate(!VM_Version::supports_cmov() );
7200 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7201 ins_cost(200);
7202 format %{ "J$cop,us skip\t# signed cmove\n\t"
7203 "MOV $dst,$src\n"
7204 "skip:" %}
7205 ins_encode %{
7206 Label Lskip;
7207 // Invert sense of branch from sense of CMOV
7208 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7209 __ movl($dst$$Register, $src$$Register);
7210 __ bind(Lskip);
7211 %}
7212 ins_pipe( pipe_cmov_reg );
7213 %}
7215 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
7216 predicate(!VM_Version::supports_cmov() );
7217 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7218 ins_cost(200);
7219 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7220 "MOV $dst,$src\n"
7221 "skip:" %}
7222 ins_encode %{
7223 Label Lskip;
7224 // Invert sense of branch from sense of CMOV
7225 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7226 __ movl($dst$$Register, $src$$Register);
7227 __ bind(Lskip);
7228 %}
7229 ins_pipe( pipe_cmov_reg );
7230 %}
7232 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
7233 predicate(VM_Version::supports_cmov() );
7234 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7235 ins_cost(200);
7236 format %{ "CMOV$cop $dst,$src" %}
7237 opcode(0x0F,0x40);
7238 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7239 ins_pipe( pipe_cmov_reg );
7240 %}
7242 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
7243 predicate(VM_Version::supports_cmov() );
7244 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7245 ins_cost(200);
7246 format %{ "CMOV$cop $dst,$src" %}
7247 opcode(0x0F,0x40);
7248 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7249 ins_pipe( pipe_cmov_reg );
7250 %}
7252 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
7253 predicate(VM_Version::supports_cmov() );
7254 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7255 ins_cost(200);
7256 expand %{
7257 cmovI_regU(cop, cr, dst, src);
7258 %}
7259 %}
7261 // Conditional move
7262 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
7263 predicate(VM_Version::supports_cmov() );
7264 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7265 ins_cost(250);
7266 format %{ "CMOV$cop $dst,$src" %}
7267 opcode(0x0F,0x40);
7268 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7269 ins_pipe( pipe_cmov_mem );
7270 %}
7272 // Conditional move
7273 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
7274 predicate(VM_Version::supports_cmov() );
7275 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7276 ins_cost(250);
7277 format %{ "CMOV$cop $dst,$src" %}
7278 opcode(0x0F,0x40);
7279 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7280 ins_pipe( pipe_cmov_mem );
7281 %}
7283 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
7284 predicate(VM_Version::supports_cmov() );
7285 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7286 ins_cost(250);
7287 expand %{
7288 cmovI_memU(cop, cr, dst, src);
7289 %}
7290 %}
7292 // Conditional move
7293 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7294 predicate(VM_Version::supports_cmov() );
7295 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7296 ins_cost(200);
7297 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7298 opcode(0x0F,0x40);
7299 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7300 ins_pipe( pipe_cmov_reg );
7301 %}
7303 // Conditional move (non-P6 version)
7304 // Note: a CMoveP is generated for stubs and native wrappers
7305 // regardless of whether we are on a P6, so we
7306 // emulate a cmov here
7307 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7308 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7309 ins_cost(300);
7310 format %{ "Jn$cop skip\n\t"
7311 "MOV $dst,$src\t# pointer\n"
7312 "skip:" %}
7313 opcode(0x8b);
7314 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7315 ins_pipe( pipe_cmov_reg );
7316 %}
7318 // Conditional move
7319 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7320 predicate(VM_Version::supports_cmov() );
7321 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7322 ins_cost(200);
7323 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7324 opcode(0x0F,0x40);
7325 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7326 ins_pipe( pipe_cmov_reg );
7327 %}
7329 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7330 predicate(VM_Version::supports_cmov() );
7331 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7332 ins_cost(200);
7333 expand %{
7334 cmovP_regU(cop, cr, dst, src);
7335 %}
7336 %}
7338 // DISABLED: Requires the ADLC to emit a bottom_type call that
7339 // correctly meets the two pointer arguments; one is an incoming
7340 // register but the other is a memory operand. ALSO appears to
7341 // be buggy with implicit null checks.
7342 //
7343 //// Conditional move
7344 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7345 // predicate(VM_Version::supports_cmov() );
7346 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7347 // ins_cost(250);
7348 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7349 // opcode(0x0F,0x40);
7350 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7351 // ins_pipe( pipe_cmov_mem );
7352 //%}
7353 //
7354 //// Conditional move
7355 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7356 // predicate(VM_Version::supports_cmov() );
7357 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7358 // ins_cost(250);
7359 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7360 // opcode(0x0F,0x40);
7361 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7362 // ins_pipe( pipe_cmov_mem );
7363 //%}
7365 // Conditional move
7366 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7367 predicate(UseSSE<=1);
7368 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7369 ins_cost(200);
7370 format %{ "FCMOV$cop $dst,$src\t# double" %}
7371 opcode(0xDA);
7372 ins_encode( enc_cmov_dpr(cop,src) );
7373 ins_pipe( pipe_cmovDPR_reg );
7374 %}
7376 // Conditional move
7377 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7378 predicate(UseSSE==0);
7379 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7380 ins_cost(200);
7381 format %{ "FCMOV$cop $dst,$src\t# float" %}
7382 opcode(0xDA);
7383 ins_encode( enc_cmov_dpr(cop,src) );
7384 ins_pipe( pipe_cmovDPR_reg );
7385 %}
7387 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7388 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7389 predicate(UseSSE<=1);
7390 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7391 ins_cost(200);
7392 format %{ "Jn$cop skip\n\t"
7393 "MOV $dst,$src\t# double\n"
7394 "skip:" %}
7395 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7396 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7397 ins_pipe( pipe_cmovDPR_reg );
7398 %}
7400 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7401 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7402 predicate(UseSSE==0);
7403 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7404 ins_cost(200);
7405 format %{ "Jn$cop skip\n\t"
7406 "MOV $dst,$src\t# float\n"
7407 "skip:" %}
7408 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7409 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7410 ins_pipe( pipe_cmovDPR_reg );
7411 %}
7413 // No CMOVE with SSE/SSE2
7414 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7415 predicate (UseSSE>=1);
7416 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7417 ins_cost(200);
7418 format %{ "Jn$cop skip\n\t"
7419 "MOVSS $dst,$src\t# float\n"
7420 "skip:" %}
7421 ins_encode %{
7422 Label skip;
7423 // Invert sense of branch from sense of CMOV
7424 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7425 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7426 __ bind(skip);
7427 %}
7428 ins_pipe( pipe_slow );
7429 %}
7431 // No CMOVE with SSE/SSE2
7432 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7433 predicate (UseSSE>=2);
7434 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7435 ins_cost(200);
7436 format %{ "Jn$cop skip\n\t"
7437 "MOVSD $dst,$src\t# float\n"
7438 "skip:" %}
7439 ins_encode %{
7440 Label skip;
7441 // Invert sense of branch from sense of CMOV
7442 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7443 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7444 __ bind(skip);
7445 %}
7446 ins_pipe( pipe_slow );
7447 %}
7449 // unsigned version
7450 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7451 predicate (UseSSE>=1);
7452 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7453 ins_cost(200);
7454 format %{ "Jn$cop skip\n\t"
7455 "MOVSS $dst,$src\t# float\n"
7456 "skip:" %}
7457 ins_encode %{
7458 Label skip;
7459 // Invert sense of branch from sense of CMOV
7460 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7461 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7462 __ bind(skip);
7463 %}
7464 ins_pipe( pipe_slow );
7465 %}
7467 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7468 predicate (UseSSE>=1);
7469 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7470 ins_cost(200);
7471 expand %{
7472 fcmovF_regU(cop, cr, dst, src);
7473 %}
7474 %}
7476 // unsigned version
7477 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7478 predicate (UseSSE>=2);
7479 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7480 ins_cost(200);
7481 format %{ "Jn$cop skip\n\t"
7482 "MOVSD $dst,$src\t# float\n"
7483 "skip:" %}
7484 ins_encode %{
7485 Label skip;
7486 // Invert sense of branch from sense of CMOV
7487 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7488 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7489 __ bind(skip);
7490 %}
7491 ins_pipe( pipe_slow );
7492 %}
7494 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7495 predicate (UseSSE>=2);
7496 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7497 ins_cost(200);
7498 expand %{
7499 fcmovD_regU(cop, cr, dst, src);
7500 %}
7501 %}
7503 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7504 predicate(VM_Version::supports_cmov() );
7505 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7506 ins_cost(200);
7507 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7508 "CMOV$cop $dst.hi,$src.hi" %}
7509 opcode(0x0F,0x40);
7510 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7511 ins_pipe( pipe_cmov_reg_long );
7512 %}
7514 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7515 predicate(VM_Version::supports_cmov() );
7516 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7517 ins_cost(200);
7518 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7519 "CMOV$cop $dst.hi,$src.hi" %}
7520 opcode(0x0F,0x40);
7521 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7522 ins_pipe( pipe_cmov_reg_long );
7523 %}
7525 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7526 predicate(VM_Version::supports_cmov() );
7527 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7528 ins_cost(200);
7529 expand %{
7530 cmovL_regU(cop, cr, dst, src);
7531 %}
7532 %}
7534 //----------Arithmetic Instructions--------------------------------------------
7535 //----------Addition Instructions----------------------------------------------
7537 instruct addExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7538 %{
7539 match(AddExactI dst src);
7540 effect(DEF cr);
7542 format %{ "ADD $dst, $src\t# addExact int" %}
7543 ins_encode %{
7544 __ addl($dst$$Register, $src$$Register);
7545 %}
7546 ins_pipe(ialu_reg_reg);
7547 %}
7549 instruct addExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
7550 %{
7551 match(AddExactI dst src);
7552 effect(DEF cr);
7554 format %{ "ADD $dst, $src\t# addExact int" %}
7555 ins_encode %{
7556 __ addl($dst$$Register, $src$$constant);
7557 %}
7558 ins_pipe(ialu_reg_reg);
7559 %}
7561 instruct addExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
7562 %{
7563 match(AddExactI dst (LoadI src));
7564 effect(DEF cr);
7566 ins_cost(125);
7567 format %{ "ADD $dst,$src\t# addExact int" %}
7568 ins_encode %{
7569 __ addl($dst$$Register, $src$$Address);
7570 %}
7571 ins_pipe( ialu_reg_mem );
7572 %}
7575 // Integer Addition Instructions
7576 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7577 match(Set dst (AddI dst src));
7578 effect(KILL cr);
7580 size(2);
7581 format %{ "ADD $dst,$src" %}
7582 opcode(0x03);
7583 ins_encode( OpcP, RegReg( dst, src) );
7584 ins_pipe( ialu_reg_reg );
7585 %}
7587 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7588 match(Set dst (AddI dst src));
7589 effect(KILL cr);
7591 format %{ "ADD $dst,$src" %}
7592 opcode(0x81, 0x00); /* /0 id */
7593 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7594 ins_pipe( ialu_reg );
7595 %}
7597 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7598 predicate(UseIncDec);
7599 match(Set dst (AddI dst src));
7600 effect(KILL cr);
7602 size(1);
7603 format %{ "INC $dst" %}
7604 opcode(0x40); /* */
7605 ins_encode( Opc_plus( primary, dst ) );
7606 ins_pipe( ialu_reg );
7607 %}
7609 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7610 match(Set dst (AddI src0 src1));
7611 ins_cost(110);
7613 format %{ "LEA $dst,[$src0 + $src1]" %}
7614 opcode(0x8D); /* 0x8D /r */
7615 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7616 ins_pipe( ialu_reg_reg );
7617 %}
7619 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7620 match(Set dst (AddP src0 src1));
7621 ins_cost(110);
7623 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7624 opcode(0x8D); /* 0x8D /r */
7625 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7626 ins_pipe( ialu_reg_reg );
7627 %}
7629 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7630 predicate(UseIncDec);
7631 match(Set dst (AddI dst src));
7632 effect(KILL cr);
7634 size(1);
7635 format %{ "DEC $dst" %}
7636 opcode(0x48); /* */
7637 ins_encode( Opc_plus( primary, dst ) );
7638 ins_pipe( ialu_reg );
7639 %}
7641 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7642 match(Set dst (AddP dst src));
7643 effect(KILL cr);
7645 size(2);
7646 format %{ "ADD $dst,$src" %}
7647 opcode(0x03);
7648 ins_encode( OpcP, RegReg( dst, src) );
7649 ins_pipe( ialu_reg_reg );
7650 %}
7652 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7653 match(Set dst (AddP dst src));
7654 effect(KILL cr);
7656 format %{ "ADD $dst,$src" %}
7657 opcode(0x81,0x00); /* Opcode 81 /0 id */
7658 // ins_encode( RegImm( dst, src) );
7659 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7660 ins_pipe( ialu_reg );
7661 %}
7663 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7664 match(Set dst (AddI dst (LoadI src)));
7665 effect(KILL cr);
7667 ins_cost(125);
7668 format %{ "ADD $dst,$src" %}
7669 opcode(0x03);
7670 ins_encode( OpcP, RegMem( dst, src) );
7671 ins_pipe( ialu_reg_mem );
7672 %}
7674 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7675 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7676 effect(KILL cr);
7678 ins_cost(150);
7679 format %{ "ADD $dst,$src" %}
7680 opcode(0x01); /* Opcode 01 /r */
7681 ins_encode( OpcP, RegMem( src, dst ) );
7682 ins_pipe( ialu_mem_reg );
7683 %}
7685 // Add Memory with Immediate
7686 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7687 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7688 effect(KILL cr);
7690 ins_cost(125);
7691 format %{ "ADD $dst,$src" %}
7692 opcode(0x81); /* Opcode 81 /0 id */
7693 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7694 ins_pipe( ialu_mem_imm );
7695 %}
7697 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7698 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7699 effect(KILL cr);
7701 ins_cost(125);
7702 format %{ "INC $dst" %}
7703 opcode(0xFF); /* Opcode FF /0 */
7704 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7705 ins_pipe( ialu_mem_imm );
7706 %}
7708 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7709 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7710 effect(KILL cr);
7712 ins_cost(125);
7713 format %{ "DEC $dst" %}
7714 opcode(0xFF); /* Opcode FF /1 */
7715 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7716 ins_pipe( ialu_mem_imm );
7717 %}
7720 instruct checkCastPP( eRegP dst ) %{
7721 match(Set dst (CheckCastPP dst));
7723 size(0);
7724 format %{ "#checkcastPP of $dst" %}
7725 ins_encode( /*empty encoding*/ );
7726 ins_pipe( empty );
7727 %}
7729 instruct castPP( eRegP dst ) %{
7730 match(Set dst (CastPP dst));
7731 format %{ "#castPP of $dst" %}
7732 ins_encode( /*empty encoding*/ );
7733 ins_pipe( empty );
7734 %}
7736 instruct castII( rRegI dst ) %{
7737 match(Set dst (CastII dst));
7738 format %{ "#castII of $dst" %}
7739 ins_encode( /*empty encoding*/ );
7740 ins_cost(0);
7741 ins_pipe( empty );
7742 %}
7745 // Load-locked - same as a regular pointer load when used with compare-swap
7746 instruct loadPLocked(eRegP dst, memory mem) %{
7747 match(Set dst (LoadPLocked mem));
7749 ins_cost(125);
7750 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7751 opcode(0x8B);
7752 ins_encode( OpcP, RegMem(dst,mem));
7753 ins_pipe( ialu_reg_mem );
7754 %}
7756 // Conditional-store of the updated heap-top.
7757 // Used during allocation of the shared heap.
7758 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7759 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7760 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7761 // EAX is killed if there is contention, but then it's also unused.
7762 // In the common case of no contention, EAX holds the new oop address.
7763 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7764 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7765 ins_pipe( pipe_cmpxchg );
7766 %}
7768 // Conditional-store of an int value.
7769 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7770 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7771 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7772 effect(KILL oldval);
7773 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7774 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7775 ins_pipe( pipe_cmpxchg );
7776 %}
7778 // Conditional-store of a long value.
7779 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7780 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7781 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7782 effect(KILL oldval);
7783 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7784 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7785 "XCHG EBX,ECX"
7786 %}
7787 ins_encode %{
7788 // Note: we need to swap rbx, and rcx before and after the
7789 // cmpxchg8 instruction because the instruction uses
7790 // rcx as the high order word of the new value to store but
7791 // our register encoding uses rbx.
7792 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7793 if( os::is_MP() )
7794 __ lock();
7795 __ cmpxchg8($mem$$Address);
7796 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7797 %}
7798 ins_pipe( pipe_cmpxchg );
7799 %}
7801 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7803 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7804 predicate(VM_Version::supports_cx8());
7805 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7806 effect(KILL cr, KILL oldval);
7807 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7808 "MOV $res,0\n\t"
7809 "JNE,s fail\n\t"
7810 "MOV $res,1\n"
7811 "fail:" %}
7812 ins_encode( enc_cmpxchg8(mem_ptr),
7813 enc_flags_ne_to_boolean(res) );
7814 ins_pipe( pipe_cmpxchg );
7815 %}
7817 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7818 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7819 effect(KILL cr, KILL oldval);
7820 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7821 "MOV $res,0\n\t"
7822 "JNE,s fail\n\t"
7823 "MOV $res,1\n"
7824 "fail:" %}
7825 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7826 ins_pipe( pipe_cmpxchg );
7827 %}
7829 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7830 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7831 effect(KILL cr, KILL oldval);
7832 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7833 "MOV $res,0\n\t"
7834 "JNE,s fail\n\t"
7835 "MOV $res,1\n"
7836 "fail:" %}
7837 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7838 ins_pipe( pipe_cmpxchg );
7839 %}
7841 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7842 predicate(n->as_LoadStore()->result_not_used());
7843 match(Set dummy (GetAndAddI mem add));
7844 effect(KILL cr);
7845 format %{ "ADDL [$mem],$add" %}
7846 ins_encode %{
7847 if (os::is_MP()) { __ lock(); }
7848 __ addl($mem$$Address, $add$$constant);
7849 %}
7850 ins_pipe( pipe_cmpxchg );
7851 %}
7853 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7854 match(Set newval (GetAndAddI mem newval));
7855 effect(KILL cr);
7856 format %{ "XADDL [$mem],$newval" %}
7857 ins_encode %{
7858 if (os::is_MP()) { __ lock(); }
7859 __ xaddl($mem$$Address, $newval$$Register);
7860 %}
7861 ins_pipe( pipe_cmpxchg );
7862 %}
7864 instruct xchgI( memory mem, rRegI newval) %{
7865 match(Set newval (GetAndSetI mem newval));
7866 format %{ "XCHGL $newval,[$mem]" %}
7867 ins_encode %{
7868 __ xchgl($newval$$Register, $mem$$Address);
7869 %}
7870 ins_pipe( pipe_cmpxchg );
7871 %}
7873 instruct xchgP( memory mem, pRegP newval) %{
7874 match(Set newval (GetAndSetP mem newval));
7875 format %{ "XCHGL $newval,[$mem]" %}
7876 ins_encode %{
7877 __ xchgl($newval$$Register, $mem$$Address);
7878 %}
7879 ins_pipe( pipe_cmpxchg );
7880 %}
7882 //----------Subtraction Instructions-------------------------------------------
7884 instruct subExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7885 %{
7886 match(SubExactI dst src);
7887 effect(DEF cr);
7889 format %{ "SUB $dst, $src\t# subExact int" %}
7890 ins_encode %{
7891 __ subl($dst$$Register, $src$$Register);
7892 %}
7893 ins_pipe(ialu_reg_reg);
7894 %}
7896 instruct subExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
7897 %{
7898 match(SubExactI dst src);
7899 effect(DEF cr);
7901 format %{ "SUB $dst, $src\t# subExact int" %}
7902 ins_encode %{
7903 __ subl($dst$$Register, $src$$constant);
7904 %}
7905 ins_pipe(ialu_reg_reg);
7906 %}
7908 instruct subExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
7909 %{
7910 match(SubExactI dst (LoadI src));
7911 effect(DEF cr);
7913 ins_cost(125);
7914 format %{ "SUB $dst,$src\t# subExact int" %}
7915 ins_encode %{
7916 __ subl($dst$$Register, $src$$Address);
7917 %}
7918 ins_pipe( ialu_reg_mem );
7919 %}
7921 // Integer Subtraction Instructions
7922 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7923 match(Set dst (SubI dst src));
7924 effect(KILL cr);
7926 size(2);
7927 format %{ "SUB $dst,$src" %}
7928 opcode(0x2B);
7929 ins_encode( OpcP, RegReg( dst, src) );
7930 ins_pipe( ialu_reg_reg );
7931 %}
7933 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7934 match(Set dst (SubI dst src));
7935 effect(KILL cr);
7937 format %{ "SUB $dst,$src" %}
7938 opcode(0x81,0x05); /* Opcode 81 /5 */
7939 // ins_encode( RegImm( dst, src) );
7940 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7941 ins_pipe( ialu_reg );
7942 %}
7944 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7945 match(Set dst (SubI dst (LoadI src)));
7946 effect(KILL cr);
7948 ins_cost(125);
7949 format %{ "SUB $dst,$src" %}
7950 opcode(0x2B);
7951 ins_encode( OpcP, RegMem( dst, src) );
7952 ins_pipe( ialu_reg_mem );
7953 %}
7955 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7956 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7957 effect(KILL cr);
7959 ins_cost(150);
7960 format %{ "SUB $dst,$src" %}
7961 opcode(0x29); /* Opcode 29 /r */
7962 ins_encode( OpcP, RegMem( src, dst ) );
7963 ins_pipe( ialu_mem_reg );
7964 %}
7966 // Subtract from a pointer
7967 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7968 match(Set dst (AddP dst (SubI zero src)));
7969 effect(KILL cr);
7971 size(2);
7972 format %{ "SUB $dst,$src" %}
7973 opcode(0x2B);
7974 ins_encode( OpcP, RegReg( dst, src) );
7975 ins_pipe( ialu_reg_reg );
7976 %}
7978 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7979 match(Set dst (SubI zero dst));
7980 effect(KILL cr);
7982 size(2);
7983 format %{ "NEG $dst" %}
7984 opcode(0xF7,0x03); // Opcode F7 /3
7985 ins_encode( OpcP, RegOpc( dst ) );
7986 ins_pipe( ialu_reg );
7987 %}
7989 instruct negExactI_eReg(eAXRegI dst, eFlagsReg cr) %{
7990 match(NegExactI dst);
7991 effect(DEF cr);
7993 format %{ "NEG $dst\t# negExact int"%}
7994 ins_encode %{
7995 __ negl($dst$$Register);
7996 %}
7997 ins_pipe(ialu_reg);
7998 %}
8000 //----------Multiplication/Division Instructions-------------------------------
8001 // Integer Multiplication Instructions
8002 // Multiply Register
8003 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8004 match(Set dst (MulI dst src));
8005 effect(KILL cr);
8007 size(3);
8008 ins_cost(300);
8009 format %{ "IMUL $dst,$src" %}
8010 opcode(0xAF, 0x0F);
8011 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8012 ins_pipe( ialu_reg_reg_alu0 );
8013 %}
8015 // Multiply 32-bit Immediate
8016 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
8017 match(Set dst (MulI src imm));
8018 effect(KILL cr);
8020 ins_cost(300);
8021 format %{ "IMUL $dst,$src,$imm" %}
8022 opcode(0x69); /* 69 /r id */
8023 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8024 ins_pipe( ialu_reg_reg_alu0 );
8025 %}
8027 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8028 match(Set dst src);
8029 effect(KILL cr);
8031 // Note that this is artificially increased to make it more expensive than loadConL
8032 ins_cost(250);
8033 format %{ "MOV EAX,$src\t// low word only" %}
8034 opcode(0xB8);
8035 ins_encode( LdImmL_Lo(dst, src) );
8036 ins_pipe( ialu_reg_fat );
8037 %}
8039 // Multiply by 32-bit Immediate, taking the shifted high order results
8040 // (special case for shift by 32)
8041 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8042 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8043 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8044 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8045 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8046 effect(USE src1, KILL cr);
8048 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8049 ins_cost(0*100 + 1*400 - 150);
8050 format %{ "IMUL EDX:EAX,$src1" %}
8051 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8052 ins_pipe( pipe_slow );
8053 %}
8055 // Multiply by 32-bit Immediate, taking the shifted high order results
8056 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8057 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8058 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8059 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8060 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8061 effect(USE src1, KILL cr);
8063 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8064 ins_cost(1*100 + 1*400 - 150);
8065 format %{ "IMUL EDX:EAX,$src1\n\t"
8066 "SAR EDX,$cnt-32" %}
8067 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8068 ins_pipe( pipe_slow );
8069 %}
8071 // Multiply Memory 32-bit Immediate
8072 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
8073 match(Set dst (MulI (LoadI src) imm));
8074 effect(KILL cr);
8076 ins_cost(300);
8077 format %{ "IMUL $dst,$src,$imm" %}
8078 opcode(0x69); /* 69 /r id */
8079 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8080 ins_pipe( ialu_reg_mem_alu0 );
8081 %}
8083 // Multiply Memory
8084 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
8085 match(Set dst (MulI dst (LoadI src)));
8086 effect(KILL cr);
8088 ins_cost(350);
8089 format %{ "IMUL $dst,$src" %}
8090 opcode(0xAF, 0x0F);
8091 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8092 ins_pipe( ialu_reg_mem_alu0 );
8093 %}
8095 // Multiply Register Int to Long
8096 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8097 // Basic Idea: long = (long)int * (long)int
8098 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8099 effect(DEF dst, USE src, USE src1, KILL flags);
8101 ins_cost(300);
8102 format %{ "IMUL $dst,$src1" %}
8104 ins_encode( long_int_multiply( dst, src1 ) );
8105 ins_pipe( ialu_reg_reg_alu0 );
8106 %}
8108 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8109 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8110 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8111 effect(KILL flags);
8113 ins_cost(300);
8114 format %{ "MUL $dst,$src1" %}
8116 ins_encode( long_uint_multiply(dst, src1) );
8117 ins_pipe( ialu_reg_reg_alu0 );
8118 %}
8120 // Multiply Register Long
8121 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8122 match(Set dst (MulL dst src));
8123 effect(KILL cr, TEMP tmp);
8124 ins_cost(4*100+3*400);
8125 // Basic idea: lo(result) = lo(x_lo * y_lo)
8126 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8127 format %{ "MOV $tmp,$src.lo\n\t"
8128 "IMUL $tmp,EDX\n\t"
8129 "MOV EDX,$src.hi\n\t"
8130 "IMUL EDX,EAX\n\t"
8131 "ADD $tmp,EDX\n\t"
8132 "MUL EDX:EAX,$src.lo\n\t"
8133 "ADD EDX,$tmp" %}
8134 ins_encode( long_multiply( dst, src, tmp ) );
8135 ins_pipe( pipe_slow );
8136 %}
8138 // Multiply Register Long where the left operand's high 32 bits are zero
8139 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8140 predicate(is_operand_hi32_zero(n->in(1)));
8141 match(Set dst (MulL dst src));
8142 effect(KILL cr, TEMP tmp);
8143 ins_cost(2*100+2*400);
8144 // Basic idea: lo(result) = lo(x_lo * y_lo)
8145 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8146 format %{ "MOV $tmp,$src.hi\n\t"
8147 "IMUL $tmp,EAX\n\t"
8148 "MUL EDX:EAX,$src.lo\n\t"
8149 "ADD EDX,$tmp" %}
8150 ins_encode %{
8151 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8152 __ imull($tmp$$Register, rax);
8153 __ mull($src$$Register);
8154 __ addl(rdx, $tmp$$Register);
8155 %}
8156 ins_pipe( pipe_slow );
8157 %}
8159 // Multiply Register Long where the right operand's high 32 bits are zero
8160 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8161 predicate(is_operand_hi32_zero(n->in(2)));
8162 match(Set dst (MulL dst src));
8163 effect(KILL cr, TEMP tmp);
8164 ins_cost(2*100+2*400);
8165 // Basic idea: lo(result) = lo(x_lo * y_lo)
8166 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8167 format %{ "MOV $tmp,$src.lo\n\t"
8168 "IMUL $tmp,EDX\n\t"
8169 "MUL EDX:EAX,$src.lo\n\t"
8170 "ADD EDX,$tmp" %}
8171 ins_encode %{
8172 __ movl($tmp$$Register, $src$$Register);
8173 __ imull($tmp$$Register, rdx);
8174 __ mull($src$$Register);
8175 __ addl(rdx, $tmp$$Register);
8176 %}
8177 ins_pipe( pipe_slow );
8178 %}
8180 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8181 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8182 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8183 match(Set dst (MulL dst src));
8184 effect(KILL cr);
8185 ins_cost(1*400);
8186 // Basic idea: lo(result) = lo(x_lo * y_lo)
8187 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8188 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8189 ins_encode %{
8190 __ mull($src$$Register);
8191 %}
8192 ins_pipe( pipe_slow );
8193 %}
8195 // Multiply Register Long by small constant
8196 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8197 match(Set dst (MulL dst src));
8198 effect(KILL cr, TEMP tmp);
8199 ins_cost(2*100+2*400);
8200 size(12);
8201 // Basic idea: lo(result) = lo(src * EAX)
8202 // hi(result) = hi(src * EAX) + lo(src * EDX)
8203 format %{ "IMUL $tmp,EDX,$src\n\t"
8204 "MOV EDX,$src\n\t"
8205 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8206 "ADD EDX,$tmp" %}
8207 ins_encode( long_multiply_con( dst, src, tmp ) );
8208 ins_pipe( pipe_slow );
8209 %}
8211 instruct mulExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
8212 %{
8213 match(MulExactI dst src);
8214 effect(DEF cr);
8216 ins_cost(300);
8217 format %{ "IMUL $dst, $src\t# mulExact int" %}
8218 ins_encode %{
8219 __ imull($dst$$Register, $src$$Register);
8220 %}
8221 ins_pipe(ialu_reg_reg_alu0);
8222 %}
8224 instruct mulExactI_eReg_imm(eAXRegI dst, rRegI src, immI imm, eFlagsReg cr)
8225 %{
8226 match(MulExactI src imm);
8227 effect(DEF cr);
8229 ins_cost(300);
8230 format %{ "IMUL $dst, $src, $imm\t# mulExact int" %}
8231 ins_encode %{
8232 __ imull($dst$$Register, $src$$Register, $imm$$constant);
8233 %}
8234 ins_pipe(ialu_reg_reg_alu0);
8235 %}
8237 instruct mulExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
8238 %{
8239 match(MulExactI dst (LoadI src));
8240 effect(DEF cr);
8242 ins_cost(350);
8243 format %{ "IMUL $dst, $src\t# mulExact int" %}
8244 ins_encode %{
8245 __ imull($dst$$Register, $src$$Address);
8246 %}
8247 ins_pipe(ialu_reg_mem_alu0);
8248 %}
8251 // Integer DIV with Register
8252 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8253 match(Set rax (DivI rax div));
8254 effect(KILL rdx, KILL cr);
8255 size(26);
8256 ins_cost(30*100+10*100);
8257 format %{ "CMP EAX,0x80000000\n\t"
8258 "JNE,s normal\n\t"
8259 "XOR EDX,EDX\n\t"
8260 "CMP ECX,-1\n\t"
8261 "JE,s done\n"
8262 "normal: CDQ\n\t"
8263 "IDIV $div\n\t"
8264 "done:" %}
8265 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8266 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8267 ins_pipe( ialu_reg_reg_alu0 );
8268 %}
8270 // Divide Register Long
8271 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8272 match(Set dst (DivL src1 src2));
8273 effect( KILL cr, KILL cx, KILL bx );
8274 ins_cost(10000);
8275 format %{ "PUSH $src1.hi\n\t"
8276 "PUSH $src1.lo\n\t"
8277 "PUSH $src2.hi\n\t"
8278 "PUSH $src2.lo\n\t"
8279 "CALL SharedRuntime::ldiv\n\t"
8280 "ADD ESP,16" %}
8281 ins_encode( long_div(src1,src2) );
8282 ins_pipe( pipe_slow );
8283 %}
8285 // Integer DIVMOD with Register, both quotient and mod results
8286 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8287 match(DivModI rax div);
8288 effect(KILL cr);
8289 size(26);
8290 ins_cost(30*100+10*100);
8291 format %{ "CMP EAX,0x80000000\n\t"
8292 "JNE,s normal\n\t"
8293 "XOR EDX,EDX\n\t"
8294 "CMP ECX,-1\n\t"
8295 "JE,s done\n"
8296 "normal: CDQ\n\t"
8297 "IDIV $div\n\t"
8298 "done:" %}
8299 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8300 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8301 ins_pipe( pipe_slow );
8302 %}
8304 // Integer MOD with Register
8305 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8306 match(Set rdx (ModI rax div));
8307 effect(KILL rax, KILL cr);
8309 size(26);
8310 ins_cost(300);
8311 format %{ "CDQ\n\t"
8312 "IDIV $div" %}
8313 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8314 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8315 ins_pipe( ialu_reg_reg_alu0 );
8316 %}
8318 // Remainder Register Long
8319 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8320 match(Set dst (ModL src1 src2));
8321 effect( KILL cr, KILL cx, KILL bx );
8322 ins_cost(10000);
8323 format %{ "PUSH $src1.hi\n\t"
8324 "PUSH $src1.lo\n\t"
8325 "PUSH $src2.hi\n\t"
8326 "PUSH $src2.lo\n\t"
8327 "CALL SharedRuntime::lrem\n\t"
8328 "ADD ESP,16" %}
8329 ins_encode( long_mod(src1,src2) );
8330 ins_pipe( pipe_slow );
8331 %}
8333 // Divide Register Long (no special case since divisor != -1)
8334 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8335 match(Set dst (DivL dst imm));
8336 effect( TEMP tmp, TEMP tmp2, KILL cr );
8337 ins_cost(1000);
8338 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8339 "XOR $tmp2,$tmp2\n\t"
8340 "CMP $tmp,EDX\n\t"
8341 "JA,s fast\n\t"
8342 "MOV $tmp2,EAX\n\t"
8343 "MOV EAX,EDX\n\t"
8344 "MOV EDX,0\n\t"
8345 "JLE,s pos\n\t"
8346 "LNEG EAX : $tmp2\n\t"
8347 "DIV $tmp # unsigned division\n\t"
8348 "XCHG EAX,$tmp2\n\t"
8349 "DIV $tmp\n\t"
8350 "LNEG $tmp2 : EAX\n\t"
8351 "JMP,s done\n"
8352 "pos:\n\t"
8353 "DIV $tmp\n\t"
8354 "XCHG EAX,$tmp2\n"
8355 "fast:\n\t"
8356 "DIV $tmp\n"
8357 "done:\n\t"
8358 "MOV EDX,$tmp2\n\t"
8359 "NEG EDX:EAX # if $imm < 0" %}
8360 ins_encode %{
8361 int con = (int)$imm$$constant;
8362 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8363 int pcon = (con > 0) ? con : -con;
8364 Label Lfast, Lpos, Ldone;
8366 __ movl($tmp$$Register, pcon);
8367 __ xorl($tmp2$$Register,$tmp2$$Register);
8368 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8369 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8371 __ movl($tmp2$$Register, $dst$$Register); // save
8372 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8373 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8374 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8376 // Negative dividend.
8377 // convert value to positive to use unsigned division
8378 __ lneg($dst$$Register, $tmp2$$Register);
8379 __ divl($tmp$$Register);
8380 __ xchgl($dst$$Register, $tmp2$$Register);
8381 __ divl($tmp$$Register);
8382 // revert result back to negative
8383 __ lneg($tmp2$$Register, $dst$$Register);
8384 __ jmpb(Ldone);
8386 __ bind(Lpos);
8387 __ divl($tmp$$Register); // Use unsigned division
8388 __ xchgl($dst$$Register, $tmp2$$Register);
8389 // Fallthrow for final divide, tmp2 has 32 bit hi result
8391 __ bind(Lfast);
8392 // fast path: src is positive
8393 __ divl($tmp$$Register); // Use unsigned division
8395 __ bind(Ldone);
8396 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8397 if (con < 0) {
8398 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8399 }
8400 %}
8401 ins_pipe( pipe_slow );
8402 %}
8404 // Remainder Register Long (remainder fit into 32 bits)
8405 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8406 match(Set dst (ModL dst imm));
8407 effect( TEMP tmp, TEMP tmp2, KILL cr );
8408 ins_cost(1000);
8409 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8410 "CMP $tmp,EDX\n\t"
8411 "JA,s fast\n\t"
8412 "MOV $tmp2,EAX\n\t"
8413 "MOV EAX,EDX\n\t"
8414 "MOV EDX,0\n\t"
8415 "JLE,s pos\n\t"
8416 "LNEG EAX : $tmp2\n\t"
8417 "DIV $tmp # unsigned division\n\t"
8418 "MOV EAX,$tmp2\n\t"
8419 "DIV $tmp\n\t"
8420 "NEG EDX\n\t"
8421 "JMP,s done\n"
8422 "pos:\n\t"
8423 "DIV $tmp\n\t"
8424 "MOV EAX,$tmp2\n"
8425 "fast:\n\t"
8426 "DIV $tmp\n"
8427 "done:\n\t"
8428 "MOV EAX,EDX\n\t"
8429 "SAR EDX,31\n\t" %}
8430 ins_encode %{
8431 int con = (int)$imm$$constant;
8432 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8433 int pcon = (con > 0) ? con : -con;
8434 Label Lfast, Lpos, Ldone;
8436 __ movl($tmp$$Register, pcon);
8437 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8438 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8440 __ movl($tmp2$$Register, $dst$$Register); // save
8441 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8442 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8443 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8445 // Negative dividend.
8446 // convert value to positive to use unsigned division
8447 __ lneg($dst$$Register, $tmp2$$Register);
8448 __ divl($tmp$$Register);
8449 __ movl($dst$$Register, $tmp2$$Register);
8450 __ divl($tmp$$Register);
8451 // revert remainder back to negative
8452 __ negl(HIGH_FROM_LOW($dst$$Register));
8453 __ jmpb(Ldone);
8455 __ bind(Lpos);
8456 __ divl($tmp$$Register);
8457 __ movl($dst$$Register, $tmp2$$Register);
8459 __ bind(Lfast);
8460 // fast path: src is positive
8461 __ divl($tmp$$Register);
8463 __ bind(Ldone);
8464 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8465 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8467 %}
8468 ins_pipe( pipe_slow );
8469 %}
8471 // Integer Shift Instructions
8472 // Shift Left by one
8473 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8474 match(Set dst (LShiftI dst shift));
8475 effect(KILL cr);
8477 size(2);
8478 format %{ "SHL $dst,$shift" %}
8479 opcode(0xD1, 0x4); /* D1 /4 */
8480 ins_encode( OpcP, RegOpc( dst ) );
8481 ins_pipe( ialu_reg );
8482 %}
8484 // Shift Left by 8-bit immediate
8485 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8486 match(Set dst (LShiftI dst shift));
8487 effect(KILL cr);
8489 size(3);
8490 format %{ "SHL $dst,$shift" %}
8491 opcode(0xC1, 0x4); /* C1 /4 ib */
8492 ins_encode( RegOpcImm( dst, shift) );
8493 ins_pipe( ialu_reg );
8494 %}
8496 // Shift Left by variable
8497 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8498 match(Set dst (LShiftI dst shift));
8499 effect(KILL cr);
8501 size(2);
8502 format %{ "SHL $dst,$shift" %}
8503 opcode(0xD3, 0x4); /* D3 /4 */
8504 ins_encode( OpcP, RegOpc( dst ) );
8505 ins_pipe( ialu_reg_reg );
8506 %}
8508 // Arithmetic shift right by one
8509 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8510 match(Set dst (RShiftI dst shift));
8511 effect(KILL cr);
8513 size(2);
8514 format %{ "SAR $dst,$shift" %}
8515 opcode(0xD1, 0x7); /* D1 /7 */
8516 ins_encode( OpcP, RegOpc( dst ) );
8517 ins_pipe( ialu_reg );
8518 %}
8520 // Arithmetic shift right by one
8521 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8522 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8523 effect(KILL cr);
8524 format %{ "SAR $dst,$shift" %}
8525 opcode(0xD1, 0x7); /* D1 /7 */
8526 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8527 ins_pipe( ialu_mem_imm );
8528 %}
8530 // Arithmetic Shift Right by 8-bit immediate
8531 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8532 match(Set dst (RShiftI dst shift));
8533 effect(KILL cr);
8535 size(3);
8536 format %{ "SAR $dst,$shift" %}
8537 opcode(0xC1, 0x7); /* C1 /7 ib */
8538 ins_encode( RegOpcImm( dst, shift ) );
8539 ins_pipe( ialu_mem_imm );
8540 %}
8542 // Arithmetic Shift Right by 8-bit immediate
8543 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8544 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8545 effect(KILL cr);
8547 format %{ "SAR $dst,$shift" %}
8548 opcode(0xC1, 0x7); /* C1 /7 ib */
8549 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8550 ins_pipe( ialu_mem_imm );
8551 %}
8553 // Arithmetic Shift Right by variable
8554 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8555 match(Set dst (RShiftI dst shift));
8556 effect(KILL cr);
8558 size(2);
8559 format %{ "SAR $dst,$shift" %}
8560 opcode(0xD3, 0x7); /* D3 /7 */
8561 ins_encode( OpcP, RegOpc( dst ) );
8562 ins_pipe( ialu_reg_reg );
8563 %}
8565 // Logical shift right by one
8566 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8567 match(Set dst (URShiftI dst shift));
8568 effect(KILL cr);
8570 size(2);
8571 format %{ "SHR $dst,$shift" %}
8572 opcode(0xD1, 0x5); /* D1 /5 */
8573 ins_encode( OpcP, RegOpc( dst ) );
8574 ins_pipe( ialu_reg );
8575 %}
8577 // Logical Shift Right by 8-bit immediate
8578 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8579 match(Set dst (URShiftI dst shift));
8580 effect(KILL cr);
8582 size(3);
8583 format %{ "SHR $dst,$shift" %}
8584 opcode(0xC1, 0x5); /* C1 /5 ib */
8585 ins_encode( RegOpcImm( dst, shift) );
8586 ins_pipe( ialu_reg );
8587 %}
8590 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8591 // This idiom is used by the compiler for the i2b bytecode.
8592 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
8593 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8595 size(3);
8596 format %{ "MOVSX $dst,$src :8" %}
8597 ins_encode %{
8598 __ movsbl($dst$$Register, $src$$Register);
8599 %}
8600 ins_pipe(ialu_reg_reg);
8601 %}
8603 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8604 // This idiom is used by the compiler the i2s bytecode.
8605 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
8606 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8608 size(3);
8609 format %{ "MOVSX $dst,$src :16" %}
8610 ins_encode %{
8611 __ movswl($dst$$Register, $src$$Register);
8612 %}
8613 ins_pipe(ialu_reg_reg);
8614 %}
8617 // Logical Shift Right by variable
8618 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8619 match(Set dst (URShiftI dst shift));
8620 effect(KILL cr);
8622 size(2);
8623 format %{ "SHR $dst,$shift" %}
8624 opcode(0xD3, 0x5); /* D3 /5 */
8625 ins_encode( OpcP, RegOpc( dst ) );
8626 ins_pipe( ialu_reg_reg );
8627 %}
8630 //----------Logical Instructions-----------------------------------------------
8631 //----------Integer Logical Instructions---------------------------------------
8632 // And Instructions
8633 // And Register with Register
8634 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8635 match(Set dst (AndI dst src));
8636 effect(KILL cr);
8638 size(2);
8639 format %{ "AND $dst,$src" %}
8640 opcode(0x23);
8641 ins_encode( OpcP, RegReg( dst, src) );
8642 ins_pipe( ialu_reg_reg );
8643 %}
8645 // And Register with Immediate
8646 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8647 match(Set dst (AndI dst src));
8648 effect(KILL cr);
8650 format %{ "AND $dst,$src" %}
8651 opcode(0x81,0x04); /* Opcode 81 /4 */
8652 // ins_encode( RegImm( dst, src) );
8653 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8654 ins_pipe( ialu_reg );
8655 %}
8657 // And Register with Memory
8658 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8659 match(Set dst (AndI dst (LoadI src)));
8660 effect(KILL cr);
8662 ins_cost(125);
8663 format %{ "AND $dst,$src" %}
8664 opcode(0x23);
8665 ins_encode( OpcP, RegMem( dst, src) );
8666 ins_pipe( ialu_reg_mem );
8667 %}
8669 // And Memory with Register
8670 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8671 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8672 effect(KILL cr);
8674 ins_cost(150);
8675 format %{ "AND $dst,$src" %}
8676 opcode(0x21); /* Opcode 21 /r */
8677 ins_encode( OpcP, RegMem( src, dst ) );
8678 ins_pipe( ialu_mem_reg );
8679 %}
8681 // And Memory with Immediate
8682 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8683 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8684 effect(KILL cr);
8686 ins_cost(125);
8687 format %{ "AND $dst,$src" %}
8688 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8689 // ins_encode( MemImm( dst, src) );
8690 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8691 ins_pipe( ialu_mem_imm );
8692 %}
8694 // Or Instructions
8695 // Or Register with Register
8696 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8697 match(Set dst (OrI dst src));
8698 effect(KILL cr);
8700 size(2);
8701 format %{ "OR $dst,$src" %}
8702 opcode(0x0B);
8703 ins_encode( OpcP, RegReg( dst, src) );
8704 ins_pipe( ialu_reg_reg );
8705 %}
8707 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8708 match(Set dst (OrI dst (CastP2X src)));
8709 effect(KILL cr);
8711 size(2);
8712 format %{ "OR $dst,$src" %}
8713 opcode(0x0B);
8714 ins_encode( OpcP, RegReg( dst, src) );
8715 ins_pipe( ialu_reg_reg );
8716 %}
8719 // Or Register with Immediate
8720 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8721 match(Set dst (OrI dst src));
8722 effect(KILL cr);
8724 format %{ "OR $dst,$src" %}
8725 opcode(0x81,0x01); /* Opcode 81 /1 id */
8726 // ins_encode( RegImm( dst, src) );
8727 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8728 ins_pipe( ialu_reg );
8729 %}
8731 // Or Register with Memory
8732 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8733 match(Set dst (OrI dst (LoadI src)));
8734 effect(KILL cr);
8736 ins_cost(125);
8737 format %{ "OR $dst,$src" %}
8738 opcode(0x0B);
8739 ins_encode( OpcP, RegMem( dst, src) );
8740 ins_pipe( ialu_reg_mem );
8741 %}
8743 // Or Memory with Register
8744 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8745 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8746 effect(KILL cr);
8748 ins_cost(150);
8749 format %{ "OR $dst,$src" %}
8750 opcode(0x09); /* Opcode 09 /r */
8751 ins_encode( OpcP, RegMem( src, dst ) );
8752 ins_pipe( ialu_mem_reg );
8753 %}
8755 // Or Memory with Immediate
8756 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8757 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8758 effect(KILL cr);
8760 ins_cost(125);
8761 format %{ "OR $dst,$src" %}
8762 opcode(0x81,0x1); /* Opcode 81 /1 id */
8763 // ins_encode( MemImm( dst, src) );
8764 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8765 ins_pipe( ialu_mem_imm );
8766 %}
8768 // ROL/ROR
8769 // ROL expand
8770 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8771 effect(USE_DEF dst, USE shift, KILL cr);
8773 format %{ "ROL $dst, $shift" %}
8774 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8775 ins_encode( OpcP, RegOpc( dst ));
8776 ins_pipe( ialu_reg );
8777 %}
8779 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8780 effect(USE_DEF dst, USE shift, KILL cr);
8782 format %{ "ROL $dst, $shift" %}
8783 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8784 ins_encode( RegOpcImm(dst, shift) );
8785 ins_pipe(ialu_reg);
8786 %}
8788 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8789 effect(USE_DEF dst, USE shift, KILL cr);
8791 format %{ "ROL $dst, $shift" %}
8792 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8793 ins_encode(OpcP, RegOpc(dst));
8794 ins_pipe( ialu_reg_reg );
8795 %}
8796 // end of ROL expand
8798 // ROL 32bit by one once
8799 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8800 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8802 expand %{
8803 rolI_eReg_imm1(dst, lshift, cr);
8804 %}
8805 %}
8807 // ROL 32bit var by imm8 once
8808 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8809 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8810 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8812 expand %{
8813 rolI_eReg_imm8(dst, lshift, cr);
8814 %}
8815 %}
8817 // ROL 32bit var by var once
8818 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8819 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8821 expand %{
8822 rolI_eReg_CL(dst, shift, cr);
8823 %}
8824 %}
8826 // ROL 32bit var by var once
8827 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8828 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8830 expand %{
8831 rolI_eReg_CL(dst, shift, cr);
8832 %}
8833 %}
8835 // ROR expand
8836 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8837 effect(USE_DEF dst, USE shift, KILL cr);
8839 format %{ "ROR $dst, $shift" %}
8840 opcode(0xD1,0x1); /* Opcode D1 /1 */
8841 ins_encode( OpcP, RegOpc( dst ) );
8842 ins_pipe( ialu_reg );
8843 %}
8845 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8846 effect (USE_DEF dst, USE shift, KILL cr);
8848 format %{ "ROR $dst, $shift" %}
8849 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8850 ins_encode( RegOpcImm(dst, shift) );
8851 ins_pipe( ialu_reg );
8852 %}
8854 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8855 effect(USE_DEF dst, USE shift, KILL cr);
8857 format %{ "ROR $dst, $shift" %}
8858 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8859 ins_encode(OpcP, RegOpc(dst));
8860 ins_pipe( ialu_reg_reg );
8861 %}
8862 // end of ROR expand
8864 // ROR right once
8865 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8866 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8868 expand %{
8869 rorI_eReg_imm1(dst, rshift, cr);
8870 %}
8871 %}
8873 // ROR 32bit by immI8 once
8874 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8875 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8876 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8878 expand %{
8879 rorI_eReg_imm8(dst, rshift, cr);
8880 %}
8881 %}
8883 // ROR 32bit var by var once
8884 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8885 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8887 expand %{
8888 rorI_eReg_CL(dst, shift, cr);
8889 %}
8890 %}
8892 // ROR 32bit var by var once
8893 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8894 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8896 expand %{
8897 rorI_eReg_CL(dst, shift, cr);
8898 %}
8899 %}
8901 // Xor Instructions
8902 // Xor Register with Register
8903 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8904 match(Set dst (XorI dst src));
8905 effect(KILL cr);
8907 size(2);
8908 format %{ "XOR $dst,$src" %}
8909 opcode(0x33);
8910 ins_encode( OpcP, RegReg( dst, src) );
8911 ins_pipe( ialu_reg_reg );
8912 %}
8914 // Xor Register with Immediate -1
8915 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8916 match(Set dst (XorI dst imm));
8918 size(2);
8919 format %{ "NOT $dst" %}
8920 ins_encode %{
8921 __ notl($dst$$Register);
8922 %}
8923 ins_pipe( ialu_reg );
8924 %}
8926 // Xor Register with Immediate
8927 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8928 match(Set dst (XorI dst src));
8929 effect(KILL cr);
8931 format %{ "XOR $dst,$src" %}
8932 opcode(0x81,0x06); /* Opcode 81 /6 id */
8933 // ins_encode( RegImm( dst, src) );
8934 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8935 ins_pipe( ialu_reg );
8936 %}
8938 // Xor Register with Memory
8939 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8940 match(Set dst (XorI dst (LoadI src)));
8941 effect(KILL cr);
8943 ins_cost(125);
8944 format %{ "XOR $dst,$src" %}
8945 opcode(0x33);
8946 ins_encode( OpcP, RegMem(dst, src) );
8947 ins_pipe( ialu_reg_mem );
8948 %}
8950 // Xor Memory with Register
8951 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8952 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8953 effect(KILL cr);
8955 ins_cost(150);
8956 format %{ "XOR $dst,$src" %}
8957 opcode(0x31); /* Opcode 31 /r */
8958 ins_encode( OpcP, RegMem( src, dst ) );
8959 ins_pipe( ialu_mem_reg );
8960 %}
8962 // Xor Memory with Immediate
8963 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8964 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8965 effect(KILL cr);
8967 ins_cost(125);
8968 format %{ "XOR $dst,$src" %}
8969 opcode(0x81,0x6); /* Opcode 81 /6 id */
8970 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8971 ins_pipe( ialu_mem_imm );
8972 %}
8974 //----------Convert Int to Boolean---------------------------------------------
8976 instruct movI_nocopy(rRegI dst, rRegI src) %{
8977 effect( DEF dst, USE src );
8978 format %{ "MOV $dst,$src" %}
8979 ins_encode( enc_Copy( dst, src) );
8980 ins_pipe( ialu_reg_reg );
8981 %}
8983 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8984 effect( USE_DEF dst, USE src, KILL cr );
8986 size(4);
8987 format %{ "NEG $dst\n\t"
8988 "ADC $dst,$src" %}
8989 ins_encode( neg_reg(dst),
8990 OpcRegReg(0x13,dst,src) );
8991 ins_pipe( ialu_reg_reg_long );
8992 %}
8994 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8995 match(Set dst (Conv2B src));
8997 expand %{
8998 movI_nocopy(dst,src);
8999 ci2b(dst,src,cr);
9000 %}
9001 %}
9003 instruct movP_nocopy(rRegI dst, eRegP src) %{
9004 effect( DEF dst, USE src );
9005 format %{ "MOV $dst,$src" %}
9006 ins_encode( enc_Copy( dst, src) );
9007 ins_pipe( ialu_reg_reg );
9008 %}
9010 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
9011 effect( USE_DEF dst, USE src, KILL cr );
9012 format %{ "NEG $dst\n\t"
9013 "ADC $dst,$src" %}
9014 ins_encode( neg_reg(dst),
9015 OpcRegReg(0x13,dst,src) );
9016 ins_pipe( ialu_reg_reg_long );
9017 %}
9019 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
9020 match(Set dst (Conv2B src));
9022 expand %{
9023 movP_nocopy(dst,src);
9024 cp2b(dst,src,cr);
9025 %}
9026 %}
9028 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{
9029 match(Set dst (CmpLTMask p q));
9030 effect(KILL cr);
9031 ins_cost(400);
9033 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9034 format %{ "XOR $dst,$dst\n\t"
9035 "CMP $p,$q\n\t"
9036 "SETlt $dst\n\t"
9037 "NEG $dst" %}
9038 ins_encode %{
9039 Register Rp = $p$$Register;
9040 Register Rq = $q$$Register;
9041 Register Rd = $dst$$Register;
9042 Label done;
9043 __ xorl(Rd, Rd);
9044 __ cmpl(Rp, Rq);
9045 __ setb(Assembler::less, Rd);
9046 __ negl(Rd);
9047 %}
9049 ins_pipe(pipe_slow);
9050 %}
9052 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{
9053 match(Set dst (CmpLTMask dst zero));
9054 effect(DEF dst, KILL cr);
9055 ins_cost(100);
9057 format %{ "SAR $dst,31\t# cmpLTMask0" %}
9058 ins_encode %{
9059 __ sarl($dst$$Register, 31);
9060 %}
9061 ins_pipe(ialu_reg);
9062 %}
9064 /* better to save a register than avoid a branch */
9065 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
9066 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9067 effect(KILL cr);
9068 ins_cost(400);
9069 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t"
9070 "JGE done\n\t"
9071 "ADD $p,$y\n"
9072 "done: " %}
9073 ins_encode %{
9074 Register Rp = $p$$Register;
9075 Register Rq = $q$$Register;
9076 Register Ry = $y$$Register;
9077 Label done;
9078 __ subl(Rp, Rq);
9079 __ jccb(Assembler::greaterEqual, done);
9080 __ addl(Rp, Ry);
9081 __ bind(done);
9082 %}
9084 ins_pipe(pipe_cmplt);
9085 %}
9087 /* better to save a register than avoid a branch */
9088 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
9089 match(Set y (AndI (CmpLTMask p q) y));
9090 effect(KILL cr);
9092 ins_cost(300);
9094 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t"
9095 "JLT done\n\t"
9096 "XORL $y, $y\n"
9097 "done: " %}
9098 ins_encode %{
9099 Register Rp = $p$$Register;
9100 Register Rq = $q$$Register;
9101 Register Ry = $y$$Register;
9102 Label done;
9103 __ cmpl(Rp, Rq);
9104 __ jccb(Assembler::less, done);
9105 __ xorl(Ry, Ry);
9106 __ bind(done);
9107 %}
9109 ins_pipe(pipe_cmplt);
9110 %}
9112 /* If I enable this, I encourage spilling in the inner loop of compress.
9113 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{
9114 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9115 */
9117 //----------Long Instructions------------------------------------------------
9118 // Add Long Register with Register
9119 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9120 match(Set dst (AddL dst src));
9121 effect(KILL cr);
9122 ins_cost(200);
9123 format %{ "ADD $dst.lo,$src.lo\n\t"
9124 "ADC $dst.hi,$src.hi" %}
9125 opcode(0x03, 0x13);
9126 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9127 ins_pipe( ialu_reg_reg_long );
9128 %}
9130 // Add Long Register with Immediate
9131 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9132 match(Set dst (AddL dst src));
9133 effect(KILL cr);
9134 format %{ "ADD $dst.lo,$src.lo\n\t"
9135 "ADC $dst.hi,$src.hi" %}
9136 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9137 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9138 ins_pipe( ialu_reg_long );
9139 %}
9141 // Add Long Register with Memory
9142 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9143 match(Set dst (AddL dst (LoadL mem)));
9144 effect(KILL cr);
9145 ins_cost(125);
9146 format %{ "ADD $dst.lo,$mem\n\t"
9147 "ADC $dst.hi,$mem+4" %}
9148 opcode(0x03, 0x13);
9149 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9150 ins_pipe( ialu_reg_long_mem );
9151 %}
9153 // Subtract Long Register with Register.
9154 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9155 match(Set dst (SubL dst src));
9156 effect(KILL cr);
9157 ins_cost(200);
9158 format %{ "SUB $dst.lo,$src.lo\n\t"
9159 "SBB $dst.hi,$src.hi" %}
9160 opcode(0x2B, 0x1B);
9161 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9162 ins_pipe( ialu_reg_reg_long );
9163 %}
9165 // Subtract Long Register with Immediate
9166 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9167 match(Set dst (SubL dst src));
9168 effect(KILL cr);
9169 format %{ "SUB $dst.lo,$src.lo\n\t"
9170 "SBB $dst.hi,$src.hi" %}
9171 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9172 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9173 ins_pipe( ialu_reg_long );
9174 %}
9176 // Subtract Long Register with Memory
9177 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9178 match(Set dst (SubL dst (LoadL mem)));
9179 effect(KILL cr);
9180 ins_cost(125);
9181 format %{ "SUB $dst.lo,$mem\n\t"
9182 "SBB $dst.hi,$mem+4" %}
9183 opcode(0x2B, 0x1B);
9184 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9185 ins_pipe( ialu_reg_long_mem );
9186 %}
9188 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9189 match(Set dst (SubL zero dst));
9190 effect(KILL cr);
9191 ins_cost(300);
9192 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9193 ins_encode( neg_long(dst) );
9194 ins_pipe( ialu_reg_reg_long );
9195 %}
9197 // And Long Register with Register
9198 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9199 match(Set dst (AndL dst src));
9200 effect(KILL cr);
9201 format %{ "AND $dst.lo,$src.lo\n\t"
9202 "AND $dst.hi,$src.hi" %}
9203 opcode(0x23,0x23);
9204 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9205 ins_pipe( ialu_reg_reg_long );
9206 %}
9208 // And Long Register with Immediate
9209 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9210 match(Set dst (AndL dst src));
9211 effect(KILL cr);
9212 format %{ "AND $dst.lo,$src.lo\n\t"
9213 "AND $dst.hi,$src.hi" %}
9214 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9215 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9216 ins_pipe( ialu_reg_long );
9217 %}
9219 // And Long Register with Memory
9220 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9221 match(Set dst (AndL dst (LoadL mem)));
9222 effect(KILL cr);
9223 ins_cost(125);
9224 format %{ "AND $dst.lo,$mem\n\t"
9225 "AND $dst.hi,$mem+4" %}
9226 opcode(0x23, 0x23);
9227 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9228 ins_pipe( ialu_reg_long_mem );
9229 %}
9231 // Or Long Register with Register
9232 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9233 match(Set dst (OrL dst src));
9234 effect(KILL cr);
9235 format %{ "OR $dst.lo,$src.lo\n\t"
9236 "OR $dst.hi,$src.hi" %}
9237 opcode(0x0B,0x0B);
9238 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9239 ins_pipe( ialu_reg_reg_long );
9240 %}
9242 // Or Long Register with Immediate
9243 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9244 match(Set dst (OrL dst src));
9245 effect(KILL cr);
9246 format %{ "OR $dst.lo,$src.lo\n\t"
9247 "OR $dst.hi,$src.hi" %}
9248 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9249 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9250 ins_pipe( ialu_reg_long );
9251 %}
9253 // Or Long Register with Memory
9254 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9255 match(Set dst (OrL dst (LoadL mem)));
9256 effect(KILL cr);
9257 ins_cost(125);
9258 format %{ "OR $dst.lo,$mem\n\t"
9259 "OR $dst.hi,$mem+4" %}
9260 opcode(0x0B,0x0B);
9261 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9262 ins_pipe( ialu_reg_long_mem );
9263 %}
9265 // Xor Long Register with Register
9266 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9267 match(Set dst (XorL dst src));
9268 effect(KILL cr);
9269 format %{ "XOR $dst.lo,$src.lo\n\t"
9270 "XOR $dst.hi,$src.hi" %}
9271 opcode(0x33,0x33);
9272 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9273 ins_pipe( ialu_reg_reg_long );
9274 %}
9276 // Xor Long Register with Immediate -1
9277 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9278 match(Set dst (XorL dst imm));
9279 format %{ "NOT $dst.lo\n\t"
9280 "NOT $dst.hi" %}
9281 ins_encode %{
9282 __ notl($dst$$Register);
9283 __ notl(HIGH_FROM_LOW($dst$$Register));
9284 %}
9285 ins_pipe( ialu_reg_long );
9286 %}
9288 // Xor Long Register with Immediate
9289 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9290 match(Set dst (XorL dst src));
9291 effect(KILL cr);
9292 format %{ "XOR $dst.lo,$src.lo\n\t"
9293 "XOR $dst.hi,$src.hi" %}
9294 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9295 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9296 ins_pipe( ialu_reg_long );
9297 %}
9299 // Xor Long Register with Memory
9300 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9301 match(Set dst (XorL dst (LoadL mem)));
9302 effect(KILL cr);
9303 ins_cost(125);
9304 format %{ "XOR $dst.lo,$mem\n\t"
9305 "XOR $dst.hi,$mem+4" %}
9306 opcode(0x33,0x33);
9307 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9308 ins_pipe( ialu_reg_long_mem );
9309 %}
9311 // Shift Left Long by 1
9312 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9313 predicate(UseNewLongLShift);
9314 match(Set dst (LShiftL dst cnt));
9315 effect(KILL cr);
9316 ins_cost(100);
9317 format %{ "ADD $dst.lo,$dst.lo\n\t"
9318 "ADC $dst.hi,$dst.hi" %}
9319 ins_encode %{
9320 __ addl($dst$$Register,$dst$$Register);
9321 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9322 %}
9323 ins_pipe( ialu_reg_long );
9324 %}
9326 // Shift Left Long by 2
9327 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9328 predicate(UseNewLongLShift);
9329 match(Set dst (LShiftL dst cnt));
9330 effect(KILL cr);
9331 ins_cost(100);
9332 format %{ "ADD $dst.lo,$dst.lo\n\t"
9333 "ADC $dst.hi,$dst.hi\n\t"
9334 "ADD $dst.lo,$dst.lo\n\t"
9335 "ADC $dst.hi,$dst.hi" %}
9336 ins_encode %{
9337 __ addl($dst$$Register,$dst$$Register);
9338 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9339 __ addl($dst$$Register,$dst$$Register);
9340 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9341 %}
9342 ins_pipe( ialu_reg_long );
9343 %}
9345 // Shift Left Long by 3
9346 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9347 predicate(UseNewLongLShift);
9348 match(Set dst (LShiftL dst cnt));
9349 effect(KILL cr);
9350 ins_cost(100);
9351 format %{ "ADD $dst.lo,$dst.lo\n\t"
9352 "ADC $dst.hi,$dst.hi\n\t"
9353 "ADD $dst.lo,$dst.lo\n\t"
9354 "ADC $dst.hi,$dst.hi\n\t"
9355 "ADD $dst.lo,$dst.lo\n\t"
9356 "ADC $dst.hi,$dst.hi" %}
9357 ins_encode %{
9358 __ addl($dst$$Register,$dst$$Register);
9359 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9360 __ addl($dst$$Register,$dst$$Register);
9361 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9362 __ addl($dst$$Register,$dst$$Register);
9363 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9364 %}
9365 ins_pipe( ialu_reg_long );
9366 %}
9368 // Shift Left Long by 1-31
9369 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9370 match(Set dst (LShiftL dst cnt));
9371 effect(KILL cr);
9372 ins_cost(200);
9373 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9374 "SHL $dst.lo,$cnt" %}
9375 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9376 ins_encode( move_long_small_shift(dst,cnt) );
9377 ins_pipe( ialu_reg_long );
9378 %}
9380 // Shift Left Long by 32-63
9381 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9382 match(Set dst (LShiftL dst cnt));
9383 effect(KILL cr);
9384 ins_cost(300);
9385 format %{ "MOV $dst.hi,$dst.lo\n"
9386 "\tSHL $dst.hi,$cnt-32\n"
9387 "\tXOR $dst.lo,$dst.lo" %}
9388 opcode(0xC1, 0x4); /* C1 /4 ib */
9389 ins_encode( move_long_big_shift_clr(dst,cnt) );
9390 ins_pipe( ialu_reg_long );
9391 %}
9393 // Shift Left Long by variable
9394 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9395 match(Set dst (LShiftL dst shift));
9396 effect(KILL cr);
9397 ins_cost(500+200);
9398 size(17);
9399 format %{ "TEST $shift,32\n\t"
9400 "JEQ,s small\n\t"
9401 "MOV $dst.hi,$dst.lo\n\t"
9402 "XOR $dst.lo,$dst.lo\n"
9403 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9404 "SHL $dst.lo,$shift" %}
9405 ins_encode( shift_left_long( dst, shift ) );
9406 ins_pipe( pipe_slow );
9407 %}
9409 // Shift Right Long by 1-31
9410 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9411 match(Set dst (URShiftL dst cnt));
9412 effect(KILL cr);
9413 ins_cost(200);
9414 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9415 "SHR $dst.hi,$cnt" %}
9416 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9417 ins_encode( move_long_small_shift(dst,cnt) );
9418 ins_pipe( ialu_reg_long );
9419 %}
9421 // Shift Right Long by 32-63
9422 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9423 match(Set dst (URShiftL dst cnt));
9424 effect(KILL cr);
9425 ins_cost(300);
9426 format %{ "MOV $dst.lo,$dst.hi\n"
9427 "\tSHR $dst.lo,$cnt-32\n"
9428 "\tXOR $dst.hi,$dst.hi" %}
9429 opcode(0xC1, 0x5); /* C1 /5 ib */
9430 ins_encode( move_long_big_shift_clr(dst,cnt) );
9431 ins_pipe( ialu_reg_long );
9432 %}
9434 // Shift Right Long by variable
9435 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9436 match(Set dst (URShiftL dst shift));
9437 effect(KILL cr);
9438 ins_cost(600);
9439 size(17);
9440 format %{ "TEST $shift,32\n\t"
9441 "JEQ,s small\n\t"
9442 "MOV $dst.lo,$dst.hi\n\t"
9443 "XOR $dst.hi,$dst.hi\n"
9444 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9445 "SHR $dst.hi,$shift" %}
9446 ins_encode( shift_right_long( dst, shift ) );
9447 ins_pipe( pipe_slow );
9448 %}
9450 // Shift Right Long by 1-31
9451 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9452 match(Set dst (RShiftL dst cnt));
9453 effect(KILL cr);
9454 ins_cost(200);
9455 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9456 "SAR $dst.hi,$cnt" %}
9457 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9458 ins_encode( move_long_small_shift(dst,cnt) );
9459 ins_pipe( ialu_reg_long );
9460 %}
9462 // Shift Right Long by 32-63
9463 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9464 match(Set dst (RShiftL dst cnt));
9465 effect(KILL cr);
9466 ins_cost(300);
9467 format %{ "MOV $dst.lo,$dst.hi\n"
9468 "\tSAR $dst.lo,$cnt-32\n"
9469 "\tSAR $dst.hi,31" %}
9470 opcode(0xC1, 0x7); /* C1 /7 ib */
9471 ins_encode( move_long_big_shift_sign(dst,cnt) );
9472 ins_pipe( ialu_reg_long );
9473 %}
9475 // Shift Right arithmetic Long by variable
9476 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9477 match(Set dst (RShiftL dst shift));
9478 effect(KILL cr);
9479 ins_cost(600);
9480 size(18);
9481 format %{ "TEST $shift,32\n\t"
9482 "JEQ,s small\n\t"
9483 "MOV $dst.lo,$dst.hi\n\t"
9484 "SAR $dst.hi,31\n"
9485 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9486 "SAR $dst.hi,$shift" %}
9487 ins_encode( shift_right_arith_long( dst, shift ) );
9488 ins_pipe( pipe_slow );
9489 %}
9492 //----------Double Instructions------------------------------------------------
9493 // Double Math
9495 // Compare & branch
9497 // P6 version of float compare, sets condition codes in EFLAGS
9498 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9499 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9500 match(Set cr (CmpD src1 src2));
9501 effect(KILL rax);
9502 ins_cost(150);
9503 format %{ "FLD $src1\n\t"
9504 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9505 "JNP exit\n\t"
9506 "MOV ah,1 // saw a NaN, set CF\n\t"
9507 "SAHF\n"
9508 "exit:\tNOP // avoid branch to branch" %}
9509 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9510 ins_encode( Push_Reg_DPR(src1),
9511 OpcP, RegOpc(src2),
9512 cmpF_P6_fixup );
9513 ins_pipe( pipe_slow );
9514 %}
9516 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9517 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9518 match(Set cr (CmpD src1 src2));
9519 ins_cost(150);
9520 format %{ "FLD $src1\n\t"
9521 "FUCOMIP ST,$src2 // P6 instruction" %}
9522 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9523 ins_encode( Push_Reg_DPR(src1),
9524 OpcP, RegOpc(src2));
9525 ins_pipe( pipe_slow );
9526 %}
9528 // Compare & branch
9529 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9530 predicate(UseSSE<=1);
9531 match(Set cr (CmpD src1 src2));
9532 effect(KILL rax);
9533 ins_cost(200);
9534 format %{ "FLD $src1\n\t"
9535 "FCOMp $src2\n\t"
9536 "FNSTSW AX\n\t"
9537 "TEST AX,0x400\n\t"
9538 "JZ,s flags\n\t"
9539 "MOV AH,1\t# unordered treat as LT\n"
9540 "flags:\tSAHF" %}
9541 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9542 ins_encode( Push_Reg_DPR(src1),
9543 OpcP, RegOpc(src2),
9544 fpu_flags);
9545 ins_pipe( pipe_slow );
9546 %}
9548 // Compare vs zero into -1,0,1
9549 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9550 predicate(UseSSE<=1);
9551 match(Set dst (CmpD3 src1 zero));
9552 effect(KILL cr, KILL rax);
9553 ins_cost(280);
9554 format %{ "FTSTD $dst,$src1" %}
9555 opcode(0xE4, 0xD9);
9556 ins_encode( Push_Reg_DPR(src1),
9557 OpcS, OpcP, PopFPU,
9558 CmpF_Result(dst));
9559 ins_pipe( pipe_slow );
9560 %}
9562 // Compare into -1,0,1
9563 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9564 predicate(UseSSE<=1);
9565 match(Set dst (CmpD3 src1 src2));
9566 effect(KILL cr, KILL rax);
9567 ins_cost(300);
9568 format %{ "FCMPD $dst,$src1,$src2" %}
9569 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9570 ins_encode( Push_Reg_DPR(src1),
9571 OpcP, RegOpc(src2),
9572 CmpF_Result(dst));
9573 ins_pipe( pipe_slow );
9574 %}
9576 // float compare and set condition codes in EFLAGS by XMM regs
9577 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9578 predicate(UseSSE>=2);
9579 match(Set cr (CmpD src1 src2));
9580 ins_cost(145);
9581 format %{ "UCOMISD $src1,$src2\n\t"
9582 "JNP,s exit\n\t"
9583 "PUSHF\t# saw NaN, set CF\n\t"
9584 "AND [rsp], #0xffffff2b\n\t"
9585 "POPF\n"
9586 "exit:" %}
9587 ins_encode %{
9588 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9589 emit_cmpfp_fixup(_masm);
9590 %}
9591 ins_pipe( pipe_slow );
9592 %}
9594 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9595 predicate(UseSSE>=2);
9596 match(Set cr (CmpD src1 src2));
9597 ins_cost(100);
9598 format %{ "UCOMISD $src1,$src2" %}
9599 ins_encode %{
9600 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9601 %}
9602 ins_pipe( pipe_slow );
9603 %}
9605 // float compare and set condition codes in EFLAGS by XMM regs
9606 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9607 predicate(UseSSE>=2);
9608 match(Set cr (CmpD src1 (LoadD src2)));
9609 ins_cost(145);
9610 format %{ "UCOMISD $src1,$src2\n\t"
9611 "JNP,s exit\n\t"
9612 "PUSHF\t# saw NaN, set CF\n\t"
9613 "AND [rsp], #0xffffff2b\n\t"
9614 "POPF\n"
9615 "exit:" %}
9616 ins_encode %{
9617 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9618 emit_cmpfp_fixup(_masm);
9619 %}
9620 ins_pipe( pipe_slow );
9621 %}
9623 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9624 predicate(UseSSE>=2);
9625 match(Set cr (CmpD src1 (LoadD src2)));
9626 ins_cost(100);
9627 format %{ "UCOMISD $src1,$src2" %}
9628 ins_encode %{
9629 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9630 %}
9631 ins_pipe( pipe_slow );
9632 %}
9634 // Compare into -1,0,1 in XMM
9635 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9636 predicate(UseSSE>=2);
9637 match(Set dst (CmpD3 src1 src2));
9638 effect(KILL cr);
9639 ins_cost(255);
9640 format %{ "UCOMISD $src1, $src2\n\t"
9641 "MOV $dst, #-1\n\t"
9642 "JP,s done\n\t"
9643 "JB,s done\n\t"
9644 "SETNE $dst\n\t"
9645 "MOVZB $dst, $dst\n"
9646 "done:" %}
9647 ins_encode %{
9648 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9649 emit_cmpfp3(_masm, $dst$$Register);
9650 %}
9651 ins_pipe( pipe_slow );
9652 %}
9654 // Compare into -1,0,1 in XMM and memory
9655 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9656 predicate(UseSSE>=2);
9657 match(Set dst (CmpD3 src1 (LoadD src2)));
9658 effect(KILL cr);
9659 ins_cost(275);
9660 format %{ "UCOMISD $src1, $src2\n\t"
9661 "MOV $dst, #-1\n\t"
9662 "JP,s done\n\t"
9663 "JB,s done\n\t"
9664 "SETNE $dst\n\t"
9665 "MOVZB $dst, $dst\n"
9666 "done:" %}
9667 ins_encode %{
9668 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9669 emit_cmpfp3(_masm, $dst$$Register);
9670 %}
9671 ins_pipe( pipe_slow );
9672 %}
9675 instruct subDPR_reg(regDPR dst, regDPR src) %{
9676 predicate (UseSSE <=1);
9677 match(Set dst (SubD dst src));
9679 format %{ "FLD $src\n\t"
9680 "DSUBp $dst,ST" %}
9681 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9682 ins_cost(150);
9683 ins_encode( Push_Reg_DPR(src),
9684 OpcP, RegOpc(dst) );
9685 ins_pipe( fpu_reg_reg );
9686 %}
9688 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9689 predicate (UseSSE <=1);
9690 match(Set dst (RoundDouble (SubD src1 src2)));
9691 ins_cost(250);
9693 format %{ "FLD $src2\n\t"
9694 "DSUB ST,$src1\n\t"
9695 "FSTP_D $dst\t# D-round" %}
9696 opcode(0xD8, 0x5);
9697 ins_encode( Push_Reg_DPR(src2),
9698 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9699 ins_pipe( fpu_mem_reg_reg );
9700 %}
9703 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9704 predicate (UseSSE <=1);
9705 match(Set dst (SubD dst (LoadD src)));
9706 ins_cost(150);
9708 format %{ "FLD $src\n\t"
9709 "DSUBp $dst,ST" %}
9710 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9711 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9712 OpcP, RegOpc(dst) );
9713 ins_pipe( fpu_reg_mem );
9714 %}
9716 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9717 predicate (UseSSE<=1);
9718 match(Set dst (AbsD src));
9719 ins_cost(100);
9720 format %{ "FABS" %}
9721 opcode(0xE1, 0xD9);
9722 ins_encode( OpcS, OpcP );
9723 ins_pipe( fpu_reg_reg );
9724 %}
9726 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9727 predicate(UseSSE<=1);
9728 match(Set dst (NegD src));
9729 ins_cost(100);
9730 format %{ "FCHS" %}
9731 opcode(0xE0, 0xD9);
9732 ins_encode( OpcS, OpcP );
9733 ins_pipe( fpu_reg_reg );
9734 %}
9736 instruct addDPR_reg(regDPR dst, regDPR src) %{
9737 predicate(UseSSE<=1);
9738 match(Set dst (AddD dst src));
9739 format %{ "FLD $src\n\t"
9740 "DADD $dst,ST" %}
9741 size(4);
9742 ins_cost(150);
9743 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9744 ins_encode( Push_Reg_DPR(src),
9745 OpcP, RegOpc(dst) );
9746 ins_pipe( fpu_reg_reg );
9747 %}
9750 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9751 predicate(UseSSE<=1);
9752 match(Set dst (RoundDouble (AddD src1 src2)));
9753 ins_cost(250);
9755 format %{ "FLD $src2\n\t"
9756 "DADD ST,$src1\n\t"
9757 "FSTP_D $dst\t# D-round" %}
9758 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9759 ins_encode( Push_Reg_DPR(src2),
9760 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9761 ins_pipe( fpu_mem_reg_reg );
9762 %}
9765 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9766 predicate(UseSSE<=1);
9767 match(Set dst (AddD dst (LoadD src)));
9768 ins_cost(150);
9770 format %{ "FLD $src\n\t"
9771 "DADDp $dst,ST" %}
9772 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9773 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9774 OpcP, RegOpc(dst) );
9775 ins_pipe( fpu_reg_mem );
9776 %}
9778 // add-to-memory
9779 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9780 predicate(UseSSE<=1);
9781 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9782 ins_cost(150);
9784 format %{ "FLD_D $dst\n\t"
9785 "DADD ST,$src\n\t"
9786 "FST_D $dst" %}
9787 opcode(0xDD, 0x0);
9788 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9789 Opcode(0xD8), RegOpc(src),
9790 set_instruction_start,
9791 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9792 ins_pipe( fpu_reg_mem );
9793 %}
9795 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9796 predicate(UseSSE<=1);
9797 match(Set dst (AddD dst con));
9798 ins_cost(125);
9799 format %{ "FLD1\n\t"
9800 "DADDp $dst,ST" %}
9801 ins_encode %{
9802 __ fld1();
9803 __ faddp($dst$$reg);
9804 %}
9805 ins_pipe(fpu_reg);
9806 %}
9808 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9809 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9810 match(Set dst (AddD dst con));
9811 ins_cost(200);
9812 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9813 "DADDp $dst,ST" %}
9814 ins_encode %{
9815 __ fld_d($constantaddress($con));
9816 __ faddp($dst$$reg);
9817 %}
9818 ins_pipe(fpu_reg_mem);
9819 %}
9821 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9822 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9823 match(Set dst (RoundDouble (AddD src con)));
9824 ins_cost(200);
9825 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9826 "DADD ST,$src\n\t"
9827 "FSTP_D $dst\t# D-round" %}
9828 ins_encode %{
9829 __ fld_d($constantaddress($con));
9830 __ fadd($src$$reg);
9831 __ fstp_d(Address(rsp, $dst$$disp));
9832 %}
9833 ins_pipe(fpu_mem_reg_con);
9834 %}
9836 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9837 predicate(UseSSE<=1);
9838 match(Set dst (MulD dst src));
9839 format %{ "FLD $src\n\t"
9840 "DMULp $dst,ST" %}
9841 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9842 ins_cost(150);
9843 ins_encode( Push_Reg_DPR(src),
9844 OpcP, RegOpc(dst) );
9845 ins_pipe( fpu_reg_reg );
9846 %}
9848 // Strict FP instruction biases argument before multiply then
9849 // biases result to avoid double rounding of subnormals.
9850 //
9851 // scale arg1 by multiplying arg1 by 2^(-15360)
9852 // load arg2
9853 // multiply scaled arg1 by arg2
9854 // rescale product by 2^(15360)
9855 //
9856 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9857 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9858 match(Set dst (MulD dst src));
9859 ins_cost(1); // Select this instruction for all strict FP double multiplies
9861 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9862 "DMULp $dst,ST\n\t"
9863 "FLD $src\n\t"
9864 "DMULp $dst,ST\n\t"
9865 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9866 "DMULp $dst,ST\n\t" %}
9867 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9868 ins_encode( strictfp_bias1(dst),
9869 Push_Reg_DPR(src),
9870 OpcP, RegOpc(dst),
9871 strictfp_bias2(dst) );
9872 ins_pipe( fpu_reg_reg );
9873 %}
9875 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9876 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9877 match(Set dst (MulD dst con));
9878 ins_cost(200);
9879 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9880 "DMULp $dst,ST" %}
9881 ins_encode %{
9882 __ fld_d($constantaddress($con));
9883 __ fmulp($dst$$reg);
9884 %}
9885 ins_pipe(fpu_reg_mem);
9886 %}
9889 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9890 predicate( UseSSE<=1 );
9891 match(Set dst (MulD dst (LoadD src)));
9892 ins_cost(200);
9893 format %{ "FLD_D $src\n\t"
9894 "DMULp $dst,ST" %}
9895 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9896 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9897 OpcP, RegOpc(dst) );
9898 ins_pipe( fpu_reg_mem );
9899 %}
9901 //
9902 // Cisc-alternate to reg-reg multiply
9903 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9904 predicate( UseSSE<=1 );
9905 match(Set dst (MulD src (LoadD mem)));
9906 ins_cost(250);
9907 format %{ "FLD_D $mem\n\t"
9908 "DMUL ST,$src\n\t"
9909 "FSTP_D $dst" %}
9910 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9911 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9912 OpcReg_FPR(src),
9913 Pop_Reg_DPR(dst) );
9914 ins_pipe( fpu_reg_reg_mem );
9915 %}
9918 // MACRO3 -- addDPR a mulDPR
9919 // This instruction is a '2-address' instruction in that the result goes
9920 // back to src2. This eliminates a move from the macro; possibly the
9921 // register allocator will have to add it back (and maybe not).
9922 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9923 predicate( UseSSE<=1 );
9924 match(Set src2 (AddD (MulD src0 src1) src2));
9925 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9926 "DMUL ST,$src1\n\t"
9927 "DADDp $src2,ST" %}
9928 ins_cost(250);
9929 opcode(0xDD); /* LoadD DD /0 */
9930 ins_encode( Push_Reg_FPR(src0),
9931 FMul_ST_reg(src1),
9932 FAddP_reg_ST(src2) );
9933 ins_pipe( fpu_reg_reg_reg );
9934 %}
9937 // MACRO3 -- subDPR a mulDPR
9938 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9939 predicate( UseSSE<=1 );
9940 match(Set src2 (SubD (MulD src0 src1) src2));
9941 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9942 "DMUL ST,$src1\n\t"
9943 "DSUBRp $src2,ST" %}
9944 ins_cost(250);
9945 ins_encode( Push_Reg_FPR(src0),
9946 FMul_ST_reg(src1),
9947 Opcode(0xDE), Opc_plus(0xE0,src2));
9948 ins_pipe( fpu_reg_reg_reg );
9949 %}
9952 instruct divDPR_reg(regDPR dst, regDPR src) %{
9953 predicate( UseSSE<=1 );
9954 match(Set dst (DivD dst src));
9956 format %{ "FLD $src\n\t"
9957 "FDIVp $dst,ST" %}
9958 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9959 ins_cost(150);
9960 ins_encode( Push_Reg_DPR(src),
9961 OpcP, RegOpc(dst) );
9962 ins_pipe( fpu_reg_reg );
9963 %}
9965 // Strict FP instruction biases argument before division then
9966 // biases result, to avoid double rounding of subnormals.
9967 //
9968 // scale dividend by multiplying dividend by 2^(-15360)
9969 // load divisor
9970 // divide scaled dividend by divisor
9971 // rescale quotient by 2^(15360)
9972 //
9973 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9974 predicate (UseSSE<=1);
9975 match(Set dst (DivD dst src));
9976 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9977 ins_cost(01);
9979 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9980 "DMULp $dst,ST\n\t"
9981 "FLD $src\n\t"
9982 "FDIVp $dst,ST\n\t"
9983 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9984 "DMULp $dst,ST\n\t" %}
9985 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9986 ins_encode( strictfp_bias1(dst),
9987 Push_Reg_DPR(src),
9988 OpcP, RegOpc(dst),
9989 strictfp_bias2(dst) );
9990 ins_pipe( fpu_reg_reg );
9991 %}
9993 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9994 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9995 match(Set dst (RoundDouble (DivD src1 src2)));
9997 format %{ "FLD $src1\n\t"
9998 "FDIV ST,$src2\n\t"
9999 "FSTP_D $dst\t# D-round" %}
10000 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
10001 ins_encode( Push_Reg_DPR(src1),
10002 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
10003 ins_pipe( fpu_mem_reg_reg );
10004 %}
10007 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
10008 predicate(UseSSE<=1);
10009 match(Set dst (ModD dst src));
10010 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10012 format %{ "DMOD $dst,$src" %}
10013 ins_cost(250);
10014 ins_encode(Push_Reg_Mod_DPR(dst, src),
10015 emitModDPR(),
10016 Push_Result_Mod_DPR(src),
10017 Pop_Reg_DPR(dst));
10018 ins_pipe( pipe_slow );
10019 %}
10021 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
10022 predicate(UseSSE>=2);
10023 match(Set dst (ModD src0 src1));
10024 effect(KILL rax, KILL cr);
10026 format %{ "SUB ESP,8\t # DMOD\n"
10027 "\tMOVSD [ESP+0],$src1\n"
10028 "\tFLD_D [ESP+0]\n"
10029 "\tMOVSD [ESP+0],$src0\n"
10030 "\tFLD_D [ESP+0]\n"
10031 "loop:\tFPREM\n"
10032 "\tFWAIT\n"
10033 "\tFNSTSW AX\n"
10034 "\tSAHF\n"
10035 "\tJP loop\n"
10036 "\tFSTP_D [ESP+0]\n"
10037 "\tMOVSD $dst,[ESP+0]\n"
10038 "\tADD ESP,8\n"
10039 "\tFSTP ST0\t # Restore FPU Stack"
10040 %}
10041 ins_cost(250);
10042 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
10043 ins_pipe( pipe_slow );
10044 %}
10046 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
10047 predicate (UseSSE<=1);
10048 match(Set dst (SinD src));
10049 ins_cost(1800);
10050 format %{ "DSIN $dst" %}
10051 opcode(0xD9, 0xFE);
10052 ins_encode( OpcP, OpcS );
10053 ins_pipe( pipe_slow );
10054 %}
10056 instruct sinD_reg(regD dst, eFlagsReg cr) %{
10057 predicate (UseSSE>=2);
10058 match(Set dst (SinD dst));
10059 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10060 ins_cost(1800);
10061 format %{ "DSIN $dst" %}
10062 opcode(0xD9, 0xFE);
10063 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10064 ins_pipe( pipe_slow );
10065 %}
10067 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
10068 predicate (UseSSE<=1);
10069 match(Set dst (CosD src));
10070 ins_cost(1800);
10071 format %{ "DCOS $dst" %}
10072 opcode(0xD9, 0xFF);
10073 ins_encode( OpcP, OpcS );
10074 ins_pipe( pipe_slow );
10075 %}
10077 instruct cosD_reg(regD dst, eFlagsReg cr) %{
10078 predicate (UseSSE>=2);
10079 match(Set dst (CosD dst));
10080 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10081 ins_cost(1800);
10082 format %{ "DCOS $dst" %}
10083 opcode(0xD9, 0xFF);
10084 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10085 ins_pipe( pipe_slow );
10086 %}
10088 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
10089 predicate (UseSSE<=1);
10090 match(Set dst(TanD src));
10091 format %{ "DTAN $dst" %}
10092 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10093 Opcode(0xDD), Opcode(0xD8)); // fstp st
10094 ins_pipe( pipe_slow );
10095 %}
10097 instruct tanD_reg(regD dst, eFlagsReg cr) %{
10098 predicate (UseSSE>=2);
10099 match(Set dst(TanD dst));
10100 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10101 format %{ "DTAN $dst" %}
10102 ins_encode( Push_SrcD(dst),
10103 Opcode(0xD9), Opcode(0xF2), // fptan
10104 Opcode(0xDD), Opcode(0xD8), // fstp st
10105 Push_ResultD(dst) );
10106 ins_pipe( pipe_slow );
10107 %}
10109 instruct atanDPR_reg(regDPR dst, regDPR src) %{
10110 predicate (UseSSE<=1);
10111 match(Set dst(AtanD dst src));
10112 format %{ "DATA $dst,$src" %}
10113 opcode(0xD9, 0xF3);
10114 ins_encode( Push_Reg_DPR(src),
10115 OpcP, OpcS, RegOpc(dst) );
10116 ins_pipe( pipe_slow );
10117 %}
10119 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
10120 predicate (UseSSE>=2);
10121 match(Set dst(AtanD dst src));
10122 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10123 format %{ "DATA $dst,$src" %}
10124 opcode(0xD9, 0xF3);
10125 ins_encode( Push_SrcD(src),
10126 OpcP, OpcS, Push_ResultD(dst) );
10127 ins_pipe( pipe_slow );
10128 %}
10130 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
10131 predicate (UseSSE<=1);
10132 match(Set dst (SqrtD src));
10133 format %{ "DSQRT $dst,$src" %}
10134 opcode(0xFA, 0xD9);
10135 ins_encode( Push_Reg_DPR(src),
10136 OpcS, OpcP, Pop_Reg_DPR(dst) );
10137 ins_pipe( pipe_slow );
10138 %}
10140 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10141 predicate (UseSSE<=1);
10142 match(Set Y (PowD X Y)); // Raise X to the Yth power
10143 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10144 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
10145 ins_encode %{
10146 __ subptr(rsp, 8);
10147 __ fld_s($X$$reg - 1);
10148 __ fast_pow();
10149 __ addptr(rsp, 8);
10150 %}
10151 ins_pipe( pipe_slow );
10152 %}
10154 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10155 predicate (UseSSE>=2);
10156 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10157 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10158 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
10159 ins_encode %{
10160 __ subptr(rsp, 8);
10161 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
10162 __ fld_d(Address(rsp, 0));
10163 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
10164 __ fld_d(Address(rsp, 0));
10165 __ fast_pow();
10166 __ fstp_d(Address(rsp, 0));
10167 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10168 __ addptr(rsp, 8);
10169 %}
10170 ins_pipe( pipe_slow );
10171 %}
10174 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10175 predicate (UseSSE<=1);
10176 match(Set dpr1 (ExpD dpr1));
10177 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10178 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
10179 ins_encode %{
10180 __ fast_exp();
10181 %}
10182 ins_pipe( pipe_slow );
10183 %}
10185 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10186 predicate (UseSSE>=2);
10187 match(Set dst (ExpD src));
10188 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10189 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
10190 ins_encode %{
10191 __ subptr(rsp, 8);
10192 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10193 __ fld_d(Address(rsp, 0));
10194 __ fast_exp();
10195 __ fstp_d(Address(rsp, 0));
10196 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10197 __ addptr(rsp, 8);
10198 %}
10199 ins_pipe( pipe_slow );
10200 %}
10202 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10203 predicate (UseSSE<=1);
10204 // The source Double operand on FPU stack
10205 match(Set dst (Log10D src));
10206 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10207 // fxch ; swap ST(0) with ST(1)
10208 // fyl2x ; compute log_10(2) * log_2(x)
10209 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10210 "FXCH \n\t"
10211 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10212 %}
10213 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10214 Opcode(0xD9), Opcode(0xC9), // fxch
10215 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10217 ins_pipe( pipe_slow );
10218 %}
10220 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10221 predicate (UseSSE>=2);
10222 effect(KILL cr);
10223 match(Set dst (Log10D src));
10224 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10225 // fyl2x ; compute log_10(2) * log_2(x)
10226 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10227 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10228 %}
10229 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10230 Push_SrcD(src),
10231 Opcode(0xD9), Opcode(0xF1), // fyl2x
10232 Push_ResultD(dst));
10234 ins_pipe( pipe_slow );
10235 %}
10237 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10238 predicate (UseSSE<=1);
10239 // The source Double operand on FPU stack
10240 match(Set dst (LogD src));
10241 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10242 // fxch ; swap ST(0) with ST(1)
10243 // fyl2x ; compute log_e(2) * log_2(x)
10244 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10245 "FXCH \n\t"
10246 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10247 %}
10248 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10249 Opcode(0xD9), Opcode(0xC9), // fxch
10250 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10252 ins_pipe( pipe_slow );
10253 %}
10255 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10256 predicate (UseSSE>=2);
10257 effect(KILL cr);
10258 // The source and result Double operands in XMM registers
10259 match(Set dst (LogD src));
10260 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10261 // fyl2x ; compute log_e(2) * log_2(x)
10262 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10263 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10264 %}
10265 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10266 Push_SrcD(src),
10267 Opcode(0xD9), Opcode(0xF1), // fyl2x
10268 Push_ResultD(dst));
10269 ins_pipe( pipe_slow );
10270 %}
10272 //-------------Float Instructions-------------------------------
10273 // Float Math
10275 // Code for float compare:
10276 // fcompp();
10277 // fwait(); fnstsw_ax();
10278 // sahf();
10279 // movl(dst, unordered_result);
10280 // jcc(Assembler::parity, exit);
10281 // movl(dst, less_result);
10282 // jcc(Assembler::below, exit);
10283 // movl(dst, equal_result);
10284 // jcc(Assembler::equal, exit);
10285 // movl(dst, greater_result);
10286 // exit:
10288 // P6 version of float compare, sets condition codes in EFLAGS
10289 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10290 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10291 match(Set cr (CmpF src1 src2));
10292 effect(KILL rax);
10293 ins_cost(150);
10294 format %{ "FLD $src1\n\t"
10295 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10296 "JNP exit\n\t"
10297 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10298 "SAHF\n"
10299 "exit:\tNOP // avoid branch to branch" %}
10300 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10301 ins_encode( Push_Reg_DPR(src1),
10302 OpcP, RegOpc(src2),
10303 cmpF_P6_fixup );
10304 ins_pipe( pipe_slow );
10305 %}
10307 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10308 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10309 match(Set cr (CmpF src1 src2));
10310 ins_cost(100);
10311 format %{ "FLD $src1\n\t"
10312 "FUCOMIP ST,$src2 // P6 instruction" %}
10313 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10314 ins_encode( Push_Reg_DPR(src1),
10315 OpcP, RegOpc(src2));
10316 ins_pipe( pipe_slow );
10317 %}
10320 // Compare & branch
10321 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10322 predicate(UseSSE == 0);
10323 match(Set cr (CmpF src1 src2));
10324 effect(KILL rax);
10325 ins_cost(200);
10326 format %{ "FLD $src1\n\t"
10327 "FCOMp $src2\n\t"
10328 "FNSTSW AX\n\t"
10329 "TEST AX,0x400\n\t"
10330 "JZ,s flags\n\t"
10331 "MOV AH,1\t# unordered treat as LT\n"
10332 "flags:\tSAHF" %}
10333 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10334 ins_encode( Push_Reg_DPR(src1),
10335 OpcP, RegOpc(src2),
10336 fpu_flags);
10337 ins_pipe( pipe_slow );
10338 %}
10340 // Compare vs zero into -1,0,1
10341 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10342 predicate(UseSSE == 0);
10343 match(Set dst (CmpF3 src1 zero));
10344 effect(KILL cr, KILL rax);
10345 ins_cost(280);
10346 format %{ "FTSTF $dst,$src1" %}
10347 opcode(0xE4, 0xD9);
10348 ins_encode( Push_Reg_DPR(src1),
10349 OpcS, OpcP, PopFPU,
10350 CmpF_Result(dst));
10351 ins_pipe( pipe_slow );
10352 %}
10354 // Compare into -1,0,1
10355 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10356 predicate(UseSSE == 0);
10357 match(Set dst (CmpF3 src1 src2));
10358 effect(KILL cr, KILL rax);
10359 ins_cost(300);
10360 format %{ "FCMPF $dst,$src1,$src2" %}
10361 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10362 ins_encode( Push_Reg_DPR(src1),
10363 OpcP, RegOpc(src2),
10364 CmpF_Result(dst));
10365 ins_pipe( pipe_slow );
10366 %}
10368 // float compare and set condition codes in EFLAGS by XMM regs
10369 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10370 predicate(UseSSE>=1);
10371 match(Set cr (CmpF src1 src2));
10372 ins_cost(145);
10373 format %{ "UCOMISS $src1,$src2\n\t"
10374 "JNP,s exit\n\t"
10375 "PUSHF\t# saw NaN, set CF\n\t"
10376 "AND [rsp], #0xffffff2b\n\t"
10377 "POPF\n"
10378 "exit:" %}
10379 ins_encode %{
10380 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10381 emit_cmpfp_fixup(_masm);
10382 %}
10383 ins_pipe( pipe_slow );
10384 %}
10386 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10387 predicate(UseSSE>=1);
10388 match(Set cr (CmpF src1 src2));
10389 ins_cost(100);
10390 format %{ "UCOMISS $src1,$src2" %}
10391 ins_encode %{
10392 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10393 %}
10394 ins_pipe( pipe_slow );
10395 %}
10397 // float compare and set condition codes in EFLAGS by XMM regs
10398 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10399 predicate(UseSSE>=1);
10400 match(Set cr (CmpF src1 (LoadF src2)));
10401 ins_cost(165);
10402 format %{ "UCOMISS $src1,$src2\n\t"
10403 "JNP,s exit\n\t"
10404 "PUSHF\t# saw NaN, set CF\n\t"
10405 "AND [rsp], #0xffffff2b\n\t"
10406 "POPF\n"
10407 "exit:" %}
10408 ins_encode %{
10409 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10410 emit_cmpfp_fixup(_masm);
10411 %}
10412 ins_pipe( pipe_slow );
10413 %}
10415 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10416 predicate(UseSSE>=1);
10417 match(Set cr (CmpF src1 (LoadF src2)));
10418 ins_cost(100);
10419 format %{ "UCOMISS $src1,$src2" %}
10420 ins_encode %{
10421 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10422 %}
10423 ins_pipe( pipe_slow );
10424 %}
10426 // Compare into -1,0,1 in XMM
10427 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10428 predicate(UseSSE>=1);
10429 match(Set dst (CmpF3 src1 src2));
10430 effect(KILL cr);
10431 ins_cost(255);
10432 format %{ "UCOMISS $src1, $src2\n\t"
10433 "MOV $dst, #-1\n\t"
10434 "JP,s done\n\t"
10435 "JB,s done\n\t"
10436 "SETNE $dst\n\t"
10437 "MOVZB $dst, $dst\n"
10438 "done:" %}
10439 ins_encode %{
10440 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10441 emit_cmpfp3(_masm, $dst$$Register);
10442 %}
10443 ins_pipe( pipe_slow );
10444 %}
10446 // Compare into -1,0,1 in XMM and memory
10447 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10448 predicate(UseSSE>=1);
10449 match(Set dst (CmpF3 src1 (LoadF src2)));
10450 effect(KILL cr);
10451 ins_cost(275);
10452 format %{ "UCOMISS $src1, $src2\n\t"
10453 "MOV $dst, #-1\n\t"
10454 "JP,s done\n\t"
10455 "JB,s done\n\t"
10456 "SETNE $dst\n\t"
10457 "MOVZB $dst, $dst\n"
10458 "done:" %}
10459 ins_encode %{
10460 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10461 emit_cmpfp3(_masm, $dst$$Register);
10462 %}
10463 ins_pipe( pipe_slow );
10464 %}
10466 // Spill to obtain 24-bit precision
10467 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10468 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10469 match(Set dst (SubF src1 src2));
10471 format %{ "FSUB $dst,$src1 - $src2" %}
10472 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10473 ins_encode( Push_Reg_FPR(src1),
10474 OpcReg_FPR(src2),
10475 Pop_Mem_FPR(dst) );
10476 ins_pipe( fpu_mem_reg_reg );
10477 %}
10478 //
10479 // This instruction does not round to 24-bits
10480 instruct subFPR_reg(regFPR dst, regFPR src) %{
10481 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10482 match(Set dst (SubF dst src));
10484 format %{ "FSUB $dst,$src" %}
10485 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10486 ins_encode( Push_Reg_FPR(src),
10487 OpcP, RegOpc(dst) );
10488 ins_pipe( fpu_reg_reg );
10489 %}
10491 // Spill to obtain 24-bit precision
10492 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10493 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10494 match(Set dst (AddF src1 src2));
10496 format %{ "FADD $dst,$src1,$src2" %}
10497 opcode(0xD8, 0x0); /* D8 C0+i */
10498 ins_encode( Push_Reg_FPR(src2),
10499 OpcReg_FPR(src1),
10500 Pop_Mem_FPR(dst) );
10501 ins_pipe( fpu_mem_reg_reg );
10502 %}
10503 //
10504 // This instruction does not round to 24-bits
10505 instruct addFPR_reg(regFPR dst, regFPR src) %{
10506 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10507 match(Set dst (AddF dst src));
10509 format %{ "FLD $src\n\t"
10510 "FADDp $dst,ST" %}
10511 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10512 ins_encode( Push_Reg_FPR(src),
10513 OpcP, RegOpc(dst) );
10514 ins_pipe( fpu_reg_reg );
10515 %}
10517 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10518 predicate(UseSSE==0);
10519 match(Set dst (AbsF src));
10520 ins_cost(100);
10521 format %{ "FABS" %}
10522 opcode(0xE1, 0xD9);
10523 ins_encode( OpcS, OpcP );
10524 ins_pipe( fpu_reg_reg );
10525 %}
10527 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10528 predicate(UseSSE==0);
10529 match(Set dst (NegF src));
10530 ins_cost(100);
10531 format %{ "FCHS" %}
10532 opcode(0xE0, 0xD9);
10533 ins_encode( OpcS, OpcP );
10534 ins_pipe( fpu_reg_reg );
10535 %}
10537 // Cisc-alternate to addFPR_reg
10538 // Spill to obtain 24-bit precision
10539 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10540 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10541 match(Set dst (AddF src1 (LoadF src2)));
10543 format %{ "FLD $src2\n\t"
10544 "FADD ST,$src1\n\t"
10545 "FSTP_S $dst" %}
10546 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10547 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10548 OpcReg_FPR(src1),
10549 Pop_Mem_FPR(dst) );
10550 ins_pipe( fpu_mem_reg_mem );
10551 %}
10552 //
10553 // Cisc-alternate to addFPR_reg
10554 // This instruction does not round to 24-bits
10555 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10556 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10557 match(Set dst (AddF dst (LoadF src)));
10559 format %{ "FADD $dst,$src" %}
10560 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10561 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10562 OpcP, RegOpc(dst) );
10563 ins_pipe( fpu_reg_mem );
10564 %}
10566 // // Following two instructions for _222_mpegaudio
10567 // Spill to obtain 24-bit precision
10568 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10569 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10570 match(Set dst (AddF src1 src2));
10572 format %{ "FADD $dst,$src1,$src2" %}
10573 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10574 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10575 OpcReg_FPR(src2),
10576 Pop_Mem_FPR(dst) );
10577 ins_pipe( fpu_mem_reg_mem );
10578 %}
10580 // Cisc-spill variant
10581 // Spill to obtain 24-bit precision
10582 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10583 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10584 match(Set dst (AddF src1 (LoadF src2)));
10586 format %{ "FADD $dst,$src1,$src2 cisc" %}
10587 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10588 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10589 set_instruction_start,
10590 OpcP, RMopc_Mem(secondary,src1),
10591 Pop_Mem_FPR(dst) );
10592 ins_pipe( fpu_mem_mem_mem );
10593 %}
10595 // Spill to obtain 24-bit precision
10596 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10597 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10598 match(Set dst (AddF src1 src2));
10600 format %{ "FADD $dst,$src1,$src2" %}
10601 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10602 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10603 set_instruction_start,
10604 OpcP, RMopc_Mem(secondary,src1),
10605 Pop_Mem_FPR(dst) );
10606 ins_pipe( fpu_mem_mem_mem );
10607 %}
10610 // Spill to obtain 24-bit precision
10611 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10612 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10613 match(Set dst (AddF src con));
10614 format %{ "FLD $src\n\t"
10615 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10616 "FSTP_S $dst" %}
10617 ins_encode %{
10618 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10619 __ fadd_s($constantaddress($con));
10620 __ fstp_s(Address(rsp, $dst$$disp));
10621 %}
10622 ins_pipe(fpu_mem_reg_con);
10623 %}
10624 //
10625 // This instruction does not round to 24-bits
10626 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10627 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10628 match(Set dst (AddF src con));
10629 format %{ "FLD $src\n\t"
10630 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10631 "FSTP $dst" %}
10632 ins_encode %{
10633 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10634 __ fadd_s($constantaddress($con));
10635 __ fstp_d($dst$$reg);
10636 %}
10637 ins_pipe(fpu_reg_reg_con);
10638 %}
10640 // Spill to obtain 24-bit precision
10641 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10642 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10643 match(Set dst (MulF src1 src2));
10645 format %{ "FLD $src1\n\t"
10646 "FMUL $src2\n\t"
10647 "FSTP_S $dst" %}
10648 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10649 ins_encode( Push_Reg_FPR(src1),
10650 OpcReg_FPR(src2),
10651 Pop_Mem_FPR(dst) );
10652 ins_pipe( fpu_mem_reg_reg );
10653 %}
10654 //
10655 // This instruction does not round to 24-bits
10656 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10657 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10658 match(Set dst (MulF src1 src2));
10660 format %{ "FLD $src1\n\t"
10661 "FMUL $src2\n\t"
10662 "FSTP_S $dst" %}
10663 opcode(0xD8, 0x1); /* D8 C8+i */
10664 ins_encode( Push_Reg_FPR(src2),
10665 OpcReg_FPR(src1),
10666 Pop_Reg_FPR(dst) );
10667 ins_pipe( fpu_reg_reg_reg );
10668 %}
10671 // Spill to obtain 24-bit precision
10672 // Cisc-alternate to reg-reg multiply
10673 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10674 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10675 match(Set dst (MulF src1 (LoadF src2)));
10677 format %{ "FLD_S $src2\n\t"
10678 "FMUL $src1\n\t"
10679 "FSTP_S $dst" %}
10680 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10681 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10682 OpcReg_FPR(src1),
10683 Pop_Mem_FPR(dst) );
10684 ins_pipe( fpu_mem_reg_mem );
10685 %}
10686 //
10687 // This instruction does not round to 24-bits
10688 // Cisc-alternate to reg-reg multiply
10689 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10690 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10691 match(Set dst (MulF src1 (LoadF src2)));
10693 format %{ "FMUL $dst,$src1,$src2" %}
10694 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10695 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10696 OpcReg_FPR(src1),
10697 Pop_Reg_FPR(dst) );
10698 ins_pipe( fpu_reg_reg_mem );
10699 %}
10701 // Spill to obtain 24-bit precision
10702 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10703 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10704 match(Set dst (MulF src1 src2));
10706 format %{ "FMUL $dst,$src1,$src2" %}
10707 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10708 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10709 set_instruction_start,
10710 OpcP, RMopc_Mem(secondary,src1),
10711 Pop_Mem_FPR(dst) );
10712 ins_pipe( fpu_mem_mem_mem );
10713 %}
10715 // Spill to obtain 24-bit precision
10716 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10717 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10718 match(Set dst (MulF src con));
10720 format %{ "FLD $src\n\t"
10721 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10722 "FSTP_S $dst" %}
10723 ins_encode %{
10724 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10725 __ fmul_s($constantaddress($con));
10726 __ fstp_s(Address(rsp, $dst$$disp));
10727 %}
10728 ins_pipe(fpu_mem_reg_con);
10729 %}
10730 //
10731 // This instruction does not round to 24-bits
10732 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10733 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10734 match(Set dst (MulF src con));
10736 format %{ "FLD $src\n\t"
10737 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10738 "FSTP $dst" %}
10739 ins_encode %{
10740 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10741 __ fmul_s($constantaddress($con));
10742 __ fstp_d($dst$$reg);
10743 %}
10744 ins_pipe(fpu_reg_reg_con);
10745 %}
10748 //
10749 // MACRO1 -- subsume unshared load into mulFPR
10750 // This instruction does not round to 24-bits
10751 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10752 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10753 match(Set dst (MulF (LoadF mem1) src));
10755 format %{ "FLD $mem1 ===MACRO1===\n\t"
10756 "FMUL ST,$src\n\t"
10757 "FSTP $dst" %}
10758 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10759 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10760 OpcReg_FPR(src),
10761 Pop_Reg_FPR(dst) );
10762 ins_pipe( fpu_reg_reg_mem );
10763 %}
10764 //
10765 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10766 // This instruction does not round to 24-bits
10767 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10768 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10769 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10770 ins_cost(95);
10772 format %{ "FLD $mem1 ===MACRO2===\n\t"
10773 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10774 "FADD ST,$src2\n\t"
10775 "FSTP $dst" %}
10776 opcode(0xD9); /* LoadF D9 /0 */
10777 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10778 FMul_ST_reg(src1),
10779 FAdd_ST_reg(src2),
10780 Pop_Reg_FPR(dst) );
10781 ins_pipe( fpu_reg_mem_reg_reg );
10782 %}
10784 // MACRO3 -- addFPR a mulFPR
10785 // This instruction does not round to 24-bits. It is a '2-address'
10786 // instruction in that the result goes back to src2. This eliminates
10787 // a move from the macro; possibly the register allocator will have
10788 // to add it back (and maybe not).
10789 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10790 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10791 match(Set src2 (AddF (MulF src0 src1) src2));
10793 format %{ "FLD $src0 ===MACRO3===\n\t"
10794 "FMUL ST,$src1\n\t"
10795 "FADDP $src2,ST" %}
10796 opcode(0xD9); /* LoadF D9 /0 */
10797 ins_encode( Push_Reg_FPR(src0),
10798 FMul_ST_reg(src1),
10799 FAddP_reg_ST(src2) );
10800 ins_pipe( fpu_reg_reg_reg );
10801 %}
10803 // MACRO4 -- divFPR subFPR
10804 // This instruction does not round to 24-bits
10805 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10806 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10807 match(Set dst (DivF (SubF src2 src1) src3));
10809 format %{ "FLD $src2 ===MACRO4===\n\t"
10810 "FSUB ST,$src1\n\t"
10811 "FDIV ST,$src3\n\t"
10812 "FSTP $dst" %}
10813 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10814 ins_encode( Push_Reg_FPR(src2),
10815 subFPR_divFPR_encode(src1,src3),
10816 Pop_Reg_FPR(dst) );
10817 ins_pipe( fpu_reg_reg_reg_reg );
10818 %}
10820 // Spill to obtain 24-bit precision
10821 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10822 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10823 match(Set dst (DivF src1 src2));
10825 format %{ "FDIV $dst,$src1,$src2" %}
10826 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10827 ins_encode( Push_Reg_FPR(src1),
10828 OpcReg_FPR(src2),
10829 Pop_Mem_FPR(dst) );
10830 ins_pipe( fpu_mem_reg_reg );
10831 %}
10832 //
10833 // This instruction does not round to 24-bits
10834 instruct divFPR_reg(regFPR dst, regFPR src) %{
10835 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10836 match(Set dst (DivF dst src));
10838 format %{ "FDIV $dst,$src" %}
10839 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10840 ins_encode( Push_Reg_FPR(src),
10841 OpcP, RegOpc(dst) );
10842 ins_pipe( fpu_reg_reg );
10843 %}
10846 // Spill to obtain 24-bit precision
10847 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10848 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10849 match(Set dst (ModF src1 src2));
10850 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10852 format %{ "FMOD $dst,$src1,$src2" %}
10853 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10854 emitModDPR(),
10855 Push_Result_Mod_DPR(src2),
10856 Pop_Mem_FPR(dst));
10857 ins_pipe( pipe_slow );
10858 %}
10859 //
10860 // This instruction does not round to 24-bits
10861 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10862 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10863 match(Set dst (ModF dst src));
10864 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10866 format %{ "FMOD $dst,$src" %}
10867 ins_encode(Push_Reg_Mod_DPR(dst, src),
10868 emitModDPR(),
10869 Push_Result_Mod_DPR(src),
10870 Pop_Reg_FPR(dst));
10871 ins_pipe( pipe_slow );
10872 %}
10874 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10875 predicate(UseSSE>=1);
10876 match(Set dst (ModF src0 src1));
10877 effect(KILL rax, KILL cr);
10878 format %{ "SUB ESP,4\t # FMOD\n"
10879 "\tMOVSS [ESP+0],$src1\n"
10880 "\tFLD_S [ESP+0]\n"
10881 "\tMOVSS [ESP+0],$src0\n"
10882 "\tFLD_S [ESP+0]\n"
10883 "loop:\tFPREM\n"
10884 "\tFWAIT\n"
10885 "\tFNSTSW AX\n"
10886 "\tSAHF\n"
10887 "\tJP loop\n"
10888 "\tFSTP_S [ESP+0]\n"
10889 "\tMOVSS $dst,[ESP+0]\n"
10890 "\tADD ESP,4\n"
10891 "\tFSTP ST0\t # Restore FPU Stack"
10892 %}
10893 ins_cost(250);
10894 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10895 ins_pipe( pipe_slow );
10896 %}
10899 //----------Arithmetic Conversion Instructions---------------------------------
10900 // The conversions operations are all Alpha sorted. Please keep it that way!
10902 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10903 predicate(UseSSE==0);
10904 match(Set dst (RoundFloat src));
10905 ins_cost(125);
10906 format %{ "FST_S $dst,$src\t# F-round" %}
10907 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10908 ins_pipe( fpu_mem_reg );
10909 %}
10911 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10912 predicate(UseSSE<=1);
10913 match(Set dst (RoundDouble src));
10914 ins_cost(125);
10915 format %{ "FST_D $dst,$src\t# D-round" %}
10916 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10917 ins_pipe( fpu_mem_reg );
10918 %}
10920 // Force rounding to 24-bit precision and 6-bit exponent
10921 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10922 predicate(UseSSE==0);
10923 match(Set dst (ConvD2F src));
10924 format %{ "FST_S $dst,$src\t# F-round" %}
10925 expand %{
10926 roundFloat_mem_reg(dst,src);
10927 %}
10928 %}
10930 // Force rounding to 24-bit precision and 6-bit exponent
10931 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10932 predicate(UseSSE==1);
10933 match(Set dst (ConvD2F src));
10934 effect( KILL cr );
10935 format %{ "SUB ESP,4\n\t"
10936 "FST_S [ESP],$src\t# F-round\n\t"
10937 "MOVSS $dst,[ESP]\n\t"
10938 "ADD ESP,4" %}
10939 ins_encode %{
10940 __ subptr(rsp, 4);
10941 if ($src$$reg != FPR1L_enc) {
10942 __ fld_s($src$$reg-1);
10943 __ fstp_s(Address(rsp, 0));
10944 } else {
10945 __ fst_s(Address(rsp, 0));
10946 }
10947 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10948 __ addptr(rsp, 4);
10949 %}
10950 ins_pipe( pipe_slow );
10951 %}
10953 // Force rounding double precision to single precision
10954 instruct convD2F_reg(regF dst, regD src) %{
10955 predicate(UseSSE>=2);
10956 match(Set dst (ConvD2F src));
10957 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10958 ins_encode %{
10959 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10960 %}
10961 ins_pipe( pipe_slow );
10962 %}
10964 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10965 predicate(UseSSE==0);
10966 match(Set dst (ConvF2D src));
10967 format %{ "FST_S $dst,$src\t# D-round" %}
10968 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10969 ins_pipe( fpu_reg_reg );
10970 %}
10972 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10973 predicate(UseSSE==1);
10974 match(Set dst (ConvF2D src));
10975 format %{ "FST_D $dst,$src\t# D-round" %}
10976 expand %{
10977 roundDouble_mem_reg(dst,src);
10978 %}
10979 %}
10981 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10982 predicate(UseSSE==1);
10983 match(Set dst (ConvF2D src));
10984 effect( KILL cr );
10985 format %{ "SUB ESP,4\n\t"
10986 "MOVSS [ESP] $src\n\t"
10987 "FLD_S [ESP]\n\t"
10988 "ADD ESP,4\n\t"
10989 "FSTP $dst\t# D-round" %}
10990 ins_encode %{
10991 __ subptr(rsp, 4);
10992 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10993 __ fld_s(Address(rsp, 0));
10994 __ addptr(rsp, 4);
10995 __ fstp_d($dst$$reg);
10996 %}
10997 ins_pipe( pipe_slow );
10998 %}
11000 instruct convF2D_reg(regD dst, regF src) %{
11001 predicate(UseSSE>=2);
11002 match(Set dst (ConvF2D src));
11003 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11004 ins_encode %{
11005 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
11006 %}
11007 ins_pipe( pipe_slow );
11008 %}
11010 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11011 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
11012 predicate(UseSSE<=1);
11013 match(Set dst (ConvD2I src));
11014 effect( KILL tmp, KILL cr );
11015 format %{ "FLD $src\t# Convert double to int \n\t"
11016 "FLDCW trunc mode\n\t"
11017 "SUB ESP,4\n\t"
11018 "FISTp [ESP + #0]\n\t"
11019 "FLDCW std/24-bit mode\n\t"
11020 "POP EAX\n\t"
11021 "CMP EAX,0x80000000\n\t"
11022 "JNE,s fast\n\t"
11023 "FLD_D $src\n\t"
11024 "CALL d2i_wrapper\n"
11025 "fast:" %}
11026 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
11027 ins_pipe( pipe_slow );
11028 %}
11030 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11031 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11032 predicate(UseSSE>=2);
11033 match(Set dst (ConvD2I src));
11034 effect( KILL tmp, KILL cr );
11035 format %{ "CVTTSD2SI $dst, $src\n\t"
11036 "CMP $dst,0x80000000\n\t"
11037 "JNE,s fast\n\t"
11038 "SUB ESP, 8\n\t"
11039 "MOVSD [ESP], $src\n\t"
11040 "FLD_D [ESP]\n\t"
11041 "ADD ESP, 8\n\t"
11042 "CALL d2i_wrapper\n"
11043 "fast:" %}
11044 ins_encode %{
11045 Label fast;
11046 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
11047 __ cmpl($dst$$Register, 0x80000000);
11048 __ jccb(Assembler::notEqual, fast);
11049 __ subptr(rsp, 8);
11050 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11051 __ fld_d(Address(rsp, 0));
11052 __ addptr(rsp, 8);
11053 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11054 __ bind(fast);
11055 %}
11056 ins_pipe( pipe_slow );
11057 %}
11059 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
11060 predicate(UseSSE<=1);
11061 match(Set dst (ConvD2L src));
11062 effect( KILL cr );
11063 format %{ "FLD $src\t# Convert double to long\n\t"
11064 "FLDCW trunc mode\n\t"
11065 "SUB ESP,8\n\t"
11066 "FISTp [ESP + #0]\n\t"
11067 "FLDCW std/24-bit mode\n\t"
11068 "POP EAX\n\t"
11069 "POP EDX\n\t"
11070 "CMP EDX,0x80000000\n\t"
11071 "JNE,s fast\n\t"
11072 "TEST EAX,EAX\n\t"
11073 "JNE,s fast\n\t"
11074 "FLD $src\n\t"
11075 "CALL d2l_wrapper\n"
11076 "fast:" %}
11077 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
11078 ins_pipe( pipe_slow );
11079 %}
11081 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11082 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11083 predicate (UseSSE>=2);
11084 match(Set dst (ConvD2L src));
11085 effect( KILL cr );
11086 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11087 "MOVSD [ESP],$src\n\t"
11088 "FLD_D [ESP]\n\t"
11089 "FLDCW trunc mode\n\t"
11090 "FISTp [ESP + #0]\n\t"
11091 "FLDCW std/24-bit mode\n\t"
11092 "POP EAX\n\t"
11093 "POP EDX\n\t"
11094 "CMP EDX,0x80000000\n\t"
11095 "JNE,s fast\n\t"
11096 "TEST EAX,EAX\n\t"
11097 "JNE,s fast\n\t"
11098 "SUB ESP,8\n\t"
11099 "MOVSD [ESP],$src\n\t"
11100 "FLD_D [ESP]\n\t"
11101 "ADD ESP,8\n\t"
11102 "CALL d2l_wrapper\n"
11103 "fast:" %}
11104 ins_encode %{
11105 Label fast;
11106 __ subptr(rsp, 8);
11107 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11108 __ fld_d(Address(rsp, 0));
11109 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11110 __ fistp_d(Address(rsp, 0));
11111 // Restore the rounding mode, mask the exception
11112 if (Compile::current()->in_24_bit_fp_mode()) {
11113 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11114 } else {
11115 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11116 }
11117 // Load the converted long, adjust CPU stack
11118 __ pop(rax);
11119 __ pop(rdx);
11120 __ cmpl(rdx, 0x80000000);
11121 __ jccb(Assembler::notEqual, fast);
11122 __ testl(rax, rax);
11123 __ jccb(Assembler::notEqual, fast);
11124 __ subptr(rsp, 8);
11125 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11126 __ fld_d(Address(rsp, 0));
11127 __ addptr(rsp, 8);
11128 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11129 __ bind(fast);
11130 %}
11131 ins_pipe( pipe_slow );
11132 %}
11134 // Convert a double to an int. Java semantics require we do complex
11135 // manglations in the corner cases. So we set the rounding mode to
11136 // 'zero', store the darned double down as an int, and reset the
11137 // rounding mode to 'nearest'. The hardware stores a flag value down
11138 // if we would overflow or converted a NAN; we check for this and
11139 // and go the slow path if needed.
11140 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
11141 predicate(UseSSE==0);
11142 match(Set dst (ConvF2I src));
11143 effect( KILL tmp, KILL cr );
11144 format %{ "FLD $src\t# Convert float to int \n\t"
11145 "FLDCW trunc mode\n\t"
11146 "SUB ESP,4\n\t"
11147 "FISTp [ESP + #0]\n\t"
11148 "FLDCW std/24-bit mode\n\t"
11149 "POP EAX\n\t"
11150 "CMP EAX,0x80000000\n\t"
11151 "JNE,s fast\n\t"
11152 "FLD $src\n\t"
11153 "CALL d2i_wrapper\n"
11154 "fast:" %}
11155 // DPR2I_encoding works for FPR2I
11156 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
11157 ins_pipe( pipe_slow );
11158 %}
11160 // Convert a float in xmm to an int reg.
11161 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11162 predicate(UseSSE>=1);
11163 match(Set dst (ConvF2I src));
11164 effect( KILL tmp, KILL cr );
11165 format %{ "CVTTSS2SI $dst, $src\n\t"
11166 "CMP $dst,0x80000000\n\t"
11167 "JNE,s fast\n\t"
11168 "SUB ESP, 4\n\t"
11169 "MOVSS [ESP], $src\n\t"
11170 "FLD [ESP]\n\t"
11171 "ADD ESP, 4\n\t"
11172 "CALL d2i_wrapper\n"
11173 "fast:" %}
11174 ins_encode %{
11175 Label fast;
11176 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11177 __ cmpl($dst$$Register, 0x80000000);
11178 __ jccb(Assembler::notEqual, fast);
11179 __ subptr(rsp, 4);
11180 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11181 __ fld_s(Address(rsp, 0));
11182 __ addptr(rsp, 4);
11183 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11184 __ bind(fast);
11185 %}
11186 ins_pipe( pipe_slow );
11187 %}
11189 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11190 predicate(UseSSE==0);
11191 match(Set dst (ConvF2L src));
11192 effect( KILL cr );
11193 format %{ "FLD $src\t# Convert float to long\n\t"
11194 "FLDCW trunc mode\n\t"
11195 "SUB ESP,8\n\t"
11196 "FISTp [ESP + #0]\n\t"
11197 "FLDCW std/24-bit mode\n\t"
11198 "POP EAX\n\t"
11199 "POP EDX\n\t"
11200 "CMP EDX,0x80000000\n\t"
11201 "JNE,s fast\n\t"
11202 "TEST EAX,EAX\n\t"
11203 "JNE,s fast\n\t"
11204 "FLD $src\n\t"
11205 "CALL d2l_wrapper\n"
11206 "fast:" %}
11207 // DPR2L_encoding works for FPR2L
11208 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11209 ins_pipe( pipe_slow );
11210 %}
11212 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11213 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11214 predicate (UseSSE>=1);
11215 match(Set dst (ConvF2L src));
11216 effect( KILL cr );
11217 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11218 "MOVSS [ESP],$src\n\t"
11219 "FLD_S [ESP]\n\t"
11220 "FLDCW trunc mode\n\t"
11221 "FISTp [ESP + #0]\n\t"
11222 "FLDCW std/24-bit mode\n\t"
11223 "POP EAX\n\t"
11224 "POP EDX\n\t"
11225 "CMP EDX,0x80000000\n\t"
11226 "JNE,s fast\n\t"
11227 "TEST EAX,EAX\n\t"
11228 "JNE,s fast\n\t"
11229 "SUB ESP,4\t# Convert float to long\n\t"
11230 "MOVSS [ESP],$src\n\t"
11231 "FLD_S [ESP]\n\t"
11232 "ADD ESP,4\n\t"
11233 "CALL d2l_wrapper\n"
11234 "fast:" %}
11235 ins_encode %{
11236 Label fast;
11237 __ subptr(rsp, 8);
11238 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11239 __ fld_s(Address(rsp, 0));
11240 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11241 __ fistp_d(Address(rsp, 0));
11242 // Restore the rounding mode, mask the exception
11243 if (Compile::current()->in_24_bit_fp_mode()) {
11244 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11245 } else {
11246 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11247 }
11248 // Load the converted long, adjust CPU stack
11249 __ pop(rax);
11250 __ pop(rdx);
11251 __ cmpl(rdx, 0x80000000);
11252 __ jccb(Assembler::notEqual, fast);
11253 __ testl(rax, rax);
11254 __ jccb(Assembler::notEqual, fast);
11255 __ subptr(rsp, 4);
11256 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11257 __ fld_s(Address(rsp, 0));
11258 __ addptr(rsp, 4);
11259 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11260 __ bind(fast);
11261 %}
11262 ins_pipe( pipe_slow );
11263 %}
11265 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11266 predicate( UseSSE<=1 );
11267 match(Set dst (ConvI2D src));
11268 format %{ "FILD $src\n\t"
11269 "FSTP $dst" %}
11270 opcode(0xDB, 0x0); /* DB /0 */
11271 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11272 ins_pipe( fpu_reg_mem );
11273 %}
11275 instruct convI2D_reg(regD dst, rRegI src) %{
11276 predicate( UseSSE>=2 && !UseXmmI2D );
11277 match(Set dst (ConvI2D src));
11278 format %{ "CVTSI2SD $dst,$src" %}
11279 ins_encode %{
11280 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11281 %}
11282 ins_pipe( pipe_slow );
11283 %}
11285 instruct convI2D_mem(regD dst, memory mem) %{
11286 predicate( UseSSE>=2 );
11287 match(Set dst (ConvI2D (LoadI mem)));
11288 format %{ "CVTSI2SD $dst,$mem" %}
11289 ins_encode %{
11290 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11291 %}
11292 ins_pipe( pipe_slow );
11293 %}
11295 instruct convXI2D_reg(regD dst, rRegI src)
11296 %{
11297 predicate( UseSSE>=2 && UseXmmI2D );
11298 match(Set dst (ConvI2D src));
11300 format %{ "MOVD $dst,$src\n\t"
11301 "CVTDQ2PD $dst,$dst\t# i2d" %}
11302 ins_encode %{
11303 __ movdl($dst$$XMMRegister, $src$$Register);
11304 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11305 %}
11306 ins_pipe(pipe_slow); // XXX
11307 %}
11309 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11310 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11311 match(Set dst (ConvI2D (LoadI mem)));
11312 format %{ "FILD $mem\n\t"
11313 "FSTP $dst" %}
11314 opcode(0xDB); /* DB /0 */
11315 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11316 Pop_Reg_DPR(dst));
11317 ins_pipe( fpu_reg_mem );
11318 %}
11320 // Convert a byte to a float; no rounding step needed.
11321 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11322 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11323 match(Set dst (ConvI2F src));
11324 format %{ "FILD $src\n\t"
11325 "FSTP $dst" %}
11327 opcode(0xDB, 0x0); /* DB /0 */
11328 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11329 ins_pipe( fpu_reg_mem );
11330 %}
11332 // In 24-bit mode, force exponent rounding by storing back out
11333 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11334 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11335 match(Set dst (ConvI2F src));
11336 ins_cost(200);
11337 format %{ "FILD $src\n\t"
11338 "FSTP_S $dst" %}
11339 opcode(0xDB, 0x0); /* DB /0 */
11340 ins_encode( Push_Mem_I(src),
11341 Pop_Mem_FPR(dst));
11342 ins_pipe( fpu_mem_mem );
11343 %}
11345 // In 24-bit mode, force exponent rounding by storing back out
11346 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11347 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11348 match(Set dst (ConvI2F (LoadI mem)));
11349 ins_cost(200);
11350 format %{ "FILD $mem\n\t"
11351 "FSTP_S $dst" %}
11352 opcode(0xDB); /* DB /0 */
11353 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11354 Pop_Mem_FPR(dst));
11355 ins_pipe( fpu_mem_mem );
11356 %}
11358 // This instruction does not round to 24-bits
11359 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11360 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11361 match(Set dst (ConvI2F src));
11362 format %{ "FILD $src\n\t"
11363 "FSTP $dst" %}
11364 opcode(0xDB, 0x0); /* DB /0 */
11365 ins_encode( Push_Mem_I(src),
11366 Pop_Reg_FPR(dst));
11367 ins_pipe( fpu_reg_mem );
11368 %}
11370 // This instruction does not round to 24-bits
11371 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11372 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11373 match(Set dst (ConvI2F (LoadI mem)));
11374 format %{ "FILD $mem\n\t"
11375 "FSTP $dst" %}
11376 opcode(0xDB); /* DB /0 */
11377 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11378 Pop_Reg_FPR(dst));
11379 ins_pipe( fpu_reg_mem );
11380 %}
11382 // Convert an int to a float in xmm; no rounding step needed.
11383 instruct convI2F_reg(regF dst, rRegI src) %{
11384 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11385 match(Set dst (ConvI2F src));
11386 format %{ "CVTSI2SS $dst, $src" %}
11387 ins_encode %{
11388 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11389 %}
11390 ins_pipe( pipe_slow );
11391 %}
11393 instruct convXI2F_reg(regF dst, rRegI src)
11394 %{
11395 predicate( UseSSE>=2 && UseXmmI2F );
11396 match(Set dst (ConvI2F src));
11398 format %{ "MOVD $dst,$src\n\t"
11399 "CVTDQ2PS $dst,$dst\t# i2f" %}
11400 ins_encode %{
11401 __ movdl($dst$$XMMRegister, $src$$Register);
11402 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11403 %}
11404 ins_pipe(pipe_slow); // XXX
11405 %}
11407 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11408 match(Set dst (ConvI2L src));
11409 effect(KILL cr);
11410 ins_cost(375);
11411 format %{ "MOV $dst.lo,$src\n\t"
11412 "MOV $dst.hi,$src\n\t"
11413 "SAR $dst.hi,31" %}
11414 ins_encode(convert_int_long(dst,src));
11415 ins_pipe( ialu_reg_reg_long );
11416 %}
11418 // Zero-extend convert int to long
11419 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11420 match(Set dst (AndL (ConvI2L src) mask) );
11421 effect( KILL flags );
11422 ins_cost(250);
11423 format %{ "MOV $dst.lo,$src\n\t"
11424 "XOR $dst.hi,$dst.hi" %}
11425 opcode(0x33); // XOR
11426 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11427 ins_pipe( ialu_reg_reg_long );
11428 %}
11430 // Zero-extend long
11431 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11432 match(Set dst (AndL src mask) );
11433 effect( KILL flags );
11434 ins_cost(250);
11435 format %{ "MOV $dst.lo,$src.lo\n\t"
11436 "XOR $dst.hi,$dst.hi\n\t" %}
11437 opcode(0x33); // XOR
11438 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11439 ins_pipe( ialu_reg_reg_long );
11440 %}
11442 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11443 predicate (UseSSE<=1);
11444 match(Set dst (ConvL2D src));
11445 effect( KILL cr );
11446 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11447 "PUSH $src.lo\n\t"
11448 "FILD ST,[ESP + #0]\n\t"
11449 "ADD ESP,8\n\t"
11450 "FSTP_D $dst\t# D-round" %}
11451 opcode(0xDF, 0x5); /* DF /5 */
11452 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11453 ins_pipe( pipe_slow );
11454 %}
11456 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11457 predicate (UseSSE>=2);
11458 match(Set dst (ConvL2D src));
11459 effect( KILL cr );
11460 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11461 "PUSH $src.lo\n\t"
11462 "FILD_D [ESP]\n\t"
11463 "FSTP_D [ESP]\n\t"
11464 "MOVSD $dst,[ESP]\n\t"
11465 "ADD ESP,8" %}
11466 opcode(0xDF, 0x5); /* DF /5 */
11467 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11468 ins_pipe( pipe_slow );
11469 %}
11471 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11472 predicate (UseSSE>=1);
11473 match(Set dst (ConvL2F src));
11474 effect( KILL cr );
11475 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11476 "PUSH $src.lo\n\t"
11477 "FILD_D [ESP]\n\t"
11478 "FSTP_S [ESP]\n\t"
11479 "MOVSS $dst,[ESP]\n\t"
11480 "ADD ESP,8" %}
11481 opcode(0xDF, 0x5); /* DF /5 */
11482 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11483 ins_pipe( pipe_slow );
11484 %}
11486 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11487 match(Set dst (ConvL2F src));
11488 effect( KILL cr );
11489 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11490 "PUSH $src.lo\n\t"
11491 "FILD ST,[ESP + #0]\n\t"
11492 "ADD ESP,8\n\t"
11493 "FSTP_S $dst\t# F-round" %}
11494 opcode(0xDF, 0x5); /* DF /5 */
11495 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11496 ins_pipe( pipe_slow );
11497 %}
11499 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11500 match(Set dst (ConvL2I src));
11501 effect( DEF dst, USE src );
11502 format %{ "MOV $dst,$src.lo" %}
11503 ins_encode(enc_CopyL_Lo(dst,src));
11504 ins_pipe( ialu_reg_reg );
11505 %}
11508 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11509 match(Set dst (MoveF2I src));
11510 effect( DEF dst, USE src );
11511 ins_cost(100);
11512 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11513 ins_encode %{
11514 __ movl($dst$$Register, Address(rsp, $src$$disp));
11515 %}
11516 ins_pipe( ialu_reg_mem );
11517 %}
11519 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11520 predicate(UseSSE==0);
11521 match(Set dst (MoveF2I src));
11522 effect( DEF dst, USE src );
11524 ins_cost(125);
11525 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11526 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11527 ins_pipe( fpu_mem_reg );
11528 %}
11530 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11531 predicate(UseSSE>=1);
11532 match(Set dst (MoveF2I src));
11533 effect( DEF dst, USE src );
11535 ins_cost(95);
11536 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11537 ins_encode %{
11538 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11539 %}
11540 ins_pipe( pipe_slow );
11541 %}
11543 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11544 predicate(UseSSE>=2);
11545 match(Set dst (MoveF2I src));
11546 effect( DEF dst, USE src );
11547 ins_cost(85);
11548 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11549 ins_encode %{
11550 __ movdl($dst$$Register, $src$$XMMRegister);
11551 %}
11552 ins_pipe( pipe_slow );
11553 %}
11555 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11556 match(Set dst (MoveI2F src));
11557 effect( DEF dst, USE src );
11559 ins_cost(100);
11560 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11561 ins_encode %{
11562 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11563 %}
11564 ins_pipe( ialu_mem_reg );
11565 %}
11568 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11569 predicate(UseSSE==0);
11570 match(Set dst (MoveI2F src));
11571 effect(DEF dst, USE src);
11573 ins_cost(125);
11574 format %{ "FLD_S $src\n\t"
11575 "FSTP $dst\t# MoveI2F_stack_reg" %}
11576 opcode(0xD9); /* D9 /0, FLD m32real */
11577 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11578 Pop_Reg_FPR(dst) );
11579 ins_pipe( fpu_reg_mem );
11580 %}
11582 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11583 predicate(UseSSE>=1);
11584 match(Set dst (MoveI2F src));
11585 effect( DEF dst, USE src );
11587 ins_cost(95);
11588 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11589 ins_encode %{
11590 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11591 %}
11592 ins_pipe( pipe_slow );
11593 %}
11595 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11596 predicate(UseSSE>=2);
11597 match(Set dst (MoveI2F src));
11598 effect( DEF dst, USE src );
11600 ins_cost(85);
11601 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11602 ins_encode %{
11603 __ movdl($dst$$XMMRegister, $src$$Register);
11604 %}
11605 ins_pipe( pipe_slow );
11606 %}
11608 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11609 match(Set dst (MoveD2L src));
11610 effect(DEF dst, USE src);
11612 ins_cost(250);
11613 format %{ "MOV $dst.lo,$src\n\t"
11614 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11615 opcode(0x8B, 0x8B);
11616 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11617 ins_pipe( ialu_mem_long_reg );
11618 %}
11620 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11621 predicate(UseSSE<=1);
11622 match(Set dst (MoveD2L src));
11623 effect(DEF dst, USE src);
11625 ins_cost(125);
11626 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11627 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11628 ins_pipe( fpu_mem_reg );
11629 %}
11631 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11632 predicate(UseSSE>=2);
11633 match(Set dst (MoveD2L src));
11634 effect(DEF dst, USE src);
11635 ins_cost(95);
11636 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11637 ins_encode %{
11638 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11639 %}
11640 ins_pipe( pipe_slow );
11641 %}
11643 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11644 predicate(UseSSE>=2);
11645 match(Set dst (MoveD2L src));
11646 effect(DEF dst, USE src, TEMP tmp);
11647 ins_cost(85);
11648 format %{ "MOVD $dst.lo,$src\n\t"
11649 "PSHUFLW $tmp,$src,0x4E\n\t"
11650 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11651 ins_encode %{
11652 __ movdl($dst$$Register, $src$$XMMRegister);
11653 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11654 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11655 %}
11656 ins_pipe( pipe_slow );
11657 %}
11659 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11660 match(Set dst (MoveL2D src));
11661 effect(DEF dst, USE src);
11663 ins_cost(200);
11664 format %{ "MOV $dst,$src.lo\n\t"
11665 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11666 opcode(0x89, 0x89);
11667 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11668 ins_pipe( ialu_mem_long_reg );
11669 %}
11672 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11673 predicate(UseSSE<=1);
11674 match(Set dst (MoveL2D src));
11675 effect(DEF dst, USE src);
11676 ins_cost(125);
11678 format %{ "FLD_D $src\n\t"
11679 "FSTP $dst\t# MoveL2D_stack_reg" %}
11680 opcode(0xDD); /* DD /0, FLD m64real */
11681 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11682 Pop_Reg_DPR(dst) );
11683 ins_pipe( fpu_reg_mem );
11684 %}
11687 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11688 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11689 match(Set dst (MoveL2D src));
11690 effect(DEF dst, USE src);
11692 ins_cost(95);
11693 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11694 ins_encode %{
11695 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11696 %}
11697 ins_pipe( pipe_slow );
11698 %}
11700 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11701 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11702 match(Set dst (MoveL2D src));
11703 effect(DEF dst, USE src);
11705 ins_cost(95);
11706 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11707 ins_encode %{
11708 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11709 %}
11710 ins_pipe( pipe_slow );
11711 %}
11713 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11714 predicate(UseSSE>=2);
11715 match(Set dst (MoveL2D src));
11716 effect(TEMP dst, USE src, TEMP tmp);
11717 ins_cost(85);
11718 format %{ "MOVD $dst,$src.lo\n\t"
11719 "MOVD $tmp,$src.hi\n\t"
11720 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11721 ins_encode %{
11722 __ movdl($dst$$XMMRegister, $src$$Register);
11723 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11724 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11725 %}
11726 ins_pipe( pipe_slow );
11727 %}
11730 // =======================================================================
11731 // fast clearing of an array
11732 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11733 predicate(!UseFastStosb);
11734 match(Set dummy (ClearArray cnt base));
11735 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11736 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11737 "SHL ECX,1\t# Convert doublewords to words\n\t"
11738 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11739 ins_encode %{
11740 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11741 %}
11742 ins_pipe( pipe_slow );
11743 %}
11745 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11746 predicate(UseFastStosb);
11747 match(Set dummy (ClearArray cnt base));
11748 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11749 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11750 "SHL ECX,3\t# Convert doublewords to bytes\n\t"
11751 "REP STOSB\t# store EAX into [EDI++] while ECX--" %}
11752 ins_encode %{
11753 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11754 %}
11755 ins_pipe( pipe_slow );
11756 %}
11758 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11759 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11760 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11761 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11763 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11764 ins_encode %{
11765 __ string_compare($str1$$Register, $str2$$Register,
11766 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11767 $tmp1$$XMMRegister);
11768 %}
11769 ins_pipe( pipe_slow );
11770 %}
11772 // fast string equals
11773 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11774 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11775 match(Set result (StrEquals (Binary str1 str2) cnt));
11776 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11778 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11779 ins_encode %{
11780 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11781 $cnt$$Register, $result$$Register, $tmp3$$Register,
11782 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11783 %}
11784 ins_pipe( pipe_slow );
11785 %}
11787 // fast search of substring with known size.
11788 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11789 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11790 predicate(UseSSE42Intrinsics);
11791 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11792 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11794 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11795 ins_encode %{
11796 int icnt2 = (int)$int_cnt2$$constant;
11797 if (icnt2 >= 8) {
11798 // IndexOf for constant substrings with size >= 8 elements
11799 // which don't need to be loaded through stack.
11800 __ string_indexofC8($str1$$Register, $str2$$Register,
11801 $cnt1$$Register, $cnt2$$Register,
11802 icnt2, $result$$Register,
11803 $vec$$XMMRegister, $tmp$$Register);
11804 } else {
11805 // Small strings are loaded through stack if they cross page boundary.
11806 __ string_indexof($str1$$Register, $str2$$Register,
11807 $cnt1$$Register, $cnt2$$Register,
11808 icnt2, $result$$Register,
11809 $vec$$XMMRegister, $tmp$$Register);
11810 }
11811 %}
11812 ins_pipe( pipe_slow );
11813 %}
11815 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11816 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11817 predicate(UseSSE42Intrinsics);
11818 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11819 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11821 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11822 ins_encode %{
11823 __ string_indexof($str1$$Register, $str2$$Register,
11824 $cnt1$$Register, $cnt2$$Register,
11825 (-1), $result$$Register,
11826 $vec$$XMMRegister, $tmp$$Register);
11827 %}
11828 ins_pipe( pipe_slow );
11829 %}
11831 // fast array equals
11832 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11833 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11834 %{
11835 match(Set result (AryEq ary1 ary2));
11836 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11837 //ins_cost(300);
11839 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11840 ins_encode %{
11841 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11842 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11843 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11844 %}
11845 ins_pipe( pipe_slow );
11846 %}
11848 // encode char[] to byte[] in ISO_8859_1
11849 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len,
11850 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
11851 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{
11852 match(Set result (EncodeISOArray src (Binary dst len)));
11853 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11855 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %}
11856 ins_encode %{
11857 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11858 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11859 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11860 %}
11861 ins_pipe( pipe_slow );
11862 %}
11865 //----------Control Flow Instructions------------------------------------------
11866 // Signed compare Instructions
11867 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11868 match(Set cr (CmpI op1 op2));
11869 effect( DEF cr, USE op1, USE op2 );
11870 format %{ "CMP $op1,$op2" %}
11871 opcode(0x3B); /* Opcode 3B /r */
11872 ins_encode( OpcP, RegReg( op1, op2) );
11873 ins_pipe( ialu_cr_reg_reg );
11874 %}
11876 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11877 match(Set cr (CmpI op1 op2));
11878 effect( DEF cr, USE op1 );
11879 format %{ "CMP $op1,$op2" %}
11880 opcode(0x81,0x07); /* Opcode 81 /7 */
11881 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11882 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11883 ins_pipe( ialu_cr_reg_imm );
11884 %}
11886 // Cisc-spilled version of cmpI_eReg
11887 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11888 match(Set cr (CmpI op1 (LoadI op2)));
11890 format %{ "CMP $op1,$op2" %}
11891 ins_cost(500);
11892 opcode(0x3B); /* Opcode 3B /r */
11893 ins_encode( OpcP, RegMem( op1, op2) );
11894 ins_pipe( ialu_cr_reg_mem );
11895 %}
11897 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11898 match(Set cr (CmpI src zero));
11899 effect( DEF cr, USE src );
11901 format %{ "TEST $src,$src" %}
11902 opcode(0x85);
11903 ins_encode( OpcP, RegReg( src, src ) );
11904 ins_pipe( ialu_cr_reg_imm );
11905 %}
11907 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11908 match(Set cr (CmpI (AndI src con) zero));
11910 format %{ "TEST $src,$con" %}
11911 opcode(0xF7,0x00);
11912 ins_encode( OpcP, RegOpc(src), Con32(con) );
11913 ins_pipe( ialu_cr_reg_imm );
11914 %}
11916 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11917 match(Set cr (CmpI (AndI src mem) zero));
11919 format %{ "TEST $src,$mem" %}
11920 opcode(0x85);
11921 ins_encode( OpcP, RegMem( src, mem ) );
11922 ins_pipe( ialu_cr_reg_mem );
11923 %}
11925 // Unsigned compare Instructions; really, same as signed except they
11926 // produce an eFlagsRegU instead of eFlagsReg.
11927 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11928 match(Set cr (CmpU op1 op2));
11930 format %{ "CMPu $op1,$op2" %}
11931 opcode(0x3B); /* Opcode 3B /r */
11932 ins_encode( OpcP, RegReg( op1, op2) );
11933 ins_pipe( ialu_cr_reg_reg );
11934 %}
11936 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11937 match(Set cr (CmpU op1 op2));
11939 format %{ "CMPu $op1,$op2" %}
11940 opcode(0x81,0x07); /* Opcode 81 /7 */
11941 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11942 ins_pipe( ialu_cr_reg_imm );
11943 %}
11945 // // Cisc-spilled version of cmpU_eReg
11946 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11947 match(Set cr (CmpU op1 (LoadI op2)));
11949 format %{ "CMPu $op1,$op2" %}
11950 ins_cost(500);
11951 opcode(0x3B); /* Opcode 3B /r */
11952 ins_encode( OpcP, RegMem( op1, op2) );
11953 ins_pipe( ialu_cr_reg_mem );
11954 %}
11956 // // Cisc-spilled version of cmpU_eReg
11957 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11958 // match(Set cr (CmpU (LoadI op1) op2));
11959 //
11960 // format %{ "CMPu $op1,$op2" %}
11961 // ins_cost(500);
11962 // opcode(0x39); /* Opcode 39 /r */
11963 // ins_encode( OpcP, RegMem( op1, op2) );
11964 //%}
11966 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11967 match(Set cr (CmpU src zero));
11969 format %{ "TESTu $src,$src" %}
11970 opcode(0x85);
11971 ins_encode( OpcP, RegReg( src, src ) );
11972 ins_pipe( ialu_cr_reg_imm );
11973 %}
11975 // Unsigned pointer compare Instructions
11976 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11977 match(Set cr (CmpP op1 op2));
11979 format %{ "CMPu $op1,$op2" %}
11980 opcode(0x3B); /* Opcode 3B /r */
11981 ins_encode( OpcP, RegReg( op1, op2) );
11982 ins_pipe( ialu_cr_reg_reg );
11983 %}
11985 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11986 match(Set cr (CmpP op1 op2));
11988 format %{ "CMPu $op1,$op2" %}
11989 opcode(0x81,0x07); /* Opcode 81 /7 */
11990 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11991 ins_pipe( ialu_cr_reg_imm );
11992 %}
11994 // // Cisc-spilled version of cmpP_eReg
11995 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11996 match(Set cr (CmpP op1 (LoadP op2)));
11998 format %{ "CMPu $op1,$op2" %}
11999 ins_cost(500);
12000 opcode(0x3B); /* Opcode 3B /r */
12001 ins_encode( OpcP, RegMem( op1, op2) );
12002 ins_pipe( ialu_cr_reg_mem );
12003 %}
12005 // // Cisc-spilled version of cmpP_eReg
12006 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12007 // match(Set cr (CmpP (LoadP op1) op2));
12008 //
12009 // format %{ "CMPu $op1,$op2" %}
12010 // ins_cost(500);
12011 // opcode(0x39); /* Opcode 39 /r */
12012 // ins_encode( OpcP, RegMem( op1, op2) );
12013 //%}
12015 // Compare raw pointer (used in out-of-heap check).
12016 // Only works because non-oop pointers must be raw pointers
12017 // and raw pointers have no anti-dependencies.
12018 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12019 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
12020 match(Set cr (CmpP op1 (LoadP op2)));
12022 format %{ "CMPu $op1,$op2" %}
12023 opcode(0x3B); /* Opcode 3B /r */
12024 ins_encode( OpcP, RegMem( op1, op2) );
12025 ins_pipe( ialu_cr_reg_mem );
12026 %}
12028 //
12029 // This will generate a signed flags result. This should be ok
12030 // since any compare to a zero should be eq/neq.
12031 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12032 match(Set cr (CmpP src zero));
12034 format %{ "TEST $src,$src" %}
12035 opcode(0x85);
12036 ins_encode( OpcP, RegReg( src, src ) );
12037 ins_pipe( ialu_cr_reg_imm );
12038 %}
12040 // Cisc-spilled version of testP_reg
12041 // This will generate a signed flags result. This should be ok
12042 // since any compare to a zero should be eq/neq.
12043 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12044 match(Set cr (CmpP (LoadP op) zero));
12046 format %{ "TEST $op,0xFFFFFFFF" %}
12047 ins_cost(500);
12048 opcode(0xF7); /* Opcode F7 /0 */
12049 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12050 ins_pipe( ialu_cr_reg_imm );
12051 %}
12053 // Yanked all unsigned pointer compare operations.
12054 // Pointer compares are done with CmpP which is already unsigned.
12056 //----------Max and Min--------------------------------------------------------
12057 // Min Instructions
12058 ////
12059 // *** Min and Max using the conditional move are slower than the
12060 // *** branch version on a Pentium III.
12061 // // Conditional move for min
12062 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
12063 // effect( USE_DEF op2, USE op1, USE cr );
12064 // format %{ "CMOVlt $op2,$op1\t! min" %}
12065 // opcode(0x4C,0x0F);
12066 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12067 // ins_pipe( pipe_cmov_reg );
12068 //%}
12069 //
12070 //// Min Register with Register (P6 version)
12071 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
12072 // predicate(VM_Version::supports_cmov() );
12073 // match(Set op2 (MinI op1 op2));
12074 // ins_cost(200);
12075 // expand %{
12076 // eFlagsReg cr;
12077 // compI_eReg(cr,op1,op2);
12078 // cmovI_reg_lt(op2,op1,cr);
12079 // %}
12080 //%}
12082 // Min Register with Register (generic version)
12083 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
12084 match(Set dst (MinI dst src));
12085 effect(KILL flags);
12086 ins_cost(300);
12088 format %{ "MIN $dst,$src" %}
12089 opcode(0xCC);
12090 ins_encode( min_enc(dst,src) );
12091 ins_pipe( pipe_slow );
12092 %}
12094 // Max Register with Register
12095 // *** Min and Max using the conditional move are slower than the
12096 // *** branch version on a Pentium III.
12097 // // Conditional move for max
12098 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
12099 // effect( USE_DEF op2, USE op1, USE cr );
12100 // format %{ "CMOVgt $op2,$op1\t! max" %}
12101 // opcode(0x4F,0x0F);
12102 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12103 // ins_pipe( pipe_cmov_reg );
12104 //%}
12105 //
12106 // // Max Register with Register (P6 version)
12107 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
12108 // predicate(VM_Version::supports_cmov() );
12109 // match(Set op2 (MaxI op1 op2));
12110 // ins_cost(200);
12111 // expand %{
12112 // eFlagsReg cr;
12113 // compI_eReg(cr,op1,op2);
12114 // cmovI_reg_gt(op2,op1,cr);
12115 // %}
12116 //%}
12118 // Max Register with Register (generic version)
12119 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
12120 match(Set dst (MaxI dst src));
12121 effect(KILL flags);
12122 ins_cost(300);
12124 format %{ "MAX $dst,$src" %}
12125 opcode(0xCC);
12126 ins_encode( max_enc(dst,src) );
12127 ins_pipe( pipe_slow );
12128 %}
12130 // ============================================================================
12131 // Counted Loop limit node which represents exact final iterator value.
12132 // Note: the resulting value should fit into integer range since
12133 // counted loops have limit check on overflow.
12134 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
12135 match(Set limit (LoopLimit (Binary init limit) stride));
12136 effect(TEMP limit_hi, TEMP tmp, KILL flags);
12137 ins_cost(300);
12139 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
12140 ins_encode %{
12141 int strd = (int)$stride$$constant;
12142 assert(strd != 1 && strd != -1, "sanity");
12143 int m1 = (strd > 0) ? 1 : -1;
12144 // Convert limit to long (EAX:EDX)
12145 __ cdql();
12146 // Convert init to long (init:tmp)
12147 __ movl($tmp$$Register, $init$$Register);
12148 __ sarl($tmp$$Register, 31);
12149 // $limit - $init
12150 __ subl($limit$$Register, $init$$Register);
12151 __ sbbl($limit_hi$$Register, $tmp$$Register);
12152 // + ($stride - 1)
12153 if (strd > 0) {
12154 __ addl($limit$$Register, (strd - 1));
12155 __ adcl($limit_hi$$Register, 0);
12156 __ movl($tmp$$Register, strd);
12157 } else {
12158 __ addl($limit$$Register, (strd + 1));
12159 __ adcl($limit_hi$$Register, -1);
12160 __ lneg($limit_hi$$Register, $limit$$Register);
12161 __ movl($tmp$$Register, -strd);
12162 }
12163 // signed devision: (EAX:EDX) / pos_stride
12164 __ idivl($tmp$$Register);
12165 if (strd < 0) {
12166 // restore sign
12167 __ negl($tmp$$Register);
12168 }
12169 // (EAX) * stride
12170 __ mull($tmp$$Register);
12171 // + init (ignore upper bits)
12172 __ addl($limit$$Register, $init$$Register);
12173 %}
12174 ins_pipe( pipe_slow );
12175 %}
12177 // ============================================================================
12178 // Branch Instructions
12179 // Jump Table
12180 instruct jumpXtnd(rRegI switch_val) %{
12181 match(Jump switch_val);
12182 ins_cost(350);
12183 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
12184 ins_encode %{
12185 // Jump to Address(table_base + switch_reg)
12186 Address index(noreg, $switch_val$$Register, Address::times_1);
12187 __ jump(ArrayAddress($constantaddress, index));
12188 %}
12189 ins_pipe(pipe_jmp);
12190 %}
12192 // Jump Direct - Label defines a relative address from JMP+1
12193 instruct jmpDir(label labl) %{
12194 match(Goto);
12195 effect(USE labl);
12197 ins_cost(300);
12198 format %{ "JMP $labl" %}
12199 size(5);
12200 ins_encode %{
12201 Label* L = $labl$$label;
12202 __ jmp(*L, false); // Always long jump
12203 %}
12204 ins_pipe( pipe_jmp );
12205 %}
12207 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12208 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12209 match(If cop cr);
12210 effect(USE labl);
12212 ins_cost(300);
12213 format %{ "J$cop $labl" %}
12214 size(6);
12215 ins_encode %{
12216 Label* L = $labl$$label;
12217 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12218 %}
12219 ins_pipe( pipe_jcc );
12220 %}
12222 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12223 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12224 match(CountedLoopEnd cop cr);
12225 effect(USE labl);
12227 ins_cost(300);
12228 format %{ "J$cop $labl\t# Loop end" %}
12229 size(6);
12230 ins_encode %{
12231 Label* L = $labl$$label;
12232 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12233 %}
12234 ins_pipe( pipe_jcc );
12235 %}
12237 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12238 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12239 match(CountedLoopEnd cop cmp);
12240 effect(USE labl);
12242 ins_cost(300);
12243 format %{ "J$cop,u $labl\t# Loop end" %}
12244 size(6);
12245 ins_encode %{
12246 Label* L = $labl$$label;
12247 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12248 %}
12249 ins_pipe( pipe_jcc );
12250 %}
12252 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12253 match(CountedLoopEnd cop cmp);
12254 effect(USE labl);
12256 ins_cost(200);
12257 format %{ "J$cop,u $labl\t# Loop end" %}
12258 size(6);
12259 ins_encode %{
12260 Label* L = $labl$$label;
12261 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12262 %}
12263 ins_pipe( pipe_jcc );
12264 %}
12266 // Jump Direct Conditional - using unsigned comparison
12267 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12268 match(If cop cmp);
12269 effect(USE labl);
12271 ins_cost(300);
12272 format %{ "J$cop,u $labl" %}
12273 size(6);
12274 ins_encode %{
12275 Label* L = $labl$$label;
12276 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12277 %}
12278 ins_pipe(pipe_jcc);
12279 %}
12281 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12282 match(If cop cmp);
12283 effect(USE labl);
12285 ins_cost(200);
12286 format %{ "J$cop,u $labl" %}
12287 size(6);
12288 ins_encode %{
12289 Label* L = $labl$$label;
12290 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12291 %}
12292 ins_pipe(pipe_jcc);
12293 %}
12295 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12296 match(If cop cmp);
12297 effect(USE labl);
12299 ins_cost(200);
12300 format %{ $$template
12301 if ($cop$$cmpcode == Assembler::notEqual) {
12302 $$emit$$"JP,u $labl\n\t"
12303 $$emit$$"J$cop,u $labl"
12304 } else {
12305 $$emit$$"JP,u done\n\t"
12306 $$emit$$"J$cop,u $labl\n\t"
12307 $$emit$$"done:"
12308 }
12309 %}
12310 ins_encode %{
12311 Label* l = $labl$$label;
12312 if ($cop$$cmpcode == Assembler::notEqual) {
12313 __ jcc(Assembler::parity, *l, false);
12314 __ jcc(Assembler::notEqual, *l, false);
12315 } else if ($cop$$cmpcode == Assembler::equal) {
12316 Label done;
12317 __ jccb(Assembler::parity, done);
12318 __ jcc(Assembler::equal, *l, false);
12319 __ bind(done);
12320 } else {
12321 ShouldNotReachHere();
12322 }
12323 %}
12324 ins_pipe(pipe_jcc);
12325 %}
12327 // ============================================================================
12328 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12329 // array for an instance of the superklass. Set a hidden internal cache on a
12330 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12331 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12332 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12333 match(Set result (PartialSubtypeCheck sub super));
12334 effect( KILL rcx, KILL cr );
12336 ins_cost(1100); // slightly larger than the next version
12337 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12338 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12339 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12340 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12341 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12342 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12343 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12344 "miss:\t" %}
12346 opcode(0x1); // Force a XOR of EDI
12347 ins_encode( enc_PartialSubtypeCheck() );
12348 ins_pipe( pipe_slow );
12349 %}
12351 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12352 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12353 effect( KILL rcx, KILL result );
12355 ins_cost(1000);
12356 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12357 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12358 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12359 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12360 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12361 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12362 "miss:\t" %}
12364 opcode(0x0); // No need to XOR EDI
12365 ins_encode( enc_PartialSubtypeCheck() );
12366 ins_pipe( pipe_slow );
12367 %}
12369 // ============================================================================
12370 // Branch Instructions -- short offset versions
12371 //
12372 // These instructions are used to replace jumps of a long offset (the default
12373 // match) with jumps of a shorter offset. These instructions are all tagged
12374 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12375 // match rules in general matching. Instead, the ADLC generates a conversion
12376 // method in the MachNode which can be used to do in-place replacement of the
12377 // long variant with the shorter variant. The compiler will determine if a
12378 // branch can be taken by the is_short_branch_offset() predicate in the machine
12379 // specific code section of the file.
12381 // Jump Direct - Label defines a relative address from JMP+1
12382 instruct jmpDir_short(label labl) %{
12383 match(Goto);
12384 effect(USE labl);
12386 ins_cost(300);
12387 format %{ "JMP,s $labl" %}
12388 size(2);
12389 ins_encode %{
12390 Label* L = $labl$$label;
12391 __ jmpb(*L);
12392 %}
12393 ins_pipe( pipe_jmp );
12394 ins_short_branch(1);
12395 %}
12397 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12398 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12399 match(If cop cr);
12400 effect(USE labl);
12402 ins_cost(300);
12403 format %{ "J$cop,s $labl" %}
12404 size(2);
12405 ins_encode %{
12406 Label* L = $labl$$label;
12407 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12408 %}
12409 ins_pipe( pipe_jcc );
12410 ins_short_branch(1);
12411 %}
12413 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12414 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12415 match(CountedLoopEnd cop cr);
12416 effect(USE labl);
12418 ins_cost(300);
12419 format %{ "J$cop,s $labl\t# Loop end" %}
12420 size(2);
12421 ins_encode %{
12422 Label* L = $labl$$label;
12423 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12424 %}
12425 ins_pipe( pipe_jcc );
12426 ins_short_branch(1);
12427 %}
12429 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12430 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12431 match(CountedLoopEnd cop cmp);
12432 effect(USE labl);
12434 ins_cost(300);
12435 format %{ "J$cop,us $labl\t# Loop end" %}
12436 size(2);
12437 ins_encode %{
12438 Label* L = $labl$$label;
12439 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12440 %}
12441 ins_pipe( pipe_jcc );
12442 ins_short_branch(1);
12443 %}
12445 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12446 match(CountedLoopEnd cop cmp);
12447 effect(USE labl);
12449 ins_cost(300);
12450 format %{ "J$cop,us $labl\t# Loop end" %}
12451 size(2);
12452 ins_encode %{
12453 Label* L = $labl$$label;
12454 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12455 %}
12456 ins_pipe( pipe_jcc );
12457 ins_short_branch(1);
12458 %}
12460 // Jump Direct Conditional - using unsigned comparison
12461 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12462 match(If cop cmp);
12463 effect(USE labl);
12465 ins_cost(300);
12466 format %{ "J$cop,us $labl" %}
12467 size(2);
12468 ins_encode %{
12469 Label* L = $labl$$label;
12470 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12471 %}
12472 ins_pipe( pipe_jcc );
12473 ins_short_branch(1);
12474 %}
12476 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12477 match(If cop cmp);
12478 effect(USE labl);
12480 ins_cost(300);
12481 format %{ "J$cop,us $labl" %}
12482 size(2);
12483 ins_encode %{
12484 Label* L = $labl$$label;
12485 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12486 %}
12487 ins_pipe( pipe_jcc );
12488 ins_short_branch(1);
12489 %}
12491 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12492 match(If cop cmp);
12493 effect(USE labl);
12495 ins_cost(300);
12496 format %{ $$template
12497 if ($cop$$cmpcode == Assembler::notEqual) {
12498 $$emit$$"JP,u,s $labl\n\t"
12499 $$emit$$"J$cop,u,s $labl"
12500 } else {
12501 $$emit$$"JP,u,s done\n\t"
12502 $$emit$$"J$cop,u,s $labl\n\t"
12503 $$emit$$"done:"
12504 }
12505 %}
12506 size(4);
12507 ins_encode %{
12508 Label* l = $labl$$label;
12509 if ($cop$$cmpcode == Assembler::notEqual) {
12510 __ jccb(Assembler::parity, *l);
12511 __ jccb(Assembler::notEqual, *l);
12512 } else if ($cop$$cmpcode == Assembler::equal) {
12513 Label done;
12514 __ jccb(Assembler::parity, done);
12515 __ jccb(Assembler::equal, *l);
12516 __ bind(done);
12517 } else {
12518 ShouldNotReachHere();
12519 }
12520 %}
12521 ins_pipe(pipe_jcc);
12522 ins_short_branch(1);
12523 %}
12525 // ============================================================================
12526 // Long Compare
12527 //
12528 // Currently we hold longs in 2 registers. Comparing such values efficiently
12529 // is tricky. The flavor of compare used depends on whether we are testing
12530 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12531 // The GE test is the negated LT test. The LE test can be had by commuting
12532 // the operands (yielding a GE test) and then negating; negate again for the
12533 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12534 // NE test is negated from that.
12536 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12537 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12538 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12539 // are collapsed internally in the ADLC's dfa-gen code. The match for
12540 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12541 // foo match ends up with the wrong leaf. One fix is to not match both
12542 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12543 // both forms beat the trinary form of long-compare and both are very useful
12544 // on Intel which has so few registers.
12546 // Manifest a CmpL result in an integer register. Very painful.
12547 // This is the test to avoid.
12548 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12549 match(Set dst (CmpL3 src1 src2));
12550 effect( KILL flags );
12551 ins_cost(1000);
12552 format %{ "XOR $dst,$dst\n\t"
12553 "CMP $src1.hi,$src2.hi\n\t"
12554 "JLT,s m_one\n\t"
12555 "JGT,s p_one\n\t"
12556 "CMP $src1.lo,$src2.lo\n\t"
12557 "JB,s m_one\n\t"
12558 "JEQ,s done\n"
12559 "p_one:\tINC $dst\n\t"
12560 "JMP,s done\n"
12561 "m_one:\tDEC $dst\n"
12562 "done:" %}
12563 ins_encode %{
12564 Label p_one, m_one, done;
12565 __ xorptr($dst$$Register, $dst$$Register);
12566 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12567 __ jccb(Assembler::less, m_one);
12568 __ jccb(Assembler::greater, p_one);
12569 __ cmpl($src1$$Register, $src2$$Register);
12570 __ jccb(Assembler::below, m_one);
12571 __ jccb(Assembler::equal, done);
12572 __ bind(p_one);
12573 __ incrementl($dst$$Register);
12574 __ jmpb(done);
12575 __ bind(m_one);
12576 __ decrementl($dst$$Register);
12577 __ bind(done);
12578 %}
12579 ins_pipe( pipe_slow );
12580 %}
12582 //======
12583 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12584 // compares. Can be used for LE or GT compares by reversing arguments.
12585 // NOT GOOD FOR EQ/NE tests.
12586 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12587 match( Set flags (CmpL src zero ));
12588 ins_cost(100);
12589 format %{ "TEST $src.hi,$src.hi" %}
12590 opcode(0x85);
12591 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12592 ins_pipe( ialu_cr_reg_reg );
12593 %}
12595 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12596 // compares. Can be used for LE or GT compares by reversing arguments.
12597 // NOT GOOD FOR EQ/NE tests.
12598 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12599 match( Set flags (CmpL src1 src2 ));
12600 effect( TEMP tmp );
12601 ins_cost(300);
12602 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12603 "MOV $tmp,$src1.hi\n\t"
12604 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12605 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12606 ins_pipe( ialu_cr_reg_reg );
12607 %}
12609 // Long compares reg < zero/req OR reg >= zero/req.
12610 // Just a wrapper for a normal branch, plus the predicate test.
12611 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12612 match(If cmp flags);
12613 effect(USE labl);
12614 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12615 expand %{
12616 jmpCon(cmp,flags,labl); // JLT or JGE...
12617 %}
12618 %}
12620 // Compare 2 longs and CMOVE longs.
12621 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12622 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12623 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12624 ins_cost(400);
12625 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12626 "CMOV$cmp $dst.hi,$src.hi" %}
12627 opcode(0x0F,0x40);
12628 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12629 ins_pipe( pipe_cmov_reg_long );
12630 %}
12632 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12633 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12634 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12635 ins_cost(500);
12636 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12637 "CMOV$cmp $dst.hi,$src.hi" %}
12638 opcode(0x0F,0x40);
12639 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12640 ins_pipe( pipe_cmov_reg_long );
12641 %}
12643 // Compare 2 longs and CMOVE ints.
12644 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12645 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12646 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12647 ins_cost(200);
12648 format %{ "CMOV$cmp $dst,$src" %}
12649 opcode(0x0F,0x40);
12650 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12651 ins_pipe( pipe_cmov_reg );
12652 %}
12654 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12655 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12656 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12657 ins_cost(250);
12658 format %{ "CMOV$cmp $dst,$src" %}
12659 opcode(0x0F,0x40);
12660 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12661 ins_pipe( pipe_cmov_mem );
12662 %}
12664 // Compare 2 longs and CMOVE ints.
12665 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12666 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12667 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12668 ins_cost(200);
12669 format %{ "CMOV$cmp $dst,$src" %}
12670 opcode(0x0F,0x40);
12671 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12672 ins_pipe( pipe_cmov_reg );
12673 %}
12675 // Compare 2 longs and CMOVE doubles
12676 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12677 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12678 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12679 ins_cost(200);
12680 expand %{
12681 fcmovDPR_regS(cmp,flags,dst,src);
12682 %}
12683 %}
12685 // Compare 2 longs and CMOVE doubles
12686 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12687 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12688 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12689 ins_cost(200);
12690 expand %{
12691 fcmovD_regS(cmp,flags,dst,src);
12692 %}
12693 %}
12695 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12696 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12697 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12698 ins_cost(200);
12699 expand %{
12700 fcmovFPR_regS(cmp,flags,dst,src);
12701 %}
12702 %}
12704 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12705 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12706 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12707 ins_cost(200);
12708 expand %{
12709 fcmovF_regS(cmp,flags,dst,src);
12710 %}
12711 %}
12713 //======
12714 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12715 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12716 match( Set flags (CmpL src zero ));
12717 effect(TEMP tmp);
12718 ins_cost(200);
12719 format %{ "MOV $tmp,$src.lo\n\t"
12720 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12721 ins_encode( long_cmp_flags0( src, tmp ) );
12722 ins_pipe( ialu_reg_reg_long );
12723 %}
12725 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12726 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12727 match( Set flags (CmpL src1 src2 ));
12728 ins_cost(200+300);
12729 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12730 "JNE,s skip\n\t"
12731 "CMP $src1.hi,$src2.hi\n\t"
12732 "skip:\t" %}
12733 ins_encode( long_cmp_flags1( src1, src2 ) );
12734 ins_pipe( ialu_cr_reg_reg );
12735 %}
12737 // Long compare reg == zero/reg OR reg != zero/reg
12738 // Just a wrapper for a normal branch, plus the predicate test.
12739 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12740 match(If cmp flags);
12741 effect(USE labl);
12742 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12743 expand %{
12744 jmpCon(cmp,flags,labl); // JEQ or JNE...
12745 %}
12746 %}
12748 // Compare 2 longs and CMOVE longs.
12749 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12750 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12751 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12752 ins_cost(400);
12753 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12754 "CMOV$cmp $dst.hi,$src.hi" %}
12755 opcode(0x0F,0x40);
12756 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12757 ins_pipe( pipe_cmov_reg_long );
12758 %}
12760 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12761 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12762 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12763 ins_cost(500);
12764 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12765 "CMOV$cmp $dst.hi,$src.hi" %}
12766 opcode(0x0F,0x40);
12767 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12768 ins_pipe( pipe_cmov_reg_long );
12769 %}
12771 // Compare 2 longs and CMOVE ints.
12772 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12773 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12774 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12775 ins_cost(200);
12776 format %{ "CMOV$cmp $dst,$src" %}
12777 opcode(0x0F,0x40);
12778 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12779 ins_pipe( pipe_cmov_reg );
12780 %}
12782 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12783 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12784 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12785 ins_cost(250);
12786 format %{ "CMOV$cmp $dst,$src" %}
12787 opcode(0x0F,0x40);
12788 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12789 ins_pipe( pipe_cmov_mem );
12790 %}
12792 // Compare 2 longs and CMOVE ints.
12793 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12794 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12795 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12796 ins_cost(200);
12797 format %{ "CMOV$cmp $dst,$src" %}
12798 opcode(0x0F,0x40);
12799 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12800 ins_pipe( pipe_cmov_reg );
12801 %}
12803 // Compare 2 longs and CMOVE doubles
12804 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12805 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12806 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12807 ins_cost(200);
12808 expand %{
12809 fcmovDPR_regS(cmp,flags,dst,src);
12810 %}
12811 %}
12813 // Compare 2 longs and CMOVE doubles
12814 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12815 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12816 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12817 ins_cost(200);
12818 expand %{
12819 fcmovD_regS(cmp,flags,dst,src);
12820 %}
12821 %}
12823 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12824 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12825 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12826 ins_cost(200);
12827 expand %{
12828 fcmovFPR_regS(cmp,flags,dst,src);
12829 %}
12830 %}
12832 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12833 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12834 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12835 ins_cost(200);
12836 expand %{
12837 fcmovF_regS(cmp,flags,dst,src);
12838 %}
12839 %}
12841 //======
12842 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12843 // Same as cmpL_reg_flags_LEGT except must negate src
12844 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12845 match( Set flags (CmpL src zero ));
12846 effect( TEMP tmp );
12847 ins_cost(300);
12848 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12849 "CMP $tmp,$src.lo\n\t"
12850 "SBB $tmp,$src.hi\n\t" %}
12851 ins_encode( long_cmp_flags3(src, tmp) );
12852 ins_pipe( ialu_reg_reg_long );
12853 %}
12855 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12856 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12857 // requires a commuted test to get the same result.
12858 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12859 match( Set flags (CmpL src1 src2 ));
12860 effect( TEMP tmp );
12861 ins_cost(300);
12862 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12863 "MOV $tmp,$src2.hi\n\t"
12864 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12865 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12866 ins_pipe( ialu_cr_reg_reg );
12867 %}
12869 // Long compares reg < zero/req OR reg >= zero/req.
12870 // Just a wrapper for a normal branch, plus the predicate test
12871 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12872 match(If cmp flags);
12873 effect(USE labl);
12874 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12875 ins_cost(300);
12876 expand %{
12877 jmpCon(cmp,flags,labl); // JGT or JLE...
12878 %}
12879 %}
12881 // Compare 2 longs and CMOVE longs.
12882 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12883 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12884 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12885 ins_cost(400);
12886 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12887 "CMOV$cmp $dst.hi,$src.hi" %}
12888 opcode(0x0F,0x40);
12889 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12890 ins_pipe( pipe_cmov_reg_long );
12891 %}
12893 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12894 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12895 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12896 ins_cost(500);
12897 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12898 "CMOV$cmp $dst.hi,$src.hi+4" %}
12899 opcode(0x0F,0x40);
12900 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12901 ins_pipe( pipe_cmov_reg_long );
12902 %}
12904 // Compare 2 longs and CMOVE ints.
12905 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12906 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12907 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12908 ins_cost(200);
12909 format %{ "CMOV$cmp $dst,$src" %}
12910 opcode(0x0F,0x40);
12911 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12912 ins_pipe( pipe_cmov_reg );
12913 %}
12915 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12916 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12917 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12918 ins_cost(250);
12919 format %{ "CMOV$cmp $dst,$src" %}
12920 opcode(0x0F,0x40);
12921 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12922 ins_pipe( pipe_cmov_mem );
12923 %}
12925 // Compare 2 longs and CMOVE ptrs.
12926 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12927 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12928 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12929 ins_cost(200);
12930 format %{ "CMOV$cmp $dst,$src" %}
12931 opcode(0x0F,0x40);
12932 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12933 ins_pipe( pipe_cmov_reg );
12934 %}
12936 // Compare 2 longs and CMOVE doubles
12937 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12938 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12939 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12940 ins_cost(200);
12941 expand %{
12942 fcmovDPR_regS(cmp,flags,dst,src);
12943 %}
12944 %}
12946 // Compare 2 longs and CMOVE doubles
12947 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12948 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12949 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12950 ins_cost(200);
12951 expand %{
12952 fcmovD_regS(cmp,flags,dst,src);
12953 %}
12954 %}
12956 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12957 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12958 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12959 ins_cost(200);
12960 expand %{
12961 fcmovFPR_regS(cmp,flags,dst,src);
12962 %}
12963 %}
12966 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12967 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12968 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12969 ins_cost(200);
12970 expand %{
12971 fcmovF_regS(cmp,flags,dst,src);
12972 %}
12973 %}
12976 // ============================================================================
12977 // Procedure Call/Return Instructions
12978 // Call Java Static Instruction
12979 // Note: If this code changes, the corresponding ret_addr_offset() and
12980 // compute_padding() functions will have to be adjusted.
12981 instruct CallStaticJavaDirect(method meth) %{
12982 match(CallStaticJava);
12983 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12984 effect(USE meth);
12986 ins_cost(300);
12987 format %{ "CALL,static " %}
12988 opcode(0xE8); /* E8 cd */
12989 ins_encode( pre_call_resets,
12990 Java_Static_Call( meth ),
12991 call_epilog,
12992 post_call_FPU );
12993 ins_pipe( pipe_slow );
12994 ins_alignment(4);
12995 %}
12997 // Call Java Static Instruction (method handle version)
12998 // Note: If this code changes, the corresponding ret_addr_offset() and
12999 // compute_padding() functions will have to be adjusted.
13000 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
13001 match(CallStaticJava);
13002 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
13003 effect(USE meth);
13004 // EBP is saved by all callees (for interpreter stack correction).
13005 // We use it here for a similar purpose, in {preserve,restore}_SP.
13007 ins_cost(300);
13008 format %{ "CALL,static/MethodHandle " %}
13009 opcode(0xE8); /* E8 cd */
13010 ins_encode( pre_call_resets,
13011 preserve_SP,
13012 Java_Static_Call( meth ),
13013 restore_SP,
13014 call_epilog,
13015 post_call_FPU );
13016 ins_pipe( pipe_slow );
13017 ins_alignment(4);
13018 %}
13020 // Call Java Dynamic Instruction
13021 // Note: If this code changes, the corresponding ret_addr_offset() and
13022 // compute_padding() functions will have to be adjusted.
13023 instruct CallDynamicJavaDirect(method meth) %{
13024 match(CallDynamicJava);
13025 effect(USE meth);
13027 ins_cost(300);
13028 format %{ "MOV EAX,(oop)-1\n\t"
13029 "CALL,dynamic" %}
13030 opcode(0xE8); /* E8 cd */
13031 ins_encode( pre_call_resets,
13032 Java_Dynamic_Call( meth ),
13033 call_epilog,
13034 post_call_FPU );
13035 ins_pipe( pipe_slow );
13036 ins_alignment(4);
13037 %}
13039 // Call Runtime Instruction
13040 instruct CallRuntimeDirect(method meth) %{
13041 match(CallRuntime );
13042 effect(USE meth);
13044 ins_cost(300);
13045 format %{ "CALL,runtime " %}
13046 opcode(0xE8); /* E8 cd */
13047 // Use FFREEs to clear entries in float stack
13048 ins_encode( pre_call_resets,
13049 FFree_Float_Stack_All,
13050 Java_To_Runtime( meth ),
13051 post_call_FPU );
13052 ins_pipe( pipe_slow );
13053 %}
13055 // Call runtime without safepoint
13056 instruct CallLeafDirect(method meth) %{
13057 match(CallLeaf);
13058 effect(USE meth);
13060 ins_cost(300);
13061 format %{ "CALL_LEAF,runtime " %}
13062 opcode(0xE8); /* E8 cd */
13063 ins_encode( pre_call_resets,
13064 FFree_Float_Stack_All,
13065 Java_To_Runtime( meth ),
13066 Verify_FPU_For_Leaf, post_call_FPU );
13067 ins_pipe( pipe_slow );
13068 %}
13070 instruct CallLeafNoFPDirect(method meth) %{
13071 match(CallLeafNoFP);
13072 effect(USE meth);
13074 ins_cost(300);
13075 format %{ "CALL_LEAF_NOFP,runtime " %}
13076 opcode(0xE8); /* E8 cd */
13077 ins_encode(Java_To_Runtime(meth));
13078 ins_pipe( pipe_slow );
13079 %}
13082 // Return Instruction
13083 // Remove the return address & jump to it.
13084 instruct Ret() %{
13085 match(Return);
13086 format %{ "RET" %}
13087 opcode(0xC3);
13088 ins_encode(OpcP);
13089 ins_pipe( pipe_jmp );
13090 %}
13092 // Tail Call; Jump from runtime stub to Java code.
13093 // Also known as an 'interprocedural jump'.
13094 // Target of jump will eventually return to caller.
13095 // TailJump below removes the return address.
13096 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13097 match(TailCall jump_target method_oop );
13098 ins_cost(300);
13099 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13100 opcode(0xFF, 0x4); /* Opcode FF /4 */
13101 ins_encode( OpcP, RegOpc(jump_target) );
13102 ins_pipe( pipe_jmp );
13103 %}
13106 // Tail Jump; remove the return address; jump to target.
13107 // TailCall above leaves the return address around.
13108 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13109 match( TailJump jump_target ex_oop );
13110 ins_cost(300);
13111 format %{ "POP EDX\t# pop return address into dummy\n\t"
13112 "JMP $jump_target " %}
13113 opcode(0xFF, 0x4); /* Opcode FF /4 */
13114 ins_encode( enc_pop_rdx,
13115 OpcP, RegOpc(jump_target) );
13116 ins_pipe( pipe_jmp );
13117 %}
13119 // Create exception oop: created by stack-crawling runtime code.
13120 // Created exception is now available to this handler, and is setup
13121 // just prior to jumping to this handler. No code emitted.
13122 instruct CreateException( eAXRegP ex_oop )
13123 %{
13124 match(Set ex_oop (CreateEx));
13126 size(0);
13127 // use the following format syntax
13128 format %{ "# exception oop is in EAX; no code emitted" %}
13129 ins_encode();
13130 ins_pipe( empty );
13131 %}
13134 // Rethrow exception:
13135 // The exception oop will come in the first argument position.
13136 // Then JUMP (not call) to the rethrow stub code.
13137 instruct RethrowException()
13138 %{
13139 match(Rethrow);
13141 // use the following format syntax
13142 format %{ "JMP rethrow_stub" %}
13143 ins_encode(enc_rethrow);
13144 ins_pipe( pipe_jmp );
13145 %}
13147 // inlined locking and unlocking
13150 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
13151 match( Set cr (FastLock object box) );
13152 effect( TEMP tmp, TEMP scr, USE_KILL box );
13153 ins_cost(300);
13154 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
13155 ins_encode( Fast_Lock(object,box,tmp,scr) );
13156 ins_pipe( pipe_slow );
13157 %}
13159 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13160 match( Set cr (FastUnlock object box) );
13161 effect( TEMP tmp, USE_KILL box );
13162 ins_cost(300);
13163 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
13164 ins_encode( Fast_Unlock(object,box,tmp) );
13165 ins_pipe( pipe_slow );
13166 %}
13170 // ============================================================================
13171 // Safepoint Instruction
13172 instruct safePoint_poll(eFlagsReg cr) %{
13173 match(SafePoint);
13174 effect(KILL cr);
13176 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13177 // On SPARC that might be acceptable as we can generate the address with
13178 // just a sethi, saving an or. By polling at offset 0 we can end up
13179 // putting additional pressure on the index-0 in the D$. Because of
13180 // alignment (just like the situation at hand) the lower indices tend
13181 // to see more traffic. It'd be better to change the polling address
13182 // to offset 0 of the last $line in the polling page.
13184 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13185 ins_cost(125);
13186 size(6) ;
13187 ins_encode( Safepoint_Poll() );
13188 ins_pipe( ialu_reg_mem );
13189 %}
13192 // ============================================================================
13193 // This name is KNOWN by the ADLC and cannot be changed.
13194 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13195 // for this guy.
13196 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
13197 match(Set dst (ThreadLocal));
13198 effect(DEF dst, KILL cr);
13200 format %{ "MOV $dst, Thread::current()" %}
13201 ins_encode %{
13202 Register dstReg = as_Register($dst$$reg);
13203 __ get_thread(dstReg);
13204 %}
13205 ins_pipe( ialu_reg_fat );
13206 %}
13210 //----------PEEPHOLE RULES-----------------------------------------------------
13211 // These must follow all instruction definitions as they use the names
13212 // defined in the instructions definitions.
13213 //
13214 // peepmatch ( root_instr_name [preceding_instruction]* );
13215 //
13216 // peepconstraint %{
13217 // (instruction_number.operand_name relational_op instruction_number.operand_name
13218 // [, ...] );
13219 // // instruction numbers are zero-based using left to right order in peepmatch
13220 //
13221 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13222 // // provide an instruction_number.operand_name for each operand that appears
13223 // // in the replacement instruction's match rule
13224 //
13225 // ---------VM FLAGS---------------------------------------------------------
13226 //
13227 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13228 //
13229 // Each peephole rule is given an identifying number starting with zero and
13230 // increasing by one in the order seen by the parser. An individual peephole
13231 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13232 // on the command-line.
13233 //
13234 // ---------CURRENT LIMITATIONS----------------------------------------------
13235 //
13236 // Only match adjacent instructions in same basic block
13237 // Only equality constraints
13238 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13239 // Only one replacement instruction
13240 //
13241 // ---------EXAMPLE----------------------------------------------------------
13242 //
13243 // // pertinent parts of existing instructions in architecture description
13244 // instruct movI(rRegI dst, rRegI src) %{
13245 // match(Set dst (CopyI src));
13246 // %}
13247 //
13248 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13249 // match(Set dst (AddI dst src));
13250 // effect(KILL cr);
13251 // %}
13252 //
13253 // // Change (inc mov) to lea
13254 // peephole %{
13255 // // increment preceeded by register-register move
13256 // peepmatch ( incI_eReg movI );
13257 // // require that the destination register of the increment
13258 // // match the destination register of the move
13259 // peepconstraint ( 0.dst == 1.dst );
13260 // // construct a replacement instruction that sets
13261 // // the destination to ( move's source register + one )
13262 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13263 // %}
13264 //
13265 // Implementation no longer uses movX instructions since
13266 // machine-independent system no longer uses CopyX nodes.
13267 //
13268 // peephole %{
13269 // peepmatch ( incI_eReg movI );
13270 // peepconstraint ( 0.dst == 1.dst );
13271 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13272 // %}
13273 //
13274 // peephole %{
13275 // peepmatch ( decI_eReg movI );
13276 // peepconstraint ( 0.dst == 1.dst );
13277 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13278 // %}
13279 //
13280 // peephole %{
13281 // peepmatch ( addI_eReg_imm movI );
13282 // peepconstraint ( 0.dst == 1.dst );
13283 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13284 // %}
13285 //
13286 // peephole %{
13287 // peepmatch ( addP_eReg_imm movP );
13288 // peepconstraint ( 0.dst == 1.dst );
13289 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13290 // %}
13292 // // Change load of spilled value to only a spill
13293 // instruct storeI(memory mem, rRegI src) %{
13294 // match(Set mem (StoreI mem src));
13295 // %}
13296 //
13297 // instruct loadI(rRegI dst, memory mem) %{
13298 // match(Set dst (LoadI mem));
13299 // %}
13300 //
13301 peephole %{
13302 peepmatch ( loadI storeI );
13303 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13304 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13305 %}
13307 //----------SMARTSPILL RULES---------------------------------------------------
13308 // These must follow all instruction definitions as they use the names
13309 // defined in the instructions definitions.