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 //

 // Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved.

 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 //

 // This code is free software; you can redistribute it and/or modify it

 // under the terms of the GNU General Public License version 2 only, as

 // published by the Free Software Foundation.

 //

 // This code is distributed in the hope that it will be useful, but WITHOUT

 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 // version 2 for more details (a copy is included in the LICENSE file that

 // accompanied this code).

 //

 // You should have received a copy of the GNU General Public License version

 // 2 along with this work; if not, write to the Free Software Foundation,

 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 //

 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 // or visit www.oracle.com if you need additional information or have any

 // questions.

 //

 //

 // SPARC Architecture Description File

 //----------REGISTER DEFINITION BLOCK------------------------------------------

 // This information is used by the matcher and the register allocator to

 // describe individual registers and classes of registers within the target

 // archtecture.

 register %{

 //----------Architecture Description Register Definitions----------------------

 // General Registers

 // "reg_def"  name ( register save type, C convention save type,

 //                   ideal register type, encoding, vm name );

 // Register Save Types:

 //

 // NS  = No-Save:       The register allocator assumes that these registers

 //                      can be used without saving upon entry to the method, &

 //                      that they do not need to be saved at call sites.

 //

 // SOC = Save-On-Call:  The register allocator assumes that these registers

 //                      can be used without saving upon entry to the method,

 //                      but that they must be saved at call sites.

 //

 // SOE = Save-On-Entry: The register allocator assumes that these registers

 //                      must be saved before using them upon entry to the

 //                      method, but they do not need to be saved at call

 //                      sites.

 //

 // AS  = Always-Save:   The register allocator assumes that these registers

 //                      must be saved before using them upon entry to the

 //                      method, & that they must be saved at call sites.

 //

 // Ideal Register Type is used to determine how to save & restore a

 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get

 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.

 //

 // The encoding number is the actual bit-pattern placed into the opcodes.

 // ----------------------------

 // Integer/Long Registers

 // ----------------------------

 // Need to expose the hi/lo aspect of 64-bit registers

 // This register set is used for both the 64-bit build and

 // the 32-bit build with 1-register longs.

 // Global Registers 0-7

 reg_def R_G0H( NS,  NS, Op_RegI,128, G0->as_VMReg()->next());

 reg_def R_G0 ( NS,  NS, Op_RegI,  0, G0->as_VMReg());

 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());

 reg_def R_G1 (SOC, SOC, Op_RegI,  1, G1->as_VMReg());

 reg_def R_G2H( NS,  NS, Op_RegI,130, G2->as_VMReg()->next());

 reg_def R_G2 ( NS,  NS, Op_RegI,  2, G2->as_VMReg());

 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());

 reg_def R_G3 (SOC, SOC, Op_RegI,  3, G3->as_VMReg());

 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());

 reg_def R_G4 (SOC, SOC, Op_RegI,  4, G4->as_VMReg());

 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());

 reg_def R_G5 (SOC, SOC, Op_RegI,  5, G5->as_VMReg());

 reg_def R_G6H( NS,  NS, Op_RegI,134, G6->as_VMReg()->next());

 reg_def R_G6 ( NS,  NS, Op_RegI,  6, G6->as_VMReg());

 reg_def R_G7H( NS,  NS, Op_RegI,135, G7->as_VMReg()->next());

 reg_def R_G7 ( NS,  NS, Op_RegI,  7, G7->as_VMReg());

 // Output Registers 0-7

 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());

 reg_def R_O0 (SOC, SOC, Op_RegI,  8, O0->as_VMReg());

 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());

 reg_def R_O1 (SOC, SOC, Op_RegI,  9, O1->as_VMReg());

 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());

 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());

 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());

 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());

 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());

 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());

 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());

 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());

 reg_def R_SPH( NS,  NS, Op_RegI,142, SP->as_VMReg()->next());

 reg_def R_SP ( NS,  NS, Op_RegI, 14, SP->as_VMReg());

 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());

 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());

 // Local Registers 0-7

 reg_def R_L0H( NS,  NS, Op_RegI,144, L0->as_VMReg()->next());

 reg_def R_L0 ( NS,  NS, Op_RegI, 16, L0->as_VMReg());

 reg_def R_L1H( NS,  NS, Op_RegI,145, L1->as_VMReg()->next());

 reg_def R_L1 ( NS,  NS, Op_RegI, 17, L1->as_VMReg());

 reg_def R_L2H( NS,  NS, Op_RegI,146, L2->as_VMReg()->next());

 reg_def R_L2 ( NS,  NS, Op_RegI, 18, L2->as_VMReg());

 reg_def R_L3H( NS,  NS, Op_RegI,147, L3->as_VMReg()->next());

 reg_def R_L3 ( NS,  NS, Op_RegI, 19, L3->as_VMReg());

 reg_def R_L4H( NS,  NS, Op_RegI,148, L4->as_VMReg()->next());

 reg_def R_L4 ( NS,  NS, Op_RegI, 20, L4->as_VMReg());

 reg_def R_L5H( NS,  NS, Op_RegI,149, L5->as_VMReg()->next());

 reg_def R_L5 ( NS,  NS, Op_RegI, 21, L5->as_VMReg());

 reg_def R_L6H( NS,  NS, Op_RegI,150, L6->as_VMReg()->next());

 reg_def R_L6 ( NS,  NS, Op_RegI, 22, L6->as_VMReg());

 reg_def R_L7H( NS,  NS, Op_RegI,151, L7->as_VMReg()->next());

 reg_def R_L7 ( NS,  NS, Op_RegI, 23, L7->as_VMReg());

 // Input Registers 0-7

 reg_def R_I0H( NS,  NS, Op_RegI,152, I0->as_VMReg()->next());

 reg_def R_I0 ( NS,  NS, Op_RegI, 24, I0->as_VMReg());

 reg_def R_I1H( NS,  NS, Op_RegI,153, I1->as_VMReg()->next());

 reg_def R_I1 ( NS,  NS, Op_RegI, 25, I1->as_VMReg());

 reg_def R_I2H( NS,  NS, Op_RegI,154, I2->as_VMReg()->next());

 reg_def R_I2 ( NS,  NS, Op_RegI, 26, I2->as_VMReg());

 reg_def R_I3H( NS,  NS, Op_RegI,155, I3->as_VMReg()->next());

 reg_def R_I3 ( NS,  NS, Op_RegI, 27, I3->as_VMReg());

 reg_def R_I4H( NS,  NS, Op_RegI,156, I4->as_VMReg()->next());

 reg_def R_I4 ( NS,  NS, Op_RegI, 28, I4->as_VMReg());

 reg_def R_I5H( NS,  NS, Op_RegI,157, I5->as_VMReg()->next());

 reg_def R_I5 ( NS,  NS, Op_RegI, 29, I5->as_VMReg());

 reg_def R_FPH( NS,  NS, Op_RegI,158, FP->as_VMReg()->next());

 reg_def R_FP ( NS,  NS, Op_RegI, 30, FP->as_VMReg());

 reg_def R_I7H( NS,  NS, Op_RegI,159, I7->as_VMReg()->next());

 reg_def R_I7 ( NS,  NS, Op_RegI, 31, I7->as_VMReg());

 // ----------------------------

 // Float/Double Registers

 // ----------------------------

 // Float Registers

 reg_def R_F0 ( SOC, SOC, Op_RegF,  0, F0->as_VMReg());

 reg_def R_F1 ( SOC, SOC, Op_RegF,  1, F1->as_VMReg());

 reg_def R_F2 ( SOC, SOC, Op_RegF,  2, F2->as_VMReg());

 reg_def R_F3 ( SOC, SOC, Op_RegF,  3, F3->as_VMReg());

 reg_def R_F4 ( SOC, SOC, Op_RegF,  4, F4->as_VMReg());

 reg_def R_F5 ( SOC, SOC, Op_RegF,  5, F5->as_VMReg());

 reg_def R_F6 ( SOC, SOC, Op_RegF,  6, F6->as_VMReg());

 reg_def R_F7 ( SOC, SOC, Op_RegF,  7, F7->as_VMReg());

 reg_def R_F8 ( SOC, SOC, Op_RegF,  8, F8->as_VMReg());

 reg_def R_F9 ( SOC, SOC, Op_RegF,  9, F9->as_VMReg());

 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());

 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());

 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());

 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());

 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());

 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());

 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());

 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());

 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());

 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());

 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());

 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());

 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());

 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());

 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());

 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());

 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());

 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());

 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());

 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());

 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());

 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());

 // Double Registers

 // The rules of ADL require that double registers be defined in pairs.

 // Each pair must be two 32-bit values, but not necessarily a pair of

 // single float registers.  In each pair, ADLC-assigned register numbers

 // must be adjacent, with the lower number even.  Finally, when the

 // CPU stores such a register pair to memory, the word associated with

 // the lower ADLC-assigned number must be stored to the lower address.

 // These definitions specify the actual bit encodings of the sparc

 // double fp register numbers.  FloatRegisterImpl in register_sparc.hpp

 // wants 0-63, so we have to convert every time we want to use fp regs

 // with the macroassembler, using reg_to_DoubleFloatRegister_object().

 // 255 is a flag meaning "don't go here".

 // I believe we can't handle callee-save doubles D32 and up until

 // the place in the sparc stack crawler that asserts on the 255 is

 // fixed up.

 reg_def R_D32 (SOC, SOC, Op_RegD,  1, F32->as_VMReg());

 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());

 reg_def R_D34 (SOC, SOC, Op_RegD,  3, F34->as_VMReg());

 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());

 reg_def R_D36 (SOC, SOC, Op_RegD,  5, F36->as_VMReg());

 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());

 reg_def R_D38 (SOC, SOC, Op_RegD,  7, F38->as_VMReg());

 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());

 reg_def R_D40 (SOC, SOC, Op_RegD,  9, F40->as_VMReg());

 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());

 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());

 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());

 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());

 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());

 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());

 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());

 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());

 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());

 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());

 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());

 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());

 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());

 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());

 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());

 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());

 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());

 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());

 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());

 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());

 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());

 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());

 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());

 // ----------------------------

 // Special Registers

 // Condition Codes Flag Registers

 // I tried to break out ICC and XCC but it's not very pretty.

 // Every Sparc instruction which defs/kills one also kills the other.

 // Hence every compare instruction which defs one kind of flags ends

 // up needing a kill of the other.

 reg_def CCR (SOC, SOC,  Op_RegFlags, 0, VMRegImpl::Bad());

 reg_def FCC0(SOC, SOC,  Op_RegFlags, 0, VMRegImpl::Bad());

 reg_def FCC1(SOC, SOC,  Op_RegFlags, 1, VMRegImpl::Bad());

 reg_def FCC2(SOC, SOC,  Op_RegFlags, 2, VMRegImpl::Bad());

 reg_def FCC3(SOC, SOC,  Op_RegFlags, 3, VMRegImpl::Bad());

 // ----------------------------

 // Specify the enum values for the registers.  These enums are only used by the

 // OptoReg "class". We can convert these enum values at will to VMReg when needed

 // for visibility to the rest of the vm. The order of this enum influences the

 // register allocator so having the freedom to set this order and not be stuck

 // with the order that is natural for the rest of the vm is worth it.

 alloc_class chunk0(

   R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,

   R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,

   R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,

   R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);

 // Note that a register is not allocatable unless it is also mentioned

 // in a widely-used reg_class below.  Thus, R_G7 and R_G0 are outside i_reg.

 alloc_class chunk1(

   // The first registers listed here are those most likely to be used

   // as temporaries.  We move F0..F7 away from the front of the list,

   // to reduce the likelihood of interferences with parameters and

   // return values.  Likewise, we avoid using F0/F1 for parameters,

   // since they are used for return values.

   // This FPU fine-tuning is worth about 1% on the SPEC geomean.

   R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,

   R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,

   R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,

   R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values

   R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,

   R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,

   R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,

   R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);

 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);

 //----------Architecture Description Register Classes--------------------------

 // Several register classes are automatically defined based upon information in

 // this architecture description.

 // 1) reg_class inline_cache_reg           ( as defined in frame section )

 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )

 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )

 //

 // G0 is not included in integer class since it has special meaning.

 reg_class g0_reg(R_G0);

 // ----------------------------

 // Integer Register Classes

 // ----------------------------

 // Exclusions from i_reg:

 // R_G0: hardwired zero

 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)

 // R_G6: reserved by Solaris ABI to tools

 // R_G7: reserved by Solaris ABI to libthread

 // R_O7: Used as a temp in many encodings

 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);

 // Class for all integer registers, except the G registers.  This is used for

 // encodings which use G registers as temps.  The regular inputs to such

 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator

 // will not put an input into a temp register.

 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);

 reg_class g1_regI(R_G1);

 reg_class g3_regI(R_G3);

 reg_class g4_regI(R_G4);

 reg_class o0_regI(R_O0);

 reg_class o7_regI(R_O7);

 // ----------------------------

 // Pointer Register Classes

 // ----------------------------

 #ifdef _LP64

 // 64-bit build means 64-bit pointers means hi/lo pairs

 reg_class ptr_reg(            R_G1H,R_G1,             R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,

                   R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,

                   R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,

                   R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );

 // Lock encodings use G3 and G4 internally

 reg_class lock_ptr_reg(       R_G1H,R_G1,                                     R_G5H,R_G5,

                   R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,

                   R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,

                   R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );

 // Special class for storeP instructions, which can store SP or RPC to TLS.

 // It is also used for memory addressing, allowing direct TLS addressing.

 reg_class sp_ptr_reg(         R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,

                   R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,

                   R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,

                   R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );

 // R_L7 is the lowest-priority callee-save (i.e., NS) register

 // We use it to save R_G2 across calls out of Java.

 reg_class l7_regP(R_L7H,R_L7);

 // Other special pointer regs

 reg_class g1_regP(R_G1H,R_G1);

 reg_class g2_regP(R_G2H,R_G2);

 reg_class g3_regP(R_G3H,R_G3);

 reg_class g4_regP(R_G4H,R_G4);

 reg_class g5_regP(R_G5H,R_G5);

 reg_class i0_regP(R_I0H,R_I0);

 reg_class o0_regP(R_O0H,R_O0);

 reg_class o1_regP(R_O1H,R_O1);

 reg_class o2_regP(R_O2H,R_O2);

 reg_class o7_regP(R_O7H,R_O7);

 #else // _LP64

 // 32-bit build means 32-bit pointers means 1 register.

 reg_class ptr_reg(     R_G1,     R_G3,R_G4,R_G5,

                   R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,

                   R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,

                   R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);

 // Lock encodings use G3 and G4 internally

 reg_class lock_ptr_reg(R_G1,               R_G5,

                   R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,

                   R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,

                   R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);

 // Special class for storeP instructions, which can store SP or RPC to TLS.

 // It is also used for memory addressing, allowing direct TLS addressing.

 reg_class sp_ptr_reg(  R_G1,R_G2,R_G3,R_G4,R_G5,

                   R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,

                   R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,

                   R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);

 // R_L7 is the lowest-priority callee-save (i.e., NS) register

 // We use it to save R_G2 across calls out of Java.

 reg_class l7_regP(R_L7);

 // Other special pointer regs

 reg_class g1_regP(R_G1);

 reg_class g2_regP(R_G2);

 reg_class g3_regP(R_G3);

 reg_class g4_regP(R_G4);

 reg_class g5_regP(R_G5);

 reg_class i0_regP(R_I0);

 reg_class o0_regP(R_O0);

 reg_class o1_regP(R_O1);

 reg_class o2_regP(R_O2);

 reg_class o7_regP(R_O7);

 #endif // _LP64

 // ----------------------------

 // Long Register Classes

 // ----------------------------

 // Longs in 1 register.  Aligned adjacent hi/lo pairs.

 // Note:  O7 is never in this class; it is sometimes used as an encoding temp.

 reg_class long_reg(             R_G1H,R_G1,             R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5

                    ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5

 #ifdef _LP64

 // 64-bit, longs in 1 register: use all 64-bit integer registers

 // 32-bit, longs in 1 register: cannot use I's and L's.  Restrict to O's and G's.

                    ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7

                    ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5

 #endif // _LP64

                   );

 reg_class g1_regL(R_G1H,R_G1);

 reg_class g3_regL(R_G3H,R_G3);

 reg_class o2_regL(R_O2H,R_O2);

 reg_class o7_regL(R_O7H,R_O7);

 // ----------------------------

 // Special Class for Condition Code Flags Register

 reg_class int_flags(CCR);

 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);

 reg_class float_flag0(FCC0);

 // ----------------------------

 // Float Point Register Classes

 // ----------------------------

 // Skip F30/F31, they are reserved for mem-mem copies

 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);

 // Paired floating point registers--they show up in the same order as the floats,

 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.

 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,

                    R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,

                    /* Use extra V9 double registers; this AD file does not support V8 */

                    R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,

                    R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x

                    );

 // Paired floating point registers--they show up in the same order as the floats,

 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.

 // This class is usable for mis-aligned loads as happen in I2C adapters.

 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,

                    R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);

 %}

 //----------DEFINITION BLOCK---------------------------------------------------

 // Define name --> value mappings to inform the ADLC of an integer valued name

 // Current support includes integer values in the range [0, 0x7FFFFFFF]

 // Format:

 //        int_def  <name>         ( <int_value>, <expression>);

 // Generated Code in ad_<arch>.hpp

 //        #define  <name>   (<expression>)

 //        // value == <int_value>

 // Generated code in ad_<arch>.cpp adlc_verification()

 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");

 //

 definitions %{

 // The default cost (of an ALU instruction).

   int_def DEFAULT_COST      (    100,     100);

   int_def HUGE_COST         (1000000, 1000000);

 // Memory refs are twice as expensive as run-of-the-mill.

   int_def MEMORY_REF_COST   (    200, DEFAULT_COST * 2);

 // Branches are even more expensive.

   int_def BRANCH_COST       (    300, DEFAULT_COST * 3);

   int_def CALL_COST         (    300, DEFAULT_COST * 3);

 %}

 //----------SOURCE BLOCK-------------------------------------------------------

 // This is a block of C++ code which provides values, functions, and

 // definitions necessary in the rest of the architecture description

 source_hpp %{

 // Must be visible to the DFA in dfa_sparc.cpp

 extern bool can_branch_register( Node *bol, Node *cmp );

 extern bool use_block_zeroing(Node* count);

 // Macros to extract hi & lo halves from a long pair.

 // G0 is not part of any long pair, so assert on that.

 // Prevents accidentally using G1 instead of G0.

 #define LONG_HI_REG(x) (x)

 #define LONG_LO_REG(x) (x)

 %}

 source %{

 #define __ _masm.

 // tertiary op of a LoadP or StoreP encoding

 #define REGP_OP true

 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);

 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);

 static Register reg_to_register_object(int register_encoding);

 // Used by the DFA in dfa_sparc.cpp.

 // Check for being able to use a V9 branch-on-register.  Requires a

 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-

 // extended.  Doesn't work following an integer ADD, for example, because of

 // overflow (-1 incremented yields 0 plus a carry in the high-order word).  On

 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and

 // replace them with zero, which could become sign-extension in a different OS

 // release.  There's no obvious reason why an interrupt will ever fill these

 // bits with non-zero junk (the registers are reloaded with standard LD

 // instructions which either zero-fill or sign-fill).

 bool can_branch_register( Node *bol, Node *cmp ) {

   if( !BranchOnRegister ) return false;

 #ifdef _LP64

   if( cmp->Opcode() == Op_CmpP )

     return true;  // No problems with pointer compares

 #endif

   if( cmp->Opcode() == Op_CmpL )

     return true;  // No problems with long compares

   if( !SparcV9RegsHiBitsZero ) return false;

   if( bol->as_Bool()->_test._test != BoolTest::ne &&

       bol->as_Bool()->_test._test != BoolTest::eq )

      return false;

   // Check for comparing against a 'safe' value.  Any operation which

   // clears out the high word is safe.  Thus, loads and certain shifts

   // are safe, as are non-negative constants.  Any operation which

   // preserves zero bits in the high word is safe as long as each of its

   // inputs are safe.  Thus, phis and bitwise booleans are safe if their

   // inputs are safe.  At present, the only important case to recognize

   // seems to be loads.  Constants should fold away, and shifts &

   // logicals can use the 'cc' forms.

   Node *x = cmp->in(1);

   if( x->is_Load() ) return true;

   if( x->is_Phi() ) {

     for( uint i = 1; i < x->req(); i++ )

       if( !x->in(i)->is_Load() )

         return false;

     return true;

   }

   return false;

 }

 bool use_block_zeroing(Node* count) {

   // Use BIS for zeroing if count is not constant

   // or it is >= BlockZeroingLowLimit.

   return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);

 }

 // ****************************************************************************

 // REQUIRED FUNCTIONALITY

 // !!!!! Special hack to get all type of calls to specify the byte offset

 //       from the start of the call to the point where the return address

 //       will point.

 //       The "return address" is the address of the call instruction, plus 8.

 int MachCallStaticJavaNode::ret_addr_offset() {

   int offset = NativeCall::instruction_size;  // call; delay slot

   if (_method_handle_invoke)

     offset += 4;  // restore SP

   return offset;

 }

 int MachCallDynamicJavaNode::ret_addr_offset() {

   int vtable_index = this->_vtable_index;

   if (vtable_index < 0) {

     // must be invalid_vtable_index, not nonvirtual_vtable_index

     assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");

     return (NativeMovConstReg::instruction_size +

            NativeCall::instruction_size);  // sethi; setlo; call; delay slot

   } else {

     assert(!UseInlineCaches, "expect vtable calls only if not using ICs");

     int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();

     int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();

     int klass_load_size;

     if (UseCompressedClassPointers) {

       assert(Universe::heap() != NULL, "java heap should be initialized");

       klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;

     } else {

       klass_load_size = 1*BytesPerInstWord;

     }

     if (Assembler::is_simm13(v_off)) {

       return klass_load_size +

              (2*BytesPerInstWord +           // ld_ptr, ld_ptr

              NativeCall::instruction_size);  // call; delay slot

     } else {

       return klass_load_size +

              (4*BytesPerInstWord +           // set_hi, set, ld_ptr, ld_ptr

              NativeCall::instruction_size);  // call; delay slot

     }

   }

 }

 int MachCallRuntimeNode::ret_addr_offset() {

 #ifdef _LP64

   if (MacroAssembler::is_far_target(entry_point())) {

     return NativeFarCall::instruction_size;

   } else {

     return NativeCall::instruction_size;

   }

 #else

   return NativeCall::instruction_size;  // call; delay slot

 #endif

 }

 // Indicate if the safepoint node needs the polling page as an input.

 // Since Sparc does not have absolute addressing, it does.

 bool SafePointNode::needs_polling_address_input() {

   return true;

 }

 // emit an interrupt that is caught by the debugger (for debugging compiler)

 void emit_break(CodeBuffer &cbuf) {

   MacroAssembler _masm(&cbuf);

   __ breakpoint_trap();

 }

 #ifndef PRODUCT

 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {

   st->print("TA");

 }

 #endif

 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {

   emit_break(cbuf);

 }

 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {

   return MachNode::size(ra_);

 }

 // Traceable jump

 void  emit_jmpl(CodeBuffer &cbuf, int jump_target) {

   MacroAssembler _masm(&cbuf);

   Register rdest = reg_to_register_object(jump_target);

   __ JMP(rdest, 0);

   __ delayed()->nop();

 }

 // Traceable jump and set exception pc

 void  emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {

   MacroAssembler _masm(&cbuf);

   Register rdest = reg_to_register_object(jump_target);

   __ JMP(rdest, 0);

   __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );

 }

 void emit_nop(CodeBuffer &cbuf) {

   MacroAssembler _masm(&cbuf);

   __ nop();

 }

 void emit_illtrap(CodeBuffer &cbuf) {

   MacroAssembler _masm(&cbuf);

   __ illtrap(0);

 }

 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {

   assert(n->rule() != loadUB_rule, "");

   intptr_t offset = 0;

   const TypePtr *adr_type = TYPE_PTR_SENTINAL;  // Check for base==RegI, disp==immP

   const Node* addr = n->get_base_and_disp(offset, adr_type);

   assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");

   assert(addr != NULL && addr != (Node*)-1, "invalid addr");

   assert(addr->bottom_type()->isa_oopptr() == atype, "");

   atype = atype->add_offset(offset);

   assert(disp32 == offset, "wrong disp32");

   return atype->_offset;

 }

 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {

   assert(n->rule() != loadUB_rule, "");

   intptr_t offset = 0;

   Node* addr = n->in(2);

   assert(addr->bottom_type()->isa_oopptr() == atype, "");

   if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {

     Node* a = addr->in(2/*AddPNode::Address*/);

     Node* o = addr->in(3/*AddPNode::Offset*/);

     offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;

     atype = a->bottom_type()->is_ptr()->add_offset(offset);

     assert(atype->isa_oop_ptr(), "still an oop");

   }

   offset = atype->is_ptr()->_offset;

   if (offset != Type::OffsetBot)  offset += disp32;

   return offset;

 }

 static inline jdouble replicate_immI(int con, int count, int width) {

   // Load a constant replicated "count" times with width "width"

   assert(count*width == 8 && width <= 4, "sanity");

   int bit_width = width * 8;

   jlong val = con;

   val &= (((jlong) 1) << bit_width) - 1;  // mask off sign bits

   for (int i = 0; i < count - 1; i++) {

     val |= (val << bit_width);

   }

   jdouble dval = *((jdouble*) &val);  // coerce to double type

   return dval;

 }

 static inline jdouble replicate_immF(float con) {

   // Replicate float con 2 times and pack into vector.

   int val = *((int*)&con);

   jlong lval = val;

   lval = (lval << 32) | (lval & 0xFFFFFFFFl);

   jdouble dval = *((jdouble*) &lval);  // coerce to double type

   return dval;

 }

 // Standard Sparc opcode form2 field breakdown

 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {

   f0 &= (1<<19)-1;     // Mask displacement to 19 bits

   int op = (f30 << 30) |

            (f29 << 29) |

            (f25 << 25) |

            (f22 << 22) |

            (f20 << 20) |

            (f19 << 19) |

            (f0  <<  0);

   cbuf.insts()->emit_int32(op);

 }

 // Standard Sparc opcode form2 field breakdown

 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {

   f0 >>= 10;           // Drop 10 bits

   f0 &= (1<<22)-1;     // Mask displacement to 22 bits

   int op = (f30 << 30) |

            (f25 << 25) |

            (f22 << 22) |

            (f0  <<  0);

   cbuf.insts()->emit_int32(op);

 }

 // Standard Sparc opcode form3 field breakdown

 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {

   int op = (f30 << 30) |

            (f25 << 25) |

            (f19 << 19) |

            (f14 << 14) |

            (f5  <<  5) |

            (f0  <<  0);

   cbuf.insts()->emit_int32(op);

 }

 // Standard Sparc opcode form3 field breakdown

 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {

   simm13 &= (1<<13)-1; // Mask to 13 bits

   int op = (f30 << 30) |

            (f25 << 25) |

            (f19 << 19) |

            (f14 << 14) |

            (1   << 13) | // bit to indicate immediate-mode

            (simm13<<0);

   cbuf.insts()->emit_int32(op);

 }

 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {

   simm10 &= (1<<10)-1; // Mask to 10 bits

   emit3_simm13(cbuf,f30,f25,f19,f14,simm10);

 }

 #ifdef ASSERT

 // Helper function for VerifyOops in emit_form3_mem_reg

 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {

   warning("VerifyOops encountered unexpected instruction:");

   n->dump(2);

   warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);

 }

 #endif

 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,

                         int src1_enc, int disp32, int src2_enc, int dst_enc) {

 #ifdef ASSERT

   // The following code implements the +VerifyOops feature.

   // It verifies oop values which are loaded into or stored out of

   // the current method activation.  +VerifyOops complements techniques

   // like ScavengeALot, because it eagerly inspects oops in transit,

   // as they enter or leave the stack, as opposed to ScavengeALot,

   // which inspects oops "at rest", in the stack or heap, at safepoints.

   // For this reason, +VerifyOops can sometimes detect bugs very close

   // to their point of creation.  It can also serve as a cross-check

   // on the validity of oop maps, when used toegether with ScavengeALot.

   // It would be good to verify oops at other points, especially

   // when an oop is used as a base pointer for a load or store.

   // This is presently difficult, because it is hard to know when

   // a base address is biased or not.  (If we had such information,

   // it would be easy and useful to make a two-argument version of

   // verify_oop which unbiases the base, and performs verification.)

   assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");

   bool is_verified_oop_base  = false;

   bool is_verified_oop_load  = false;

   bool is_verified_oop_store = false;

   int tmp_enc = -1;

   if (VerifyOops && src1_enc != R_SP_enc) {

     // classify the op, mainly for an assert check

     int st_op = 0, ld_op = 0;

     switch (primary) {

     case Assembler::stb_op3:  st_op = Op_StoreB; break;

     case Assembler::sth_op3:  st_op = Op_StoreC; break;

     case Assembler::stx_op3:  // may become StoreP or stay StoreI or StoreD0

     case Assembler::stw_op3:  st_op = Op_StoreI; break;

     case Assembler::std_op3:  st_op = Op_StoreL; break;

     case Assembler::stf_op3:  st_op = Op_StoreF; break;

     case Assembler::stdf_op3: st_op = Op_StoreD; break;

     case Assembler::ldsb_op3: ld_op = Op_LoadB; break;

     case Assembler::ldub_op3: ld_op = Op_LoadUB; break;

     case Assembler::lduh_op3: ld_op = Op_LoadUS; break;

     case Assembler::ldsh_op3: ld_op = Op_LoadS; break;

     case Assembler::ldx_op3:  // may become LoadP or stay LoadI

     case Assembler::ldsw_op3: // may become LoadP or stay LoadI

     case Assembler::lduw_op3: ld_op = Op_LoadI; break;

     case Assembler::ldd_op3:  ld_op = Op_LoadL; break;

     case Assembler::ldf_op3:  ld_op = Op_LoadF; break;

     case Assembler::lddf_op3: ld_op = Op_LoadD; break;

     case Assembler::prefetch_op3: ld_op = Op_LoadI; break;

     default: ShouldNotReachHere();

     }

     if (tertiary == REGP_OP) {

       if      (st_op == Op_StoreI)  st_op = Op_StoreP;

       else if (ld_op == Op_LoadI)   ld_op = Op_LoadP;

       else                          ShouldNotReachHere();

       if (st_op) {

         // a store

         // inputs are (0:control, 1:memory, 2:address, 3:value)

         Node* n2 = n->in(3);

         if (n2 != NULL) {

           const Type* t = n2->bottom_type();

           is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;

         }

       } else {

         // a load

         const Type* t = n->bottom_type();

         is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;

       }

     }

     if (ld_op) {

       // a Load

       // inputs are (0:control, 1:memory, 2:address)

       if (!(n->ideal_Opcode()==ld_op)       && // Following are special cases

           !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&

           !(n->ideal_Opcode()==Op_LoadI     && ld_op==Op_LoadF) &&

           !(n->ideal_Opcode()==Op_LoadF     && ld_op==Op_LoadI) &&

           !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&

           !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&

           !(n->ideal_Opcode()==Op_LoadL     && ld_op==Op_LoadI) &&

           !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&

           !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&

           !(n->ideal_Opcode()==Op_ConvI2F   && ld_op==Op_LoadF) &&

           !(n->ideal_Opcode()==Op_ConvI2D   && ld_op==Op_LoadF) &&

           !(n->ideal_Opcode()==Op_PrefetchRead  && ld_op==Op_LoadI) &&

           !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&

           !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&

           !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&

           !(n->rule() == loadUB_rule)) {

         verify_oops_warning(n, n->ideal_Opcode(), ld_op);

       }

     } else if (st_op) {

       // a Store

       // inputs are (0:control, 1:memory, 2:address, 3:value)

       if (!(n->ideal_Opcode()==st_op)    && // Following are special cases

           !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&

           !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&

           !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&

           !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&

           !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&

           !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {

         verify_oops_warning(n, n->ideal_Opcode(), st_op);

       }

     }

     if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {

       Node* addr = n->in(2);

       if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {

         const TypeOopPtr* atype = addr->bottom_type()->isa_instptr();  // %%% oopptr?

         if (atype != NULL) {

           intptr_t offset = get_offset_from_base(n, atype, disp32);

           intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);

           if (offset != offset_2) {

             get_offset_from_base(n, atype, disp32);

             get_offset_from_base_2(n, atype, disp32);

           }

           assert(offset == offset_2, "different offsets");

           if (offset == disp32) {

             // we now know that src1 is a true oop pointer

             is_verified_oop_base = true;

             if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {

               if( primary == Assembler::ldd_op3 ) {

                 is_verified_oop_base = false; // Cannot 'ldd' into O7

               } else {

                 tmp_enc = dst_enc;

                 dst_enc = R_O7_enc; // Load into O7; preserve source oop

                 assert(src1_enc != dst_enc, "");

               }

             }

           }

           if (st_op && (( offset == oopDesc::klass_offset_in_bytes())

                        || offset == oopDesc::mark_offset_in_bytes())) {

                       // loading the mark should not be allowed either, but

                       // we don't check this since it conflicts with InlineObjectHash

                       // usage of LoadINode to get the mark. We could keep the

                       // check if we create a new LoadMarkNode

             // but do not verify the object before its header is initialized

             ShouldNotReachHere();

           }

         }

       }

     }

   }

 #endif

   uint instr;

   instr = (Assembler::ldst_op << 30)

         | (dst_enc        << 25)

         | (primary        << 19)

         | (src1_enc       << 14);

   uint index = src2_enc;

   int disp = disp32;

   if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)

     disp += STACK_BIAS;

   // We should have a compiler bailout here rather than a guarantee.

   // Better yet would be some mechanism to handle variable-size matches correctly.

   guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );

   if( disp == 0 ) {

     // use reg-reg form

     // bit 13 is already zero

     instr |= index;

   } else {

     // use reg-imm form

     instr |= 0x00002000;          // set bit 13 to one

     instr |= disp & 0x1FFF;

   }

   cbuf.insts()->emit_int32(instr);

 #ifdef ASSERT

   {

     MacroAssembler _masm(&cbuf);

     if (is_verified_oop_base) {

       __ verify_oop(reg_to_register_object(src1_enc));

     }

     if (is_verified_oop_store) {

       __ verify_oop(reg_to_register_object(dst_enc));

     }

     if (tmp_enc != -1) {

       __ mov(O7, reg_to_register_object(tmp_enc));

     }

     if (is_verified_oop_load) {

       __ verify_oop(reg_to_register_object(dst_enc));

     }

   }

 #endif

 }

 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {

   // The method which records debug information at every safepoint

   // expects the call to be the first instruction in the snippet as

   // it creates a PcDesc structure which tracks the offset of a call

   // from the start of the codeBlob. This offset is computed as

   // code_end() - code_begin() of the code which has been emitted

   // so far.

   // In this particular case we have skirted around the problem by

   // putting the "mov" instruction in the delay slot but the problem

   // may bite us again at some other point and a cleaner/generic

   // solution using relocations would be needed.

   MacroAssembler _masm(&cbuf);

   __ set_inst_mark();

   // We flush the current window just so that there is a valid stack copy

   // the fact that the current window becomes active again instantly is

   // not a problem there is nothing live in it.

 #ifdef ASSERT

   int startpos = __ offset();

 #endif /* ASSERT */

   __ call((address)entry_point, rtype);

   if (preserve_g2)   __ delayed()->mov(G2, L7);

   else __ delayed()->nop();

   if (preserve_g2)   __ mov(L7, G2);

 #ifdef ASSERT

   if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {

 #ifdef _LP64

     // Trash argument dump slots.

     __ set(0xb0b8ac0db0b8ac0d, G1);

     __ mov(G1, G5);

     __ stx(G1, SP, STACK_BIAS + 0x80);

     __ stx(G1, SP, STACK_BIAS + 0x88);

     __ stx(G1, SP, STACK_BIAS + 0x90);

     __ stx(G1, SP, STACK_BIAS + 0x98);

     __ stx(G1, SP, STACK_BIAS + 0xA0);

     __ stx(G1, SP, STACK_BIAS + 0xA8);

 #else // _LP64

     // this is also a native call, so smash the first 7 stack locations,

     // and the various registers

     // Note:  [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],

     // while [SP+0x44..0x58] are the argument dump slots.

     __ set((intptr_t)0xbaadf00d, G1);

     __ mov(G1, G5);

     __ sllx(G1, 32, G1);

     __ or3(G1, G5, G1);

     __ mov(G1, G5);

     __ stx(G1, SP, 0x40);

     __ stx(G1, SP, 0x48);

     __ stx(G1, SP, 0x50);

     __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot

 #endif // _LP64

   }

 #endif /*ASSERT*/

 }

 //=============================================================================

 // REQUIRED FUNCTIONALITY for encoding

 void emit_lo(CodeBuffer &cbuf, int val) {  }

 void emit_hi(CodeBuffer &cbuf, int val) {  }

 //=============================================================================

 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();

 int Compile::ConstantTable::calculate_table_base_offset() const {

   if (UseRDPCForConstantTableBase) {

     // The table base offset might be less but then it fits into

     // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).

     return Assembler::min_simm13();

   } else {

     int offset = -(size() / 2);

     if (!Assembler::is_simm13(offset)) {

       offset = Assembler::min_simm13();

     }

     return offset;

   }

 }

 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }

 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {

   ShouldNotReachHere();

 }

 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {

   Compile* C = ra_->C;

   Compile::ConstantTable& constant_table = C->constant_table();

   MacroAssembler _masm(&cbuf);

   Register r = as_Register(ra_->get_encode(this));

   CodeSection* consts_section = __ code()->consts();

   int consts_size = consts_section->align_at_start(consts_section->size());

   assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));

   if (UseRDPCForConstantTableBase) {

     // For the following RDPC logic to work correctly the consts

     // section must be allocated right before the insts section.  This

     // assert checks for that.  The layout and the SECT_* constants

     // are defined in src/share/vm/asm/codeBuffer.hpp.

     assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");

     int insts_offset = __ offset();

     // Layout:

     //

     // |----------- consts section ------------|----------- insts section -----------...

     // |------ constant table -----|- padding -|------------------x----

     //                                                            \ current PC (RDPC instruction)

     // |<------------- consts_size ----------->|<- insts_offset ->|

     //                                                            \ table base

     // The table base offset is later added to the load displacement

     // so it has to be negative.

     int table_base_offset = -(consts_size + insts_offset);

     int disp;

     // If the displacement from the current PC to the constant table

     // base fits into simm13 we set the constant table base to the

     // current PC.

     if (Assembler::is_simm13(table_base_offset)) {

       constant_table.set_table_base_offset(table_base_offset);

       disp = 0;

     } else {

       // Otherwise we set the constant table base offset to the

       // maximum negative displacement of load instructions to keep

       // the disp as small as possible:

       //

       // |<------------- consts_size ----------->|<- insts_offset ->|

       // |<--------- min_simm13 --------->|<-------- disp --------->|

       //                                  \ table base

       table_base_offset = Assembler::min_simm13();

       constant_table.set_table_base_offset(table_base_offset);

       disp = (consts_size + insts_offset) + table_base_offset;

     }

     __ rdpc(r);

     if (disp != 0) {

       assert(r != O7, "need temporary");

       __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);

     }

   }

   else {

     // Materialize the constant table base.

     address baseaddr = consts_section->start() + -(constant_table.table_base_offset());

     RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);

     AddressLiteral base(baseaddr, rspec);

     __ set(base, r);

   }

 }

 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {

   if (UseRDPCForConstantTableBase) {

     // This is really the worst case but generally it's only 1 instruction.

     return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;

   } else {

     return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;

   }

 }

 #ifndef PRODUCT

 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {

   char reg[128];

   ra_->dump_register(this, reg);

   if (UseRDPCForConstantTableBase) {

     st->print("RDPC   %s\t! constant table base", reg);

   } else {

     st->print("SET    &constanttable,%s\t! constant table base", reg);

   }

 }

 #endif

 //=============================================================================

 #ifndef PRODUCT

 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {

   Compile* C = ra_->C;

   for (int i = 0; i < OptoPrologueNops; i++) {

     st->print_cr("NOP"); st->print("\t");

   }

   if( VerifyThread ) {

     st->print_cr("Verify_Thread"); st->print("\t");

   }

   size_t framesize = C->frame_slots() << LogBytesPerInt;

   // Calls to C2R adapters often do not accept exceptional returns.

   // We require that their callers must bang for them.  But be careful, because

   // some VM calls (such as call site linkage) can use several kilobytes of

   // stack.  But the stack safety zone should account for that.

   // See bugs 4446381, 4468289, 4497237.

   if (C->need_stack_bang(framesize)) {

     st->print_cr("! stack bang"); st->print("\t");

   }

   if (Assembler::is_simm13(-framesize)) {

     st->print   ("SAVE   R_SP,-%d,R_SP",framesize);

   } else {

     st->print_cr("SETHI  R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");

     st->print_cr("ADD    R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");

     st->print   ("SAVE   R_SP,R_G3,R_SP");

   }

 }

 #endif

 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {

   Compile* C = ra_->C;

   MacroAssembler _masm(&cbuf);

   for (int i = 0; i < OptoPrologueNops; i++) {

     __ nop();

   }

   __ verify_thread();

   size_t framesize = C->frame_slots() << LogBytesPerInt;

   assert(framesize >= 16*wordSize, "must have room for reg. save area");

   assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");

   // Calls to C2R adapters often do not accept exceptional returns.

   // We require that their callers must bang for them.  But be careful, because

   // some VM calls (such as call site linkage) can use several kilobytes of

   // stack.  But the stack safety zone should account for that.

   // See bugs 4446381, 4468289, 4497237.

   if (C->need_stack_bang(framesize)) {

     __ generate_stack_overflow_check(framesize);

   }

   if (Assembler::is_simm13(-framesize)) {

     __ save(SP, -framesize, SP);

   } else {

     __ sethi(-framesize & ~0x3ff, G3);

     __ add(G3, -framesize & 0x3ff, G3);

     __ save(SP, G3, SP);

   }

   C->set_frame_complete( __ offset() );

   if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {

     // NOTE: We set the table base offset here because users might be

     // emitted before MachConstantBaseNode.

     Compile::ConstantTable& constant_table = C->constant_table();

     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());

   }

 }

 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {

   return MachNode::size(ra_);

 }

 int MachPrologNode::reloc() const {

   return 10; // a large enough number

 }

 //=============================================================================

 #ifndef PRODUCT

 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {

   Compile* C = ra_->C;

   if( do_polling() && ra_->C->is_method_compilation() ) {

     st->print("SETHI  #PollAddr,L0\t! Load Polling address\n\t");

 #ifdef _LP64

     st->print("LDX    [L0],G0\t!Poll for Safepointing\n\t");

 #else

     st->print("LDUW   [L0],G0\t!Poll for Safepointing\n\t");

 #endif

   }

   if( do_polling() )

     st->print("RET\n\t");

   st->print("RESTORE");

 }

 #endif

 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {

   MacroAssembler _masm(&cbuf);

   Compile* C = ra_->C;

   __ verify_thread();

   // If this does safepoint polling, then do it here

   if( do_polling() && ra_->C->is_method_compilation() ) {

     AddressLiteral polling_page(os::get_polling_page());

     __ sethi(polling_page, L0);

     __ relocate(relocInfo::poll_return_type);

     __ ld_ptr( L0, 0, G0 );

   }

   // If this is a return, then stuff the restore in the delay slot

   if( do_polling() ) {

     __ ret();

     __ delayed()->restore();

   } else {

     __ restore();

   }

 }

 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {

   return MachNode::size(ra_);

 }

 int MachEpilogNode::reloc() const {

   return 16; // a large enough number

 }

 const Pipeline * MachEpilogNode::pipeline() const {

   return MachNode::pipeline_class();

 }

 int MachEpilogNode::safepoint_offset() const {

   assert( do_polling(), "no return for this epilog node");

   return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;

 }

 //=============================================================================

 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack

 enum RC { rc_bad, rc_int, rc_float, rc_stack };

 static enum RC rc_class( OptoReg::Name reg ) {

   if( !OptoReg::is_valid(reg)  ) return rc_bad;

   if (OptoReg::is_stack(reg)) return rc_stack;

   VMReg r = OptoReg::as_VMReg(reg);

   if (r->is_Register()) return rc_int;

   assert(r->is_FloatRegister(), "must be");

   return rc_float;

 }

 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {

   if( cbuf ) {

     // Better yet would be some mechanism to handle variable-size matches correctly

     if (!Assembler::is_simm13(offset + STACK_BIAS)) {

       ra_->C->record_method_not_compilable("unable to handle large constant offsets");

     } else {

       emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);

     }

   }

 #ifndef PRODUCT

   else if( !do_size ) {

     if( size != 0 ) st->print("\n\t");

     if( is_load ) st->print("%s   [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));

     else          st->print("%s   R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);

   }

 #endif

   return size+4;

 }

 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {

   if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );

 #ifndef PRODUCT

   else if( !do_size ) {

     if( size != 0 ) st->print("\n\t");

     st->print("%s  R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));

   }

 #endif

   return size+4;

 }

 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,

                                         PhaseRegAlloc *ra_,

                                         bool do_size,

                                         outputStream* st ) const {

   // Get registers to move

   OptoReg::Name src_second = ra_->get_reg_second(in(1));

   OptoReg::Name src_first = ra_->get_reg_first(in(1));

   OptoReg::Name dst_second = ra_->get_reg_second(this );

   OptoReg::Name dst_first = ra_->get_reg_first(this );

   enum RC src_second_rc = rc_class(src_second);

   enum RC src_first_rc = rc_class(src_first);

   enum RC dst_second_rc = rc_class(dst_second);

   enum RC dst_first_rc = rc_class(dst_first);

   assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );

   // Generate spill code!

   int size = 0;

   if( src_first == dst_first && src_second == dst_second )

     return size;            // Self copy, no move

   // --------------------------------------

   // Check for mem-mem move.  Load into unused float registers and fall into

   // the float-store case.

   if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {

     int offset = ra_->reg2offset(src_first);

     // Further check for aligned-adjacent pair, so we can use a double load

     if( (src_first&1)==0 && src_first+1 == src_second ) {

       src_second    = OptoReg::Name(R_F31_num);

       src_second_rc = rc_float;

       size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);

     } else {

       size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);

     }

     src_first    = OptoReg::Name(R_F30_num);

     src_first_rc = rc_float;

   }

   if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {

     int offset = ra_->reg2offset(src_second);

     size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);

     src_second    = OptoReg::Name(R_F31_num);

     src_second_rc = rc_float;

   }

   // --------------------------------------

   // Check for float->int copy; requires a trip through memory

   if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {

     int offset = frame::register_save_words*wordSize;

     if (cbuf) {

       emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );

       impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);

       impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);

       emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );

     }

 #ifndef PRODUCT

     else if (!do_size) {

       if (size != 0) st->print("\n\t");

       st->print(  "SUB    R_SP,16,R_SP\n");

       impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);

       impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);

       st->print("\tADD    R_SP,16,R_SP\n");

     }

 #endif

     size += 16;

   }

   // Check for float->int copy on T4

   if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {

     // Further check for aligned-adjacent pair, so we can use a double move

     if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)

       return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);

     size  =  impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);

   }

   // Check for int->float copy on T4

   if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {

     // Further check for aligned-adjacent pair, so we can use a double move

     if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)

       return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);

     size  =  impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);

   }

   // --------------------------------------

   // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.

   // In such cases, I have to do the big-endian swap.  For aligned targets, the

   // hardware does the flop for me.  Doubles are always aligned, so no problem

   // there.  Misaligned sources only come from native-long-returns (handled

   // special below).

 #ifndef _LP64

   if( src_first_rc == rc_int &&     // source is already big-endian

       src_second_rc != rc_bad &&    // 64-bit move

       ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst

     assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );

     // Do the big-endian flop.

     OptoReg::Name tmp    = dst_first   ; dst_first    = dst_second   ; dst_second    = tmp   ;

     enum RC       tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;

   }

 #endif

   // --------------------------------------

   // Check for integer reg-reg copy

   if( src_first_rc == rc_int && dst_first_rc == rc_int ) {

 #ifndef _LP64

     if( src_first == R_O0_num && src_second == R_O1_num ) {  // Check for the evil O0/O1 native long-return case

       // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value

       //       as stored in memory.  On a big-endian machine like SPARC, this means that the _second

       //       operand contains the least significant word of the 64-bit value and vice versa.

       OptoReg::Name tmp = OptoReg::Name(R_O7_num);

       assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );

       // Shift O0 left in-place, zero-extend O1, then OR them into the dst

       if( cbuf ) {

         emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );

         emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );

         emit3       ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );

 #ifndef PRODUCT

       } else if( !do_size ) {

         if( size != 0 ) st->print("\n\t");

         st->print("SLLX   R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));

         st->print("SRL    R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));

         st->print("OR     R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));

 #endif

       }

       return size+12;

     }

     else if( dst_first == R_I0_num && dst_second == R_I1_num ) {

       // returning a long value in I0/I1

       // a SpillCopy must be able to target a return instruction's reg_class

       // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value

       //       as stored in memory.  On a big-endian machine like SPARC, this means that the _second

       //       operand contains the least significant word of the 64-bit value and vice versa.

       OptoReg::Name tdest = dst_first;

       if (src_first == dst_first) {

         tdest = OptoReg::Name(R_O7_num);

         size += 4;

       }

       if( cbuf ) {

         assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");

         // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1

         // ShrL_reg_imm6

         emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );

         // ShrR_reg_imm6  src, 0, dst

         emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );

         if (tdest != dst_first) {

           emit3     ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );

         }

       }

 #ifndef PRODUCT

       else if( !do_size ) {

         if( size != 0 ) st->print("\n\t");  // %%%%% !!!!!

         st->print("SRLX   R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));

         st->print("SRL    R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));

         if (tdest != dst_first) {

           st->print("MOV    R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));

         }

       }

 #endif // PRODUCT

       return size+8;

     }

 #endif // !_LP64

     // Else normal reg-reg copy

     assert( src_second != dst_first, "smashed second before evacuating it" );

     size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV  ",size, st);

     assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );

     // This moves an aligned adjacent pair.

     // See if we are done.

     if( src_first+1 == src_second && dst_first+1 == dst_second )

       return size;

   }

   // Check for integer store

   if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {

     int offset = ra_->reg2offset(dst_first);

     // Further check for aligned-adjacent pair, so we can use a double store

     if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )

       return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);

     size  =  impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);

   }

   // Check for integer load

   if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {

     int offset = ra_->reg2offset(src_first);

     // Further check for aligned-adjacent pair, so we can use a double load

     if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )

       return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);

     size  =  impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);

   }

   // Check for float reg-reg copy

   if( src_first_rc == rc_float && dst_first_rc == rc_float ) {

     // Further check for aligned-adjacent pair, so we can use a double move

     if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )

       return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);

     size  =  impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);

   }

   // Check for float store

   if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {

     int offset = ra_->reg2offset(dst_first);

     // Further check for aligned-adjacent pair, so we can use a double store

     if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )

       return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);

     size  =  impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);

   }

   // Check for float load

   if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {

     int offset = ra_->reg2offset(src_first);

     // Further check for aligned-adjacent pair, so we can use a double load

     if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )

       return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);

     size  =  impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);

   }

   // --------------------------------------------------------------------

   // Check for hi bits still needing moving.  Only happens for misaligned

   // arguments to native calls.

   if( src_second == dst_second )

     return size;               // Self copy; no move

   assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );

 #ifndef _LP64

   // In the LP64 build, all registers can be moved as aligned/adjacent

   // pairs, so there's never any need to move the high bits separately.

   // The 32-bit builds have to deal with the 32-bit ABI which can force

   // all sorts of silly alignment problems.

   // Check for integer reg-reg copy.  Hi bits are stuck up in the top

   // 32-bits of a 64-bit register, but are needed in low bits of another

   // register (else it's a hi-bits-to-hi-bits copy which should have

   // happened already as part of a 64-bit move)

   if( src_second_rc == rc_int && dst_second_rc == rc_int ) {

     assert( (src_second&1)==1, "its the evil O0/O1 native return case" );

     assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );

     // Shift src_second down to dst_second's low bits.

     if( cbuf ) {

       emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );

 #ifndef PRODUCT

     } else if( !do_size ) {

       if( size != 0 ) st->print("\n\t");

       st->print("SRLX   R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));

 #endif

     }

     return size+4;

   }

   // Check for high word integer store.  Must down-shift the hi bits

   // into a temp register, then fall into the case of storing int bits.

   if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {

     // Shift src_second down to dst_second's low bits.

     if( cbuf ) {

       emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );

 #ifndef PRODUCT

     } else if( !do_size ) {

       if( size != 0 ) st->print("\n\t");

       st->print("SRLX   R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));

 #endif

     }

     size+=4;

     src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!

   }

   // Check for high word integer load

   if( dst_second_rc == rc_int && src_second_rc == rc_stack )

     return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);

   // Check for high word integer store

   if( src_second_rc == rc_int && dst_second_rc == rc_stack )

     return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);

   // Check for high word float store

   if( src_second_rc == rc_float && dst_second_rc == rc_stack )

     return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);

 #endif // !_LP64

   Unimplemented();

 }

 #ifndef PRODUCT

 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {

   implementation( NULL, ra_, false, st );

 }

 #endif

 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {

   implementation( &cbuf, ra_, false, NULL );

 }

 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {

   return implementation( NULL, ra_, true, NULL );

 }

 //=============================================================================

 #ifndef PRODUCT

 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {

   st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);

 }

 #endif

 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {

   MacroAssembler _masm(&cbuf);

   for(int i = 0; i < _count; i += 1) {

     __ nop();

   }

 }

 uint MachNopNode::size(PhaseRegAlloc *ra_) const {

   return 4 * _count;

 }

 //=============================================================================

 #ifndef PRODUCT

 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {

   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());

   int reg = ra_->get_reg_first(this);

   st->print("LEA    [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);

 }

 #endif

 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {

   MacroAssembler _masm(&cbuf);

   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;

   int reg = ra_->get_encode(this);

   if (Assembler::is_simm13(offset)) {

      __ add(SP, offset, reg_to_register_object(reg));

   } else {

      __ set(offset, O7);

      __ add(SP, O7, reg_to_register_object(reg));

   }

 }

 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {

   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)

   assert(ra_ == ra_->C->regalloc(), "sanity");

   return ra_->C->scratch_emit_size(this);

 }

 //=============================================================================

 #ifndef PRODUCT

 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {

   st->print_cr("\nUEP:");

 #ifdef    _LP64

   if (UseCompressedClassPointers) {

     assert(Universe::heap() != NULL, "java heap should be initialized");

     st->print_cr("\tLDUW   [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");

     if (Universe::narrow_klass_base() != 0) {

       st->print_cr("\tSET    Universe::narrow_klass_base,R_G6_heap_base");

       if (Universe::narrow_klass_shift() != 0) {

         st->print_cr("\tSLL    R_G5,Universe::narrow_klass_shift,R_G5");

       }

       st->print_cr("\tADD    R_G5,R_G6_heap_base,R_G5");

       st->print_cr("\tSET    Universe::narrow_ptrs_base,R_G6_heap_base");

     } else {

       st->print_cr("\tSLL    R_G5,Universe::narrow_klass_shift,R_G5");

     }

   } else {

     st->print_cr("\tLDX    [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");

   }

   st->print_cr("\tCMP    R_G5,R_G3" );

   st->print   ("\tTne    xcc,R_G0+ST_RESERVED_FOR_USER_0+2");

 #else  // _LP64

   st->print_cr("\tLDUW   [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");

   st->print_cr("\tCMP    R_G5,R_G3" );

   st->print   ("\tTne    icc,R_G0+ST_RESERVED_FOR_USER_0+2");

 #endif // _LP64

 }

 #endif

 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {

   MacroAssembler _masm(&cbuf);

   Register G5_ic_reg  = reg_to_register_object(Matcher::inline_cache_reg_encode());

   Register temp_reg   = G3;

   assert( G5_ic_reg != temp_reg, "conflicting registers" );

   // Load klass from receiver

   __ load_klass(O0, temp_reg);

   // Compare against expected klass

   __ cmp(temp_reg, G5_ic_reg);

   // Branch to miss code, checks xcc or icc depending

   __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);

 }

 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {

   return MachNode::size(ra_);

 }

 //=============================================================================

 uint size_exception_handler() {

   if (TraceJumps) {

     return (400); // just a guess

   }

   return ( NativeJump::instruction_size ); // sethi;jmp;nop

 }

 uint size_deopt_handler() {

   if (TraceJumps) {

     return (400); // just a guess

   }

   return ( 4+  NativeJump::instruction_size ); // save;sethi;jmp;restore

 }

 // Emit exception handler code.

 int emit_exception_handler(CodeBuffer& cbuf) {

   Register temp_reg = G3;

   AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());

   MacroAssembler _masm(&cbuf);

   address base =

   __ start_a_stub(size_exception_handler());

   if (base == NULL)  return 0;  // CodeBuffer::expand failed

   int offset = __ offset();

   __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp

   __ delayed()->nop();

   assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");

   __ end_a_stub();

   return offset;

 }

 int emit_deopt_handler(CodeBuffer& cbuf) {

   // Can't use any of the current frame's registers as we may have deopted

   // at a poll and everything (including G3) can be live.

   Register temp_reg = L0;

   AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());

   MacroAssembler _masm(&cbuf);

   address base =

   __ start_a_stub(size_deopt_handler());

   if (base == NULL)  return 0;  // CodeBuffer::expand failed

   int offset = __ offset();

   __ save_frame(0);

   __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp

   __ delayed()->restore();

   assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");

   __ end_a_stub();

   return offset;

 }

 // Given a register encoding, produce a Integer Register object

 static Register reg_to_register_object(int register_encoding) {

   assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");

   return as_Register(register_encoding);

 }

 // Given a register encoding, produce a single-precision Float Register object

 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {

   assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");

   return as_SingleFloatRegister(register_encoding);

 }

 // Given a register encoding, produce a double-precision Float Register object

 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {

   assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");

   assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");

   return as_DoubleFloatRegister(register_encoding);

 }

 const bool Matcher::match_rule_supported(int opcode) {

   if (!has_match_rule(opcode))

     return false;

   switch (opcode) {

   case Op_CountLeadingZerosI:

   case Op_CountLeadingZerosL:

   case Op_CountTrailingZerosI:

   case Op_CountTrailingZerosL:

   case Op_PopCountI:

   case Op_PopCountL:

     if (!UsePopCountInstruction)

       return false;

   case Op_CompareAndSwapL:

 #ifdef _LP64

   case Op_CompareAndSwapP:

 #endif

     if (!VM_Version::supports_cx8())

       return false;

     break;

   }

   return true;  // Per default match rules are supported.

 }

 int Matcher::regnum_to_fpu_offset(int regnum) {

   return regnum - 32; // The FP registers are in the second chunk

 }

 #ifdef ASSERT

 address last_rethrow = NULL;  // debugging aid for Rethrow encoding

 #endif

 // Vector width in bytes

 const int Matcher::vector_width_in_bytes(BasicType bt) {

   assert(MaxVectorSize == 8, "");

   return 8;

 }

 // Vector ideal reg

 const int Matcher::vector_ideal_reg(int size) {

   assert(MaxVectorSize == 8, "");

   return Op_RegD;

 }

 const int Matcher::vector_shift_count_ideal_reg(int size) {

   fatal("vector shift is not supported");

   return Node::NotAMachineReg;

 }

 // Limits on vector size (number of elements) loaded into vector.

 const int Matcher::max_vector_size(const BasicType bt) {

   assert(is_java_primitive(bt), "only primitive type vectors");

   return vector_width_in_bytes(bt)/type2aelembytes(bt);

 }

 const int Matcher::min_vector_size(const BasicType bt) {

   return max_vector_size(bt); // Same as max.

 }

 // SPARC doesn't support misaligned vectors store/load.

 const bool Matcher::misaligned_vectors_ok() {

   return false;

 }

 // USII supports fxtof through the whole range of number, USIII doesn't

 const bool Matcher::convL2FSupported(void) {

   return VM_Version::has_fast_fxtof();

 }

 // Is this branch offset short enough that a short branch can be used?

 //

 // NOTE: If the platform does not provide any short branch variants, then

 //       this method should return false for offset 0.

 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {

   // The passed offset is relative to address of the branch.

   // Don't need to adjust the offset.

   return UseCBCond && Assembler::is_simm12(offset);

 }

 const bool Matcher::isSimpleConstant64(jlong value) {

   // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.

   // Depends on optimizations in MacroAssembler::setx.

   int hi = (int)(value >> 32);

   int lo = (int)(value & ~0);

   return (hi == 0) || (hi == -1) || (lo == 0);

 }

 // No scaling for the parameter the ClearArray node.

 const bool Matcher::init_array_count_is_in_bytes = true;

 // Threshold size for cleararray.

 const int Matcher::init_array_short_size = 8 * BytesPerLong;

 // No additional cost for CMOVL.

 const int Matcher::long_cmove_cost() { return 0; }

 // CMOVF/CMOVD are expensive on T4 and on SPARC64.

 const int Matcher::float_cmove_cost() {

   return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;

 }

 // Does the CPU require late expand (see block.cpp for description of late expand)?

 const bool Matcher::require_postalloc_expand = false;

 // Should the Matcher clone shifts on addressing modes, expecting them to

 // be subsumed into complex addressing expressions or compute them into

 // registers?  True for Intel but false for most RISCs

 const bool Matcher::clone_shift_expressions = false;

 // Do we need to mask the count passed to shift instructions or does

 // the cpu only look at the lower 5/6 bits anyway?

 const bool Matcher::need_masked_shift_count = false;

 bool Matcher::narrow_oop_use_complex_address() {

   NOT_LP64(ShouldNotCallThis());

   assert(UseCompressedOops, "only for compressed oops code");

   return false;

 }

 bool Matcher::narrow_klass_use_complex_address() {

   NOT_LP64(ShouldNotCallThis());

   assert(UseCompressedClassPointers, "only for compressed klass code");

   return false;

 }

 // Is it better to copy float constants, or load them directly from memory?

 // Intel can load a float constant from a direct address, requiring no

 // extra registers.  Most RISCs will have to materialize an address into a

 // register first, so they would do better to copy the constant from stack.

 const bool Matcher::rematerialize_float_constants = false;

 // If CPU can load and store mis-aligned doubles directly then no fixup is

 // needed.  Else we split the double into 2 integer pieces and move it

 // piece-by-piece.  Only happens when passing doubles into C code as the

 // Java calling convention forces doubles to be aligned.

 #ifdef _LP64

 const bool Matcher::misaligned_doubles_ok = true;

 #else

 const bool Matcher::misaligned_doubles_ok = false;

 #endif

 // No-op on SPARC.

 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {

 }

 // Advertise here if the CPU requires explicit rounding operations

 // to implement the UseStrictFP mode.

 const bool Matcher::strict_fp_requires_explicit_rounding = false;

 // Are floats conerted to double when stored to stack during deoptimization?

 // Sparc does not handle callee-save floats.

 bool Matcher::float_in_double() { return false; }

 // Do ints take an entire long register or just half?

 // Note that we if-def off of _LP64.

 // The relevant question is how the int is callee-saved.  In _LP64

 // the whole long is written but de-opt'ing will have to extract

 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.

 #ifdef _LP64

 const bool Matcher::int_in_long = true;

 #else

 const bool Matcher::int_in_long = false;

 #endif

 // Return whether or not this register is ever used as an argument.  This

 // function is used on startup to build the trampoline stubs in generateOptoStub.

 // Registers not mentioned will be killed by the VM call in the trampoline, and

 // arguments in those registers not be available to the callee.

 bool Matcher::can_be_java_arg( int reg ) {

   // Standard sparc 6 args in registers

   if( reg == R_I0_num ||

       reg == R_I1_num ||

       reg == R_I2_num ||

       reg == R_I3_num ||

       reg == R_I4_num ||

       reg == R_I5_num ) return true;

 #ifdef _LP64

   // 64-bit builds can pass 64-bit pointers and longs in

   // the high I registers

   if( reg == R_I0H_num ||

       reg == R_I1H_num ||

       reg == R_I2H_num ||

       reg == R_I3H_num ||

       reg == R_I4H_num ||

       reg == R_I5H_num ) return true;

   if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {

     return true;

   }

 #else

   // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.

   // Longs cannot be passed in O regs, because O regs become I regs

   // after a 'save' and I regs get their high bits chopped off on

   // interrupt.

   if( reg == R_G1H_num || reg == R_G1_num ) return true;

   if( reg == R_G4H_num || reg == R_G4_num ) return true;

 #endif

   // A few float args in registers

   if( reg >= R_F0_num && reg <= R_F7_num ) return true;

   return false;

 }

 bool Matcher::is_spillable_arg( int reg ) {

   return can_be_java_arg(reg);

 }

 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {

   // Use hardware SDIVX instruction when it is

   // faster than a code which use multiply.

   return VM_Version::has_fast_idiv();

 }

 // Register for DIVI projection of divmodI

 RegMask Matcher::divI_proj_mask() {

   ShouldNotReachHere();

   return RegMask();

 }

 // Register for MODI projection of divmodI

 RegMask Matcher::modI_proj_mask() {

   ShouldNotReachHere();

   return RegMask();

 }

 // Register for DIVL projection of divmodL

 RegMask Matcher::divL_proj_mask() {

   ShouldNotReachHere();

   return RegMask();

 }

 // Register for MODL projection of divmodL

 RegMask Matcher::modL_proj_mask() {

   ShouldNotReachHere();

   return RegMask();

 }

 const RegMask Matcher::method_handle_invoke_SP_save_mask() {

   return L7_REGP_mask();

 }

 const RegMask Matcher::mathExactI_result_proj_mask() {

   return G1_REGI_mask();

 }

 const RegMask Matcher::mathExactL_result_proj_mask() {

   return G1_REGL_mask();

 }

 const RegMask Matcher::mathExactI_flags_proj_mask() {

   return INT_FLAGS_mask();

 }

 %}

 // The intptr_t operand types, defined by textual substitution.

 // (Cf. opto/type.hpp.  This lets us avoid many, many other ifdefs.)

 #ifdef _LP64

 #define immX      immL

 #define immX13    immL13

 #define immX13m7  immL13m7

 #define iRegX     iRegL

 #define g1RegX    g1RegL

 #else

 #define immX      immI

 #define immX13    immI13

 #define immX13m7  immI13m7

 #define iRegX     iRegI

 #define g1RegX    g1RegI

 #endif

 //----------ENCODING BLOCK-----------------------------------------------------

 // This block specifies the encoding classes used by the compiler to output

 // byte streams.  Encoding classes are parameterized macros used by

 // Machine Instruction Nodes in order to generate the bit encoding of the

 // instruction.  Operands specify their base encoding interface with the

 // interface keyword.  There are currently supported four interfaces,

 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER.  REG_INTER causes an

 // operand to generate a function which returns its register number when

 // queried.   CONST_INTER causes an operand to generate a function which

 // returns the value of the constant when queried.  MEMORY_INTER causes an

 // operand to generate four functions which return the Base Register, the

 // Index Register, the Scale Value, and the Offset Value of the operand when

 // queried.  COND_INTER causes an operand to generate six functions which

 // return the encoding code (ie - encoding bits for the instruction)

 // associated with each basic boolean condition for a conditional instruction.

 //

 // Instructions specify two basic values for encoding.  Again, a function

 // is available to check if the constant displacement is an oop. They use the

 // ins_encode keyword to specify their encoding classes (which must be

 // a sequence of enc_class names, and their parameters, specified in

 // the encoding block), and they use the

 // opcode keyword to specify, in order, their primary, secondary, and

 // tertiary opcode.  Only the opcode sections which a particular instruction

 // needs for encoding need to be specified.

 encode %{

   enc_class enc_untested %{

 #ifdef ASSERT

     MacroAssembler _masm(&cbuf);

     __ untested("encoding");

 #endif

   %}

   enc_class form3_mem_reg( memory mem, iRegI dst ) %{

     emit_form3_mem_reg(cbuf, this, $primary, $tertiary,

                        $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);

   %}

   enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{

     emit_form3_mem_reg(cbuf, this, $primary, -1,

                        $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);

   %}

   enc_class form3_mem_prefetch_read( memory mem ) %{

     emit_form3_mem_reg(cbuf, this, $primary, -1,

                        $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);

   %}

   enc_class form3_mem_prefetch_write( memory mem ) %{

     emit_form3_mem_reg(cbuf, this, $primary, -1,

                        $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);

   %}

   enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{

     assert(Assembler::is_simm13($mem$$disp  ), "need disp and disp+4");

     assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");

     guarantee($mem$$index == R_G0_enc, "double index?");

     emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );

     emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp,   R_G0_enc, $reg$$reg );

     emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );

     emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );

   %}

   enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{

     assert(Assembler::is_simm13($mem$$disp  ), "need disp and disp+4");

     assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");

     guarantee($mem$$index == R_G0_enc, "double index?");

     // Load long with 2 instructions

     emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp,   R_G0_enc, $reg$$reg+0 );

     emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );

   %}

   //%%% form3_mem_plus_4_reg is a hack--get rid of it

   enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{

     guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");

     emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);

   %}

   enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{

     // Encode a reg-reg copy.  If it is useless, then empty encoding.

     if( $rs2$$reg != $rd$$reg )

       emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );

   %}

   // Target lo half of long

   enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{

     // Encode a reg-reg copy.  If it is useless, then empty encoding.

     if( $rs2$$reg != LONG_LO_REG($rd$$reg) )

       emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );

   %}

   // Source lo half of long

   enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{

     // Encode a reg-reg copy.  If it is useless, then empty encoding.

     if( LONG_LO_REG($rs2$$reg) != $rd$$reg )

       emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );

   %}

   // Target hi half of long

   enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{

     emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );

   %}

   // Source lo half of long, and leave it sign extended.

   enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{

     // Sign extend low half

     emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );

   %}

   // Source hi half of long, and leave it sign extended.

   enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{

     // Shift high half to low half

     emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );

   %}

   // Source hi half of long

   enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{

     // Encode a reg-reg copy.  If it is useless, then empty encoding.

     if( LONG_HI_REG($rs2$$reg) != $rd$$reg )

       emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );

   %}

   enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{

     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );

   %}

   enc_class enc_to_bool( iRegI src, iRegI dst ) %{

     emit3       ( cbuf, Assembler::arith_op,         0, Assembler::subcc_op3, 0, 0, $src$$reg );

     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );

   %}

   enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{

     emit3       ( cbuf, Assembler::arith_op,         0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );

     // clear if nothing else is happening

     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0,  0 );

     // blt,a,pn done

     emit2_19    ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );

     // mov dst,-1 in delay slot

     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );

   %}

   enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{

     emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );

   %}

   enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{

     emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );

   %}

   enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{

     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );

   %}

   enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{

     emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );

   %}

   enc_class move_return_pc_to_o1() %{

     emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );

   %}

 #ifdef _LP64

   /* %%% merge with enc_to_bool */

   enc_class enc_convP2B( iRegI dst, iRegP src ) %{

     MacroAssembler _masm(&cbuf);

     Register   src_reg = reg_to_register_object($src$$reg);

     Register   dst_reg = reg_to_register_object($dst$$reg);

     __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);

   %}

 #endif

   enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{

     // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))

     MacroAssembler _masm(&cbuf);

     Register   p_reg = reg_to_register_object($p$$reg);

     Register   q_reg = reg_to_register_object($q$$reg);

     Register   y_reg = reg_to_register_object($y$$reg);

     Register tmp_reg = reg_to_register_object($tmp$$reg);

     __ subcc( p_reg, q_reg,   p_reg );

     __ add  ( p_reg, y_reg, tmp_reg );

     __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );

   %}

   enc_class form_d2i_helper(regD src, regF dst) %{

     // fcmp %fcc0,$src,$src

     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );

     // branch %fcc0 not-nan, predict taken

     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );

     // fdtoi $src,$dst

     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fdtoi_opf, $src$$reg );

     // fitos $dst,$dst (if nan)

     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fitos_opf, $dst$$reg );

     // clear $dst (if nan)

     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );

     // carry on here...

   %}

   enc_class form_d2l_helper(regD src, regD dst) %{

     // fcmp %fcc0,$src,$src  check for NAN

     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );

     // branch %fcc0 not-nan, predict taken

     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );

     // fdtox $src,$dst   convert in delay slot

     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fdtox_opf, $src$$reg );

     // fxtod $dst,$dst  (if nan)

     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fxtod_opf, $dst$$reg );

     // clear $dst (if nan)

     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );

     // carry on here...

   %}

   enc_class form_f2i_helper(regF src, regF dst) %{

     // fcmps %fcc0,$src,$src

     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );

     // branch %fcc0 not-nan, predict taken

     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );

     // fstoi $src,$dst

     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fstoi_opf, $src$$reg );

     // fitos $dst,$dst (if nan)

     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fitos_opf, $dst$$reg );

     // clear $dst (if nan)

     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );

     // carry on here...

   %}

   enc_class form_f2l_helper(regF src, regD dst) %{

     // fcmps %fcc0,$src,$src

     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );

     // branch %fcc0 not-nan, predict taken

     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );

     // fstox $src,$dst

     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fstox_opf, $src$$reg );

     // fxtod $dst,$dst (if nan)

     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fxtod_opf, $dst$$reg );

     // clear $dst (if nan)

     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );

     // carry on here...

   %}

   enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}

   enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}

   enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}

   enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}

   enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}

   enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}

   enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}

   enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{

     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );

   %}

   enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{

     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );

   %}

   enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{

     emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );

   %}

   enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{

     emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );

   %}

   enc_class form3_convI2F(regF rs2, regF rd) %{

     emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);

   %}

   // Encloding class for traceable jumps

   enc_class form_jmpl(g3RegP dest) %{

     emit_jmpl(cbuf, $dest$$reg);

   %}

   enc_class form_jmpl_set_exception_pc(g1RegP dest) %{

     emit_jmpl_set_exception_pc(cbuf, $dest$$reg);

   %}

   enc_class form2_nop() %{

     emit_nop(cbuf);

   %}

   enc_class form2_illtrap() %{

     emit_illtrap(cbuf);

   %}

   // Compare longs and convert into -1, 0, 1.

   enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{

     // CMP $src1,$src2

     emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );

     // blt,a,pn done

     emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less   , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );

     // mov dst,-1 in delay slot

     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );

     // bgt,a,pn done

     emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );

     // mov dst,1 in delay slot

     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0,  1 );

     // CLR    $dst

     emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );

   %}

   enc_class enc_PartialSubtypeCheck() %{

     MacroAssembler _masm(&cbuf);

     __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);

     __ delayed()->nop();

   %}

   enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{

     MacroAssembler _masm(&cbuf);

     Label* L = $labl$$label;

     Assembler::Predict predict_taken =

       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;

     __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);

     __ delayed()->nop();

   %}

   enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{

     MacroAssembler _masm(&cbuf);

     Label* L = $labl$$label;

     Assembler::Predict predict_taken =

       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;

     __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);

     __ delayed()->nop();

   %}

   enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{

     int op = (Assembler::arith_op << 30) |

              ($dst$$reg << 25) |

              (Assembler::movcc_op3 << 19) |

              (1 << 18) |                    // cc2 bit for 'icc'

              ($cmp$$cmpcode << 14) |

              (0 << 13) |                    // select register move

              ($pcc$$constant << 11) |       // cc1, cc0 bits for 'icc' or 'xcc'

              ($src$$reg << 0);

     cbuf.insts()->emit_int32(op);

   %}

   enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{

     int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits

     int op = (Assembler::arith_op << 30) |

              ($dst$$reg << 25) |

              (Assembler::movcc_op3 << 19) |

              (1 << 18) |                    // cc2 bit for 'icc'

              ($cmp$$cmpcode << 14) |

              (1 << 13) |                    // select immediate move

              ($pcc$$constant << 11) |       // cc1, cc0 bits for 'icc'

              (simm11 << 0);

     cbuf.insts()->emit_int32(op);

   %}

   enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{

     int op = (Assembler::arith_op << 30) |

              ($dst$$reg << 25) |

              (Assembler::movcc_op3 << 19) |

              (0 << 18) |                    // cc2 bit for 'fccX'

              ($cmp$$cmpcode << 14) |

              (0 << 13) |                    // select register move

              ($fcc$$reg << 11) |            // cc1, cc0 bits for fcc0-fcc3

              ($src$$reg << 0);

     cbuf.insts()->emit_int32(op);

   %}

   enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{

     int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits

     int op = (Assembler::arith_op << 30) |

              ($dst$$reg << 25) |

              (Assembler::movcc_op3 << 19) |

              (0 << 18) |                    // cc2 bit for 'fccX'

              ($cmp$$cmpcode << 14) |

              (1 << 13) |                    // select immediate move

              ($fcc$$reg << 11) |            // cc1, cc0 bits for fcc0-fcc3

              (simm11 << 0);

     cbuf.insts()->emit_int32(op);

   %}

   enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{

     int op = (Assembler::arith_op << 30) |

              ($dst$$reg << 25) |

              (Assembler::fpop2_op3 << 19) |

              (0 << 18) |

              ($cmp$$cmpcode << 14) |

              (1 << 13) |                    // select register move

              ($pcc$$constant << 11) |       // cc1-cc0 bits for 'icc' or 'xcc'

              ($primary << 5) |              // select single, double or quad

              ($src$$reg << 0);

     cbuf.insts()->emit_int32(op);

   %}

   enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{

     int op = (Assembler::arith_op << 30) |

              ($dst$$reg << 25) |

              (Assembler::fpop2_op3 << 19) |

              (0 << 18) |

              ($cmp$$cmpcode << 14) |

              ($fcc$$reg << 11) |            // cc2-cc0 bits for 'fccX'

              ($primary << 5) |              // select single, double or quad

              ($src$$reg << 0);

     cbuf.insts()->emit_int32(op);

   %}

   // Used by the MIN/MAX encodings.  Same as a CMOV, but

   // the condition comes from opcode-field instead of an argument.

   enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{

     int op = (Assembler::arith_op << 30) |

              ($dst$$reg << 25) |

              (Assembler::movcc_op3 << 19) |

              (1 << 18) |                    // cc2 bit for 'icc'

              ($primary << 14) |

              (0 << 13) |                    // select register move

              (0 << 11) |                    // cc1, cc0 bits for 'icc'

              ($src$$reg << 0);

     cbuf.insts()->emit_int32(op);

   %}

   enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{

     int op = (Assembler::arith_op << 30) |

              ($dst$$reg << 25) |

              (Assembler::movcc_op3 << 19) |

              (6 << 16) |                    // cc2 bit for 'xcc'

              ($primary << 14) |

              (0 << 13) |                    // select register move

              (0 << 11) |                    // cc1, cc0 bits for 'icc'

              ($src$$reg << 0);

     cbuf.insts()->emit_int32(op);

   %}

   enc_class Set13( immI13 src, iRegI rd ) %{

     emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );

   %}

   enc_class SetHi22( immI src, iRegI rd ) %{

     emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );

   %}

   enc_class Set32( immI src, iRegI rd ) %{

     MacroAssembler _masm(&cbuf);

     __ set($src$$constant, reg_to_register_object($rd$$reg));

   %}

   enc_class call_epilog %{

     if( VerifyStackAtCalls ) {

       MacroAssembler _masm(&cbuf);

       int framesize = ra_->C->frame_slots() << LogBytesPerInt;

       Register temp_reg = G3;

       __ add(SP, framesize, temp_reg);

       __ cmp(temp_reg, FP);

       __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);

     }

   %}

   // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value

   // to G1 so the register allocator will not have to deal with the misaligned register

   // pair.

   enc_class adjust_long_from_native_call %{

 #ifndef _LP64

     if (returns_long()) {

       //    sllx  O0,32,O0

       emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );

       //    srl   O1,0,O1

       emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );

       //    or    O0,O1,G1

       emit3       ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );

     }

 #endif

   %}

   enc_class Java_To_Runtime (method meth) %{    // CALL Java_To_Runtime

     // CALL directly to the runtime

     // The user of this is responsible for ensuring that R_L7 is empty (killed).

     emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,

                     /*preserve_g2=*/true);

   %}

   enc_class preserve_SP %{

     MacroAssembler _masm(&cbuf);

     __ mov(SP, L7_mh_SP_save);

   %}

   enc_class restore_SP %{

     MacroAssembler _masm(&cbuf);

     __ mov(L7_mh_SP_save, SP);

   %}

   enc_class Java_Static_Call (method meth) %{    // JAVA STATIC CALL

     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to determine

     // who we intended to call.

     if (!_method) {

       emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);

     } else if (_optimized_virtual) {

       emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);

     } else {

       emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);

     }

     if (_method) {  // Emit stub for static call.

       CompiledStaticCall::emit_to_interp_stub(cbuf);

     }

   %}

   enc_class Java_Dynamic_Call (method meth) %{    // JAVA DYNAMIC CALL

     MacroAssembler _masm(&cbuf);

     __ set_inst_mark();

     int vtable_index = this->_vtable_index;

     // MachCallDynamicJavaNode::ret_addr_offset uses this same test

     if (vtable_index < 0) {

       // must be invalid_vtable_index, not nonvirtual_vtable_index

       assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");

       Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());

       assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");

       assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");

       __ ic_call((address)$meth$$method);

     } else {

       assert(!UseInlineCaches, "expect vtable calls only if not using ICs");

       // Just go thru the vtable

       // get receiver klass (receiver already checked for non-null)

       // If we end up going thru a c2i adapter interpreter expects method in G5

       int off = __ offset();

       __ load_klass(O0, G3_scratch);

       int klass_load_size;

       if (UseCompressedClassPointers) {

         assert(Universe::heap() != NULL, "java heap should be initialized");

         klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;

       } else {

         klass_load_size = 1*BytesPerInstWord;

       }

       int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();

       int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();

       if (Assembler::is_simm13(v_off)) {

         __ ld_ptr(G3, v_off, G5_method);

       } else {

         // Generate 2 instructions

         __ Assembler::sethi(v_off & ~0x3ff, G5_method);

         __ or3(G5_method, v_off & 0x3ff, G5_method);

         // ld_ptr, set_hi, set

         assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,

                "Unexpected instruction size(s)");

         __ ld_ptr(G3, G5_method, G5_method);

       }

       // NOTE: for vtable dispatches, the vtable entry will never be null.

       // However it may very well end up in handle_wrong_method if the

       // method is abstract for the particular class.

       __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);

       // jump to target (either compiled code or c2iadapter)

       __ jmpl(G3_scratch, G0, O7);

       __ delayed()->nop();

     }

   %}

   enc_class Java_Compiled_Call (method meth) %{    // JAVA COMPILED CALL

     MacroAssembler _masm(&cbuf);

     Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());

     Register temp_reg = G3;   // caller must kill G3!  We cannot reuse G5_ic_reg here because

                               // we might be calling a C2I adapter which needs it.

     assert(temp_reg != G5_ic_reg, "conflicting registers");

     // Load nmethod

     __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);

     // CALL to compiled java, indirect the contents of G3

     __ set_inst_mark();

     __ callr(temp_reg, G0);

     __ delayed()->nop();

   %}

 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{

     MacroAssembler _masm(&cbuf);

     Register Rdividend = reg_to_register_object($src1$$reg);

     Register Rdivisor = reg_to_register_object($src2$$reg);

     Register Rresult = reg_to_register_object($dst$$reg);

     __ sra(Rdivisor, 0, Rdivisor);

     __ sra(Rdividend, 0, Rdividend);

     __ sdivx(Rdividend, Rdivisor, Rresult);

 %}