Tue, 28 Oct 2008 09:31:30 -0700
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
Reviewed-by: kvn, rasbold
1 //
2 // Copyright 1998-2008 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
25 // SPARC Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning 'dont go here'.
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg());
197 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()->next());
198 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg());
199 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()->next());
200 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg());
201 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()->next());
202 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg());
203 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()->next());
204 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg());
205 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()->next());
206 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg());
207 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()->next());
208 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg());
209 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()->next());
210 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg());
211 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()->next());
212 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg());
213 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()->next());
214 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg());
215 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()->next());
216 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg());
217 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()->next());
218 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg());
219 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()->next());
220 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg());
221 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()->next());
222 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg());
223 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()->next());
224 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg());
225 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()->next());
226 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg());
227 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()->next());
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class o2_regL(R_O2H,R_O2);
399 reg_class o7_regL(R_O7H,R_O7);
401 // ----------------------------
402 // Special Class for Condition Code Flags Register
403 reg_class int_flags(CCR);
404 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
405 reg_class float_flag0(FCC0);
408 // ----------------------------
409 // Float Point Register Classes
410 // ----------------------------
411 // Skip F30/F31, they are reserved for mem-mem copies
412 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414 // Paired floating point registers--they show up in the same order as the floats,
415 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
416 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
417 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
418 /* Use extra V9 double registers; this AD file does not support V8 */
419 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
420 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
421 );
423 // Paired floating point registers--they show up in the same order as the floats,
424 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
425 // This class is usable for mis-aligned loads as happen in I2C adapters.
426 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
427 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 );
428 %}
430 //----------DEFINITION BLOCK---------------------------------------------------
431 // Define name --> value mappings to inform the ADLC of an integer valued name
432 // Current support includes integer values in the range [0, 0x7FFFFFFF]
433 // Format:
434 // int_def <name> ( <int_value>, <expression>);
435 // Generated Code in ad_<arch>.hpp
436 // #define <name> (<expression>)
437 // // value == <int_value>
438 // Generated code in ad_<arch>.cpp adlc_verification()
439 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
440 //
441 definitions %{
442 // The default cost (of an ALU instruction).
443 int_def DEFAULT_COST ( 100, 100);
444 int_def HUGE_COST (1000000, 1000000);
446 // Memory refs are twice as expensive as run-of-the-mill.
447 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449 // Branches are even more expensive.
450 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
451 int_def CALL_COST ( 300, DEFAULT_COST * 3);
452 %}
455 //----------SOURCE BLOCK-------------------------------------------------------
456 // This is a block of C++ code which provides values, functions, and
457 // definitions necessary in the rest of the architecture description
458 source_hpp %{
459 // Must be visible to the DFA in dfa_sparc.cpp
460 extern bool can_branch_register( Node *bol, Node *cmp );
462 // Macros to extract hi & lo halves from a long pair.
463 // G0 is not part of any long pair, so assert on that.
464 // Prevents accidently using G1 instead of G0.
465 #define LONG_HI_REG(x) (x)
466 #define LONG_LO_REG(x) (x)
468 %}
470 source %{
471 #define __ _masm.
473 // tertiary op of a LoadP or StoreP encoding
474 #define REGP_OP true
476 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
477 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
478 static Register reg_to_register_object(int register_encoding);
480 // Used by the DFA in dfa_sparc.cpp.
481 // Check for being able to use a V9 branch-on-register. Requires a
482 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
483 // extended. Doesn't work following an integer ADD, for example, because of
484 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
485 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
486 // replace them with zero, which could become sign-extension in a different OS
487 // release. There's no obvious reason why an interrupt will ever fill these
488 // bits with non-zero junk (the registers are reloaded with standard LD
489 // instructions which either zero-fill or sign-fill).
490 bool can_branch_register( Node *bol, Node *cmp ) {
491 if( !BranchOnRegister ) return false;
492 #ifdef _LP64
493 if( cmp->Opcode() == Op_CmpP )
494 return true; // No problems with pointer compares
495 #endif
496 if( cmp->Opcode() == Op_CmpL )
497 return true; // No problems with long compares
499 if( !SparcV9RegsHiBitsZero ) return false;
500 if( bol->as_Bool()->_test._test != BoolTest::ne &&
501 bol->as_Bool()->_test._test != BoolTest::eq )
502 return false;
504 // Check for comparing against a 'safe' value. Any operation which
505 // clears out the high word is safe. Thus, loads and certain shifts
506 // are safe, as are non-negative constants. Any operation which
507 // preserves zero bits in the high word is safe as long as each of its
508 // inputs are safe. Thus, phis and bitwise booleans are safe if their
509 // inputs are safe. At present, the only important case to recognize
510 // seems to be loads. Constants should fold away, and shifts &
511 // logicals can use the 'cc' forms.
512 Node *x = cmp->in(1);
513 if( x->is_Load() ) return true;
514 if( x->is_Phi() ) {
515 for( uint i = 1; i < x->req(); i++ )
516 if( !x->in(i)->is_Load() )
517 return false;
518 return true;
519 }
520 return false;
521 }
523 // ****************************************************************************
525 // REQUIRED FUNCTIONALITY
527 // !!!!! Special hack to get all type of calls to specify the byte offset
528 // from the start of the call to the point where the return address
529 // will point.
530 // The "return address" is the address of the call instruction, plus 8.
532 int MachCallStaticJavaNode::ret_addr_offset() {
533 return NativeCall::instruction_size; // call; delay slot
534 }
536 int MachCallDynamicJavaNode::ret_addr_offset() {
537 int vtable_index = this->_vtable_index;
538 if (vtable_index < 0) {
539 // must be invalid_vtable_index, not nonvirtual_vtable_index
540 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
541 return (NativeMovConstReg::instruction_size +
542 NativeCall::instruction_size); // sethi; setlo; call; delay slot
543 } else {
544 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
545 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
546 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
547 int klass_load_size;
548 if (UseCompressedOops) {
549 klass_load_size = 3*BytesPerInstWord; // see MacroAssembler::load_klass()
550 } else {
551 klass_load_size = 1*BytesPerInstWord;
552 }
553 if( Assembler::is_simm13(v_off) ) {
554 return klass_load_size +
555 (2*BytesPerInstWord + // ld_ptr, ld_ptr
556 NativeCall::instruction_size); // call; delay slot
557 } else {
558 return klass_load_size +
559 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
560 NativeCall::instruction_size); // call; delay slot
561 }
562 }
563 }
565 int MachCallRuntimeNode::ret_addr_offset() {
566 #ifdef _LP64
567 return NativeFarCall::instruction_size; // farcall; delay slot
568 #else
569 return NativeCall::instruction_size; // call; delay slot
570 #endif
571 }
573 // Indicate if the safepoint node needs the polling page as an input.
574 // Since Sparc does not have absolute addressing, it does.
575 bool SafePointNode::needs_polling_address_input() {
576 return true;
577 }
579 // emit an interrupt that is caught by the debugger (for debugging compiler)
580 void emit_break(CodeBuffer &cbuf) {
581 MacroAssembler _masm(&cbuf);
582 __ breakpoint_trap();
583 }
585 #ifndef PRODUCT
586 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
587 st->print("TA");
588 }
589 #endif
591 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
592 emit_break(cbuf);
593 }
595 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
596 return MachNode::size(ra_);
597 }
599 // Traceable jump
600 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
601 MacroAssembler _masm(&cbuf);
602 Register rdest = reg_to_register_object(jump_target);
603 __ JMP(rdest, 0);
604 __ delayed()->nop();
605 }
607 // Traceable jump and set exception pc
608 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
609 MacroAssembler _masm(&cbuf);
610 Register rdest = reg_to_register_object(jump_target);
611 __ JMP(rdest, 0);
612 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
613 }
615 void emit_nop(CodeBuffer &cbuf) {
616 MacroAssembler _masm(&cbuf);
617 __ nop();
618 }
620 void emit_illtrap(CodeBuffer &cbuf) {
621 MacroAssembler _masm(&cbuf);
622 __ illtrap(0);
623 }
626 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
627 assert(n->rule() != loadUB_rule, "");
629 intptr_t offset = 0;
630 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
631 const Node* addr = n->get_base_and_disp(offset, adr_type);
632 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
633 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
634 assert(addr->bottom_type()->isa_oopptr() == atype, "");
635 atype = atype->add_offset(offset);
636 assert(disp32 == offset, "wrong disp32");
637 return atype->_offset;
638 }
641 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
642 assert(n->rule() != loadUB_rule, "");
644 intptr_t offset = 0;
645 Node* addr = n->in(2);
646 assert(addr->bottom_type()->isa_oopptr() == atype, "");
647 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
648 Node* a = addr->in(2/*AddPNode::Address*/);
649 Node* o = addr->in(3/*AddPNode::Offset*/);
650 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
651 atype = a->bottom_type()->is_ptr()->add_offset(offset);
652 assert(atype->isa_oop_ptr(), "still an oop");
653 }
654 offset = atype->is_ptr()->_offset;
655 if (offset != Type::OffsetBot) offset += disp32;
656 return offset;
657 }
659 // Standard Sparc opcode form2 field breakdown
660 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
661 f0 &= (1<<19)-1; // Mask displacement to 19 bits
662 int op = (f30 << 30) |
663 (f29 << 29) |
664 (f25 << 25) |
665 (f22 << 22) |
666 (f20 << 20) |
667 (f19 << 19) |
668 (f0 << 0);
669 *((int*)(cbuf.code_end())) = op;
670 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
671 }
673 // Standard Sparc opcode form2 field breakdown
674 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
675 f0 >>= 10; // Drop 10 bits
676 f0 &= (1<<22)-1; // Mask displacement to 22 bits
677 int op = (f30 << 30) |
678 (f25 << 25) |
679 (f22 << 22) |
680 (f0 << 0);
681 *((int*)(cbuf.code_end())) = op;
682 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
683 }
685 // Standard Sparc opcode form3 field breakdown
686 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
687 int op = (f30 << 30) |
688 (f25 << 25) |
689 (f19 << 19) |
690 (f14 << 14) |
691 (f5 << 5) |
692 (f0 << 0);
693 *((int*)(cbuf.code_end())) = op;
694 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
695 }
697 // Standard Sparc opcode form3 field breakdown
698 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
699 simm13 &= (1<<13)-1; // Mask to 13 bits
700 int op = (f30 << 30) |
701 (f25 << 25) |
702 (f19 << 19) |
703 (f14 << 14) |
704 (1 << 13) | // bit to indicate immediate-mode
705 (simm13<<0);
706 *((int*)(cbuf.code_end())) = op;
707 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
708 }
710 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
711 simm10 &= (1<<10)-1; // Mask to 10 bits
712 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
713 }
715 #ifdef ASSERT
716 // Helper function for VerifyOops in emit_form3_mem_reg
717 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
718 warning("VerifyOops encountered unexpected instruction:");
719 n->dump(2);
720 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
721 }
722 #endif
725 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
726 int src1_enc, int disp32, int src2_enc, int dst_enc) {
728 #ifdef ASSERT
729 // The following code implements the +VerifyOops feature.
730 // It verifies oop values which are loaded into or stored out of
731 // the current method activation. +VerifyOops complements techniques
732 // like ScavengeALot, because it eagerly inspects oops in transit,
733 // as they enter or leave the stack, as opposed to ScavengeALot,
734 // which inspects oops "at rest", in the stack or heap, at safepoints.
735 // For this reason, +VerifyOops can sometimes detect bugs very close
736 // to their point of creation. It can also serve as a cross-check
737 // on the validity of oop maps, when used toegether with ScavengeALot.
739 // It would be good to verify oops at other points, especially
740 // when an oop is used as a base pointer for a load or store.
741 // This is presently difficult, because it is hard to know when
742 // a base address is biased or not. (If we had such information,
743 // it would be easy and useful to make a two-argument version of
744 // verify_oop which unbiases the base, and performs verification.)
746 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
747 bool is_verified_oop_base = false;
748 bool is_verified_oop_load = false;
749 bool is_verified_oop_store = false;
750 int tmp_enc = -1;
751 if (VerifyOops && src1_enc != R_SP_enc) {
752 // classify the op, mainly for an assert check
753 int st_op = 0, ld_op = 0;
754 switch (primary) {
755 case Assembler::stb_op3: st_op = Op_StoreB; break;
756 case Assembler::sth_op3: st_op = Op_StoreC; break;
757 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
758 case Assembler::stw_op3: st_op = Op_StoreI; break;
759 case Assembler::std_op3: st_op = Op_StoreL; break;
760 case Assembler::stf_op3: st_op = Op_StoreF; break;
761 case Assembler::stdf_op3: st_op = Op_StoreD; break;
763 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
764 case Assembler::lduh_op3: ld_op = Op_LoadC; break;
765 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
766 case Assembler::ldx_op3: // may become LoadP or stay LoadI
767 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
768 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
769 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
770 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
771 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
772 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
773 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
775 default: ShouldNotReachHere();
776 }
777 if (tertiary == REGP_OP) {
778 if (st_op == Op_StoreI) st_op = Op_StoreP;
779 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
780 else ShouldNotReachHere();
781 if (st_op) {
782 // a store
783 // inputs are (0:control, 1:memory, 2:address, 3:value)
784 Node* n2 = n->in(3);
785 if (n2 != NULL) {
786 const Type* t = n2->bottom_type();
787 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
788 }
789 } else {
790 // a load
791 const Type* t = n->bottom_type();
792 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
793 }
794 }
796 if (ld_op) {
797 // a Load
798 // inputs are (0:control, 1:memory, 2:address)
799 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
800 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
801 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
802 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
803 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
804 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
805 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
806 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
807 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
808 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
809 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
810 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
811 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
812 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
813 !(n->rule() == loadUB_rule)) {
814 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
815 }
816 } else if (st_op) {
817 // a Store
818 // inputs are (0:control, 1:memory, 2:address, 3:value)
819 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
820 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
821 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
822 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
823 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
824 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
825 verify_oops_warning(n, n->ideal_Opcode(), st_op);
826 }
827 }
829 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
830 Node* addr = n->in(2);
831 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
832 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
833 if (atype != NULL) {
834 intptr_t offset = get_offset_from_base(n, atype, disp32);
835 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
836 if (offset != offset_2) {
837 get_offset_from_base(n, atype, disp32);
838 get_offset_from_base_2(n, atype, disp32);
839 }
840 assert(offset == offset_2, "different offsets");
841 if (offset == disp32) {
842 // we now know that src1 is a true oop pointer
843 is_verified_oop_base = true;
844 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
845 if( primary == Assembler::ldd_op3 ) {
846 is_verified_oop_base = false; // Cannot 'ldd' into O7
847 } else {
848 tmp_enc = dst_enc;
849 dst_enc = R_O7_enc; // Load into O7; preserve source oop
850 assert(src1_enc != dst_enc, "");
851 }
852 }
853 }
854 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
855 || offset == oopDesc::mark_offset_in_bytes())) {
856 // loading the mark should not be allowed either, but
857 // we don't check this since it conflicts with InlineObjectHash
858 // usage of LoadINode to get the mark. We could keep the
859 // check if we create a new LoadMarkNode
860 // but do not verify the object before its header is initialized
861 ShouldNotReachHere();
862 }
863 }
864 }
865 }
866 }
867 #endif
869 uint instr;
870 instr = (Assembler::ldst_op << 30)
871 | (dst_enc << 25)
872 | (primary << 19)
873 | (src1_enc << 14);
875 uint index = src2_enc;
876 int disp = disp32;
878 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
879 disp += STACK_BIAS;
881 // We should have a compiler bailout here rather than a guarantee.
882 // Better yet would be some mechanism to handle variable-size matches correctly.
883 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
885 if( disp == 0 ) {
886 // use reg-reg form
887 // bit 13 is already zero
888 instr |= index;
889 } else {
890 // use reg-imm form
891 instr |= 0x00002000; // set bit 13 to one
892 instr |= disp & 0x1FFF;
893 }
895 uint *code = (uint*)cbuf.code_end();
896 *code = instr;
897 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
899 #ifdef ASSERT
900 {
901 MacroAssembler _masm(&cbuf);
902 if (is_verified_oop_base) {
903 __ verify_oop(reg_to_register_object(src1_enc));
904 }
905 if (is_verified_oop_store) {
906 __ verify_oop(reg_to_register_object(dst_enc));
907 }
908 if (tmp_enc != -1) {
909 __ mov(O7, reg_to_register_object(tmp_enc));
910 }
911 if (is_verified_oop_load) {
912 __ verify_oop(reg_to_register_object(dst_enc));
913 }
914 }
915 #endif
916 }
918 void emit_form3_mem_reg_asi(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
919 int src1_enc, int disp32, int src2_enc, int dst_enc, int asi) {
921 uint instr;
922 instr = (Assembler::ldst_op << 30)
923 | (dst_enc << 25)
924 | (primary << 19)
925 | (src1_enc << 14);
927 int disp = disp32;
928 int index = src2_enc;
930 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
931 disp += STACK_BIAS;
933 // We should have a compiler bailout here rather than a guarantee.
934 // Better yet would be some mechanism to handle variable-size matches correctly.
935 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
937 if( disp != 0 ) {
938 // use reg-reg form
939 // set src2=R_O7 contains offset
940 index = R_O7_enc;
941 emit3_simm13( cbuf, Assembler::arith_op, index, Assembler::or_op3, 0, disp);
942 }
943 instr |= (asi << 5);
944 instr |= index;
945 uint *code = (uint*)cbuf.code_end();
946 *code = instr;
947 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
948 }
950 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) {
951 // The method which records debug information at every safepoint
952 // expects the call to be the first instruction in the snippet as
953 // it creates a PcDesc structure which tracks the offset of a call
954 // from the start of the codeBlob. This offset is computed as
955 // code_end() - code_begin() of the code which has been emitted
956 // so far.
957 // In this particular case we have skirted around the problem by
958 // putting the "mov" instruction in the delay slot but the problem
959 // may bite us again at some other point and a cleaner/generic
960 // solution using relocations would be needed.
961 MacroAssembler _masm(&cbuf);
962 __ set_inst_mark();
964 // We flush the current window just so that there is a valid stack copy
965 // the fact that the current window becomes active again instantly is
966 // not a problem there is nothing live in it.
968 #ifdef ASSERT
969 int startpos = __ offset();
970 #endif /* ASSERT */
972 #ifdef _LP64
973 // Calls to the runtime or native may not be reachable from compiled code,
974 // so we generate the far call sequence on 64 bit sparc.
975 // This code sequence is relocatable to any address, even on LP64.
976 if ( force_far_call ) {
977 __ relocate(rtype);
978 Address dest(O7, (address)entry_point);
979 __ jumpl_to(dest, O7);
980 }
981 else
982 #endif
983 {
984 __ call((address)entry_point, rtype);
985 }
987 if (preserve_g2) __ delayed()->mov(G2, L7);
988 else __ delayed()->nop();
990 if (preserve_g2) __ mov(L7, G2);
992 #ifdef ASSERT
993 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
994 #ifdef _LP64
995 // Trash argument dump slots.
996 __ set(0xb0b8ac0db0b8ac0d, G1);
997 __ mov(G1, G5);
998 __ stx(G1, SP, STACK_BIAS + 0x80);
999 __ stx(G1, SP, STACK_BIAS + 0x88);
1000 __ stx(G1, SP, STACK_BIAS + 0x90);
1001 __ stx(G1, SP, STACK_BIAS + 0x98);
1002 __ stx(G1, SP, STACK_BIAS + 0xA0);
1003 __ stx(G1, SP, STACK_BIAS + 0xA8);
1004 #else // _LP64
1005 // this is also a native call, so smash the first 7 stack locations,
1006 // and the various registers
1008 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1009 // while [SP+0x44..0x58] are the argument dump slots.
1010 __ set((intptr_t)0xbaadf00d, G1);
1011 __ mov(G1, G5);
1012 __ sllx(G1, 32, G1);
1013 __ or3(G1, G5, G1);
1014 __ mov(G1, G5);
1015 __ stx(G1, SP, 0x40);
1016 __ stx(G1, SP, 0x48);
1017 __ stx(G1, SP, 0x50);
1018 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1019 #endif // _LP64
1020 }
1021 #endif /*ASSERT*/
1022 }
1024 //=============================================================================
1025 // REQUIRED FUNCTIONALITY for encoding
1026 void emit_lo(CodeBuffer &cbuf, int val) { }
1027 void emit_hi(CodeBuffer &cbuf, int val) { }
1029 void emit_ptr(CodeBuffer &cbuf, intptr_t val, Register reg, bool ForceRelocatable) {
1030 MacroAssembler _masm(&cbuf);
1031 if (ForceRelocatable) {
1032 Address addr(reg, (address)val);
1033 __ sethi(addr, ForceRelocatable);
1034 __ add(addr, reg);
1035 } else {
1036 __ set(val, reg);
1037 }
1038 }
1041 //=============================================================================
1043 #ifndef PRODUCT
1044 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1045 Compile* C = ra_->C;
1047 for (int i = 0; i < OptoPrologueNops; i++) {
1048 st->print_cr("NOP"); st->print("\t");
1049 }
1051 if( VerifyThread ) {
1052 st->print_cr("Verify_Thread"); st->print("\t");
1053 }
1055 size_t framesize = C->frame_slots() << LogBytesPerInt;
1057 // Calls to C2R adapters often do not accept exceptional returns.
1058 // We require that their callers must bang for them. But be careful, because
1059 // some VM calls (such as call site linkage) can use several kilobytes of
1060 // stack. But the stack safety zone should account for that.
1061 // See bugs 4446381, 4468289, 4497237.
1062 if (C->need_stack_bang(framesize)) {
1063 st->print_cr("! stack bang"); st->print("\t");
1064 }
1066 if (Assembler::is_simm13(-framesize)) {
1067 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1068 } else {
1069 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1070 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1071 st->print ("SAVE R_SP,R_G3,R_SP");
1072 }
1074 }
1075 #endif
1077 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1078 Compile* C = ra_->C;
1079 MacroAssembler _masm(&cbuf);
1081 for (int i = 0; i < OptoPrologueNops; i++) {
1082 __ nop();
1083 }
1085 __ verify_thread();
1087 size_t framesize = C->frame_slots() << LogBytesPerInt;
1088 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1089 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1091 // Calls to C2R adapters often do not accept exceptional returns.
1092 // We require that their callers must bang for them. But be careful, because
1093 // some VM calls (such as call site linkage) can use several kilobytes of
1094 // stack. But the stack safety zone should account for that.
1095 // See bugs 4446381, 4468289, 4497237.
1096 if (C->need_stack_bang(framesize)) {
1097 __ generate_stack_overflow_check(framesize);
1098 }
1100 if (Assembler::is_simm13(-framesize)) {
1101 __ save(SP, -framesize, SP);
1102 } else {
1103 __ sethi(-framesize & ~0x3ff, G3);
1104 __ add(G3, -framesize & 0x3ff, G3);
1105 __ save(SP, G3, SP);
1106 }
1107 C->set_frame_complete( __ offset() );
1108 }
1110 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1111 return MachNode::size(ra_);
1112 }
1114 int MachPrologNode::reloc() const {
1115 return 10; // a large enough number
1116 }
1118 //=============================================================================
1119 #ifndef PRODUCT
1120 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1121 Compile* C = ra_->C;
1123 if( do_polling() && ra_->C->is_method_compilation() ) {
1124 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1125 #ifdef _LP64
1126 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1127 #else
1128 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1129 #endif
1130 }
1132 if( do_polling() )
1133 st->print("RET\n\t");
1135 st->print("RESTORE");
1136 }
1137 #endif
1139 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1140 MacroAssembler _masm(&cbuf);
1141 Compile* C = ra_->C;
1143 __ verify_thread();
1145 // If this does safepoint polling, then do it here
1146 if( do_polling() && ra_->C->is_method_compilation() ) {
1147 Address polling_page(L0, (address)os::get_polling_page());
1148 __ sethi(polling_page, false);
1149 __ relocate(relocInfo::poll_return_type);
1150 __ ld_ptr( L0, 0, G0 );
1151 }
1153 // If this is a return, then stuff the restore in the delay slot
1154 if( do_polling() ) {
1155 __ ret();
1156 __ delayed()->restore();
1157 } else {
1158 __ restore();
1159 }
1160 }
1162 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1163 return MachNode::size(ra_);
1164 }
1166 int MachEpilogNode::reloc() const {
1167 return 16; // a large enough number
1168 }
1170 const Pipeline * MachEpilogNode::pipeline() const {
1171 return MachNode::pipeline_class();
1172 }
1174 int MachEpilogNode::safepoint_offset() const {
1175 assert( do_polling(), "no return for this epilog node");
1176 return MacroAssembler::size_of_sethi(os::get_polling_page());
1177 }
1179 //=============================================================================
1181 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1182 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1183 static enum RC rc_class( OptoReg::Name reg ) {
1184 if( !OptoReg::is_valid(reg) ) return rc_bad;
1185 if (OptoReg::is_stack(reg)) return rc_stack;
1186 VMReg r = OptoReg::as_VMReg(reg);
1187 if (r->is_Register()) return rc_int;
1188 assert(r->is_FloatRegister(), "must be");
1189 return rc_float;
1190 }
1192 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1193 if( cbuf ) {
1194 // Better yet would be some mechanism to handle variable-size matches correctly
1195 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1196 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1197 } else {
1198 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1199 }
1200 }
1201 #ifndef PRODUCT
1202 else if( !do_size ) {
1203 if( size != 0 ) st->print("\n\t");
1204 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1205 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1206 }
1207 #endif
1208 return size+4;
1209 }
1211 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1212 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1213 #ifndef PRODUCT
1214 else if( !do_size ) {
1215 if( size != 0 ) st->print("\n\t");
1216 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1217 }
1218 #endif
1219 return size+4;
1220 }
1222 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1223 PhaseRegAlloc *ra_,
1224 bool do_size,
1225 outputStream* st ) const {
1226 // Get registers to move
1227 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1228 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1229 OptoReg::Name dst_second = ra_->get_reg_second(this );
1230 OptoReg::Name dst_first = ra_->get_reg_first(this );
1232 enum RC src_second_rc = rc_class(src_second);
1233 enum RC src_first_rc = rc_class(src_first);
1234 enum RC dst_second_rc = rc_class(dst_second);
1235 enum RC dst_first_rc = rc_class(dst_first);
1237 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1239 // Generate spill code!
1240 int size = 0;
1242 if( src_first == dst_first && src_second == dst_second )
1243 return size; // Self copy, no move
1245 // --------------------------------------
1246 // Check for mem-mem move. Load into unused float registers and fall into
1247 // the float-store case.
1248 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1249 int offset = ra_->reg2offset(src_first);
1250 // Further check for aligned-adjacent pair, so we can use a double load
1251 if( (src_first&1)==0 && src_first+1 == src_second ) {
1252 src_second = OptoReg::Name(R_F31_num);
1253 src_second_rc = rc_float;
1254 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1255 } else {
1256 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1257 }
1258 src_first = OptoReg::Name(R_F30_num);
1259 src_first_rc = rc_float;
1260 }
1262 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1263 int offset = ra_->reg2offset(src_second);
1264 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1265 src_second = OptoReg::Name(R_F31_num);
1266 src_second_rc = rc_float;
1267 }
1269 // --------------------------------------
1270 // Check for float->int copy; requires a trip through memory
1271 if( src_first_rc == rc_float && dst_first_rc == rc_int ) {
1272 int offset = frame::register_save_words*wordSize;
1273 if( cbuf ) {
1274 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1275 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1276 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1277 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1278 }
1279 #ifndef PRODUCT
1280 else if( !do_size ) {
1281 if( size != 0 ) st->print("\n\t");
1282 st->print( "SUB R_SP,16,R_SP\n");
1283 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1284 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1285 st->print("\tADD R_SP,16,R_SP\n");
1286 }
1287 #endif
1288 size += 16;
1289 }
1291 // --------------------------------------
1292 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1293 // In such cases, I have to do the big-endian swap. For aligned targets, the
1294 // hardware does the flop for me. Doubles are always aligned, so no problem
1295 // there. Misaligned sources only come from native-long-returns (handled
1296 // special below).
1297 #ifndef _LP64
1298 if( src_first_rc == rc_int && // source is already big-endian
1299 src_second_rc != rc_bad && // 64-bit move
1300 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1301 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1302 // Do the big-endian flop.
1303 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1304 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1305 }
1306 #endif
1308 // --------------------------------------
1309 // Check for integer reg-reg copy
1310 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1311 #ifndef _LP64
1312 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1313 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1314 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1315 // operand contains the least significant word of the 64-bit value and vice versa.
1316 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1317 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1318 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1319 if( cbuf ) {
1320 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1321 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1322 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1323 #ifndef PRODUCT
1324 } else if( !do_size ) {
1325 if( size != 0 ) st->print("\n\t");
1326 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1327 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1328 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1329 #endif
1330 }
1331 return size+12;
1332 }
1333 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1334 // returning a long value in I0/I1
1335 // a SpillCopy must be able to target a return instruction's reg_class
1336 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1337 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1338 // operand contains the least significant word of the 64-bit value and vice versa.
1339 OptoReg::Name tdest = dst_first;
1341 if (src_first == dst_first) {
1342 tdest = OptoReg::Name(R_O7_num);
1343 size += 4;
1344 }
1346 if( cbuf ) {
1347 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1348 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1349 // ShrL_reg_imm6
1350 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1351 // ShrR_reg_imm6 src, 0, dst
1352 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1353 if (tdest != dst_first) {
1354 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1355 }
1356 }
1357 #ifndef PRODUCT
1358 else if( !do_size ) {
1359 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1360 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1361 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1362 if (tdest != dst_first) {
1363 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1364 }
1365 }
1366 #endif // PRODUCT
1367 return size+8;
1368 }
1369 #endif // !_LP64
1370 // Else normal reg-reg copy
1371 assert( src_second != dst_first, "smashed second before evacuating it" );
1372 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1373 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1374 // This moves an aligned adjacent pair.
1375 // See if we are done.
1376 if( src_first+1 == src_second && dst_first+1 == dst_second )
1377 return size;
1378 }
1380 // Check for integer store
1381 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1382 int offset = ra_->reg2offset(dst_first);
1383 // Further check for aligned-adjacent pair, so we can use a double store
1384 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1385 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1386 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1387 }
1389 // Check for integer load
1390 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1391 int offset = ra_->reg2offset(src_first);
1392 // Further check for aligned-adjacent pair, so we can use a double load
1393 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1394 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1395 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1396 }
1398 // Check for float reg-reg copy
1399 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1400 // Further check for aligned-adjacent pair, so we can use a double move
1401 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1402 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1403 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1404 }
1406 // Check for float store
1407 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1408 int offset = ra_->reg2offset(dst_first);
1409 // Further check for aligned-adjacent pair, so we can use a double store
1410 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1411 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1412 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1413 }
1415 // Check for float load
1416 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1417 int offset = ra_->reg2offset(src_first);
1418 // Further check for aligned-adjacent pair, so we can use a double load
1419 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1420 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1421 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1422 }
1424 // --------------------------------------------------------------------
1425 // Check for hi bits still needing moving. Only happens for misaligned
1426 // arguments to native calls.
1427 if( src_second == dst_second )
1428 return size; // Self copy; no move
1429 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1431 #ifndef _LP64
1432 // In the LP64 build, all registers can be moved as aligned/adjacent
1433 // pairs, so there's never any need to move the high bits seperately.
1434 // The 32-bit builds have to deal with the 32-bit ABI which can force
1435 // all sorts of silly alignment problems.
1437 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1438 // 32-bits of a 64-bit register, but are needed in low bits of another
1439 // register (else it's a hi-bits-to-hi-bits copy which should have
1440 // happened already as part of a 64-bit move)
1441 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1442 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1443 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1444 // Shift src_second down to dst_second's low bits.
1445 if( cbuf ) {
1446 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1447 #ifndef PRODUCT
1448 } else if( !do_size ) {
1449 if( size != 0 ) st->print("\n\t");
1450 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1451 #endif
1452 }
1453 return size+4;
1454 }
1456 // Check for high word integer store. Must down-shift the hi bits
1457 // into a temp register, then fall into the case of storing int bits.
1458 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1459 // Shift src_second down to dst_second's low bits.
1460 if( cbuf ) {
1461 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1462 #ifndef PRODUCT
1463 } else if( !do_size ) {
1464 if( size != 0 ) st->print("\n\t");
1465 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1466 #endif
1467 }
1468 size+=4;
1469 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1470 }
1472 // Check for high word integer load
1473 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1474 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1476 // Check for high word integer store
1477 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1478 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1480 // Check for high word float store
1481 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1482 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1484 #endif // !_LP64
1486 Unimplemented();
1487 }
1489 #ifndef PRODUCT
1490 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1491 implementation( NULL, ra_, false, st );
1492 }
1493 #endif
1495 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1496 implementation( &cbuf, ra_, false, NULL );
1497 }
1499 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1500 return implementation( NULL, ra_, true, NULL );
1501 }
1503 //=============================================================================
1504 #ifndef PRODUCT
1505 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1506 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1507 }
1508 #endif
1510 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1511 MacroAssembler _masm(&cbuf);
1512 for(int i = 0; i < _count; i += 1) {
1513 __ nop();
1514 }
1515 }
1517 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1518 return 4 * _count;
1519 }
1522 //=============================================================================
1523 #ifndef PRODUCT
1524 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1525 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1526 int reg = ra_->get_reg_first(this);
1527 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1528 }
1529 #endif
1531 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1532 MacroAssembler _masm(&cbuf);
1533 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1534 int reg = ra_->get_encode(this);
1536 if (Assembler::is_simm13(offset)) {
1537 __ add(SP, offset, reg_to_register_object(reg));
1538 } else {
1539 __ set(offset, O7);
1540 __ add(SP, O7, reg_to_register_object(reg));
1541 }
1542 }
1544 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1545 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1546 assert(ra_ == ra_->C->regalloc(), "sanity");
1547 return ra_->C->scratch_emit_size(this);
1548 }
1550 //=============================================================================
1552 // emit call stub, compiled java to interpretor
1553 void emit_java_to_interp(CodeBuffer &cbuf ) {
1555 // Stub is fixed up when the corresponding call is converted from calling
1556 // compiled code to calling interpreted code.
1557 // set (empty), G5
1558 // jmp -1
1560 address mark = cbuf.inst_mark(); // get mark within main instrs section
1562 MacroAssembler _masm(&cbuf);
1564 address base =
1565 __ start_a_stub(Compile::MAX_stubs_size);
1566 if (base == NULL) return; // CodeBuffer::expand failed
1568 // static stub relocation stores the instruction address of the call
1569 __ relocate(static_stub_Relocation::spec(mark));
1571 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1573 __ set_inst_mark();
1574 Address a(G3, (address)-1);
1575 __ JUMP(a, 0);
1577 __ delayed()->nop();
1579 // Update current stubs pointer and restore code_end.
1580 __ end_a_stub();
1581 }
1583 // size of call stub, compiled java to interpretor
1584 uint size_java_to_interp() {
1585 // This doesn't need to be accurate but it must be larger or equal to
1586 // the real size of the stub.
1587 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1588 NativeJump::instruction_size + // sethi; jmp; nop
1589 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1590 }
1591 // relocation entries for call stub, compiled java to interpretor
1592 uint reloc_java_to_interp() {
1593 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1594 }
1597 //=============================================================================
1598 #ifndef PRODUCT
1599 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1600 st->print_cr("\nUEP:");
1601 #ifdef _LP64
1602 if (UseCompressedOops) {
1603 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1604 st->print_cr("\tSLL R_G5,3,R_G5");
1605 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1606 } else {
1607 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1608 }
1609 st->print_cr("\tCMP R_G5,R_G3" );
1610 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1611 #else // _LP64
1612 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1613 st->print_cr("\tCMP R_G5,R_G3" );
1614 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1615 #endif // _LP64
1616 }
1617 #endif
1619 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1620 MacroAssembler _masm(&cbuf);
1621 Label L;
1622 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1623 Register temp_reg = G3;
1624 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1626 // Load klass from reciever
1627 __ load_klass(O0, temp_reg);
1628 // Compare against expected klass
1629 __ cmp(temp_reg, G5_ic_reg);
1630 // Branch to miss code, checks xcc or icc depending
1631 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1632 }
1634 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1635 return MachNode::size(ra_);
1636 }
1639 //=============================================================================
1641 uint size_exception_handler() {
1642 if (TraceJumps) {
1643 return (400); // just a guess
1644 }
1645 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1646 }
1648 uint size_deopt_handler() {
1649 if (TraceJumps) {
1650 return (400); // just a guess
1651 }
1652 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1653 }
1655 // Emit exception handler code.
1656 int emit_exception_handler(CodeBuffer& cbuf) {
1657 Register temp_reg = G3;
1658 Address exception_blob(temp_reg, OptoRuntime::exception_blob()->instructions_begin());
1659 MacroAssembler _masm(&cbuf);
1661 address base =
1662 __ start_a_stub(size_exception_handler());
1663 if (base == NULL) return 0; // CodeBuffer::expand failed
1665 int offset = __ offset();
1667 __ JUMP(exception_blob, 0); // sethi;jmp
1668 __ delayed()->nop();
1670 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1672 __ end_a_stub();
1674 return offset;
1675 }
1677 int emit_deopt_handler(CodeBuffer& cbuf) {
1678 // Can't use any of the current frame's registers as we may have deopted
1679 // at a poll and everything (including G3) can be live.
1680 Register temp_reg = L0;
1681 Address deopt_blob(temp_reg, SharedRuntime::deopt_blob()->unpack());
1682 MacroAssembler _masm(&cbuf);
1684 address base =
1685 __ start_a_stub(size_deopt_handler());
1686 if (base == NULL) return 0; // CodeBuffer::expand failed
1688 int offset = __ offset();
1689 __ save_frame(0);
1690 __ JUMP(deopt_blob, 0); // sethi;jmp
1691 __ delayed()->restore();
1693 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1695 __ end_a_stub();
1696 return offset;
1698 }
1700 // Given a register encoding, produce a Integer Register object
1701 static Register reg_to_register_object(int register_encoding) {
1702 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1703 return as_Register(register_encoding);
1704 }
1706 // Given a register encoding, produce a single-precision Float Register object
1707 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1708 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1709 return as_SingleFloatRegister(register_encoding);
1710 }
1712 // Given a register encoding, produce a double-precision Float Register object
1713 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1714 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1715 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1716 return as_DoubleFloatRegister(register_encoding);
1717 }
1719 int Matcher::regnum_to_fpu_offset(int regnum) {
1720 return regnum - 32; // The FP registers are in the second chunk
1721 }
1723 #ifdef ASSERT
1724 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1725 #endif
1727 // Vector width in bytes
1728 const uint Matcher::vector_width_in_bytes(void) {
1729 return 8;
1730 }
1732 // Vector ideal reg
1733 const uint Matcher::vector_ideal_reg(void) {
1734 return Op_RegD;
1735 }
1737 // USII supports fxtof through the whole range of number, USIII doesn't
1738 const bool Matcher::convL2FSupported(void) {
1739 return VM_Version::has_fast_fxtof();
1740 }
1742 // Is this branch offset short enough that a short branch can be used?
1743 //
1744 // NOTE: If the platform does not provide any short branch variants, then
1745 // this method should return false for offset 0.
1746 bool Matcher::is_short_branch_offset(int rule, int offset) {
1747 return false;
1748 }
1750 const bool Matcher::isSimpleConstant64(jlong value) {
1751 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1752 // Depends on optimizations in MacroAssembler::setx.
1753 int hi = (int)(value >> 32);
1754 int lo = (int)(value & ~0);
1755 return (hi == 0) || (hi == -1) || (lo == 0);
1756 }
1758 // No scaling for the parameter the ClearArray node.
1759 const bool Matcher::init_array_count_is_in_bytes = true;
1761 // Threshold size for cleararray.
1762 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1764 // Should the Matcher clone shifts on addressing modes, expecting them to
1765 // be subsumed into complex addressing expressions or compute them into
1766 // registers? True for Intel but false for most RISCs
1767 const bool Matcher::clone_shift_expressions = false;
1769 // Is it better to copy float constants, or load them directly from memory?
1770 // Intel can load a float constant from a direct address, requiring no
1771 // extra registers. Most RISCs will have to materialize an address into a
1772 // register first, so they would do better to copy the constant from stack.
1773 const bool Matcher::rematerialize_float_constants = false;
1775 // If CPU can load and store mis-aligned doubles directly then no fixup is
1776 // needed. Else we split the double into 2 integer pieces and move it
1777 // piece-by-piece. Only happens when passing doubles into C code as the
1778 // Java calling convention forces doubles to be aligned.
1779 #ifdef _LP64
1780 const bool Matcher::misaligned_doubles_ok = true;
1781 #else
1782 const bool Matcher::misaligned_doubles_ok = false;
1783 #endif
1785 // No-op on SPARC.
1786 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1787 }
1789 // Advertise here if the CPU requires explicit rounding operations
1790 // to implement the UseStrictFP mode.
1791 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1793 // Do floats take an entire double register or just half?
1794 const bool Matcher::float_in_double = false;
1796 // Do ints take an entire long register or just half?
1797 // Note that we if-def off of _LP64.
1798 // The relevant question is how the int is callee-saved. In _LP64
1799 // the whole long is written but de-opt'ing will have to extract
1800 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1801 #ifdef _LP64
1802 const bool Matcher::int_in_long = true;
1803 #else
1804 const bool Matcher::int_in_long = false;
1805 #endif
1807 // Return whether or not this register is ever used as an argument. This
1808 // function is used on startup to build the trampoline stubs in generateOptoStub.
1809 // Registers not mentioned will be killed by the VM call in the trampoline, and
1810 // arguments in those registers not be available to the callee.
1811 bool Matcher::can_be_java_arg( int reg ) {
1812 // Standard sparc 6 args in registers
1813 if( reg == R_I0_num ||
1814 reg == R_I1_num ||
1815 reg == R_I2_num ||
1816 reg == R_I3_num ||
1817 reg == R_I4_num ||
1818 reg == R_I5_num ) return true;
1819 #ifdef _LP64
1820 // 64-bit builds can pass 64-bit pointers and longs in
1821 // the high I registers
1822 if( reg == R_I0H_num ||
1823 reg == R_I1H_num ||
1824 reg == R_I2H_num ||
1825 reg == R_I3H_num ||
1826 reg == R_I4H_num ||
1827 reg == R_I5H_num ) return true;
1829 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1830 return true;
1831 }
1833 #else
1834 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1835 // Longs cannot be passed in O regs, because O regs become I regs
1836 // after a 'save' and I regs get their high bits chopped off on
1837 // interrupt.
1838 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1839 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1840 #endif
1841 // A few float args in registers
1842 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1844 return false;
1845 }
1847 bool Matcher::is_spillable_arg( int reg ) {
1848 return can_be_java_arg(reg);
1849 }
1851 // Register for DIVI projection of divmodI
1852 RegMask Matcher::divI_proj_mask() {
1853 ShouldNotReachHere();
1854 return RegMask();
1855 }
1857 // Register for MODI projection of divmodI
1858 RegMask Matcher::modI_proj_mask() {
1859 ShouldNotReachHere();
1860 return RegMask();
1861 }
1863 // Register for DIVL projection of divmodL
1864 RegMask Matcher::divL_proj_mask() {
1865 ShouldNotReachHere();
1866 return RegMask();
1867 }
1869 // Register for MODL projection of divmodL
1870 RegMask Matcher::modL_proj_mask() {
1871 ShouldNotReachHere();
1872 return RegMask();
1873 }
1875 %}
1878 // The intptr_t operand types, defined by textual substitution.
1879 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1880 #ifdef _LP64
1881 #define immX immL
1882 #define immX13 immL13
1883 #define iRegX iRegL
1884 #define g1RegX g1RegL
1885 #else
1886 #define immX immI
1887 #define immX13 immI13
1888 #define iRegX iRegI
1889 #define g1RegX g1RegI
1890 #endif
1892 //----------ENCODING BLOCK-----------------------------------------------------
1893 // This block specifies the encoding classes used by the compiler to output
1894 // byte streams. Encoding classes are parameterized macros used by
1895 // Machine Instruction Nodes in order to generate the bit encoding of the
1896 // instruction. Operands specify their base encoding interface with the
1897 // interface keyword. There are currently supported four interfaces,
1898 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1899 // operand to generate a function which returns its register number when
1900 // queried. CONST_INTER causes an operand to generate a function which
1901 // returns the value of the constant when queried. MEMORY_INTER causes an
1902 // operand to generate four functions which return the Base Register, the
1903 // Index Register, the Scale Value, and the Offset Value of the operand when
1904 // queried. COND_INTER causes an operand to generate six functions which
1905 // return the encoding code (ie - encoding bits for the instruction)
1906 // associated with each basic boolean condition for a conditional instruction.
1907 //
1908 // Instructions specify two basic values for encoding. Again, a function
1909 // is available to check if the constant displacement is an oop. They use the
1910 // ins_encode keyword to specify their encoding classes (which must be
1911 // a sequence of enc_class names, and their parameters, specified in
1912 // the encoding block), and they use the
1913 // opcode keyword to specify, in order, their primary, secondary, and
1914 // tertiary opcode. Only the opcode sections which a particular instruction
1915 // needs for encoding need to be specified.
1916 encode %{
1917 enc_class enc_untested %{
1918 #ifdef ASSERT
1919 MacroAssembler _masm(&cbuf);
1920 __ untested("encoding");
1921 #endif
1922 %}
1924 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
1925 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
1926 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1927 %}
1929 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
1930 emit_form3_mem_reg(cbuf, this, $primary, -1,
1931 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
1932 %}
1934 enc_class form3_mem_reg_little( memory mem, iRegI dst) %{
1935 emit_form3_mem_reg_asi(cbuf, this, $primary, -1,
1936 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg, Assembler::ASI_PRIMARY_LITTLE);
1937 %}
1939 enc_class form3_mem_prefetch_read( memory mem ) %{
1940 emit_form3_mem_reg(cbuf, this, $primary, -1,
1941 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
1942 %}
1944 enc_class form3_mem_prefetch_write( memory mem ) %{
1945 emit_form3_mem_reg(cbuf, this, $primary, -1,
1946 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
1947 %}
1949 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
1950 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1951 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1952 guarantee($mem$$index == R_G0_enc, "double index?");
1953 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
1954 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
1955 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
1956 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
1957 %}
1959 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
1960 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
1961 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
1962 guarantee($mem$$index == R_G0_enc, "double index?");
1963 // Load long with 2 instructions
1964 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
1965 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
1966 %}
1968 //%%% form3_mem_plus_4_reg is a hack--get rid of it
1969 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
1970 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
1971 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
1972 %}
1974 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
1975 // Encode a reg-reg copy. If it is useless, then empty encoding.
1976 if( $rs2$$reg != $rd$$reg )
1977 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
1978 %}
1980 // Target lo half of long
1981 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
1982 // Encode a reg-reg copy. If it is useless, then empty encoding.
1983 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
1984 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
1985 %}
1987 // Source lo half of long
1988 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
1989 // Encode a reg-reg copy. If it is useless, then empty encoding.
1990 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
1991 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
1992 %}
1994 // Target hi half of long
1995 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
1996 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
1997 %}
1999 // Source lo half of long, and leave it sign extended.
2000 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2001 // Sign extend low half
2002 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2003 %}
2005 // Source hi half of long, and leave it sign extended.
2006 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2007 // Shift high half to low half
2008 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2009 %}
2011 // Source hi half of long
2012 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2013 // Encode a reg-reg copy. If it is useless, then empty encoding.
2014 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2015 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2016 %}
2018 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2019 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2020 %}
2022 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2023 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2024 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2025 %}
2027 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2028 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2029 // clear if nothing else is happening
2030 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2031 // blt,a,pn done
2032 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2033 // mov dst,-1 in delay slot
2034 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2035 %}
2037 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2038 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2039 %}
2041 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2042 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2043 %}
2045 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2046 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2047 %}
2049 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2050 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2051 %}
2053 enc_class move_return_pc_to_o1() %{
2054 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2055 %}
2057 #ifdef _LP64
2058 /* %%% merge with enc_to_bool */
2059 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2060 MacroAssembler _masm(&cbuf);
2062 Register src_reg = reg_to_register_object($src$$reg);
2063 Register dst_reg = reg_to_register_object($dst$$reg);
2064 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2065 %}
2066 #endif
2068 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2069 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2070 MacroAssembler _masm(&cbuf);
2072 Register p_reg = reg_to_register_object($p$$reg);
2073 Register q_reg = reg_to_register_object($q$$reg);
2074 Register y_reg = reg_to_register_object($y$$reg);
2075 Register tmp_reg = reg_to_register_object($tmp$$reg);
2077 __ subcc( p_reg, q_reg, p_reg );
2078 __ add ( p_reg, y_reg, tmp_reg );
2079 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2080 %}
2082 enc_class form_d2i_helper(regD src, regF dst) %{
2083 // fcmp %fcc0,$src,$src
2084 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2085 // branch %fcc0 not-nan, predict taken
2086 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2087 // fdtoi $src,$dst
2088 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2089 // fitos $dst,$dst (if nan)
2090 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2091 // clear $dst (if nan)
2092 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2093 // carry on here...
2094 %}
2096 enc_class form_d2l_helper(regD src, regD dst) %{
2097 // fcmp %fcc0,$src,$src check for NAN
2098 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2099 // branch %fcc0 not-nan, predict taken
2100 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2101 // fdtox $src,$dst convert in delay slot
2102 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2103 // fxtod $dst,$dst (if nan)
2104 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2105 // clear $dst (if nan)
2106 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2107 // carry on here...
2108 %}
2110 enc_class form_f2i_helper(regF src, regF dst) %{
2111 // fcmps %fcc0,$src,$src
2112 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2113 // branch %fcc0 not-nan, predict taken
2114 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2115 // fstoi $src,$dst
2116 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2117 // fitos $dst,$dst (if nan)
2118 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2119 // clear $dst (if nan)
2120 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2121 // carry on here...
2122 %}
2124 enc_class form_f2l_helper(regF src, regD dst) %{
2125 // fcmps %fcc0,$src,$src
2126 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2127 // branch %fcc0 not-nan, predict taken
2128 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2129 // fstox $src,$dst
2130 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2131 // fxtod $dst,$dst (if nan)
2132 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2133 // clear $dst (if nan)
2134 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2135 // carry on here...
2136 %}
2138 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2139 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2140 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2141 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2143 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2145 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2146 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2148 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2149 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2150 %}
2152 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2153 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2154 %}
2156 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2157 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2158 %}
2160 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2161 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2162 %}
2164 enc_class form3_convI2F(regF rs2, regF rd) %{
2165 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2166 %}
2168 // Encloding class for traceable jumps
2169 enc_class form_jmpl(g3RegP dest) %{
2170 emit_jmpl(cbuf, $dest$$reg);
2171 %}
2173 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2174 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2175 %}
2177 enc_class form2_nop() %{
2178 emit_nop(cbuf);
2179 %}
2181 enc_class form2_illtrap() %{
2182 emit_illtrap(cbuf);
2183 %}
2186 // Compare longs and convert into -1, 0, 1.
2187 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2188 // CMP $src1,$src2
2189 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2190 // blt,a,pn done
2191 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2192 // mov dst,-1 in delay slot
2193 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2194 // bgt,a,pn done
2195 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2196 // mov dst,1 in delay slot
2197 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2198 // CLR $dst
2199 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2200 %}
2202 enc_class enc_PartialSubtypeCheck() %{
2203 MacroAssembler _masm(&cbuf);
2204 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2205 __ delayed()->nop();
2206 %}
2208 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{
2209 MacroAssembler _masm(&cbuf);
2210 Label &L = *($labl$$label);
2211 Assembler::Predict predict_taken =
2212 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2214 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L);
2215 __ delayed()->nop();
2216 %}
2218 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{
2219 MacroAssembler _masm(&cbuf);
2220 Label &L = *($labl$$label);
2221 Assembler::Predict predict_taken =
2222 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2224 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L);
2225 __ delayed()->nop();
2226 %}
2228 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
2229 MacroAssembler _masm(&cbuf);
2230 Label &L = *($labl$$label);
2231 Assembler::Predict predict_taken =
2232 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2234 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
2235 __ delayed()->nop();
2236 %}
2238 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
2239 MacroAssembler _masm(&cbuf);
2240 Label &L = *($labl$$label);
2241 Assembler::Predict predict_taken =
2242 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2244 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
2245 __ delayed()->nop();
2246 %}
2248 enc_class jump_enc( iRegX switch_val, o7RegI table) %{
2249 MacroAssembler _masm(&cbuf);
2251 Register switch_reg = as_Register($switch_val$$reg);
2252 Register table_reg = O7;
2254 address table_base = __ address_table_constant(_index2label);
2255 RelocationHolder rspec = internal_word_Relocation::spec(table_base);
2257 // Load table address
2258 Address the_pc(table_reg, table_base, rspec);
2259 __ load_address(the_pc);
2261 // Jump to base address + switch value
2262 __ ld_ptr(table_reg, switch_reg, table_reg);
2263 __ jmp(table_reg, G0);
2264 __ delayed()->nop();
2266 %}
2268 enc_class enc_ba( Label labl ) %{
2269 MacroAssembler _masm(&cbuf);
2270 Label &L = *($labl$$label);
2271 __ ba(false, L);
2272 __ delayed()->nop();
2273 %}
2275 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
2276 MacroAssembler _masm(&cbuf);
2277 Label &L = *$labl$$label;
2278 Assembler::Predict predict_taken =
2279 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2281 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
2282 __ delayed()->nop();
2283 %}
2285 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2286 int op = (Assembler::arith_op << 30) |
2287 ($dst$$reg << 25) |
2288 (Assembler::movcc_op3 << 19) |
2289 (1 << 18) | // cc2 bit for 'icc'
2290 ($cmp$$cmpcode << 14) |
2291 (0 << 13) | // select register move
2292 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2293 ($src$$reg << 0);
2294 *((int*)(cbuf.code_end())) = op;
2295 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2296 %}
2298 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2299 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2300 int op = (Assembler::arith_op << 30) |
2301 ($dst$$reg << 25) |
2302 (Assembler::movcc_op3 << 19) |
2303 (1 << 18) | // cc2 bit for 'icc'
2304 ($cmp$$cmpcode << 14) |
2305 (1 << 13) | // select immediate move
2306 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2307 (simm11 << 0);
2308 *((int*)(cbuf.code_end())) = op;
2309 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2310 %}
2312 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2313 int op = (Assembler::arith_op << 30) |
2314 ($dst$$reg << 25) |
2315 (Assembler::movcc_op3 << 19) |
2316 (0 << 18) | // cc2 bit for 'fccX'
2317 ($cmp$$cmpcode << 14) |
2318 (0 << 13) | // select register move
2319 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2320 ($src$$reg << 0);
2321 *((int*)(cbuf.code_end())) = op;
2322 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2323 %}
2325 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2326 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2327 int op = (Assembler::arith_op << 30) |
2328 ($dst$$reg << 25) |
2329 (Assembler::movcc_op3 << 19) |
2330 (0 << 18) | // cc2 bit for 'fccX'
2331 ($cmp$$cmpcode << 14) |
2332 (1 << 13) | // select immediate move
2333 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2334 (simm11 << 0);
2335 *((int*)(cbuf.code_end())) = op;
2336 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2337 %}
2339 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2340 int op = (Assembler::arith_op << 30) |
2341 ($dst$$reg << 25) |
2342 (Assembler::fpop2_op3 << 19) |
2343 (0 << 18) |
2344 ($cmp$$cmpcode << 14) |
2345 (1 << 13) | // select register move
2346 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2347 ($primary << 5) | // select single, double or quad
2348 ($src$$reg << 0);
2349 *((int*)(cbuf.code_end())) = op;
2350 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2351 %}
2353 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2354 int op = (Assembler::arith_op << 30) |
2355 ($dst$$reg << 25) |
2356 (Assembler::fpop2_op3 << 19) |
2357 (0 << 18) |
2358 ($cmp$$cmpcode << 14) |
2359 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2360 ($primary << 5) | // select single, double or quad
2361 ($src$$reg << 0);
2362 *((int*)(cbuf.code_end())) = op;
2363 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2364 %}
2366 // Used by the MIN/MAX encodings. Same as a CMOV, but
2367 // the condition comes from opcode-field instead of an argument.
2368 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2369 int op = (Assembler::arith_op << 30) |
2370 ($dst$$reg << 25) |
2371 (Assembler::movcc_op3 << 19) |
2372 (1 << 18) | // cc2 bit for 'icc'
2373 ($primary << 14) |
2374 (0 << 13) | // select register move
2375 (0 << 11) | // cc1, cc0 bits for 'icc'
2376 ($src$$reg << 0);
2377 *((int*)(cbuf.code_end())) = op;
2378 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2379 %}
2381 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2382 int op = (Assembler::arith_op << 30) |
2383 ($dst$$reg << 25) |
2384 (Assembler::movcc_op3 << 19) |
2385 (6 << 16) | // cc2 bit for 'xcc'
2386 ($primary << 14) |
2387 (0 << 13) | // select register move
2388 (0 << 11) | // cc1, cc0 bits for 'icc'
2389 ($src$$reg << 0);
2390 *((int*)(cbuf.code_end())) = op;
2391 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2392 %}
2394 // Utility encoding for loading a 64 bit Pointer into a register
2395 // The 64 bit pointer is stored in the generated code stream
2396 enc_class SetPtr( immP src, iRegP rd ) %{
2397 Register dest = reg_to_register_object($rd$$reg);
2398 // [RGV] This next line should be generated from ADLC
2399 if ( _opnds[1]->constant_is_oop() ) {
2400 intptr_t val = $src$$constant;
2401 MacroAssembler _masm(&cbuf);
2402 __ set_oop_constant((jobject)val, dest);
2403 } else { // non-oop pointers, e.g. card mark base, heap top
2404 emit_ptr(cbuf, $src$$constant, dest, /*ForceRelocatable=*/ false);
2405 }
2406 %}
2408 enc_class Set13( immI13 src, iRegI rd ) %{
2409 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2410 %}
2412 enc_class SetHi22( immI src, iRegI rd ) %{
2413 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2414 %}
2416 enc_class Set32( immI src, iRegI rd ) %{
2417 MacroAssembler _masm(&cbuf);
2418 __ set($src$$constant, reg_to_register_object($rd$$reg));
2419 %}
2421 enc_class SetNull( iRegI rd ) %{
2422 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 );
2423 %}
2425 enc_class call_epilog %{
2426 if( VerifyStackAtCalls ) {
2427 MacroAssembler _masm(&cbuf);
2428 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2429 Register temp_reg = G3;
2430 __ add(SP, framesize, temp_reg);
2431 __ cmp(temp_reg, FP);
2432 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2433 }
2434 %}
2436 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2437 // to G1 so the register allocator will not have to deal with the misaligned register
2438 // pair.
2439 enc_class adjust_long_from_native_call %{
2440 #ifndef _LP64
2441 if (returns_long()) {
2442 // sllx O0,32,O0
2443 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2444 // srl O1,0,O1
2445 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2446 // or O0,O1,G1
2447 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2448 }
2449 #endif
2450 %}
2452 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2453 // CALL directly to the runtime
2454 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2455 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2456 /*preserve_g2=*/true, /*force far call*/true);
2457 %}
2459 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2460 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2461 // who we intended to call.
2462 if ( !_method ) {
2463 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2464 } else if (_optimized_virtual) {
2465 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2466 } else {
2467 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2468 }
2469 if( _method ) { // Emit stub for static call
2470 emit_java_to_interp(cbuf);
2471 }
2472 %}
2474 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2475 MacroAssembler _masm(&cbuf);
2476 __ set_inst_mark();
2477 int vtable_index = this->_vtable_index;
2478 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2479 if (vtable_index < 0) {
2480 // must be invalid_vtable_index, not nonvirtual_vtable_index
2481 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
2482 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2483 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2484 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2485 // !!!!!
2486 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
2487 // emit_call_dynamic_prologue( cbuf );
2488 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
2490 address virtual_call_oop_addr = __ inst_mark();
2491 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2492 // who we intended to call.
2493 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
2494 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
2495 } else {
2496 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2497 // Just go thru the vtable
2498 // get receiver klass (receiver already checked for non-null)
2499 // If we end up going thru a c2i adapter interpreter expects method in G5
2500 int off = __ offset();
2501 __ load_klass(O0, G3_scratch);
2502 int klass_load_size;
2503 if (UseCompressedOops) {
2504 klass_load_size = 3*BytesPerInstWord;
2505 } else {
2506 klass_load_size = 1*BytesPerInstWord;
2507 }
2508 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2509 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2510 if( __ is_simm13(v_off) ) {
2511 __ ld_ptr(G3, v_off, G5_method);
2512 } else {
2513 // Generate 2 instructions
2514 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2515 __ or3(G5_method, v_off & 0x3ff, G5_method);
2516 // ld_ptr, set_hi, set
2517 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2518 "Unexpected instruction size(s)");
2519 __ ld_ptr(G3, G5_method, G5_method);
2520 }
2521 // NOTE: for vtable dispatches, the vtable entry will never be null.
2522 // However it may very well end up in handle_wrong_method if the
2523 // method is abstract for the particular class.
2524 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
2525 // jump to target (either compiled code or c2iadapter)
2526 __ jmpl(G3_scratch, G0, O7);
2527 __ delayed()->nop();
2528 }
2529 %}
2531 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2532 MacroAssembler _masm(&cbuf);
2534 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2535 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2536 // we might be calling a C2I adapter which needs it.
2538 assert(temp_reg != G5_ic_reg, "conflicting registers");
2539 // Load nmethod
2540 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
2542 // CALL to compiled java, indirect the contents of G3
2543 __ set_inst_mark();
2544 __ callr(temp_reg, G0);
2545 __ delayed()->nop();
2546 %}
2548 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2549 MacroAssembler _masm(&cbuf);
2550 Register Rdividend = reg_to_register_object($src1$$reg);
2551 Register Rdivisor = reg_to_register_object($src2$$reg);
2552 Register Rresult = reg_to_register_object($dst$$reg);
2554 __ sra(Rdivisor, 0, Rdivisor);
2555 __ sra(Rdividend, 0, Rdividend);
2556 __ sdivx(Rdividend, Rdivisor, Rresult);
2557 %}
2559 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2560 MacroAssembler _masm(&cbuf);
2562 Register Rdividend = reg_to_register_object($src1$$reg);
2563 int divisor = $imm$$constant;
2564 Register Rresult = reg_to_register_object($dst$$reg);
2566 __ sra(Rdividend, 0, Rdividend);
2567 __ sdivx(Rdividend, divisor, Rresult);
2568 %}
2570 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2571 MacroAssembler _masm(&cbuf);
2572 Register Rsrc1 = reg_to_register_object($src1$$reg);
2573 Register Rsrc2 = reg_to_register_object($src2$$reg);
2574 Register Rdst = reg_to_register_object($dst$$reg);
2576 __ sra( Rsrc1, 0, Rsrc1 );
2577 __ sra( Rsrc2, 0, Rsrc2 );
2578 __ mulx( Rsrc1, Rsrc2, Rdst );
2579 __ srlx( Rdst, 32, Rdst );
2580 %}
2582 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2583 MacroAssembler _masm(&cbuf);
2584 Register Rdividend = reg_to_register_object($src1$$reg);
2585 Register Rdivisor = reg_to_register_object($src2$$reg);
2586 Register Rresult = reg_to_register_object($dst$$reg);
2587 Register Rscratch = reg_to_register_object($scratch$$reg);
2589 assert(Rdividend != Rscratch, "");
2590 assert(Rdivisor != Rscratch, "");
2592 __ sra(Rdividend, 0, Rdividend);
2593 __ sra(Rdivisor, 0, Rdivisor);
2594 __ sdivx(Rdividend, Rdivisor, Rscratch);
2595 __ mulx(Rscratch, Rdivisor, Rscratch);
2596 __ sub(Rdividend, Rscratch, Rresult);
2597 %}
2599 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2600 MacroAssembler _masm(&cbuf);
2602 Register Rdividend = reg_to_register_object($src1$$reg);
2603 int divisor = $imm$$constant;
2604 Register Rresult = reg_to_register_object($dst$$reg);
2605 Register Rscratch = reg_to_register_object($scratch$$reg);
2607 assert(Rdividend != Rscratch, "");
2609 __ sra(Rdividend, 0, Rdividend);
2610 __ sdivx(Rdividend, divisor, Rscratch);
2611 __ mulx(Rscratch, divisor, Rscratch);
2612 __ sub(Rdividend, Rscratch, Rresult);
2613 %}
2615 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2616 MacroAssembler _masm(&cbuf);
2618 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2619 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2621 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2622 %}
2624 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2625 MacroAssembler _masm(&cbuf);
2627 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2628 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2630 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2631 %}
2633 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2634 MacroAssembler _masm(&cbuf);
2636 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2637 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2639 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2640 %}
2642 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2643 MacroAssembler _masm(&cbuf);
2645 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2646 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2648 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2649 %}
2651 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2652 MacroAssembler _masm(&cbuf);
2654 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2655 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2657 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2658 %}
2660 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2661 MacroAssembler _masm(&cbuf);
2663 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2664 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2666 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2667 %}
2669 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2670 MacroAssembler _masm(&cbuf);
2672 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2673 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2675 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2676 %}
2678 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2679 MacroAssembler _masm(&cbuf);
2681 Register Roop = reg_to_register_object($oop$$reg);
2682 Register Rbox = reg_to_register_object($box$$reg);
2683 Register Rscratch = reg_to_register_object($scratch$$reg);
2684 Register Rmark = reg_to_register_object($scratch2$$reg);
2686 assert(Roop != Rscratch, "");
2687 assert(Roop != Rmark, "");
2688 assert(Rbox != Rscratch, "");
2689 assert(Rbox != Rmark, "");
2691 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters);
2692 %}
2694 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2695 MacroAssembler _masm(&cbuf);
2697 Register Roop = reg_to_register_object($oop$$reg);
2698 Register Rbox = reg_to_register_object($box$$reg);
2699 Register Rscratch = reg_to_register_object($scratch$$reg);
2700 Register Rmark = reg_to_register_object($scratch2$$reg);
2702 assert(Roop != Rscratch, "");
2703 assert(Roop != Rmark, "");
2704 assert(Rbox != Rscratch, "");
2705 assert(Rbox != Rmark, "");
2707 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch);
2708 %}
2710 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2711 MacroAssembler _masm(&cbuf);
2712 Register Rmem = reg_to_register_object($mem$$reg);
2713 Register Rold = reg_to_register_object($old$$reg);
2714 Register Rnew = reg_to_register_object($new$$reg);
2716 // casx_under_lock picks 1 of 3 encodings:
2717 // For 32-bit pointers you get a 32-bit CAS
2718 // For 64-bit pointers you get a 64-bit CASX
2719 __ casx_under_lock(Rmem, Rold, Rnew, // Swap(*Rmem,Rnew) if *Rmem == Rold
2720 (address) StubRoutines::Sparc::atomic_memory_operation_lock_addr());
2721 __ cmp( Rold, Rnew );
2722 %}
2724 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2725 Register Rmem = reg_to_register_object($mem$$reg);
2726 Register Rold = reg_to_register_object($old$$reg);
2727 Register Rnew = reg_to_register_object($new$$reg);
2729 MacroAssembler _masm(&cbuf);
2730 __ mov(Rnew, O7);
2731 __ casx(Rmem, Rold, O7);
2732 __ cmp( Rold, O7 );
2733 %}
2735 // raw int cas, used for compareAndSwap
2736 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2737 Register Rmem = reg_to_register_object($mem$$reg);
2738 Register Rold = reg_to_register_object($old$$reg);
2739 Register Rnew = reg_to_register_object($new$$reg);
2741 MacroAssembler _masm(&cbuf);
2742 __ mov(Rnew, O7);
2743 __ cas(Rmem, Rold, O7);
2744 __ cmp( Rold, O7 );
2745 %}
2747 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2748 Register Rres = reg_to_register_object($res$$reg);
2750 MacroAssembler _masm(&cbuf);
2751 __ mov(1, Rres);
2752 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2753 %}
2755 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2756 Register Rres = reg_to_register_object($res$$reg);
2758 MacroAssembler _masm(&cbuf);
2759 __ mov(1, Rres);
2760 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2761 %}
2763 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2764 MacroAssembler _masm(&cbuf);
2765 Register Rdst = reg_to_register_object($dst$$reg);
2766 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2767 : reg_to_DoubleFloatRegister_object($src1$$reg);
2768 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2769 : reg_to_DoubleFloatRegister_object($src2$$reg);
2771 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2772 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2773 %}
2775 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate
2776 MacroAssembler _masm(&cbuf);
2777 Register dest = reg_to_register_object($dst$$reg);
2778 Register temp = reg_to_register_object($tmp$$reg);
2779 __ set64( $src$$constant, dest, temp );
2780 %}
2782 enc_class LdImmF(immF src, regF dst, o7RegP tmp) %{ // Load Immediate
2783 address float_address = MacroAssembler(&cbuf).float_constant($src$$constant);
2784 RelocationHolder rspec = internal_word_Relocation::spec(float_address);
2785 #ifdef _LP64
2786 Register tmp_reg = reg_to_register_object($tmp$$reg);
2787 cbuf.relocate(cbuf.code_end(), rspec, 0);
2788 emit_ptr(cbuf, (intptr_t)float_address, tmp_reg, /*ForceRelocatable=*/ true);
2789 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::ldf_op3, $tmp$$reg, 0 );
2790 #else // _LP64
2791 uint *code;
2792 int tmp_reg = $tmp$$reg;
2794 cbuf.relocate(cbuf.code_end(), rspec, 0);
2795 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) float_address );
2797 cbuf.relocate(cbuf.code_end(), rspec, 0);
2798 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::ldf_op3, tmp_reg, (intptr_t) float_address );
2799 #endif // _LP64
2800 %}
2802 enc_class LdImmD(immD src, regD dst, o7RegP tmp) %{ // Load Immediate
2803 address double_address = MacroAssembler(&cbuf).double_constant($src$$constant);
2804 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
2805 #ifdef _LP64
2806 Register tmp_reg = reg_to_register_object($tmp$$reg);
2807 cbuf.relocate(cbuf.code_end(), rspec, 0);
2808 emit_ptr(cbuf, (intptr_t)double_address, tmp_reg, /*ForceRelocatable=*/ true);
2809 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, $tmp$$reg, 0 );
2810 #else // _LP64
2811 uint *code;
2812 int tmp_reg = $tmp$$reg;
2814 cbuf.relocate(cbuf.code_end(), rspec, 0);
2815 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) double_address );
2817 cbuf.relocate(cbuf.code_end(), rspec, 0);
2818 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, tmp_reg, (intptr_t) double_address );
2819 #endif // _LP64
2820 %}
2822 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{
2823 // Load a constant replicated "count" times with width "width"
2824 int bit_width = $width$$constant * 8;
2825 jlong elt_val = $src$$constant;
2826 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits
2827 jlong val = elt_val;
2828 for (int i = 0; i < $count$$constant - 1; i++) {
2829 val <<= bit_width;
2830 val |= elt_val;
2831 }
2832 jdouble dval = *(jdouble*)&val; // coerce to double type
2833 address double_address = MacroAssembler(&cbuf).double_constant(dval);
2834 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
2835 #ifdef _LP64
2836 Register tmp_reg = reg_to_register_object($tmp$$reg);
2837 cbuf.relocate(cbuf.code_end(), rspec, 0);
2838 emit_ptr(cbuf, (intptr_t)double_address, tmp_reg, /*ForceRelocatable=*/ true);
2839 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, $tmp$$reg, 0 );
2840 #else // _LP64
2841 uint *code;
2842 int tmp_reg = $tmp$$reg;
2844 cbuf.relocate(cbuf.code_end(), rspec, 0);
2845 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) double_address );
2847 cbuf.relocate(cbuf.code_end(), rspec, 0);
2848 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, tmp_reg, (intptr_t) double_address );
2849 #endif // _LP64
2850 %}
2853 enc_class ShouldNotEncodeThis ( ) %{
2854 ShouldNotCallThis();
2855 %}
2857 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
2858 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
2859 MacroAssembler _masm(&cbuf);
2860 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
2861 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
2862 Register base_pointer_arg = reg_to_register_object($base$$reg);
2864 Label loop;
2865 __ mov(nof_bytes_arg, nof_bytes_tmp);
2867 // Loop and clear, walking backwards through the array.
2868 // nof_bytes_tmp (if >0) is always the number of bytes to zero
2869 __ bind(loop);
2870 __ deccc(nof_bytes_tmp, 8);
2871 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
2872 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
2873 // %%%% this mini-loop must not cross a cache boundary!
2874 %}
2877 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
2878 Label Ldone, Lloop;
2879 MacroAssembler _masm(&cbuf);
2881 Register str1_reg = reg_to_register_object($str1$$reg);
2882 Register str2_reg = reg_to_register_object($str2$$reg);
2883 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
2884 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
2885 Register result_reg = reg_to_register_object($result$$reg);
2887 // Get the first character position in both strings
2888 // [8] char array, [12] offset, [16] count
2889 int value_offset = java_lang_String:: value_offset_in_bytes();
2890 int offset_offset = java_lang_String::offset_offset_in_bytes();
2891 int count_offset = java_lang_String:: count_offset_in_bytes();
2893 // load str1 (jchar*) base address into tmp1_reg
2894 __ load_heap_oop(Address(str1_reg, 0, value_offset), tmp1_reg);
2895 __ ld(Address(str1_reg, 0, offset_offset), result_reg);
2896 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
2897 __ ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted
2898 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2899 __ load_heap_oop(Address(str2_reg, 0, value_offset), tmp2_reg); // hoisted
2900 __ add(result_reg, tmp1_reg, tmp1_reg);
2902 // load str2 (jchar*) base address into tmp2_reg
2903 // __ ld_ptr(Address(str2_reg, 0, value_offset), tmp2_reg); // hoisted
2904 __ ld(Address(str2_reg, 0, offset_offset), result_reg);
2905 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
2906 __ ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted
2907 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2908 __ subcc(str1_reg, str2_reg, O7); // hoisted
2909 __ add(result_reg, tmp2_reg, tmp2_reg);
2911 // Compute the minimum of the string lengths(str1_reg) and the
2912 // difference of the string lengths (stack)
2914 // discard string base pointers, after loading up the lengths
2915 // __ ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted
2916 // __ ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted
2918 // See if the lengths are different, and calculate min in str1_reg.
2919 // Stash diff in O7 in case we need it for a tie-breaker.
2920 Label Lskip;
2921 // __ subcc(str1_reg, str2_reg, O7); // hoisted
2922 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
2923 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2924 // str2 is shorter, so use its count:
2925 __ delayed()->sll(str2_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
2926 __ bind(Lskip);
2928 // reallocate str1_reg, str2_reg, result_reg
2929 // Note: limit_reg holds the string length pre-scaled by 2
2930 Register limit_reg = str1_reg;
2931 Register chr2_reg = str2_reg;
2932 Register chr1_reg = result_reg;
2933 // tmp{12} are the base pointers
2935 // Is the minimum length zero?
2936 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2937 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2938 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2940 // Load first characters
2941 __ lduh(tmp1_reg, 0, chr1_reg);
2942 __ lduh(tmp2_reg, 0, chr2_reg);
2944 // Compare first characters
2945 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2946 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2947 assert(chr1_reg == result_reg, "result must be pre-placed");
2948 __ delayed()->nop();
2950 {
2951 // Check after comparing first character to see if strings are equivalent
2952 Label LSkip2;
2953 // Check if the strings start at same location
2954 __ cmp(tmp1_reg, tmp2_reg);
2955 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2956 __ delayed()->nop();
2958 // Check if the length difference is zero (in O7)
2959 __ cmp(G0, O7);
2960 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2961 __ delayed()->mov(G0, result_reg); // result is zero
2963 // Strings might not be equal
2964 __ bind(LSkip2);
2965 }
2967 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2968 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2969 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2971 // Shift tmp1_reg and tmp2_reg to the end of the arrays, negate limit
2972 __ add(tmp1_reg, limit_reg, tmp1_reg);
2973 __ add(tmp2_reg, limit_reg, tmp2_reg);
2974 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2976 // Compare the rest of the characters
2977 __ lduh(tmp1_reg, limit_reg, chr1_reg);
2978 __ bind(Lloop);
2979 // __ lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
2980 __ lduh(tmp2_reg, limit_reg, chr2_reg);
2981 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2982 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2983 assert(chr1_reg == result_reg, "result must be pre-placed");
2984 __ delayed()->inccc(limit_reg, sizeof(jchar));
2985 // annul LDUH if branch is not taken to prevent access past end of string
2986 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2987 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
2989 // If strings are equal up to min length, return the length difference.
2990 __ mov(O7, result_reg);
2992 // Otherwise, return the difference between the first mismatched chars.
2993 __ bind(Ldone);
2994 %}
2996 enc_class enc_rethrow() %{
2997 cbuf.set_inst_mark();
2998 Register temp_reg = G3;
2999 Address rethrow_stub(temp_reg, OptoRuntime::rethrow_stub());
3000 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3001 MacroAssembler _masm(&cbuf);
3002 #ifdef ASSERT
3003 __ save_frame(0);
3004 Address last_rethrow_addr(L1, (address)&last_rethrow);
3005 __ sethi(last_rethrow_addr);
3006 __ get_pc(L2);
3007 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3008 __ st_ptr(L2, last_rethrow_addr);
3009 __ restore();
3010 #endif
3011 __ JUMP(rethrow_stub, 0); // sethi;jmp
3012 __ delayed()->nop();
3013 %}
3015 enc_class emit_mem_nop() %{
3016 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3017 unsigned int *code = (unsigned int*)cbuf.code_end();
3018 *code = (unsigned int)0xc0839040;
3019 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3020 %}
3022 enc_class emit_fadd_nop() %{
3023 // Generates the instruction FMOVS f31,f31
3024 unsigned int *code = (unsigned int*)cbuf.code_end();
3025 *code = (unsigned int)0xbfa0003f;
3026 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3027 %}
3029 enc_class emit_br_nop() %{
3030 // Generates the instruction BPN,PN .
3031 unsigned int *code = (unsigned int*)cbuf.code_end();
3032 *code = (unsigned int)0x00400000;
3033 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3034 %}
3036 enc_class enc_membar_acquire %{
3037 MacroAssembler _masm(&cbuf);
3038 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3039 %}
3041 enc_class enc_membar_release %{
3042 MacroAssembler _masm(&cbuf);
3043 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3044 %}
3046 enc_class enc_membar_volatile %{
3047 MacroAssembler _masm(&cbuf);
3048 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3049 %}
3051 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
3052 MacroAssembler _masm(&cbuf);
3053 Register src_reg = reg_to_register_object($src$$reg);
3054 Register dst_reg = reg_to_register_object($dst$$reg);
3055 __ sllx(src_reg, 56, dst_reg);
3056 __ srlx(dst_reg, 8, O7);
3057 __ or3 (dst_reg, O7, dst_reg);
3058 __ srlx(dst_reg, 16, O7);
3059 __ or3 (dst_reg, O7, dst_reg);
3060 __ srlx(dst_reg, 32, O7);
3061 __ or3 (dst_reg, O7, dst_reg);
3062 %}
3064 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
3065 MacroAssembler _masm(&cbuf);
3066 Register src_reg = reg_to_register_object($src$$reg);
3067 Register dst_reg = reg_to_register_object($dst$$reg);
3068 __ sll(src_reg, 24, dst_reg);
3069 __ srl(dst_reg, 8, O7);
3070 __ or3(dst_reg, O7, dst_reg);
3071 __ srl(dst_reg, 16, O7);
3072 __ or3(dst_reg, O7, dst_reg);
3073 %}
3075 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
3076 MacroAssembler _masm(&cbuf);
3077 Register src_reg = reg_to_register_object($src$$reg);
3078 Register dst_reg = reg_to_register_object($dst$$reg);
3079 __ sllx(src_reg, 48, dst_reg);
3080 __ srlx(dst_reg, 16, O7);
3081 __ or3 (dst_reg, O7, dst_reg);
3082 __ srlx(dst_reg, 32, O7);
3083 __ or3 (dst_reg, O7, dst_reg);
3084 %}
3086 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
3087 MacroAssembler _masm(&cbuf);
3088 Register src_reg = reg_to_register_object($src$$reg);
3089 Register dst_reg = reg_to_register_object($dst$$reg);
3090 __ sllx(src_reg, 32, dst_reg);
3091 __ srlx(dst_reg, 32, O7);
3092 __ or3 (dst_reg, O7, dst_reg);
3093 %}
3095 %}
3097 //----------FRAME--------------------------------------------------------------
3098 // Definition of frame structure and management information.
3099 //
3100 // S T A C K L A Y O U T Allocators stack-slot number
3101 // | (to get allocators register number
3102 // G Owned by | | v add VMRegImpl::stack0)
3103 // r CALLER | |
3104 // o | +--------+ pad to even-align allocators stack-slot
3105 // w V | pad0 | numbers; owned by CALLER
3106 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3107 // h ^ | in | 5
3108 // | | args | 4 Holes in incoming args owned by SELF
3109 // | | | | 3
3110 // | | +--------+
3111 // V | | old out| Empty on Intel, window on Sparc
3112 // | old |preserve| Must be even aligned.
3113 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3114 // | | in | 3 area for Intel ret address
3115 // Owned by |preserve| Empty on Sparc.
3116 // SELF +--------+
3117 // | | pad2 | 2 pad to align old SP
3118 // | +--------+ 1
3119 // | | locks | 0
3120 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3121 // | | pad1 | 11 pad to align new SP
3122 // | +--------+
3123 // | | | 10
3124 // | | spills | 9 spills
3125 // V | | 8 (pad0 slot for callee)
3126 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3127 // ^ | out | 7
3128 // | | args | 6 Holes in outgoing args owned by CALLEE
3129 // Owned by +--------+
3130 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3131 // | new |preserve| Must be even-aligned.
3132 // | SP-+--------+----> Matcher::_new_SP, even aligned
3133 // | | |
3134 //
3135 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3136 // known from SELF's arguments and the Java calling convention.
3137 // Region 6-7 is determined per call site.
3138 // Note 2: If the calling convention leaves holes in the incoming argument
3139 // area, those holes are owned by SELF. Holes in the outgoing area
3140 // are owned by the CALLEE. Holes should not be nessecary in the
3141 // incoming area, as the Java calling convention is completely under
3142 // the control of the AD file. Doubles can be sorted and packed to
3143 // avoid holes. Holes in the outgoing arguments may be nessecary for
3144 // varargs C calling conventions.
3145 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3146 // even aligned with pad0 as needed.
3147 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3148 // region 6-11 is even aligned; it may be padded out more so that
3149 // the region from SP to FP meets the minimum stack alignment.
3151 frame %{
3152 // What direction does stack grow in (assumed to be same for native & Java)
3153 stack_direction(TOWARDS_LOW);
3155 // These two registers define part of the calling convention
3156 // between compiled code and the interpreter.
3157 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
3158 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3160 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3161 cisc_spilling_operand_name(indOffset);
3163 // Number of stack slots consumed by a Monitor enter
3164 #ifdef _LP64
3165 sync_stack_slots(2);
3166 #else
3167 sync_stack_slots(1);
3168 #endif
3170 // Compiled code's Frame Pointer
3171 frame_pointer(R_SP);
3173 // Stack alignment requirement
3174 stack_alignment(StackAlignmentInBytes);
3175 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3176 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3178 // Number of stack slots between incoming argument block and the start of
3179 // a new frame. The PROLOG must add this many slots to the stack. The
3180 // EPILOG must remove this many slots.
3181 in_preserve_stack_slots(0);
3183 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3184 // for calls to C. Supports the var-args backing area for register parms.
3185 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3186 #ifdef _LP64
3187 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3188 varargs_C_out_slots_killed(12);
3189 #else
3190 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3191 varargs_C_out_slots_killed( 7);
3192 #endif
3194 // The after-PROLOG location of the return address. Location of
3195 // return address specifies a type (REG or STACK) and a number
3196 // representing the register number (i.e. - use a register name) or
3197 // stack slot.
3198 return_addr(REG R_I7); // Ret Addr is in register I7
3200 // Body of function which returns an OptoRegs array locating
3201 // arguments either in registers or in stack slots for calling
3202 // java
3203 calling_convention %{
3204 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3206 %}
3208 // Body of function which returns an OptoRegs array locating
3209 // arguments either in registers or in stack slots for callin
3210 // C.
3211 c_calling_convention %{
3212 // This is obviously always outgoing
3213 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3214 %}
3216 // Location of native (C/C++) and interpreter return values. This is specified to
3217 // be the same as Java. In the 32-bit VM, long values are actually returned from
3218 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3219 // to and from the register pairs is done by the appropriate call and epilog
3220 // opcodes. This simplifies the register allocator.
3221 c_return_value %{
3222 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3223 #ifdef _LP64
3224 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3225 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3226 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3227 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3228 #else // !_LP64
3229 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3230 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3231 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3232 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3233 #endif
3234 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3235 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3236 %}
3238 // Location of compiled Java return values. Same as C
3239 return_value %{
3240 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3241 #ifdef _LP64
3242 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3243 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3244 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3245 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3246 #else // !_LP64
3247 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3248 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3249 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3250 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3251 #endif
3252 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3253 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3254 %}
3256 %}
3259 //----------ATTRIBUTES---------------------------------------------------------
3260 //----------Operand Attributes-------------------------------------------------
3261 op_attrib op_cost(1); // Required cost attribute
3263 //----------Instruction Attributes---------------------------------------------
3264 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3265 ins_attrib ins_size(32); // Required size attribute (in bits)
3266 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3267 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3268 // non-matching short branch variant of some
3269 // long branch?
3271 //----------OPERANDS-----------------------------------------------------------
3272 // Operand definitions must precede instruction definitions for correct parsing
3273 // in the ADLC because operands constitute user defined types which are used in
3274 // instruction definitions.
3276 //----------Simple Operands----------------------------------------------------
3277 // Immediate Operands
3278 // Integer Immediate: 32-bit
3279 operand immI() %{
3280 match(ConI);
3282 op_cost(0);
3283 // formats are generated automatically for constants and base registers
3284 format %{ %}
3285 interface(CONST_INTER);
3286 %}
3288 // Integer Immediate: 13-bit
3289 operand immI13() %{
3290 predicate(Assembler::is_simm13(n->get_int()));
3291 match(ConI);
3292 op_cost(0);
3294 format %{ %}
3295 interface(CONST_INTER);
3296 %}
3298 // Unsigned (positive) Integer Immediate: 13-bit
3299 operand immU13() %{
3300 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3301 match(ConI);
3302 op_cost(0);
3304 format %{ %}
3305 interface(CONST_INTER);
3306 %}
3308 // Integer Immediate: 6-bit
3309 operand immU6() %{
3310 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3311 match(ConI);
3312 op_cost(0);
3313 format %{ %}
3314 interface(CONST_INTER);
3315 %}
3317 // Integer Immediate: 11-bit
3318 operand immI11() %{
3319 predicate(Assembler::is_simm(n->get_int(),11));
3320 match(ConI);
3321 op_cost(0);
3322 format %{ %}
3323 interface(CONST_INTER);
3324 %}
3326 // Integer Immediate: 0-bit
3327 operand immI0() %{
3328 predicate(n->get_int() == 0);
3329 match(ConI);
3330 op_cost(0);
3332 format %{ %}
3333 interface(CONST_INTER);
3334 %}
3336 // Integer Immediate: the value 10
3337 operand immI10() %{
3338 predicate(n->get_int() == 10);
3339 match(ConI);
3340 op_cost(0);
3342 format %{ %}
3343 interface(CONST_INTER);
3344 %}
3346 // Integer Immediate: the values 0-31
3347 operand immU5() %{
3348 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3349 match(ConI);
3350 op_cost(0);
3352 format %{ %}
3353 interface(CONST_INTER);
3354 %}
3356 // Integer Immediate: the values 1-31
3357 operand immI_1_31() %{
3358 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3359 match(ConI);
3360 op_cost(0);
3362 format %{ %}
3363 interface(CONST_INTER);
3364 %}
3366 // Integer Immediate: the values 32-63
3367 operand immI_32_63() %{
3368 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3369 match(ConI);
3370 op_cost(0);
3372 format %{ %}
3373 interface(CONST_INTER);
3374 %}
3376 // Integer Immediate: the value 255
3377 operand immI_255() %{
3378 predicate( n->get_int() == 255 );
3379 match(ConI);
3380 op_cost(0);
3382 format %{ %}
3383 interface(CONST_INTER);
3384 %}
3386 // Long Immediate: the value FF
3387 operand immL_FF() %{
3388 predicate( n->get_long() == 0xFFL );
3389 match(ConL);
3390 op_cost(0);
3392 format %{ %}
3393 interface(CONST_INTER);
3394 %}
3396 // Long Immediate: the value FFFF
3397 operand immL_FFFF() %{
3398 predicate( n->get_long() == 0xFFFFL );
3399 match(ConL);
3400 op_cost(0);
3402 format %{ %}
3403 interface(CONST_INTER);
3404 %}
3406 // Pointer Immediate: 32 or 64-bit
3407 operand immP() %{
3408 match(ConP);
3410 op_cost(5);
3411 // formats are generated automatically for constants and base registers
3412 format %{ %}
3413 interface(CONST_INTER);
3414 %}
3416 operand immP13() %{
3417 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3418 match(ConP);
3419 op_cost(0);
3421 format %{ %}
3422 interface(CONST_INTER);
3423 %}
3425 operand immP0() %{
3426 predicate(n->get_ptr() == 0);
3427 match(ConP);
3428 op_cost(0);
3430 format %{ %}
3431 interface(CONST_INTER);
3432 %}
3434 operand immP_poll() %{
3435 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3436 match(ConP);
3438 // formats are generated automatically for constants and base registers
3439 format %{ %}
3440 interface(CONST_INTER);
3441 %}
3443 // Pointer Immediate
3444 operand immN()
3445 %{
3446 match(ConN);
3448 op_cost(10);
3449 format %{ %}
3450 interface(CONST_INTER);
3451 %}
3453 // NULL Pointer Immediate
3454 operand immN0()
3455 %{
3456 predicate(n->get_narrowcon() == 0);
3457 match(ConN);
3459 op_cost(0);
3460 format %{ %}
3461 interface(CONST_INTER);
3462 %}
3464 operand immL() %{
3465 match(ConL);
3466 op_cost(40);
3467 // formats are generated automatically for constants and base registers
3468 format %{ %}
3469 interface(CONST_INTER);
3470 %}
3472 operand immL0() %{
3473 predicate(n->get_long() == 0L);
3474 match(ConL);
3475 op_cost(0);
3476 // formats are generated automatically for constants and base registers
3477 format %{ %}
3478 interface(CONST_INTER);
3479 %}
3481 // Long Immediate: 13-bit
3482 operand immL13() %{
3483 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3484 match(ConL);
3485 op_cost(0);
3487 format %{ %}
3488 interface(CONST_INTER);
3489 %}
3491 // Long Immediate: low 32-bit mask
3492 operand immL_32bits() %{
3493 predicate(n->get_long() == 0xFFFFFFFFL);
3494 match(ConL);
3495 op_cost(0);
3497 format %{ %}
3498 interface(CONST_INTER);
3499 %}
3501 // Double Immediate
3502 operand immD() %{
3503 match(ConD);
3505 op_cost(40);
3506 format %{ %}
3507 interface(CONST_INTER);
3508 %}
3510 operand immD0() %{
3511 #ifdef _LP64
3512 // on 64-bit architectures this comparision is faster
3513 predicate(jlong_cast(n->getd()) == 0);
3514 #else
3515 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3516 #endif
3517 match(ConD);
3519 op_cost(0);
3520 format %{ %}
3521 interface(CONST_INTER);
3522 %}
3524 // Float Immediate
3525 operand immF() %{
3526 match(ConF);
3528 op_cost(20);
3529 format %{ %}
3530 interface(CONST_INTER);
3531 %}
3533 // Float Immediate: 0
3534 operand immF0() %{
3535 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3536 match(ConF);
3538 op_cost(0);
3539 format %{ %}
3540 interface(CONST_INTER);
3541 %}
3543 // Integer Register Operands
3544 // Integer Register
3545 operand iRegI() %{
3546 constraint(ALLOC_IN_RC(int_reg));
3547 match(RegI);
3549 match(notemp_iRegI);
3550 match(g1RegI);
3551 match(o0RegI);
3552 match(iRegIsafe);
3554 format %{ %}
3555 interface(REG_INTER);
3556 %}
3558 operand notemp_iRegI() %{
3559 constraint(ALLOC_IN_RC(notemp_int_reg));
3560 match(RegI);
3562 match(o0RegI);
3564 format %{ %}
3565 interface(REG_INTER);
3566 %}
3568 operand o0RegI() %{
3569 constraint(ALLOC_IN_RC(o0_regI));
3570 match(iRegI);
3572 format %{ %}
3573 interface(REG_INTER);
3574 %}
3576 // Pointer Register
3577 operand iRegP() %{
3578 constraint(ALLOC_IN_RC(ptr_reg));
3579 match(RegP);
3581 match(lock_ptr_RegP);
3582 match(g1RegP);
3583 match(g2RegP);
3584 match(g3RegP);
3585 match(g4RegP);
3586 match(i0RegP);
3587 match(o0RegP);
3588 match(o1RegP);
3589 match(l7RegP);
3591 format %{ %}
3592 interface(REG_INTER);
3593 %}
3595 operand sp_ptr_RegP() %{
3596 constraint(ALLOC_IN_RC(sp_ptr_reg));
3597 match(RegP);
3598 match(iRegP);
3600 format %{ %}
3601 interface(REG_INTER);
3602 %}
3604 operand lock_ptr_RegP() %{
3605 constraint(ALLOC_IN_RC(lock_ptr_reg));
3606 match(RegP);
3607 match(i0RegP);
3608 match(o0RegP);
3609 match(o1RegP);
3610 match(l7RegP);
3612 format %{ %}
3613 interface(REG_INTER);
3614 %}
3616 operand g1RegP() %{
3617 constraint(ALLOC_IN_RC(g1_regP));
3618 match(iRegP);
3620 format %{ %}
3621 interface(REG_INTER);
3622 %}
3624 operand g2RegP() %{
3625 constraint(ALLOC_IN_RC(g2_regP));
3626 match(iRegP);
3628 format %{ %}
3629 interface(REG_INTER);
3630 %}
3632 operand g3RegP() %{
3633 constraint(ALLOC_IN_RC(g3_regP));
3634 match(iRegP);
3636 format %{ %}
3637 interface(REG_INTER);
3638 %}
3640 operand g1RegI() %{
3641 constraint(ALLOC_IN_RC(g1_regI));
3642 match(iRegI);
3644 format %{ %}
3645 interface(REG_INTER);
3646 %}
3648 operand g3RegI() %{
3649 constraint(ALLOC_IN_RC(g3_regI));
3650 match(iRegI);
3652 format %{ %}
3653 interface(REG_INTER);
3654 %}
3656 operand g4RegI() %{
3657 constraint(ALLOC_IN_RC(g4_regI));
3658 match(iRegI);
3660 format %{ %}
3661 interface(REG_INTER);
3662 %}
3664 operand g4RegP() %{
3665 constraint(ALLOC_IN_RC(g4_regP));
3666 match(iRegP);
3668 format %{ %}
3669 interface(REG_INTER);
3670 %}
3672 operand i0RegP() %{
3673 constraint(ALLOC_IN_RC(i0_regP));
3674 match(iRegP);
3676 format %{ %}
3677 interface(REG_INTER);
3678 %}
3680 operand o0RegP() %{
3681 constraint(ALLOC_IN_RC(o0_regP));
3682 match(iRegP);
3684 format %{ %}
3685 interface(REG_INTER);
3686 %}
3688 operand o1RegP() %{
3689 constraint(ALLOC_IN_RC(o1_regP));
3690 match(iRegP);
3692 format %{ %}
3693 interface(REG_INTER);
3694 %}
3696 operand o2RegP() %{
3697 constraint(ALLOC_IN_RC(o2_regP));
3698 match(iRegP);
3700 format %{ %}
3701 interface(REG_INTER);
3702 %}
3704 operand o7RegP() %{
3705 constraint(ALLOC_IN_RC(o7_regP));
3706 match(iRegP);
3708 format %{ %}
3709 interface(REG_INTER);
3710 %}
3712 operand l7RegP() %{
3713 constraint(ALLOC_IN_RC(l7_regP));
3714 match(iRegP);
3716 format %{ %}
3717 interface(REG_INTER);
3718 %}
3720 operand o7RegI() %{
3721 constraint(ALLOC_IN_RC(o7_regI));
3722 match(iRegI);
3724 format %{ %}
3725 interface(REG_INTER);
3726 %}
3728 operand iRegN() %{
3729 constraint(ALLOC_IN_RC(int_reg));
3730 match(RegN);
3732 format %{ %}
3733 interface(REG_INTER);
3734 %}
3736 // Long Register
3737 operand iRegL() %{
3738 constraint(ALLOC_IN_RC(long_reg));
3739 match(RegL);
3741 format %{ %}
3742 interface(REG_INTER);
3743 %}
3745 operand o2RegL() %{
3746 constraint(ALLOC_IN_RC(o2_regL));
3747 match(iRegL);
3749 format %{ %}
3750 interface(REG_INTER);
3751 %}
3753 operand o7RegL() %{
3754 constraint(ALLOC_IN_RC(o7_regL));
3755 match(iRegL);
3757 format %{ %}
3758 interface(REG_INTER);
3759 %}
3761 operand g1RegL() %{
3762 constraint(ALLOC_IN_RC(g1_regL));
3763 match(iRegL);
3765 format %{ %}
3766 interface(REG_INTER);
3767 %}
3769 // Int Register safe
3770 // This is 64bit safe
3771 operand iRegIsafe() %{
3772 constraint(ALLOC_IN_RC(long_reg));
3774 match(iRegI);
3776 format %{ %}
3777 interface(REG_INTER);
3778 %}
3780 // Condition Code Flag Register
3781 operand flagsReg() %{
3782 constraint(ALLOC_IN_RC(int_flags));
3783 match(RegFlags);
3785 format %{ "ccr" %} // both ICC and XCC
3786 interface(REG_INTER);
3787 %}
3789 // Condition Code Register, unsigned comparisons.
3790 operand flagsRegU() %{
3791 constraint(ALLOC_IN_RC(int_flags));
3792 match(RegFlags);
3794 format %{ "icc_U" %}
3795 interface(REG_INTER);
3796 %}
3798 // Condition Code Register, pointer comparisons.
3799 operand flagsRegP() %{
3800 constraint(ALLOC_IN_RC(int_flags));
3801 match(RegFlags);
3803 #ifdef _LP64
3804 format %{ "xcc_P" %}
3805 #else
3806 format %{ "icc_P" %}
3807 #endif
3808 interface(REG_INTER);
3809 %}
3811 // Condition Code Register, long comparisons.
3812 operand flagsRegL() %{
3813 constraint(ALLOC_IN_RC(int_flags));
3814 match(RegFlags);
3816 format %{ "xcc_L" %}
3817 interface(REG_INTER);
3818 %}
3820 // Condition Code Register, floating comparisons, unordered same as "less".
3821 operand flagsRegF() %{
3822 constraint(ALLOC_IN_RC(float_flags));
3823 match(RegFlags);
3824 match(flagsRegF0);
3826 format %{ %}
3827 interface(REG_INTER);
3828 %}
3830 operand flagsRegF0() %{
3831 constraint(ALLOC_IN_RC(float_flag0));
3832 match(RegFlags);
3834 format %{ %}
3835 interface(REG_INTER);
3836 %}
3839 // Condition Code Flag Register used by long compare
3840 operand flagsReg_long_LTGE() %{
3841 constraint(ALLOC_IN_RC(int_flags));
3842 match(RegFlags);
3843 format %{ "icc_LTGE" %}
3844 interface(REG_INTER);
3845 %}
3846 operand flagsReg_long_EQNE() %{
3847 constraint(ALLOC_IN_RC(int_flags));
3848 match(RegFlags);
3849 format %{ "icc_EQNE" %}
3850 interface(REG_INTER);
3851 %}
3852 operand flagsReg_long_LEGT() %{
3853 constraint(ALLOC_IN_RC(int_flags));
3854 match(RegFlags);
3855 format %{ "icc_LEGT" %}
3856 interface(REG_INTER);
3857 %}
3860 operand regD() %{
3861 constraint(ALLOC_IN_RC(dflt_reg));
3862 match(RegD);
3864 format %{ %}
3865 interface(REG_INTER);
3866 %}
3868 operand regF() %{
3869 constraint(ALLOC_IN_RC(sflt_reg));
3870 match(RegF);
3872 format %{ %}
3873 interface(REG_INTER);
3874 %}
3876 operand regD_low() %{
3877 constraint(ALLOC_IN_RC(dflt_low_reg));
3878 match(RegD);
3880 format %{ %}
3881 interface(REG_INTER);
3882 %}
3884 // Special Registers
3886 // Method Register
3887 operand inline_cache_regP(iRegP reg) %{
3888 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
3889 match(reg);
3890 format %{ %}
3891 interface(REG_INTER);
3892 %}
3894 operand interpreter_method_oop_regP(iRegP reg) %{
3895 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
3896 match(reg);
3897 format %{ %}
3898 interface(REG_INTER);
3899 %}
3902 //----------Complex Operands---------------------------------------------------
3903 // Indirect Memory Reference
3904 operand indirect(sp_ptr_RegP reg) %{
3905 constraint(ALLOC_IN_RC(sp_ptr_reg));
3906 match(reg);
3908 op_cost(100);
3909 format %{ "[$reg]" %}
3910 interface(MEMORY_INTER) %{
3911 base($reg);
3912 index(0x0);
3913 scale(0x0);
3914 disp(0x0);
3915 %}
3916 %}
3918 // Indirect with Offset
3919 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
3920 constraint(ALLOC_IN_RC(sp_ptr_reg));
3921 match(AddP reg offset);
3923 op_cost(100);
3924 format %{ "[$reg + $offset]" %}
3925 interface(MEMORY_INTER) %{
3926 base($reg);
3927 index(0x0);
3928 scale(0x0);
3929 disp($offset);
3930 %}
3931 %}
3933 // Note: Intel has a swapped version also, like this:
3934 //operand indOffsetX(iRegI reg, immP offset) %{
3935 // constraint(ALLOC_IN_RC(int_reg));
3936 // match(AddP offset reg);
3937 //
3938 // op_cost(100);
3939 // format %{ "[$reg + $offset]" %}
3940 // interface(MEMORY_INTER) %{
3941 // base($reg);
3942 // index(0x0);
3943 // scale(0x0);
3944 // disp($offset);
3945 // %}
3946 //%}
3947 //// However, it doesn't make sense for SPARC, since
3948 // we have no particularly good way to embed oops in
3949 // single instructions.
3951 // Indirect with Register Index
3952 operand indIndex(iRegP addr, iRegX index) %{
3953 constraint(ALLOC_IN_RC(ptr_reg));
3954 match(AddP addr index);
3956 op_cost(100);
3957 format %{ "[$addr + $index]" %}
3958 interface(MEMORY_INTER) %{
3959 base($addr);
3960 index($index);
3961 scale(0x0);
3962 disp(0x0);
3963 %}
3964 %}
3966 //----------Special Memory Operands--------------------------------------------
3967 // Stack Slot Operand - This operand is used for loading and storing temporary
3968 // values on the stack where a match requires a value to
3969 // flow through memory.
3970 operand stackSlotI(sRegI reg) %{
3971 constraint(ALLOC_IN_RC(stack_slots));
3972 op_cost(100);
3973 //match(RegI);
3974 format %{ "[$reg]" %}
3975 interface(MEMORY_INTER) %{
3976 base(0xE); // R_SP
3977 index(0x0);
3978 scale(0x0);
3979 disp($reg); // Stack Offset
3980 %}
3981 %}
3983 operand stackSlotP(sRegP reg) %{
3984 constraint(ALLOC_IN_RC(stack_slots));
3985 op_cost(100);
3986 //match(RegP);
3987 format %{ "[$reg]" %}
3988 interface(MEMORY_INTER) %{
3989 base(0xE); // R_SP
3990 index(0x0);
3991 scale(0x0);
3992 disp($reg); // Stack Offset
3993 %}
3994 %}
3996 operand stackSlotF(sRegF reg) %{
3997 constraint(ALLOC_IN_RC(stack_slots));
3998 op_cost(100);
3999 //match(RegF);
4000 format %{ "[$reg]" %}
4001 interface(MEMORY_INTER) %{
4002 base(0xE); // R_SP
4003 index(0x0);
4004 scale(0x0);
4005 disp($reg); // Stack Offset
4006 %}
4007 %}
4008 operand stackSlotD(sRegD reg) %{
4009 constraint(ALLOC_IN_RC(stack_slots));
4010 op_cost(100);
4011 //match(RegD);
4012 format %{ "[$reg]" %}
4013 interface(MEMORY_INTER) %{
4014 base(0xE); // R_SP
4015 index(0x0);
4016 scale(0x0);
4017 disp($reg); // Stack Offset
4018 %}
4019 %}
4020 operand stackSlotL(sRegL reg) %{
4021 constraint(ALLOC_IN_RC(stack_slots));
4022 op_cost(100);
4023 //match(RegL);
4024 format %{ "[$reg]" %}
4025 interface(MEMORY_INTER) %{
4026 base(0xE); // R_SP
4027 index(0x0);
4028 scale(0x0);
4029 disp($reg); // Stack Offset
4030 %}
4031 %}
4033 // Operands for expressing Control Flow
4034 // NOTE: Label is a predefined operand which should not be redefined in
4035 // the AD file. It is generically handled within the ADLC.
4037 //----------Conditional Branch Operands----------------------------------------
4038 // Comparison Op - This is the operation of the comparison, and is limited to
4039 // the following set of codes:
4040 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4041 //
4042 // Other attributes of the comparison, such as unsignedness, are specified
4043 // by the comparison instruction that sets a condition code flags register.
4044 // That result is represented by a flags operand whose subtype is appropriate
4045 // to the unsignedness (etc.) of the comparison.
4046 //
4047 // Later, the instruction which matches both the Comparison Op (a Bool) and
4048 // the flags (produced by the Cmp) specifies the coding of the comparison op
4049 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4051 operand cmpOp() %{
4052 match(Bool);
4054 format %{ "" %}
4055 interface(COND_INTER) %{
4056 equal(0x1);
4057 not_equal(0x9);
4058 less(0x3);
4059 greater_equal(0xB);
4060 less_equal(0x2);
4061 greater(0xA);
4062 %}
4063 %}
4065 // Comparison Op, unsigned
4066 operand cmpOpU() %{
4067 match(Bool);
4069 format %{ "u" %}
4070 interface(COND_INTER) %{
4071 equal(0x1);
4072 not_equal(0x9);
4073 less(0x5);
4074 greater_equal(0xD);
4075 less_equal(0x4);
4076 greater(0xC);
4077 %}
4078 %}
4080 // Comparison Op, pointer (same as unsigned)
4081 operand cmpOpP() %{
4082 match(Bool);
4084 format %{ "p" %}
4085 interface(COND_INTER) %{
4086 equal(0x1);
4087 not_equal(0x9);
4088 less(0x5);
4089 greater_equal(0xD);
4090 less_equal(0x4);
4091 greater(0xC);
4092 %}
4093 %}
4095 // Comparison Op, branch-register encoding
4096 operand cmpOp_reg() %{
4097 match(Bool);
4099 format %{ "" %}
4100 interface(COND_INTER) %{
4101 equal (0x1);
4102 not_equal (0x5);
4103 less (0x3);
4104 greater_equal(0x7);
4105 less_equal (0x2);
4106 greater (0x6);
4107 %}
4108 %}
4110 // Comparison Code, floating, unordered same as less
4111 operand cmpOpF() %{
4112 match(Bool);
4114 format %{ "fl" %}
4115 interface(COND_INTER) %{
4116 equal(0x9);
4117 not_equal(0x1);
4118 less(0x3);
4119 greater_equal(0xB);
4120 less_equal(0xE);
4121 greater(0x6);
4122 %}
4123 %}
4125 // Used by long compare
4126 operand cmpOp_commute() %{
4127 match(Bool);
4129 format %{ "" %}
4130 interface(COND_INTER) %{
4131 equal(0x1);
4132 not_equal(0x9);
4133 less(0xA);
4134 greater_equal(0x2);
4135 less_equal(0xB);
4136 greater(0x3);
4137 %}
4138 %}
4140 //----------OPERAND CLASSES----------------------------------------------------
4141 // Operand Classes are groups of operands that are used to simplify
4142 // instruction definitions by not requiring the AD writer to specify seperate
4143 // instructions for every form of operand when the instruction accepts
4144 // multiple operand types with the same basic encoding and format. The classic
4145 // case of this is memory operands.
4146 // Indirect is not included since its use is limited to Compare & Swap
4147 opclass memory( indirect, indOffset13, indIndex );
4149 //----------PIPELINE-----------------------------------------------------------
4150 pipeline %{
4152 //----------ATTRIBUTES---------------------------------------------------------
4153 attributes %{
4154 fixed_size_instructions; // Fixed size instructions
4155 branch_has_delay_slot; // Branch has delay slot following
4156 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4157 instruction_unit_size = 4; // An instruction is 4 bytes long
4158 instruction_fetch_unit_size = 16; // The processor fetches one line
4159 instruction_fetch_units = 1; // of 16 bytes
4161 // List of nop instructions
4162 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4163 %}
4165 //----------RESOURCES----------------------------------------------------------
4166 // Resources are the functional units available to the machine
4167 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4169 //----------PIPELINE DESCRIPTION-----------------------------------------------
4170 // Pipeline Description specifies the stages in the machine's pipeline
4172 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4174 //----------PIPELINE CLASSES---------------------------------------------------
4175 // Pipeline Classes describe the stages in which input and output are
4176 // referenced by the hardware pipeline.
4178 // Integer ALU reg-reg operation
4179 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4180 single_instruction;
4181 dst : E(write);
4182 src1 : R(read);
4183 src2 : R(read);
4184 IALU : R;
4185 %}
4187 // Integer ALU reg-reg long operation
4188 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4189 instruction_count(2);
4190 dst : E(write);
4191 src1 : R(read);
4192 src2 : R(read);
4193 IALU : R;
4194 IALU : R;
4195 %}
4197 // Integer ALU reg-reg long dependent operation
4198 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4199 instruction_count(1); multiple_bundles;
4200 dst : E(write);
4201 src1 : R(read);
4202 src2 : R(read);
4203 cr : E(write);
4204 IALU : R(2);
4205 %}
4207 // Integer ALU reg-imm operaion
4208 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4209 single_instruction;
4210 dst : E(write);
4211 src1 : R(read);
4212 IALU : R;
4213 %}
4215 // Integer ALU reg-reg operation with condition code
4216 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4217 single_instruction;
4218 dst : E(write);
4219 cr : E(write);
4220 src1 : R(read);
4221 src2 : R(read);
4222 IALU : R;
4223 %}
4225 // Integer ALU reg-imm operation with condition code
4226 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4227 single_instruction;
4228 dst : E(write);
4229 cr : E(write);
4230 src1 : R(read);
4231 IALU : R;
4232 %}
4234 // Integer ALU zero-reg operation
4235 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4236 single_instruction;
4237 dst : E(write);
4238 src2 : R(read);
4239 IALU : R;
4240 %}
4242 // Integer ALU zero-reg operation with condition code only
4243 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4244 single_instruction;
4245 cr : E(write);
4246 src : R(read);
4247 IALU : R;
4248 %}
4250 // Integer ALU reg-reg operation with condition code only
4251 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4252 single_instruction;
4253 cr : E(write);
4254 src1 : R(read);
4255 src2 : R(read);
4256 IALU : R;
4257 %}
4259 // Integer ALU reg-imm operation with condition code only
4260 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4261 single_instruction;
4262 cr : E(write);
4263 src1 : R(read);
4264 IALU : R;
4265 %}
4267 // Integer ALU reg-reg-zero operation with condition code only
4268 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4269 single_instruction;
4270 cr : E(write);
4271 src1 : R(read);
4272 src2 : R(read);
4273 IALU : R;
4274 %}
4276 // Integer ALU reg-imm-zero operation with condition code only
4277 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4278 single_instruction;
4279 cr : E(write);
4280 src1 : R(read);
4281 IALU : R;
4282 %}
4284 // Integer ALU reg-reg operation with condition code, src1 modified
4285 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4286 single_instruction;
4287 cr : E(write);
4288 src1 : E(write);
4289 src1 : R(read);
4290 src2 : R(read);
4291 IALU : R;
4292 %}
4294 // Integer ALU reg-imm operation with condition code, src1 modified
4295 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4296 single_instruction;
4297 cr : E(write);
4298 src1 : E(write);
4299 src1 : R(read);
4300 IALU : R;
4301 %}
4303 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4304 multiple_bundles;
4305 dst : E(write)+4;
4306 cr : E(write);
4307 src1 : R(read);
4308 src2 : R(read);
4309 IALU : R(3);
4310 BR : R(2);
4311 %}
4313 // Integer ALU operation
4314 pipe_class ialu_none(iRegI dst) %{
4315 single_instruction;
4316 dst : E(write);
4317 IALU : R;
4318 %}
4320 // Integer ALU reg operation
4321 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4322 single_instruction; may_have_no_code;
4323 dst : E(write);
4324 src : R(read);
4325 IALU : R;
4326 %}
4328 // Integer ALU reg conditional operation
4329 // This instruction has a 1 cycle stall, and cannot execute
4330 // in the same cycle as the instruction setting the condition
4331 // code. We kludge this by pretending to read the condition code
4332 // 1 cycle earlier, and by marking the functional units as busy
4333 // for 2 cycles with the result available 1 cycle later than
4334 // is really the case.
4335 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4336 single_instruction;
4337 op2_out : C(write);
4338 op1 : R(read);
4339 cr : R(read); // This is really E, with a 1 cycle stall
4340 BR : R(2);
4341 MS : R(2);
4342 %}
4344 #ifdef _LP64
4345 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4346 instruction_count(1); multiple_bundles;
4347 dst : C(write)+1;
4348 src : R(read)+1;
4349 IALU : R(1);
4350 BR : E(2);
4351 MS : E(2);
4352 %}
4353 #endif
4355 // Integer ALU reg operation
4356 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4357 single_instruction; may_have_no_code;
4358 dst : E(write);
4359 src : R(read);
4360 IALU : R;
4361 %}
4362 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4363 single_instruction; may_have_no_code;
4364 dst : E(write);
4365 src : R(read);
4366 IALU : R;
4367 %}
4369 // Two integer ALU reg operations
4370 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4371 instruction_count(2);
4372 dst : E(write);
4373 src : R(read);
4374 A0 : R;
4375 A1 : R;
4376 %}
4378 // Two integer ALU reg operations
4379 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4380 instruction_count(2); may_have_no_code;
4381 dst : E(write);
4382 src : R(read);
4383 A0 : R;
4384 A1 : R;
4385 %}
4387 // Integer ALU imm operation
4388 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4389 single_instruction;
4390 dst : E(write);
4391 IALU : R;
4392 %}
4394 // Integer ALU reg-reg with carry operation
4395 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4396 single_instruction;
4397 dst : E(write);
4398 src1 : R(read);
4399 src2 : R(read);
4400 IALU : R;
4401 %}
4403 // Integer ALU cc operation
4404 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4405 single_instruction;
4406 dst : E(write);
4407 cc : R(read);
4408 IALU : R;
4409 %}
4411 // Integer ALU cc / second IALU operation
4412 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4413 instruction_count(1); multiple_bundles;
4414 dst : E(write)+1;
4415 src : R(read);
4416 IALU : R;
4417 %}
4419 // Integer ALU cc / second IALU operation
4420 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4421 instruction_count(1); multiple_bundles;
4422 dst : E(write)+1;
4423 p : R(read);
4424 q : R(read);
4425 IALU : R;
4426 %}
4428 // Integer ALU hi-lo-reg operation
4429 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4430 instruction_count(1); multiple_bundles;
4431 dst : E(write)+1;
4432 IALU : R(2);
4433 %}
4435 // Float ALU hi-lo-reg operation (with temp)
4436 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4437 instruction_count(1); multiple_bundles;
4438 dst : E(write)+1;
4439 IALU : R(2);
4440 %}
4442 // Long Constant
4443 pipe_class loadConL( iRegL dst, immL src ) %{
4444 instruction_count(2); multiple_bundles;
4445 dst : E(write)+1;
4446 IALU : R(2);
4447 IALU : R(2);
4448 %}
4450 // Pointer Constant
4451 pipe_class loadConP( iRegP dst, immP src ) %{
4452 instruction_count(0); multiple_bundles;
4453 fixed_latency(6);
4454 %}
4456 // Polling Address
4457 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4458 #ifdef _LP64
4459 instruction_count(0); multiple_bundles;
4460 fixed_latency(6);
4461 #else
4462 dst : E(write);
4463 IALU : R;
4464 #endif
4465 %}
4467 // Long Constant small
4468 pipe_class loadConLlo( iRegL dst, immL src ) %{
4469 instruction_count(2);
4470 dst : E(write);
4471 IALU : R;
4472 IALU : R;
4473 %}
4475 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4476 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4477 instruction_count(1); multiple_bundles;
4478 src : R(read);
4479 dst : M(write)+1;
4480 IALU : R;
4481 MS : E;
4482 %}
4484 // Integer ALU nop operation
4485 pipe_class ialu_nop() %{
4486 single_instruction;
4487 IALU : R;
4488 %}
4490 // Integer ALU nop operation
4491 pipe_class ialu_nop_A0() %{
4492 single_instruction;
4493 A0 : R;
4494 %}
4496 // Integer ALU nop operation
4497 pipe_class ialu_nop_A1() %{
4498 single_instruction;
4499 A1 : R;
4500 %}
4502 // Integer Multiply reg-reg operation
4503 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4504 single_instruction;
4505 dst : E(write);
4506 src1 : R(read);
4507 src2 : R(read);
4508 MS : R(5);
4509 %}
4511 // Integer Multiply reg-imm operation
4512 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4513 single_instruction;
4514 dst : E(write);
4515 src1 : R(read);
4516 MS : R(5);
4517 %}
4519 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4520 single_instruction;
4521 dst : E(write)+4;
4522 src1 : R(read);
4523 src2 : R(read);
4524 MS : R(6);
4525 %}
4527 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4528 single_instruction;
4529 dst : E(write)+4;
4530 src1 : R(read);
4531 MS : R(6);
4532 %}
4534 // Integer Divide reg-reg
4535 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4536 instruction_count(1); multiple_bundles;
4537 dst : E(write);
4538 temp : E(write);
4539 src1 : R(read);
4540 src2 : R(read);
4541 temp : R(read);
4542 MS : R(38);
4543 %}
4545 // Integer Divide reg-imm
4546 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4547 instruction_count(1); multiple_bundles;
4548 dst : E(write);
4549 temp : E(write);
4550 src1 : R(read);
4551 temp : R(read);
4552 MS : R(38);
4553 %}
4555 // Long Divide
4556 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4557 dst : E(write)+71;
4558 src1 : R(read);
4559 src2 : R(read)+1;
4560 MS : R(70);
4561 %}
4563 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4564 dst : E(write)+71;
4565 src1 : R(read);
4566 MS : R(70);
4567 %}
4569 // Floating Point Add Float
4570 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4571 single_instruction;
4572 dst : X(write);
4573 src1 : E(read);
4574 src2 : E(read);
4575 FA : R;
4576 %}
4578 // Floating Point Add Double
4579 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4580 single_instruction;
4581 dst : X(write);
4582 src1 : E(read);
4583 src2 : E(read);
4584 FA : R;
4585 %}
4587 // Floating Point Conditional Move based on integer flags
4588 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4589 single_instruction;
4590 dst : X(write);
4591 src : E(read);
4592 cr : R(read);
4593 FA : R(2);
4594 BR : R(2);
4595 %}
4597 // Floating Point Conditional Move based on integer flags
4598 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4599 single_instruction;
4600 dst : X(write);
4601 src : E(read);
4602 cr : R(read);
4603 FA : R(2);
4604 BR : R(2);
4605 %}
4607 // Floating Point Multiply Float
4608 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4609 single_instruction;
4610 dst : X(write);
4611 src1 : E(read);
4612 src2 : E(read);
4613 FM : R;
4614 %}
4616 // Floating Point Multiply Double
4617 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4618 single_instruction;
4619 dst : X(write);
4620 src1 : E(read);
4621 src2 : E(read);
4622 FM : R;
4623 %}
4625 // Floating Point Divide Float
4626 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4627 single_instruction;
4628 dst : X(write);
4629 src1 : E(read);
4630 src2 : E(read);
4631 FM : R;
4632 FDIV : C(14);
4633 %}
4635 // Floating Point Divide Double
4636 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4637 single_instruction;
4638 dst : X(write);
4639 src1 : E(read);
4640 src2 : E(read);
4641 FM : R;
4642 FDIV : C(17);
4643 %}
4645 // Floating Point Move/Negate/Abs Float
4646 pipe_class faddF_reg(regF dst, regF src) %{
4647 single_instruction;
4648 dst : W(write);
4649 src : E(read);
4650 FA : R(1);
4651 %}
4653 // Floating Point Move/Negate/Abs Double
4654 pipe_class faddD_reg(regD dst, regD src) %{
4655 single_instruction;
4656 dst : W(write);
4657 src : E(read);
4658 FA : R;
4659 %}
4661 // Floating Point Convert F->D
4662 pipe_class fcvtF2D(regD dst, regF src) %{
4663 single_instruction;
4664 dst : X(write);
4665 src : E(read);
4666 FA : R;
4667 %}
4669 // Floating Point Convert I->D
4670 pipe_class fcvtI2D(regD dst, regF src) %{
4671 single_instruction;
4672 dst : X(write);
4673 src : E(read);
4674 FA : R;
4675 %}
4677 // Floating Point Convert LHi->D
4678 pipe_class fcvtLHi2D(regD dst, regD src) %{
4679 single_instruction;
4680 dst : X(write);
4681 src : E(read);
4682 FA : R;
4683 %}
4685 // Floating Point Convert L->D
4686 pipe_class fcvtL2D(regD dst, regF src) %{
4687 single_instruction;
4688 dst : X(write);
4689 src : E(read);
4690 FA : R;
4691 %}
4693 // Floating Point Convert L->F
4694 pipe_class fcvtL2F(regD dst, regF src) %{
4695 single_instruction;
4696 dst : X(write);
4697 src : E(read);
4698 FA : R;
4699 %}
4701 // Floating Point Convert D->F
4702 pipe_class fcvtD2F(regD dst, regF src) %{
4703 single_instruction;
4704 dst : X(write);
4705 src : E(read);
4706 FA : R;
4707 %}
4709 // Floating Point Convert I->L
4710 pipe_class fcvtI2L(regD dst, regF src) %{
4711 single_instruction;
4712 dst : X(write);
4713 src : E(read);
4714 FA : R;
4715 %}
4717 // Floating Point Convert D->F
4718 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4719 instruction_count(1); multiple_bundles;
4720 dst : X(write)+6;
4721 src : E(read);
4722 FA : R;
4723 %}
4725 // Floating Point Convert D->L
4726 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4727 instruction_count(1); multiple_bundles;
4728 dst : X(write)+6;
4729 src : E(read);
4730 FA : R;
4731 %}
4733 // Floating Point Convert F->I
4734 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4735 instruction_count(1); multiple_bundles;
4736 dst : X(write)+6;
4737 src : E(read);
4738 FA : R;
4739 %}
4741 // Floating Point Convert F->L
4742 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4743 instruction_count(1); multiple_bundles;
4744 dst : X(write)+6;
4745 src : E(read);
4746 FA : R;
4747 %}
4749 // Floating Point Convert I->F
4750 pipe_class fcvtI2F(regF dst, regF src) %{
4751 single_instruction;
4752 dst : X(write);
4753 src : E(read);
4754 FA : R;
4755 %}
4757 // Floating Point Compare
4758 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4759 single_instruction;
4760 cr : X(write);
4761 src1 : E(read);
4762 src2 : E(read);
4763 FA : R;
4764 %}
4766 // Floating Point Compare
4767 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4768 single_instruction;
4769 cr : X(write);
4770 src1 : E(read);
4771 src2 : E(read);
4772 FA : R;
4773 %}
4775 // Floating Add Nop
4776 pipe_class fadd_nop() %{
4777 single_instruction;
4778 FA : R;
4779 %}
4781 // Integer Store to Memory
4782 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4783 single_instruction;
4784 mem : R(read);
4785 src : C(read);
4786 MS : R;
4787 %}
4789 // Integer Store to Memory
4790 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4791 single_instruction;
4792 mem : R(read);
4793 src : C(read);
4794 MS : R;
4795 %}
4797 // Integer Store Zero to Memory
4798 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4799 single_instruction;
4800 mem : R(read);
4801 MS : R;
4802 %}
4804 // Special Stack Slot Store
4805 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4806 single_instruction;
4807 stkSlot : R(read);
4808 src : C(read);
4809 MS : R;
4810 %}
4812 // Special Stack Slot Store
4813 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4814 instruction_count(2); multiple_bundles;
4815 stkSlot : R(read);
4816 src : C(read);
4817 MS : R(2);
4818 %}
4820 // Float Store
4821 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4822 single_instruction;
4823 mem : R(read);
4824 src : C(read);
4825 MS : R;
4826 %}
4828 // Float Store
4829 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4830 single_instruction;
4831 mem : R(read);
4832 MS : R;
4833 %}
4835 // Double Store
4836 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4837 instruction_count(1);
4838 mem : R(read);
4839 src : C(read);
4840 MS : R;
4841 %}
4843 // Double Store
4844 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
4845 single_instruction;
4846 mem : R(read);
4847 MS : R;
4848 %}
4850 // Special Stack Slot Float Store
4851 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
4852 single_instruction;
4853 stkSlot : R(read);
4854 src : C(read);
4855 MS : R;
4856 %}
4858 // Special Stack Slot Double Store
4859 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
4860 single_instruction;
4861 stkSlot : R(read);
4862 src : C(read);
4863 MS : R;
4864 %}
4866 // Integer Load (when sign bit propagation not needed)
4867 pipe_class iload_mem(iRegI dst, memory mem) %{
4868 single_instruction;
4869 mem : R(read);
4870 dst : C(write);
4871 MS : R;
4872 %}
4874 // Integer Load from stack operand
4875 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
4876 single_instruction;
4877 mem : R(read);
4878 dst : C(write);
4879 MS : R;
4880 %}
4882 // Integer Load (when sign bit propagation or masking is needed)
4883 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
4884 single_instruction;
4885 mem : R(read);
4886 dst : M(write);
4887 MS : R;
4888 %}
4890 // Float Load
4891 pipe_class floadF_mem(regF dst, memory mem) %{
4892 single_instruction;
4893 mem : R(read);
4894 dst : M(write);
4895 MS : R;
4896 %}
4898 // Float Load
4899 pipe_class floadD_mem(regD dst, memory mem) %{
4900 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
4901 mem : R(read);
4902 dst : M(write);
4903 MS : R;
4904 %}
4906 // Float Load
4907 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
4908 single_instruction;
4909 stkSlot : R(read);
4910 dst : M(write);
4911 MS : R;
4912 %}
4914 // Float Load
4915 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
4916 single_instruction;
4917 stkSlot : R(read);
4918 dst : M(write);
4919 MS : R;
4920 %}
4922 // Memory Nop
4923 pipe_class mem_nop() %{
4924 single_instruction;
4925 MS : R;
4926 %}
4928 pipe_class sethi(iRegP dst, immI src) %{
4929 single_instruction;
4930 dst : E(write);
4931 IALU : R;
4932 %}
4934 pipe_class loadPollP(iRegP poll) %{
4935 single_instruction;
4936 poll : R(read);
4937 MS : R;
4938 %}
4940 pipe_class br(Universe br, label labl) %{
4941 single_instruction_with_delay_slot;
4942 BR : R;
4943 %}
4945 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
4946 single_instruction_with_delay_slot;
4947 cr : E(read);
4948 BR : R;
4949 %}
4951 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
4952 single_instruction_with_delay_slot;
4953 op1 : E(read);
4954 BR : R;
4955 MS : R;
4956 %}
4958 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
4959 single_instruction_with_delay_slot;
4960 cr : E(read);
4961 BR : R;
4962 %}
4964 pipe_class br_nop() %{
4965 single_instruction;
4966 BR : R;
4967 %}
4969 pipe_class simple_call(method meth) %{
4970 instruction_count(2); multiple_bundles; force_serialization;
4971 fixed_latency(100);
4972 BR : R(1);
4973 MS : R(1);
4974 A0 : R(1);
4975 %}
4977 pipe_class compiled_call(method meth) %{
4978 instruction_count(1); multiple_bundles; force_serialization;
4979 fixed_latency(100);
4980 MS : R(1);
4981 %}
4983 pipe_class call(method meth) %{
4984 instruction_count(0); multiple_bundles; force_serialization;
4985 fixed_latency(100);
4986 %}
4988 pipe_class tail_call(Universe ignore, label labl) %{
4989 single_instruction; has_delay_slot;
4990 fixed_latency(100);
4991 BR : R(1);
4992 MS : R(1);
4993 %}
4995 pipe_class ret(Universe ignore) %{
4996 single_instruction; has_delay_slot;
4997 BR : R(1);
4998 MS : R(1);
4999 %}
5001 pipe_class ret_poll(g3RegP poll) %{
5002 instruction_count(3); has_delay_slot;
5003 poll : E(read);
5004 MS : R;
5005 %}
5007 // The real do-nothing guy
5008 pipe_class empty( ) %{
5009 instruction_count(0);
5010 %}
5012 pipe_class long_memory_op() %{
5013 instruction_count(0); multiple_bundles; force_serialization;
5014 fixed_latency(25);
5015 MS : R(1);
5016 %}
5018 // Check-cast
5019 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5020 array : R(read);
5021 match : R(read);
5022 IALU : R(2);
5023 BR : R(2);
5024 MS : R;
5025 %}
5027 // Convert FPU flags into +1,0,-1
5028 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5029 src1 : E(read);
5030 src2 : E(read);
5031 dst : E(write);
5032 FA : R;
5033 MS : R(2);
5034 BR : R(2);
5035 %}
5037 // Compare for p < q, and conditionally add y
5038 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5039 p : E(read);
5040 q : E(read);
5041 y : E(read);
5042 IALU : R(3)
5043 %}
5045 // Perform a compare, then move conditionally in a branch delay slot.
5046 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5047 src2 : E(read);
5048 srcdst : E(read);
5049 IALU : R;
5050 BR : R;
5051 %}
5053 // Define the class for the Nop node
5054 define %{
5055 MachNop = ialu_nop;
5056 %}
5058 %}
5060 //----------INSTRUCTIONS-------------------------------------------------------
5062 //------------Special Stack Slot instructions - no match rules-----------------
5063 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5064 // No match rule to avoid chain rule match.
5065 effect(DEF dst, USE src);
5066 ins_cost(MEMORY_REF_COST);
5067 size(4);
5068 format %{ "LDF $src,$dst\t! stkI to regF" %}
5069 opcode(Assembler::ldf_op3);
5070 ins_encode(simple_form3_mem_reg(src, dst));
5071 ins_pipe(floadF_stk);
5072 %}
5074 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5075 // No match rule to avoid chain rule match.
5076 effect(DEF dst, USE src);
5077 ins_cost(MEMORY_REF_COST);
5078 size(4);
5079 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5080 opcode(Assembler::lddf_op3);
5081 ins_encode(simple_form3_mem_reg(src, dst));
5082 ins_pipe(floadD_stk);
5083 %}
5085 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5086 // No match rule to avoid chain rule match.
5087 effect(DEF dst, USE src);
5088 ins_cost(MEMORY_REF_COST);
5089 size(4);
5090 format %{ "STF $src,$dst\t! regF to stkI" %}
5091 opcode(Assembler::stf_op3);
5092 ins_encode(simple_form3_mem_reg(dst, src));
5093 ins_pipe(fstoreF_stk_reg);
5094 %}
5096 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5097 // No match rule to avoid chain rule match.
5098 effect(DEF dst, USE src);
5099 ins_cost(MEMORY_REF_COST);
5100 size(4);
5101 format %{ "STDF $src,$dst\t! regD to stkL" %}
5102 opcode(Assembler::stdf_op3);
5103 ins_encode(simple_form3_mem_reg(dst, src));
5104 ins_pipe(fstoreD_stk_reg);
5105 %}
5107 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5108 effect(DEF dst, USE src);
5109 ins_cost(MEMORY_REF_COST*2);
5110 size(8);
5111 format %{ "STW $src,$dst.hi\t! long\n\t"
5112 "STW R_G0,$dst.lo" %}
5113 opcode(Assembler::stw_op3);
5114 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5115 ins_pipe(lstoreI_stk_reg);
5116 %}
5118 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5119 // No match rule to avoid chain rule match.
5120 effect(DEF dst, USE src);
5121 ins_cost(MEMORY_REF_COST);
5122 size(4);
5123 format %{ "STX $src,$dst\t! regL to stkD" %}
5124 opcode(Assembler::stx_op3);
5125 ins_encode(simple_form3_mem_reg( dst, src ) );
5126 ins_pipe(istore_stk_reg);
5127 %}
5129 //---------- Chain stack slots between similar types --------
5131 // Load integer from stack slot
5132 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5133 match(Set dst src);
5134 ins_cost(MEMORY_REF_COST);
5136 size(4);
5137 format %{ "LDUW $src,$dst\t!stk" %}
5138 opcode(Assembler::lduw_op3);
5139 ins_encode(simple_form3_mem_reg( src, dst ) );
5140 ins_pipe(iload_mem);
5141 %}
5143 // Store integer to stack slot
5144 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5145 match(Set dst src);
5146 ins_cost(MEMORY_REF_COST);
5148 size(4);
5149 format %{ "STW $src,$dst\t!stk" %}
5150 opcode(Assembler::stw_op3);
5151 ins_encode(simple_form3_mem_reg( dst, src ) );
5152 ins_pipe(istore_mem_reg);
5153 %}
5155 // Load long from stack slot
5156 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5157 match(Set dst src);
5159 ins_cost(MEMORY_REF_COST);
5160 size(4);
5161 format %{ "LDX $src,$dst\t! long" %}
5162 opcode(Assembler::ldx_op3);
5163 ins_encode(simple_form3_mem_reg( src, dst ) );
5164 ins_pipe(iload_mem);
5165 %}
5167 // Store long to stack slot
5168 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5169 match(Set dst src);
5171 ins_cost(MEMORY_REF_COST);
5172 size(4);
5173 format %{ "STX $src,$dst\t! long" %}
5174 opcode(Assembler::stx_op3);
5175 ins_encode(simple_form3_mem_reg( dst, src ) );
5176 ins_pipe(istore_mem_reg);
5177 %}
5179 #ifdef _LP64
5180 // Load pointer from stack slot, 64-bit encoding
5181 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5182 match(Set dst src);
5183 ins_cost(MEMORY_REF_COST);
5184 size(4);
5185 format %{ "LDX $src,$dst\t!ptr" %}
5186 opcode(Assembler::ldx_op3);
5187 ins_encode(simple_form3_mem_reg( src, dst ) );
5188 ins_pipe(iload_mem);
5189 %}
5191 // Store pointer to stack slot
5192 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5193 match(Set dst src);
5194 ins_cost(MEMORY_REF_COST);
5195 size(4);
5196 format %{ "STX $src,$dst\t!ptr" %}
5197 opcode(Assembler::stx_op3);
5198 ins_encode(simple_form3_mem_reg( dst, src ) );
5199 ins_pipe(istore_mem_reg);
5200 %}
5201 #else // _LP64
5202 // Load pointer from stack slot, 32-bit encoding
5203 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5204 match(Set dst src);
5205 ins_cost(MEMORY_REF_COST);
5206 format %{ "LDUW $src,$dst\t!ptr" %}
5207 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5208 ins_encode(simple_form3_mem_reg( src, dst ) );
5209 ins_pipe(iload_mem);
5210 %}
5212 // Store pointer to stack slot
5213 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5214 match(Set dst src);
5215 ins_cost(MEMORY_REF_COST);
5216 format %{ "STW $src,$dst\t!ptr" %}
5217 opcode(Assembler::stw_op3, Assembler::ldst_op);
5218 ins_encode(simple_form3_mem_reg( dst, src ) );
5219 ins_pipe(istore_mem_reg);
5220 %}
5221 #endif // _LP64
5223 //------------Special Nop instructions for bundling - no match rules-----------
5224 // Nop using the A0 functional unit
5225 instruct Nop_A0() %{
5226 ins_cost(0);
5228 format %{ "NOP ! Alu Pipeline" %}
5229 opcode(Assembler::or_op3, Assembler::arith_op);
5230 ins_encode( form2_nop() );
5231 ins_pipe(ialu_nop_A0);
5232 %}
5234 // Nop using the A1 functional unit
5235 instruct Nop_A1( ) %{
5236 ins_cost(0);
5238 format %{ "NOP ! Alu Pipeline" %}
5239 opcode(Assembler::or_op3, Assembler::arith_op);
5240 ins_encode( form2_nop() );
5241 ins_pipe(ialu_nop_A1);
5242 %}
5244 // Nop using the memory functional unit
5245 instruct Nop_MS( ) %{
5246 ins_cost(0);
5248 format %{ "NOP ! Memory Pipeline" %}
5249 ins_encode( emit_mem_nop );
5250 ins_pipe(mem_nop);
5251 %}
5253 // Nop using the floating add functional unit
5254 instruct Nop_FA( ) %{
5255 ins_cost(0);
5257 format %{ "NOP ! Floating Add Pipeline" %}
5258 ins_encode( emit_fadd_nop );
5259 ins_pipe(fadd_nop);
5260 %}
5262 // Nop using the branch functional unit
5263 instruct Nop_BR( ) %{
5264 ins_cost(0);
5266 format %{ "NOP ! Branch Pipeline" %}
5267 ins_encode( emit_br_nop );
5268 ins_pipe(br_nop);
5269 %}
5271 //----------Load/Store/Move Instructions---------------------------------------
5272 //----------Load Instructions--------------------------------------------------
5273 // Load Byte (8bit signed)
5274 instruct loadB(iRegI dst, memory mem) %{
5275 match(Set dst (LoadB mem));
5276 ins_cost(MEMORY_REF_COST);
5278 size(4);
5279 format %{ "LDSB $mem,$dst" %}
5280 opcode(Assembler::ldsb_op3);
5281 ins_encode(simple_form3_mem_reg( mem, dst ) );
5282 ins_pipe(iload_mask_mem);
5283 %}
5285 // Load Byte (8bit UNsigned) into an int reg
5286 instruct loadUB(iRegI dst, memory mem, immI_255 bytemask) %{
5287 match(Set dst (AndI (LoadB mem) bytemask));
5288 ins_cost(MEMORY_REF_COST);
5290 size(4);
5291 format %{ "LDUB $mem,$dst" %}
5292 opcode(Assembler::ldub_op3);
5293 ins_encode(simple_form3_mem_reg( mem, dst ) );
5294 ins_pipe(iload_mask_mem);
5295 %}
5297 // Load Byte (8bit UNsigned) into a Long Register
5298 instruct loadUBL(iRegL dst, memory mem, immL_FF bytemask) %{
5299 match(Set dst (AndL (ConvI2L (LoadB mem)) bytemask));
5300 ins_cost(MEMORY_REF_COST);
5302 size(4);
5303 format %{ "LDUB $mem,$dst" %}
5304 opcode(Assembler::ldub_op3);
5305 ins_encode(simple_form3_mem_reg( mem, dst ) );
5306 ins_pipe(iload_mask_mem);
5307 %}
5309 // Load Char (16bit UNsigned) into a Long Register
5310 instruct loadUCL(iRegL dst, memory mem, immL_FFFF bytemask) %{
5311 match(Set dst (AndL (ConvI2L (LoadC mem)) bytemask));
5312 ins_cost(MEMORY_REF_COST);
5314 size(4);
5315 format %{ "LDUH $mem,$dst" %}
5316 opcode(Assembler::lduh_op3);
5317 ins_encode(simple_form3_mem_reg( mem, dst ) );
5318 ins_pipe(iload_mask_mem);
5319 %}
5321 // Load Char (16bit unsigned)
5322 instruct loadC(iRegI dst, memory mem) %{
5323 match(Set dst (LoadC mem));
5324 ins_cost(MEMORY_REF_COST);
5326 size(4);
5327 format %{ "LDUH $mem,$dst" %}
5328 opcode(Assembler::lduh_op3);
5329 ins_encode(simple_form3_mem_reg( mem, dst ) );
5330 ins_pipe(iload_mask_mem);
5331 %}
5333 // Load Integer
5334 instruct loadI(iRegI dst, memory mem) %{
5335 match(Set dst (LoadI mem));
5336 ins_cost(MEMORY_REF_COST);
5337 size(4);
5339 format %{ "LDUW $mem,$dst" %}
5340 opcode(Assembler::lduw_op3);
5341 ins_encode(simple_form3_mem_reg( mem, dst ) );
5342 ins_pipe(iload_mem);
5343 %}
5345 // Load Long - aligned
5346 instruct loadL(iRegL dst, memory mem ) %{
5347 match(Set dst (LoadL mem));
5348 ins_cost(MEMORY_REF_COST);
5349 size(4);
5350 format %{ "LDX $mem,$dst\t! long" %}
5351 opcode(Assembler::ldx_op3);
5352 ins_encode(simple_form3_mem_reg( mem, dst ) );
5353 ins_pipe(iload_mem);
5354 %}
5356 // Load Long - UNaligned
5357 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5358 match(Set dst (LoadL_unaligned mem));
5359 effect(KILL tmp);
5360 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5361 size(16);
5362 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5363 "\tLDUW $mem ,$dst\n"
5364 "\tSLLX #32, $dst, $dst\n"
5365 "\tOR $dst, R_O7, $dst" %}
5366 opcode(Assembler::lduw_op3);
5367 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5368 ins_pipe(iload_mem);
5369 %}
5371 // Load Aligned Packed Byte into a Double Register
5372 instruct loadA8B(regD dst, memory mem) %{
5373 match(Set dst (Load8B mem));
5374 ins_cost(MEMORY_REF_COST);
5375 size(4);
5376 format %{ "LDDF $mem,$dst\t! packed8B" %}
5377 opcode(Assembler::lddf_op3);
5378 ins_encode(simple_form3_mem_reg( mem, dst ) );
5379 ins_pipe(floadD_mem);
5380 %}
5382 // Load Aligned Packed Char into a Double Register
5383 instruct loadA4C(regD dst, memory mem) %{
5384 match(Set dst (Load4C mem));
5385 ins_cost(MEMORY_REF_COST);
5386 size(4);
5387 format %{ "LDDF $mem,$dst\t! packed4C" %}
5388 opcode(Assembler::lddf_op3);
5389 ins_encode(simple_form3_mem_reg( mem, dst ) );
5390 ins_pipe(floadD_mem);
5391 %}
5393 // Load Aligned Packed Short into a Double Register
5394 instruct loadA4S(regD dst, memory mem) %{
5395 match(Set dst (Load4S mem));
5396 ins_cost(MEMORY_REF_COST);
5397 size(4);
5398 format %{ "LDDF $mem,$dst\t! packed4S" %}
5399 opcode(Assembler::lddf_op3);
5400 ins_encode(simple_form3_mem_reg( mem, dst ) );
5401 ins_pipe(floadD_mem);
5402 %}
5404 // Load Aligned Packed Int into a Double Register
5405 instruct loadA2I(regD dst, memory mem) %{
5406 match(Set dst (Load2I mem));
5407 ins_cost(MEMORY_REF_COST);
5408 size(4);
5409 format %{ "LDDF $mem,$dst\t! packed2I" %}
5410 opcode(Assembler::lddf_op3);
5411 ins_encode(simple_form3_mem_reg( mem, dst ) );
5412 ins_pipe(floadD_mem);
5413 %}
5415 // Load Range
5416 instruct loadRange(iRegI dst, memory mem) %{
5417 match(Set dst (LoadRange mem));
5418 ins_cost(MEMORY_REF_COST);
5420 size(4);
5421 format %{ "LDUW $mem,$dst\t! range" %}
5422 opcode(Assembler::lduw_op3);
5423 ins_encode(simple_form3_mem_reg( mem, dst ) );
5424 ins_pipe(iload_mem);
5425 %}
5427 // Load Integer into %f register (for fitos/fitod)
5428 instruct loadI_freg(regF dst, memory mem) %{
5429 match(Set dst (LoadI mem));
5430 ins_cost(MEMORY_REF_COST);
5431 size(4);
5433 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5434 opcode(Assembler::ldf_op3);
5435 ins_encode(simple_form3_mem_reg( mem, dst ) );
5436 ins_pipe(floadF_mem);
5437 %}
5439 // Load Pointer
5440 instruct loadP(iRegP dst, memory mem) %{
5441 match(Set dst (LoadP mem));
5442 ins_cost(MEMORY_REF_COST);
5443 size(4);
5445 #ifndef _LP64
5446 format %{ "LDUW $mem,$dst\t! ptr" %}
5447 opcode(Assembler::lduw_op3, 0, REGP_OP);
5448 #else
5449 format %{ "LDX $mem,$dst\t! ptr" %}
5450 opcode(Assembler::ldx_op3, 0, REGP_OP);
5451 #endif
5452 ins_encode( form3_mem_reg( mem, dst ) );
5453 ins_pipe(iload_mem);
5454 %}
5456 // Load Compressed Pointer
5457 instruct loadN(iRegN dst, memory mem) %{
5458 match(Set dst (LoadN mem));
5459 ins_cost(MEMORY_REF_COST);
5460 size(4);
5462 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5463 ins_encode %{
5464 Register base = as_Register($mem$$base);
5465 Register index = as_Register($mem$$index);
5466 Register dst = $dst$$Register;
5467 if (index != G0) {
5468 __ lduw(base, index, dst);
5469 } else {
5470 __ lduw(base, $mem$$disp, dst);
5471 }
5472 %}
5473 ins_pipe(iload_mem);
5474 %}
5476 // Load Klass Pointer
5477 instruct loadKlass(iRegP dst, memory mem) %{
5478 match(Set dst (LoadKlass mem));
5479 ins_cost(MEMORY_REF_COST);
5480 size(4);
5482 #ifndef _LP64
5483 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5484 opcode(Assembler::lduw_op3, 0, REGP_OP);
5485 #else
5486 format %{ "LDX $mem,$dst\t! klass ptr" %}
5487 opcode(Assembler::ldx_op3, 0, REGP_OP);
5488 #endif
5489 ins_encode( form3_mem_reg( mem, dst ) );
5490 ins_pipe(iload_mem);
5491 %}
5493 // Load narrow Klass Pointer
5494 instruct loadNKlass(iRegN dst, memory mem) %{
5495 match(Set dst (LoadNKlass mem));
5496 ins_cost(MEMORY_REF_COST);
5497 size(4);
5499 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5501 ins_encode %{
5502 Register base = as_Register($mem$$base);
5503 Register index = as_Register($mem$$index);
5504 Register dst = $dst$$Register;
5505 if (index != G0) {
5506 __ lduw(base, index, dst);
5507 } else {
5508 __ lduw(base, $mem$$disp, dst);
5509 }
5510 %}
5511 ins_pipe(iload_mem);
5512 %}
5514 // Load Short (16bit signed)
5515 instruct loadS(iRegI dst, memory mem) %{
5516 match(Set dst (LoadS mem));
5517 ins_cost(MEMORY_REF_COST);
5519 size(4);
5520 format %{ "LDSH $mem,$dst" %}
5521 opcode(Assembler::ldsh_op3);
5522 ins_encode(simple_form3_mem_reg( mem, dst ) );
5523 ins_pipe(iload_mask_mem);
5524 %}
5526 // Load Double
5527 instruct loadD(regD dst, memory mem) %{
5528 match(Set dst (LoadD mem));
5529 ins_cost(MEMORY_REF_COST);
5531 size(4);
5532 format %{ "LDDF $mem,$dst" %}
5533 opcode(Assembler::lddf_op3);
5534 ins_encode(simple_form3_mem_reg( mem, dst ) );
5535 ins_pipe(floadD_mem);
5536 %}
5538 // Load Double - UNaligned
5539 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5540 match(Set dst (LoadD_unaligned mem));
5541 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5542 size(8);
5543 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5544 "\tLDF $mem+4,$dst.lo\t!" %}
5545 opcode(Assembler::ldf_op3);
5546 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5547 ins_pipe(iload_mem);
5548 %}
5550 // Load Float
5551 instruct loadF(regF dst, memory mem) %{
5552 match(Set dst (LoadF mem));
5553 ins_cost(MEMORY_REF_COST);
5555 size(4);
5556 format %{ "LDF $mem,$dst" %}
5557 opcode(Assembler::ldf_op3);
5558 ins_encode(simple_form3_mem_reg( mem, dst ) );
5559 ins_pipe(floadF_mem);
5560 %}
5562 // Load Constant
5563 instruct loadConI( iRegI dst, immI src ) %{
5564 match(Set dst src);
5565 ins_cost(DEFAULT_COST * 3/2);
5566 format %{ "SET $src,$dst" %}
5567 ins_encode( Set32(src, dst) );
5568 ins_pipe(ialu_hi_lo_reg);
5569 %}
5571 instruct loadConI13( iRegI dst, immI13 src ) %{
5572 match(Set dst src);
5574 size(4);
5575 format %{ "MOV $src,$dst" %}
5576 ins_encode( Set13( src, dst ) );
5577 ins_pipe(ialu_imm);
5578 %}
5580 instruct loadConP(iRegP dst, immP src) %{
5581 match(Set dst src);
5582 ins_cost(DEFAULT_COST * 3/2);
5583 format %{ "SET $src,$dst\t!ptr" %}
5584 // This rule does not use "expand" unlike loadConI because then
5585 // the result type is not known to be an Oop. An ADLC
5586 // enhancement will be needed to make that work - not worth it!
5588 ins_encode( SetPtr( src, dst ) );
5589 ins_pipe(loadConP);
5591 %}
5593 instruct loadConP0(iRegP dst, immP0 src) %{
5594 match(Set dst src);
5596 size(4);
5597 format %{ "CLR $dst\t!ptr" %}
5598 ins_encode( SetNull( dst ) );
5599 ins_pipe(ialu_imm);
5600 %}
5602 instruct loadConP_poll(iRegP dst, immP_poll src) %{
5603 match(Set dst src);
5604 ins_cost(DEFAULT_COST);
5605 format %{ "SET $src,$dst\t!ptr" %}
5606 ins_encode %{
5607 Address polling_page(reg_to_register_object($dst$$reg), (address)os::get_polling_page());
5608 __ sethi(polling_page, false );
5609 %}
5610 ins_pipe(loadConP_poll);
5611 %}
5613 instruct loadConN0(iRegN dst, immN0 src) %{
5614 match(Set dst src);
5616 size(4);
5617 format %{ "CLR $dst\t! compressed NULL ptr" %}
5618 ins_encode( SetNull( dst ) );
5619 ins_pipe(ialu_imm);
5620 %}
5622 instruct loadConN(iRegN dst, immN src) %{
5623 match(Set dst src);
5624 ins_cost(DEFAULT_COST * 3/2);
5625 format %{ "SET $src,$dst\t! compressed ptr" %}
5626 ins_encode %{
5627 Register dst = $dst$$Register;
5628 __ set_narrow_oop((jobject)$src$$constant, dst);
5629 %}
5630 ins_pipe(ialu_hi_lo_reg);
5631 %}
5633 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{
5634 // %%% maybe this should work like loadConD
5635 match(Set dst src);
5636 effect(KILL tmp);
5637 ins_cost(DEFAULT_COST * 4);
5638 format %{ "SET64 $src,$dst KILL $tmp\t! long" %}
5639 ins_encode( LdImmL(src, dst, tmp) );
5640 ins_pipe(loadConL);
5641 %}
5643 instruct loadConL0( iRegL dst, immL0 src ) %{
5644 match(Set dst src);
5645 ins_cost(DEFAULT_COST);
5646 size(4);
5647 format %{ "CLR $dst\t! long" %}
5648 ins_encode( Set13( src, dst ) );
5649 ins_pipe(ialu_imm);
5650 %}
5652 instruct loadConL13( iRegL dst, immL13 src ) %{
5653 match(Set dst src);
5654 ins_cost(DEFAULT_COST * 2);
5656 size(4);
5657 format %{ "MOV $src,$dst\t! long" %}
5658 ins_encode( Set13( src, dst ) );
5659 ins_pipe(ialu_imm);
5660 %}
5662 instruct loadConF(regF dst, immF src, o7RegP tmp) %{
5663 match(Set dst src);
5664 effect(KILL tmp);
5666 #ifdef _LP64
5667 size(36);
5668 #else
5669 size(8);
5670 #endif
5672 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t"
5673 "LDF [$tmp+lo(&$src)],$dst" %}
5674 ins_encode( LdImmF(src, dst, tmp) );
5675 ins_pipe(loadConFD);
5676 %}
5678 instruct loadConD(regD dst, immD src, o7RegP tmp) %{
5679 match(Set dst src);
5680 effect(KILL tmp);
5682 #ifdef _LP64
5683 size(36);
5684 #else
5685 size(8);
5686 #endif
5688 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t"
5689 "LDDF [$tmp+lo(&$src)],$dst" %}
5690 ins_encode( LdImmD(src, dst, tmp) );
5691 ins_pipe(loadConFD);
5692 %}
5694 // Prefetch instructions.
5695 // Must be safe to execute with invalid address (cannot fault).
5697 instruct prefetchr( memory mem ) %{
5698 match( PrefetchRead mem );
5699 ins_cost(MEMORY_REF_COST);
5701 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
5702 opcode(Assembler::prefetch_op3);
5703 ins_encode( form3_mem_prefetch_read( mem ) );
5704 ins_pipe(iload_mem);
5705 %}
5707 instruct prefetchw( memory mem ) %{
5708 match( PrefetchWrite mem );
5709 ins_cost(MEMORY_REF_COST);
5711 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
5712 opcode(Assembler::prefetch_op3);
5713 ins_encode( form3_mem_prefetch_write( mem ) );
5714 ins_pipe(iload_mem);
5715 %}
5718 //----------Store Instructions-------------------------------------------------
5719 // Store Byte
5720 instruct storeB(memory mem, iRegI src) %{
5721 match(Set mem (StoreB mem src));
5722 ins_cost(MEMORY_REF_COST);
5724 size(4);
5725 format %{ "STB $src,$mem\t! byte" %}
5726 opcode(Assembler::stb_op3);
5727 ins_encode(simple_form3_mem_reg( mem, src ) );
5728 ins_pipe(istore_mem_reg);
5729 %}
5731 instruct storeB0(memory mem, immI0 src) %{
5732 match(Set mem (StoreB mem src));
5733 ins_cost(MEMORY_REF_COST);
5735 size(4);
5736 format %{ "STB $src,$mem\t! byte" %}
5737 opcode(Assembler::stb_op3);
5738 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5739 ins_pipe(istore_mem_zero);
5740 %}
5742 instruct storeCM0(memory mem, immI0 src) %{
5743 match(Set mem (StoreCM mem src));
5744 ins_cost(MEMORY_REF_COST);
5746 size(4);
5747 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
5748 opcode(Assembler::stb_op3);
5749 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5750 ins_pipe(istore_mem_zero);
5751 %}
5753 // Store Char/Short
5754 instruct storeC(memory mem, iRegI src) %{
5755 match(Set mem (StoreC mem src));
5756 ins_cost(MEMORY_REF_COST);
5758 size(4);
5759 format %{ "STH $src,$mem\t! short" %}
5760 opcode(Assembler::sth_op3);
5761 ins_encode(simple_form3_mem_reg( mem, src ) );
5762 ins_pipe(istore_mem_reg);
5763 %}
5765 instruct storeC0(memory mem, immI0 src) %{
5766 match(Set mem (StoreC mem src));
5767 ins_cost(MEMORY_REF_COST);
5769 size(4);
5770 format %{ "STH $src,$mem\t! short" %}
5771 opcode(Assembler::sth_op3);
5772 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5773 ins_pipe(istore_mem_zero);
5774 %}
5776 // Store Integer
5777 instruct storeI(memory mem, iRegI src) %{
5778 match(Set mem (StoreI mem src));
5779 ins_cost(MEMORY_REF_COST);
5781 size(4);
5782 format %{ "STW $src,$mem" %}
5783 opcode(Assembler::stw_op3);
5784 ins_encode(simple_form3_mem_reg( mem, src ) );
5785 ins_pipe(istore_mem_reg);
5786 %}
5788 // Store Long
5789 instruct storeL(memory mem, iRegL src) %{
5790 match(Set mem (StoreL mem src));
5791 ins_cost(MEMORY_REF_COST);
5792 size(4);
5793 format %{ "STX $src,$mem\t! long" %}
5794 opcode(Assembler::stx_op3);
5795 ins_encode(simple_form3_mem_reg( mem, src ) );
5796 ins_pipe(istore_mem_reg);
5797 %}
5799 instruct storeI0(memory mem, immI0 src) %{
5800 match(Set mem (StoreI mem src));
5801 ins_cost(MEMORY_REF_COST);
5803 size(4);
5804 format %{ "STW $src,$mem" %}
5805 opcode(Assembler::stw_op3);
5806 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5807 ins_pipe(istore_mem_zero);
5808 %}
5810 instruct storeL0(memory mem, immL0 src) %{
5811 match(Set mem (StoreL mem src));
5812 ins_cost(MEMORY_REF_COST);
5814 size(4);
5815 format %{ "STX $src,$mem" %}
5816 opcode(Assembler::stx_op3);
5817 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5818 ins_pipe(istore_mem_zero);
5819 %}
5821 // Store Integer from float register (used after fstoi)
5822 instruct storeI_Freg(memory mem, regF src) %{
5823 match(Set mem (StoreI mem src));
5824 ins_cost(MEMORY_REF_COST);
5826 size(4);
5827 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
5828 opcode(Assembler::stf_op3);
5829 ins_encode(simple_form3_mem_reg( mem, src ) );
5830 ins_pipe(fstoreF_mem_reg);
5831 %}
5833 // Store Pointer
5834 instruct storeP(memory dst, sp_ptr_RegP src) %{
5835 match(Set dst (StoreP dst src));
5836 ins_cost(MEMORY_REF_COST);
5837 size(4);
5839 #ifndef _LP64
5840 format %{ "STW $src,$dst\t! ptr" %}
5841 opcode(Assembler::stw_op3, 0, REGP_OP);
5842 #else
5843 format %{ "STX $src,$dst\t! ptr" %}
5844 opcode(Assembler::stx_op3, 0, REGP_OP);
5845 #endif
5846 ins_encode( form3_mem_reg( dst, src ) );
5847 ins_pipe(istore_mem_spORreg);
5848 %}
5850 instruct storeP0(memory dst, immP0 src) %{
5851 match(Set dst (StoreP dst src));
5852 ins_cost(MEMORY_REF_COST);
5853 size(4);
5855 #ifndef _LP64
5856 format %{ "STW $src,$dst\t! ptr" %}
5857 opcode(Assembler::stw_op3, 0, REGP_OP);
5858 #else
5859 format %{ "STX $src,$dst\t! ptr" %}
5860 opcode(Assembler::stx_op3, 0, REGP_OP);
5861 #endif
5862 ins_encode( form3_mem_reg( dst, R_G0 ) );
5863 ins_pipe(istore_mem_zero);
5864 %}
5866 // Store Compressed Pointer
5867 instruct storeN(memory dst, iRegN src) %{
5868 match(Set dst (StoreN dst src));
5869 ins_cost(MEMORY_REF_COST);
5870 size(4);
5872 format %{ "STW $src,$dst\t! compressed ptr" %}
5873 ins_encode %{
5874 Register base = as_Register($dst$$base);
5875 Register index = as_Register($dst$$index);
5876 Register src = $src$$Register;
5877 if (index != G0) {
5878 __ stw(src, base, index);
5879 } else {
5880 __ stw(src, base, $dst$$disp);
5881 }
5882 %}
5883 ins_pipe(istore_mem_spORreg);
5884 %}
5886 instruct storeN0(memory dst, immN0 src) %{
5887 match(Set dst (StoreN dst src));
5888 ins_cost(MEMORY_REF_COST);
5889 size(4);
5891 format %{ "STW $src,$dst\t! compressed ptr" %}
5892 ins_encode %{
5893 Register base = as_Register($dst$$base);
5894 Register index = as_Register($dst$$index);
5895 if (index != G0) {
5896 __ stw(0, base, index);
5897 } else {
5898 __ stw(0, base, $dst$$disp);
5899 }
5900 %}
5901 ins_pipe(istore_mem_zero);
5902 %}
5904 // Store Double
5905 instruct storeD( memory mem, regD src) %{
5906 match(Set mem (StoreD mem src));
5907 ins_cost(MEMORY_REF_COST);
5909 size(4);
5910 format %{ "STDF $src,$mem" %}
5911 opcode(Assembler::stdf_op3);
5912 ins_encode(simple_form3_mem_reg( mem, src ) );
5913 ins_pipe(fstoreD_mem_reg);
5914 %}
5916 instruct storeD0( memory mem, immD0 src) %{
5917 match(Set mem (StoreD mem src));
5918 ins_cost(MEMORY_REF_COST);
5920 size(4);
5921 format %{ "STX $src,$mem" %}
5922 opcode(Assembler::stx_op3);
5923 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5924 ins_pipe(fstoreD_mem_zero);
5925 %}
5927 // Store Float
5928 instruct storeF( memory mem, regF src) %{
5929 match(Set mem (StoreF mem src));
5930 ins_cost(MEMORY_REF_COST);
5932 size(4);
5933 format %{ "STF $src,$mem" %}
5934 opcode(Assembler::stf_op3);
5935 ins_encode(simple_form3_mem_reg( mem, src ) );
5936 ins_pipe(fstoreF_mem_reg);
5937 %}
5939 instruct storeF0( memory mem, immF0 src) %{
5940 match(Set mem (StoreF mem src));
5941 ins_cost(MEMORY_REF_COST);
5943 size(4);
5944 format %{ "STW $src,$mem\t! storeF0" %}
5945 opcode(Assembler::stw_op3);
5946 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
5947 ins_pipe(fstoreF_mem_zero);
5948 %}
5950 // Store Aligned Packed Bytes in Double register to memory
5951 instruct storeA8B(memory mem, regD src) %{
5952 match(Set mem (Store8B mem src));
5953 ins_cost(MEMORY_REF_COST);
5954 size(4);
5955 format %{ "STDF $src,$mem\t! packed8B" %}
5956 opcode(Assembler::stdf_op3);
5957 ins_encode(simple_form3_mem_reg( mem, src ) );
5958 ins_pipe(fstoreD_mem_reg);
5959 %}
5961 // Convert oop pointer into compressed form
5962 instruct encodeHeapOop(iRegN dst, iRegP src) %{
5963 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
5964 match(Set dst (EncodeP src));
5965 format %{ "encode_heap_oop $src, $dst" %}
5966 ins_encode %{
5967 __ encode_heap_oop($src$$Register, $dst$$Register);
5968 %}
5969 ins_pipe(ialu_reg);
5970 %}
5972 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
5973 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
5974 match(Set dst (EncodeP src));
5975 format %{ "encode_heap_oop_not_null $src, $dst" %}
5976 ins_encode %{
5977 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
5978 %}
5979 ins_pipe(ialu_reg);
5980 %}
5982 instruct decodeHeapOop(iRegP dst, iRegN src) %{
5983 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
5984 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
5985 match(Set dst (DecodeN src));
5986 format %{ "decode_heap_oop $src, $dst" %}
5987 ins_encode %{
5988 __ decode_heap_oop($src$$Register, $dst$$Register);
5989 %}
5990 ins_pipe(ialu_reg);
5991 %}
5993 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
5994 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
5995 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
5996 match(Set dst (DecodeN src));
5997 format %{ "decode_heap_oop_not_null $src, $dst" %}
5998 ins_encode %{
5999 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6000 %}
6001 ins_pipe(ialu_reg);
6002 %}
6005 // Store Zero into Aligned Packed Bytes
6006 instruct storeA8B0(memory mem, immI0 zero) %{
6007 match(Set mem (Store8B mem zero));
6008 ins_cost(MEMORY_REF_COST);
6009 size(4);
6010 format %{ "STX $zero,$mem\t! packed8B" %}
6011 opcode(Assembler::stx_op3);
6012 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6013 ins_pipe(fstoreD_mem_zero);
6014 %}
6016 // Store Aligned Packed Chars/Shorts in Double register to memory
6017 instruct storeA4C(memory mem, regD src) %{
6018 match(Set mem (Store4C mem src));
6019 ins_cost(MEMORY_REF_COST);
6020 size(4);
6021 format %{ "STDF $src,$mem\t! packed4C" %}
6022 opcode(Assembler::stdf_op3);
6023 ins_encode(simple_form3_mem_reg( mem, src ) );
6024 ins_pipe(fstoreD_mem_reg);
6025 %}
6027 // Store Zero into Aligned Packed Chars/Shorts
6028 instruct storeA4C0(memory mem, immI0 zero) %{
6029 match(Set mem (Store4C mem (Replicate4C zero)));
6030 ins_cost(MEMORY_REF_COST);
6031 size(4);
6032 format %{ "STX $zero,$mem\t! packed4C" %}
6033 opcode(Assembler::stx_op3);
6034 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6035 ins_pipe(fstoreD_mem_zero);
6036 %}
6038 // Store Aligned Packed Ints in Double register to memory
6039 instruct storeA2I(memory mem, regD src) %{
6040 match(Set mem (Store2I mem src));
6041 ins_cost(MEMORY_REF_COST);
6042 size(4);
6043 format %{ "STDF $src,$mem\t! packed2I" %}
6044 opcode(Assembler::stdf_op3);
6045 ins_encode(simple_form3_mem_reg( mem, src ) );
6046 ins_pipe(fstoreD_mem_reg);
6047 %}
6049 // Store Zero into Aligned Packed Ints
6050 instruct storeA2I0(memory mem, immI0 zero) %{
6051 match(Set mem (Store2I mem zero));
6052 ins_cost(MEMORY_REF_COST);
6053 size(4);
6054 format %{ "STX $zero,$mem\t! packed2I" %}
6055 opcode(Assembler::stx_op3);
6056 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6057 ins_pipe(fstoreD_mem_zero);
6058 %}
6061 //----------MemBar Instructions-----------------------------------------------
6062 // Memory barrier flavors
6064 instruct membar_acquire() %{
6065 match(MemBarAcquire);
6066 ins_cost(4*MEMORY_REF_COST);
6068 size(0);
6069 format %{ "MEMBAR-acquire" %}
6070 ins_encode( enc_membar_acquire );
6071 ins_pipe(long_memory_op);
6072 %}
6074 instruct membar_acquire_lock() %{
6075 match(MemBarAcquire);
6076 predicate(Matcher::prior_fast_lock(n));
6077 ins_cost(0);
6079 size(0);
6080 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6081 ins_encode( );
6082 ins_pipe(empty);
6083 %}
6085 instruct membar_release() %{
6086 match(MemBarRelease);
6087 ins_cost(4*MEMORY_REF_COST);
6089 size(0);
6090 format %{ "MEMBAR-release" %}
6091 ins_encode( enc_membar_release );
6092 ins_pipe(long_memory_op);
6093 %}
6095 instruct membar_release_lock() %{
6096 match(MemBarRelease);
6097 predicate(Matcher::post_fast_unlock(n));
6098 ins_cost(0);
6100 size(0);
6101 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6102 ins_encode( );
6103 ins_pipe(empty);
6104 %}
6106 instruct membar_volatile() %{
6107 match(MemBarVolatile);
6108 ins_cost(4*MEMORY_REF_COST);
6110 size(4);
6111 format %{ "MEMBAR-volatile" %}
6112 ins_encode( enc_membar_volatile );
6113 ins_pipe(long_memory_op);
6114 %}
6116 instruct unnecessary_membar_volatile() %{
6117 match(MemBarVolatile);
6118 predicate(Matcher::post_store_load_barrier(n));
6119 ins_cost(0);
6121 size(0);
6122 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6123 ins_encode( );
6124 ins_pipe(empty);
6125 %}
6127 //----------Register Move Instructions-----------------------------------------
6128 instruct roundDouble_nop(regD dst) %{
6129 match(Set dst (RoundDouble dst));
6130 ins_cost(0);
6131 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6132 ins_encode( );
6133 ins_pipe(empty);
6134 %}
6137 instruct roundFloat_nop(regF dst) %{
6138 match(Set dst (RoundFloat dst));
6139 ins_cost(0);
6140 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6141 ins_encode( );
6142 ins_pipe(empty);
6143 %}
6146 // Cast Index to Pointer for unsafe natives
6147 instruct castX2P(iRegX src, iRegP dst) %{
6148 match(Set dst (CastX2P src));
6150 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6151 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6152 ins_pipe(ialu_reg);
6153 %}
6155 // Cast Pointer to Index for unsafe natives
6156 instruct castP2X(iRegP src, iRegX dst) %{
6157 match(Set dst (CastP2X src));
6159 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6160 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6161 ins_pipe(ialu_reg);
6162 %}
6164 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6165 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6166 match(Set stkSlot src); // chain rule
6167 ins_cost(MEMORY_REF_COST);
6168 format %{ "STDF $src,$stkSlot\t!stk" %}
6169 opcode(Assembler::stdf_op3);
6170 ins_encode(simple_form3_mem_reg(stkSlot, src));
6171 ins_pipe(fstoreD_stk_reg);
6172 %}
6174 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6175 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6176 match(Set dst stkSlot); // chain rule
6177 ins_cost(MEMORY_REF_COST);
6178 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6179 opcode(Assembler::lddf_op3);
6180 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6181 ins_pipe(floadD_stk);
6182 %}
6184 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6185 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6186 match(Set stkSlot src); // chain rule
6187 ins_cost(MEMORY_REF_COST);
6188 format %{ "STF $src,$stkSlot\t!stk" %}
6189 opcode(Assembler::stf_op3);
6190 ins_encode(simple_form3_mem_reg(stkSlot, src));
6191 ins_pipe(fstoreF_stk_reg);
6192 %}
6194 //----------Conditional Move---------------------------------------------------
6195 // Conditional move
6196 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6197 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6198 ins_cost(150);
6199 format %{ "MOV$cmp $pcc,$src,$dst" %}
6200 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6201 ins_pipe(ialu_reg);
6202 %}
6204 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6205 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6206 ins_cost(140);
6207 format %{ "MOV$cmp $pcc,$src,$dst" %}
6208 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6209 ins_pipe(ialu_imm);
6210 %}
6212 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6213 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6214 ins_cost(150);
6215 size(4);
6216 format %{ "MOV$cmp $icc,$src,$dst" %}
6217 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6218 ins_pipe(ialu_reg);
6219 %}
6221 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6222 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6223 ins_cost(140);
6224 size(4);
6225 format %{ "MOV$cmp $icc,$src,$dst" %}
6226 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6227 ins_pipe(ialu_imm);
6228 %}
6230 instruct cmovII_U_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6231 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6232 ins_cost(150);
6233 size(4);
6234 format %{ "MOV$cmp $icc,$src,$dst" %}
6235 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6236 ins_pipe(ialu_reg);
6237 %}
6239 instruct cmovII_U_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6240 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6241 ins_cost(140);
6242 size(4);
6243 format %{ "MOV$cmp $icc,$src,$dst" %}
6244 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6245 ins_pipe(ialu_imm);
6246 %}
6248 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6249 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6250 ins_cost(150);
6251 size(4);
6252 format %{ "MOV$cmp $fcc,$src,$dst" %}
6253 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6254 ins_pipe(ialu_reg);
6255 %}
6257 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6258 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6259 ins_cost(140);
6260 size(4);
6261 format %{ "MOV$cmp $fcc,$src,$dst" %}
6262 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6263 ins_pipe(ialu_imm);
6264 %}
6266 // Conditional move for RegN. Only cmov(reg,reg).
6267 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6268 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6269 ins_cost(150);
6270 format %{ "MOV$cmp $pcc,$src,$dst" %}
6271 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6272 ins_pipe(ialu_reg);
6273 %}
6275 // This instruction also works with CmpN so we don't need cmovNN_reg.
6276 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6277 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6278 ins_cost(150);
6279 size(4);
6280 format %{ "MOV$cmp $icc,$src,$dst" %}
6281 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6282 ins_pipe(ialu_reg);
6283 %}
6285 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6286 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6287 ins_cost(150);
6288 size(4);
6289 format %{ "MOV$cmp $fcc,$src,$dst" %}
6290 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6291 ins_pipe(ialu_reg);
6292 %}
6294 // Conditional move
6295 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6296 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6297 ins_cost(150);
6298 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6299 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6300 ins_pipe(ialu_reg);
6301 %}
6303 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6304 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6305 ins_cost(140);
6306 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6307 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6308 ins_pipe(ialu_imm);
6309 %}
6311 // This instruction also works with CmpN so we don't need cmovPN_reg.
6312 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6313 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6314 ins_cost(150);
6316 size(4);
6317 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6318 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6319 ins_pipe(ialu_reg);
6320 %}
6322 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6323 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6324 ins_cost(140);
6326 size(4);
6327 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6328 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6329 ins_pipe(ialu_imm);
6330 %}
6332 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6333 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6334 ins_cost(150);
6335 size(4);
6336 format %{ "MOV$cmp $fcc,$src,$dst" %}
6337 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6338 ins_pipe(ialu_imm);
6339 %}
6341 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6342 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6343 ins_cost(140);
6344 size(4);
6345 format %{ "MOV$cmp $fcc,$src,$dst" %}
6346 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6347 ins_pipe(ialu_imm);
6348 %}
6350 // Conditional move
6351 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6352 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6353 ins_cost(150);
6354 opcode(0x101);
6355 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6356 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6357 ins_pipe(int_conditional_float_move);
6358 %}
6360 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6361 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6362 ins_cost(150);
6364 size(4);
6365 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6366 opcode(0x101);
6367 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6368 ins_pipe(int_conditional_float_move);
6369 %}
6371 // Conditional move,
6372 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6373 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6374 ins_cost(150);
6375 size(4);
6376 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6377 opcode(0x1);
6378 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6379 ins_pipe(int_conditional_double_move);
6380 %}
6382 // Conditional move
6383 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6384 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6385 ins_cost(150);
6386 size(4);
6387 opcode(0x102);
6388 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6389 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6390 ins_pipe(int_conditional_double_move);
6391 %}
6393 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6394 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6395 ins_cost(150);
6397 size(4);
6398 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6399 opcode(0x102);
6400 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6401 ins_pipe(int_conditional_double_move);
6402 %}
6404 // Conditional move,
6405 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6406 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6407 ins_cost(150);
6408 size(4);
6409 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6410 opcode(0x2);
6411 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6412 ins_pipe(int_conditional_double_move);
6413 %}
6415 // Conditional move
6416 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6417 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6418 ins_cost(150);
6419 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6420 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6421 ins_pipe(ialu_reg);
6422 %}
6424 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6425 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6426 ins_cost(140);
6427 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6428 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6429 ins_pipe(ialu_imm);
6430 %}
6432 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6433 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6434 ins_cost(150);
6436 size(4);
6437 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6438 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6439 ins_pipe(ialu_reg);
6440 %}
6443 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6444 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6445 ins_cost(150);
6447 size(4);
6448 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6449 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6450 ins_pipe(ialu_reg);
6451 %}
6455 //----------OS and Locking Instructions----------------------------------------
6457 // This name is KNOWN by the ADLC and cannot be changed.
6458 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6459 // for this guy.
6460 instruct tlsLoadP(g2RegP dst) %{
6461 match(Set dst (ThreadLocal));
6463 size(0);
6464 ins_cost(0);
6465 format %{ "# TLS is in G2" %}
6466 ins_encode( /*empty encoding*/ );
6467 ins_pipe(ialu_none);
6468 %}
6470 instruct checkCastPP( iRegP dst ) %{
6471 match(Set dst (CheckCastPP dst));
6473 size(0);
6474 format %{ "# checkcastPP of $dst" %}
6475 ins_encode( /*empty encoding*/ );
6476 ins_pipe(empty);
6477 %}
6480 instruct castPP( iRegP dst ) %{
6481 match(Set dst (CastPP dst));
6482 format %{ "# castPP of $dst" %}
6483 ins_encode( /*empty encoding*/ );
6484 ins_pipe(empty);
6485 %}
6487 instruct castII( iRegI dst ) %{
6488 match(Set dst (CastII dst));
6489 format %{ "# castII of $dst" %}
6490 ins_encode( /*empty encoding*/ );
6491 ins_cost(0);
6492 ins_pipe(empty);
6493 %}
6495 //----------Arithmetic Instructions--------------------------------------------
6496 // Addition Instructions
6497 // Register Addition
6498 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6499 match(Set dst (AddI src1 src2));
6501 size(4);
6502 format %{ "ADD $src1,$src2,$dst" %}
6503 ins_encode %{
6504 __ add($src1$$Register, $src2$$Register, $dst$$Register);
6505 %}
6506 ins_pipe(ialu_reg_reg);
6507 %}
6509 // Immediate Addition
6510 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6511 match(Set dst (AddI src1 src2));
6513 size(4);
6514 format %{ "ADD $src1,$src2,$dst" %}
6515 opcode(Assembler::add_op3, Assembler::arith_op);
6516 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6517 ins_pipe(ialu_reg_imm);
6518 %}
6520 // Pointer Register Addition
6521 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
6522 match(Set dst (AddP src1 src2));
6524 size(4);
6525 format %{ "ADD $src1,$src2,$dst" %}
6526 opcode(Assembler::add_op3, Assembler::arith_op);
6527 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6528 ins_pipe(ialu_reg_reg);
6529 %}
6531 // Pointer Immediate Addition
6532 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
6533 match(Set dst (AddP src1 src2));
6535 size(4);
6536 format %{ "ADD $src1,$src2,$dst" %}
6537 opcode(Assembler::add_op3, Assembler::arith_op);
6538 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6539 ins_pipe(ialu_reg_imm);
6540 %}
6542 // Long Addition
6543 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6544 match(Set dst (AddL src1 src2));
6546 size(4);
6547 format %{ "ADD $src1,$src2,$dst\t! long" %}
6548 opcode(Assembler::add_op3, Assembler::arith_op);
6549 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6550 ins_pipe(ialu_reg_reg);
6551 %}
6553 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
6554 match(Set dst (AddL src1 con));
6556 size(4);
6557 format %{ "ADD $src1,$con,$dst" %}
6558 opcode(Assembler::add_op3, Assembler::arith_op);
6559 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
6560 ins_pipe(ialu_reg_imm);
6561 %}
6563 //----------Conditional_store--------------------------------------------------
6564 // Conditional-store of the updated heap-top.
6565 // Used during allocation of the shared heap.
6566 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
6568 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
6569 instruct loadPLocked(iRegP dst, memory mem) %{
6570 match(Set dst (LoadPLocked mem));
6571 ins_cost(MEMORY_REF_COST);
6573 #ifndef _LP64
6574 size(4);
6575 format %{ "LDUW $mem,$dst\t! ptr" %}
6576 opcode(Assembler::lduw_op3, 0, REGP_OP);
6577 #else
6578 format %{ "LDX $mem,$dst\t! ptr" %}
6579 opcode(Assembler::ldx_op3, 0, REGP_OP);
6580 #endif
6581 ins_encode( form3_mem_reg( mem, dst ) );
6582 ins_pipe(iload_mem);
6583 %}
6585 // LoadL-locked. Same as a regular long load when used with a compare-swap
6586 instruct loadLLocked(iRegL dst, memory mem) %{
6587 match(Set dst (LoadLLocked mem));
6588 ins_cost(MEMORY_REF_COST);
6589 size(4);
6590 format %{ "LDX $mem,$dst\t! long" %}
6591 opcode(Assembler::ldx_op3);
6592 ins_encode(simple_form3_mem_reg( mem, dst ) );
6593 ins_pipe(iload_mem);
6594 %}
6596 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
6597 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
6598 effect( KILL newval );
6599 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
6600 "CMP R_G3,$oldval\t\t! See if we made progress" %}
6601 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
6602 ins_pipe( long_memory_op );
6603 %}
6605 instruct storeLConditional_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6606 match(Set res (StoreLConditional mem_ptr (Binary oldval newval)));
6607 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6608 // Marshal the register pairs into V9 64-bit registers, then do the compare-and-swap
6609 format %{
6610 "MOV $newval,R_O7\n\t"
6611 "CASXA [$mem_ptr],$oldval,R_O7\t! If $oldval==[$mem_ptr] Then store R_O7 into [$mem_ptr], set R_O7=[$mem_ptr] in any case\n\t"
6612 "CMP $oldval,R_O7\t\t! See if we made progress\n\t"
6613 "MOV 1,$res\n\t"
6614 "MOVne xcc,R_G0,$res"
6615 %}
6616 ins_encode( enc_casx(mem_ptr, oldval, newval),
6617 enc_lflags_ne_to_boolean(res) );
6618 ins_pipe( long_memory_op );
6619 %}
6621 instruct storeLConditional_flags(iRegP mem_ptr, iRegL oldval, iRegL newval, flagsRegL xcc, o7RegI tmp1, immI0 zero) %{
6622 match(Set xcc (CmpI (StoreLConditional mem_ptr (Binary oldval newval)) zero));
6623 effect( USE mem_ptr, KILL tmp1);
6624 // Marshal the register pairs into V9 64-bit registers, then do the compare-and-swap
6625 format %{
6626 "MOV $newval,R_O7\n\t"
6627 "CASXA [$mem_ptr],$oldval,R_O7\t! If $oldval==[$mem_ptr] Then store R_O7 into [$mem_ptr], set R_O7=[$mem_ptr] in any case\n\t"
6628 "CMP $oldval,R_O7\t\t! See if we made progress"
6629 %}
6630 ins_encode( enc_casx(mem_ptr, oldval, newval));
6631 ins_pipe( long_memory_op );
6632 %}
6634 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
6636 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6637 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
6638 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6639 format %{
6640 "MOV $newval,O7\n\t"
6641 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6642 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6643 "MOV 1,$res\n\t"
6644 "MOVne xcc,R_G0,$res"
6645 %}
6646 ins_encode( enc_casx(mem_ptr, oldval, newval),
6647 enc_lflags_ne_to_boolean(res) );
6648 ins_pipe( long_memory_op );
6649 %}
6652 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6653 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
6654 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6655 format %{
6656 "MOV $newval,O7\n\t"
6657 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6658 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6659 "MOV 1,$res\n\t"
6660 "MOVne icc,R_G0,$res"
6661 %}
6662 ins_encode( enc_casi(mem_ptr, oldval, newval),
6663 enc_iflags_ne_to_boolean(res) );
6664 ins_pipe( long_memory_op );
6665 %}
6667 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6668 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
6669 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6670 format %{
6671 "MOV $newval,O7\n\t"
6672 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6673 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6674 "MOV 1,$res\n\t"
6675 "MOVne xcc,R_G0,$res"
6676 %}
6677 #ifdef _LP64
6678 ins_encode( enc_casx(mem_ptr, oldval, newval),
6679 enc_lflags_ne_to_boolean(res) );
6680 #else
6681 ins_encode( enc_casi(mem_ptr, oldval, newval),
6682 enc_iflags_ne_to_boolean(res) );
6683 #endif
6684 ins_pipe( long_memory_op );
6685 %}
6687 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6688 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
6689 effect( USE mem_ptr, KILL ccr, KILL tmp1);
6690 format %{
6691 "MOV $newval,O7\n\t"
6692 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
6693 "CMP $oldval,O7\t\t! See if we made progress\n\t"
6694 "MOV 1,$res\n\t"
6695 "MOVne icc,R_G0,$res"
6696 %}
6697 ins_encode( enc_casi(mem_ptr, oldval, newval),
6698 enc_iflags_ne_to_boolean(res) );
6699 ins_pipe( long_memory_op );
6700 %}
6702 //---------------------
6703 // Subtraction Instructions
6704 // Register Subtraction
6705 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6706 match(Set dst (SubI src1 src2));
6708 size(4);
6709 format %{ "SUB $src1,$src2,$dst" %}
6710 opcode(Assembler::sub_op3, Assembler::arith_op);
6711 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6712 ins_pipe(ialu_reg_reg);
6713 %}
6715 // Immediate Subtraction
6716 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6717 match(Set dst (SubI src1 src2));
6719 size(4);
6720 format %{ "SUB $src1,$src2,$dst" %}
6721 opcode(Assembler::sub_op3, Assembler::arith_op);
6722 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6723 ins_pipe(ialu_reg_imm);
6724 %}
6726 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
6727 match(Set dst (SubI zero src2));
6729 size(4);
6730 format %{ "NEG $src2,$dst" %}
6731 opcode(Assembler::sub_op3, Assembler::arith_op);
6732 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
6733 ins_pipe(ialu_zero_reg);
6734 %}
6736 // Long subtraction
6737 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6738 match(Set dst (SubL src1 src2));
6740 size(4);
6741 format %{ "SUB $src1,$src2,$dst\t! long" %}
6742 opcode(Assembler::sub_op3, Assembler::arith_op);
6743 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6744 ins_pipe(ialu_reg_reg);
6745 %}
6747 // Immediate Subtraction
6748 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
6749 match(Set dst (SubL src1 con));
6751 size(4);
6752 format %{ "SUB $src1,$con,$dst\t! long" %}
6753 opcode(Assembler::sub_op3, Assembler::arith_op);
6754 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
6755 ins_pipe(ialu_reg_imm);
6756 %}
6758 // Long negation
6759 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
6760 match(Set dst (SubL zero src2));
6762 size(4);
6763 format %{ "NEG $src2,$dst\t! long" %}
6764 opcode(Assembler::sub_op3, Assembler::arith_op);
6765 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
6766 ins_pipe(ialu_zero_reg);
6767 %}
6769 // Multiplication Instructions
6770 // Integer Multiplication
6771 // Register Multiplication
6772 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6773 match(Set dst (MulI src1 src2));
6775 size(4);
6776 format %{ "MULX $src1,$src2,$dst" %}
6777 opcode(Assembler::mulx_op3, Assembler::arith_op);
6778 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6779 ins_pipe(imul_reg_reg);
6780 %}
6782 // Immediate Multiplication
6783 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6784 match(Set dst (MulI src1 src2));
6786 size(4);
6787 format %{ "MULX $src1,$src2,$dst" %}
6788 opcode(Assembler::mulx_op3, Assembler::arith_op);
6789 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6790 ins_pipe(imul_reg_imm);
6791 %}
6793 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6794 match(Set dst (MulL src1 src2));
6795 ins_cost(DEFAULT_COST * 5);
6796 size(4);
6797 format %{ "MULX $src1,$src2,$dst\t! long" %}
6798 opcode(Assembler::mulx_op3, Assembler::arith_op);
6799 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6800 ins_pipe(mulL_reg_reg);
6801 %}
6803 // Immediate Multiplication
6804 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
6805 match(Set dst (MulL src1 src2));
6806 ins_cost(DEFAULT_COST * 5);
6807 size(4);
6808 format %{ "MULX $src1,$src2,$dst" %}
6809 opcode(Assembler::mulx_op3, Assembler::arith_op);
6810 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6811 ins_pipe(mulL_reg_imm);
6812 %}
6814 // Integer Division
6815 // Register Division
6816 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
6817 match(Set dst (DivI src1 src2));
6818 ins_cost((2+71)*DEFAULT_COST);
6820 format %{ "SRA $src2,0,$src2\n\t"
6821 "SRA $src1,0,$src1\n\t"
6822 "SDIVX $src1,$src2,$dst" %}
6823 ins_encode( idiv_reg( src1, src2, dst ) );
6824 ins_pipe(sdiv_reg_reg);
6825 %}
6827 // Immediate Division
6828 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
6829 match(Set dst (DivI src1 src2));
6830 ins_cost((2+71)*DEFAULT_COST);
6832 format %{ "SRA $src1,0,$src1\n\t"
6833 "SDIVX $src1,$src2,$dst" %}
6834 ins_encode( idiv_imm( src1, src2, dst ) );
6835 ins_pipe(sdiv_reg_imm);
6836 %}
6838 //----------Div-By-10-Expansion------------------------------------------------
6839 // Extract hi bits of a 32x32->64 bit multiply.
6840 // Expand rule only, not matched
6841 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
6842 effect( DEF dst, USE src1, USE src2 );
6843 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
6844 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
6845 ins_encode( enc_mul_hi(dst,src1,src2));
6846 ins_pipe(sdiv_reg_reg);
6847 %}
6849 // Magic constant, reciprical of 10
6850 instruct loadConI_x66666667(iRegIsafe dst) %{
6851 effect( DEF dst );
6853 size(8);
6854 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
6855 ins_encode( Set32(0x66666667, dst) );
6856 ins_pipe(ialu_hi_lo_reg);
6857 %}
6859 // Register Shift Right Arithmatic Long by 32-63
6860 instruct sra_31( iRegI dst, iRegI src ) %{
6861 effect( DEF dst, USE src );
6862 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
6863 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
6864 ins_pipe(ialu_reg_reg);
6865 %}
6867 // Arithmetic Shift Right by 8-bit immediate
6868 instruct sra_reg_2( iRegI dst, iRegI src ) %{
6869 effect( DEF dst, USE src );
6870 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
6871 opcode(Assembler::sra_op3, Assembler::arith_op);
6872 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
6873 ins_pipe(ialu_reg_imm);
6874 %}
6876 // Integer DIV with 10
6877 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
6878 match(Set dst (DivI src div));
6879 ins_cost((6+6)*DEFAULT_COST);
6880 expand %{
6881 iRegIsafe tmp1; // Killed temps;
6882 iRegIsafe tmp2; // Killed temps;
6883 iRegI tmp3; // Killed temps;
6884 iRegI tmp4; // Killed temps;
6885 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
6886 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
6887 sra_31( tmp3, src ); // SRA src,31 -> tmp3
6888 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
6889 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
6890 %}
6891 %}
6893 // Register Long Division
6894 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6895 match(Set dst (DivL src1 src2));
6896 ins_cost(DEFAULT_COST*71);
6897 size(4);
6898 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
6899 opcode(Assembler::sdivx_op3, Assembler::arith_op);
6900 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6901 ins_pipe(divL_reg_reg);
6902 %}
6904 // Register Long Division
6905 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
6906 match(Set dst (DivL src1 src2));
6907 ins_cost(DEFAULT_COST*71);
6908 size(4);
6909 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
6910 opcode(Assembler::sdivx_op3, Assembler::arith_op);
6911 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6912 ins_pipe(divL_reg_imm);
6913 %}
6915 // Integer Remainder
6916 // Register Remainder
6917 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
6918 match(Set dst (ModI src1 src2));
6919 effect( KILL ccr, KILL temp);
6921 format %{ "SREM $src1,$src2,$dst" %}
6922 ins_encode( irem_reg(src1, src2, dst, temp) );
6923 ins_pipe(sdiv_reg_reg);
6924 %}
6926 // Immediate Remainder
6927 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
6928 match(Set dst (ModI src1 src2));
6929 effect( KILL ccr, KILL temp);
6931 format %{ "SREM $src1,$src2,$dst" %}
6932 ins_encode( irem_imm(src1, src2, dst, temp) );
6933 ins_pipe(sdiv_reg_imm);
6934 %}
6936 // Register Long Remainder
6937 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
6938 effect(DEF dst, USE src1, USE src2);
6939 size(4);
6940 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
6941 opcode(Assembler::sdivx_op3, Assembler::arith_op);
6942 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6943 ins_pipe(divL_reg_reg);
6944 %}
6946 // Register Long Division
6947 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
6948 effect(DEF dst, USE src1, USE src2);
6949 size(4);
6950 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
6951 opcode(Assembler::sdivx_op3, Assembler::arith_op);
6952 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6953 ins_pipe(divL_reg_imm);
6954 %}
6956 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
6957 effect(DEF dst, USE src1, USE src2);
6958 size(4);
6959 format %{ "MULX $src1,$src2,$dst\t! long" %}
6960 opcode(Assembler::mulx_op3, Assembler::arith_op);
6961 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6962 ins_pipe(mulL_reg_reg);
6963 %}
6965 // Immediate Multiplication
6966 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
6967 effect(DEF dst, USE src1, USE src2);
6968 size(4);
6969 format %{ "MULX $src1,$src2,$dst" %}
6970 opcode(Assembler::mulx_op3, Assembler::arith_op);
6971 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
6972 ins_pipe(mulL_reg_imm);
6973 %}
6975 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
6976 effect(DEF dst, USE src1, USE src2);
6977 size(4);
6978 format %{ "SUB $src1,$src2,$dst\t! long" %}
6979 opcode(Assembler::sub_op3, Assembler::arith_op);
6980 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6981 ins_pipe(ialu_reg_reg);
6982 %}
6984 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
6985 effect(DEF dst, USE src1, USE src2);
6986 size(4);
6987 format %{ "SUB $src1,$src2,$dst\t! long" %}
6988 opcode(Assembler::sub_op3, Assembler::arith_op);
6989 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
6990 ins_pipe(ialu_reg_reg);
6991 %}
6993 // Register Long Remainder
6994 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
6995 match(Set dst (ModL src1 src2));
6996 ins_cost(DEFAULT_COST*(71 + 6 + 1));
6997 expand %{
6998 iRegL tmp1;
6999 iRegL tmp2;
7000 divL_reg_reg_1(tmp1, src1, src2);
7001 mulL_reg_reg_1(tmp2, tmp1, src2);
7002 subL_reg_reg_1(dst, src1, tmp2);
7003 %}
7004 %}
7006 // Register Long Remainder
7007 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7008 match(Set dst (ModL src1 src2));
7009 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7010 expand %{
7011 iRegL tmp1;
7012 iRegL tmp2;
7013 divL_reg_imm13_1(tmp1, src1, src2);
7014 mulL_reg_imm13_1(tmp2, tmp1, src2);
7015 subL_reg_reg_2 (dst, src1, tmp2);
7016 %}
7017 %}
7019 // Integer Shift Instructions
7020 // Register Shift Left
7021 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7022 match(Set dst (LShiftI src1 src2));
7024 size(4);
7025 format %{ "SLL $src1,$src2,$dst" %}
7026 opcode(Assembler::sll_op3, Assembler::arith_op);
7027 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7028 ins_pipe(ialu_reg_reg);
7029 %}
7031 // Register Shift Left Immediate
7032 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7033 match(Set dst (LShiftI src1 src2));
7035 size(4);
7036 format %{ "SLL $src1,$src2,$dst" %}
7037 opcode(Assembler::sll_op3, Assembler::arith_op);
7038 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7039 ins_pipe(ialu_reg_imm);
7040 %}
7042 // Register Shift Left
7043 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7044 match(Set dst (LShiftL src1 src2));
7046 size(4);
7047 format %{ "SLLX $src1,$src2,$dst" %}
7048 opcode(Assembler::sllx_op3, Assembler::arith_op);
7049 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7050 ins_pipe(ialu_reg_reg);
7051 %}
7053 // Register Shift Left Immediate
7054 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7055 match(Set dst (LShiftL src1 src2));
7057 size(4);
7058 format %{ "SLLX $src1,$src2,$dst" %}
7059 opcode(Assembler::sllx_op3, Assembler::arith_op);
7060 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7061 ins_pipe(ialu_reg_imm);
7062 %}
7064 // Register Arithmetic Shift Right
7065 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7066 match(Set dst (RShiftI src1 src2));
7067 size(4);
7068 format %{ "SRA $src1,$src2,$dst" %}
7069 opcode(Assembler::sra_op3, Assembler::arith_op);
7070 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7071 ins_pipe(ialu_reg_reg);
7072 %}
7074 // Register Arithmetic Shift Right Immediate
7075 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7076 match(Set dst (RShiftI src1 src2));
7078 size(4);
7079 format %{ "SRA $src1,$src2,$dst" %}
7080 opcode(Assembler::sra_op3, Assembler::arith_op);
7081 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7082 ins_pipe(ialu_reg_imm);
7083 %}
7085 // Register Shift Right Arithmatic Long
7086 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7087 match(Set dst (RShiftL src1 src2));
7089 size(4);
7090 format %{ "SRAX $src1,$src2,$dst" %}
7091 opcode(Assembler::srax_op3, Assembler::arith_op);
7092 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7093 ins_pipe(ialu_reg_reg);
7094 %}
7096 // Register Shift Left Immediate
7097 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7098 match(Set dst (RShiftL src1 src2));
7100 size(4);
7101 format %{ "SRAX $src1,$src2,$dst" %}
7102 opcode(Assembler::srax_op3, Assembler::arith_op);
7103 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7104 ins_pipe(ialu_reg_imm);
7105 %}
7107 // Register Shift Right
7108 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7109 match(Set dst (URShiftI src1 src2));
7111 size(4);
7112 format %{ "SRL $src1,$src2,$dst" %}
7113 opcode(Assembler::srl_op3, Assembler::arith_op);
7114 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7115 ins_pipe(ialu_reg_reg);
7116 %}
7118 // Register Shift Right Immediate
7119 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7120 match(Set dst (URShiftI src1 src2));
7122 size(4);
7123 format %{ "SRL $src1,$src2,$dst" %}
7124 opcode(Assembler::srl_op3, Assembler::arith_op);
7125 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7126 ins_pipe(ialu_reg_imm);
7127 %}
7129 // Register Shift Right
7130 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7131 match(Set dst (URShiftL src1 src2));
7133 size(4);
7134 format %{ "SRLX $src1,$src2,$dst" %}
7135 opcode(Assembler::srlx_op3, Assembler::arith_op);
7136 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7137 ins_pipe(ialu_reg_reg);
7138 %}
7140 // Register Shift Right Immediate
7141 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7142 match(Set dst (URShiftL src1 src2));
7144 size(4);
7145 format %{ "SRLX $src1,$src2,$dst" %}
7146 opcode(Assembler::srlx_op3, Assembler::arith_op);
7147 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7148 ins_pipe(ialu_reg_imm);
7149 %}
7151 // Register Shift Right Immediate with a CastP2X
7152 #ifdef _LP64
7153 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7154 match(Set dst (URShiftL (CastP2X src1) src2));
7155 size(4);
7156 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7157 opcode(Assembler::srlx_op3, Assembler::arith_op);
7158 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7159 ins_pipe(ialu_reg_imm);
7160 %}
7161 #else
7162 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7163 match(Set dst (URShiftI (CastP2X src1) src2));
7164 size(4);
7165 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7166 opcode(Assembler::srl_op3, Assembler::arith_op);
7167 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7168 ins_pipe(ialu_reg_imm);
7169 %}
7170 #endif
7173 //----------Floating Point Arithmetic Instructions-----------------------------
7175 // Add float single precision
7176 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7177 match(Set dst (AddF src1 src2));
7179 size(4);
7180 format %{ "FADDS $src1,$src2,$dst" %}
7181 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7182 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7183 ins_pipe(faddF_reg_reg);
7184 %}
7186 // Add float double precision
7187 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7188 match(Set dst (AddD src1 src2));
7190 size(4);
7191 format %{ "FADDD $src1,$src2,$dst" %}
7192 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7193 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7194 ins_pipe(faddD_reg_reg);
7195 %}
7197 // Sub float single precision
7198 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7199 match(Set dst (SubF src1 src2));
7201 size(4);
7202 format %{ "FSUBS $src1,$src2,$dst" %}
7203 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7204 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7205 ins_pipe(faddF_reg_reg);
7206 %}
7208 // Sub float double precision
7209 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7210 match(Set dst (SubD src1 src2));
7212 size(4);
7213 format %{ "FSUBD $src1,$src2,$dst" %}
7214 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7215 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7216 ins_pipe(faddD_reg_reg);
7217 %}
7219 // Mul float single precision
7220 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7221 match(Set dst (MulF src1 src2));
7223 size(4);
7224 format %{ "FMULS $src1,$src2,$dst" %}
7225 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7226 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7227 ins_pipe(fmulF_reg_reg);
7228 %}
7230 // Mul float double precision
7231 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7232 match(Set dst (MulD src1 src2));
7234 size(4);
7235 format %{ "FMULD $src1,$src2,$dst" %}
7236 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7237 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7238 ins_pipe(fmulD_reg_reg);
7239 %}
7241 // Div float single precision
7242 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7243 match(Set dst (DivF src1 src2));
7245 size(4);
7246 format %{ "FDIVS $src1,$src2,$dst" %}
7247 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7248 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7249 ins_pipe(fdivF_reg_reg);
7250 %}
7252 // Div float double precision
7253 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7254 match(Set dst (DivD src1 src2));
7256 size(4);
7257 format %{ "FDIVD $src1,$src2,$dst" %}
7258 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7259 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7260 ins_pipe(fdivD_reg_reg);
7261 %}
7263 // Absolute float double precision
7264 instruct absD_reg(regD dst, regD src) %{
7265 match(Set dst (AbsD src));
7267 format %{ "FABSd $src,$dst" %}
7268 ins_encode(fabsd(dst, src));
7269 ins_pipe(faddD_reg);
7270 %}
7272 // Absolute float single precision
7273 instruct absF_reg(regF dst, regF src) %{
7274 match(Set dst (AbsF src));
7276 format %{ "FABSs $src,$dst" %}
7277 ins_encode(fabss(dst, src));
7278 ins_pipe(faddF_reg);
7279 %}
7281 instruct negF_reg(regF dst, regF src) %{
7282 match(Set dst (NegF src));
7284 size(4);
7285 format %{ "FNEGs $src,$dst" %}
7286 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7287 ins_encode(form3_opf_rs2F_rdF(src, dst));
7288 ins_pipe(faddF_reg);
7289 %}
7291 instruct negD_reg(regD dst, regD src) %{
7292 match(Set dst (NegD src));
7294 format %{ "FNEGd $src,$dst" %}
7295 ins_encode(fnegd(dst, src));
7296 ins_pipe(faddD_reg);
7297 %}
7299 // Sqrt float double precision
7300 instruct sqrtF_reg_reg(regF dst, regF src) %{
7301 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7303 size(4);
7304 format %{ "FSQRTS $src,$dst" %}
7305 ins_encode(fsqrts(dst, src));
7306 ins_pipe(fdivF_reg_reg);
7307 %}
7309 // Sqrt float double precision
7310 instruct sqrtD_reg_reg(regD dst, regD src) %{
7311 match(Set dst (SqrtD src));
7313 size(4);
7314 format %{ "FSQRTD $src,$dst" %}
7315 ins_encode(fsqrtd(dst, src));
7316 ins_pipe(fdivD_reg_reg);
7317 %}
7319 //----------Logical Instructions-----------------------------------------------
7320 // And Instructions
7321 // Register And
7322 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7323 match(Set dst (AndI src1 src2));
7325 size(4);
7326 format %{ "AND $src1,$src2,$dst" %}
7327 opcode(Assembler::and_op3, Assembler::arith_op);
7328 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7329 ins_pipe(ialu_reg_reg);
7330 %}
7332 // Immediate And
7333 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7334 match(Set dst (AndI src1 src2));
7336 size(4);
7337 format %{ "AND $src1,$src2,$dst" %}
7338 opcode(Assembler::and_op3, Assembler::arith_op);
7339 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7340 ins_pipe(ialu_reg_imm);
7341 %}
7343 // Register And Long
7344 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7345 match(Set dst (AndL src1 src2));
7347 ins_cost(DEFAULT_COST);
7348 size(4);
7349 format %{ "AND $src1,$src2,$dst\t! long" %}
7350 opcode(Assembler::and_op3, Assembler::arith_op);
7351 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7352 ins_pipe(ialu_reg_reg);
7353 %}
7355 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7356 match(Set dst (AndL src1 con));
7358 ins_cost(DEFAULT_COST);
7359 size(4);
7360 format %{ "AND $src1,$con,$dst\t! long" %}
7361 opcode(Assembler::and_op3, Assembler::arith_op);
7362 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7363 ins_pipe(ialu_reg_imm);
7364 %}
7366 // Or Instructions
7367 // Register Or
7368 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7369 match(Set dst (OrI src1 src2));
7371 size(4);
7372 format %{ "OR $src1,$src2,$dst" %}
7373 opcode(Assembler::or_op3, Assembler::arith_op);
7374 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7375 ins_pipe(ialu_reg_reg);
7376 %}
7378 // Immediate Or
7379 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7380 match(Set dst (OrI src1 src2));
7382 size(4);
7383 format %{ "OR $src1,$src2,$dst" %}
7384 opcode(Assembler::or_op3, Assembler::arith_op);
7385 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7386 ins_pipe(ialu_reg_imm);
7387 %}
7389 // Register Or Long
7390 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7391 match(Set dst (OrL src1 src2));
7393 ins_cost(DEFAULT_COST);
7394 size(4);
7395 format %{ "OR $src1,$src2,$dst\t! long" %}
7396 opcode(Assembler::or_op3, Assembler::arith_op);
7397 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7398 ins_pipe(ialu_reg_reg);
7399 %}
7401 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7402 match(Set dst (OrL src1 con));
7403 ins_cost(DEFAULT_COST*2);
7405 ins_cost(DEFAULT_COST);
7406 size(4);
7407 format %{ "OR $src1,$con,$dst\t! long" %}
7408 opcode(Assembler::or_op3, Assembler::arith_op);
7409 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7410 ins_pipe(ialu_reg_imm);
7411 %}
7413 // Xor Instructions
7414 // Register Xor
7415 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7416 match(Set dst (XorI src1 src2));
7418 size(4);
7419 format %{ "XOR $src1,$src2,$dst" %}
7420 opcode(Assembler::xor_op3, Assembler::arith_op);
7421 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7422 ins_pipe(ialu_reg_reg);
7423 %}
7425 // Immediate Xor
7426 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7427 match(Set dst (XorI src1 src2));
7429 size(4);
7430 format %{ "XOR $src1,$src2,$dst" %}
7431 opcode(Assembler::xor_op3, Assembler::arith_op);
7432 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7433 ins_pipe(ialu_reg_imm);
7434 %}
7436 // Register Xor Long
7437 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7438 match(Set dst (XorL src1 src2));
7440 ins_cost(DEFAULT_COST);
7441 size(4);
7442 format %{ "XOR $src1,$src2,$dst\t! long" %}
7443 opcode(Assembler::xor_op3, Assembler::arith_op);
7444 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7445 ins_pipe(ialu_reg_reg);
7446 %}
7448 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7449 match(Set dst (XorL src1 con));
7451 ins_cost(DEFAULT_COST);
7452 size(4);
7453 format %{ "XOR $src1,$con,$dst\t! long" %}
7454 opcode(Assembler::xor_op3, Assembler::arith_op);
7455 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7456 ins_pipe(ialu_reg_imm);
7457 %}
7459 //----------Convert to Boolean-------------------------------------------------
7460 // Nice hack for 32-bit tests but doesn't work for
7461 // 64-bit pointers.
7462 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
7463 match(Set dst (Conv2B src));
7464 effect( KILL ccr );
7465 ins_cost(DEFAULT_COST*2);
7466 format %{ "CMP R_G0,$src\n\t"
7467 "ADDX R_G0,0,$dst" %}
7468 ins_encode( enc_to_bool( src, dst ) );
7469 ins_pipe(ialu_reg_ialu);
7470 %}
7472 #ifndef _LP64
7473 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
7474 match(Set dst (Conv2B src));
7475 effect( KILL ccr );
7476 ins_cost(DEFAULT_COST*2);
7477 format %{ "CMP R_G0,$src\n\t"
7478 "ADDX R_G0,0,$dst" %}
7479 ins_encode( enc_to_bool( src, dst ) );
7480 ins_pipe(ialu_reg_ialu);
7481 %}
7482 #else
7483 instruct convP2B( iRegI dst, iRegP src ) %{
7484 match(Set dst (Conv2B src));
7485 ins_cost(DEFAULT_COST*2);
7486 format %{ "MOV $src,$dst\n\t"
7487 "MOVRNZ $src,1,$dst" %}
7488 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
7489 ins_pipe(ialu_clr_and_mover);
7490 %}
7491 #endif
7493 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
7494 match(Set dst (CmpLTMask p q));
7495 effect( KILL ccr );
7496 ins_cost(DEFAULT_COST*4);
7497 format %{ "CMP $p,$q\n\t"
7498 "MOV #0,$dst\n\t"
7499 "BLT,a .+8\n\t"
7500 "MOV #-1,$dst" %}
7501 ins_encode( enc_ltmask(p,q,dst) );
7502 ins_pipe(ialu_reg_reg_ialu);
7503 %}
7505 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
7506 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
7507 effect(KILL ccr, TEMP tmp);
7508 ins_cost(DEFAULT_COST*3);
7510 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
7511 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
7512 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
7513 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
7514 ins_pipe( cadd_cmpltmask );
7515 %}
7517 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
7518 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y)));
7519 effect( KILL ccr, TEMP tmp);
7520 ins_cost(DEFAULT_COST*3);
7522 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
7523 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
7524 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
7525 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
7526 ins_pipe( cadd_cmpltmask );
7527 %}
7529 //----------Arithmetic Conversion Instructions---------------------------------
7530 // The conversions operations are all Alpha sorted. Please keep it that way!
7532 instruct convD2F_reg(regF dst, regD src) %{
7533 match(Set dst (ConvD2F src));
7534 size(4);
7535 format %{ "FDTOS $src,$dst" %}
7536 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
7537 ins_encode(form3_opf_rs2D_rdF(src, dst));
7538 ins_pipe(fcvtD2F);
7539 %}
7542 // Convert a double to an int in a float register.
7543 // If the double is a NAN, stuff a zero in instead.
7544 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
7545 effect(DEF dst, USE src, KILL fcc0);
7546 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
7547 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7548 "FDTOI $src,$dst\t! convert in delay slot\n\t"
7549 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
7550 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
7551 "skip:" %}
7552 ins_encode(form_d2i_helper(src,dst));
7553 ins_pipe(fcvtD2I);
7554 %}
7556 instruct convD2I_reg(stackSlotI dst, regD src) %{
7557 match(Set dst (ConvD2I src));
7558 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7559 expand %{
7560 regF tmp;
7561 convD2I_helper(tmp, src);
7562 regF_to_stkI(dst, tmp);
7563 %}
7564 %}
7566 // Convert a double to a long in a double register.
7567 // If the double is a NAN, stuff a zero in instead.
7568 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
7569 effect(DEF dst, USE src, KILL fcc0);
7570 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
7571 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7572 "FDTOX $src,$dst\t! convert in delay slot\n\t"
7573 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
7574 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
7575 "skip:" %}
7576 ins_encode(form_d2l_helper(src,dst));
7577 ins_pipe(fcvtD2L);
7578 %}
7581 // Double to Long conversion
7582 instruct convD2L_reg(stackSlotL dst, regD src) %{
7583 match(Set dst (ConvD2L src));
7584 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7585 expand %{
7586 regD tmp;
7587 convD2L_helper(tmp, src);
7588 regD_to_stkL(dst, tmp);
7589 %}
7590 %}
7593 instruct convF2D_reg(regD dst, regF src) %{
7594 match(Set dst (ConvF2D src));
7595 format %{ "FSTOD $src,$dst" %}
7596 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
7597 ins_encode(form3_opf_rs2F_rdD(src, dst));
7598 ins_pipe(fcvtF2D);
7599 %}
7602 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
7603 effect(DEF dst, USE src, KILL fcc0);
7604 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
7605 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7606 "FSTOI $src,$dst\t! convert in delay slot\n\t"
7607 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
7608 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
7609 "skip:" %}
7610 ins_encode(form_f2i_helper(src,dst));
7611 ins_pipe(fcvtF2I);
7612 %}
7614 instruct convF2I_reg(stackSlotI dst, regF src) %{
7615 match(Set dst (ConvF2I src));
7616 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7617 expand %{
7618 regF tmp;
7619 convF2I_helper(tmp, src);
7620 regF_to_stkI(dst, tmp);
7621 %}
7622 %}
7625 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
7626 effect(DEF dst, USE src, KILL fcc0);
7627 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
7628 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
7629 "FSTOX $src,$dst\t! convert in delay slot\n\t"
7630 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
7631 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
7632 "skip:" %}
7633 ins_encode(form_f2l_helper(src,dst));
7634 ins_pipe(fcvtF2L);
7635 %}
7637 // Float to Long conversion
7638 instruct convF2L_reg(stackSlotL dst, regF src) %{
7639 match(Set dst (ConvF2L src));
7640 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
7641 expand %{
7642 regD tmp;
7643 convF2L_helper(tmp, src);
7644 regD_to_stkL(dst, tmp);
7645 %}
7646 %}
7649 instruct convI2D_helper(regD dst, regF tmp) %{
7650 effect(USE tmp, DEF dst);
7651 format %{ "FITOD $tmp,$dst" %}
7652 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
7653 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
7654 ins_pipe(fcvtI2D);
7655 %}
7657 instruct convI2D_reg(stackSlotI src, regD dst) %{
7658 match(Set dst (ConvI2D src));
7659 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7660 expand %{
7661 regF tmp;
7662 stkI_to_regF( tmp, src);
7663 convI2D_helper( dst, tmp);
7664 %}
7665 %}
7667 instruct convI2D_mem( regD_low dst, memory mem ) %{
7668 match(Set dst (ConvI2D (LoadI mem)));
7669 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7670 size(8);
7671 format %{ "LDF $mem,$dst\n\t"
7672 "FITOD $dst,$dst" %}
7673 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
7674 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
7675 ins_pipe(floadF_mem);
7676 %}
7679 instruct convI2F_helper(regF dst, regF tmp) %{
7680 effect(DEF dst, USE tmp);
7681 format %{ "FITOS $tmp,$dst" %}
7682 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
7683 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
7684 ins_pipe(fcvtI2F);
7685 %}
7687 instruct convI2F_reg( regF dst, stackSlotI src ) %{
7688 match(Set dst (ConvI2F src));
7689 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7690 expand %{
7691 regF tmp;
7692 stkI_to_regF(tmp,src);
7693 convI2F_helper(dst, tmp);
7694 %}
7695 %}
7697 instruct convI2F_mem( regF dst, memory mem ) %{
7698 match(Set dst (ConvI2F (LoadI mem)));
7699 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7700 size(8);
7701 format %{ "LDF $mem,$dst\n\t"
7702 "FITOS $dst,$dst" %}
7703 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
7704 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
7705 ins_pipe(floadF_mem);
7706 %}
7709 instruct convI2L_reg(iRegL dst, iRegI src) %{
7710 match(Set dst (ConvI2L src));
7711 size(4);
7712 format %{ "SRA $src,0,$dst\t! int->long" %}
7713 opcode(Assembler::sra_op3, Assembler::arith_op);
7714 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
7715 ins_pipe(ialu_reg_reg);
7716 %}
7718 // Zero-extend convert int to long
7719 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
7720 match(Set dst (AndL (ConvI2L src) mask) );
7721 size(4);
7722 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
7723 opcode(Assembler::srl_op3, Assembler::arith_op);
7724 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
7725 ins_pipe(ialu_reg_reg);
7726 %}
7728 // Zero-extend long
7729 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
7730 match(Set dst (AndL src mask) );
7731 size(4);
7732 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
7733 opcode(Assembler::srl_op3, Assembler::arith_op);
7734 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
7735 ins_pipe(ialu_reg_reg);
7736 %}
7738 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
7739 match(Set dst (MoveF2I src));
7740 effect(DEF dst, USE src);
7741 ins_cost(MEMORY_REF_COST);
7743 size(4);
7744 format %{ "LDUW $src,$dst\t! MoveF2I" %}
7745 opcode(Assembler::lduw_op3);
7746 ins_encode(simple_form3_mem_reg( src, dst ) );
7747 ins_pipe(iload_mem);
7748 %}
7750 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
7751 match(Set dst (MoveI2F src));
7752 effect(DEF dst, USE src);
7753 ins_cost(MEMORY_REF_COST);
7755 size(4);
7756 format %{ "LDF $src,$dst\t! MoveI2F" %}
7757 opcode(Assembler::ldf_op3);
7758 ins_encode(simple_form3_mem_reg(src, dst));
7759 ins_pipe(floadF_stk);
7760 %}
7762 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
7763 match(Set dst (MoveD2L src));
7764 effect(DEF dst, USE src);
7765 ins_cost(MEMORY_REF_COST);
7767 size(4);
7768 format %{ "LDX $src,$dst\t! MoveD2L" %}
7769 opcode(Assembler::ldx_op3);
7770 ins_encode(simple_form3_mem_reg( src, dst ) );
7771 ins_pipe(iload_mem);
7772 %}
7774 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
7775 match(Set dst (MoveL2D src));
7776 effect(DEF dst, USE src);
7777 ins_cost(MEMORY_REF_COST);
7779 size(4);
7780 format %{ "LDDF $src,$dst\t! MoveL2D" %}
7781 opcode(Assembler::lddf_op3);
7782 ins_encode(simple_form3_mem_reg(src, dst));
7783 ins_pipe(floadD_stk);
7784 %}
7786 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
7787 match(Set dst (MoveF2I src));
7788 effect(DEF dst, USE src);
7789 ins_cost(MEMORY_REF_COST);
7791 size(4);
7792 format %{ "STF $src,$dst\t!MoveF2I" %}
7793 opcode(Assembler::stf_op3);
7794 ins_encode(simple_form3_mem_reg(dst, src));
7795 ins_pipe(fstoreF_stk_reg);
7796 %}
7798 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
7799 match(Set dst (MoveI2F src));
7800 effect(DEF dst, USE src);
7801 ins_cost(MEMORY_REF_COST);
7803 size(4);
7804 format %{ "STW $src,$dst\t!MoveI2F" %}
7805 opcode(Assembler::stw_op3);
7806 ins_encode(simple_form3_mem_reg( dst, src ) );
7807 ins_pipe(istore_mem_reg);
7808 %}
7810 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
7811 match(Set dst (MoveD2L src));
7812 effect(DEF dst, USE src);
7813 ins_cost(MEMORY_REF_COST);
7815 size(4);
7816 format %{ "STDF $src,$dst\t!MoveD2L" %}
7817 opcode(Assembler::stdf_op3);
7818 ins_encode(simple_form3_mem_reg(dst, src));
7819 ins_pipe(fstoreD_stk_reg);
7820 %}
7822 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
7823 match(Set dst (MoveL2D src));
7824 effect(DEF dst, USE src);
7825 ins_cost(MEMORY_REF_COST);
7827 size(4);
7828 format %{ "STX $src,$dst\t!MoveL2D" %}
7829 opcode(Assembler::stx_op3);
7830 ins_encode(simple_form3_mem_reg( dst, src ) );
7831 ins_pipe(istore_mem_reg);
7832 %}
7835 //-----------
7836 // Long to Double conversion using V8 opcodes.
7837 // Still useful because cheetah traps and becomes
7838 // amazingly slow for some common numbers.
7840 // Magic constant, 0x43300000
7841 instruct loadConI_x43300000(iRegI dst) %{
7842 effect(DEF dst);
7843 size(4);
7844 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
7845 ins_encode(SetHi22(0x43300000, dst));
7846 ins_pipe(ialu_none);
7847 %}
7849 // Magic constant, 0x41f00000
7850 instruct loadConI_x41f00000(iRegI dst) %{
7851 effect(DEF dst);
7852 size(4);
7853 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
7854 ins_encode(SetHi22(0x41f00000, dst));
7855 ins_pipe(ialu_none);
7856 %}
7858 // Construct a double from two float halves
7859 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
7860 effect(DEF dst, USE src1, USE src2);
7861 size(8);
7862 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
7863 "FMOVS $src2.lo,$dst.lo" %}
7864 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
7865 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
7866 ins_pipe(faddD_reg_reg);
7867 %}
7869 // Convert integer in high half of a double register (in the lower half of
7870 // the double register file) to double
7871 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
7872 effect(DEF dst, USE src);
7873 size(4);
7874 format %{ "FITOD $src,$dst" %}
7875 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
7876 ins_encode(form3_opf_rs2D_rdD(src, dst));
7877 ins_pipe(fcvtLHi2D);
7878 %}
7880 // Add float double precision
7881 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
7882 effect(DEF dst, USE src1, USE src2);
7883 size(4);
7884 format %{ "FADDD $src1,$src2,$dst" %}
7885 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7886 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7887 ins_pipe(faddD_reg_reg);
7888 %}
7890 // Sub float double precision
7891 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
7892 effect(DEF dst, USE src1, USE src2);
7893 size(4);
7894 format %{ "FSUBD $src1,$src2,$dst" %}
7895 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7896 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7897 ins_pipe(faddD_reg_reg);
7898 %}
7900 // Mul float double precision
7901 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
7902 effect(DEF dst, USE src1, USE src2);
7903 size(4);
7904 format %{ "FMULD $src1,$src2,$dst" %}
7905 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7906 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7907 ins_pipe(fmulD_reg_reg);
7908 %}
7910 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
7911 match(Set dst (ConvL2D src));
7912 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
7914 expand %{
7915 regD_low tmpsrc;
7916 iRegI ix43300000;
7917 iRegI ix41f00000;
7918 stackSlotL lx43300000;
7919 stackSlotL lx41f00000;
7920 regD_low dx43300000;
7921 regD dx41f00000;
7922 regD tmp1;
7923 regD_low tmp2;
7924 regD tmp3;
7925 regD tmp4;
7927 stkL_to_regD(tmpsrc, src);
7929 loadConI_x43300000(ix43300000);
7930 loadConI_x41f00000(ix41f00000);
7931 regI_to_stkLHi(lx43300000, ix43300000);
7932 regI_to_stkLHi(lx41f00000, ix41f00000);
7933 stkL_to_regD(dx43300000, lx43300000);
7934 stkL_to_regD(dx41f00000, lx41f00000);
7936 convI2D_regDHi_regD(tmp1, tmpsrc);
7937 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
7938 subD_regD_regD(tmp3, tmp2, dx43300000);
7939 mulD_regD_regD(tmp4, tmp1, dx41f00000);
7940 addD_regD_regD(dst, tmp3, tmp4);
7941 %}
7942 %}
7944 // Long to Double conversion using fast fxtof
7945 instruct convL2D_helper(regD dst, regD tmp) %{
7946 effect(DEF dst, USE tmp);
7947 size(4);
7948 format %{ "FXTOD $tmp,$dst" %}
7949 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
7950 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
7951 ins_pipe(fcvtL2D);
7952 %}
7954 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{
7955 predicate(VM_Version::has_fast_fxtof());
7956 match(Set dst (ConvL2D src));
7957 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
7958 expand %{
7959 regD tmp;
7960 stkL_to_regD(tmp, src);
7961 convL2D_helper(dst, tmp);
7962 %}
7963 %}
7965 //-----------
7966 // Long to Float conversion using V8 opcodes.
7967 // Still useful because cheetah traps and becomes
7968 // amazingly slow for some common numbers.
7970 // Long to Float conversion using fast fxtof
7971 instruct convL2F_helper(regF dst, regD tmp) %{
7972 effect(DEF dst, USE tmp);
7973 size(4);
7974 format %{ "FXTOS $tmp,$dst" %}
7975 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
7976 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
7977 ins_pipe(fcvtL2F);
7978 %}
7980 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{
7981 match(Set dst (ConvL2F src));
7982 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
7983 expand %{
7984 regD tmp;
7985 stkL_to_regD(tmp, src);
7986 convL2F_helper(dst, tmp);
7987 %}
7988 %}
7989 //-----------
7991 instruct convL2I_reg(iRegI dst, iRegL src) %{
7992 match(Set dst (ConvL2I src));
7993 #ifndef _LP64
7994 format %{ "MOV $src.lo,$dst\t! long->int" %}
7995 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
7996 ins_pipe(ialu_move_reg_I_to_L);
7997 #else
7998 size(4);
7999 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8000 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8001 ins_pipe(ialu_reg);
8002 #endif
8003 %}
8005 // Register Shift Right Immediate
8006 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8007 match(Set dst (ConvL2I (RShiftL src cnt)));
8009 size(4);
8010 format %{ "SRAX $src,$cnt,$dst" %}
8011 opcode(Assembler::srax_op3, Assembler::arith_op);
8012 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8013 ins_pipe(ialu_reg_imm);
8014 %}
8016 // Replicate scalar to packed byte values in Double register
8017 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
8018 effect(DEF dst, USE src);
8019 format %{ "SLLX $src,56,$dst\n\t"
8020 "SRLX $dst, 8,O7\n\t"
8021 "OR $dst,O7,$dst\n\t"
8022 "SRLX $dst,16,O7\n\t"
8023 "OR $dst,O7,$dst\n\t"
8024 "SRLX $dst,32,O7\n\t"
8025 "OR $dst,O7,$dst\t! replicate8B" %}
8026 ins_encode( enc_repl8b(src, dst));
8027 ins_pipe(ialu_reg);
8028 %}
8030 // Replicate scalar to packed byte values in Double register
8031 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8032 match(Set dst (Replicate8B src));
8033 expand %{
8034 iRegL tmp;
8035 Repl8B_reg_helper(tmp, src);
8036 regL_to_stkD(dst, tmp);
8037 %}
8038 %}
8040 // Replicate scalar constant to packed byte values in Double register
8041 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{
8042 match(Set dst (Replicate8B src));
8043 #ifdef _LP64
8044 size(36);
8045 #else
8046 size(8);
8047 #endif
8048 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t"
8049 "LDDF [$tmp+lo(&Repl8($src))],$dst" %}
8050 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) );
8051 ins_pipe(loadConFD);
8052 %}
8054 // Replicate scalar to packed char values into stack slot
8055 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8056 effect(DEF dst, USE src);
8057 format %{ "SLLX $src,48,$dst\n\t"
8058 "SRLX $dst,16,O7\n\t"
8059 "OR $dst,O7,$dst\n\t"
8060 "SRLX $dst,32,O7\n\t"
8061 "OR $dst,O7,$dst\t! replicate4C" %}
8062 ins_encode( enc_repl4s(src, dst) );
8063 ins_pipe(ialu_reg);
8064 %}
8066 // Replicate scalar to packed char values into stack slot
8067 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8068 match(Set dst (Replicate4C src));
8069 expand %{
8070 iRegL tmp;
8071 Repl4C_reg_helper(tmp, src);
8072 regL_to_stkD(dst, tmp);
8073 %}
8074 %}
8076 // Replicate scalar constant to packed char values in Double register
8077 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{
8078 match(Set dst (Replicate4C src));
8079 #ifdef _LP64
8080 size(36);
8081 #else
8082 size(8);
8083 #endif
8084 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t"
8085 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8086 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8087 ins_pipe(loadConFD);
8088 %}
8090 // Replicate scalar to packed short values into stack slot
8091 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8092 effect(DEF dst, USE src);
8093 format %{ "SLLX $src,48,$dst\n\t"
8094 "SRLX $dst,16,O7\n\t"
8095 "OR $dst,O7,$dst\n\t"
8096 "SRLX $dst,32,O7\n\t"
8097 "OR $dst,O7,$dst\t! replicate4S" %}
8098 ins_encode( enc_repl4s(src, dst) );
8099 ins_pipe(ialu_reg);
8100 %}
8102 // Replicate scalar to packed short values into stack slot
8103 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8104 match(Set dst (Replicate4S src));
8105 expand %{
8106 iRegL tmp;
8107 Repl4S_reg_helper(tmp, src);
8108 regL_to_stkD(dst, tmp);
8109 %}
8110 %}
8112 // Replicate scalar constant to packed short values in Double register
8113 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{
8114 match(Set dst (Replicate4S src));
8115 #ifdef _LP64
8116 size(36);
8117 #else
8118 size(8);
8119 #endif
8120 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t"
8121 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
8122 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
8123 ins_pipe(loadConFD);
8124 %}
8126 // Replicate scalar to packed int values in Double register
8127 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
8128 effect(DEF dst, USE src);
8129 format %{ "SLLX $src,32,$dst\n\t"
8130 "SRLX $dst,32,O7\n\t"
8131 "OR $dst,O7,$dst\t! replicate2I" %}
8132 ins_encode( enc_repl2i(src, dst));
8133 ins_pipe(ialu_reg);
8134 %}
8136 // Replicate scalar to packed int values in Double register
8137 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
8138 match(Set dst (Replicate2I src));
8139 expand %{
8140 iRegL tmp;
8141 Repl2I_reg_helper(tmp, src);
8142 regL_to_stkD(dst, tmp);
8143 %}
8144 %}
8146 // Replicate scalar zero constant to packed int values in Double register
8147 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{
8148 match(Set dst (Replicate2I src));
8149 #ifdef _LP64
8150 size(36);
8151 #else
8152 size(8);
8153 #endif
8154 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t"
8155 "LDDF [$tmp+lo(&Repl2($src))],$dst" %}
8156 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) );
8157 ins_pipe(loadConFD);
8158 %}
8160 //----------Control Flow Instructions------------------------------------------
8161 // Compare Instructions
8162 // Compare Integers
8163 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8164 match(Set icc (CmpI op1 op2));
8165 effect( DEF icc, USE op1, USE op2 );
8167 size(4);
8168 format %{ "CMP $op1,$op2" %}
8169 opcode(Assembler::subcc_op3, Assembler::arith_op);
8170 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8171 ins_pipe(ialu_cconly_reg_reg);
8172 %}
8174 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8175 match(Set icc (CmpU op1 op2));
8177 size(4);
8178 format %{ "CMP $op1,$op2\t! unsigned" %}
8179 opcode(Assembler::subcc_op3, Assembler::arith_op);
8180 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8181 ins_pipe(ialu_cconly_reg_reg);
8182 %}
8184 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8185 match(Set icc (CmpI op1 op2));
8186 effect( DEF icc, USE op1 );
8188 size(4);
8189 format %{ "CMP $op1,$op2" %}
8190 opcode(Assembler::subcc_op3, Assembler::arith_op);
8191 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8192 ins_pipe(ialu_cconly_reg_imm);
8193 %}
8195 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8196 match(Set icc (CmpI (AndI op1 op2) zero));
8198 size(4);
8199 format %{ "BTST $op2,$op1" %}
8200 opcode(Assembler::andcc_op3, Assembler::arith_op);
8201 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8202 ins_pipe(ialu_cconly_reg_reg_zero);
8203 %}
8205 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8206 match(Set icc (CmpI (AndI op1 op2) zero));
8208 size(4);
8209 format %{ "BTST $op2,$op1" %}
8210 opcode(Assembler::andcc_op3, Assembler::arith_op);
8211 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8212 ins_pipe(ialu_cconly_reg_imm_zero);
8213 %}
8215 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8216 match(Set xcc (CmpL op1 op2));
8217 effect( DEF xcc, USE op1, USE op2 );
8219 size(4);
8220 format %{ "CMP $op1,$op2\t\t! long" %}
8221 opcode(Assembler::subcc_op3, Assembler::arith_op);
8222 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8223 ins_pipe(ialu_cconly_reg_reg);
8224 %}
8226 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8227 match(Set xcc (CmpL op1 con));
8228 effect( DEF xcc, USE op1, USE con );
8230 size(4);
8231 format %{ "CMP $op1,$con\t\t! long" %}
8232 opcode(Assembler::subcc_op3, Assembler::arith_op);
8233 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8234 ins_pipe(ialu_cconly_reg_reg);
8235 %}
8237 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8238 match(Set xcc (CmpL (AndL op1 op2) zero));
8239 effect( DEF xcc, USE op1, USE op2 );
8241 size(4);
8242 format %{ "BTST $op1,$op2\t\t! long" %}
8243 opcode(Assembler::andcc_op3, Assembler::arith_op);
8244 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8245 ins_pipe(ialu_cconly_reg_reg);
8246 %}
8248 // useful for checking the alignment of a pointer:
8249 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8250 match(Set xcc (CmpL (AndL op1 con) zero));
8251 effect( DEF xcc, USE op1, USE con );
8253 size(4);
8254 format %{ "BTST $op1,$con\t\t! long" %}
8255 opcode(Assembler::andcc_op3, Assembler::arith_op);
8256 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8257 ins_pipe(ialu_cconly_reg_reg);
8258 %}
8260 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
8261 match(Set icc (CmpU op1 op2));
8263 size(4);
8264 format %{ "CMP $op1,$op2\t! unsigned" %}
8265 opcode(Assembler::subcc_op3, Assembler::arith_op);
8266 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8267 ins_pipe(ialu_cconly_reg_imm);
8268 %}
8270 // Compare Pointers
8271 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8272 match(Set pcc (CmpP op1 op2));
8274 size(4);
8275 format %{ "CMP $op1,$op2\t! ptr" %}
8276 opcode(Assembler::subcc_op3, Assembler::arith_op);
8277 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8278 ins_pipe(ialu_cconly_reg_reg);
8279 %}
8281 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8282 match(Set pcc (CmpP op1 op2));
8284 size(4);
8285 format %{ "CMP $op1,$op2\t! ptr" %}
8286 opcode(Assembler::subcc_op3, Assembler::arith_op);
8287 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8288 ins_pipe(ialu_cconly_reg_imm);
8289 %}
8291 // Compare Narrow oops
8292 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8293 match(Set icc (CmpN op1 op2));
8295 size(4);
8296 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8297 opcode(Assembler::subcc_op3, Assembler::arith_op);
8298 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8299 ins_pipe(ialu_cconly_reg_reg);
8300 %}
8302 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8303 match(Set icc (CmpN op1 op2));
8305 size(4);
8306 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8307 opcode(Assembler::subcc_op3, Assembler::arith_op);
8308 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8309 ins_pipe(ialu_cconly_reg_imm);
8310 %}
8312 //----------Max and Min--------------------------------------------------------
8313 // Min Instructions
8314 // Conditional move for min
8315 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8316 effect( USE_DEF op2, USE op1, USE icc );
8318 size(4);
8319 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8320 opcode(Assembler::less);
8321 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8322 ins_pipe(ialu_reg_flags);
8323 %}
8325 // Min Register with Register.
8326 instruct minI_eReg(iRegI op1, iRegI op2) %{
8327 match(Set op2 (MinI op1 op2));
8328 ins_cost(DEFAULT_COST*2);
8329 expand %{
8330 flagsReg icc;
8331 compI_iReg(icc,op1,op2);
8332 cmovI_reg_lt(op2,op1,icc);
8333 %}
8334 %}
8336 // Max Instructions
8337 // Conditional move for max
8338 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8339 effect( USE_DEF op2, USE op1, USE icc );
8340 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8341 opcode(Assembler::greater);
8342 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8343 ins_pipe(ialu_reg_flags);
8344 %}
8346 // Max Register with Register
8347 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8348 match(Set op2 (MaxI op1 op2));
8349 ins_cost(DEFAULT_COST*2);
8350 expand %{
8351 flagsReg icc;
8352 compI_iReg(icc,op1,op2);
8353 cmovI_reg_gt(op2,op1,icc);
8354 %}
8355 %}
8358 //----------Float Compares----------------------------------------------------
8359 // Compare floating, generate condition code
8360 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8361 match(Set fcc (CmpF src1 src2));
8363 size(4);
8364 format %{ "FCMPs $fcc,$src1,$src2" %}
8365 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8366 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8367 ins_pipe(faddF_fcc_reg_reg_zero);
8368 %}
8370 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8371 match(Set fcc (CmpD src1 src2));
8373 size(4);
8374 format %{ "FCMPd $fcc,$src1,$src2" %}
8375 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8376 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8377 ins_pipe(faddD_fcc_reg_reg_zero);
8378 %}
8381 // Compare floating, generate -1,0,1
8382 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8383 match(Set dst (CmpF3 src1 src2));
8384 effect(KILL fcc0);
8385 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8386 format %{ "fcmpl $dst,$src1,$src2" %}
8387 // Primary = float
8388 opcode( true );
8389 ins_encode( floating_cmp( dst, src1, src2 ) );
8390 ins_pipe( floating_cmp );
8391 %}
8393 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8394 match(Set dst (CmpD3 src1 src2));
8395 effect(KILL fcc0);
8396 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8397 format %{ "dcmpl $dst,$src1,$src2" %}
8398 // Primary = double (not float)
8399 opcode( false );
8400 ins_encode( floating_cmp( dst, src1, src2 ) );
8401 ins_pipe( floating_cmp );
8402 %}
8404 //----------Branches---------------------------------------------------------
8405 // Jump
8406 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8407 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8408 match(Jump switch_val);
8410 ins_cost(350);
8412 format %{ "SETHI [hi(table_base)],O7\n\t"
8413 "ADD O7, lo(table_base), O7\n\t"
8414 "LD [O7+$switch_val], O7\n\t"
8415 "JUMP O7"
8416 %}
8417 ins_encode( jump_enc( switch_val, table) );
8418 ins_pc_relative(1);
8419 ins_pipe(ialu_reg_reg);
8420 %}
8422 // Direct Branch. Use V8 version with longer range.
8423 instruct branch(label labl) %{
8424 match(Goto);
8425 effect(USE labl);
8427 size(8);
8428 ins_cost(BRANCH_COST);
8429 format %{ "BA $labl" %}
8430 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond
8431 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always);
8432 ins_encode( enc_ba( labl ) );
8433 ins_pc_relative(1);
8434 ins_pipe(br);
8435 %}
8437 // Conditional Direct Branch
8438 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
8439 match(If cmp icc);
8440 effect(USE labl);
8442 size(8);
8443 ins_cost(BRANCH_COST);
8444 format %{ "BP$cmp $icc,$labl" %}
8445 // Prim = bits 24-22, Secnd = bits 31-30
8446 ins_encode( enc_bp( labl, cmp, icc ) );
8447 ins_pc_relative(1);
8448 ins_pipe(br_cc);
8449 %}
8451 // Branch-on-register tests all 64 bits. We assume that values
8452 // in 64-bit registers always remains zero or sign extended
8453 // unless our code munges the high bits. Interrupts can chop
8454 // the high order bits to zero or sign at any time.
8455 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
8456 match(If cmp (CmpI op1 zero));
8457 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8458 effect(USE labl);
8460 size(8);
8461 ins_cost(BRANCH_COST);
8462 format %{ "BR$cmp $op1,$labl" %}
8463 ins_encode( enc_bpr( labl, cmp, op1 ) );
8464 ins_pc_relative(1);
8465 ins_pipe(br_reg);
8466 %}
8468 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
8469 match(If cmp (CmpP op1 null));
8470 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8471 effect(USE labl);
8473 size(8);
8474 ins_cost(BRANCH_COST);
8475 format %{ "BR$cmp $op1,$labl" %}
8476 ins_encode( enc_bpr( labl, cmp, op1 ) );
8477 ins_pc_relative(1);
8478 ins_pipe(br_reg);
8479 %}
8481 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
8482 match(If cmp (CmpL op1 zero));
8483 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
8484 effect(USE labl);
8486 size(8);
8487 ins_cost(BRANCH_COST);
8488 format %{ "BR$cmp $op1,$labl" %}
8489 ins_encode( enc_bpr( labl, cmp, op1 ) );
8490 ins_pc_relative(1);
8491 ins_pipe(br_reg);
8492 %}
8494 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
8495 match(If cmp icc);
8496 effect(USE labl);
8498 format %{ "BP$cmp $icc,$labl" %}
8499 // Prim = bits 24-22, Secnd = bits 31-30
8500 ins_encode( enc_bp( labl, cmp, icc ) );
8501 ins_pc_relative(1);
8502 ins_pipe(br_cc);
8503 %}
8505 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
8506 match(If cmp pcc);
8507 effect(USE labl);
8509 size(8);
8510 ins_cost(BRANCH_COST);
8511 format %{ "BP$cmp $pcc,$labl" %}
8512 // Prim = bits 24-22, Secnd = bits 31-30
8513 ins_encode( enc_bpx( labl, cmp, pcc ) );
8514 ins_pc_relative(1);
8515 ins_pipe(br_cc);
8516 %}
8518 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
8519 match(If cmp fcc);
8520 effect(USE labl);
8522 size(8);
8523 ins_cost(BRANCH_COST);
8524 format %{ "FBP$cmp $fcc,$labl" %}
8525 // Prim = bits 24-22, Secnd = bits 31-30
8526 ins_encode( enc_fbp( labl, cmp, fcc ) );
8527 ins_pc_relative(1);
8528 ins_pipe(br_fcc);
8529 %}
8531 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
8532 match(CountedLoopEnd cmp icc);
8533 effect(USE labl);
8535 size(8);
8536 ins_cost(BRANCH_COST);
8537 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
8538 // Prim = bits 24-22, Secnd = bits 31-30
8539 ins_encode( enc_bp( labl, cmp, icc ) );
8540 ins_pc_relative(1);
8541 ins_pipe(br_cc);
8542 %}
8544 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
8545 match(CountedLoopEnd cmp icc);
8546 effect(USE labl);
8548 size(8);
8549 ins_cost(BRANCH_COST);
8550 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
8551 // Prim = bits 24-22, Secnd = bits 31-30
8552 ins_encode( enc_bp( labl, cmp, icc ) );
8553 ins_pc_relative(1);
8554 ins_pipe(br_cc);
8555 %}
8557 // ============================================================================
8558 // Long Compare
8559 //
8560 // Currently we hold longs in 2 registers. Comparing such values efficiently
8561 // is tricky. The flavor of compare used depends on whether we are testing
8562 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
8563 // The GE test is the negated LT test. The LE test can be had by commuting
8564 // the operands (yielding a GE test) and then negating; negate again for the
8565 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
8566 // NE test is negated from that.
8568 // Due to a shortcoming in the ADLC, it mixes up expressions like:
8569 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
8570 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
8571 // are collapsed internally in the ADLC's dfa-gen code. The match for
8572 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
8573 // foo match ends up with the wrong leaf. One fix is to not match both
8574 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
8575 // both forms beat the trinary form of long-compare and both are very useful
8576 // on Intel which has so few registers.
8578 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
8579 match(If cmp xcc);
8580 effect(USE labl);
8582 size(8);
8583 ins_cost(BRANCH_COST);
8584 format %{ "BP$cmp $xcc,$labl" %}
8585 // Prim = bits 24-22, Secnd = bits 31-30
8586 ins_encode( enc_bpl( labl, cmp, xcc ) );
8587 ins_pc_relative(1);
8588 ins_pipe(br_cc);
8589 %}
8591 // Manifest a CmpL3 result in an integer register. Very painful.
8592 // This is the test to avoid.
8593 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
8594 match(Set dst (CmpL3 src1 src2) );
8595 effect( KILL ccr );
8596 ins_cost(6*DEFAULT_COST);
8597 size(24);
8598 format %{ "CMP $src1,$src2\t\t! long\n"
8599 "\tBLT,a,pn done\n"
8600 "\tMOV -1,$dst\t! delay slot\n"
8601 "\tBGT,a,pn done\n"
8602 "\tMOV 1,$dst\t! delay slot\n"
8603 "\tCLR $dst\n"
8604 "done:" %}
8605 ins_encode( cmpl_flag(src1,src2,dst) );
8606 ins_pipe(cmpL_reg);
8607 %}
8609 // Conditional move
8610 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
8611 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
8612 ins_cost(150);
8613 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
8614 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8615 ins_pipe(ialu_reg);
8616 %}
8618 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
8619 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
8620 ins_cost(140);
8621 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
8622 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8623 ins_pipe(ialu_imm);
8624 %}
8626 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
8627 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
8628 ins_cost(150);
8629 format %{ "MOV$cmp $xcc,$src,$dst" %}
8630 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8631 ins_pipe(ialu_reg);
8632 %}
8634 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
8635 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
8636 ins_cost(140);
8637 format %{ "MOV$cmp $xcc,$src,$dst" %}
8638 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8639 ins_pipe(ialu_imm);
8640 %}
8642 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
8643 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
8644 ins_cost(150);
8645 format %{ "MOV$cmp $xcc,$src,$dst" %}
8646 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8647 ins_pipe(ialu_reg);
8648 %}
8650 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
8651 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
8652 ins_cost(150);
8653 format %{ "MOV$cmp $xcc,$src,$dst" %}
8654 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8655 ins_pipe(ialu_reg);
8656 %}
8658 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
8659 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
8660 ins_cost(140);
8661 format %{ "MOV$cmp $xcc,$src,$dst" %}
8662 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8663 ins_pipe(ialu_imm);
8664 %}
8666 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
8667 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
8668 ins_cost(150);
8669 opcode(0x101);
8670 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
8671 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
8672 ins_pipe(int_conditional_float_move);
8673 %}
8675 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
8676 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
8677 ins_cost(150);
8678 opcode(0x102);
8679 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
8680 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
8681 ins_pipe(int_conditional_float_move);
8682 %}
8684 // ============================================================================
8685 // Safepoint Instruction
8686 instruct safePoint_poll(iRegP poll) %{
8687 match(SafePoint poll);
8688 effect(USE poll);
8690 size(4);
8691 #ifdef _LP64
8692 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
8693 #else
8694 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
8695 #endif
8696 ins_encode %{
8697 __ relocate(relocInfo::poll_type);
8698 __ ld_ptr($poll$$Register, 0, G0);
8699 %}
8700 ins_pipe(loadPollP);
8701 %}
8703 // ============================================================================
8704 // Call Instructions
8705 // Call Java Static Instruction
8706 instruct CallStaticJavaDirect( method meth ) %{
8707 match(CallStaticJava);
8708 effect(USE meth);
8710 size(8);
8711 ins_cost(CALL_COST);
8712 format %{ "CALL,static ; NOP ==> " %}
8713 ins_encode( Java_Static_Call( meth ), call_epilog );
8714 ins_pc_relative(1);
8715 ins_pipe(simple_call);
8716 %}
8718 // Call Java Dynamic Instruction
8719 instruct CallDynamicJavaDirect( method meth ) %{
8720 match(CallDynamicJava);
8721 effect(USE meth);
8723 ins_cost(CALL_COST);
8724 format %{ "SET (empty),R_G5\n\t"
8725 "CALL,dynamic ; NOP ==> " %}
8726 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
8727 ins_pc_relative(1);
8728 ins_pipe(call);
8729 %}
8731 // Call Runtime Instruction
8732 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
8733 match(CallRuntime);
8734 effect(USE meth, KILL l7);
8735 ins_cost(CALL_COST);
8736 format %{ "CALL,runtime" %}
8737 ins_encode( Java_To_Runtime( meth ),
8738 call_epilog, adjust_long_from_native_call );
8739 ins_pc_relative(1);
8740 ins_pipe(simple_call);
8741 %}
8743 // Call runtime without safepoint - same as CallRuntime
8744 instruct CallLeafDirect(method meth, l7RegP l7) %{
8745 match(CallLeaf);
8746 effect(USE meth, KILL l7);
8747 ins_cost(CALL_COST);
8748 format %{ "CALL,runtime leaf" %}
8749 ins_encode( Java_To_Runtime( meth ),
8750 call_epilog,
8751 adjust_long_from_native_call );
8752 ins_pc_relative(1);
8753 ins_pipe(simple_call);
8754 %}
8756 // Call runtime without safepoint - same as CallLeaf
8757 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
8758 match(CallLeafNoFP);
8759 effect(USE meth, KILL l7);
8760 ins_cost(CALL_COST);
8761 format %{ "CALL,runtime leaf nofp" %}
8762 ins_encode( Java_To_Runtime( meth ),
8763 call_epilog,
8764 adjust_long_from_native_call );
8765 ins_pc_relative(1);
8766 ins_pipe(simple_call);
8767 %}
8769 // Tail Call; Jump from runtime stub to Java code.
8770 // Also known as an 'interprocedural jump'.
8771 // Target of jump will eventually return to caller.
8772 // TailJump below removes the return address.
8773 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
8774 match(TailCall jump_target method_oop );
8776 ins_cost(CALL_COST);
8777 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
8778 ins_encode(form_jmpl(jump_target));
8779 ins_pipe(tail_call);
8780 %}
8783 // Return Instruction
8784 instruct Ret() %{
8785 match(Return);
8787 // The epilogue node did the ret already.
8788 size(0);
8789 format %{ "! return" %}
8790 ins_encode();
8791 ins_pipe(empty);
8792 %}
8795 // Tail Jump; remove the return address; jump to target.
8796 // TailCall above leaves the return address around.
8797 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
8798 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
8799 // "restore" before this instruction (in Epilogue), we need to materialize it
8800 // in %i0.
8801 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
8802 match( TailJump jump_target ex_oop );
8803 ins_cost(CALL_COST);
8804 format %{ "! discard R_O7\n\t"
8805 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
8806 ins_encode(form_jmpl_set_exception_pc(jump_target));
8807 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
8808 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
8809 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
8810 ins_pipe(tail_call);
8811 %}
8813 // Create exception oop: created by stack-crawling runtime code.
8814 // Created exception is now available to this handler, and is setup
8815 // just prior to jumping to this handler. No code emitted.
8816 instruct CreateException( o0RegP ex_oop )
8817 %{
8818 match(Set ex_oop (CreateEx));
8819 ins_cost(0);
8821 size(0);
8822 // use the following format syntax
8823 format %{ "! exception oop is in R_O0; no code emitted" %}
8824 ins_encode();
8825 ins_pipe(empty);
8826 %}
8829 // Rethrow exception:
8830 // The exception oop will come in the first argument position.
8831 // Then JUMP (not call) to the rethrow stub code.
8832 instruct RethrowException()
8833 %{
8834 match(Rethrow);
8835 ins_cost(CALL_COST);
8837 // use the following format syntax
8838 format %{ "Jmp rethrow_stub" %}
8839 ins_encode(enc_rethrow);
8840 ins_pipe(tail_call);
8841 %}
8844 // Die now
8845 instruct ShouldNotReachHere( )
8846 %{
8847 match(Halt);
8848 ins_cost(CALL_COST);
8850 size(4);
8851 // Use the following format syntax
8852 format %{ "ILLTRAP ; ShouldNotReachHere" %}
8853 ins_encode( form2_illtrap() );
8854 ins_pipe(tail_call);
8855 %}
8857 // ============================================================================
8858 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
8859 // array for an instance of the superklass. Set a hidden internal cache on a
8860 // hit (cache is checked with exposed code in gen_subtype_check()). Return
8861 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
8862 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
8863 match(Set index (PartialSubtypeCheck sub super));
8864 effect( KILL pcc, KILL o7 );
8865 ins_cost(DEFAULT_COST*10);
8866 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
8867 ins_encode( enc_PartialSubtypeCheck() );
8868 ins_pipe(partial_subtype_check_pipe);
8869 %}
8871 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
8872 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
8873 effect( KILL idx, KILL o7 );
8874 ins_cost(DEFAULT_COST*10);
8875 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
8876 ins_encode( enc_PartialSubtypeCheck() );
8877 ins_pipe(partial_subtype_check_pipe);
8878 %}
8881 // ============================================================================
8882 // inlined locking and unlocking
8884 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
8885 match(Set pcc (FastLock object box));
8887 effect(KILL scratch, TEMP scratch2);
8888 ins_cost(100);
8890 size(4*112); // conservative overestimation ...
8891 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
8892 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
8893 ins_pipe(long_memory_op);
8894 %}
8897 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
8898 match(Set pcc (FastUnlock object box));
8899 effect(KILL scratch, TEMP scratch2);
8900 ins_cost(100);
8902 size(4*120); // conservative overestimation ...
8903 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
8904 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
8905 ins_pipe(long_memory_op);
8906 %}
8908 // Count and Base registers are fixed because the allocator cannot
8909 // kill unknown registers. The encodings are generic.
8910 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
8911 match(Set dummy (ClearArray cnt base));
8912 effect(TEMP temp, KILL ccr);
8913 ins_cost(300);
8914 format %{ "MOV $cnt,$temp\n"
8915 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
8916 " BRge loop\t\t! Clearing loop\n"
8917 " STX G0,[$base+$temp]\t! delay slot" %}
8918 ins_encode( enc_Clear_Array(cnt, base, temp) );
8919 ins_pipe(long_memory_op);
8920 %}
8922 instruct string_compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
8923 o7RegI tmp3, flagsReg ccr) %{
8924 match(Set result (StrComp str1 str2));
8925 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3);
8926 ins_cost(300);
8927 format %{ "String Compare $str1,$str2 -> $result" %}
8928 ins_encode( enc_String_Compare(str1, str2, tmp1, tmp2, result) );
8929 ins_pipe(long_memory_op);
8930 %}
8932 // ============================================================================
8933 //------------Bytes reverse--------------------------------------------------
8935 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
8936 match(Set dst (ReverseBytesI src));
8937 effect(DEF dst, USE src);
8939 // Op cost is artificially doubled to make sure that load or store
8940 // instructions are preferred over this one which requires a spill
8941 // onto a stack slot.
8942 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
8943 size(8);
8944 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
8945 opcode(Assembler::lduwa_op3);
8946 ins_encode( form3_mem_reg_little(src, dst) );
8947 ins_pipe( iload_mem );
8948 %}
8950 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
8951 match(Set dst (ReverseBytesL src));
8952 effect(DEF dst, USE src);
8954 // Op cost is artificially doubled to make sure that load or store
8955 // instructions are preferred over this one which requires a spill
8956 // onto a stack slot.
8957 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
8958 size(8);
8959 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
8961 opcode(Assembler::ldxa_op3);
8962 ins_encode( form3_mem_reg_little(src, dst) );
8963 ins_pipe( iload_mem );
8964 %}
8966 // Load Integer reversed byte order
8967 instruct loadI_reversed(iRegI dst, memory src) %{
8968 match(Set dst (ReverseBytesI (LoadI src)));
8970 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8971 size(8);
8972 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
8974 opcode(Assembler::lduwa_op3);
8975 ins_encode( form3_mem_reg_little( src, dst) );
8976 ins_pipe(iload_mem);
8977 %}
8979 // Load Long - aligned and reversed
8980 instruct loadL_reversed(iRegL dst, memory src) %{
8981 match(Set dst (ReverseBytesL (LoadL src)));
8983 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8984 size(8);
8985 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
8987 opcode(Assembler::ldxa_op3);
8988 ins_encode( form3_mem_reg_little( src, dst ) );
8989 ins_pipe(iload_mem);
8990 %}
8992 // Store Integer reversed byte order
8993 instruct storeI_reversed(memory dst, iRegI src) %{
8994 match(Set dst (StoreI dst (ReverseBytesI src)));
8996 ins_cost(MEMORY_REF_COST);
8997 size(8);
8998 format %{ "STWA $src, $dst\t!asi=primary_little" %}
9000 opcode(Assembler::stwa_op3);
9001 ins_encode( form3_mem_reg_little( dst, src) );
9002 ins_pipe(istore_mem_reg);
9003 %}
9005 // Store Long reversed byte order
9006 instruct storeL_reversed(memory dst, iRegL src) %{
9007 match(Set dst (StoreL dst (ReverseBytesL src)));
9009 ins_cost(MEMORY_REF_COST);
9010 size(8);
9011 format %{ "STXA $src, $dst\t!asi=primary_little" %}
9013 opcode(Assembler::stxa_op3);
9014 ins_encode( form3_mem_reg_little( dst, src) );
9015 ins_pipe(istore_mem_reg);
9016 %}
9018 //----------PEEPHOLE RULES-----------------------------------------------------
9019 // These must follow all instruction definitions as they use the names
9020 // defined in the instructions definitions.
9021 //
9022 // peepmatch ( root_instr_name [preceeding_instruction]* );
9023 //
9024 // peepconstraint %{
9025 // (instruction_number.operand_name relational_op instruction_number.operand_name
9026 // [, ...] );
9027 // // instruction numbers are zero-based using left to right order in peepmatch
9028 //
9029 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
9030 // // provide an instruction_number.operand_name for each operand that appears
9031 // // in the replacement instruction's match rule
9032 //
9033 // ---------VM FLAGS---------------------------------------------------------
9034 //
9035 // All peephole optimizations can be turned off using -XX:-OptoPeephole
9036 //
9037 // Each peephole rule is given an identifying number starting with zero and
9038 // increasing by one in the order seen by the parser. An individual peephole
9039 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
9040 // on the command-line.
9041 //
9042 // ---------CURRENT LIMITATIONS----------------------------------------------
9043 //
9044 // Only match adjacent instructions in same basic block
9045 // Only equality constraints
9046 // Only constraints between operands, not (0.dest_reg == EAX_enc)
9047 // Only one replacement instruction
9048 //
9049 // ---------EXAMPLE----------------------------------------------------------
9050 //
9051 // // pertinent parts of existing instructions in architecture description
9052 // instruct movI(eRegI dst, eRegI src) %{
9053 // match(Set dst (CopyI src));
9054 // %}
9055 //
9056 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
9057 // match(Set dst (AddI dst src));
9058 // effect(KILL cr);
9059 // %}
9060 //
9061 // // Change (inc mov) to lea
9062 // peephole %{
9063 // // increment preceeded by register-register move
9064 // peepmatch ( incI_eReg movI );
9065 // // require that the destination register of the increment
9066 // // match the destination register of the move
9067 // peepconstraint ( 0.dst == 1.dst );
9068 // // construct a replacement instruction that sets
9069 // // the destination to ( move's source register + one )
9070 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
9071 // %}
9072 //
9074 // // Change load of spilled value to only a spill
9075 // instruct storeI(memory mem, eRegI src) %{
9076 // match(Set mem (StoreI mem src));
9077 // %}
9078 //
9079 // instruct loadI(eRegI dst, memory mem) %{
9080 // match(Set dst (LoadI mem));
9081 // %}
9082 //
9083 // peephole %{
9084 // peepmatch ( loadI storeI );
9085 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
9086 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
9087 // %}
9089 //----------SMARTSPILL RULES---------------------------------------------------
9090 // These must follow all instruction definitions as they use the names
9091 // defined in the instructions definitions.
9092 //
9093 // SPARC will probably not have any of these rules due to RISC instruction set.
9095 //----------PIPELINE-----------------------------------------------------------
9096 // Rules which define the behavior of the target architectures pipeline.