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src/cpu/mips/vm/disassembler_mips.cpp@4bfb40d1e17a
src/cpu/mips/vm/disassembler_mips.cpp
Wed, 29 Mar 2017 09:41:51 +0800
- author
- aoqi
- date
- Wed, 29 Mar 2017 09:41:51 +0800
- changeset 392
- 4bfb40d1e17a
- parent 379
- 00a9fa322917
- child 402
- 16a6a17346a7
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- -rw-r--r--
#4662 TieredCompilation is turned off.
TieredCompilation is not supported yet.
1 /*
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #ifdef USE_PRAGMA_IDENT_SRC
27 #pragma ident "@(#)disassembler_mips.cpp 1.35 03/12/23 16:36:14 JVM"
28 #endif
29 # include "precompiled.hpp"
30 # include "depChecker_mips.hpp"
31 # include "runtime/fprofiler.hpp"
34 class mips32_env : public DisassemblerEnv {
35 private:
36 nmethod* code;
37 outputStream* output;
38 public:
39 mips32_env(nmethod* rcode, outputStream* routput) {
40 code = rcode;
41 output = routput;
42 }
43 void print_label(intptr_t value);
44 void print_raw(const char* str) { output->print_raw(str); }
45 void print(const char* format, ...);
46 char* string_for_offset(intptr_t value);
47 char* string_for_constant(unsigned char* pc, intptr_t value, int is_decimal);
48 };
51 void mips32_env::print_label(intptr_t value) {
52 if (!Universe::is_fully_initialized()) {
53 output->print(INTPTR_FORMAT, value);
54 return;
55 }
56 address adr = (address) value;
57 if (StubRoutines::contains(adr)) {
58 StubCodeDesc* desc = StubCodeDesc::desc_for(adr);
59 const char * desc_name = "unknown stub";
60 if (desc != NULL) {
61 desc_name = desc->name();
62 }
63 output->print("Stub::%s", desc_name);
64 if (WizardMode) output->print(" " INTPTR_FORMAT, value);
65 } else {
66 output->print(INTPTR_FORMAT, value);
67 }
68 }
70 void mips32_env::print(const char* format, ...) {
71 va_list ap;
72 va_start(ap, format);
73 output->vprint(format, ap);
74 va_end(ap);
75 }
77 char* mips32_env::string_for_offset(intptr_t value) {
78 stringStream st;
79 if (!Universe::is_fully_initialized()) {
80 st.print("%d", value);
81 return st.as_string();
82 }
83 BarrierSet* bs = Universe::heap()->barrier_set();
84 BarrierSet::Name bsn = bs->kind();
86 if (bs->kind() == BarrierSet::CardTableModRef && (jbyte*) value == ((CardTableModRefBS*)(bs))->byte_map_base) {
87 st.print("word_map_base");
88 } else {
89 st.print("%d", value);
90 }
91 return st.as_string();
92 }
94 char* mips32_env::string_for_constant(unsigned char* pc, intptr_t value, int is_decimal) {
95 stringStream st;
96 oop obj = NULL;
97 #ifndef CORE
98 if (code && (obj = code->embeddedOop_at(pc))!=NULL) {
99 obj->print_value_on(&st);
100 } else
101 #endif
102 {
103 if (is_decimal == 1) {
104 st.print("%d", value);
105 } else {
106 st.print("0x%lx", value);
107 }
108 }
109 return st.as_string();
110 }
112 #define PRINT_NOP() \
113 env->print("nop");
115 #define PRINT_ORRI(OP) \
116 env->print("%s %s, %s, 0x%x", OP, as_Register(Assembler::rt(insn))->name(), \
117 as_Register(Assembler::rs(insn))->name(), \
118 (short)Assembler::low16(insn) )
120 #define PRINT_ORRL(OP) \
121 env->print("%s %s, %s, ", OP, as_Register(Assembler::rs(insn))->name(), \
122 as_Register(Assembler::rt(insn))->name()); \
123 env->print_label( (intptr_t)start + 4 + ((short)Assembler::low16(insn)<<2) )
125 #define PRINT_J(OP) \
126 env->print("%s ", (char*)OP); \
127 env->print_label( ( ( (intptr_t)start + 4 ) & 0xc0000000 ) | ( Assembler::low26(insn) << 2 ) ); \
128 env->print("");
130 #define PRINT_ORSL(OP) \
131 env->print("%s %s, ", OP, as_Register(Assembler::rs(insn))->name()); \
132 env->print_label( (intptr_t)start + 4 + (short)Assembler::low16(insn) ); \
133 env->print("");
135 #define PRINT_OROB(OP) \
136 env->print("%s %s, 0x%x(%s)", OP, as_Register(Assembler::rt(insn))->name(), \
137 (short)Assembler::low16(insn), \
138 as_Register(Assembler::rs(insn))->name() )
140 #define PRINT_OFOB(OP) \
141 env->print("%s %s, 0x%x(%s)", OP, as_FloatRegister(Assembler::rt(insn))->name(), \
142 (short)Assembler::low16(insn), \
143 as_Register(Assembler::rs(insn))->name() )
146 #define PRINT_ORRS(OP) \
147 env->print("%s %s, %s, %d", OP, as_Register(Assembler::rd(insn))->name(), \
148 as_Register(Assembler::rt(insn))->name(), \
149 Assembler::sa(insn) )
151 #define PRINT_ORRR(OP) \
152 env->print("%s %s, %s, %s", OP, as_Register(Assembler::rd(insn))->name(), \
153 as_Register(Assembler::rs(insn))->name(), \
154 as_Register(Assembler::rt(insn))->name() )
156 #define PRINT_ORRII(OP) \
157 env->print("%s %s, %s, 0x%x, 0x%x", OP,as_Register(Assembler::rt(insn))->name(), \
158 as_Register(Assembler::rs(insn))->name(), \
159 ((short)Assembler::low(insn, 11)), \
160 ((short)Assembler::low(insn, 6)) )
162 #define PRINT_ORRRI_GSLDC2(OP) \
163 env->print("%s %s, 0x%x(%s, %s)", OP, is_float?as_FloatRegister(Assembler::rt(insn))->name():as_Register(Assembler::rt(insn))->name(), \
164 ((short)Assembler::low(insn, 11) >> 3), \
165 as_Register(Assembler::rs(insn))->name(), \
166 as_Register(Assembler::rd(insn))->name())
168 #define PRINT_COP1X(OP) \
169 env->print("%s %s, %s, %s, %s", OP, as_FloatRegister(Assembler::sa(insn))->name(), \
170 as_FloatRegister(Assembler::rt(insn))->name(), \
171 as_FloatRegister(Assembler::rd(insn))->name(), \
172 as_FloatRegister(Assembler::rs(insn))->name())
174 /*
175 * "<< 17 >> 23 << 4" is short for "<< 17 >> 17 >> 6 << 4". vAddr = sign_extend(offset << 4 ) + GPR[base]
176 * "<< 17 >> 17": sign-extending
177 * ">> 6": offset pos
178 * "<< 4": offset << 4
179 */
180 #define PRINT_ORRRI_GSLQ(OP) \
181 env->print("%s %s, %s, %d(%s)", OP, as_Register((insn)&0x1f)->name(), \
182 as_Register(Assembler::rt(insn))->name(), (Assembler::low(insn, 15) << 17 >> 23 << 4), \
183 as_Register(Assembler::rs(insn))->name())
185 #define PRINT_ORRR_2(OP) \
186 env->print("%s %s, %s, %s", OP, as_Register(Assembler::rd(insn))->name(), \
187 as_Register(Assembler::rt(insn))->name(), \
188 as_Register(Assembler::rs(insn))->name() )
190 #define PRINT_ORS(OP) \
191 env->print("%s %s", OP, as_Register(Assembler::rs(insn))->name())
193 #define PRINT_ORD(OP) \
194 env->print("%s %s", OP, as_Register(Assembler::rd(insn))->name())
196 #define PRINT_ORR(OP) \
197 env->print("%s %s, %s", OP, as_Register(Assembler::rs(insn))->name(), \
198 as_Register(Assembler::rt(insn))->name())
200 #define PRINT_ORR_2(OP) \
201 env->print("%s %s, %s", OP, as_Register(Assembler::rt(insn))->name(), \
202 as_Register(Assembler::rd(insn))->name())
204 #define PRINT_FLOAT(OP) \
205 env->print("%s.%s %s, %s, %s", OP, fmt, as_FloatRegister(Assembler::sa(insn))->name(), \
206 as_FloatRegister(Assembler::rd(insn))->name(), \
207 as_FloatRegister(Assembler::rt(insn))->name() )
209 #define PRINT_CVT(OP) \
210 env->print("%s.%s %s, %s", OP, fmt, as_FloatRegister(Assembler::sa(insn))->name(), \
211 as_FloatRegister(Assembler::rd(insn))->name() )
213 #define PRINT_C_COND_FMT(OP) \
214 env->print("%s.%s $fcc%d, %s, %s", OP, fmt, fcc, as_FloatRegister(Assembler::rt(insn))->name(), \
215 as_FloatRegister(Assembler::rd(insn))->name())
217 static const char* fmt_str(int fmt) {
218 switch(fmt) {
219 case Assembler::single_fmt:
220 return "s";
221 case Assembler::double_fmt:
222 return "d";
223 case Assembler::word_fmt:
224 return "w";
225 case Assembler::long_fmt:
226 return "l";
227 case Assembler::ps_fmt:
228 return "ps";
229 }
231 return "";
232 }
234 address Disassembler::decode_instruction(address start, DisassemblerEnv* env) {
235 int insn = *(int*)start;
236 int opcode = Assembler::opcode(insn);
237 int special;
238 const char *fmt;
239 int flag = 0;
240 int fcc = 0;
242 if (insn == 0)
243 {
244 PRINT_NOP();
245 return start+4;
246 }
248 switch(opcode) {
249 // case op
250 // case special_op
251 // case regimm_op
252 // case cop0_op not
253 // case cop1_op
254 // case cop2_op not
255 // case cop1x_op
256 // case special2_op
257 // case special3_op
258 // case gs_lwc2_op
259 // case gs_ldc2_op
260 // case gs_swc2_op
261 // case gs_sdc2_op
262 case Assembler::j_op:
263 case Assembler::jal_op:
264 PRINT_J(Assembler::ops_name[opcode]);
265 break;
266 case Assembler::beq_op:
267 case Assembler::bne_op:
268 case Assembler::blez_op:
269 case Assembler::bgtz_op:
270 PRINT_ORRL(Assembler::ops_name[opcode]);
271 break;
272 case Assembler::addi_op:
273 case Assembler::addiu_op:
274 case Assembler::slti_op:
275 case Assembler::sltiu_op:
276 case Assembler::ori_op:
277 case Assembler::andi_op:
278 case Assembler::xori_op:
279 case Assembler::daddi_op:
280 case Assembler::daddiu_op:
281 PRINT_ORRI(Assembler::ops_name[opcode]);
282 break;
283 case Assembler::lui_op:
284 env->print("lui %s, 0x%x", as_Register(Assembler::rt(insn))->name(), (short)Assembler::low16(insn) ); \
285 break;
286 case Assembler::beql_op:
287 case Assembler::bnel_op:
288 case Assembler::blezl_op:
289 case Assembler::bgtzl_op:
290 PRINT_ORRL(Assembler::ops_name[opcode]);
291 break;
292 case Assembler::ldl_op:
293 case Assembler::ldr_op:
294 case Assembler::lb_op:
295 case Assembler::lh_op:
296 case Assembler::lwl_op:
297 case Assembler::lw_op:
298 case Assembler::lbu_op:
299 case Assembler::lhu_op:
300 case Assembler::lwr_op:
301 case Assembler::lwu_op:
302 case Assembler::sb_op:
303 case Assembler::sh_op:
304 case Assembler::swl_op:
305 case Assembler::sw_op:
306 case Assembler::sdl_op:
307 case Assembler::sdr_op:
308 case Assembler::swr_op:
309 case Assembler::ll_op:
310 case Assembler::lld_op:
311 case Assembler::ld_op:
312 case Assembler::sc_op:
313 case Assembler::scd_op:
314 case Assembler::sd_op:
315 PRINT_OROB(Assembler::ops_name[opcode]);
316 break;
317 case Assembler::sdc1_op:
318 case Assembler::ldc1_op:
319 case Assembler::lwc1_op:
320 case Assembler::swc1_op:
321 PRINT_OFOB(Assembler::ops_name[opcode]);
322 break;
324 case Assembler::special_op: {
325 special = Assembler::special(insn);
326 switch(special) {
327 case Assembler::sll_op:
328 PRINT_ORRS(Assembler::special_name[special]);
329 break;
330 case Assembler::srl_op:
331 if (insn & (1 << 21)) {
332 PRINT_ORRS("rotr");
333 } else {
334 PRINT_ORRS(Assembler::special_name[special]);
335 }
336 break;
337 case Assembler::sra_op:
338 PRINT_ORRS(Assembler::special_name[special]);
339 break;
340 case Assembler::dsll_op:
341 PRINT_ORRS(Assembler::special_name[special]);
342 break;
343 case Assembler::dsrl_op:
344 if (insn & (1 << 21)) {
345 PRINT_ORRS("drotr");
346 } else {
347 PRINT_ORRS(Assembler::special_name[special]);
348 }
349 break;
350 case Assembler::dsra_op:
351 PRINT_ORRS(Assembler::special_name[special]);
352 break;
353 case Assembler::dsll32_op:
354 PRINT_ORRS(Assembler::special_name[special]);
355 break;
356 case Assembler::dsrl32_op:
357 if (insn & (1 << 21)) {
358 PRINT_ORRS("drotr32");
359 } else {
360 PRINT_ORRS(Assembler::special_name[special]);
361 }
362 break;
363 case Assembler::dsra32_op:
364 PRINT_ORRS(Assembler::special_name[special]);
365 break;
367 case Assembler::movci_op:
368 flag = insn & (1 << 16);
369 if (flag) {
370 env->print("movt %s, %s", as_Register(Assembler::rd(insn))->name(), as_Register(Assembler::rs(insn))->name());
371 } else {
372 env->print("movf %s, %s", as_Register(Assembler::rd(insn))->name(), as_Register(Assembler::rs(insn))->name());
373 }
374 break;
376 case Assembler::sllv_op:
377 PRINT_ORRR_2(Assembler::special_name[special]);
378 break;
379 case Assembler::srlv_op:
380 if (insn & (1 << 6)) {
381 PRINT_ORRR_2("rotrv");
382 } else {
383 PRINT_ORRR_2(Assembler::special_name[special]);
384 }
385 break;
386 case Assembler::srav_op:
387 PRINT_ORRR_2(Assembler::special_name[special]);
388 break;
389 case Assembler::dsllv_op:
390 PRINT_ORRR_2(Assembler::special_name[special]);
391 break;
392 case Assembler::dsrlv_op:
393 if (insn & (1 << 6)) {
394 PRINT_ORRR_2("drotrv");
395 } else {
396 PRINT_ORRR_2(Assembler::special_name[special]);
397 }
398 break;
399 case Assembler::dsrav_op:
400 PRINT_ORRR_2(Assembler::special_name[special]);
401 break;
403 case Assembler::jr_op:
404 case Assembler::jalr_op:
405 case Assembler::mthi_op:
406 case Assembler::mtlo_op:
407 PRINT_ORS(Assembler::special_name[special]);
408 break;
410 case Assembler::syscall_op:
411 case Assembler::break_op:
412 env->print("%s 0x%x\n", Assembler::special_name[special], bitfield(insn, 6, 20)>>10);
413 break;
415 case Assembler::sync_op:
416 env->print("sync\n");
417 break;
419 case Assembler::mfhi_op:
420 case Assembler::mflo_op:
421 PRINT_ORD(Assembler::special_name[special]);
422 break;
424 case Assembler::mult_op:
425 case Assembler::multu_op:
426 case Assembler::div_op:
427 case Assembler::divu_op:
428 case Assembler::dmult_op:
429 case Assembler::dmultu_op:
430 case Assembler::ddiv_op:
431 case Assembler::ddivu_op:
432 PRINT_ORR(Assembler::special_name[special]);
433 break;
435 case Assembler::add_op:
436 case Assembler::addu_op:
437 case Assembler::sub_op:
438 case Assembler::subu_op:
439 case Assembler::and_op:
440 case Assembler::or_op:
441 case Assembler::xor_op:
442 case Assembler::nor_op:
443 case Assembler::slt_op:
444 case Assembler::sltu_op:
445 case Assembler::movz_op:
446 case Assembler::movn_op:
447 case Assembler::dadd_op:
448 case Assembler::daddu_op:
449 case Assembler::dsub_op:
450 case Assembler::dsubu_op:
451 PRINT_ORRR(Assembler::special_name[special]);
452 break;
454 case Assembler::tge_op:
455 case Assembler::tgeu_op:
456 case Assembler::tlt_op:
457 case Assembler::tltu_op:
458 case Assembler::teq_op:
459 case Assembler::tne_op:
460 env->print("%s 0x%x, %s, %s\n", Assembler::special_name[special], bitfield(insn, 6, 10),
461 as_Register(Assembler::rs(insn))->name(),
462 as_Register(Assembler::rt(insn))->name() );
463 break;
465 default:
466 //Unimplemented();
467 env->print("0x%x\n", insn);
468 }
469 break;
470 } //special_op
472 case Assembler::regimm_op: {
473 special = Assembler::rt(insn);
474 switch(special) {
475 case Assembler::bltz_op:
476 case Assembler::bgez_op:
477 case Assembler::bltzl_op:
478 case Assembler::bgezl_op:
479 case Assembler::bltzal_op:
480 case Assembler::bgezal_op:
481 case Assembler::bltzall_op:
482 case Assembler::bgezall_op:
483 env->print("[%lx]%s %s, ", *(int *)start, Assembler::regimm_name[special], as_Register(Assembler::rs(insn))->name());
484 env->print_label( (intptr_t)start + 4 + 4 * (short)Assembler::low16(insn) );
485 break;
487 case Assembler::tgei_op:
488 case Assembler::tgeiu_op:
489 case Assembler::tlti_op:
490 case Assembler::tltiu_op:
491 case Assembler::teqi_op:
492 case Assembler::tnei_op:
493 env->print("%s %s, %d\n", Assembler::regimm_name[special],
494 as_Register(Assembler::rs(insn))->name(),
495 (short)Assembler::low16(insn));
496 break;
498 default:
499 //Unimplemented();
500 env->print("0x%x\n", insn);
501 }
502 break;
503 } //regimm_op
505 case Assembler::cop0_op: {
506 //Unimplemented();
507 break;
508 } //cop0_op
510 case Assembler::cop1_op: {
511 special = Assembler::rs(insn);
512 switch(special) {
513 case Assembler::mfc1_op:
514 env->print("mfc1 %s, %s", as_Register(Assembler::rt(insn))->name(), as_FloatRegister(Assembler::rd(insn))->name());
515 break;
516 case Assembler::mtc1_op:
517 env->print("mtc1 %s, %s", as_Register(Assembler::rt(insn))->name(), as_FloatRegister(Assembler::rd(insn))->name());
518 break;
519 case Assembler::cfc1_op:
520 PRINT_ORR_2("cfc1");
521 break;
522 case Assembler::ctc1_op:
523 PRINT_ORR_2("ctc1");
524 break;
525 case Assembler::dmfc1_op:
526 env->print("dmfc1 %s, %s", as_Register(Assembler::rt(insn))->name(), as_FloatRegister(Assembler::rd(insn))->name());
527 break;
528 case Assembler::dmtc1_op:
529 PRINT_ORR_2("dmtc1");
530 env->print("dmtc1 %s, %s", as_Register(Assembler::rt(insn))->name(), as_FloatRegister(Assembler::rd(insn))->name());
531 break;
533 case Assembler::bc1f_op:
534 special = Assembler::rt(insn);
535 fcc = (special >> 2) & 0x7;
536 special = special & 0x3;
537 switch(special) {
538 case Assembler::bcf_op:
539 env->print("bc1f $fcc%d ", fcc);
540 env->print_label( (intptr_t)start + 4 + (short)Assembler::low16(insn) );
541 //env->print("\n");
542 break;
543 case Assembler::bcfl_op:
544 env->print("bc1fl $fcc%d ", fcc);
545 env->print_label( (intptr_t)start + 4 + (short)Assembler::low16(insn) );
546 //env->print("\n");
547 break;
548 case Assembler::bct_op:
549 env->print("bc1t $fcc%d ", fcc);
550 env->print_label( (intptr_t)start + 4 + (short)Assembler::low16(insn) );
551 //env->print("\n");
552 break;
553 case Assembler::bctl_op:
554 env->print("bc1tl $fcc%d ", fcc);
555 env->print_label( (intptr_t)start + 4 + (short)Assembler::low16(insn) );
556 //env->print("\n");
557 break;
558 default:
559 //Unimplemented();
560 env->print("0x%x\n", insn);
561 }
562 break;
563 case Assembler::single_fmt:
564 case Assembler::double_fmt:
565 case Assembler::word_fmt:
566 case Assembler::long_fmt:
567 fmt = fmt_str(special);
568 special = Assembler::special(insn);
569 switch(special) {
570 case Assembler::fadd_op:
571 case Assembler::fsub_op:
572 case Assembler::fmul_op:
573 case Assembler::fdiv_op:
574 case Assembler::fsqrt_op:
575 case Assembler::fabs_op:
576 case Assembler::fmov_op:
577 case Assembler::fneg_op:
578 case Assembler::froundl_op:
579 case Assembler::ftruncl_op:
580 case Assembler::fceill_op:
581 case Assembler::ffloorl_op:
582 case Assembler::froundw_op:
583 case Assembler::ftruncw_op:
584 case Assembler::fceilw_op:
585 case Assembler::ffloorw_op:
586 PRINT_FLOAT(Assembler::cop1_name[special]);
587 break;
589 case Assembler::fcvts_op:
590 PRINT_CVT("cvt.s");
591 break;
592 case Assembler::fcvtd_op:
593 PRINT_CVT("cvt.d");
594 break;
595 case Assembler::fcvtw_op:
596 PRINT_CVT("cvt.w");
597 break;
598 case Assembler::fcvtl_op:
599 PRINT_CVT("cvt.l");
600 break;
601 case Assembler::fcvtps_op:
602 assert(Assembler::rs(insn) == Assembler::single_fmt, "");
603 env->print("cvt.ps.s %s, %s, %s", as_FloatRegister(Assembler::sa(insn))->name(), as_FloatRegister(Assembler::rd(insn))->name(), as_FloatRegister(Assembler::rt(insn))->name());
604 break;
605 case Assembler::f_cond:
606 case Assembler::un_cond:
607 case Assembler::eq_cond:
608 case Assembler::ueq_cond:
609 case Assembler::olt_cond:
610 case Assembler::ult_cond:
611 case Assembler::ole_cond:
612 case Assembler::ule_cond:
613 case Assembler::sf_cond:
614 case Assembler::ngle_cond:
615 case Assembler::seq_cond:
616 case Assembler::ngl_cond:
617 case Assembler::lt_cond:
618 case Assembler::nge_cond:
619 case Assembler::le_cond:
620 case Assembler::ngt_cond:
621 fcc = (insn >> 8) & 0x7;
622 PRINT_C_COND_FMT(Assembler::cop1_name[special]);
623 break;
624 default:
625 //tty->print_cr("0x%x(%x)", insn, opcode);
626 //Unimplemented();
627 env->print("0x%x\n", insn);
628 }
629 break;
630 case Assembler::ps_fmt:
631 fmt = fmt_str(special);
632 special = Assembler::special(insn);
633 switch(special) {
634 case Assembler::fadd_op:
635 case Assembler::fsub_op:
636 case Assembler::fmul_op:
637 case Assembler::fabs_op:
638 case Assembler::fmov_op:
639 case Assembler::fneg_op:
640 PRINT_FLOAT(Assembler::cop1_name[special]);
641 break;
642 default:
643 //tty->print_cr("0x%x(%x)", insn, opcode);
644 //Unimplemented();
645 env->print("0x%x\n", insn);
646 }
647 }
648 break;
649 } //cop1_op
651 case Assembler::gs_cop2_op: {
652 //Unimplemented();
653 env->print("0x%x\n", insn);
654 break;
655 } //gs_cop2_op
657 case Assembler::cop1x_op: {
658 special = Assembler::special(insn);
659 switch(special) {
660 case Assembler::madd_s_op:
661 case Assembler::madd_d_op:
662 case Assembler::madd_ps_op:
663 case Assembler::msub_s_op:
664 case Assembler::msub_d_op:
665 case Assembler::msub_ps_op:
666 case Assembler::nmadd_s_op:
667 case Assembler::nmadd_d_op:
668 case Assembler::nmadd_ps_op:
669 case Assembler::nmsub_s_op:
670 case Assembler::nmsub_d_op:
671 case Assembler::nmsub_ps_op:
672 PRINT_COP1X(Assembler::cop1x_name[Assembler::special(insn)]);
673 break;
674 }
675 break;
676 } //cop1x_op
678 case Assembler::special2_op: {
679 special = Assembler::special(insn);
680 switch(special) {
681 case Assembler::mul_op:
682 case Assembler::gsdiv_op:
683 case Assembler::gsddiv_op:
684 case Assembler::gsmod_op:
685 case Assembler::gsdmod_op:
686 case Assembler::gsdmult_op:
687 PRINT_ORRR(Assembler::special2_name[special]);
688 break;
689 case Assembler::madd_op:
690 case Assembler::msub_op:
691 PRINT_ORR(Assembler::special2_name[special]);
692 break;
693 case Assembler::gs0x03_op:
694 if ( (insn & (0x1f << 6)) == (18 << 6) ) {
695 PRINT_ORR("gsandn");
696 }
697 break;
698 case Assembler::gs0x06_op:
699 if ( (insn & (0x1f << 6)) == (18 << 6) ) {
700 PRINT_ORR("gsorn");
701 }
702 break;
703 }
704 break;
705 } //special2_op
707 case Assembler::special3_op: {
708 special = Assembler::special(insn);
709 int msb = (insn>>11) & 0x1f;
710 int lsb = (insn>>6) & 0x1f;
711 switch(special) {
712 case Assembler::ext_op:
713 env->print("ext, %s, %s, 0x%x, 0x%x", as_Register(Assembler::rt(insn))->name(),
714 as_Register(Assembler::rs(insn))->name(), lsb, msb + 1);
715 break;
716 case Assembler::dext_op:
717 env->print("dext, %s, %s, 0x%x, 0x%x", as_Register(Assembler::rt(insn))->name(),
718 as_Register(Assembler::rs(insn))->name(), lsb, msb + 1);
719 break;
720 case Assembler::ins_op:
721 env->print("ins, %s, %s, 0x%x, 0x%x", as_Register(Assembler::rt(insn))->name(),
722 as_Register(Assembler::rs(insn))->name(), lsb, msb - lsb + 1);
723 break;
724 case Assembler::dinsm_op:
725 env->print("dinsm, %s, %s, 0x%x, 0x%x", as_Register(Assembler::rt(insn))->name(),
726 as_Register(Assembler::rs(insn))->name(), lsb, msb - lsb + 33);
727 break;
728 case Assembler::dinsu_op:
729 env->print("dinsu, %s, %s, 0x%x, 0x%x", as_Register(Assembler::rt(insn))->name(),
730 as_Register(Assembler::rs(insn))->name(), lsb + 32, msb - lsb + 1);
731 break;
732 case Assembler::dins_op:
733 env->print("dins, %s, %s, 0x%x, 0x%x", as_Register(Assembler::rt(insn))->name(),
734 as_Register(Assembler::rs(insn))->name(), lsb, msb - lsb + 1);
735 break;
736 case Assembler::re1_op: {
737 int dsp = (insn>>6)&0x1f;
738 bool op_is_imm = false;
739 switch(dsp) {
740 case Assembler::repl_qb_op:
741 case Assembler::repl_ph_op:
742 op_is_imm = true;
743 case Assembler::absq_s_qb_op:
744 case Assembler::replv_qb_op:
745 case Assembler::absq_s_ph_op:
746 case Assembler::replv_ph_op:
747 case Assembler::absq_s_w_op:
748 case Assembler::bitrev_op: {
749 const char* dsp_names[] = {
750 "", "absq_s.qb", "repl.qb", "replv.qb", "precequ.ph.qbl", "precequ.ph.qbr", "precequ.ph.qbla", "precequ.ph.qbra",
751 "", "absq_s.ph", "repl.ph", "replv.ph", "preceq.w.phl", "preceq.w.phr", "", "",
752 "", "absq_s.w", "", "", "", "", "", "",
753 "", "", "", "bitrev", "preceu.ph.qbl", "preceu.ph.qbr", "preceu.ph.qbla", "preceu.ph.qbra"
754 };
755 if (op_is_imm)
756 env->print("%s %s, 0x%x", dsp_names[dsp], as_Register(Assembler::rd(insn))->name(), (insn>>16)&0x3ff);
757 else
758 env->print("%s %s, %s", dsp_names[dsp], as_Register(Assembler::rd(insn))->name(), as_Register(Assembler::rt(insn))->name());
759 break;
760 }
761 default:
762 break;
763 }
764 break;
765 } //Assembler::re1_op
766 case Assembler::re2_op: {
767 int dsp = (insn>>6)&0x1f;
768 bool op_is_imm = false;
769 switch(dsp) {
770 case Assembler::repl_ob_op:
771 case Assembler::repl_qh_op:
772 op_is_imm = true;
773 case Assembler::replv_ob_op:
774 case Assembler::absq_s_qh_op:
775 case Assembler::replv_qh_op:
776 case Assembler::absq_s_pw_op:
777 case Assembler::repl_pw_op:
778 case Assembler::replv_pw_op: {
780 const char* dsp_names[] = {
781 "", "", "", "", "", "", "", "",
782 "", "absq_s.qh", "repl.qh", "replv.qh", "preceq.pw.qhl", "preceq.pw.qhr", "preceq.pw.phla ", "preceq.pw.phra",
783 "", "absq_s.pw", "repl.pw", "replv.pw", "preceq.l.pwl", "preceq.l.pwr", "", "",
784 "", "", "", "", "preceu.qh.obl", "preceu.qh.obr", "preceu.qh.obla", "preceu.qh.obra"
785 };
786 if (op_is_imm)
787 env->print("%s %s, 0x%x", dsp_names[dsp], as_Register(Assembler::rd(insn))->name(), (insn>>16)&0x3ff);
788 else
789 env->print("%s %s, %s", dsp_names[dsp], as_Register(Assembler::rd(insn))->name(), as_Register(Assembler::rt(insn))->name());
790 break;
791 }
792 default:
793 break;
794 }
795 break;
796 } //Assembler::re2_op
797 case Assembler::bshfl_op:
798 if ( (insn & (0x1f << 6)) == (Assembler::seb_op << 6) ) {
799 env->print("seb, %s, %s", as_Register(Assembler::rd(insn))->name(), as_Register(Assembler::rt(insn))->name());
800 } else if ( (insn & (0x1f << 6)) == (Assembler::seh_op << 6) ) {
801 env->print("seh, %s, %s", as_Register(Assembler::rd(insn))->name(), as_Register(Assembler::rt(insn))->name());
802 } else {
803 env->print("Invalid instruction");
804 }
805 break;
806 }
807 break;
808 } //special3_op
810 case Assembler::gs_lwc2_op: {
811 if ((Assembler::special(insn) & 0x20) != 0 ) {
812 //gslq rq, rt, offset(base)
813 if ( (insn & (1 << 15)) == 0) {
814 special = Assembler::gslq_op;
815 PRINT_ORRRI_GSLQ(Assembler::gs_lwc2_name[special]);
816 } else {
817 //gsLQC1
818 env->print("gs_lwc2_op 0x%x\n", insn);
819 }
820 } else {
821 env->print("gs_lwc2_op 0x%x\n", insn);
822 }
823 break;
824 } //gs_lwc2_op
826 case Assembler::gs_ldc2_op: {
827 special = Assembler::special(insn) & 0x7;
828 bool is_float = false;
829 switch(special) {
830 case Assembler::gslbx_op:
831 case Assembler::gslhx_op:
832 case Assembler::gslwx_op:
833 case Assembler::gsldx_op:
834 PRINT_ORRRI_GSLDC2(Assembler::gs_ldc2_name[special]);
835 break;
836 case Assembler::gslwxc1_op:
837 case Assembler::gsldxc1_op:
838 is_float = true;
839 PRINT_ORRRI_GSLDC2(Assembler::gs_ldc2_name[special]);
840 break;
841 default:
842 break;
843 }
844 break;
845 } //gs_ldc2_op
847 case Assembler::gs_swc2_op: {
848 if ((Assembler::special(insn) & 0x20) != 0 ) {
849 //gssq rq, rt, offset(base)
850 if ( (insn & (1 << 15)) == 0) {
851 //gsSQ
852 special = Assembler::gssq_op;
853 PRINT_ORRRI_GSLQ(Assembler::gs_swc2_name[special]);
854 } else {
855 //gsSQC1
856 env->print("0x%x\n", insn);
857 }
858 } else {
859 env->print("0x%x\n", insn);
860 }
861 break;
862 } //gs_swc2_op
864 case Assembler::gs_sdc2_op: {
865 special = Assembler::special(insn) & 0x7;
866 bool is_float = false;
867 switch(special) {
868 case Assembler::gssbx_op:
869 case Assembler::gsshx_op:
870 case Assembler::gsswx_op:
871 case Assembler::gssdx_op:
872 PRINT_ORRRI_GSLDC2(Assembler::gs_sdc2_name[special]);
873 break;
874 case Assembler::gsswxc1_op:
875 case Assembler::gssdxc1_op:
876 is_float = true;
877 PRINT_ORRRI_GSLDC2(Assembler::gs_sdc2_name[special]);
878 break;
879 default:
880 break;
881 }
882 break;
883 } //gs_sdc2_op
885 default:
886 //tty->print_cr("0x%x(%x)", insn, opcode);
887 //Unimplemented();
888 env->print("0x%x\n", insn);
889 }
891 return start+4;
892 }
894 /*
895 void Disassembler::decode(address start, address end, outputStream* st, CodeComments c) {
896 if (!load_library()) return;
897 decode_env env(CodeCache::find_blob_unsafe(start), st, c);
898 env.decode_instructions(start, end);
899 }
900 */
902 void Disassembler::decode(CodeBlob* cb, outputStream* st) {
903 #ifndef CORE
904 st = st ? st : tty;
905 st->print_cr("Decoding CodeBlob " INTPTR_FORMAT, cb);
906 decode(cb->content_begin(), cb->content_end(), st);
907 #endif
908 }
911 void Disassembler::decode(u_char* begin, u_char* end, outputStream* st) {
912 st = st ? st : tty;
914 const int show_bytes = false; // for disassembler debugging
916 mips32_env env(NULL, st);
917 unsigned char* p = (unsigned char*) begin;
918 CodeBlob* cb = CodeCache::find_blob_unsafe(begin);
919 while (p < (unsigned char*) end) {
920 if (cb != NULL) {
921 cb->print_block_comment(st, (unsigned char*)(p - cb->content_begin()));
922 }
924 unsigned char* p0 = p;
925 st->print(" "INTPTR_FORMAT ": ", p);
926 p = decode_instruction(p, &env);
927 if (show_bytes) {
928 st->print("\t\t\t");
929 while (p0 < p) st->print("%x ", *p0++);
930 }
931 st->cr();
932 }
933 }
936 void Disassembler::decode(nmethod* nm, outputStream* st) {
937 #ifndef CORE
938 st = st ? st : tty;
940 st->print_cr("Decoding compiled method " INTPTR_FORMAT ":", nm);
941 st->print("Code:");
942 st->cr();
944 mips32_env env(nm, st);
946 // Print constant table.
947 if (nm->consts_size() > 0) {
948 nm->print_nmethod_labels(st, nm->consts_begin());
949 int offset = 0;
950 for (address p = nm->consts_begin(); p < nm->consts_end(); p += 4, offset += 4) {
951 if ((offset % 8) == 0) {
952 st->print_cr(" " PTR_FORMAT " (offset: %4d): " PTR32_FORMAT " " PTR64_FORMAT, p, offset, *((int32_t*) p), *((int64_t*) p));
953 } else {
954 st->print_cr(" " PTR_FORMAT " (offset: %4d): " PTR32_FORMAT, p, offset, *((int32_t*) p));
955 }
956 }
957 }
959 #ifdef COMPILER1
960 unsigned char* p = nm->code_begin();
961 #else
962 unsigned char* p = nm->content_begin();
963 #endif
964 unsigned char* end = nm->content_end();
965 while (p < end) {
966 if (p == nm->entry_point()) st->print_cr("[Entry Point]");
967 if (p == nm->verified_entry_point()) st->print_cr("[Verified Entry Point]");
968 if (p == nm->exception_begin()) st->print_cr("[Exception Handler]");
969 if (p == nm->stub_begin()) st->print_cr("[Stub Code]");
970 if (p == nm->consts_begin()) st->print_cr("[Constants]");
971 nm->print_block_comment(st, (unsigned char*)(p - nm->content_begin()));
972 unsigned char* p0 = p;
973 st->print(" " INTPTR_FORMAT ": ", p);
974 p = decode_instruction(p, &env);
975 nm->print_code_comment_on(st, 40, p0, p);
976 st->cr();
977 // Output pc bucket ticks if we have any
978 address bucket_pc = FlatProfiler::bucket_start_for(p);
979 if (bucket_pc != NULL && bucket_pc > p0 && bucket_pc <= p) {
980 int bucket_count = FlatProfiler::bucket_count_for(bucket_pc);
981 tty->print_cr("[%d]", bucket_count);
982 }
983 }
984 #endif
985 }
