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1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #ifndef CPU_MIPS_VM_ASSEMBLER_MIPS_HPP
27 #define CPU_MIPS_VM_ASSEMBLER_MIPS_HPP
29 #include "asm/register.hpp"
31 class BiasedLockingCounters;
34 // Note: A register location is represented via a Register, not
35 // via an address for efficiency & simplicity reasons.
37 class ArrayAddress;
39 class Address VALUE_OBJ_CLASS_SPEC {
41 public:
42 enum ScaleFactor {
43 no_scale = -1,
44 times_1 = 0,
45 times_2 = 1,
46 times_4 = 2,
47 times_8 = 3,
48 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
49 };
51 static ScaleFactor times(int size) {
52 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
53 if (size == 8) return times_8;
54 if (size == 4) return times_4;
55 if (size == 2) return times_2;
56 return times_1;
57 }
59 private:
60 Register _base;
61 Register _index;
62 ScaleFactor _scale;
63 int _disp;
64 RelocationHolder _rspec;
66 // Easily misused constructors make them private
67 // %%% can we make these go away?
68 //FIXME aoqi
69 //NOT_LP64(Address(address loc, RelocationHolder spec);)
70 Address(address loc, RelocationHolder spec);
71 Address(int disp, address loc, relocInfo::relocType rtype);
72 Address(int disp, address loc, RelocationHolder spec);
74 public:
76 int disp() { return _disp; }
77 // creation
78 Address()
79 : _base(noreg),
80 _index(noreg),
81 _scale(no_scale),
82 _disp(0) {
83 }
85 // No default displacement otherwise Register can be implicitly
86 // converted to 0(Register) which is quite a different animal.
88 Address(Register base, int disp)
89 : _base(base),
90 _index(noreg),
91 _scale(no_scale),
92 _disp(disp) {
93 }
95 Address(Register base)
96 : _base(base),
97 _index(noreg),
98 _scale(no_scale),
99 _disp(0) {
100 }
102 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
103 : _base (base),
104 _index(index),
105 _scale(scale),
106 _disp (disp) {
107 assert(!index->is_valid() == (scale == Address::no_scale),
108 "inconsistent address");
109 }
111 // The following two overloads are used in connection with the
112 // ByteSize type (see sizes.hpp). They simplify the use of
113 // ByteSize'd arguments in assembly code. Note that their equivalent
114 // for the optimized build are the member functions with int disp
115 // argument since ByteSize is mapped to an int type in that case.
116 //
117 // Note: DO NOT introduce similar overloaded functions for WordSize
118 // arguments as in the optimized mode, both ByteSize and WordSize
119 // are mapped to the same type and thus the compiler cannot make a
120 // distinction anymore (=> compiler errors).
122 #ifdef ASSERT
123 Address(Register base, ByteSize disp)
124 : _base(base),
125 _index(noreg),
126 _scale(no_scale),
127 _disp(in_bytes(disp)) {
128 }
130 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
131 : _base(base),
132 _index(index),
133 _scale(scale),
134 _disp(in_bytes(disp)) {
135 assert(!index->is_valid() == (scale == Address::no_scale),
136 "inconsistent address");
137 }
138 #endif // ASSERT
140 // accessors
141 bool uses(Register reg) const { return _base == reg || _index == reg; }
142 Register base() const { return _base; }
143 Register index() const { return _index; }
144 ScaleFactor scale() const { return _scale; }
145 int disp() const { return _disp; }
147 // Convert the raw encoding form into the form expected by the constructor for
148 // Address. An index of 4 (rsp) corresponds to having no index, so convert
149 // that to noreg for the Address constructor.
150 //static Address make_raw(int base, int index, int scale, int disp);
152 static Address make_array(ArrayAddress);
154 /*
155 private:
156 bool base_needs_rex() const {
157 return _base != noreg && _base->encoding() >= 8;
158 }
160 bool index_needs_rex() const {
161 return _index != noreg &&_index->encoding() >= 8;
162 }
164 relocInfo::relocType reloc() const { return _rspec.type(); }
165 */
166 friend class Assembler;
167 friend class MacroAssembler;
168 friend class LIR_Assembler; // base/index/scale/disp
169 };
172 // Calling convention
173 class Argument VALUE_OBJ_CLASS_SPEC {
174 private:
175 int _number;
176 public:
177 enum {
178 #ifdef _LP64
179 n_register_parameters = 8, // 8 integer registers used to pass parameters
180 n_float_register_parameters = 8 // 4 float registers used to pass parameters
181 #else
182 n_register_parameters = 4, // 4 integer registers used to pass parameters
183 n_float_register_parameters = 4 // 4 float registers used to pass parameters
184 #endif
185 };
187 Argument(int number):_number(number){ }
188 Argument successor() {return Argument(number() + 1);}
190 int number()const {return _number;}
191 bool is_Register()const {return _number < n_register_parameters;}
192 bool is_FloatRegister()const {return _number < n_float_register_parameters;}
194 Register as_Register()const {
195 assert(is_Register(), "must be a register argument");
196 return ::as_Register(A0->encoding() + _number);
197 }
198 FloatRegister as_FloatRegister()const {
199 assert(is_FloatRegister(), "must be a float register argument");
200 return ::as_FloatRegister(F12->encoding() + _number);
201 }
203 Address as_caller_address()const {return Address(SP, (number() LP64_ONLY( -n_register_parameters)) * wordSize);}
204 };
208 //
209 // AddressLiteral has been split out from Address because operands of this type
210 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
211 // the few instructions that need to deal with address literals are unique and the
212 // MacroAssembler does not have to implement every instruction in the Assembler
213 // in order to search for address literals that may need special handling depending
214 // on the instruction and the platform. As small step on the way to merging i486/amd64
215 // directories.
216 //
217 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
218 friend class ArrayAddress;
219 RelocationHolder _rspec;
220 // Typically we use AddressLiterals we want to use their rval
221 // However in some situations we want the lval (effect address) of the item.
222 // We provide a special factory for making those lvals.
223 bool _is_lval;
225 // If the target is far we'll need to load the ea of this to
226 // a register to reach it. Otherwise if near we can do rip
227 // relative addressing.
229 address _target;
231 protected:
232 // creation
233 AddressLiteral()
234 : _is_lval(false),
235 _target(NULL)
236 {}
238 public:
240 AddressLiteral(address target, relocInfo::relocType rtype);
242 AddressLiteral(address target, RelocationHolder const& rspec)
243 : _rspec(rspec),
244 _is_lval(false),
245 _target(target)
246 {}
247 #ifdef _LP64
248 // 32-bit complains about a multiple declaration for int*.
249 AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none)
250 : _target((address) addr),
251 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
252 #endif
255 AddressLiteral addr() {
256 AddressLiteral ret = *this;
257 ret._is_lval = true;
258 return ret;
259 }
262 private:
264 address target() { return _target; }
265 bool is_lval() { return _is_lval; }
267 relocInfo::relocType reloc() const { return _rspec.type(); }
268 const RelocationHolder& rspec() const { return _rspec; }
270 friend class Assembler;
271 friend class MacroAssembler;
272 friend class Address;
273 friend class LIR_Assembler;
274 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
275 switch (rtype) {
276 case relocInfo::external_word_type:
277 return external_word_Relocation::spec(addr);
278 case relocInfo::internal_word_type:
279 return internal_word_Relocation::spec(addr);
280 case relocInfo::opt_virtual_call_type:
281 return opt_virtual_call_Relocation::spec();
282 case relocInfo::static_call_type:
283 return static_call_Relocation::spec();
284 case relocInfo::runtime_call_type:
285 return runtime_call_Relocation::spec();
286 case relocInfo::poll_type:
287 case relocInfo::poll_return_type:
288 return Relocation::spec_simple(rtype);
289 case relocInfo::none:
290 case relocInfo::oop_type:
291 // Oops are a special case. Normally they would be their own section
292 // but in cases like icBuffer they are literals in the code stream that
293 // we don't have a section for. We use none so that we get a literal address
294 // which is always patchable.
295 return RelocationHolder();
296 default:
297 ShouldNotReachHere();
298 return RelocationHolder();
299 }
300 }
302 };
304 // Convience classes
305 class RuntimeAddress: public AddressLiteral {
307 public:
309 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
311 };
313 class OopAddress: public AddressLiteral {
315 public:
317 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
319 };
321 class ExternalAddress: public AddressLiteral {
323 public:
325 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}
327 };
329 class InternalAddress: public AddressLiteral {
331 public:
333 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
335 };
337 // x86 can do array addressing as a single operation since disp can be an absolute
338 // address amd64 can't. We create a class that expresses the concept but does extra
339 // magic on amd64 to get the final result
341 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
342 private:
344 AddressLiteral _base;
345 Address _index;
347 public:
349 ArrayAddress() {};
350 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
351 AddressLiteral base() { return _base; }
352 Address index() { return _index; }
354 };
356 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
358 // The MIPS LOONGSON Assembler: Pure assembler doing NO optimizations on the instruction
359 // level ; i.e., what you write is what you get. The Assembler is generating code into
360 // a CodeBuffer.
362 class Assembler : public AbstractAssembler {
363 friend class AbstractAssembler; // for the non-virtual hack
364 friend class LIR_Assembler; // as_Address()
365 friend class StubGenerator;
367 public:
369 public:
371 static const int LogInstructionSize = 2;
372 static const int InstructionSize = 1 << LogInstructionSize;
374 // opcode, highest 6 bits: bits[31...26]
375 enum ops {
376 special_op = 0x00, // special_ops
377 regimm_op = 0x01, // regimm_ops
378 j_op = 0x02,
379 jal_op = 0x03,
380 beq_op = 0x04,
381 bne_op = 0x05,
382 blez_op = 0x06,
383 bgtz_op = 0x07,
384 addi_op = 0x08,
385 addiu_op = 0x09,
386 slti_op = 0x0a,
387 sltiu_op = 0x0b,
388 andi_op = 0x0c,
389 ori_op = 0x0d,
390 xori_op = 0x0e,
391 lui_op = 0x0f,
392 cop0_op = 0x10, // cop0_ops
393 cop1_op = 0x11, // cop1_ops
394 gs_cop2_op = 0x12, // gs_cop2_ops
395 cop1x_op = 0x13, // cop1x_ops
396 beql_op = 0x14,
397 bnel_op = 0x15,
398 blezl_op = 0x16,
399 bgtzl_op = 0x17,
400 daddi_op = 0x18,
401 daddiu_op = 0x19,
402 ldl_op = 0x1a,
403 ldr_op = 0x1b,
404 special2_op = 0x1c, // special2_ops
405 msa_op = 0x1e, // msa_ops
406 special3_op = 0x1f, // special3_ops
407 lb_op = 0x20,
408 lh_op = 0x21,
409 lwl_op = 0x22,
410 lw_op = 0x23,
411 lbu_op = 0x24,
412 lhu_op = 0x25,
413 lwr_op = 0x26,
414 lwu_op = 0x27,
415 sb_op = 0x28,
416 sh_op = 0x29,
417 swl_op = 0x2a,
418 sw_op = 0x2b,
419 sdl_op = 0x2c,
420 sdr_op = 0x2d,
421 swr_op = 0x2e,
422 cache_op = 0x2f,
423 ll_op = 0x30,
424 lwc1_op = 0x31,
425 gs_lwc2_op = 0x32, //gs_lwc2_ops
426 pref_op = 0x33,
427 lld_op = 0x34,
428 ldc1_op = 0x35,
429 gs_ldc2_op = 0x36, //gs_ldc2_ops
430 ld_op = 0x37,
431 sc_op = 0x38,
432 swc1_op = 0x39,
433 gs_swc2_op = 0x3a, //gs_swc2_ops
434 scd_op = 0x3c,
435 sdc1_op = 0x3d,
436 gs_sdc2_op = 0x3e, //gs_sdc2_ops
437 sd_op = 0x3f
438 };
440 static const char *ops_name[];
442 //special family, the opcode is in low 6 bits.
443 enum special_ops {
444 sll_op = 0x00,
445 movci_op = 0x01,
446 srl_op = 0x02,
447 sra_op = 0x03,
448 sllv_op = 0x04,
449 srlv_op = 0x06,
450 srav_op = 0x07,
451 jr_op = 0x08,
452 jalr_op = 0x09,
453 movz_op = 0x0a,
454 movn_op = 0x0b,
455 syscall_op = 0x0c,
456 break_op = 0x0d,
457 sync_op = 0x0f,
458 mfhi_op = 0x10,
459 mthi_op = 0x11,
460 mflo_op = 0x12,
461 mtlo_op = 0x13,
462 dsllv_op = 0x14,
463 dsrlv_op = 0x16,
464 dsrav_op = 0x17,
465 mult_op = 0x18,
466 multu_op = 0x19,
467 div_op = 0x1a,
468 divu_op = 0x1b,
469 dmult_op = 0x1c,
470 dmultu_op = 0x1d,
471 ddiv_op = 0x1e,
472 ddivu_op = 0x1f,
473 add_op = 0x20,
474 addu_op = 0x21,
475 sub_op = 0x22,
476 subu_op = 0x23,
477 and_op = 0x24,
478 or_op = 0x25,
479 xor_op = 0x26,
480 nor_op = 0x27,
481 slt_op = 0x2a,
482 sltu_op = 0x2b,
483 dadd_op = 0x2c,
484 daddu_op = 0x2d,
485 dsub_op = 0x2e,
486 dsubu_op = 0x2f,
487 tge_op = 0x30,
488 tgeu_op = 0x31,
489 tlt_op = 0x32,
490 tltu_op = 0x33,
491 teq_op = 0x34,
492 tne_op = 0x36,
493 dsll_op = 0x38,
494 dsrl_op = 0x3a,
495 dsra_op = 0x3b,
496 dsll32_op = 0x3c,
497 dsrl32_op = 0x3e,
498 dsra32_op = 0x3f
499 };
501 static const char* special_name[];
503 //regimm family, the opcode is in rt[16...20], 5 bits
504 enum regimm_ops {
505 bltz_op = 0x00,
506 bgez_op = 0x01,
507 bltzl_op = 0x02,
508 bgezl_op = 0x03,
509 tgei_op = 0x08,
510 tgeiu_op = 0x09,
511 tlti_op = 0x0a,
512 tltiu_op = 0x0b,
513 teqi_op = 0x0c,
514 tnei_op = 0x0e,
515 bltzal_op = 0x10,
516 bgezal_op = 0x11,
517 bltzall_op = 0x12,
518 bgezall_op = 0x13,
519 bposge32_op = 0x1c,
520 bposge64_op = 0x1d,
521 synci_op = 0x1f,
522 };
524 static const char* regimm_name[];
526 //cop0 family, the ops is in bits[25...21], 5 bits
527 enum cop0_ops {
528 mfc0_op = 0x00,
529 dmfc0_op = 0x01,
530 //
531 mxgc0_op = 0x03, //MFGC0, DMFGC0, MTGC0
532 mtc0_op = 0x04,
533 dmtc0_op = 0x05,
534 rdpgpr_op = 0x0a,
535 inter_op = 0x0b,
536 wrpgpr_op = 0x0c
537 };
539 //cop1 family, the ops is in bits[25...21], 5 bits
540 enum cop1_ops {
541 mfc1_op = 0x00,
542 dmfc1_op = 0x01,
543 cfc1_op = 0x02,
544 mfhc1_op = 0x03,
545 mtc1_op = 0x04,
546 dmtc1_op = 0x05,
547 ctc1_op = 0x06,
548 mthc1_op = 0x07,
549 bc1f_op = 0x08,
550 single_fmt = 0x10,
551 double_fmt = 0x11,
552 word_fmt = 0x14,
553 long_fmt = 0x15,
554 ps_fmt = 0x16
555 };
558 //2 bist (bits[17...16]) of bc1x instructions (cop1)
559 enum bc_ops {
560 bcf_op = 0x0,
561 bct_op = 0x1,
562 bcfl_op = 0x2,
563 bctl_op = 0x3,
564 };
566 // low 6 bits of c_x_fmt instructions (cop1)
567 enum c_conds {
568 f_cond = 0x30,
569 un_cond = 0x31,
570 eq_cond = 0x32,
571 ueq_cond = 0x33,
572 olt_cond = 0x34,
573 ult_cond = 0x35,
574 ole_cond = 0x36,
575 ule_cond = 0x37,
576 sf_cond = 0x38,
577 ngle_cond = 0x39,
578 seq_cond = 0x3a,
579 ngl_cond = 0x3b,
580 lt_cond = 0x3c,
581 nge_cond = 0x3d,
582 le_cond = 0x3e,
583 ngt_cond = 0x3f
584 };
586 // low 6 bits of cop1 instructions
587 enum float_ops {
588 fadd_op = 0x00,
589 fsub_op = 0x01,
590 fmul_op = 0x02,
591 fdiv_op = 0x03,
592 fsqrt_op = 0x04,
593 fabs_op = 0x05,
594 fmov_op = 0x06,
595 fneg_op = 0x07,
596 froundl_op = 0x08,
597 ftruncl_op = 0x09,
598 fceill_op = 0x0a,
599 ffloorl_op = 0x0b,
600 froundw_op = 0x0c,
601 ftruncw_op = 0x0d,
602 fceilw_op = 0x0e,
603 ffloorw_op = 0x0f,
604 movf_f_op = 0x11,
605 movt_f_op = 0x11,
606 movz_f_op = 0x12,
607 movn_f_op = 0x13,
608 frecip_op = 0x15,
609 frsqrt_op = 0x16,
610 fcvts_op = 0x20,
611 fcvtd_op = 0x21,
612 fcvtw_op = 0x24,
613 fcvtl_op = 0x25,
614 fcvtps_op = 0x26,
615 fcvtspl_op = 0x28,
616 fpll_op = 0x2c,
617 fplu_op = 0x2d,
618 fpul_op = 0x2e,
619 fpuu_op = 0x2f
620 };
622 static const char* cop1_name[];
624 //cop1x family, the opcode is in low 6 bits.
625 enum cop1x_ops {
626 lwxc1_op = 0x00,
627 ldxc1_op = 0x01,
628 luxc1_op = 0x05,
629 swxc1_op = 0x08,
630 sdxc1_op = 0x09,
631 suxc1_op = 0x0d,
632 prefx_op = 0x0f,
634 alnv_ps_op = 0x1e,
635 madd_s_op = 0x20,
636 madd_d_op = 0x21,
637 madd_ps_op = 0x26,
638 msub_s_op = 0x28,
639 msub_d_op = 0x29,
640 msub_ps_op = 0x2e,
641 nmadd_s_op = 0x30,
642 nmadd_d_op = 0x31,
643 nmadd_ps_op = 0x36,
644 nmsub_s_op = 0x38,
645 nmsub_d_op = 0x39,
646 nmsub_ps_op = 0x3e
647 };
649 static const char* cop1x_name[];
651 //special2 family, the opcode is in low 6 bits.
652 enum special2_ops {
653 madd_op = 0x00,
654 maddu_op = 0x01,
655 mul_op = 0x02,
656 gs0x03_op = 0x03,
657 msub_op = 0x04,
658 msubu_op = 0x05,
659 gs0x06_op = 0x06,
660 gsemul2_op = 0x07,
661 gsemul3_op = 0x08,
662 gsemul4_op = 0x09,
663 gsemul5_op = 0x0a,
664 gsemul6_op = 0x0b,
665 gsemul7_op = 0x0c,
666 gsemul8_op = 0x0d,
667 gsemul9_op = 0x0e,
668 gsemul10_op = 0x0f,
669 gsmult_op = 0x10,
670 gsdmult_op = 0x11,
671 gsmultu_op = 0x12,
672 gsdmultu_op = 0x13,
673 gsdiv_op = 0x14,
674 gsddiv_op = 0x15,
675 gsdivu_op = 0x16,
676 gsddivu_op = 0x17,
677 gsmod_op = 0x1c,
678 gsdmod_op = 0x1d,
679 gsmodu_op = 0x1e,
680 gsdmodu_op = 0x1f,
681 clz_op = 0x20,
682 clo_op = 0x21,
683 xctx_op = 0x22, //ctz, cto, dctz, dcto, gsX
684 gsrxr_x_op = 0x23, //gsX
685 dclz_op = 0x24,
686 dclo_op = 0x25,
687 gsle_op = 0x26,
688 gsgt_op = 0x27,
689 gs86j_op = 0x28,
690 gsloop_op = 0x29,
691 gsaj_op = 0x2a,
692 gsldpc_op = 0x2b,
693 gs86set_op = 0x30,
694 gstm_op = 0x31,
695 gscvt_ld_op = 0x32,
696 gscvt_ud_op = 0x33,
697 gseflag_op = 0x34,
698 gscam_op = 0x35,
699 gstop_op = 0x36,
700 gssettag_op = 0x37,
701 gssdbbp_op = 0x38
702 };
704 static const char* special2_name[];
706 // special3 family, the opcode is in low 6 bits.
707 enum special3_ops {
708 ext_op = 0x00,
709 dextm_op = 0x01,
710 dextu_op = 0x02,
711 dext_op = 0x03,
712 ins_op = 0x04,
713 dinsm_op = 0x05,
714 dinsu_op = 0x06,
715 dins_op = 0x07,
716 lxx_op = 0x0a, //lwx, lhx, lbux, ldx
717 insv_op = 0x0c,
718 dinsv_op = 0x0d,
719 ar1_op = 0x10, //MIPS DSP
720 cmp1_op = 0x11, //MIPS DSP
721 re1_op = 0x12, //MIPS DSP, re1_ops
722 sh1_op = 0x13, //MIPS DSP
723 ar2_op = 0x14, //MIPS DSP
724 cmp2_op = 0x15, //MIPS DSP
725 re2_op = 0x16, //MIPS DSP, re2_ops
726 sh2_op = 0x17, //MIPS DSP
727 ar3_op = 0x18, //MIPS DSP
728 bshfl_op = 0x20 //seb, seh
729 };
731 // re1_ops
732 enum re1_ops {
733 absq_s_qb_op = 0x01,
734 repl_qb_op = 0x02,
735 replv_qb_op = 0x03,
736 absq_s_ph_op = 0x09,
737 repl_ph_op = 0x0a,
738 replv_ph_op = 0x0b,
739 absq_s_w_op = 0x11,
740 bitrev_op = 0x1b
741 };
743 // re2_ops
744 enum re2_ops {
745 repl_ob_op = 0x02,
746 replv_ob_op = 0x03,
747 absq_s_qh_op = 0x09,
748 repl_qh_op = 0x0a,
749 replv_qh_op = 0x0b,
750 absq_s_pw_op = 0x11,
751 repl_pw_op = 0x12,
752 replv_pw_op = 0x13,
753 };
755 static const char* special3_name[];
757 // lwc2/gs_lwc2 family, the opcode is in low 6 bits.
758 enum gs_lwc2_ops {
759 gslble_op = 0x10,
760 gslbgt_op = 0x11,
761 gslhle_op = 0x12,
762 gslhgt_op = 0x13,
763 gslwle_op = 0x14,
764 gslwgt_op = 0x15,
765 gsldle_op = 0x16,
766 gsldgt_op = 0x17,
767 gslwlec1_op = 0x1c,
768 gslwgtc1_op = 0x1d,
769 gsldlec1_op = 0x1e,
770 gsldgtc1_op = 0x1f,
771 gslq_op = 0x20
772 };
774 static const char* gs_lwc2_name[];
776 // ldc2/gs_ldc2 family, the opcode is in low 3 bits.
777 enum gs_ldc2_ops {
778 gslbx_op = 0x0,
779 gslhx_op = 0x1,
780 gslwx_op = 0x2,
781 gsldx_op = 0x3,
782 gslwxc1_op = 0x6,
783 gsldxc1_op = 0x7
784 };
786 static const char* gs_ldc2_name[];
788 // swc2/gs_swc2 family, the opcode is in low 6 bits.
789 enum gs_swc2_ops {
790 gssble_op = 0x10,
791 gssbgt_op = 0x11,
792 gsshle_op = 0x12,
793 gsshgt_op = 0x13,
794 gsswle_op = 0x14,
795 gsswgt_op = 0x15,
796 gssdle_op = 0x16,
797 gssdgt_op = 0x17,
798 gsswlec1_op = 0x1c,
799 gsswgtc1_op = 0x1d,
800 gssdlec1_op = 0x1e,
801 gssdgtc1_op = 0x1f,
802 gssq_op = 0x20
803 };
805 static const char* gs_swc2_name[];
807 // sdc2/gs_sdc2 family, the opcode is in low 3 bits.
808 enum gs_sdc2_ops {
809 gssbx_op = 0x0,
810 gsshx_op = 0x1,
811 gsswx_op = 0x2,
812 gssdx_op = 0x3,
813 gsswxc1_op = 0x6,
814 gssdxc1_op = 0x7
815 };
817 static const char* gs_sdc2_name[];
819 /* 2013.10.16 Jin: merge from OpenJDK 8 */
820 enum WhichOperand {
821 // input to locate_operand, and format code for relocations
822 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
823 disp32_operand = 1, // embedded 32-bit displacement or address
824 call32_operand = 2, // embedded 32-bit self-relative displacement
825 #ifndef _LP64
826 _WhichOperand_limit = 3
827 #else
828 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
829 _WhichOperand_limit = 4
830 #endif
831 };
833 static int opcode(int insn) { return (insn>>26)&0x3f; }
834 static int rs(int insn) { return (insn>>21)&0x1f; }
835 static int rt(int insn) { return (insn>>16)&0x1f; }
836 static int rd(int insn) { return (insn>>11)&0x1f; }
837 static int sa(int insn) { return (insn>>6)&0x1f; }
838 static int special(int insn) { return insn&0x3f; }
839 static int imm_off(int insn) { return (short)low16(insn); }
841 static int low (int x, int l) { return bitfield(x, 0, l); }
842 static int low16(int x) { return low(x, 16); }
843 static int low26(int x) { return low(x, 26); }
845 protected:
846 //help methods for instruction ejection
848 // I-Type (Immediate)
849 // 31 26 25 21 20 16 15 0
850 //| opcode | rs | rt | immediat |
851 //| | | | |
852 // 6 5 5 16
853 static int insn_ORRI(int op, int rs, int rt, int imm) { return (op<<26) | (rs<<21) | (rt<<16) | low16(imm); }
855 // R-Type (Register)
856 // 31 26 25 21 20 16 15 11 10 6 5 0
857 //| special | rs | rt | rd | 0 | opcode |
858 //| 0 0 0 0 0 0 | | | | 0 0 0 0 0 | |
859 // 6 5 5 5 5 6
860 static int insn_RRRO(int rs, int rt, int rd, int op) { return (rs<<21) | (rt<<16) | (rd<<11) | op; }
861 static int insn_RRSO(int rt, int rd, int sa, int op) { return (rt<<16) | (rd<<11) | (sa<<6) | op; }
862 static int insn_RRCO(int rs, int rt, int code, int op) { return (rs<<21) | (rt<<16) | (code<<6) | op; }
864 static int insn_COP0(int op, int rt, int rd) { return (cop0_op<<26) | (op<<21) | (rt<<16) | (rd<<11); }
865 static int insn_COP1(int op, int rt, int fs) { return (cop1_op<<26) | (op<<21) | (rt<<16) | (fs<<11); }
867 static int insn_F3RO(int fmt, int ft, int fs, int fd, int func) {
868 return (cop1_op<<26) | (fmt<<21) | (ft<<16) | (fs<<11) | (fd<<6) | func;
869 }
870 static int insn_F3ROX(int fmt, int ft, int fs, int fd, int func) {
871 return (cop1x_op<<26) | (fmt<<21) | (ft<<16) | (fs<<11) | (fd<<6) | func;
872 }
875 //static int low (int x, int l) { return bitfield(x, 0, l); }
876 //static int low16(int x) { return low(x, 16); }
877 //static int low26(int x) { return low(x, 26); }
879 static int high (int x, int l) { return bitfield(x, 32-l, l); }
880 static int high16(int x) { return high(x, 16); }
881 static int high6 (int x) { return high(x, 6); }
883 //get the offset field of jump/branch instruction
884 int offset(address entry) {
885 assert(is_simm16((entry - pc() - 4) / 4), "change this code");
886 if (!is_simm16((entry - pc() - 4) / 4)) {
887 tty->print_cr("!!! is_simm16: %x", (entry - pc() - 4) / 4);
888 }
889 return (entry - pc() - 4) / 4;
890 }
893 public:
894 using AbstractAssembler::offset;
896 //sign expand with the sign bit is h
897 static int expand(int x, int h) { return -(x & (1<<h)) | x; }
899 // If x is a mask, return the number of one-bit in x.
900 // else return -1.
901 static int is_int_mask(int x);
903 // If x is a mask, return the number of one-bit in x.
904 // else return -1.
905 static int is_jlong_mask(jlong x);
907 // MIPS lui/addiu is both sign extended, so if you wan't to use off32/imm32, you have to use the follow three
908 static int split_low(int x) {
909 return (x & 0xffff);
910 }
912 static int split_high(int x) {
913 return ( (x >> 16) + ((x & 0x8000) != 0) ) & 0xffff;
914 }
916 static int merge(int low, int high) {
917 return expand(low, 15) + (high<<16);
918 }
920 #ifdef _LP64
921 static intptr_t merge(intptr_t x0, intptr_t x16, intptr_t x32, intptr_t x48) {
922 return (x48 << 48) | (x32 << 32) | (x16 << 16) | x0;
923 }
924 #endif
926 // modified by spark 2005/08/18
927 static bool is_simm (int x, int nbits) { return -( 1 << nbits-1 ) <= x && x < ( 1 << nbits-1 ); }
928 static bool is_simm16(int x) { return is_simm(x, 16); }
930 static bool fit_in_jal(address target, address pc) {
931 #ifdef _LP64
932 int dst = ((intptr_t)target - (((intptr_t)pc + 4) & 0xfffffffff0000000))>>2;
933 #else
934 int dst = ((intptr_t)target - (((intptr_t)pc + 4) & 0xf0000000))>>2;
935 #endif
936 if ((dst >= 0) && (dst < (1<<26))) return true;
937 else return false;
938 }
940 bool fit_int_branch(address entry) {
941 return is_simm16(offset(entry));
942 }
944 protected:
945 #ifdef ASSERT
946 #define CHECK_DELAY
947 #endif
948 #ifdef CHECK_DELAY
949 enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
950 #endif
952 public:
953 void assert_not_delayed() {
954 #ifdef CHECK_DELAY
955 assert_not_delayed("next instruction should not be a delay slot");
956 #endif
957 }
959 void assert_not_delayed(const char* msg) {
960 #ifdef CHECK_DELAY
961 //guarantee( delay_state == no_delay, msg );
962 //aoqi_test
963 if(delay_state != no_delay){
964 tty->print_cr("%s:%d, pc: %lx", __func__, __LINE__, pc());
965 }
966 assert(delay_state == no_delay, msg);
967 #endif
968 }
970 protected:
971 // Delay slot helpers
972 // cti is called when emitting control-transfer instruction,
973 // BEFORE doing the emitting.
974 // Only effective when assertion-checking is enabled.
976 // called when emitting cti with a delay slot, AFTER emitting
977 void has_delay_slot() {
978 #ifdef CHECK_DELAY
979 assert_not_delayed("just checking");
980 delay_state = at_delay_slot;
981 #endif
982 }
984 public:
985 Assembler* delayed() {
986 #ifdef CHECK_DELAY
987 guarantee( delay_state == at_delay_slot, "delayed instructition is not in delay slot");
988 delay_state = filling_delay_slot;
989 #endif
990 return this;
991 }
993 void flush() {
994 #ifdef CHECK_DELAY
995 guarantee( delay_state == no_delay, "ending code with a delay slot");
996 #endif
997 AbstractAssembler::flush();
998 }
1000 inline void emit_long(int); // shadows AbstractAssembler::emit_long
1001 inline void emit_data(int x) { emit_long(x); }
1002 inline void emit_data(int, RelocationHolder const&);
1003 inline void emit_data(int, relocInfo::relocType rtype);
1004 inline void check_delay();
1007 // Generic instructions
1008 // Does 32bit or 64bit as needed for the platform. In some sense these
1009 // belong in macro assembler but there is no need for both varieties to exist
1011 #ifndef _LP64
1012 void add(Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), add_op)); }
1013 void addi(Register rt, Register rs, int imm) { emit_long(insn_ORRI(addi_op, (int)rs->encoding(), (int)rt->encoding(), imm)); }
1014 void addiu(Register rt, Register rs, int imm) { emit_long(insn_ORRI(addiu_op, (int)rs->encoding(), (int)rt->encoding(), imm)); }
1015 void addu(Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), addu_op)); }
1016 #else
1017 void add(Register rd, Register rs, Register rt) { dadd (rd, rs, rt); }
1018 void add32(Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), add_op)); }
1019 void addu32(Register rd, Register rs, Register rt){ emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), addu_op)); }
1020 void addiu32(Register rt, Register rs, int imm) { emit_long(insn_ORRI(addiu_op, (int)rs->encoding(), (int)rt->encoding(), imm)); }
1021 void addi(Register rt, Register rs, int imm) { daddi (rt, rs, imm);}
1022 void addiu(Register rt, Register rs, int imm) { daddiu (rt, rs, imm);}
1023 void addu(Register rd, Register rs, Register rt) { daddu (rd, rs, rt); }
1024 #endif
1026 void andr(Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), and_op)); }
1027 void andi(Register rt, Register rs, int imm) { emit_long(insn_ORRI(andi_op, (int)rs->encoding(), (int)rt->encoding(), imm)); }
1029 void beq (Register rs, Register rt, int off) { emit_long(insn_ORRI(beq_op, (int)rs->encoding(), (int)rt->encoding(), off)); has_delay_slot(); }
1030 void beql (Register rs, Register rt, int off) { emit_long(insn_ORRI(beql_op, (int)rs->encoding(), (int)rt->encoding(), off)); has_delay_slot(); }
1031 void bgez (Register rs, int off) { emit_long(insn_ORRI(regimm_op, (int)rs->encoding(), bgez_op, off)); has_delay_slot(); }
1032 void bgezal (Register rs, int off) { emit_long(insn_ORRI(regimm_op, (int)rs->encoding(), bgezal_op, off)); has_delay_slot(); }
1033 void bgezall(Register rs, int off) { emit_long(insn_ORRI(regimm_op, (int)rs->encoding(), bgezall_op, off)); has_delay_slot(); }
1034 void bgezl (Register rs, int off) { emit_long(insn_ORRI(regimm_op, (int)rs->encoding(), bgezl_op, off)); has_delay_slot(); }
1035 void bgtz (Register rs, int off) { emit_long(insn_ORRI(bgtz_op, (int)rs->encoding(), 0, off)); has_delay_slot(); }
1036 void bgtzl (Register rs, int off) { emit_long(insn_ORRI(bgtzl_op, (int)rs->encoding(), 0, off)); has_delay_slot(); }
1037 void blez (Register rs, int off) { emit_long(insn_ORRI(blez_op, (int)rs->encoding(), 0, off)); has_delay_slot(); }
1038 void blezl (Register rs, int off) { emit_long(insn_ORRI(blezl_op, (int)rs->encoding(), 0, off)); has_delay_slot(); }
1039 void bltz (Register rs, int off) { emit_long(insn_ORRI(regimm_op, (int)rs->encoding(), bltz_op, off)); has_delay_slot(); }
1040 void bltzal (Register rs, int off) { emit_long(insn_ORRI(regimm_op, (int)rs->encoding(), bltzal_op, off)); has_delay_slot(); }
1041 void bltzall(Register rs, int off) { emit_long(insn_ORRI(regimm_op, (int)rs->encoding(), bltzall_op, off)); has_delay_slot(); }
1042 void bltzl (Register rs, int off) { emit_long(insn_ORRI(regimm_op, (int)rs->encoding(), bltzl_op, off)); has_delay_slot(); }
1043 void bne (Register rs, Register rt, int off) { emit_long(insn_ORRI(bne_op, (int)rs->encoding(), (int)rt->encoding(), off)); has_delay_slot(); }
1044 void bnel (Register rs, Register rt, int off) { emit_long(insn_ORRI(bnel_op, (int)rs->encoding(), (int)rt->encoding(), off)); has_delay_slot(); }
1045 void brk (int code) { emit_long(break_op | (code<<16)); }
1047 void beq (Register rs, Register rt, address entry) { beq(rs, rt, offset(entry)); }
1048 void beql (Register rs, Register rt, address entry) { beql(rs, rt, offset(entry));}
1049 void bgez (Register rs, address entry) { bgez (rs, offset(entry)); }
1050 void bgezal (Register rs, address entry) { bgezal (rs, offset(entry)); }
1051 void bgezall(Register rs, address entry) { bgezall(rs, offset(entry)); }
1052 void bgezl (Register rs, address entry) { bgezl (rs, offset(entry)); }
1053 void bgtz (Register rs, address entry) { bgtz (rs, offset(entry)); }
1054 void bgtzl (Register rs, address entry) { bgtzl (rs, offset(entry)); }
1055 void blez (Register rs, address entry) { blez (rs, offset(entry)); }
1056 void blezl (Register rs, address entry) { blezl (rs, offset(entry)); }
1057 void bltz (Register rs, address entry) { bltz (rs, offset(entry)); }
1058 void bltzal (Register rs, address entry) { bltzal (rs, offset(entry)); }
1059 void bltzall(Register rs, address entry) { bltzall(rs, offset(entry)); }
1060 void bltzl (Register rs, address entry) { bltzl (rs, offset(entry)); }
1061 void bne (Register rs, Register rt, address entry) { bne(rs, rt, offset(entry)); }
1062 void bnel (Register rs, Register rt, address entry) { bnel(rs, rt, offset(entry)); }
1064 void beq (Register rs, Register rt, Label& L) { beq(rs, rt, target(L)); }
1065 void beql (Register rs, Register rt, Label& L) { beql(rs, rt, target(L)); }
1066 void bgez (Register rs, Label& L){ bgez (rs, target(L)); }
1067 void bgezal (Register rs, Label& L){ bgezal (rs, target(L)); }
1068 void bgezall(Register rs, Label& L){ bgezall(rs, target(L)); }
1069 void bgezl (Register rs, Label& L){ bgezl (rs, target(L)); }
1070 void bgtz (Register rs, Label& L){ bgtz (rs, target(L)); }
1071 void bgtzl (Register rs, Label& L){ bgtzl (rs, target(L)); }
1072 void blez (Register rs, Label& L){ blez (rs, target(L)); }
1073 void blezl (Register rs, Label& L){ blezl (rs, target(L)); }
1074 void bltz (Register rs, Label& L){ bltz (rs, target(L)); }
1075 void bltzal (Register rs, Label& L){ bltzal (rs, target(L)); }
1076 void bltzall(Register rs, Label& L){ bltzall(rs, target(L)); }
1077 void bltzl (Register rs, Label& L){ bltzl (rs, target(L)); }
1078 void bne (Register rs, Register rt, Label& L){ bne(rs, rt, target(L)); }
1079 void bnel (Register rs, Register rt, Label& L){ bnel(rs, rt, target(L)); }
1081 void dadd (Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), dadd_op)); }
1082 void daddi (Register rt, Register rs, int imm) { emit_long(insn_ORRI(daddi_op, (int)rs->encoding(), (int)rt->encoding(), imm)); }
1083 void daddiu(Register rt, Register rs, int imm) { emit_long(insn_ORRI(daddiu_op, (int)rs->encoding(), (int)rt->encoding(), imm)); }
1084 void daddu (Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), daddu_op)); }
1085 void ddiv (Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, ddiv_op)); }
1086 void ddivu (Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, ddivu_op)); }
1088 void movz (Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), movz_op)); }
1089 void movn (Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), movn_op)); }
1091 void movt (Register rd, Register rs) { emit_long(((int)rs->encoding() << 21) | (1 << 16) | ((int)rd->encoding() << 11) | movci_op); }
1092 void movf (Register rd, Register rs) { emit_long(((int)rs->encoding() << 21) | ((int)rd->encoding() << 11) | movci_op); }
1094 enum bshfl_ops {
1095 seb_op = 0x10,
1096 seh_op = 0x18
1097 };
1098 void seb (Register rd, Register rt) { emit_long((special3_op << 26) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (seb_op << 6) | bshfl_op); }
1099 void seh (Register rd, Register rt) { emit_long((special3_op << 26) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (seh_op << 6) | bshfl_op); }
1101 void ext (Register rt, Register rs, int pos, int size) {
1102 guarantee((0 <= pos) && (pos < 32), "pos must be in [0, 32)");
1103 guarantee((0 < size) && (size <= 32), "size must be in (0, 32]");
1104 guarantee((0 < pos + size) && (pos + size <= 32), "pos + size must be in (0, 32]");
1106 int lsb = pos;
1107 int msbd = size - 1;
1109 emit_long((special3_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | (msbd << 11) | (lsb << 6) | ext_op);
1110 }
1112 void dext (Register rt, Register rs, int pos, int size) {
1113 guarantee((0 <= pos) && (pos < 32), "pos must be in [0, 32)");
1114 guarantee((0 < size) && (size <= 32), "size must be in (0, 32]");
1115 guarantee((0 < pos + size) && (pos + size <= 63), "pos + size must be in (0, 63]");
1117 int lsb = pos;
1118 int msbd = size - 1;
1120 emit_long((special3_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | (msbd << 11) | (lsb << 6) | dext_op);
1121 }
1123 void rotr (Register rd, Register rt, int sa) {
1124 emit_long((special_op << 26) | (1 << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (low(sa, 5) << 6) | srl_op);
1125 }
1127 void drotr (Register rd, Register rt, int sa) {
1128 emit_long((special_op << 26) | (1 << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (low(sa, 5) << 6) | dsrl_op);
1129 }
1131 void drotr32 (Register rd, Register rt, int sa) {
1132 emit_long((special_op << 26) | (1 << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (low(sa, 5) << 6) | dsrl32_op);
1133 }
1135 void rotrv (Register rd, Register rt, Register rs) {
1136 emit_long((special_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (1 << 6) | srlv_op);
1137 }
1139 void drotrv (Register rd, Register rt, Register rs) {
1140 emit_long((special_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | (1 << 6) | dsrlv_op);
1141 }
1143 // Do mult and div need both 32-bit and 64-bit version? FIXME aoqi
1144 //#ifndef _LP64
1145 #if 1
1146 void div (Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, div_op)); }
1147 void divu (Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, divu_op)); }
1148 #else
1149 void div (Register rs, Register rt) { ddiv (rs, rt);}
1150 void divu (Register rs, Register rt) { ddivu(rs, rt);}
1151 #endif
1152 void dmult (Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, dmult_op)); }
1153 void dmultu(Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, dmultu_op)); }
1154 void dsll (Register rd, Register rt , int sa) { emit_long(insn_RRSO((int)rt->encoding(), (int)rd->encoding(), sa, dsll_op)); }
1155 void dsllv (Register rd, Register rt, Register rs) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), dsllv_op)); }
1156 void dsll32(Register rd, Register rt , int sa) { emit_long(insn_RRSO((int)rt->encoding(), (int)rd->encoding(), sa, dsll32_op)); }
1157 void dsra (Register rd, Register rt , int sa) { emit_long(insn_RRSO((int)rt->encoding(), (int)rd->encoding(), sa, dsra_op)); }
1158 void dsrav (Register rd, Register rt, Register rs) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), dsrav_op)); }
1159 void dsra32(Register rd, Register rt , int sa) { emit_long(insn_RRSO((int)rt->encoding(), (int)rd->encoding(), sa, dsra32_op)); }
1160 void dsrl (Register rd, Register rt , int sa) { emit_long(insn_RRSO((int)rt->encoding(), (int)rd->encoding(), sa, dsrl_op)); }
1161 void dsrlv (Register rd, Register rt, Register rs) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), dsrlv_op)); }
1162 void dsrl32(Register rd, Register rt , int sa) { emit_long(insn_RRSO((int)rt->encoding(), (int)rd->encoding(), sa, dsrl32_op)); }
1163 void dsub (Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), dsub_op)); }
1164 void dsubu (Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), dsubu_op)); }
1166 void b(int off) { beq(R0, R0, off); }
1167 void b(address entry) { b(offset(entry)); }
1168 void b(Label& L) { b(target(L)); }
1170 void j(address entry);
1171 void jal(address entry);
1173 void jalr(Register rd, Register rs) { emit_long( ((int)rs->encoding()<<21) | ((int)rd->encoding()<<11) | jalr_op); has_delay_slot(); }
1174 void jalr(Register rs) { jalr(RA, rs); }
1175 void jalr() { jalr(T9); }
1177 void jr(Register rs) { emit_long(((int)rs->encoding()<<21) | jr_op); has_delay_slot(); }
1179 void lb (Register rt, Register base, int off) { emit_long(insn_ORRI(lb_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1180 void lbu(Register rt, Register base, int off) { emit_long(insn_ORRI(lbu_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1181 void ld (Register rt, Register base, int off) { emit_long(insn_ORRI(ld_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1182 void ldl(Register rt, Register base, int off) { emit_long(insn_ORRI(ldl_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1183 void ldr(Register rt, Register base, int off) { emit_long(insn_ORRI(ldr_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1184 void lh (Register rt, Register base, int off) { emit_long(insn_ORRI(lh_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1185 void lhu(Register rt, Register base, int off) { emit_long(insn_ORRI(lhu_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1186 void ll (Register rt, Register base, int off) { emit_long(insn_ORRI(ll_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1187 void lld(Register rt, Register base, int off) { emit_long(insn_ORRI(lld_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1188 void lui(Register rt, int imm) { emit_long(insn_ORRI(lui_op, 0, (int)rt->encoding(), imm)); }
1189 void lw (Register rt, Register base, int off) { emit_long(insn_ORRI(lw_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1190 void lwl(Register rt, Register base, int off) { emit_long(insn_ORRI(lwl_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1191 void lwr(Register rt, Register base, int off) { emit_long(insn_ORRI(lwr_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1192 void lwu(Register rt, Register base, int off) { emit_long(insn_ORRI(lwu_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1194 void lb (Register rt, Address src);
1195 void lbu(Register rt, Address src);
1196 void ld (Register rt, Address src);
1197 void ldl(Register rt, Address src);
1198 void ldr(Register rt, Address src);
1199 void lh (Register rt, Address src);
1200 void lhu(Register rt, Address src);
1201 void ll (Register rt, Address src);
1202 void lld(Register rt, Address src);
1203 void lw (Register rt, Address src);
1204 void lwl(Register rt, Address src);
1205 void lwr(Register rt, Address src);
1206 void lwu(Register rt, Address src);
1207 void lea(Register rt, Address src);
1208 void pref(int hint, Register base, int off) { emit_long(insn_ORRI(pref_op, (int)base->encoding(), low(hint, 5), low(off, 16))); }
1210 void mfhi (Register rd) { emit_long( ((int)rd->encoding()<<11) | mfhi_op ); }
1211 void mflo (Register rd) { emit_long( ((int)rd->encoding()<<11) | mflo_op ); }
1212 void mthi (Register rs) { emit_long( ((int)rs->encoding()<<21) | mthi_op ); }
1213 void mtlo (Register rs) { emit_long( ((int)rs->encoding()<<21) | mtlo_op ); }
1215 void mult (Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, mult_op)); }
1216 void multu(Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), 0, multu_op)); }
1218 void nor(Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), nor_op)); }
1220 void orr(Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), or_op)); }
1221 void ori(Register rt, Register rs, int imm) { emit_long(insn_ORRI(ori_op, (int)rs->encoding(), (int)rt->encoding(), imm)); }
1223 void sb (Register rt, Register base, int off) { emit_long(insn_ORRI(sb_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1224 void sc (Register rt, Register base, int off) { emit_long(insn_ORRI(sc_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1225 void scd (Register rt, Register base, int off) { emit_long(insn_ORRI(scd_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1226 void sd (Register rt, Register base, int off) { emit_long(insn_ORRI(sd_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1227 void sdl (Register rt, Register base, int off) { emit_long(insn_ORRI(sdl_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1228 void sdr (Register rt, Register base, int off) { emit_long(insn_ORRI(sdr_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1229 void sh (Register rt, Register base, int off) { emit_long(insn_ORRI(sh_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1230 void sll (Register rd, Register rt , int sa) { emit_long(insn_RRSO((int)rt->encoding(), (int)rd->encoding(), low(sa, 5), sll_op)); }
1231 void sllv (Register rd, Register rt, Register rs) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), sllv_op)); }
1232 void slt (Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), slt_op)); }
1233 void slti (Register rt, Register rs, int imm) { emit_long(insn_ORRI(slti_op, (int)rs->encoding(), (int)rt->encoding(), imm)); }
1234 void sltiu(Register rt, Register rs, int imm) { emit_long(insn_ORRI(sltiu_op, (int)rs->encoding(), (int)rt->encoding(), imm)); }
1235 void sltu (Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), sltu_op)); }
1236 void sra (Register rd, Register rt , int sa) { emit_long(insn_RRSO((int)rt->encoding(), (int)rd->encoding(), sa, sra_op)); }
1237 void srav (Register rd, Register rt, Register rs) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), srav_op)); }
1238 void srl (Register rd, Register rt , int sa) { emit_long(insn_RRSO((int)rt->encoding(), (int)rd->encoding(), low(sa, 5), srl_op)); }
1239 void srlv (Register rd, Register rt, Register rs) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), srlv_op)); }
1241 #ifndef _LP64
1242 void sub (Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), sub_op)); }
1243 void subu (Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), subu_op)); }
1244 #else
1245 void sub (Register rd, Register rs, Register rt) { dsub (rd, rs, rt); }
1246 void subu (Register rd, Register rs, Register rt) { dsubu (rd, rs, rt); }
1247 void subu32 (Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), subu_op)); }
1248 #endif
1249 void sw (Register rt, Register base, int off) { emit_long(insn_ORRI(sw_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1250 void swl (Register rt, Register base, int off) { emit_long(insn_ORRI(swl_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1251 void swr (Register rt, Register base, int off) { emit_long(insn_ORRI(swr_op, (int)base->encoding(), (int)rt->encoding(), off)); }
1252 void sync () { emit_long(sync_op); }
1253 void syscall(int code) { emit_long( (code<<6) | syscall_op ); }
1255 void sb(Register rt, Address dst);
1256 void sc(Register rt, Address dst);
1257 void scd(Register rt, Address dst);
1258 void sd(Register rt, Address dst);
1259 void sdl(Register rt, Address dst);
1260 void sdr(Register rt, Address dst);
1261 void sh(Register rt, Address dst);
1262 void sw(Register rt, Address dst);
1263 void swl(Register rt, Address dst);
1264 void swr(Register rt, Address dst);
1266 void teq (Register rs, Register rt, int code) { emit_long(insn_RRCO((int)rs->encoding(), (int)rt->encoding(), code, teq_op)); }
1267 void teqi (Register rs, int imm) { emit_long(insn_ORRI(regimm_op, (int)rs->encoding(), teqi_op, imm)); }
1268 void tge (Register rs, Register rt, int code) { emit_long(insn_RRCO((int)rs->encoding(), (int)rt->encoding(), code, tge_op)); }
1269 void tgei (Register rs, int imm) { emit_long(insn_ORRI(regimm_op, (int)rs->encoding(), tgei_op, imm)); }
1270 void tgeiu(Register rs, int imm) { emit_long(insn_ORRI(regimm_op, (int)rs->encoding(), tgeiu_op, imm)); }
1271 void tgeu (Register rs, Register rt, int code) { emit_long(insn_RRCO((int)rs->encoding(), (int)rt->encoding(), code, tgeu_op)); }
1272 void tlt (Register rs, Register rt, int code) { emit_long(insn_RRCO((int)rs->encoding(), (int)rt->encoding(), code, tlt_op)); }
1273 void tlti (Register rs, int imm) { emit_long(insn_ORRI(regimm_op, (int)rs->encoding(), tlti_op, imm)); }
1274 void tltiu(Register rs, int imm) { emit_long(insn_ORRI(regimm_op, (int)rs->encoding(), tltiu_op, imm)); }
1275 void tltu (Register rs, Register rt, int code) { emit_long(insn_RRCO((int)rs->encoding(), (int)rt->encoding(), code, tltu_op)); }
1276 void tne (Register rs, Register rt, int code) { emit_long(insn_RRCO((int)rs->encoding(), (int)rt->encoding(), code, tne_op)); }
1277 void tnei (Register rs, int imm) { emit_long(insn_ORRI(regimm_op, (int)rs->encoding(), tnei_op, imm)); }
1279 void xorr(Register rd, Register rs, Register rt) { emit_long(insn_RRRO((int)rs->encoding(), (int)rt->encoding(), (int)rd->encoding(), xor_op)); }
1280 void xori(Register rt, Register rs, int imm) { emit_long(insn_ORRI(xori_op, (int)rs->encoding(), (int)rt->encoding(), imm)); }
1282 void nop() { emit_long(0); }
1286 void ldc1(FloatRegister ft, Register base, int off) { emit_long(insn_ORRI(ldc1_op, (int)base->encoding(), (int)ft->encoding(), off)); }
1287 void lwc1(FloatRegister ft, Register base, int off) { emit_long(insn_ORRI(lwc1_op, (int)base->encoding(), (int)ft->encoding(), off)); }
1288 void ldc1(FloatRegister ft, Address src);
1289 void lwc1(FloatRegister ft, Address src);
1291 //COP0
1292 void mfc0 (Register rt, Register rd) { emit_long(insn_COP0( mfc0_op, (int)rt->encoding(), (int)rd->encoding())); }
1293 void dmfc0 (Register rt, FloatRegister rd) { emit_long(insn_COP0(dmfc0_op, (int)rt->encoding(), (int)rd->encoding())); }
1294 // MFGC0, DMFGC0, MTGC0, DMTGC0 not implemented yet
1295 void mtc0 (Register rt, Register rd) { emit_long(insn_COP0( mtc0_op, (int)rt->encoding(), (int)rd->encoding())); }
1296 void dmtc0 (Register rt, FloatRegister rd) { emit_long(insn_COP0(dmtc0_op, (int)rt->encoding(), (int)rd->encoding())); }
1297 //COP0 end
1300 //COP1
1301 void mfc1 (Register rt, FloatRegister fs) { emit_long(insn_COP1 (mfc1_op, (int)rt->encoding(), (int)fs->encoding())); }
1302 void dmfc1(Register rt, FloatRegister fs) { emit_long(insn_COP1(dmfc1_op, (int)rt->encoding(), (int)fs->encoding())); }
1303 void cfc1 (Register rt, int fs) { emit_long(insn_COP1( cfc1_op, (int)rt->encoding(), fs)); }
1304 void mfhc1(Register rt, int fs) { emit_long(insn_COP1(mfhc1_op, (int)rt->encoding(), fs)); }
1305 void mtc1 (Register rt, FloatRegister fs) { emit_long(insn_COP1( mtc1_op, (int)rt->encoding(), (int)fs->encoding())); }
1306 void dmtc1(Register rt, FloatRegister fs) { emit_long(insn_COP1(dmtc1_op, (int)rt->encoding(), (int)fs->encoding())); }
1307 void ctc1 (Register rt, FloatRegister fs) { emit_long(insn_COP1( ctc1_op, (int)rt->encoding(), (int)fs->encoding())); }
1308 void ctc1 (Register rt, int fs) { emit_long(insn_COP1(ctc1_op, (int)rt->encoding(), fs)); }
1309 void mthc1(Register rt, int fs) { emit_long(insn_COP1(mthc1_op, (int)rt->encoding(), fs)); }
1311 void bc1f (int off) { emit_long(insn_ORRI(cop1_op, bc1f_op, bcf_op, off)); has_delay_slot(); }
1312 void bc1fl(int off) { emit_long(insn_ORRI(cop1_op, bc1f_op, bcfl_op, off)); has_delay_slot(); }
1313 void bc1t (int off) { emit_long(insn_ORRI(cop1_op, bc1f_op, bct_op, off)); has_delay_slot(); }
1314 void bc1tl(int off) { emit_long(insn_ORRI(cop1_op, bc1f_op, bctl_op, off)); has_delay_slot(); }
1316 void bc1f (address entry) { bc1f(offset(entry)); }
1317 void bc1fl(address entry) { bc1fl(offset(entry)); }
1318 void bc1t (address entry) { bc1t(offset(entry)); }
1319 void bc1tl(address entry) { bc1tl(offset(entry)); }
1321 void bc1f (Label& L) { bc1f(target(L)); }
1322 void bc1fl(Label& L) { bc1fl(target(L)); }
1323 void bc1t (Label& L) { bc1t(target(L)); }
1324 void bc1tl(Label& L) { bc1tl(target(L)); }
1326 //R0->encoding() is 0; INSN_SINGLE is enclosed by {} for ctags.
1327 #define INSN_SINGLE(r1, r2, r3, op) \
1328 { emit_long(insn_F3RO(single_fmt, (int)r1->encoding(), (int)r2->encoding(), (int)r3->encoding(), op));}
1329 void add_s (FloatRegister fd, FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, fd, fadd_op)}
1330 void sub_s (FloatRegister fd, FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, fd, fsub_op)}
1331 void mul_s (FloatRegister fd, FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, fd, fmul_op)}
1332 void div_s (FloatRegister fd, FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, fd, fdiv_op)}
1333 void sqrt_s (FloatRegister fd, FloatRegister fs) {INSN_SINGLE(R0, fs, fd, fsqrt_op)}
1334 void abs_s (FloatRegister fd, FloatRegister fs) {INSN_SINGLE(R0, fs, fd, fabs_op)}
1335 void mov_s (FloatRegister fd, FloatRegister fs) {INSN_SINGLE(R0, fs, fd, fmov_op)}
1336 void neg_s (FloatRegister fd, FloatRegister fs) {INSN_SINGLE(R0, fs, fd, fneg_op)}
1337 void round_l_s(FloatRegister fd, FloatRegister fs) {INSN_SINGLE(R0, fs, fd, froundl_op)}
1338 void trunc_l_s(FloatRegister fd, FloatRegister fs) {INSN_SINGLE(R0, fs, fd, ftruncl_op)}
1339 void ceil_l_s (FloatRegister fd, FloatRegister fs) {INSN_SINGLE(R0, fs, fd, fceill_op)}
1340 void floor_l_s(FloatRegister fd, FloatRegister fs) {INSN_SINGLE(R0, fs, fd, ffloorl_op)}
1341 void round_w_s(FloatRegister fd, FloatRegister fs) {INSN_SINGLE(R0, fs, fd, froundw_op)}
1342 void trunc_w_s(FloatRegister fd, FloatRegister fs) {INSN_SINGLE(R0, fs, fd, ftruncw_op)}
1343 void ceil_w_s (FloatRegister fd, FloatRegister fs) {INSN_SINGLE(R0, fs, fd, fceilw_op)}
1344 void floor_w_s(FloatRegister fd, FloatRegister fs) {INSN_SINGLE(R0, fs, fd, ffloorw_op)}
1345 //null
1346 //void movf_s(FloatRegister rd, FloatRegister rs, FPConditionCode cc) { unimplemented(" movf_s")}
1347 //void movt_s(FloatRegister rd, FloatRegister rs, FPConditionCode cc) { unimplemented(" movt_s") }
1348 void movz_s (FloatRegister fd, FloatRegister fs, Register rt) {INSN_SINGLE(rt, fs, fd, movz_f_op)}
1349 void movn_s (FloatRegister fd, FloatRegister fs, Register rt) {INSN_SINGLE(rt, fs, fd, movn_f_op)}
1350 //null
1351 void recip_s (FloatRegister fd, FloatRegister fs) {INSN_SINGLE(R0, fs, fd, frecip_op)}
1352 void rsqrt_s (FloatRegister fd, FloatRegister fs) {INSN_SINGLE(R0, fs, fd, frsqrt_op)}
1353 //null
1354 void cvt_d_s (FloatRegister fd, FloatRegister fs) {INSN_SINGLE(R0, fs, fd, fcvtd_op)}
1355 //null
1356 void cvt_w_s (FloatRegister fd, FloatRegister fs) {INSN_SINGLE(R0, fs, fd, fcvtw_op)}
1357 void cvt_l_s (FloatRegister fd, FloatRegister fs) {INSN_SINGLE(R0, fs, fd, fcvtl_op)}
1358 void cvt_ps_s(FloatRegister fd, FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, fd, fcvtps_op)}
1359 //null
1360 void c_f_s (FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, R0, f_cond)}
1361 void c_un_s (FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, R0, un_cond)}
1362 void c_eq_s (FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, R0, eq_cond)}
1363 void c_ueq_s (FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, R0, ueq_cond)}
1364 void c_olt_s (FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, R0, olt_cond)}
1365 void c_ult_s (FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, R0, ult_cond)}
1366 void c_ole_s (FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, R0, ole_cond)}
1367 void c_ule_s (FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, R0, ule_cond)}
1368 void c_sf_s (FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, R0, sf_cond)}
1369 void c_ngle_s(FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, R0, ngle_cond)}
1370 void c_seq_s (FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, R0, seq_cond)}
1371 void c_ngl_s (FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, R0, ngl_cond)}
1372 void c_lt_s (FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, R0, lt_cond)}
1373 void c_nge_s (FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, R0, nge_cond)}
1374 void c_le_s (FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, R0, le_cond)}
1375 void c_ngt_s (FloatRegister fs, FloatRegister ft) {INSN_SINGLE(ft, fs, R0, ngt_cond)}
1377 #undef INSN_SINGLE
1380 //R0->encoding() is 0; INSN_DOUBLE is enclosed by {} for ctags.
1381 #define INSN_DOUBLE(r1, r2, r3, op) \
1382 { emit_long(insn_F3RO(double_fmt, (int)r1->encoding(), (int)r2->encoding(), (int)r3->encoding(), op));}
1384 void add_d (FloatRegister fd, FloatRegister fs, FloatRegister ft) {INSN_DOUBLE(ft, fs, fd, fadd_op)}
1385 void sub_d (FloatRegister fd, FloatRegister fs, FloatRegister ft) {INSN_DOUBLE(ft, fs, fd, fsub_op)}
1386 void mul_d (FloatRegister fd, FloatRegister fs, FloatRegister ft) {INSN_DOUBLE(ft, fs, fd, fmul_op)}
1387 void div_d (FloatRegister fd, FloatRegister fs, FloatRegister ft) {INSN_DOUBLE(ft, fs, fd, fdiv_op)}
1388 void sqrt_d (FloatRegister fd, FloatRegister fs) {INSN_DOUBLE(R0, fs, fd, fsqrt_op)}
1389 void abs_d (FloatRegister fd, FloatRegister fs) {INSN_DOUBLE(R0, fs, fd, fabs_op)}
1390 void mov_d (FloatRegister fd, FloatRegister fs) {INSN_DOUBLE(R0, fs, fd, fmov_op)}
1391 void neg_d (FloatRegister fd, FloatRegister fs) {INSN_DOUBLE(R0, fs, fd, fneg_op)}
1392 void round_l_d(FloatRegister fd, FloatRegister fs) {INSN_DOUBLE(R0, fs, fd, froundl_op)}
1393 void trunc_l_d(FloatRegister fd, FloatRegister fs) {INSN_DOUBLE(R0, fs, fd, ftruncl_op)}
1394 void ceil_l_d (FloatRegister fd, FloatRegister fs) {INSN_DOUBLE(R0, fs, fd, fceill_op)}
1395 void floor_l_d(FloatRegister fd, FloatRegister fs) {INSN_DOUBLE(R0, fs, fd, ffloorl_op)}
1396 void round_w_d(FloatRegister fd, FloatRegister fs) {INSN_DOUBLE(R0, fs, fd, froundw_op)}
1397 void trunc_w_d(FloatRegister fd, FloatRegister fs) {INSN_DOUBLE(R0, fs, fd, ftruncw_op)}
1398 void ceil_w_d (FloatRegister fd, FloatRegister fs) {INSN_DOUBLE(R0, fs, fd, fceilw_op)}
1399 void floor_w_d(FloatRegister fd, FloatRegister fs) {INSN_DOUBLE(R0, fs, fd, ffloorw_op)}
1400 //null
1401 //void movf_d(Register rd, Register rs, FPConditionCode cc) { unimplemented(" movf_d")}
1402 //void movt_d(Register rd, Register rs, FPConditionCode cc) { unimplemented(" movt_d") }
1403 void movz_d (FloatRegister fd, FloatRegister fs, Register rt) {INSN_DOUBLE(rt, fs, fd, movz_f_op)}
1404 void movn_d (FloatRegister fd, FloatRegister fs, Register rt) {INSN_DOUBLE(rt, fs, fd, movn_f_op)}
1405 //null
1406 void recip_d (FloatRegister fd, FloatRegister fs) {INSN_DOUBLE(R0, fs, fd, frecip_op)}
1407 void rsqrt_d (FloatRegister fd, FloatRegister fs) {INSN_DOUBLE(R0, fs, fd, frsqrt_op)}
1408 //null
1409 void cvt_s_d (FloatRegister fd, FloatRegister fs) {INSN_DOUBLE(R0, fs, fd, fcvts_op)}
1410 void cvt_l_d (FloatRegister fd, FloatRegister fs) {INSN_DOUBLE(R0, fs, fd, fcvtl_op)}
1411 //null
1412 void cvt_w_d (FloatRegister fd, FloatRegister fs) {INSN_DOUBLE(R0, fs, fd, fcvtw_op)}
1413 //null
1414 void c_f_d (FloatRegister fs, FloatRegister ft) {INSN_DOUBLE(ft, fs, R0, f_cond)}
1415 void c_un_d (FloatRegister fs, FloatRegister ft) {INSN_DOUBLE(ft, fs, R0, un_cond)}
1416 void c_eq_d (FloatRegister fs, FloatRegister ft) {INSN_DOUBLE(ft, fs, R0, eq_cond)}
1417 void c_ueq_d (FloatRegister fs, FloatRegister ft) {INSN_DOUBLE(ft, fs, R0, ueq_cond)}
1418 void c_olt_d (FloatRegister fs, FloatRegister ft) {INSN_DOUBLE(ft, fs, R0, olt_cond)}
1419 void c_ult_d (FloatRegister fs, FloatRegister ft) {INSN_DOUBLE(ft, fs, R0, ult_cond)}
1420 void c_ole_d (FloatRegister fs, FloatRegister ft) {INSN_DOUBLE(ft, fs, R0, ole_cond)}
1421 void c_ule_d (FloatRegister fs, FloatRegister ft) {INSN_DOUBLE(ft, fs, R0, ule_cond)}
1422 void c_sf_d (FloatRegister fs, FloatRegister ft) {INSN_DOUBLE(ft, fs, R0, sf_cond)}
1423 void c_ngle_d(FloatRegister fs, FloatRegister ft) {INSN_DOUBLE(ft, fs, R0, ngle_cond)}
1424 void c_seq_d (FloatRegister fs, FloatRegister ft) {INSN_DOUBLE(ft, fs, R0, seq_cond)}
1425 void c_ngl_d (FloatRegister fs, FloatRegister ft) {INSN_DOUBLE(ft, fs, R0, ngl_cond)}
1426 void c_lt_d (FloatRegister fs, FloatRegister ft) {INSN_DOUBLE(ft, fs, R0, lt_cond)}
1427 void c_nge_d (FloatRegister fs, FloatRegister ft) {INSN_DOUBLE(ft, fs, R0, nge_cond)}
1428 void c_le_d (FloatRegister fs, FloatRegister ft) {INSN_DOUBLE(ft, fs, R0, le_cond)}
1429 void c_ngt_d (FloatRegister fs, FloatRegister ft) {INSN_DOUBLE(ft, fs, R0, ngt_cond)}
1431 #undef INSN_DOUBLE
1434 //null
1435 void cvt_s_w(FloatRegister fd, FloatRegister fs) { emit_long(insn_F3RO(word_fmt, 0, (int)fs->encoding(), (int)fd->encoding(), fcvts_op)); }
1436 void cvt_d_w(FloatRegister fd, FloatRegister fs) { emit_long(insn_F3RO(word_fmt, 0, (int)fs->encoding(), (int)fd->encoding(), fcvtd_op)); }
1437 //null
1438 void cvt_s_l(FloatRegister fd, FloatRegister fs) { emit_long(insn_F3RO(long_fmt, 0, (int)fs->encoding(), (int)fd->encoding(), fcvts_op)); }
1439 void cvt_d_l(FloatRegister fd, FloatRegister fs) { emit_long(insn_F3RO(long_fmt, 0, (int)fs->encoding(), (int)fd->encoding(), fcvtd_op)); }
1440 //null
1443 //R0->encoding() is 0; INSN_PS is enclosed by {} for ctags.
1444 #define INSN_PS(r1, r2, r3, op) \
1445 { emit_long(insn_F3RO(ps_fmt, (int)r1->encoding(), (int)r2->encoding(), (int)r3->encoding(), op));}
1447 void add_ps (FloatRegister fd, FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, fd, fadd_op)}
1448 void sub_ps (FloatRegister fd, FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, fd, fsub_op)}
1449 void mul_ps (FloatRegister fd, FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, fd, fmul_op)}
1450 //null
1451 void abs_ps (FloatRegister fd, FloatRegister fs) {INSN_PS(R0, fs, fd, fabs_op)}
1452 void mov_ps (FloatRegister fd, FloatRegister fs) {INSN_PS(R0, fs, fd, fmov_op)}
1453 void neg_ps (FloatRegister fd, FloatRegister fs) {INSN_PS(R0, fs, fd, fneg_op)}
1454 //null
1455 //void movf_ps(FloatRegister rd, FloatRegister rs, FPConditionCode cc) { unimplemented(" movf_ps")}
1456 //void movt_ps(FloatRegister rd, FloatRegister rs, FPConditionCode cc) { unimplemented(" movt_ps") }
1457 void movz_ps (FloatRegister fd, FloatRegister fs, Register rt) {INSN_PS(rt, fs, fd, movz_f_op)}
1458 void movn_ps (FloatRegister fd, FloatRegister fs, Register rt) {INSN_PS(rt, fs, fd, movn_f_op)}
1459 //null
1460 void cvt_s_pu (FloatRegister fd, FloatRegister fs) {INSN_PS(R0, fs, fd, fcvts_op)}
1461 //null
1462 void cvt_s_pl (FloatRegister fd, FloatRegister fs) {INSN_PS(R0, fs, fd, fcvtspl_op)}
1463 //null
1464 void pll_ps (FloatRegister fd, FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, fd, fpll_op)}
1465 void plu_ps (FloatRegister fd, FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, fd, fplu_op)}
1466 void pul_ps (FloatRegister fd, FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, fd, fpul_op)}
1467 void puu_ps (FloatRegister fd, FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, fd, fpuu_op)}
1468 void c_f_ps (FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, R0, f_cond)}
1469 void c_un_ps (FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, R0, un_cond)}
1470 void c_eq_ps (FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, R0, eq_cond)}
1471 void c_ueq_ps (FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, R0, ueq_cond)}
1472 void c_olt_ps (FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, R0, olt_cond)}
1473 void c_ult_ps (FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, R0, ult_cond)}
1474 void c_ole_ps (FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, R0, ole_cond)}
1475 void c_ule_ps (FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, R0, ule_cond)}
1476 void c_sf_ps (FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, R0, sf_cond)}
1477 void c_ngle_ps(FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, R0, ngle_cond)}
1478 void c_seq_ps (FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, R0, seq_cond)}
1479 void c_ngl_ps (FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, R0, ngl_cond)}
1480 void c_lt_ps (FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, R0, lt_cond)}
1481 void c_nge_ps (FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, R0, nge_cond)}
1482 void c_le_ps (FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, R0, le_cond)}
1483 void c_ngt_ps (FloatRegister fs, FloatRegister ft) {INSN_PS(ft, fs, R0, ngt_cond)}
1484 //null
1485 #undef INSN_PS
1486 //COP1 end
1489 //COP1X
1490 //R0->encoding() is 0; INSN_SINGLE is enclosed by {} for ctags.
1491 #define INSN_COP1X(r0, r1, r2, r3, op) \
1492 { emit_long(insn_F3ROX((int)r0->encoding(), (int)r1->encoding(), (int)r2->encoding(), (int)r3->encoding(), op));}
1493 void madd_s(FloatRegister fd, FloatRegister fr, FloatRegister fs, FloatRegister ft) {INSN_COP1X(fr, ft, fs, fd, madd_s_op) }
1494 void madd_d(FloatRegister fd, FloatRegister fr, FloatRegister fs, FloatRegister ft) {INSN_COP1X(fr, ft, fs, fd, madd_d_op) }
1495 void madd_ps(FloatRegister fd, FloatRegister fr, FloatRegister fs, FloatRegister ft){INSN_COP1X(fr, ft, fs, fd, madd_ps_op) }
1496 void msub_s(FloatRegister fd, FloatRegister fr, FloatRegister fs, FloatRegister ft) {INSN_COP1X(fr, ft, fs, fd, msub_s_op) }
1497 void msub_d(FloatRegister fd, FloatRegister fr, FloatRegister fs, FloatRegister ft) {INSN_COP1X(fr, ft, fs, fd, msub_d_op) }
1498 void msub_ps(FloatRegister fd, FloatRegister fr, FloatRegister fs, FloatRegister ft){INSN_COP1X(fr, ft, fs, fd, msub_ps_op) }
1499 void nmadd_s(FloatRegister fd, FloatRegister fr, FloatRegister fs, FloatRegister ft) {INSN_COP1X(fr, ft, fs, fd, nmadd_s_op) }
1500 void nmadd_d(FloatRegister fd, FloatRegister fr, FloatRegister fs, FloatRegister ft) {INSN_COP1X(fr, ft, fs, fd, nmadd_d_op) }
1501 void nmadd_ps(FloatRegister fd, FloatRegister fr, FloatRegister fs, FloatRegister ft){INSN_COP1X(fr, ft, fs, fd, nmadd_ps_op) }
1502 void nmsub_s(FloatRegister fd, FloatRegister fr, FloatRegister fs, FloatRegister ft) {INSN_COP1X(fr, ft, fs, fd, nmsub_s_op) }
1503 void nmsub_d(FloatRegister fd, FloatRegister fr, FloatRegister fs, FloatRegister ft) {INSN_COP1X(fr, ft, fs, fd, nmsub_d_op) }
1504 void nmsub_ps(FloatRegister fd, FloatRegister fr, FloatRegister fs, FloatRegister ft){INSN_COP1X(fr, ft, fs, fd, nmsub_ps_op) }
1505 #undef INSN_COP1X
1506 //COP1X end
1508 //SPECIAL2
1509 //R0->encoding() is 0; INSN_PS is enclosed by {} for ctags.
1510 #define INSN_S2(op) \
1511 { emit_long((special2_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | op);}
1513 void madd (Register rs, Register rt) { emit_long((special2_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | madd_op); }
1514 void maddu (Register rs, Register rt) { emit_long((special2_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | maddu_op); }
1515 void mul (Register rd, Register rs, Register rt) { INSN_S2(mul_op) }
1516 void gsandn (Register rd, Register rs, Register rt) { INSN_S2((0x12 << 6) | gs0x03_op) }
1517 void msub (Register rs, Register rt) { emit_long((special2_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | msub_op); }
1518 void msubu (Register rs, Register rt) { emit_long((special2_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | msubu_op); }
1519 void gsorn (Register rd, Register rs, Register rt) { INSN_S2((0x12 << 6) | gs0x06_op) }
1521 void gsmult (Register rd, Register rs, Register rt) { INSN_S2(gsmult_op) }
1522 void gsdmult (Register rd, Register rs, Register rt) { INSN_S2(gsdmult_op) }
1523 void gsmultu (Register rd, Register rs, Register rt) { INSN_S2(gsmultu_op) }
1524 void gsdmultu(Register rd, Register rs, Register rt) { INSN_S2(gsdmultu_op)}
1525 void gsdiv (Register rd, Register rs, Register rt) { INSN_S2(gsdiv_op) }
1526 void gsddiv (Register rd, Register rs, Register rt) { INSN_S2(gsddiv_op) }
1527 void gsdivu (Register rd, Register rs, Register rt) { INSN_S2(gsdivu_op) }
1528 void gsddivu (Register rd, Register rs, Register rt) { INSN_S2(gsddivu_op) }
1529 void gsmod (Register rd, Register rs, Register rt) { INSN_S2(gsmod_op) }
1530 void gsdmod (Register rd, Register rs, Register rt) { INSN_S2(gsdmod_op) }
1531 void gsmodu (Register rd, Register rs, Register rt) { INSN_S2(gsmodu_op) }
1532 void gsdmodu (Register rd, Register rs, Register rt) { INSN_S2(gsdmodu_op) }
1533 void clz (Register rd, Register rs) { emit_long((special2_op << 26) | ((int)rs->encoding() << 21) | ((int)rd->encoding() << 16) | ((int)rd->encoding() << 11) | clz_op); }
1534 void clo (Register rd, Register rs) { emit_long((special2_op << 26) | ((int)rs->encoding() << 21) | ((int)rd->encoding() << 16) | ((int)rd->encoding() << 11) | clo_op); }
1535 void ctz (Register rd, Register rs) { emit_long((special2_op << 26) | ((int)rs->encoding() << 21) | ((int)rd->encoding() << 16) | ((int)rd->encoding() << 11) | 0 << 6| xctx_op); }
1536 void cto (Register rd, Register rs) { emit_long((special2_op << 26) | ((int)rs->encoding() << 21) | ((int)rd->encoding() << 16) | ((int)rd->encoding() << 11) | 1 << 6| xctx_op); }
1537 void dctz(Register rd, Register rs) { emit_long((special2_op << 26) | ((int)rs->encoding() << 21) | ((int)rd->encoding() << 16) | ((int)rd->encoding() << 11) | 2 << 6| xctx_op); }
1538 void dcto(Register rd, Register rs) { emit_long((special2_op << 26) | ((int)rs->encoding() << 21) | ((int)rd->encoding() << 16) | ((int)rd->encoding() << 11) | 3 << 6| xctx_op); }
1539 void dclz(Register rd, Register rs) { emit_long((special2_op << 26) | ((int)rs->encoding() << 21) | ((int)rd->encoding() << 16) | ((int)rd->encoding() << 11) | dclz_op); }
1540 void dclo(Register rd, Register rs) { emit_long((special2_op << 26) | ((int)rs->encoding() << 21) | ((int)rd->encoding() << 16) | ((int)rd->encoding() << 11) | dclo_op); }
1542 #undef INSN_S2
1544 //SPECIAL3
1545 /*
1546 // FIXME
1547 #define is_0_to_32(a, b) \
1548 assert (a >= 0, " just a check"); \
1549 assert (a <= 0, " just a check"); \
1550 assert (b >= 0, " just a check"); \
1551 assert (b <= 0, " just a check"); \
1552 assert (a+b >= 0, " just a check"); \
1553 assert (a+b <= 0, " just a check");
1554 */
1555 #define is_0_to_32(a, b)
1557 void ins (Register rt, Register rs, int pos, int size) { is_0_to_32(pos, size); emit_long((special3_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | (low(pos+size-1, 5) << 11) | (low(pos, 5) << 6) | ins_op); }
1558 void dinsm(Register rt, Register rs, int pos, int size) { is_0_to_32(pos, size); emit_long((special3_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | (low(pos+size-33, 5) << 11) | (low(pos, 5) << 6) | dinsm_op); }
1559 void dinsu(Register rt, Register rs, int pos, int size) { is_0_to_32(pos, size); emit_long((special3_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | (low(pos+size-33, 5) << 11) | (low(pos-32, 5) << 6) | dinsu_op); }
1560 void dins (Register rt, Register rs, int pos, int size) {
1561 guarantee((0 <= pos) && (pos < 32), "pos must be in [0, 32)");
1562 guarantee((0 < size) && (size <= 32), "size must be in (0, 32]");
1563 guarantee((0 < pos + size) && (pos + size <= 32), "pos + size must be in (0, 32]");
1565 emit_long((special3_op << 26) | ((int)rs->encoding() << 21) | ((int)rt->encoding() << 16) | (low(pos+size-1, 5) << 11) | (low(pos, 5) << 6) | dins_op);
1566 }
1568 void repl_qb (Register rd, int const8) { emit_long((special3_op << 26) | (low(const8, 8) << 16) | ((int)rd->encoding() << 11) | repl_qb_op << 6 | re1_op); }
1569 void replv_qb(Register rd, Register rt) { emit_long((special3_op << 26) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | replv_qb_op << 6 | re1_op ); }
1570 void repl_ph (Register rd, int const10) { emit_long((special3_op << 26) | (low(const10, 10) << 16) | ((int)rd->encoding() << 11) | repl_ph_op << 6 | re1_op); }
1571 void replv_ph(Register rd, Register rt) { emit_long((special3_op << 26) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | replv_ph_op << 6 | re1_op ); }
1573 void repl_ob (Register rd, int const8) { emit_long((special3_op << 26) | (low(const8, 8) << 16) | ((int)rd->encoding() << 11) | repl_ob_op << 6 | re2_op); }
1574 void replv_ob(Register rd, Register rt) { emit_long((special3_op << 26) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | replv_ob_op << 6 | re2_op ); }
1575 void repl_qh (Register rd, int const10) { emit_long((special3_op << 26) | (low(const10, 10) << 16) | ((int)rd->encoding() << 11) | repl_qh_op << 6 | re2_op); }
1576 void replv_qh(Register rd, Register rt) { emit_long((special3_op << 26) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | replv_qh_op << 6 | re2_op ); }
1577 void repl_pw (Register rd, int const10) { emit_long((special3_op << 26) | (low(const10, 10) << 16) | ((int)rd->encoding() << 11) | repl_pw_op << 6 | re2_op); }
1578 void replv_pw(Register rd, Register rt) { emit_long((special3_op << 26) | ((int)rt->encoding() << 16) | ((int)rd->encoding() << 11) | replv_pw_op << 6 | re2_op ); }
1580 void sdc1(FloatRegister ft, Register base, int off) { emit_long(insn_ORRI(sdc1_op, (int)base->encoding(), (int)ft->encoding(), off)); }
1581 void sdc1(FloatRegister ft, Address dst);
1582 void swc1(FloatRegister ft, Register base, int off) { emit_long(insn_ORRI(swc1_op, (int)base->encoding(), (int)ft->encoding(), off)); }
1583 void swc1(FloatRegister ft, Address dst);
1586 void int3();
1587 static void print_instruction(int);
1588 int patched_branch(int dest_pos, int inst, int inst_pos);
1589 int branch_destination(int inst, int pos);
1591 /* Godson3 extension */
1593 // gssq/gslq/gssqc1/gslqc1: vAddr = sign_extend(offset << 4 ) + GPR[base]. Therefore, the off should be ">> 4".
1594 void gslble(Register rt, Register base, Register bound) {
1595 emit_long((gs_lwc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gslble_op);
1596 }
1598 void gslbgt(Register rt, Register base, Register bound) {
1599 emit_long((gs_lwc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gslbgt_op);
1600 }
1602 void gslhle(Register rt, Register base, Register bound) {
1603 emit_long((gs_lwc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gslhle_op);
1604 }
1606 void gslhgt(Register rt, Register base, Register bound) {
1607 emit_long((gs_lwc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gslhgt_op);
1608 }
1610 void gslwle(Register rt, Register base, Register bound) {
1611 emit_long((gs_lwc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gslwle_op);
1612 }
1614 void gslwgt(Register rt, Register base, Register bound) {
1615 emit_long((gs_lwc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gslwgt_op);
1616 }
1618 void gsldle(Register rt, Register base, Register bound) {
1619 emit_long((gs_lwc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gsldle_op);
1620 }
1622 void gsldgt(Register rt, Register base, Register bound) {
1623 emit_long((gs_lwc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gsldgt_op);
1624 }
1626 void gslwlec1(FloatRegister rt, Register base, Register bound) {
1627 emit_long((gs_lwc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gslwlec1_op);
1628 }
1630 void gslwgtc1(FloatRegister rt, Register base, Register bound) {
1631 emit_long((gs_lwc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gslwgtc1_op);
1632 }
1634 void gsldlec1(FloatRegister rt, Register base, Register bound) {
1635 emit_long((gs_lwc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gsldlec1_op);
1636 }
1638 void gsldgtc1(FloatRegister rt, Register base, Register bound) {
1639 emit_long((gs_lwc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gsldgtc1_op);
1640 }
1642 void gslq(Register rq, Register rt, Register base, int off) {
1643 off = off >> 4;
1644 assert(is_simm(off, 9),"gslq: off exceeds 9 bits");
1645 emit_long((gs_lwc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | 0 << 15 | (low(off, 9) << 6) | gslq_op | (int)rq->encoding() );
1646 }
1648 void gssble(Register rt, Register base, Register bound) {
1649 emit_long((gs_swc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gssble_op);
1650 }
1652 void gssbgt(Register rt, Register base, Register bound) {
1653 emit_long((gs_swc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gssbgt_op);
1654 }
1656 void gsshle(Register rt, Register base, Register bound) {
1657 emit_long((gs_swc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gsshle_op);
1658 }
1660 void gsshgt(Register rt, Register base, Register bound) {
1661 emit_long((gs_swc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gsshgt_op);
1662 }
1664 void gsswle(Register rt, Register base, Register bound) {
1665 emit_long((gs_swc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gsswle_op);
1666 }
1668 void gsswgt(Register rt, Register base, Register bound) {
1669 emit_long((gs_swc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gsswgt_op);
1670 }
1672 void gssdle(Register rt, Register base, Register bound) {
1673 emit_long((gs_swc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gssdle_op);
1674 }
1676 void gssdgt(Register rt, Register base, Register bound) {
1677 emit_long((gs_swc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gssdgt_op);
1678 }
1680 void gsswlec1(FloatRegister rt, Register base, Register bound) {
1681 emit_long((gs_swc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gsswlec1_op);
1682 }
1684 void gsswgtc1(FloatRegister rt, Register base, Register bound) {
1685 emit_long((gs_swc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gsswgtc1_op);
1686 }
1688 void gssdlec1(FloatRegister rt, Register base, Register bound) {
1689 emit_long((gs_swc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gssdlec1_op);
1690 }
1692 void gssdgtc1(FloatRegister rt, Register base, Register bound) {
1693 emit_long((gs_swc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)bound->encoding() << 11) | 0 << 6 | gssdgtc1_op);
1694 }
1696 void gssq(Register rq, Register rt, Register base, int off) {
1697 off = off >> 4;
1698 assert(is_simm(off, 9),"gssq: off exceeds 9 bits");
1699 emit_long((gs_swc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | 0 << 15 | (low(off, 9) << 6) | gssq_op | (int)rq->encoding() );
1700 }
1702 //LDC2 & SDC2
1703 #define INSN(OPS, OP) \
1704 assert(is_simm(off, 8), "NAME: off exceeds 8 bits"); \
1705 assert(UseLoongsonISA, "check LoongISA"); \
1706 emit_long( (OPS << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | \
1707 ((int)index->encoding() << 11) | (low(off, 8) << 3) | OP);
1709 #define INSN_LDC2(NAME, op) \
1710 void NAME(Register rt, Register base, Register index, int off) { \
1711 INSN(gs_ldc2_op, op) \
1712 }
1714 #define INSN_LDC2_F(NAME, op) \
1715 void NAME(FloatRegister rt, Register base, Register index, int off) { \
1716 INSN(gs_ldc2_op, op) \
1717 }
1719 #define INSN_SDC2(NAME, op) \
1720 void NAME(Register rt, Register base, Register index, int off) { \
1721 INSN(gs_sdc2_op, op) \
1722 }
1724 #define INSN_SDC2_F(NAME, op) \
1725 void NAME(FloatRegister rt, Register base, Register index, int off) { \
1726 INSN(gs_sdc2_op, op) \
1727 }
1729 /*
1730 void gslbx(Register rt, Register base, Register index, int off) {
1731 assert(is_simm(off, 8), "gslbx: off exceeds 8 bits");
1732 assert(UseLoongsonISA, "check LoongISA");
1733 emit_long( (gs_ldc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) |
1734 ((int)index->encoding() << 11) | (low(off, 8) << 3) | gslbx_op);
1735 void gslbx(Register rt, Register base, Register index, int off) {INSN(gs_ldc2_op, gslbx_op);}
1737 INSN_LDC2(gslbx, gslbx_op)
1738 INSN_LDC2(gslhx, gslhx_op)
1739 INSN_LDC2(gslwx, gslwx_op)
1740 INSN_LDC2(gsldx, gsldx_op)
1741 INSN_LDC2_F(gslwxc1, gslwxc1_op)
1742 INSN_LDC2_F(gsldxc1, gsldxc1_op)
1744 INSN_SDC2(gssbx, gssbx_op)
1745 INSN_SDC2(gsshx, gsshx_op)
1746 INSN_SDC2(gsswx, gsswx_op)
1747 INSN_SDC2(gssdx, gssdx_op)
1748 INSN_SDC2_F(gsswxc1, gsswxc1_op)
1749 INSN_SDC2_F(gssdxc1, gssdxc1_op)
1750 */
1751 void gslbx(Register rt, Register base, Register index, int off) {INSN(gs_ldc2_op, gslbx_op) }
1752 void gslhx(Register rt, Register base, Register index, int off) {INSN(gs_ldc2_op, gslhx_op) }
1753 void gslwx(Register rt, Register base, Register index, int off) {INSN(gs_ldc2_op, gslwx_op) }
1754 void gsldx(Register rt, Register base, Register index, int off) {INSN(gs_ldc2_op, gsldx_op) }
1755 void gslwxc1(FloatRegister rt, Register base, Register index, int off) {INSN(gs_ldc2_op, gslwxc1_op) }
1756 void gsldxc1(FloatRegister rt, Register base, Register index, int off) {INSN(gs_ldc2_op, gsldxc1_op) }
1758 void gssbx(Register rt, Register base, Register index, int off) {INSN(gs_sdc2_op, gssbx_op) }
1759 void gsshx(Register rt, Register base, Register index, int off) {INSN(gs_sdc2_op, gsshx_op) }
1760 void gsswx(Register rt, Register base, Register index, int off) {INSN(gs_sdc2_op, gsswx_op) }
1761 void gssdx(Register rt, Register base, Register index, int off) {INSN(gs_sdc2_op, gssdx_op) }
1762 void gsswxc1(FloatRegister rt, Register base, Register index, int off) {INSN(gs_sdc2_op, gsswxc1_op) }
1763 void gssdxc1(FloatRegister rt, Register base, Register index, int off) {INSN(gs_sdc2_op, gssdxc1_op) }
1765 #undef INSN
1766 #undef INSN_LDC2
1767 #undef INSN_LDC2_F
1768 #undef INSN_SDC2
1769 #undef INSN_SDC2_F
1772 public:
1773 // Creation
1774 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1775 #ifdef CHECK_DELAY
1776 delay_state = no_delay;
1777 #endif
1778 }
1780 // Decoding
1781 static address locate_operand(address inst, WhichOperand which);
1782 static address locate_next_instruction(address inst);
1783 };
1786 // MacroAssembler extends Assembler by frequently used macros.
1787 //
1788 // Instructions for which a 'better' code sequence exists depending
1789 // on arguments should also go in here.
1791 class MacroAssembler: public Assembler {
1792 friend class LIR_Assembler;
1793 friend class Runtime1; // as_Address()
1795 public:
1796 static intptr_t i[32];
1797 static float f[32];
1798 static void print(outputStream *s);
1800 static int i_offset(unsigned int k);
1801 static int f_offset(unsigned int k);
1803 static void save_registers(MacroAssembler *masm);
1804 static void restore_registers(MacroAssembler *masm);
1806 protected:
1808 Address as_Address(AddressLiteral adr);
1809 Address as_Address(ArrayAddress adr);
1811 // Support for VM calls
1812 //
1813 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1814 // may customize this version by overriding it for its purposes (e.g., to save/restore
1815 // additional registers when doing a VM call).
1816 #ifdef CC_INTERP
1817 // c++ interpreter never wants to use interp_masm version of call_VM
1818 #define VIRTUAL
1819 #else
1820 #define VIRTUAL virtual
1821 #endif
1823 VIRTUAL void call_VM_leaf_base(
1824 address entry_point, // the entry point
1825 int number_of_arguments // the number of arguments to pop after the call
1826 );
1828 // This is the base routine called by the different versions of call_VM. The interpreter
1829 // may customize this version by overriding it for its purposes (e.g., to save/restore
1830 // additional registers when doing a VM call).
1831 //
1832 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
1833 // returns the register which contains the thread upon return. If a thread register has been
1834 // specified, the return value will correspond to that register. If no last_java_sp is specified
1835 // (noreg) than rsp will be used instead.
1836 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
1837 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1838 Register java_thread, // the thread if computed before ; use noreg otherwise
1839 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1840 address entry_point, // the entry point
1841 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
1842 bool check_exceptions // whether to check for pending exceptions after return
1843 );
1845 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1846 // The implementation is only non-empty for the InterpreterMacroAssembler,
1847 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1848 virtual void check_and_handle_popframe(Register java_thread);
1849 virtual void check_and_handle_earlyret(Register java_thread);
1851 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
1853 // helpers for FPU flag access
1854 // tmp is a temporary register, if none is available use noreg
1855 //void save_rax (Register tmp);
1856 //void restore_rax(Register tmp);
1858 public:
1859 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1861 // Support for NULL-checks
1862 //
1863 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1864 // If the accessed location is M[reg + offset] and the offset is known, provide the
1865 // offset. No explicit code generation is needed if the offset is within a certain
1866 // range (0 <= offset <= page_size).
1867 // use "teq 83, reg" in mips now, by yjl 6/20/2005
1868 void null_check(Register reg, int offset = -1);
1869 static bool needs_explicit_null_check(intptr_t offset);
1871 // Required platform-specific helpers for Label::patch_instructions.
1872 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1873 void pd_patch_instruction(address branch, address target);
1875 // Alignment
1876 void align(int modulus);
1878 // Misc
1879 //void fat_nop(); // 5 byte nop
1881 // Stack frame creation/removal
1882 void enter();
1883 void leave();
1885 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
1886 // The pointer will be loaded into the thread register.
1887 void get_thread(Register thread);
1890 // Support for VM calls
1891 //
1892 // It is imperative that all calls into the VM are handled via the call_VM macros.
1893 // They make sure that the stack linkage is setup correctly. call_VM's correspond
1894 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1897 void call_VM(Register oop_result,
1898 address entry_point,
1899 bool check_exceptions = true);
1900 void call_VM(Register oop_result,
1901 address entry_point,
1902 Register arg_1,
1903 bool check_exceptions = true);
1904 void call_VM(Register oop_result,
1905 address entry_point,
1906 Register arg_1, Register arg_2,
1907 bool check_exceptions = true);
1908 void call_VM(Register oop_result,
1909 address entry_point,
1910 Register arg_1, Register arg_2, Register arg_3,
1911 bool check_exceptions = true);
1912 // Super call_VM calls - correspond to MacroAssembler::call_VM(_leaf) calls
1913 void super_call_VM_leaf(address entry_point);
1914 void super_call_VM_leaf(address entry_point, Register arg_1);
1915 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
1916 void super_call_VM_leaf(address entry_point,
1917 Register arg_1, Register arg_2, Register arg_3);
1919 // Overloadings with last_Java_sp
1920 void call_VM(Register oop_result,
1921 Register last_java_sp,
1922 address entry_point,
1923 int number_of_arguments = 0,
1924 bool check_exceptions = true);
1925 void call_VM(Register oop_result,
1926 Register last_java_sp,
1927 address entry_point,
1928 Register arg_1, bool
1929 check_exceptions = true);
1930 void call_VM(Register oop_result,
1931 Register last_java_sp,
1932 address entry_point,
1933 Register arg_1, Register arg_2,
1934 bool check_exceptions = true);
1935 void call_VM(Register oop_result,
1936 Register last_java_sp,
1937 address entry_point,
1938 Register arg_1, Register arg_2, Register arg_3,
1939 bool check_exceptions = true);
1941 void call_VM_leaf(address entry_point,
1942 int number_of_arguments = 0);
1943 void call_VM_leaf(address entry_point,
1944 Register arg_1);
1945 void call_VM_leaf(address entry_point,
1946 Register arg_1, Register arg_2);
1947 void call_VM_leaf(address entry_point,
1948 Register arg_1, Register arg_2, Register arg_3);
1950 // last Java Frame (fills frame anchor)
1951 void set_last_Java_frame(Register thread,
1952 Register last_java_sp,
1953 Register last_java_fp,
1954 address last_java_pc);
1956 // thread in the default location (r15_thread on 64bit)
1957 void set_last_Java_frame(Register last_java_sp,
1958 Register last_java_fp,
1959 address last_java_pc);
1961 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
1963 // thread in the default location (r15_thread on 64bit)
1964 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
1966 // Stores
1967 void store_check(Register obj); // store check for obj - register is destroyed afterwards
1968 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
1971 void g1_write_barrier_pre(Register obj,
1972 #ifndef _LP64
1973 Register thread,
1974 #endif
1975 Register tmp,
1976 Register tmp2,
1977 bool tosca_live);
1978 void g1_write_barrier_post(Register store_addr,
1979 Register new_val,
1980 #ifndef _LP64
1981 Register thread,
1982 #endif
1983 Register tmp,
1984 Register tmp2);
1988 // split store_check(Register obj) to enhance instruction interleaving
1989 void store_check_part_1(Register obj);
1990 void store_check_part_2(Register obj);
1992 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
1993 void c2bool(Register x);
1994 //add for compressedoops
1995 void load_klass(Register dst, Register src);
1996 void store_klass(Register dst, Register src);
1997 void load_prototype_header(Register dst, Register src);
1998 /*
1999 // C++ bool manipulation
2001 void movbool(Register dst, Address src);
2002 void movbool(Address dst, bool boolconst);
2003 void movbool(Address dst, Register src);
2004 void testbool(Register dst);
2006 // oop manipulations
2007 void load_klass(Register dst, Register src);
2008 void store_klass(Register dst, Register src);
2010 void load_prototype_header(Register dst, Register src);*/
2012 #ifdef _LP64
2013 void store_klass_gap(Register dst, Register src);
2015 void load_heap_oop(Register dst, Address src);
2016 void store_heap_oop(Address dst, Register src);
2017 void encode_heap_oop(Register r);
2018 void encode_heap_oop(Register dst, Register src);
2019 void decode_heap_oop(Register r);
2020 void decode_heap_oop(Register dst, Register src);
2021 void encode_heap_oop_not_null(Register r);
2022 void decode_heap_oop_not_null(Register r);
2023 void encode_heap_oop_not_null(Register dst, Register src);
2024 void decode_heap_oop_not_null(Register dst, Register src);
2026 void encode_klass_not_null(Register r);
2027 void decode_klass_not_null(Register r);
2028 void encode_klass_not_null(Register dst, Register src);
2029 void decode_klass_not_null(Register dst, Register src);
2031 //void set_narrow_oop(Register dst, jobject obj);
2033 // Returns the byte size of the instructions generated by decode_klass_not_null()
2034 // when compressed klass pointers are being used.
2035 static int instr_size_for_decode_klass_not_null();
2037 // if heap base register is used - reinit it with the correct value
2038 void reinit_heapbase();
2039 DEBUG_ONLY(void verify_heapbase(const char* msg);)
2041 void set_narrow_klass(Register dst, Klass* k);
2042 void set_narrow_oop(Register dst, jobject obj);
2044 #endif // _LP64
2046 void incrementl(Register reg, int value = 1);
2048 void decrementl(Register reg, int value = 1);
2050 /*
2051 // Int division/remainder for Java
2052 // (as idivl, but checks for special case as described in JVM spec.)
2053 // returns idivl instruction offset for implicit exception handling
2054 int corrected_idivl(Register reg);
2056 // Long division/remainder for Java
2057 // (as idivq, but checks for special case as described in JVM spec.)
2058 // returns idivq instruction offset for implicit exception handling
2059 int corrected_idivq(Register reg);
2060 */
2062 void int3();
2063 /*
2064 // Long operation macros for a 32bit cpu
2065 // Long negation for Java
2066 void lneg(Register hi, Register lo);
2068 // Long multiplication for Java
2069 // (destroys contents of eax, ebx, ecx and edx)
2070 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
2072 // Long shifts for Java
2073 // (semantics as described in JVM spec.)
2074 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
2075 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
2077 // Long compare for Java
2078 // (semantics as described in JVM spec.)
2079 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
2082 // misc
2083 */
2084 // Sign extension
2085 #ifdef _LP64
2086 void sign_extend_short(Register reg) { /*dsll32(reg, reg, 16); dsra32(reg, reg, 16);*/ seh(reg, reg); }
2087 void sign_extend_byte(Register reg) { /*dsll32(reg, reg, 24); dsra32(reg, reg, 24);*/ seb(reg, reg); }
2088 #else
2089 void sign_extend_short(Register reg) { /*sll(reg, reg, 16); sra(reg, reg, 16);*/ seh(reg, reg); }
2090 void sign_extend_byte(Register reg) { /*sll(reg, reg, 24); sra(reg, reg, 24);*/ seb(reg, reg);}
2091 #endif
2092 void rem_s(FloatRegister fd, FloatRegister fs, FloatRegister ft, FloatRegister tmp);
2093 void rem_d(FloatRegister fd, FloatRegister fs, FloatRegister ft, FloatRegister tmp);
2095 // Inlined sin/cos generator for Java; must not use CPU instruction
2096 // directly on Intel as it does not have high enough precision
2097 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
2098 // number of FPU stack slots in use; all but the topmost will
2099 // require saving if a slow case is necessary. Assumes argument is
2100 // on FP TOS; result is on FP TOS. No cpu registers are changed by
2101 // this code.
2102 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
2103 /*
2104 // branch to L if FPU flag C2 is set/not set
2105 // tmp is a temporary register, if none is available use noreg
2106 void jC2 (Register tmp, Label& L);
2107 void jnC2(Register tmp, Label& L);
2109 // Pop ST (ffree & fincstp combined)
2110 void fpop();
2112 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
2113 void push_fTOS();
2115 // pops double TOS element from CPU stack and pushes on FPU stack
2116 void pop_fTOS();
2118 void empty_FPU_stack();
2120 void push_IU_state();
2121 void pop_IU_state();
2123 void push_FPU_state();
2124 void pop_FPU_state();
2126 void push_CPU_state();
2127 void pop_CPU_state();
2129 // Round up to a power of two
2130 void round_to(Register reg, int modulus);
2132 // Callee saved registers handling
2133 void push_callee_saved_registers();
2134 void pop_callee_saved_registers();
2135 */
2136 // allocation
2137 void eden_allocate(
2138 Register obj, // result: pointer to object after successful allocation
2139 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2140 int con_size_in_bytes, // object size in bytes if known at compile time
2141 Register t1, // temp register
2142 Register t2,
2143 Label& slow_case // continuation point if fast allocation fails
2144 );
2145 void tlab_allocate(
2146 Register obj, // result: pointer to object after successful allocation
2147 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2148 int con_size_in_bytes, // object size in bytes if known at compile time
2149 Register t1, // temp register
2150 Register t2, // temp register
2151 Label& slow_case // continuation point if fast allocation fails
2152 );
2153 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
2155 // void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
2158 // Debugging
2160 // only if +VerifyOops
2161 void verify_oop(Register reg, const char* s = "broken oop");
2162 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
2163 void verify_oop_subroutine();
2164 // TODO: verify method and klass metadata (compare against vptr?)
2165 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
2166 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
2168 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
2169 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
2171 // only if +VerifyFPU
2172 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
2174 // prints msg, dumps registers and stops execution
2175 void stop(const char* msg);
2177 // prints msg and continues
2178 void warn(const char* msg);
2180 static void debug(char* msg/*, RegistersForDebugging* regs*/);
2181 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
2182 static void debug64(char* msg, int64_t pc, int64_t regs[]);
2184 void print_reg(Register reg);
2185 void print_reg(FloatRegister reg);
2186 //void os_breakpoint();
2188 void untested() { stop("untested"); }
2190 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, sizeof(b), "unimplemented: %s", what); stop(b); }
2192 void should_not_reach_here() { stop("should not reach here"); }
2194 void print_CPU_state();
2196 // Stack overflow checking
2197 void bang_stack_with_offset(int offset) {
2198 // stack grows down, caller passes positive offset
2199 assert(offset > 0, "must bang with negative offset");
2200 if (offset <= 32768) {
2201 sw(A0, SP, -offset);
2202 } else {
2203 #ifdef _LP64
2204 li(AT, offset);
2205 dsub(AT, SP, AT);
2206 #else
2207 move(AT, offset);
2208 sub(AT, SP, AT);
2209 #endif
2210 sw(A0, AT, 0);
2211 }
2212 }
2214 // Writes to stack successive pages until offset reached to check for
2215 // stack overflow + shadow pages. Also, clobbers tmp
2216 void bang_stack_size(Register size, Register tmp);
2217 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2218 Register tmp,
2219 int offset);
2221 // Support for serializing memory accesses between threads
2222 void serialize_memory(Register thread, Register tmp);
2224 //void verify_tlab();
2225 void verify_tlab(Register t1, Register t2);
2227 // Biased locking support
2228 // lock_reg and obj_reg must be loaded up with the appropriate values.
2229 // swap_reg must be rax, and is killed.
2230 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
2231 // be killed; if not supplied, push/pop will be used internally to
2232 // allocate a temporary (inefficient, avoid if possible).
2233 // Optional slow case is for implementations (interpreter and C1) which branch to
2234 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
2235 // Returns offset of first potentially-faulting instruction for null
2236 // check info (currently consumed only by C1). If
2237 // swap_reg_contains_mark is true then returns -1 as it is assumed
2238 // the calling code has already passed any potential faults.
2239 int biased_locking_enter(Register lock_reg, Register obj_reg,
2240 Register swap_reg, Register tmp_reg,
2241 bool swap_reg_contains_mark,
2242 Label& done, Label* slow_case = NULL,
2243 BiasedLockingCounters* counters = NULL);
2244 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
2247 // Calls
2249 void call(address entry);
2250 void call(address entry, relocInfo::relocType rtype);
2251 void call(address entry, RelocationHolder& rh);
2252 // Emit the CompiledIC call idiom
2253 void ic_call(address entry);
2255 void jmp(address entry);
2256 void jmp(address entry, relocInfo::relocType rtype);
2258 // Argument ops
2259 /*inline void store_int_argument(Register s, Argument& a);
2260 inline void store_long_argument(Register s, Argument& a);
2261 inline void store_float_argument(FloatRegister s, Argument& a);
2262 inline void store_double_argument(FloatRegister s, Argument& a);
2263 inline void store_ptr_argument(Register s, Argument& a);*/
2264 inline void store_int_argument(Register s, Argument &a) {
2265 if(a.is_Register()) {
2266 move(a.as_Register(), s);
2267 } else {
2268 sw(s, a.as_caller_address());
2269 }
2270 }
2272 inline void store_long_argument(Register s, Argument &a) {
2273 Argument a1 = a.successor();
2274 if(a.is_Register() && a1.is_Register()) {
2275 move(a.as_Register(), s);
2276 move(a.as_Register(), s);
2277 } else {
2278 sd(s, a.as_caller_address());
2279 }
2280 }
2282 inline void store_float_argument(FloatRegister s, Argument &a) {
2283 if(a.is_Register()) {
2284 mov_s(a.as_FloatRegister(), s);
2285 } else {
2286 swc1(s, a.as_caller_address());
2287 }
2288 }
2289 inline void store_double_argument(FloatRegister s, Argument &a) {
2290 if(a.is_Register()) {
2291 mov_d(a.as_FloatRegister(), s);
2292 } else {
2293 sdc1(s, a.as_caller_address());
2294 }
2295 }
2297 inline void store_ptr_argument(Register s, Argument &a) {
2298 if(a.is_Register()) {
2299 move(a.as_Register(), s);
2300 } else {
2301 st_ptr(s, a.as_caller_address());
2302 }
2303 }
2305 // Load and store values by size and signed-ness
2306 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
2307 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
2309 // interface method calling
2310 void lookup_interface_method(Register recv_klass,
2311 Register intf_klass,
2312 RegisterOrConstant itable_index,
2313 Register method_result,
2314 Register scan_temp,
2315 Label& no_such_interface);
2316 // virtual method calling
2317 void lookup_virtual_method(Register recv_klass,
2318 RegisterOrConstant vtable_index,
2319 Register method_result);
2321 // ld_ptr will perform lw for 32 bit VMs and ld for 64 bit VMs
2322 // st_ptr will perform sw for 32 bit VMs and sd for 64 bit VMs
2323 inline void ld_ptr(Register rt, Address a){
2324 #ifdef _LP64
2325 ld(rt, a.base(), a.disp());
2326 #else
2327 lw(rt, a.base(), a.disp());
2328 #endif
2329 }
2330 inline void ld_ptr(Register rt, Register base, int offset16){
2331 #ifdef _LP64
2332 ld(rt, base, offset16);
2333 #else
2334 lw(rt, base, offset16);
2335 #endif
2337 }
2338 inline void st_ptr(Register rt, Address a){
2339 #ifdef _LP64
2340 sd(rt, a.base(), a.disp());
2341 #else
2342 sw(rt, a.base(), a.disp());
2343 #endif
2344 }
2345 inline void st_ptr(Register rt, Register base, int offset16) {
2346 #ifdef _LP64
2347 sd(rt, base, offset16);
2348 #else
2349 sw(rt, base, offset16);
2350 #endif
2352 }
2354 void ld_ptr(Register rt, Register offset, Register base);
2355 void st_ptr(Register rt, Register offset, Register base);
2357 // ld_long will perform lw for 32 bit VMs and ld for 64 bit VMs
2358 // st_long will perform sw for 32 bit VMs and sd for 64 bit VMs
2359 inline void ld_long(Register rt, Register base, int offset16);
2360 inline void st_long(Register rt, Register base, int offset16);
2361 inline void ld_long(Register rt, Address a);
2362 inline void st_long(Register rt, Address a);
2365 void ld_long(Register rt, Register offset, Register base);
2366 void st_long(Register rt, Register offset, Register base);
2367 // Regular vs. d* versions
2368 inline void addu_long(Register rd, Register rs, Register rt) {
2369 #ifdef _LP64
2370 daddu(rd, rs, rt);
2371 #else
2372 addu(rd, rs, rt);
2373 #endif
2374 }
2375 inline void addu_long(Register rd, Register rs, long imm32_64) {
2376 #ifdef _LP64
2377 daddiu(rd, rs, imm32_64);
2378 #else
2379 addiu(rd, rs, imm32_64);
2380 #endif
2382 }
2384 // Floating
2385 public:
2386 // swap the two byte of the low 16-bit halfword
2387 // this directive will use AT, be sure the high 16-bit of reg is zero
2388 // by yjl 6/28/2005
2389 void hswap(Register reg);
2390 void huswap(Register reg);
2392 // convert big endian integer to little endian integer
2393 // by yjl 6/29/2005
2394 void swap(Register reg);
2396 // implement the x86 instruction semantic
2397 // if c_reg == *dest then *dest <= x_reg
2398 // else c_reg <= *dest
2399 // the AT indicate if xchg occurred, 1 for xchged, else 0
2400 // by yjl 6/28/2005
2401 void cmpxchg(Register x_reg, Address dest, Register c_reg);
2402 #ifdef _LP64
2403 void cmpxchg32(Register x_reg, Address dest, Register c_reg);
2404 #endif
2405 void cmpxchg8(Register x_regLo, Register x_regHi, Address dest, Register c_regLo, Register c_regHi);
2409 void round_to(Register reg, int modulus) {
2410 assert_different_registers(reg, AT);
2411 increment(reg, modulus - 1);
2412 move(AT, - modulus);
2413 andr(reg, reg, AT);
2414 }
2416 //pop & push, added by aoqi
2417 #ifdef _LP64
2418 void extend_sign(Register rh, Register rl) { stop("extend_sign"); }
2419 void neg(Register reg) { dsubu(reg, R0, reg); }
2420 void push (Register reg) { sd (reg, SP, -8); daddi(SP, SP, -8); }
2421 void push (FloatRegister reg) { sdc1(reg, SP, -8); daddi(SP, SP, -8); }
2422 void pop (Register reg) { ld (reg, SP, 0); daddi(SP, SP, 8); }
2423 void pop (FloatRegister reg) { ldc1(reg, SP, 0); daddi(SP, SP, 8); }
2424 void pop () { daddi(SP, SP, 8); }
2425 void pop2 () { daddi(SP, SP, 16); }
2426 #else
2427 void extend_sign(Register rh, Register rl) { sra(rh, rl, 31); }
2428 void neg(Register reg) { subu(reg, R0, reg); }
2429 void push (Register reg) { sw (reg, SP, -4); addi(SP, SP, -4); }
2430 void push (FloatRegister reg) { swc1(reg, SP, -4); addi(SP, SP, -4); }
2431 void pop (Register reg) { lw (reg, SP, 0); addi(SP, SP, 4); }
2432 void pop (FloatRegister reg) { lwc1(reg, SP, 0); addi(SP, SP, 4); }
2433 void pop () { addi(SP, SP, 4); }
2434 void pop2 () { addi(SP, SP, 8); }
2435 #endif
2436 void push2(Register reg1, Register reg2);
2437 void pop2 (Register reg1, Register reg2);
2438 void dpush (Register reg) { sd (reg, SP, -8); daddi(SP, SP, -8); }
2439 void dpop (Register reg) { ld (reg, SP, 0); daddi(SP, SP, 8); }
2441 /* branches may exceed 16-bit offset */
2442 void b_far(address entry);
2443 void b_far(Label& L);
2445 void bne_far (Register rs, Register rt, address entry);
2446 void bne_far (Register rs, Register rt, Label& L);
2448 void beq_far (Register rs, Register rt, address entry);
2449 void beq_far (Register rs, Register rt, Label& L);
2451 //move an 32-bit immediate to Register
2452 void move(Register reg, int imm32) { li32(reg, imm32); }
2453 void li (Register rd, long imm);
2454 void li (Register rd, address addr) { li(rd, (long)addr); }
2455 //replace move(Register reg, int imm)
2456 void li32(Register rd, int imm32); // sign-extends to 64 bits on mips64
2457 #ifdef _LP64
2458 void set64(Register d, jlong value);
2459 static int insts_for_set64(jlong value);
2461 void patchable_set48(Register d, jlong value);
2462 void patchable_set32(Register d, jlong value);
2464 void patchable_call32(Register d, jlong value);
2466 static int call_size(address target, bool far, bool patchable);
2468 static bool reachable_from_cache(address target);
2470 void patchable_call(address target);
2471 void general_call(address target);
2473 void patchable_jump(address target);
2474 void general_jump(address target);
2476 void dli(Register rd, long imm) { li(rd, imm); }
2477 void li64(Register rd, long imm);
2478 void li48(Register rd, long imm);
2479 #endif
2481 #ifdef _LP64
2482 void move(Register rd, Register rs) { dadd(rd, rs, R0); }
2483 void move_u32(Register rd, Register rs) { addu32(rd, rs, R0); }
2484 #else
2485 void move(Register rd, Register rs) { add(rd, rs, R0); }
2486 #endif
2487 void dmove(Register rd, Register rs) { dadd(rd, rs, R0); }
2489 #ifdef _LP64
2490 void shl(Register reg, int sa) { dsll(reg, reg, sa); }
2491 void shr(Register reg, int sa) { dsrl(reg, reg, sa); }
2492 void sar(Register reg, int sa) { dsra(reg, reg, sa); }
2493 #else
2494 void shl(Register reg, int sa) { sll(reg, reg, sa); }
2495 void shr(Register reg, int sa) { srl(reg, reg, sa); }
2496 void sar(Register reg, int sa) { sra(reg, reg, sa); }
2497 #endif
2499 #ifndef PRODUCT
2500 static void pd_print_patched_instruction(address branch) {
2501 jint stub_inst = *(jint*) branch;
2502 print_instruction(stub_inst);
2503 ::tty->print("%s", " (unresolved)");
2505 }
2506 #endif
2508 // the follow two might use AT register, be sure you have no meanful data in AT before you call them
2509 void increment(Register reg, int imm);
2510 void decrement(Register reg, int imm);
2512 //FIXME
2513 void empty_FPU_stack(){/*need implemented*/};
2515 //we need 2 fun to save and resotre general register
2516 void pushad();
2517 void popad();
2519 // Test sub_klass against super_klass, with fast and slow paths.
2521 // The fast path produces a tri-state answer: yes / no / maybe-slow.
2522 // One of the three labels can be NULL, meaning take the fall-through.
2523 // If super_check_offset is -1, the value is loaded up from super_klass.
2524 // No registers are killed, except temp_reg.
2525 void check_klass_subtype_fast_path(Register sub_klass,
2526 Register super_klass,
2527 Register temp_reg,
2528 Label* L_success,
2529 Label* L_failure,
2530 Label* L_slow_path,
2531 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
2533 // The rest of the type check; must be wired to a corresponding fast path.
2534 // It does not repeat the fast path logic, so don't use it standalone.
2535 // The temp_reg and temp2_reg can be noreg, if no temps are available.
2536 // Updates the sub's secondary super cache as necessary.
2537 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
2538 void check_klass_subtype_slow_path(Register sub_klass,
2539 Register super_klass,
2540 Register temp_reg,
2541 Register temp2_reg,
2542 Label* L_success,
2543 Label* L_failure,
2544 bool set_cond_codes = false);
2546 // Simplified, combined version, good for typical uses.
2547 // Falls through on failure.
2548 void check_klass_subtype(Register sub_klass,
2549 Register super_klass,
2550 Register temp_reg,
2551 Label& L_success);
2553 // method handles (JSR 292)
2554 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
2556 void get_vm_result (Register oop_result, Register thread);
2557 void get_vm_result_2(Register metadata_result, Register thread);
2558 #undef VIRTUAL
2559 void atomic_inc32(address counter_addr, int inc, Register tmp_reg1, Register tmp_reg2);
2561 void fast_lock(Register obj, Register box, Register tmp, Register scr);
2562 void fast_unlock(Register obj, Register box, Register tmp);
2563 };
2565 /**
2566 * class SkipIfEqual:
2567 *
2568 * Instantiating this class will result in assembly code being output that will
2569 * jump around any code emitted between the creation of the instance and it's
2570 * automatic destruction at the end of a scope block, depending on the value of
2571 * the flag passed to the constructor, which will be checked at run-time.
2572 */
2573 class SkipIfEqual {
2574 private:
2575 MacroAssembler* _masm;
2576 Label _label;
2578 public:
2579 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
2580 ~SkipIfEqual();
2581 };
2583 #ifdef ASSERT
2584 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
2585 #endif
2587 #endif // CPU_MIPS_VM_ASSEMBLER_MIPS_HPP