Mercurial > jdk8-mips64-public > hotspot / file revision

 //

 // Copyright (c) 2003, 2011, Oracle and/or its affiliates. All rights reserved.

 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 //

 // This code is free software; you can redistribute it and/or modify it

 // under the terms of the GNU General Public License version 2 only, as

 // published by the Free Software Foundation.

 //

 // This code is distributed in the hope that it will be useful, but WITHOUT

 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 // version 2 for more details (a copy is included in the LICENSE file that

 // accompanied this code).

 //

 // You should have received a copy of the GNU General Public License version

 // 2 along with this work; if not, write to the Free Software Foundation,

 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 //

 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 // or visit www.oracle.com if you need additional information or have any

 // questions.

 //

 //

 // AMD64 Architecture Description File

 //----------REGISTER DEFINITION BLOCK------------------------------------------

 // This information is used by the matcher and the register allocator to

 // describe individual registers and classes of registers within the target

 // archtecture.

 register %{

 //----------Architecture Description Register Definitions----------------------

 // General Registers

 // "reg_def"  name ( register save type, C convention save type,

 //                   ideal register type, encoding );

 // Register Save Types:

 //

 // NS  = No-Save:       The register allocator assumes that these registers

 //                      can be used without saving upon entry to the method, &

 //                      that they do not need to be saved at call sites.

 //

 // SOC = Save-On-Call:  The register allocator assumes that these registers

 //                      can be used without saving upon entry to the method,

 //                      but that they must be saved at call sites.

 //

 // SOE = Save-On-Entry: The register allocator assumes that these registers

 //                      must be saved before using them upon entry to the

 //                      method, but they do not need to be saved at call

 //                      sites.

 //

 // AS  = Always-Save:   The register allocator assumes that these registers

 //                      must be saved before using them upon entry to the

 //                      method, & that they must be saved at call sites.

 //

 // Ideal Register Type is used to determine how to save & restore a

 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get

 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.

 //

 // The encoding number is the actual bit-pattern placed into the opcodes.

 // General Registers

 // R8-R15 must be encoded with REX.  (RSP, RBP, RSI, RDI need REX when

 // used as byte registers)

 // Previously set RBX, RSI, and RDI as save-on-entry for java code

 // Turn off SOE in java-code due to frequent use of uncommon-traps.

 // Now that allocator is better, turn on RSI and RDI as SOE registers.

 reg_def RAX  (SOC, SOC, Op_RegI,  0, rax->as_VMReg());

 reg_def RAX_H(SOC, SOC, Op_RegI,  0, rax->as_VMReg()->next());

 reg_def RCX  (SOC, SOC, Op_RegI,  1, rcx->as_VMReg());

 reg_def RCX_H(SOC, SOC, Op_RegI,  1, rcx->as_VMReg()->next());

 reg_def RDX  (SOC, SOC, Op_RegI,  2, rdx->as_VMReg());

 reg_def RDX_H(SOC, SOC, Op_RegI,  2, rdx->as_VMReg()->next());

 reg_def RBX  (SOC, SOE, Op_RegI,  3, rbx->as_VMReg());

 reg_def RBX_H(SOC, SOE, Op_RegI,  3, rbx->as_VMReg()->next());

 reg_def RSP  (NS,  NS,  Op_RegI,  4, rsp->as_VMReg());

 reg_def RSP_H(NS,  NS,  Op_RegI,  4, rsp->as_VMReg()->next());

 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code

 reg_def RBP  (NS, SOE, Op_RegI,  5, rbp->as_VMReg());

 reg_def RBP_H(NS, SOE, Op_RegI,  5, rbp->as_VMReg()->next());

 #ifdef _WIN64

 reg_def RSI  (SOC, SOE, Op_RegI,  6, rsi->as_VMReg());

 reg_def RSI_H(SOC, SOE, Op_RegI,  6, rsi->as_VMReg()->next());

 reg_def RDI  (SOC, SOE, Op_RegI,  7, rdi->as_VMReg());

 reg_def RDI_H(SOC, SOE, Op_RegI,  7, rdi->as_VMReg()->next());

 #else

 reg_def RSI  (SOC, SOC, Op_RegI,  6, rsi->as_VMReg());

 reg_def RSI_H(SOC, SOC, Op_RegI,  6, rsi->as_VMReg()->next());

 reg_def RDI  (SOC, SOC, Op_RegI,  7, rdi->as_VMReg());

 reg_def RDI_H(SOC, SOC, Op_RegI,  7, rdi->as_VMReg()->next());

 #endif

 reg_def R8   (SOC, SOC, Op_RegI,  8, r8->as_VMReg());

 reg_def R8_H (SOC, SOC, Op_RegI,  8, r8->as_VMReg()->next());

 reg_def R9   (SOC, SOC, Op_RegI,  9, r9->as_VMReg());

 reg_def R9_H (SOC, SOC, Op_RegI,  9, r9->as_VMReg()->next());

 reg_def R10  (SOC, SOC, Op_RegI, 10, r10->as_VMReg());

 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());

 reg_def R11  (SOC, SOC, Op_RegI, 11, r11->as_VMReg());

 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());

 reg_def R12  (SOC, SOE, Op_RegI, 12, r12->as_VMReg());

 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());

 reg_def R13  (SOC, SOE, Op_RegI, 13, r13->as_VMReg());

 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());

 reg_def R14  (SOC, SOE, Op_RegI, 14, r14->as_VMReg());

 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());

 reg_def R15  (SOC, SOE, Op_RegI, 15, r15->as_VMReg());

 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());

 // Floating Point Registers

 // XMM registers.  128-bit registers or 4 words each, labeled (a)-d.

 // Word a in each register holds a Float, words ab hold a Double.  We

 // currently do not use the SIMD capabilities, so registers cd are

 // unused at the moment.

 // XMM8-XMM15 must be encoded with REX.

 // Linux ABI:   No register preserved across function calls

 //              XMM0-XMM7 might hold parameters

 // Windows ABI: XMM6-XMM15 preserved across function calls

 //              XMM0-XMM3 might hold parameters

 reg_def XMM0   (SOC, SOC, Op_RegF,  0, xmm0->as_VMReg());

 reg_def XMM0_H (SOC, SOC, Op_RegF,  0, xmm0->as_VMReg()->next());

 reg_def XMM1   (SOC, SOC, Op_RegF,  1, xmm1->as_VMReg());

 reg_def XMM1_H (SOC, SOC, Op_RegF,  1, xmm1->as_VMReg()->next());

 reg_def XMM2   (SOC, SOC, Op_RegF,  2, xmm2->as_VMReg());

 reg_def XMM2_H (SOC, SOC, Op_RegF,  2, xmm2->as_VMReg()->next());

 reg_def XMM3   (SOC, SOC, Op_RegF,  3, xmm3->as_VMReg());

 reg_def XMM3_H (SOC, SOC, Op_RegF,  3, xmm3->as_VMReg()->next());

 reg_def XMM4   (SOC, SOC, Op_RegF,  4, xmm4->as_VMReg());

 reg_def XMM4_H (SOC, SOC, Op_RegF,  4, xmm4->as_VMReg()->next());

 reg_def XMM5   (SOC, SOC, Op_RegF,  5, xmm5->as_VMReg());

 reg_def XMM5_H (SOC, SOC, Op_RegF,  5, xmm5->as_VMReg()->next());

 #ifdef _WIN64

 reg_def XMM6   (SOC, SOE, Op_RegF,  6, xmm6->as_VMReg());

 reg_def XMM6_H (SOC, SOE, Op_RegF,  6, xmm6->as_VMReg()->next());

 reg_def XMM7   (SOC, SOE, Op_RegF,  7, xmm7->as_VMReg());

 reg_def XMM7_H (SOC, SOE, Op_RegF,  7, xmm7->as_VMReg()->next());

 reg_def XMM8   (SOC, SOE, Op_RegF,  8, xmm8->as_VMReg());

 reg_def XMM8_H (SOC, SOE, Op_RegF,  8, xmm8->as_VMReg()->next());

 reg_def XMM9   (SOC, SOE, Op_RegF,  9, xmm9->as_VMReg());

 reg_def XMM9_H (SOC, SOE, Op_RegF,  9, xmm9->as_VMReg()->next());

 reg_def XMM10  (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg());

 reg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next());

 reg_def XMM11  (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg());

 reg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next());

 reg_def XMM12  (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg());

 reg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next());

 reg_def XMM13  (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg());

 reg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next());

 reg_def XMM14  (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg());

 reg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next());

 reg_def XMM15  (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg());

 reg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next());

 #else

 reg_def XMM6   (SOC, SOC, Op_RegF,  6, xmm6->as_VMReg());

 reg_def XMM6_H (SOC, SOC, Op_RegF,  6, xmm6->as_VMReg()->next());

 reg_def XMM7   (SOC, SOC, Op_RegF,  7, xmm7->as_VMReg());

 reg_def XMM7_H (SOC, SOC, Op_RegF,  7, xmm7->as_VMReg()->next());

 reg_def XMM8   (SOC, SOC, Op_RegF,  8, xmm8->as_VMReg());

 reg_def XMM8_H (SOC, SOC, Op_RegF,  8, xmm8->as_VMReg()->next());

 reg_def XMM9   (SOC, SOC, Op_RegF,  9, xmm9->as_VMReg());

 reg_def XMM9_H (SOC, SOC, Op_RegF,  9, xmm9->as_VMReg()->next());

 reg_def XMM10  (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg());

 reg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next());

 reg_def XMM11  (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg());

 reg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next());

 reg_def XMM12  (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg());

 reg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next());

 reg_def XMM13  (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg());

 reg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next());

 reg_def XMM14  (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg());

 reg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next());

 reg_def XMM15  (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg());

 reg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next());

 #endif // _WIN64

 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad());

 // Specify priority of register selection within phases of register

 // allocation.  Highest priority is first.  A useful heuristic is to

 // give registers a low priority when they are required by machine

 // instructions, like EAX and EDX on I486, and choose no-save registers

 // before save-on-call, & save-on-call before save-on-entry.  Registers

 // which participate in fixed calling sequences should come last.

 // Registers which are used as pairs must fall on an even boundary.

 alloc_class chunk0(R10,         R10_H,

                    R11,         R11_H,

                    R8,          R8_H,

                    R9,          R9_H,

                    R12,         R12_H,

                    RCX,         RCX_H,

                    RBX,         RBX_H,

                    RDI,         RDI_H,

                    RDX,         RDX_H,

                    RSI,         RSI_H,

                    RAX,         RAX_H,

                    RBP,         RBP_H,

                    R13,         R13_H,

                    R14,         R14_H,

                    R15,         R15_H,

                    RSP,         RSP_H);

 // XXX probably use 8-15 first on Linux

 alloc_class chunk1(XMM0,  XMM0_H,

                    XMM1,  XMM1_H,

                    XMM2,  XMM2_H,

                    XMM3,  XMM3_H,

                    XMM4,  XMM4_H,

                    XMM5,  XMM5_H,

                    XMM6,  XMM6_H,

                    XMM7,  XMM7_H,

                    XMM8,  XMM8_H,

                    XMM9,  XMM9_H,

                    XMM10, XMM10_H,

                    XMM11, XMM11_H,

                    XMM12, XMM12_H,

                    XMM13, XMM13_H,

                    XMM14, XMM14_H,

                    XMM15, XMM15_H);

 alloc_class chunk2(RFLAGS);

 //----------Architecture Description Register Classes--------------------------

 // Several register classes are automatically defined based upon information in

 // this architecture description.

 // 1) reg_class inline_cache_reg           ( /* as def'd in frame section */ )

 // 2) reg_class compiler_method_oop_reg    ( /* as def'd in frame section */ )

 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )

 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )

 //

 // Class for all pointer registers (including RSP)

 reg_class any_reg(RAX, RAX_H,

                   RDX, RDX_H,

                   RBP, RBP_H,

                   RDI, RDI_H,

                   RSI, RSI_H,

                   RCX, RCX_H,

                   RBX, RBX_H,

                   RSP, RSP_H,

                   R8,  R8_H,

                   R9,  R9_H,

                   R10, R10_H,

                   R11, R11_H,

                   R12, R12_H,

                   R13, R13_H,

                   R14, R14_H,

                   R15, R15_H);

 // Class for all pointer registers except RSP

 reg_class ptr_reg(RAX, RAX_H,

                   RDX, RDX_H,

                   RBP, RBP_H,

                   RDI, RDI_H,

                   RSI, RSI_H,

                   RCX, RCX_H,

                   RBX, RBX_H,

                   R8,  R8_H,

                   R9,  R9_H,

                   R10, R10_H,

                   R11, R11_H,

                   R13, R13_H,

                   R14, R14_H);

 // Class for all pointer registers except RAX and RSP

 reg_class ptr_no_rax_reg(RDX, RDX_H,

                          RBP, RBP_H,

                          RDI, RDI_H,

                          RSI, RSI_H,

                          RCX, RCX_H,

                          RBX, RBX_H,

                          R8,  R8_H,

                          R9,  R9_H,

                          R10, R10_H,

                          R11, R11_H,

                          R13, R13_H,

                          R14, R14_H);

 reg_class ptr_no_rbp_reg(RDX, RDX_H,

                          RAX, RAX_H,

                          RDI, RDI_H,

                          RSI, RSI_H,

                          RCX, RCX_H,

                          RBX, RBX_H,

                          R8,  R8_H,

                          R9,  R9_H,

                          R10, R10_H,

                          R11, R11_H,

                          R13, R13_H,

                          R14, R14_H);

 // Class for all pointer registers except RAX, RBX and RSP

 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,

                              RBP, RBP_H,

                              RDI, RDI_H,

                              RSI, RSI_H,

                              RCX, RCX_H,

                              R8,  R8_H,

                              R9,  R9_H,

                              R10, R10_H,

                              R11, R11_H,

                              R13, R13_H,

                              R14, R14_H);

 // Singleton class for RAX pointer register

 reg_class ptr_rax_reg(RAX, RAX_H);

 // Singleton class for RBX pointer register

 reg_class ptr_rbx_reg(RBX, RBX_H);

 // Singleton class for RSI pointer register

 reg_class ptr_rsi_reg(RSI, RSI_H);

 // Singleton class for RDI pointer register

 reg_class ptr_rdi_reg(RDI, RDI_H);

 // Singleton class for RBP pointer register

 reg_class ptr_rbp_reg(RBP, RBP_H);

 // Singleton class for stack pointer

 reg_class ptr_rsp_reg(RSP, RSP_H);

 // Singleton class for TLS pointer

 reg_class ptr_r15_reg(R15, R15_H);

 // Class for all long registers (except RSP)

 reg_class long_reg(RAX, RAX_H,

                    RDX, RDX_H,

                    RBP, RBP_H,

                    RDI, RDI_H,

                    RSI, RSI_H,

                    RCX, RCX_H,

                    RBX, RBX_H,

                    R8,  R8_H,

                    R9,  R9_H,

                    R10, R10_H,

                    R11, R11_H,

                    R13, R13_H,

                    R14, R14_H);

 // Class for all long registers except RAX, RDX (and RSP)

 reg_class long_no_rax_rdx_reg(RBP, RBP_H,

                               RDI, RDI_H,

                               RSI, RSI_H,

                               RCX, RCX_H,

                               RBX, RBX_H,

                               R8,  R8_H,

                               R9,  R9_H,

                               R10, R10_H,

                               R11, R11_H,

                               R13, R13_H,

                               R14, R14_H);

 // Class for all long registers except RCX (and RSP)

 reg_class long_no_rcx_reg(RBP, RBP_H,

                           RDI, RDI_H,

                           RSI, RSI_H,

                           RAX, RAX_H,

                           RDX, RDX_H,

                           RBX, RBX_H,

                           R8,  R8_H,

                           R9,  R9_H,

                           R10, R10_H,

                           R11, R11_H,

                           R13, R13_H,

                           R14, R14_H);

 // Class for all long registers except RAX (and RSP)

 reg_class long_no_rax_reg(RBP, RBP_H,

                           RDX, RDX_H,

                           RDI, RDI_H,

                           RSI, RSI_H,

                           RCX, RCX_H,

                           RBX, RBX_H,

                           R8,  R8_H,

                           R9,  R9_H,

                           R10, R10_H,

                           R11, R11_H,

                           R13, R13_H,

                           R14, R14_H);

 // Singleton class for RAX long register

 reg_class long_rax_reg(RAX, RAX_H);

 // Singleton class for RCX long register

 reg_class long_rcx_reg(RCX, RCX_H);

 // Singleton class for RDX long register

 reg_class long_rdx_reg(RDX, RDX_H);

 // Class for all int registers (except RSP)

 reg_class int_reg(RAX,

                   RDX,

                   RBP,

                   RDI,

                   RSI,

                   RCX,

                   RBX,

                   R8,

                   R9,

                   R10,

                   R11,

                   R13,

                   R14);

 // Class for all int registers except RCX (and RSP)

 reg_class int_no_rcx_reg(RAX,

                          RDX,

                          RBP,

                          RDI,

                          RSI,

                          RBX,

                          R8,

                          R9,

                          R10,

                          R11,

                          R13,

                          R14);

 // Class for all int registers except RAX, RDX (and RSP)

 reg_class int_no_rax_rdx_reg(RBP,

                              RDI,

                              RSI,

                              RCX,

                              RBX,

                              R8,

                              R9,

                              R10,

                              R11,

                              R13,

                              R14);

 // Singleton class for RAX int register

 reg_class int_rax_reg(RAX);

 // Singleton class for RBX int register

 reg_class int_rbx_reg(RBX);

 // Singleton class for RCX int register

 reg_class int_rcx_reg(RCX);

 // Singleton class for RCX int register

 reg_class int_rdx_reg(RDX);

 // Singleton class for RCX int register

 reg_class int_rdi_reg(RDI);

 // Singleton class for instruction pointer

 // reg_class ip_reg(RIP);

 // Singleton class for condition codes

 reg_class int_flags(RFLAGS);

 // Class for all float registers

 reg_class float_reg(XMM0,

                     XMM1,

                     XMM2,

                     XMM3,

                     XMM4,

                     XMM5,

                     XMM6,

                     XMM7,

                     XMM8,

                     XMM9,

                     XMM10,

                     XMM11,

                     XMM12,

                     XMM13,

                     XMM14,

                     XMM15);

 // Class for all double registers

 reg_class double_reg(XMM0,  XMM0_H,

                      XMM1,  XMM1_H,

                      XMM2,  XMM2_H,

                      XMM3,  XMM3_H,

                      XMM4,  XMM4_H,

                      XMM5,  XMM5_H,

                      XMM6,  XMM6_H,

                      XMM7,  XMM7_H,

                      XMM8,  XMM8_H,

                      XMM9,  XMM9_H,

                      XMM10, XMM10_H,

                      XMM11, XMM11_H,

                      XMM12, XMM12_H,

                      XMM13, XMM13_H,

                      XMM14, XMM14_H,

                      XMM15, XMM15_H);

 %}

 //----------SOURCE BLOCK-------------------------------------------------------

 // This is a block of C++ code which provides values, functions, and

 // definitions necessary in the rest of the architecture description

 source %{

 #define   RELOC_IMM64    Assembler::imm_operand

 #define   RELOC_DISP32   Assembler::disp32_operand

 #define __ _masm.

 static int preserve_SP_size() {

   return 3;  // rex.w, op, rm(reg/reg)

 }

 // !!!!! Special hack to get all types of calls to specify the byte offset

 //       from the start of the call to the point where the return address

 //       will point.

 int MachCallStaticJavaNode::ret_addr_offset()

 {

   int offset = 5; // 5 bytes from start of call to where return address points

   if (_method_handle_invoke)

     offset += preserve_SP_size();

   return offset;

 }

 int MachCallDynamicJavaNode::ret_addr_offset()

 {

   return 15; // 15 bytes from start of call to where return address points

 }

 // In os_cpu .ad file

 // int MachCallRuntimeNode::ret_addr_offset()

 // Indicate if the safepoint node needs the polling page as an input,

 // it does if the polling page is more than disp32 away.

 bool SafePointNode::needs_polling_address_input()

 {

   return Assembler::is_polling_page_far();

 }

 //

 // Compute padding required for nodes which need alignment

 //

 // The address of the call instruction needs to be 4-byte aligned to

 // ensure that it does not span a cache line so that it can be patched.

 int CallStaticJavaDirectNode::compute_padding(int current_offset) const

 {

   current_offset += 1; // skip call opcode byte

   return round_to(current_offset, alignment_required()) - current_offset;

 }

 // The address of the call instruction needs to be 4-byte aligned to

 // ensure that it does not span a cache line so that it can be patched.

 int CallStaticJavaHandleNode::compute_padding(int current_offset) const

 {

   current_offset += preserve_SP_size();   // skip mov rbp, rsp

   current_offset += 1; // skip call opcode byte

   return round_to(current_offset, alignment_required()) - current_offset;

 }

 // The address of the call instruction needs to be 4-byte aligned to

 // ensure that it does not span a cache line so that it can be patched.

 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const

 {

   current_offset += 11; // skip movq instruction + call opcode byte

   return round_to(current_offset, alignment_required()) - current_offset;

 }

 #ifndef PRODUCT

 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const

 {

   st->print("INT3");

 }

 #endif

 // EMIT_RM()

 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {

   unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);

   cbuf.insts()->emit_int8(c);

 }

 // EMIT_CC()

 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {

   unsigned char c = (unsigned char) (f1 | f2);

   cbuf.insts()->emit_int8(c);

 }

 // EMIT_OPCODE()

 void emit_opcode(CodeBuffer &cbuf, int code) {

   cbuf.insts()->emit_int8((unsigned char) code);

 }

 // EMIT_OPCODE() w/ relocation information

 void emit_opcode(CodeBuffer &cbuf,

                  int code, relocInfo::relocType reloc, int offset, int format)

 {

   cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);

   emit_opcode(cbuf, code);

 }

 // EMIT_D8()

 void emit_d8(CodeBuffer &cbuf, int d8) {

   cbuf.insts()->emit_int8((unsigned char) d8);

 }

 // EMIT_D16()

 void emit_d16(CodeBuffer &cbuf, int d16) {

   cbuf.insts()->emit_int16(d16);

 }

 // EMIT_D32()

 void emit_d32(CodeBuffer &cbuf, int d32) {

   cbuf.insts()->emit_int32(d32);

 }

 // EMIT_D64()

 void emit_d64(CodeBuffer &cbuf, int64_t d64) {

   cbuf.insts()->emit_int64(d64);

 }

 // emit 32 bit value and construct relocation entry from relocInfo::relocType

 void emit_d32_reloc(CodeBuffer& cbuf,

                     int d32,

                     relocInfo::relocType reloc,

                     int format)

 {

   assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");

   cbuf.relocate(cbuf.insts_mark(), reloc, format);

   cbuf.insts()->emit_int32(d32);

 }

 // emit 32 bit value and construct relocation entry from RelocationHolder

 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {

 #ifdef ASSERT

   if (rspec.reloc()->type() == relocInfo::oop_type &&

       d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {

     assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");

   }

 #endif

   cbuf.relocate(cbuf.insts_mark(), rspec, format);

   cbuf.insts()->emit_int32(d32);

 }

 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {

   address next_ip = cbuf.insts_end() + 4;

   emit_d32_reloc(cbuf, (int) (addr - next_ip),

                  external_word_Relocation::spec(addr),

                  RELOC_DISP32);

 }

 // emit 64 bit value and construct relocation entry from relocInfo::relocType

 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {

   cbuf.relocate(cbuf.insts_mark(), reloc, format);

   cbuf.insts()->emit_int64(d64);

 }

 // emit 64 bit value and construct relocation entry from RelocationHolder

 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {

 #ifdef ASSERT

   if (rspec.reloc()->type() == relocInfo::oop_type &&

       d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {

     assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()),

            "cannot embed scavengable oops in code");

   }

 #endif

   cbuf.relocate(cbuf.insts_mark(), rspec, format);

   cbuf.insts()->emit_int64(d64);

 }

 // Access stack slot for load or store

 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)

 {

   emit_opcode(cbuf, opcode);                  // (e.g., FILD   [RSP+src])

   if (-0x80 <= disp && disp < 0x80) {

     emit_rm(cbuf, 0x01, rm_field, RSP_enc);   // R/M byte

     emit_rm(cbuf, 0x00, RSP_enc, RSP_enc);    // SIB byte

     emit_d8(cbuf, disp);     // Displacement  // R/M byte

   } else {

     emit_rm(cbuf, 0x02, rm_field, RSP_enc);   // R/M byte

     emit_rm(cbuf, 0x00, RSP_enc, RSP_enc);    // SIB byte

     emit_d32(cbuf, disp);     // Displacement // R/M byte

   }

 }

    // rRegI ereg, memory mem) %{    // emit_reg_mem

 void encode_RegMem(CodeBuffer &cbuf,

                    int reg,

                    int base, int index, int scale, int disp, bool disp_is_oop)

 {

   assert(!disp_is_oop, "cannot have disp");

   int regenc = reg & 7;

   int baseenc = base & 7;

   int indexenc = index & 7;

   // There is no index & no scale, use form without SIB byte

   if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {

     // If no displacement, mode is 0x0; unless base is [RBP] or [R13]

     if (disp == 0 && base != RBP_enc && base != R13_enc) {

       emit_rm(cbuf, 0x0, regenc, baseenc); // *

     } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {

       // If 8-bit displacement, mode 0x1

       emit_rm(cbuf, 0x1, regenc, baseenc); // *

       emit_d8(cbuf, disp);

     } else {

       // If 32-bit displacement

       if (base == -1) { // Special flag for absolute address

         emit_rm(cbuf, 0x0, regenc, 0x5); // *

         if (disp_is_oop) {

           emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);

         } else {

           emit_d32(cbuf, disp);

         }

       } else {

         // Normal base + offset

         emit_rm(cbuf, 0x2, regenc, baseenc); // *

         if (disp_is_oop) {

           emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);

         } else {

           emit_d32(cbuf, disp);

         }

       }

     }

   } else {

     // Else, encode with the SIB byte

     // If no displacement, mode is 0x0; unless base is [RBP] or [R13]

     if (disp == 0 && base != RBP_enc && base != R13_enc) {

       // If no displacement

       emit_rm(cbuf, 0x0, regenc, 0x4); // *

       emit_rm(cbuf, scale, indexenc, baseenc);

     } else {

       if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {

         // If 8-bit displacement, mode 0x1

         emit_rm(cbuf, 0x1, regenc, 0x4); // *

         emit_rm(cbuf, scale, indexenc, baseenc);

         emit_d8(cbuf, disp);

       } else {

         // If 32-bit displacement

         if (base == 0x04 ) {

           emit_rm(cbuf, 0x2, regenc, 0x4);

           emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???

         } else {

           emit_rm(cbuf, 0x2, regenc, 0x4);

           emit_rm(cbuf, scale, indexenc, baseenc); // *

         }

         if (disp_is_oop) {

           emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);

         } else {

           emit_d32(cbuf, disp);

         }

       }

     }

   }

 }

 // This could be in MacroAssembler but it's fairly C2 specific

 void emit_cmpfp_fixup(MacroAssembler& _masm) {

   Label exit;

   __ jccb(Assembler::noParity, exit);

   __ pushf();

   //

   // comiss/ucomiss instructions set ZF,PF,CF flags and

   // zero OF,AF,SF for NaN values.

   // Fixup flags by zeroing ZF,PF so that compare of NaN

   // values returns 'less than' result (CF is set).

   // Leave the rest of flags unchanged.

   //

   //    7 6 5 4 3 2 1 0

   //   |S|Z|r|A|r|P|r|C|  (r - reserved bit)

   //    0 0 1 0 1 0 1 1   (0x2B)

   //

   __ andq(Address(rsp, 0), 0xffffff2b);

   __ popf();

   __ bind(exit);

 }

 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {

   Label done;

   __ movl(dst, -1);

   __ jcc(Assembler::parity, done);

   __ jcc(Assembler::below, done);

   __ setb(Assembler::notEqual, dst);

   __ movzbl(dst, dst);

   __ bind(done);

 }

 //=============================================================================

 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;

 int Compile::ConstantTable::calculate_table_base_offset() const {

   return 0;  // absolute addressing, no offset

 }

 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {

   // Empty encoding

 }

 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {

   return 0;

 }

 #ifndef PRODUCT

 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {

   st->print("# MachConstantBaseNode (empty encoding)");

 }

 #endif

 //=============================================================================

 #ifndef PRODUCT

 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const

 {

   Compile* C = ra_->C;

   int framesize = C->frame_slots() << LogBytesPerInt;

   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");

   // Remove wordSize for return adr already pushed

   // and another for the RBP we are going to save

   framesize -= 2*wordSize;

   bool need_nop = true;

   // Calls to C2R adapters often do not accept exceptional returns.

   // We require that their callers must bang for them.  But be

   // careful, because some VM calls (such as call site linkage) can

   // use several kilobytes of stack.  But the stack safety zone should

   // account for that.  See bugs 4446381, 4468289, 4497237.

   if (C->need_stack_bang(framesize)) {

     st->print_cr("# stack bang"); st->print("\t");

     need_nop = false;

   }

   st->print_cr("pushq   rbp"); st->print("\t");

   if (VerifyStackAtCalls) {

     // Majik cookie to verify stack depth

     st->print_cr("pushq   0xffffffffbadb100d"

                   "\t# Majik cookie for stack depth check");

     st->print("\t");

     framesize -= wordSize; // Remove 2 for cookie

     need_nop = false;

   }

   if (framesize) {

     st->print("subq    rsp, #%d\t# Create frame", framesize);

     if (framesize < 0x80 && need_nop) {

       st->print("\n\tnop\t# nop for patch_verified_entry");

     }

   }

 }

 #endif

 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const

 {

   Compile* C = ra_->C;

   // WARNING: Initial instruction MUST be 5 bytes or longer so that

   // NativeJump::patch_verified_entry will be able to patch out the entry

   // code safely. The fldcw is ok at 6 bytes, the push to verify stack

   // depth is ok at 5 bytes, the frame allocation can be either 3 or

   // 6 bytes. So if we don't do the fldcw or the push then we must

   // use the 6 byte frame allocation even if we have no frame. :-(

   // If method sets FPU control word do it now

   int framesize = C->frame_slots() << LogBytesPerInt;

   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");

   // Remove wordSize for return adr already pushed

   // and another for the RBP we are going to save

   framesize -= 2*wordSize;

   bool need_nop = true;

   // Calls to C2R adapters often do not accept exceptional returns.

   // We require that their callers must bang for them.  But be

   // careful, because some VM calls (such as call site linkage) can

   // use several kilobytes of stack.  But the stack safety zone should

   // account for that.  See bugs 4446381, 4468289, 4497237.

   if (C->need_stack_bang(framesize)) {

     MacroAssembler masm(&cbuf);

     masm.generate_stack_overflow_check(framesize);

     need_nop = false;

   }

   // We always push rbp so that on return to interpreter rbp will be

   // restored correctly and we can correct the stack.

   emit_opcode(cbuf, 0x50 | RBP_enc);

   if (VerifyStackAtCalls) {

     // Majik cookie to verify stack depth

     emit_opcode(cbuf, 0x68); // pushq (sign-extended) 0xbadb100d

     emit_d32(cbuf, 0xbadb100d);

     framesize -= wordSize; // Remove 2 for cookie

     need_nop = false;

   }

   if (framesize) {

     emit_opcode(cbuf, Assembler::REX_W);

     if (framesize < 0x80) {

       emit_opcode(cbuf, 0x83);   // sub  SP,#framesize

       emit_rm(cbuf, 0x3, 0x05, RSP_enc);

       emit_d8(cbuf, framesize);

       if (need_nop) {

         emit_opcode(cbuf, 0x90); // nop

       }

     } else {

       emit_opcode(cbuf, 0x81);   // sub  SP,#framesize

       emit_rm(cbuf, 0x3, 0x05, RSP_enc);

       emit_d32(cbuf, framesize);

     }

   }

   C->set_frame_complete(cbuf.insts_size());

 #ifdef ASSERT

   if (VerifyStackAtCalls) {

     Label L;

     MacroAssembler masm(&cbuf);

     masm.push(rax);

     masm.mov(rax, rsp);

     masm.andptr(rax, StackAlignmentInBytes-1);

     masm.cmpptr(rax, StackAlignmentInBytes-wordSize);

     masm.pop(rax);

     masm.jcc(Assembler::equal, L);

     masm.stop("Stack is not properly aligned!");

     masm.bind(L);

   }

 #endif

   if (C->has_mach_constant_base_node()) {

     // NOTE: We set the table base offset here because users might be

     // emitted before MachConstantBaseNode.

     Compile::ConstantTable& constant_table = C->constant_table();

     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());

   }

 }

 uint MachPrologNode::size(PhaseRegAlloc* ra_) const

 {

   return MachNode::size(ra_); // too many variables; just compute it

                               // the hard way

 }

 int MachPrologNode::reloc() const

 {

   return 0; // a large enough number

 }

 //=============================================================================

 #ifndef PRODUCT

 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const

 {

   Compile* C = ra_->C;

   int framesize = C->frame_slots() << LogBytesPerInt;

   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");

   // Remove word for return adr already pushed

   // and RBP

   framesize -= 2*wordSize;

   if (framesize) {

     st->print_cr("addq    rsp, %d\t# Destroy frame", framesize);

     st->print("\t");

   }

   st->print_cr("popq   rbp");

   if (do_polling() && C->is_method_compilation()) {

     st->print("\t");

     if (Assembler::is_polling_page_far()) {

       st->print_cr("movq   rscratch1, #polling_page_address\n\t"

                    "testl  rax, [rscratch1]\t"

                    "# Safepoint: poll for GC");

     } else {

       st->print_cr("testl  rax, [rip + #offset_to_poll_page]\t"

                    "# Safepoint: poll for GC");

     }

   }

 }

 #endif

 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const

 {

   Compile* C = ra_->C;

   int framesize = C->frame_slots() << LogBytesPerInt;

   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");

   // Remove word for return adr already pushed

   // and RBP

   framesize -= 2*wordSize;

   // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here

   if (framesize) {

     emit_opcode(cbuf, Assembler::REX_W);

     if (framesize < 0x80) {

       emit_opcode(cbuf, 0x83); // addq rsp, #framesize

       emit_rm(cbuf, 0x3, 0x00, RSP_enc);

       emit_d8(cbuf, framesize);

     } else {

       emit_opcode(cbuf, 0x81); // addq rsp, #framesize

       emit_rm(cbuf, 0x3, 0x00, RSP_enc);

       emit_d32(cbuf, framesize);

     }

   }

   // popq rbp

   emit_opcode(cbuf, 0x58 | RBP_enc);

   if (do_polling() && C->is_method_compilation()) {

     MacroAssembler _masm(&cbuf);

     AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);

     if (Assembler::is_polling_page_far()) {

       __ lea(rscratch1, polling_page);

       __ relocate(relocInfo::poll_return_type);

       __ testl(rax, Address(rscratch1, 0));

     } else {

       __ testl(rax, polling_page);

     }

   }

 }

 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const

 {

   return MachNode::size(ra_); // too many variables; just compute it

                               // the hard way

 }

 int MachEpilogNode::reloc() const

 {

   return 2; // a large enough number

 }

 const Pipeline* MachEpilogNode::pipeline() const

 {

   return MachNode::pipeline_class();

 }

 int MachEpilogNode::safepoint_offset() const

 {

   return 0;

 }

 //=============================================================================

 enum RC {

   rc_bad,

   rc_int,

   rc_float,

   rc_stack

 };

 static enum RC rc_class(OptoReg::Name reg)

 {

   if( !OptoReg::is_valid(reg)  ) return rc_bad;

   if (OptoReg::is_stack(reg)) return rc_stack;

   VMReg r = OptoReg::as_VMReg(reg);

   if (r->is_Register()) return rc_int;

   assert(r->is_XMMRegister(), "must be");

   return rc_float;

 }

 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,

                                        PhaseRegAlloc* ra_,

                                        bool do_size,

                                        outputStream* st) const

 {

   // Get registers to move

   OptoReg::Name src_second = ra_->get_reg_second(in(1));

   OptoReg::Name src_first = ra_->get_reg_first(in(1));

   OptoReg::Name dst_second = ra_->get_reg_second(this);

   OptoReg::Name dst_first = ra_->get_reg_first(this);

   enum RC src_second_rc = rc_class(src_second);

   enum RC src_first_rc = rc_class(src_first);

   enum RC dst_second_rc = rc_class(dst_second);

   enum RC dst_first_rc = rc_class(dst_first);

   assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),

          "must move at least 1 register" );

   if (src_first == dst_first && src_second == dst_second) {

     // Self copy, no move

     return 0;

   } else if (src_first_rc == rc_stack) {

     // mem ->

     if (dst_first_rc == rc_stack) {

       // mem -> mem

       assert(src_second != dst_first, "overlap");

       if ((src_first & 1) == 0 && src_first + 1 == src_second &&

           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {

         // 64-bit

         int src_offset = ra_->reg2offset(src_first);

         int dst_offset = ra_->reg2offset(dst_first);

         if (cbuf) {

           emit_opcode(*cbuf, 0xFF);

           encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false);

           emit_opcode(*cbuf, 0x8F);

           encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false);

 #ifndef PRODUCT

         } else if (!do_size) {

           st->print("pushq   [rsp + #%d]\t# 64-bit mem-mem spill\n\t"

                      "popq    [rsp + #%d]",

                      src_offset,

                      dst_offset);

 #endif

         }

         return

           3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) +

           3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4));

       } else {

         // 32-bit

         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");

         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");

         // No pushl/popl, so:

         int src_offset = ra_->reg2offset(src_first);

         int dst_offset = ra_->reg2offset(dst_first);

         if (cbuf) {

           emit_opcode(*cbuf, Assembler::REX_W);

           emit_opcode(*cbuf, 0x89);

           emit_opcode(*cbuf, 0x44);

           emit_opcode(*cbuf, 0x24);

           emit_opcode(*cbuf, 0xF8);

           emit_opcode(*cbuf, 0x8B);

           encode_RegMem(*cbuf,

                         RAX_enc,

                         RSP_enc, 0x4, 0, src_offset,

                         false);

           emit_opcode(*cbuf, 0x89);

           encode_RegMem(*cbuf,

                         RAX_enc,

                         RSP_enc, 0x4, 0, dst_offset,

                         false);

           emit_opcode(*cbuf, Assembler::REX_W);

           emit_opcode(*cbuf, 0x8B);

           emit_opcode(*cbuf, 0x44);

           emit_opcode(*cbuf, 0x24);

           emit_opcode(*cbuf, 0xF8);

 #ifndef PRODUCT

         } else if (!do_size) {

           st->print("movq    [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"

                      "movl    rax, [rsp + #%d]\n\t"

                      "movl    [rsp + #%d], rax\n\t"

                      "movq    rax, [rsp - #8]",

                      src_offset,

                      dst_offset);

 #endif

         }

         return

           5 + // movq

           3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl

           3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl

           5; // movq

       }

     } else if (dst_first_rc == rc_int) {

       // mem -> gpr

       if ((src_first & 1) == 0 && src_first + 1 == src_second &&

           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {

         // 64-bit

         int offset = ra_->reg2offset(src_first);

         if (cbuf) {

           if (Matcher::_regEncode[dst_first] < 8) {

             emit_opcode(*cbuf, Assembler::REX_W);

           } else {

             emit_opcode(*cbuf, Assembler::REX_WR);

           }

           emit_opcode(*cbuf, 0x8B);

           encode_RegMem(*cbuf,

                         Matcher::_regEncode[dst_first],

                         RSP_enc, 0x4, 0, offset,

                         false);

 #ifndef PRODUCT

         } else if (!do_size) {

           st->print("movq    %s, [rsp + #%d]\t# spill",

                      Matcher::regName[dst_first],

                      offset);

 #endif

         }

         return

           ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX

       } else {

         // 32-bit

         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");

         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");

         int offset = ra_->reg2offset(src_first);

         if (cbuf) {

           if (Matcher::_regEncode[dst_first] >= 8) {

             emit_opcode(*cbuf, Assembler::REX_R);

           }

           emit_opcode(*cbuf, 0x8B);

           encode_RegMem(*cbuf,

                         Matcher::_regEncode[dst_first],

                         RSP_enc, 0x4, 0, offset,

                         false);

 #ifndef PRODUCT

         } else if (!do_size) {

           st->print("movl    %s, [rsp + #%d]\t# spill",

                      Matcher::regName[dst_first],

                      offset);

 #endif

         }

         return

           ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +

           ((Matcher::_regEncode[dst_first] < 8)

            ? 3

            : 4); // REX

       }

     } else if (dst_first_rc == rc_float) {

       // mem-> xmm

       if ((src_first & 1) == 0 && src_first + 1 == src_second &&

           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {

         // 64-bit

         int offset = ra_->reg2offset(src_first);

         if (cbuf) {

           MacroAssembler _masm(cbuf);

           __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));

 #ifndef PRODUCT

         } else if (!do_size) {

           st->print("%s  %s, [rsp + #%d]\t# spill",

                      UseXmmLoadAndClearUpper ? "movsd " : "movlpd",

                      Matcher::regName[dst_first],

                      offset);

 #endif

         }

         return

           ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +

           ((Matcher::_regEncode[dst_first] >= 8)

            ? 6

            : (5 + ((UseAVX>0)?1:0))); // REX

       } else {

         // 32-bit

         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");

         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");

         int offset = ra_->reg2offset(src_first);

         if (cbuf) {

           MacroAssembler _masm(cbuf);

           __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));

 #ifndef PRODUCT

         } else if (!do_size) {

           st->print("movss   %s, [rsp + #%d]\t# spill",

                      Matcher::regName[dst_first],

                      offset);

 #endif

         }

         return

           ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +

           ((Matcher::_regEncode[dst_first] >= 8)

            ? 6

            : (5 + ((UseAVX>0)?1:0))); // REX

       }

     }

   } else if (src_first_rc == rc_int) {

     // gpr ->

     if (dst_first_rc == rc_stack) {

       // gpr -> mem

       if ((src_first & 1) == 0 && src_first + 1 == src_second &&

           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {

         // 64-bit

         int offset = ra_->reg2offset(dst_first);

         if (cbuf) {

           if (Matcher::_regEncode[src_first] < 8) {

             emit_opcode(*cbuf, Assembler::REX_W);

           } else {

             emit_opcode(*cbuf, Assembler::REX_WR);

           }

           emit_opcode(*cbuf, 0x89);

           encode_RegMem(*cbuf,

                         Matcher::_regEncode[src_first],

                         RSP_enc, 0x4, 0, offset,

                         false);

 #ifndef PRODUCT

         } else if (!do_size) {

           st->print("movq    [rsp + #%d], %s\t# spill",

                      offset,

                      Matcher::regName[src_first]);

 #endif

         }

         return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX

       } else {

         // 32-bit

         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");

         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");

         int offset = ra_->reg2offset(dst_first);

         if (cbuf) {

           if (Matcher::_regEncode[src_first] >= 8) {

             emit_opcode(*cbuf, Assembler::REX_R);

           }

           emit_opcode(*cbuf, 0x89);

           encode_RegMem(*cbuf,

                         Matcher::_regEncode[src_first],

                         RSP_enc, 0x4, 0, offset,

                         false);

 #ifndef PRODUCT

         } else if (!do_size) {

           st->print("movl    [rsp + #%d], %s\t# spill",

                      offset,

                      Matcher::regName[src_first]);

 #endif

         }

         return

           ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +

           ((Matcher::_regEncode[src_first] < 8)

            ? 3

            : 4); // REX

       }

     } else if (dst_first_rc == rc_int) {

       // gpr -> gpr

       if ((src_first & 1) == 0 && src_first + 1 == src_second &&

           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {

         // 64-bit

         if (cbuf) {

           if (Matcher::_regEncode[dst_first] < 8) {

             if (Matcher::_regEncode[src_first] < 8) {

               emit_opcode(*cbuf, Assembler::REX_W);

             } else {

               emit_opcode(*cbuf, Assembler::REX_WB);

             }

           } else {

             if (Matcher::_regEncode[src_first] < 8) {

               emit_opcode(*cbuf, Assembler::REX_WR);

             } else {

               emit_opcode(*cbuf, Assembler::REX_WRB);

             }

           }

           emit_opcode(*cbuf, 0x8B);

           emit_rm(*cbuf, 0x3,

                   Matcher::_regEncode[dst_first] & 7,

                   Matcher::_regEncode[src_first] & 7);

 #ifndef PRODUCT

         } else if (!do_size) {

           st->print("movq    %s, %s\t# spill",

                      Matcher::regName[dst_first],

                      Matcher::regName[src_first]);

 #endif

         }

         return 3; // REX

       } else {

         // 32-bit

         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");

         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");

         if (cbuf) {

           if (Matcher::_regEncode[dst_first] < 8) {

             if (Matcher::_regEncode[src_first] >= 8) {

               emit_opcode(*cbuf, Assembler::REX_B);

             }

           } else {

             if (Matcher::_regEncode[src_first] < 8) {

               emit_opcode(*cbuf, Assembler::REX_R);

             } else {

               emit_opcode(*cbuf, Assembler::REX_RB);

             }

           }

           emit_opcode(*cbuf, 0x8B);

           emit_rm(*cbuf, 0x3,

                   Matcher::_regEncode[dst_first] & 7,

                   Matcher::_regEncode[src_first] & 7);

 #ifndef PRODUCT

         } else if (!do_size) {

           st->print("movl    %s, %s\t# spill",

                      Matcher::regName[dst_first],

                      Matcher::regName[src_first]);

 #endif

         }

         return

           (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)

           ? 2

           : 3; // REX

       }

     } else if (dst_first_rc == rc_float) {

       // gpr -> xmm

       if ((src_first & 1) == 0 && src_first + 1 == src_second &&

           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {

         // 64-bit

         if (cbuf) {

           MacroAssembler _masm(cbuf);

           __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));

 #ifndef PRODUCT

         } else if (!do_size) {

           st->print("movdq   %s, %s\t# spill",

                      Matcher::regName[dst_first],

                      Matcher::regName[src_first]);

 #endif

         }

         return 5; // REX

       } else {

         // 32-bit

         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");

         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");

         if (cbuf) {

           MacroAssembler _masm(cbuf);

           __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));

 #ifndef PRODUCT

         } else if (!do_size) {

           st->print("movdl   %s, %s\t# spill",

                      Matcher::regName[dst_first],

                      Matcher::regName[src_first]);

 #endif

         }

         return

           (Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8)

           ? 5

           : (4 + ((UseAVX>0)?1:0)); // REX

       }

     }

   } else if (src_first_rc == rc_float) {

     // xmm ->

     if (dst_first_rc == rc_stack) {

       // xmm -> mem

       if ((src_first & 1) == 0 && src_first + 1 == src_second &&

           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {

         // 64-bit

         int offset = ra_->reg2offset(dst_first);

         if (cbuf) {

           MacroAssembler _masm(cbuf);

           __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));

 #ifndef PRODUCT

         } else if (!do_size) {

           st->print("movsd   [rsp + #%d], %s\t# spill",

                      offset,

                      Matcher::regName[src_first]);

 #endif

         }

         return

           ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +

           ((Matcher::_regEncode[src_first] >= 8)

            ? 6

            : (5 + ((UseAVX>0)?1:0))); // REX

       } else {

         // 32-bit

         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");

         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");

         int offset = ra_->reg2offset(dst_first);

         if (cbuf) {

           MacroAssembler _masm(cbuf);

           __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));

 #ifndef PRODUCT

         } else if (!do_size) {

           st->print("movss   [rsp + #%d], %s\t# spill",

                      offset,

                      Matcher::regName[src_first]);

 #endif

         }

         return

           ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +

           ((Matcher::_regEncode[src_first] >=8)

            ? 6

            : (5 + ((UseAVX>0)?1:0))); // REX

       }

     } else if (dst_first_rc == rc_int) {

       // xmm -> gpr

       if ((src_first & 1) == 0 && src_first + 1 == src_second &&

           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {

         // 64-bit

         if (cbuf) {

           MacroAssembler _masm(cbuf);

           __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));

 #ifndef PRODUCT

         } else if (!do_size) {

           st->print("movdq   %s, %s\t# spill",

                      Matcher::regName[dst_first],

                      Matcher::regName[src_first]);

 #endif

         }

         return 5; // REX

       } else {

         // 32-bit

         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");

         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");

         if (cbuf) {

           MacroAssembler _masm(cbuf);

           __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));

 #ifndef PRODUCT

         } else if (!do_size) {

           st->print("movdl   %s, %s\t# spill",

                      Matcher::regName[dst_first],

                      Matcher::regName[src_first]);

 #endif

         }

         return

           (Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8)

           ? 5

           : (4 + ((UseAVX>0)?1:0)); // REX

       }

     } else if (dst_first_rc == rc_float) {

       // xmm -> xmm

       if ((src_first & 1) == 0 && src_first + 1 == src_second &&

           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {

         // 64-bit

         if (cbuf) {

           MacroAssembler _masm(cbuf);

           __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));

 #ifndef PRODUCT

         } else if (!do_size) {

           st->print("%s  %s, %s\t# spill",

                      UseXmmRegToRegMoveAll ? "movapd" : "movsd ",

                      Matcher::regName[dst_first],

                      Matcher::regName[src_first]);

 #endif

         }

         return

           (Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8)

           ? 5

           : (4 + ((UseAVX>0)?1:0)); // REX

       } else {

         // 32-bit

         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");

         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");

         if (cbuf) {

           MacroAssembler _masm(cbuf);

           __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));

 #ifndef PRODUCT

         } else if (!do_size) {

           st->print("%s  %s, %s\t# spill",

                      UseXmmRegToRegMoveAll ? "movaps" : "movss ",

                      Matcher::regName[dst_first],

                      Matcher::regName[src_first]);

 #endif

         }

         return ((UseAVX>0) ? 5:

           ((Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8)

            ? (UseXmmRegToRegMoveAll ? 4 : 5)

            : (UseXmmRegToRegMoveAll ? 3 : 4))); // REX

       }

     }

   }

   assert(0," foo ");

   Unimplemented();

   return 0;

 }

 #ifndef PRODUCT

 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const

 {

   implementation(NULL, ra_, false, st);

 }

 #endif

 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const

 {

   implementation(&cbuf, ra_, false, NULL);

 }

 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const

 {

   return implementation(NULL, ra_, true, NULL);

 }

 //=============================================================================

 #ifndef PRODUCT

 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const

 {

   st->print("nop \t# %d bytes pad for loops and calls", _count);

 }

 #endif

 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const

 {

   MacroAssembler _masm(&cbuf);

   __ nop(_count);

 }

 uint MachNopNode::size(PhaseRegAlloc*) const

 {

   return _count;

 }

 //=============================================================================

 #ifndef PRODUCT

 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const

 {

   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());

   int reg = ra_->get_reg_first(this);

   st->print("leaq    %s, [rsp + #%d]\t# box lock",

             Matcher::regName[reg], offset);

 }

 #endif

 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const

 {

   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());

   int reg = ra_->get_encode(this);

   if (offset >= 0x80) {

     emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);

     emit_opcode(cbuf, 0x8D); // LEA  reg,[SP+offset]

     emit_rm(cbuf, 0x2, reg & 7, 0x04);

     emit_rm(cbuf, 0x0, 0x04, RSP_enc);

     emit_d32(cbuf, offset);

   } else {

     emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);

     emit_opcode(cbuf, 0x8D); // LEA  reg,[SP+offset]

     emit_rm(cbuf, 0x1, reg & 7, 0x04);

     emit_rm(cbuf, 0x0, 0x04, RSP_enc);

     emit_d8(cbuf, offset);

   }

 }

 uint BoxLockNode::size(PhaseRegAlloc *ra_) const

 {

   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());

   return (offset < 0x80) ? 5 : 8; // REX

 }

 //=============================================================================

 // emit call stub, compiled java to interpreter

 void emit_java_to_interp(CodeBuffer& cbuf)

 {

   // Stub is fixed up when the corresponding call is converted from

   // calling compiled code to calling interpreted code.

   // movq rbx, 0

   // jmp -5 # to self

   address mark = cbuf.insts_mark();  // get mark within main instrs section

   // Note that the code buffer's insts_mark is always relative to insts.

   // That's why we must use the macroassembler to generate a stub.

   MacroAssembler _masm(&cbuf);

   address base =

   __ start_a_stub(Compile::MAX_stubs_size);

   if (base == NULL)  return;  // CodeBuffer::expand failed

   // static stub relocation stores the instruction address of the call

   __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64);

   // static stub relocation also tags the methodOop in the code-stream.

   __ movoop(rbx, (jobject) NULL);  // method is zapped till fixup time

   // This is recognized as unresolved by relocs/nativeinst/ic code

   __ jump(RuntimeAddress(__ pc()));

   // Update current stubs pointer and restore insts_end.

   __ end_a_stub();

 }

 // size of call stub, compiled java to interpretor

 uint size_java_to_interp()

 {

   return 15;  // movq (1+1+8); jmp (1+4)

 }

 // relocation entries for call stub, compiled java to interpretor

 uint reloc_java_to_interp()

 {

   return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call

 }

 //=============================================================================

 #ifndef PRODUCT

 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const

 {

   if (UseCompressedOops) {

     st->print_cr("movl    rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");

     if (Universe::narrow_oop_shift() != 0) {

       st->print_cr("\tdecode_heap_oop_not_null rscratch1, rscratch1");

     }

     st->print_cr("\tcmpq    rax, rscratch1\t # Inline cache check");

   } else {

     st->print_cr("\tcmpq    rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"

                  "# Inline cache check");

   }

   st->print_cr("\tjne     SharedRuntime::_ic_miss_stub");

   st->print_cr("\tnop\t# nops to align entry point");

 }

 #endif

 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const

 {

   MacroAssembler masm(&cbuf);

   uint insts_size = cbuf.insts_size();

   if (UseCompressedOops) {

     masm.load_klass(rscratch1, j_rarg0);

     masm.cmpptr(rax, rscratch1);

   } else {

     masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));

   }

   masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));

   /* WARNING these NOPs are critical so that verified entry point is properly

      4 bytes aligned for patching by NativeJump::patch_verified_entry() */

   int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);

   if (OptoBreakpoint) {

     // Leave space for int3

     nops_cnt -= 1;

   }

   nops_cnt &= 0x3; // Do not add nops if code is aligned.

   if (nops_cnt > 0)

     masm.nop(nops_cnt);

 }

 uint MachUEPNode::size(PhaseRegAlloc* ra_) const

 {

   return MachNode::size(ra_); // too many variables; just compute it

                               // the hard way

 }

 //=============================================================================

 uint size_exception_handler()

 {

   // NativeCall instruction size is the same as NativeJump.

   // Note that this value is also credited (in output.cpp) to

   // the size of the code section.

   return NativeJump::instruction_size;

 }

 // Emit exception handler code.

 int emit_exception_handler(CodeBuffer& cbuf)

 {

   // Note that the code buffer's insts_mark is always relative to insts.

   // That's why we must use the macroassembler to generate a handler.

   MacroAssembler _masm(&cbuf);

   address base =

   __ start_a_stub(size_exception_handler());

   if (base == NULL)  return 0;  // CodeBuffer::expand failed

   int offset = __ offset();

   __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));

   assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");

   __ end_a_stub();

   return offset;

 }

 uint size_deopt_handler()

 {

   // three 5 byte instructions

   return 15;

 }

 // Emit deopt handler code.

 int emit_deopt_handler(CodeBuffer& cbuf)

 {

   // Note that the code buffer's insts_mark is always relative to insts.

   // That's why we must use the macroassembler to generate a handler.

   MacroAssembler _masm(&cbuf);

   address base =

   __ start_a_stub(size_deopt_handler());

   if (base == NULL)  return 0;  // CodeBuffer::expand failed

   int offset = __ offset();

   address the_pc = (address) __ pc();

   Label next;

   // push a "the_pc" on the stack without destroying any registers

   // as they all may be live.

   // push address of "next"

   __ call(next, relocInfo::none); // reloc none is fine since it is a disp32

   __ bind(next);

   // adjust it so it matches "the_pc"

   __ subptr(Address(rsp, 0), __ offset() - offset);

   __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));

   assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");

   __ end_a_stub();

   return offset;

 }

 const bool Matcher::match_rule_supported(int opcode) {

   if (!has_match_rule(opcode))

     return false;

   return true;  // Per default match rules are supported.

 }

 int Matcher::regnum_to_fpu_offset(int regnum)

 {

   return regnum - 32; // The FP registers are in the second chunk

 }

 // This is UltraSparc specific, true just means we have fast l2f conversion

 const bool Matcher::convL2FSupported(void) {

   return true;

 }

 // Vector width in bytes

 const uint Matcher::vector_width_in_bytes(void) {

   return 8;

 }

 // Vector ideal reg

 const uint Matcher::vector_ideal_reg(void) {

   return Op_RegD;

 }

 // Is this branch offset short enough that a short branch can be used?

 //

 // NOTE: If the platform does not provide any short branch variants, then

 //       this method should return false for offset 0.

 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {

   // The passed offset is relative to address of the branch.

   // On 86 a branch displacement is calculated relative to address

   // of a next instruction.

   offset -= br_size;

   // the short version of jmpConUCF2 contains multiple branches,

   // making the reach slightly less

   if (rule == jmpConUCF2_rule)

     return (-126 <= offset && offset <= 125);

   return (-128 <= offset && offset <= 127);

 }

 const bool Matcher::isSimpleConstant64(jlong value) {

   // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.

   //return value == (int) value;  // Cf. storeImmL and immL32.

   // Probably always true, even if a temp register is required.

   return true;

 }

 // The ecx parameter to rep stosq for the ClearArray node is in words.

 const bool Matcher::init_array_count_is_in_bytes = false;

 // Threshold size for cleararray.

 const int Matcher::init_array_short_size = 8 * BytesPerLong;

 // No additional cost for CMOVL.

 const int Matcher::long_cmove_cost() { return 0; }

 // No CMOVF/CMOVD with SSE2

 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }

 // Should the Matcher clone shifts on addressing modes, expecting them

 // to be subsumed into complex addressing expressions or compute them

 // into registers?  True for Intel but false for most RISCs

 const bool Matcher::clone_shift_expressions = true;

 // Do we need to mask the count passed to shift instructions or does

 // the cpu only look at the lower 5/6 bits anyway?

 const bool Matcher::need_masked_shift_count = false;

 bool Matcher::narrow_oop_use_complex_address() {

   assert(UseCompressedOops, "only for compressed oops code");

   return (LogMinObjAlignmentInBytes <= 3);

 }

 // Is it better to copy float constants, or load them directly from

 // memory?  Intel can load a float constant from a direct address,

 // requiring no extra registers.  Most RISCs will have to materialize

 // an address into a register first, so they would do better to copy

 // the constant from stack.

 const bool Matcher::rematerialize_float_constants = true; // XXX

 // If CPU can load and store mis-aligned doubles directly then no

 // fixup is needed.  Else we split the double into 2 integer pieces

 // and move it piece-by-piece.  Only happens when passing doubles into

 // C code as the Java calling convention forces doubles to be aligned.

 const bool Matcher::misaligned_doubles_ok = true;

 // No-op on amd64

 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}

 // Advertise here if the CPU requires explicit rounding operations to

 // implement the UseStrictFP mode.

 const bool Matcher::strict_fp_requires_explicit_rounding = true;

 // Are floats conerted to double when stored to stack during deoptimization?

 // On x64 it is stored without convertion so we can use normal access.

 bool Matcher::float_in_double() { return false; }

 // Do ints take an entire long register or just half?

 const bool Matcher::int_in_long = true;

 // Return whether or not this register is ever used as an argument.

 // This function is used on startup to build the trampoline stubs in

 // generateOptoStub.  Registers not mentioned will be killed by the VM

 // call in the trampoline, and arguments in those registers not be

 // available to the callee.

 bool Matcher::can_be_java_arg(int reg)

 {

   return

     reg ==  RDI_num || reg ==  RDI_H_num ||

     reg ==  RSI_num || reg ==  RSI_H_num ||

     reg ==  RDX_num || reg ==  RDX_H_num ||

     reg ==  RCX_num || reg ==  RCX_H_num ||

     reg ==   R8_num || reg ==   R8_H_num ||

     reg ==   R9_num || reg ==   R9_H_num ||

     reg ==  R12_num || reg ==  R12_H_num ||

     reg == XMM0_num || reg == XMM0_H_num ||

     reg == XMM1_num || reg == XMM1_H_num ||

     reg == XMM2_num || reg == XMM2_H_num ||

     reg == XMM3_num || reg == XMM3_H_num ||

     reg == XMM4_num || reg == XMM4_H_num ||

     reg == XMM5_num || reg == XMM5_H_num ||

     reg == XMM6_num || reg == XMM6_H_num ||

     reg == XMM7_num || reg == XMM7_H_num;

 }

 bool Matcher::is_spillable_arg(int reg)

 {

   return can_be_java_arg(reg);

 }

 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {

   // In 64 bit mode a code which use multiply when

   // devisor is constant is faster than hardware

   // DIV instruction (it uses MulHiL).

   return false;

 }

 // Register for DIVI projection of divmodI

 RegMask Matcher::divI_proj_mask() {

   return INT_RAX_REG_mask();

 }

 // Register for MODI projection of divmodI

 RegMask Matcher::modI_proj_mask() {

   return INT_RDX_REG_mask();

 }

 // Register for DIVL projection of divmodL

 RegMask Matcher::divL_proj_mask() {

   return LONG_RAX_REG_mask();

 }

 // Register for MODL projection of divmodL

 RegMask Matcher::modL_proj_mask() {

   return LONG_RDX_REG_mask();

 }

 const RegMask Matcher::method_handle_invoke_SP_save_mask() {

   return PTR_RBP_REG_mask();

 }

 static Address build_address(int b, int i, int s, int d) {

   Register index = as_Register(i);

   Address::ScaleFactor scale = (Address::ScaleFactor)s;

   if (index == rsp) {

     index = noreg;

     scale = Address::no_scale;

   }

   Address addr(as_Register(b), index, scale, d);

   return addr;

 }

 %}

 //----------ENCODING BLOCK-----------------------------------------------------

 // This block specifies the encoding classes used by the compiler to

 // output byte streams.  Encoding classes are parameterized macros

 // used by Machine Instruction Nodes in order to generate the bit

 // encoding of the instruction.  Operands specify their base encoding

 // interface with the interface keyword.  There are currently

 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &

 // COND_INTER.  REG_INTER causes an operand to generate a function

 // which returns its register number when queried.  CONST_INTER causes

 // an operand to generate a function which returns the value of the

 // constant when queried.  MEMORY_INTER causes an operand to generate

 // four functions which return the Base Register, the Index Register,

 // the Scale Value, and the Offset Value of the operand when queried.

 // COND_INTER causes an operand to generate six functions which return

 // the encoding code (ie - encoding bits for the instruction)

 // associated with each basic boolean condition for a conditional

 // instruction.

 //

 // Instructions specify two basic values for encoding.  Again, a

 // function is available to check if the constant displacement is an

 // oop. They use the ins_encode keyword to specify their encoding

 // classes (which must be a sequence of enc_class names, and their

 // parameters, specified in the encoding block), and they use the

 // opcode keyword to specify, in order, their primary, secondary, and

 // tertiary opcode.  Only the opcode sections which a particular

 // instruction needs for encoding need to be specified.

 encode %{

   // Build emit functions for each basic byte or larger field in the

   // intel encoding scheme (opcode, rm, sib, immediate), and call them

   // from C++ code in the enc_class source block.  Emit functions will

   // live in the main source block for now.  In future, we can

   // generalize this by adding a syntax that specifies the sizes of

   // fields in an order, so that the adlc can build the emit functions

   // automagically

   // Emit primary opcode

   enc_class OpcP

   %{

     emit_opcode(cbuf, $primary);

   %}

   // Emit secondary opcode

   enc_class OpcS

   %{

     emit_opcode(cbuf, $secondary);

   %}

   // Emit tertiary opcode

   enc_class OpcT

   %{

     emit_opcode(cbuf, $tertiary);

   %}

   // Emit opcode directly

   enc_class Opcode(immI d8)

   %{

     emit_opcode(cbuf, $d8$$constant);

   %}

   // Emit size prefix

   enc_class SizePrefix

   %{

     emit_opcode(cbuf, 0x66);

   %}

   enc_class reg(rRegI reg)

   %{

     emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);

   %}

   enc_class reg_reg(rRegI dst, rRegI src)

   %{

     emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);

   %}

   enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)

   %{

     emit_opcode(cbuf, $opcode$$constant);

     emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);

   %}

   enc_class cdql_enc(no_rax_rdx_RegI div)

   %{

     // Full implementation of Java idiv and irem; checks for

     // special case as described in JVM spec., p.243 & p.271.

     //

     //         normal case                           special case

     //

     // input : rax: dividend                         min_int

     //         reg: divisor                          -1

     //

     // output: rax: quotient  (= rax idiv reg)       min_int

     //         rdx: remainder (= rax irem reg)       0

     //

     //  Code sequnce:

     //

     //    0:   3d 00 00 00 80          cmp    $0x80000000,%eax

     //    5:   75 07/08                jne    e <normal>

     //    7:   33 d2                   xor    %edx,%edx

     //  [div >= 8 -> offset + 1]

     //  [REX_B]

     //    9:   83 f9 ff                cmp    $0xffffffffffffffff,$div

     //    c:   74 03/04                je     11 <done>

     // 000000000000000e <normal>:

     //    e:   99                      cltd

     //  [div >= 8 -> offset + 1]

     //  [REX_B]

     //    f:   f7 f9                   idiv   $div

     // 0000000000000011 <done>:

     // cmp    $0x80000000,%eax

     emit_opcode(cbuf, 0x3d);

     emit_d8(cbuf, 0x00);

     emit_d8(cbuf, 0x00);

     emit_d8(cbuf, 0x00);

     emit_d8(cbuf, 0x80);

     // jne    e <normal>

     emit_opcode(cbuf, 0x75);

     emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);

     // xor    %edx,%edx

     emit_opcode(cbuf, 0x33);

     emit_d8(cbuf, 0xD2);

     // cmp    $0xffffffffffffffff,%ecx

     if ($div$$reg >= 8) {

       emit_opcode(cbuf, Assembler::REX_B);

     }

     emit_opcode(cbuf, 0x83);

     emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);

     emit_d8(cbuf, 0xFF);

     // je     11 <done>

     emit_opcode(cbuf, 0x74);

     emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);

     // <normal>

     // cltd

     emit_opcode(cbuf, 0x99);

     // idivl (note: must be emitted by the user of this rule)

     // <done>

   %}

   enc_class cdqq_enc(no_rax_rdx_RegL div)

   %{

     // Full implementation of Java ldiv and lrem; checks for

     // special case as described in JVM spec., p.243 & p.271.

     //

     //         normal case                           special case

     //

     // input : rax: dividend                         min_long

     //         reg: divisor                          -1

     //

     // output: rax: quotient  (= rax idiv reg)       min_long

     //         rdx: remainder (= rax irem reg)       0

     //

     //  Code sequnce:

     //

     //    0:   48 ba 00 00 00 00 00    mov    $0x8000000000000000,%rdx

     //    7:   00 00 80

     //    a:   48 39 d0                cmp    %rdx,%rax

     //    d:   75 08                   jne    17 <normal>

     //    f:   33 d2                   xor    %edx,%edx

     //   11:   48 83 f9 ff             cmp    $0xffffffffffffffff,$div

     //   15:   74 05                   je     1c <done>

     // 0000000000000017 <normal>:

     //   17:   48 99                   cqto

     //   19:   48 f7 f9                idiv   $div

     // 000000000000001c <done>:

     // mov    $0x8000000000000000,%rdx

     emit_opcode(cbuf, Assembler::REX_W);

     emit_opcode(cbuf, 0xBA);

     emit_d8(cbuf, 0x00);

     emit_d8(cbuf, 0x00);

     emit_d8(cbuf, 0x00);

     emit_d8(cbuf, 0x00);

     emit_d8(cbuf, 0x00);

     emit_d8(cbuf, 0x00);

     emit_d8(cbuf, 0x00);

     emit_d8(cbuf, 0x80);

     // cmp    %rdx,%rax

     emit_opcode(cbuf, Assembler::REX_W);

     emit_opcode(cbuf, 0x39);

     emit_d8(cbuf, 0xD0);

     // jne    17 <normal>

     emit_opcode(cbuf, 0x75);

     emit_d8(cbuf, 0x08);

     // xor    %edx,%edx

     emit_opcode(cbuf, 0x33);

     emit_d8(cbuf, 0xD2);

     // cmp    $0xffffffffffffffff,$div

     emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);

     emit_opcode(cbuf, 0x83);

     emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);

     emit_d8(cbuf, 0xFF);

     // je     1e <done>

     emit_opcode(cbuf, 0x74);

     emit_d8(cbuf, 0x05);

     // <normal>

     // cqto

     emit_opcode(cbuf, Assembler::REX_W);

     emit_opcode(cbuf, 0x99);

     // idivq (note: must be emitted by the user of this rule)

     // <done>

   %}

   // Opcde enc_class for 8/32 bit immediate instructions with sign-extension

   enc_class OpcSE(immI imm)

   %{

     // Emit primary opcode and set sign-extend bit

     // Check for 8-bit immediate, and set sign extend bit in opcode

     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {

       emit_opcode(cbuf, $primary | 0x02);

     } else {

       // 32-bit immediate

       emit_opcode(cbuf, $primary);

     }

   %}

   enc_class OpcSErm(rRegI dst, immI imm)

   %{

     // OpcSEr/m

     int dstenc = $dst$$reg;

     if (dstenc >= 8) {

       emit_opcode(cbuf, Assembler::REX_B);

       dstenc -= 8;

     }

     // Emit primary opcode and set sign-extend bit

     // Check for 8-bit immediate, and set sign extend bit in opcode

     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {

       emit_opcode(cbuf, $primary | 0x02);

     } else {

       // 32-bit immediate

       emit_opcode(cbuf, $primary);

     }

     // Emit r/m byte with secondary opcode, after primary opcode.

     emit_rm(cbuf, 0x3, $secondary, dstenc);

   %}

   enc_class OpcSErm_wide(rRegL dst, immI imm)

   %{

     // OpcSEr/m

     int dstenc = $dst$$reg;

     if (dstenc < 8) {

       emit_opcode(cbuf, Assembler::REX_W);

     } else {

       emit_opcode(cbuf, Assembler::REX_WB);

       dstenc -= 8;

     }

     // Emit primary opcode and set sign-extend bit

     // Check for 8-bit immediate, and set sign extend bit in opcode

     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {

       emit_opcode(cbuf, $primary | 0x02);

     } else {

       // 32-bit immediate

       emit_opcode(cbuf, $primary);

     }

     // Emit r/m byte with secondary opcode, after primary opcode.

     emit_rm(cbuf, 0x3, $secondary, dstenc);

   %}

   enc_class Con8or32(immI imm)

   %{

     // Check for 8-bit immediate, and set sign extend bit in opcode

     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {

       $$$emit8$imm$$constant;

     } else {

       // 32-bit immediate

       $$$emit32$imm$$constant;

     }

   %}

   enc_class opc2_reg(rRegI dst)

   %{

     // BSWAP

     emit_cc(cbuf, $secondary, $dst$$reg);

   %}

   enc_class opc3_reg(rRegI dst)

   %{

     // BSWAP

     emit_cc(cbuf, $tertiary, $dst$$reg);

   %}

   enc_class reg_opc(rRegI div)

   %{

     // INC, DEC, IDIV, IMOD, JMP indirect, ...

     emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);

   %}

   enc_class enc_cmov(cmpOp cop)

   %{

     // CMOV

     $$$emit8$primary;

     emit_cc(cbuf, $secondary, $cop$$cmpcode);

   %}

   enc_class enc_PartialSubtypeCheck()

   %{

     Register Rrdi = as_Register(RDI_enc); // result register

     Register Rrax = as_Register(RAX_enc); // super class

     Register Rrcx = as_Register(RCX_enc); // killed

     Register Rrsi = as_Register(RSI_enc); // sub class

     Label miss;

     const bool set_cond_codes = true;

     MacroAssembler _masm(&cbuf);

     __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,

                                      NULL, &miss,

                                      /*set_cond_codes:*/ true);

     if ($primary) {

       __ xorptr(Rrdi, Rrdi);

     }

     __ bind(miss);

   %}

   enc_class Java_To_Interpreter(method meth)

   %{

     // CALL Java_To_Interpreter

     // This is the instruction starting address for relocation info.

     cbuf.set_insts_mark();

     $$$emit8$primary;

     // CALL directly to the runtime

     emit_d32_reloc(cbuf,

                    (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),

                    runtime_call_Relocation::spec(),

                    RELOC_DISP32);

   %}

   enc_class preserve_SP %{

     debug_only(int off0 = cbuf.insts_size());

     MacroAssembler _masm(&cbuf);

     // RBP is preserved across all calls, even compiled calls.

     // Use it to preserve RSP in places where the callee might change the SP.

     __ movptr(rbp_mh_SP_save, rsp);

     debug_only(int off1 = cbuf.insts_size());

     assert(off1 - off0 == preserve_SP_size(), "correct size prediction");

   %}

   enc_class restore_SP %{

     MacroAssembler _masm(&cbuf);

     __ movptr(rsp, rbp_mh_SP_save);

   %}

   enc_class Java_Static_Call(method meth)

   %{

     // JAVA STATIC CALL

     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to

     // determine who we intended to call.

     cbuf.set_insts_mark();

     $$$emit8$primary;

     if (!_method) {

       emit_d32_reloc(cbuf,

                      (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),

                      runtime_call_Relocation::spec(),

                      RELOC_DISP32);

     } else if (_optimized_virtual) {

       emit_d32_reloc(cbuf,

                      (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),

                      opt_virtual_call_Relocation::spec(),

                      RELOC_DISP32);

     } else {

       emit_d32_reloc(cbuf,

                      (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),

                      static_call_Relocation::spec(),

                      RELOC_DISP32);

     }

     if (_method) {

       // Emit stub for static call

       emit_java_to_interp(cbuf);

     }

   %}

   enc_class Java_Dynamic_Call(method meth)

   %{

     // JAVA DYNAMIC CALL

     // !!!!!

     // Generate  "movq rax, -1", placeholder instruction to load oop-info

     // emit_call_dynamic_prologue( cbuf );

     cbuf.set_insts_mark();

     // movq rax, -1

     emit_opcode(cbuf, Assembler::REX_W);

     emit_opcode(cbuf, 0xB8 | RAX_enc);

     emit_d64_reloc(cbuf,

                    (int64_t) Universe::non_oop_word(),

                    oop_Relocation::spec_for_immediate(), RELOC_IMM64);

     address virtual_call_oop_addr = cbuf.insts_mark();

     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to determine

     // who we intended to call.

     cbuf.set_insts_mark();

     $$$emit8$primary;

     emit_d32_reloc(cbuf,

                    (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),

                    virtual_call_Relocation::spec(virtual_call_oop_addr),

                    RELOC_DISP32);

   %}

   enc_class Java_Compiled_Call(method meth)

   %{

     // JAVA COMPILED CALL

     int disp = in_bytes(methodOopDesc:: from_compiled_offset());

     // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!

     // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");

     // callq *disp(%rax)

     cbuf.set_insts_mark();

     $$$emit8$primary;

     if (disp < 0x80) {

       emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte

       emit_d8(cbuf, disp); // Displacement

     } else {

       emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte

       emit_d32(cbuf, disp); // Displacement

     }

   %}

   enc_class reg_opc_imm(rRegI dst, immI8 shift)

   %{

     // SAL, SAR, SHR

     int dstenc = $dst$$reg;

     if (dstenc >= 8) {

       emit_opcode(cbuf, Assembler::REX_B);

       dstenc -= 8;

     }

     $$$emit8$primary;

     emit_rm(cbuf, 0x3, $secondary, dstenc);

     $$$emit8$shift$$constant;

   %}

   enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)

   %{

     // SAL, SAR, SHR

     int dstenc = $dst$$reg;

     if (dstenc < 8) {

       emit_opcode(cbuf, Assembler::REX_W);

     } else {

       emit_opcode(cbuf, Assembler::REX_WB);

       dstenc -= 8;

     }

     $$$emit8$primary;

     emit_rm(cbuf, 0x3, $secondary, dstenc);

     $$$emit8$shift$$constant;

   %}

   enc_class load_immI(rRegI dst, immI src)

   %{

     int dstenc = $dst$$reg;

     if (dstenc >= 8) {

       emit_opcode(cbuf, Assembler::REX_B);

       dstenc -= 8;

     }

     emit_opcode(cbuf, 0xB8 | dstenc);

     $$$emit32$src$$constant;

   %}

   enc_class load_immL(rRegL dst, immL src)

   %{

     int dstenc = $dst$$reg;

     if (dstenc < 8) {

       emit_opcode(cbuf, Assembler::REX_W);

     } else {

       emit_opcode(cbuf, Assembler::REX_WB);

       dstenc -= 8;

     }

     emit_opcode(cbuf, 0xB8 | dstenc);

     emit_d64(cbuf, $src$$constant);

   %}

   enc_class load_immUL32(rRegL dst, immUL32 src)

   %{

     // same as load_immI, but this time we care about zeroes in the high word

     int dstenc = $dst$$reg;

     if (dstenc >= 8) {

       emit_opcode(cbuf, Assembler::REX_B);

       dstenc -= 8;

     }

     emit_opcode(cbuf, 0xB8 | dstenc);

     $$$emit32$src$$constant;

   %}

   enc_class load_immL32(rRegL dst, immL32 src)

   %{

     int dstenc = $dst$$reg;

     if (dstenc < 8) {

       emit_opcode(cbuf, Assembler::REX_W);

     } else {

       emit_opcode(cbuf, Assembler::REX_WB);

       dstenc -= 8;

     }

     emit_opcode(cbuf, 0xC7);

     emit_rm(cbuf, 0x03, 0x00, dstenc);

     $$$emit32$src$$constant;

   %}

   enc_class load_immP31(rRegP dst, immP32 src)

   %{

     // same as load_immI, but this time we care about zeroes in the high word

     int dstenc = $dst$$reg;

     if (dstenc >= 8) {

       emit_opcode(cbuf, Assembler::REX_B);

       dstenc -= 8;

     }

     emit_opcode(cbuf, 0xB8 | dstenc);

     $$$emit32$src$$constant;

   %}

   enc_class load_immP(rRegP dst, immP src)

   %{

     int dstenc = $dst$$reg;

     if (dstenc < 8) {

       emit_opcode(cbuf, Assembler::REX_W);

     } else {

       emit_opcode(cbuf, Assembler::REX_WB);

       dstenc -= 8;

     }

     emit_opcode(cbuf, 0xB8 | dstenc);

     // This next line should be generated from ADLC

     if ($src->constant_is_oop()) {

       emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64);

     } else {

       emit_d64(cbuf, $src$$constant);

     }

   %}

   enc_class Con32(immI src)

   %{

     // Output immediate

     $$$emit32$src$$constant;

   %}

   enc_class Con64(immL src)

   %{

     // Output immediate

     emit_d64($src$$constant);

   %}

   enc_class Con32F_as_bits(immF src)

   %{

     // Output Float immediate bits

     jfloat jf = $src$$constant;

     jint jf_as_bits = jint_cast(jf);

     emit_d32(cbuf, jf_as_bits);

   %}

   enc_class Con16(immI src)

   %{

     // Output immediate

     $$$emit16$src$$constant;

   %}

   // How is this different from Con32??? XXX

   enc_class Con_d32(immI src)

   %{

     emit_d32(cbuf,$src$$constant);

   %}

   enc_class conmemref (rRegP t1) %{    // Con32(storeImmI)

     // Output immediate memory reference

     emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );

     emit_d32(cbuf, 0x00);

   %}

   enc_class lock_prefix()

   %{

     if (os::is_MP()) {

       emit_opcode(cbuf, 0xF0); // lock

     }

   %}

   enc_class REX_mem(memory mem)

   %{

     if ($mem$$base >= 8) {

       if ($mem$$index < 8) {

         emit_opcode(cbuf, Assembler::REX_B);

       } else {

         emit_opcode(cbuf, Assembler::REX_XB);

       }

     } else {

       if ($mem$$index >= 8) {

         emit_opcode(cbuf, Assembler::REX_X);

       }

     }

   %}

   enc_class REX_mem_wide(memory mem)

   %{

     if ($mem$$base >= 8) {

       if ($mem$$index < 8) {

         emit_opcode(cbuf, Assembler::REX_WB);

       } else {

         emit_opcode(cbuf, Assembler::REX_WXB);

       }

     } else {

       if ($mem$$index < 8) {

         emit_opcode(cbuf, Assembler::REX_W);

       } else {

         emit_opcode(cbuf, Assembler::REX_WX);

       }

     }

   %}

   // for byte regs

   enc_class REX_breg(rRegI reg)

   %{

     if ($reg$$reg >= 4) {

       emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);

     }

   %}

   // for byte regs

   enc_class REX_reg_breg(rRegI dst, rRegI src)

   %{

     if ($dst$$reg < 8) {

       if ($src$$reg >= 4) {

         emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);

       }

     } else {

       if ($src$$reg < 8) {

         emit_opcode(cbuf, Assembler::REX_R);

       } else {

         emit_opcode(cbuf, Assembler::REX_RB);

       }

     }

   %}

   // for byte regs

   enc_class REX_breg_mem(rRegI reg, memory mem)

   %{

     if ($reg$$reg < 8) {

       if ($mem$$base < 8) {

         if ($mem$$index >= 8) {

           emit_opcode(cbuf, Assembler::REX_X);

         } else if ($reg$$reg >= 4) {

           emit_opcode(cbuf, Assembler::REX);

         }

       } else {

         if ($mem$$index < 8) {

           emit_opcode(cbuf, Assembler::REX_B);

         } else {

           emit_opcode(cbuf, Assembler::REX_XB);

         }

       }

     } else {

       if ($mem$$base < 8) {

         if ($mem$$index < 8) {

           emit_opcode(cbuf, Assembler::REX_R);