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src/cpu/sparc/vm/vm_version_sparc.hpp@44ef77ad417c
src/cpu/sparc/vm/vm_version_sparc.hpp
Wed, 17 Jun 2015 17:48:25 -0700
- author
- ascarpino
- date
- Wed, 17 Jun 2015 17:48:25 -0700
- changeset 9788
- 44ef77ad417c
- parent 8733
- 92cb89e23f3e
- child 8856
- ac27a9c85bea
- permissions
- -rw-r--r--
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
Reviewed-by: kvn, jrose, phh
1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP
26 #define CPU_SPARC_VM_VM_VERSION_SPARC_HPP
28 #include "runtime/globals_extension.hpp"
29 #include "runtime/vm_version.hpp"
31 class VM_Version: public Abstract_VM_Version {
32 protected:
33 enum Feature_Flag {
34 v8_instructions = 0,
35 hardware_mul32 = 1,
36 hardware_div32 = 2,
37 hardware_fsmuld = 3,
38 hardware_popc = 4,
39 v9_instructions = 5,
40 vis1_instructions = 6,
41 vis2_instructions = 7,
42 sun4v_instructions = 8,
43 blk_init_instructions = 9,
44 fmaf_instructions = 10,
45 fmau_instructions = 11,
46 vis3_instructions = 12,
47 cbcond_instructions = 13,
48 sparc64_family = 14,
49 M_family = 15,
50 S_family = 16,
51 T_family = 17,
52 T1_model = 18,
53 sparc5_instructions = 19,
54 aes_instructions = 20,
55 sha1_instruction = 21,
56 sha256_instruction = 22,
57 sha512_instruction = 23
58 };
60 enum Feature_Flag_Set {
61 unknown_m = 0,
62 all_features_m = -1,
64 v8_instructions_m = 1 << v8_instructions,
65 hardware_mul32_m = 1 << hardware_mul32,
66 hardware_div32_m = 1 << hardware_div32,
67 hardware_fsmuld_m = 1 << hardware_fsmuld,
68 hardware_popc_m = 1 << hardware_popc,
69 v9_instructions_m = 1 << v9_instructions,
70 vis1_instructions_m = 1 << vis1_instructions,
71 vis2_instructions_m = 1 << vis2_instructions,
72 sun4v_m = 1 << sun4v_instructions,
73 blk_init_instructions_m = 1 << blk_init_instructions,
74 fmaf_instructions_m = 1 << fmaf_instructions,
75 fmau_instructions_m = 1 << fmau_instructions,
76 vis3_instructions_m = 1 << vis3_instructions,
77 cbcond_instructions_m = 1 << cbcond_instructions,
78 sparc64_family_m = 1 << sparc64_family,
79 M_family_m = 1 << M_family,
80 S_family_m = 1 << S_family,
81 T_family_m = 1 << T_family,
82 T1_model_m = 1 << T1_model,
83 sparc5_instructions_m = 1 << sparc5_instructions,
84 aes_instructions_m = 1 << aes_instructions,
85 sha1_instruction_m = 1 << sha1_instruction,
86 sha256_instruction_m = 1 << sha256_instruction,
87 sha512_instruction_m = 1 << sha512_instruction,
89 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m,
90 generic_v9_m = generic_v8_m | v9_instructions_m,
91 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m,
93 // Temporary until we have something more accurate
94 niagara1_unique_m = sun4v_m,
95 niagara1_m = generic_v9_m | niagara1_unique_m
96 };
98 static int _features;
99 static const char* _features_str;
101 static unsigned int _L2_data_cache_line_size;
102 static unsigned int L2_data_cache_line_size() { return _L2_data_cache_line_size; }
104 static void print_features();
105 static int determine_features();
106 static int platform_features(int features);
108 // Returns true if the platform is in the niagara line (T series)
109 static bool is_M_family(int features) { return (features & M_family_m) != 0; }
110 static bool is_S_family(int features) { return (features & S_family_m) != 0; }
111 static bool is_T_family(int features) { return (features & T_family_m) != 0; }
112 static bool is_niagara() { return is_T_family(_features); }
113 #ifdef ASSERT
114 static bool is_niagara(int features) {
115 // 'sun4v_m' may be defined on both Sun/Oracle Sparc CPUs as well as
116 // on Fujitsu Sparc64 CPUs, but only Sun/Oracle Sparcs can be 'niagaras'.
117 return (features & sun4v_m) != 0 && (features & sparc64_family_m) == 0;
118 }
119 #endif
121 // Returns true if it is niagara1 (T1).
122 static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); }
124 static int maximum_niagara1_processor_count() { return 32; }
125 static int parse_features(const char* implementation);
126 public:
127 // Initialization
128 static void initialize();
130 static void init_before_ergo() { _features = determine_features(); }
132 // Instruction support
133 static bool has_v8() { return (_features & v8_instructions_m) != 0; }
134 static bool has_v9() { return (_features & v9_instructions_m) != 0; }
135 static bool has_hardware_mul32() { return (_features & hardware_mul32_m) != 0; }
136 static bool has_hardware_div32() { return (_features & hardware_div32_m) != 0; }
137 static bool has_hardware_fsmuld() { return (_features & hardware_fsmuld_m) != 0; }
138 static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; }
139 static bool has_vis1() { return (_features & vis1_instructions_m) != 0; }
140 static bool has_vis2() { return (_features & vis2_instructions_m) != 0; }
141 static bool has_vis3() { return (_features & vis3_instructions_m) != 0; }
142 static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; }
143 static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; }
144 static bool has_sparc5_instr() { return (_features & sparc5_instructions_m) != 0; }
145 static bool has_aes() { return (_features & aes_instructions_m) != 0; }
146 static bool has_sha1() { return (_features & sha1_instruction_m) != 0; }
147 static bool has_sha256() { return (_features & sha256_instruction_m) != 0; }
148 static bool has_sha512() { return (_features & sha512_instruction_m) != 0; }
150 static bool supports_compare_and_exchange()
151 { return has_v9(); }
153 // Returns true if the platform is in the niagara line (T series)
154 // and newer than the niagara1.
155 static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); }
157 static bool is_M_series() { return is_M_family(_features); }
158 static bool is_S_series() { return is_S_family(_features); }
159 static bool is_T4() { return is_T_family(_features) && has_cbcond(); }
160 static bool is_T7() { return is_T_family(_features) && has_sparc5_instr(); }
162 // Fujitsu SPARC64
163 static bool is_sparc64() { return (_features & sparc64_family_m) != 0; }
165 static bool is_sun4v() { return (_features & sun4v_m) != 0; }
166 static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); }
168 static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); }
169 static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); }
171 // T4 and newer Sparc have fast RDPC instruction.
172 static bool has_fast_rdpc() { return is_T4(); }
174 // On T4 and newer Sparc BIS to the beginning of cache line always zeros it.
175 static bool has_block_zeroing() { return has_blk_init() && is_T4(); }
177 static const char* cpu_features() { return _features_str; }
179 // default prefetch block size on sparc
180 static intx prefetch_data_size() { return L2_data_cache_line_size(); }
182 // Prefetch
183 static intx prefetch_copy_interval_in_bytes() {
184 intx interval = PrefetchCopyIntervalInBytes;
185 return interval >= 0 ? interval : (has_v9() ? 512 : 0);
186 }
187 static intx prefetch_scan_interval_in_bytes() {
188 intx interval = PrefetchScanIntervalInBytes;
189 return interval >= 0 ? interval : (has_v9() ? 512 : 0);
190 }
191 static intx prefetch_fields_ahead() {
192 intx count = PrefetchFieldsAhead;
193 return count >= 0 ? count : (is_ultra3() ? 1 : 0);
194 }
196 static intx allocate_prefetch_distance() {
197 // This method should be called before allocate_prefetch_style().
198 intx count = AllocatePrefetchDistance;
199 if (count < 0) { // default is not defined ?
200 count = 512;
201 }
202 return count;
203 }
204 static intx allocate_prefetch_style() {
205 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
206 // Return 0 if AllocatePrefetchDistance was not defined.
207 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
208 }
210 // Assembler testing
211 static void allow_all();
212 static void revert();
214 // Override the Abstract_VM_Version implementation.
215 static uint page_size_count() { return is_sun4v() ? 4 : 2; }
217 // Calculates the number of parallel threads
218 static unsigned int calc_parallel_worker_threads();
219 };
221 #endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP
