src/cpu/sparc/vm/assembler_sparc.hpp

Thu, 07 Oct 2010 15:12:57 -0400

author
bobv
date
Thu, 07 Oct 2010 15:12:57 -0400
changeset 2223
3dc12ef8735e
parent 2035
a64438a2b7e8
child 2201
d55217dc206f
permissions
-rw-r--r--

6989297: Integrate additional portability improvements
Reviewed-by: vladidan, dholmes

     1 /*
     2  * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     4  *
     5  * This code is free software; you can redistribute it and/or modify it
     6  * under the terms of the GNU General Public License version 2 only, as
     7  * published by the Free Software Foundation.
     8  *
     9  * This code is distributed in the hope that it will be useful, but WITHOUT
    10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    12  * version 2 for more details (a copy is included in the LICENSE file that
    13  * accompanied this code).
    14  *
    15  * You should have received a copy of the GNU General Public License version
    16  * 2 along with this work; if not, write to the Free Software Foundation,
    17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
    18  *
    19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
    20  * or visit www.oracle.com if you need additional information or have any
    21  * questions.
    22  *
    23  */
    25 class BiasedLockingCounters;
    27 // <sys/trap.h> promises that the system will not use traps 16-31
    28 #define ST_RESERVED_FOR_USER_0 0x10
    30 /* Written: David Ungar 4/19/97 */
    32 // Contains all the definitions needed for sparc assembly code generation.
    34 // Register aliases for parts of the system:
    36 // 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe
    37 // across context switches in V8+ ABI.  Of course, there are no 64 bit regs
    38 // in V8 ABI. All 64 bits are preserved in V9 ABI for all registers.
    40 // g2-g4 are scratch registers called "application globals".  Their
    41 // meaning is reserved to the "compilation system"--which means us!
    42 // They are are not supposed to be touched by ordinary C code, although
    43 // highly-optimized C code might steal them for temps.  They are safe
    44 // across thread switches, and the ABI requires that they be safe
    45 // across function calls.
    46 //
    47 // g1 and g3 are touched by more modules.  V8 allows g1 to be clobbered
    48 // across func calls, and V8+ also allows g5 to be clobbered across
    49 // func calls.  Also, g1 and g5 can get touched while doing shared
    50 // library loading.
    51 //
    52 // We must not touch g7 (it is the thread-self register) and g6 is
    53 // reserved for certain tools.  g0, of course, is always zero.
    54 //
    55 // (Sources:  SunSoft Compilers Group, thread library engineers.)
    57 // %%%% The interpreter should be revisited to reduce global scratch regs.
    59 // This global always holds the current JavaThread pointer:
    61 REGISTER_DECLARATION(Register, G2_thread , G2);
    62 REGISTER_DECLARATION(Register, G6_heapbase , G6);
    64 // The following globals are part of the Java calling convention:
    66 REGISTER_DECLARATION(Register, G5_method             , G5);
    67 REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method);
    68 REGISTER_DECLARATION(Register, G5_inline_cache_reg   , G5_method);
    70 // The following globals are used for the new C1 & interpreter calling convention:
    71 REGISTER_DECLARATION(Register, Gargs        , G4); // pointing to the last argument
    73 // This local is used to preserve G2_thread in the interpreter and in stubs:
    74 REGISTER_DECLARATION(Register, L7_thread_cache , L7);
    76 // These globals are used as scratch registers in the interpreter:
    78 REGISTER_DECLARATION(Register, Gframe_size   , G1); // SAME REG as G1_scratch
    79 REGISTER_DECLARATION(Register, G1_scratch    , G1); // also SAME
    80 REGISTER_DECLARATION(Register, G3_scratch    , G3);
    81 REGISTER_DECLARATION(Register, G4_scratch    , G4);
    83 // These globals are used as short-lived scratch registers in the compiler:
    85 REGISTER_DECLARATION(Register, Gtemp  , G5);
    87 // JSR 292 fixed register usages:
    88 REGISTER_DECLARATION(Register, G5_method_type        , G5);
    89 REGISTER_DECLARATION(Register, G3_method_handle      , G3);
    90 REGISTER_DECLARATION(Register, L7_mh_SP_save         , L7);
    92 // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass,
    93 // because a single patchable "set" instruction (NativeMovConstReg,
    94 // or NativeMovConstPatching for compiler1) instruction
    95 // serves to set up either quantity, depending on whether the compiled
    96 // call site is an inline cache or is megamorphic.  See the function
    97 // CompiledIC::set_to_megamorphic.
    98 //
    99 // If a inline cache targets an interpreted method, then the
   100 // G5 register will be used twice during the call.  First,
   101 // the call site will be patched to load a compiledICHolder
   102 // into G5. (This is an ordered pair of ic_klass, method.)
   103 // The c2i adapter will first check the ic_klass, then load
   104 // G5_method with the method part of the pair just before
   105 // jumping into the interpreter.
   106 //
   107 // Note that G5_method is only the method-self for the interpreter,
   108 // and is logically unrelated to G5_megamorphic_method.
   109 //
   110 // Invariants on G2_thread (the JavaThread pointer):
   111 //  - it should not be used for any other purpose anywhere
   112 //  - it must be re-initialized by StubRoutines::call_stub()
   113 //  - it must be preserved around every use of call_VM
   115 // We can consider using g2/g3/g4 to cache more values than the
   116 // JavaThread, such as the card-marking base or perhaps pointers into
   117 // Eden.  It's something of a waste to use them as scratch temporaries,
   118 // since they are not supposed to be volatile.  (Of course, if we find
   119 // that Java doesn't benefit from application globals, then we can just
   120 // use them as ordinary temporaries.)
   121 //
   122 // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,
   123 // it makes sense to use them routinely for procedure linkage,
   124 // whenever the On registers are not applicable.  Examples:  G5_method,
   125 // G5_inline_cache_klass, and a double handful of miscellaneous compiler
   126 // stubs.  This means that compiler stubs, etc., should be kept to a
   127 // maximum of two or three G-register arguments.
   130 // stub frames
   132 REGISTER_DECLARATION(Register, Lentry_args      , L0); // pointer to args passed to callee (interpreter) not stub itself
   134 // Interpreter frames
   136 #ifdef CC_INTERP
   137 REGISTER_DECLARATION(Register, Lstate           , L0); // interpreter state object pointer
   138 REGISTER_DECLARATION(Register, L1_scratch       , L1); // scratch
   139 REGISTER_DECLARATION(Register, Lmirror          , L1); // mirror (for native methods only)
   140 REGISTER_DECLARATION(Register, L2_scratch       , L2);
   141 REGISTER_DECLARATION(Register, L3_scratch       , L3);
   142 REGISTER_DECLARATION(Register, L4_scratch       , L4);
   143 REGISTER_DECLARATION(Register, Lscratch         , L5); // C1 uses
   144 REGISTER_DECLARATION(Register, Lscratch2        , L6); // C1 uses
   145 REGISTER_DECLARATION(Register, L7_scratch       , L7); // constant pool cache
   146 REGISTER_DECLARATION(Register, O5_savedSP       , O5);
   147 REGISTER_DECLARATION(Register, I5_savedSP       , I5); // Saved SP before bumping for locals.  This is simply
   148                                                        // a copy SP, so in 64-bit it's a biased value.  The bias
   149                                                        // is added and removed as needed in the frame code.
   150 // Interface to signature handler
   151 REGISTER_DECLARATION(Register, Llocals          , L7); // pointer to locals for signature handler
   152 REGISTER_DECLARATION(Register, Lmethod          , L6); // methodOop when calling signature handler
   154 #else
   155 REGISTER_DECLARATION(Register, Lesp             , L0); // expression stack pointer
   156 REGISTER_DECLARATION(Register, Lbcp             , L1); // pointer to next bytecode
   157 REGISTER_DECLARATION(Register, Lmethod          , L2);
   158 REGISTER_DECLARATION(Register, Llocals          , L3);
   159 REGISTER_DECLARATION(Register, Largs            , L3); // pointer to locals for signature handler
   160                                                        // must match Llocals in asm interpreter
   161 REGISTER_DECLARATION(Register, Lmonitors        , L4);
   162 REGISTER_DECLARATION(Register, Lbyte_code       , L5);
   163 // When calling out from the interpreter we record SP so that we can remove any extra stack
   164 // space allocated during adapter transitions. This register is only live from the point
   165 // of the call until we return.
   166 REGISTER_DECLARATION(Register, Llast_SP         , L5);
   167 REGISTER_DECLARATION(Register, Lscratch         , L5);
   168 REGISTER_DECLARATION(Register, Lscratch2        , L6);
   169 REGISTER_DECLARATION(Register, LcpoolCache      , L6); // constant pool cache
   171 REGISTER_DECLARATION(Register, O5_savedSP       , O5);
   172 REGISTER_DECLARATION(Register, I5_savedSP       , I5); // Saved SP before bumping for locals.  This is simply
   173                                                        // a copy SP, so in 64-bit it's a biased value.  The bias
   174                                                        // is added and removed as needed in the frame code.
   175 REGISTER_DECLARATION(Register, IdispatchTables  , I4); // Base address of the bytecode dispatch tables
   176 REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode
   177 REGISTER_DECLARATION(Register, ImethodDataPtr   , I2); // Pointer to the current method data
   178 #endif /* CC_INTERP */
   180 // NOTE: Lscratch2 and LcpoolCache point to the same registers in
   181 //       the interpreter code. If Lscratch2 needs to be used for some
   182 //       purpose than LcpoolCache should be restore after that for
   183 //       the interpreter to work right
   184 // (These assignments must be compatible with L7_thread_cache; see above.)
   186 // Since Lbcp points into the middle of the method object,
   187 // it is temporarily converted into a "bcx" during GC.
   189 // Exception processing
   190 // These registers are passed into exception handlers.
   191 // All exception handlers require the exception object being thrown.
   192 // In addition, an nmethod's exception handler must be passed
   193 // the address of the call site within the nmethod, to allow
   194 // proper selection of the applicable catch block.
   195 // (Interpreter frames use their own bcp() for this purpose.)
   196 //
   197 // The Oissuing_pc value is not always needed.  When jumping to a
   198 // handler that is known to be interpreted, the Oissuing_pc value can be
   199 // omitted.  An actual catch block in compiled code receives (from its
   200 // nmethod's exception handler) the thrown exception in the Oexception,
   201 // but it doesn't need the Oissuing_pc.
   202 //
   203 // If an exception handler (either interpreted or compiled)
   204 // discovers there is no applicable catch block, it updates
   205 // the Oissuing_pc to the continuation PC of its own caller,
   206 // pops back to that caller's stack frame, and executes that
   207 // caller's exception handler.  Obviously, this process will
   208 // iterate until the control stack is popped back to a method
   209 // containing an applicable catch block.  A key invariant is
   210 // that the Oissuing_pc value is always a value local to
   211 // the method whose exception handler is currently executing.
   212 //
   213 // Note:  The issuing PC value is __not__ a raw return address (I7 value).
   214 // It is a "return pc", the address __following__ the call.
   215 // Raw return addresses are converted to issuing PCs by frame::pc(),
   216 // or by stubs.  Issuing PCs can be used directly with PC range tables.
   217 //
   218 REGISTER_DECLARATION(Register, Oexception  , O0); // exception being thrown
   219 REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from
   222 // These must occur after the declarations above
   223 #ifndef DONT_USE_REGISTER_DEFINES
   225 #define Gthread             AS_REGISTER(Register, Gthread)
   226 #define Gmethod             AS_REGISTER(Register, Gmethod)
   227 #define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method)
   228 #define Ginline_cache_reg   AS_REGISTER(Register, Ginline_cache_reg)
   229 #define Gargs               AS_REGISTER(Register, Gargs)
   230 #define Lthread_cache       AS_REGISTER(Register, Lthread_cache)
   231 #define Gframe_size         AS_REGISTER(Register, Gframe_size)
   232 #define Gtemp               AS_REGISTER(Register, Gtemp)
   234 #ifdef CC_INTERP
   235 #define Lstate              AS_REGISTER(Register, Lstate)
   236 #define Lesp                AS_REGISTER(Register, Lesp)
   237 #define L1_scratch          AS_REGISTER(Register, L1_scratch)
   238 #define Lmirror             AS_REGISTER(Register, Lmirror)
   239 #define L2_scratch          AS_REGISTER(Register, L2_scratch)
   240 #define L3_scratch          AS_REGISTER(Register, L3_scratch)
   241 #define L4_scratch          AS_REGISTER(Register, L4_scratch)
   242 #define Lscratch            AS_REGISTER(Register, Lscratch)
   243 #define Lscratch2           AS_REGISTER(Register, Lscratch2)
   244 #define L7_scratch          AS_REGISTER(Register, L7_scratch)
   245 #define Ostate              AS_REGISTER(Register, Ostate)
   246 #else
   247 #define Lesp                AS_REGISTER(Register, Lesp)
   248 #define Lbcp                AS_REGISTER(Register, Lbcp)
   249 #define Lmethod             AS_REGISTER(Register, Lmethod)
   250 #define Llocals             AS_REGISTER(Register, Llocals)
   251 #define Lmonitors           AS_REGISTER(Register, Lmonitors)
   252 #define Lbyte_code          AS_REGISTER(Register, Lbyte_code)
   253 #define Lscratch            AS_REGISTER(Register, Lscratch)
   254 #define Lscratch2           AS_REGISTER(Register, Lscratch2)
   255 #define LcpoolCache         AS_REGISTER(Register, LcpoolCache)
   256 #endif /* ! CC_INTERP */
   258 #define Lentry_args         AS_REGISTER(Register, Lentry_args)
   259 #define I5_savedSP          AS_REGISTER(Register, I5_savedSP)
   260 #define O5_savedSP          AS_REGISTER(Register, O5_savedSP)
   261 #define IdispatchAddress    AS_REGISTER(Register, IdispatchAddress)
   262 #define ImethodDataPtr      AS_REGISTER(Register, ImethodDataPtr)
   263 #define IdispatchTables     AS_REGISTER(Register, IdispatchTables)
   265 #define Oexception          AS_REGISTER(Register, Oexception)
   266 #define Oissuing_pc         AS_REGISTER(Register, Oissuing_pc)
   269 #endif
   271 // Address is an abstraction used to represent a memory location.
   272 //
   273 // Note: A register location is represented via a Register, not
   274 //       via an address for efficiency & simplicity reasons.
   276 class Address VALUE_OBJ_CLASS_SPEC {
   277  private:
   278   Register           _base;           // Base register.
   279   RegisterOrConstant _index_or_disp;  // Index register or constant displacement.
   280   RelocationHolder   _rspec;
   282  public:
   283   Address() : _base(noreg), _index_or_disp(noreg) {}
   285   Address(Register base, RegisterOrConstant index_or_disp)
   286     : _base(base),
   287       _index_or_disp(index_or_disp) {
   288   }
   290   Address(Register base, Register index)
   291     : _base(base),
   292       _index_or_disp(index) {
   293   }
   295   Address(Register base, int disp)
   296     : _base(base),
   297       _index_or_disp(disp) {
   298   }
   300 #ifdef ASSERT
   301   // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
   302   Address(Register base, ByteSize disp)
   303     : _base(base),
   304       _index_or_disp(in_bytes(disp)) {
   305   }
   306 #endif
   308   // accessors
   309   Register base()      const { return _base; }
   310   Register index()     const { return _index_or_disp.as_register(); }
   311   int      disp()      const { return _index_or_disp.as_constant(); }
   313   bool     has_index() const { return _index_or_disp.is_register(); }
   314   bool     has_disp()  const { return _index_or_disp.is_constant(); }
   316   const relocInfo::relocType rtype() { return _rspec.type(); }
   317   const RelocationHolder&    rspec() { return _rspec; }
   319   RelocationHolder rspec(int offset) const {
   320     return offset == 0 ? _rspec : _rspec.plus(offset);
   321   }
   323   inline bool is_simm13(int offset = 0);  // check disp+offset for overflow
   325   Address plus_disp(int plusdisp) const {     // bump disp by a small amount
   326     assert(_index_or_disp.is_constant(), "must have a displacement");
   327     Address a(base(), disp() + plusdisp);
   328     return a;
   329   }
   331   Address after_save() const {
   332     Address a = (*this);
   333     a._base = a._base->after_save();
   334     return a;
   335   }
   337   Address after_restore() const {
   338     Address a = (*this);
   339     a._base = a._base->after_restore();
   340     return a;
   341   }
   343   // Convert the raw encoding form into the form expected by the
   344   // constructor for Address.
   345   static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop);
   347   friend class Assembler;
   348 };
   351 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
   352  private:
   353   address          _address;
   354   RelocationHolder _rspec;
   356   RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
   357     switch (rtype) {
   358     case relocInfo::external_word_type:
   359       return external_word_Relocation::spec(addr);
   360     case relocInfo::internal_word_type:
   361       return internal_word_Relocation::spec(addr);
   362 #ifdef _LP64
   363     case relocInfo::opt_virtual_call_type:
   364       return opt_virtual_call_Relocation::spec();
   365     case relocInfo::static_call_type:
   366       return static_call_Relocation::spec();
   367     case relocInfo::runtime_call_type:
   368       return runtime_call_Relocation::spec();
   369 #endif
   370     case relocInfo::none:
   371       return RelocationHolder();
   372     default:
   373       ShouldNotReachHere();
   374       return RelocationHolder();
   375     }
   376   }
   378  protected:
   379   // creation
   380   AddressLiteral() : _address(NULL), _rspec(NULL) {}
   382  public:
   383   AddressLiteral(address addr, RelocationHolder const& rspec)
   384     : _address(addr),
   385       _rspec(rspec) {}
   387   // Some constructors to avoid casting at the call site.
   388   AddressLiteral(jobject obj, RelocationHolder const& rspec)
   389     : _address((address) obj),
   390       _rspec(rspec) {}
   392   AddressLiteral(intptr_t value, RelocationHolder const& rspec)
   393     : _address((address) value),
   394       _rspec(rspec) {}
   396   AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
   397     : _address((address) addr),
   398     _rspec(rspec_from_rtype(rtype, (address) addr)) {}
   400   // Some constructors to avoid casting at the call site.
   401   AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none)
   402     : _address((address) addr),
   403     _rspec(rspec_from_rtype(rtype, (address) addr)) {}
   405   AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none)
   406     : _address((address) addr),
   407       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
   409   AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none)
   410     : _address((address) addr),
   411       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
   413   AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none)
   414     : _address((address) addr),
   415       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
   417   AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none)
   418     : _address((address) addr),
   419       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
   421   AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none)
   422     : _address((address) addr),
   423       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
   425 #ifdef _LP64
   426   // 32-bit complains about a multiple declaration for int*.
   427   AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none)
   428     : _address((address) addr),
   429       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
   430 #endif
   432   AddressLiteral(oop addr, relocInfo::relocType rtype = relocInfo::none)
   433     : _address((address) addr),
   434       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
   436   AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none)
   437     : _address((address) addr),
   438       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
   440   AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none)
   441     : _address((address) addr),
   442       _rspec(rspec_from_rtype(rtype, (address) addr)) {}
   444   intptr_t value() const { return (intptr_t) _address; }
   445   int      low10() const;
   447   const relocInfo::relocType rtype() const { return _rspec.type(); }
   448   const RelocationHolder&    rspec() const { return _rspec; }
   450   RelocationHolder rspec(int offset) const {
   451     return offset == 0 ? _rspec : _rspec.plus(offset);
   452   }
   453 };
   456 inline Address RegisterImpl::address_in_saved_window() const {
   457    return (Address(SP, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS));
   458 }
   462 // Argument is an abstraction used to represent an outgoing
   463 // actual argument or an incoming formal parameter, whether
   464 // it resides in memory or in a register, in a manner consistent
   465 // with the SPARC Application Binary Interface, or ABI.  This is
   466 // often referred to as the native or C calling convention.
   468 class Argument VALUE_OBJ_CLASS_SPEC {
   469  private:
   470   int _number;
   471   bool _is_in;
   473  public:
   474 #ifdef _LP64
   475   enum {
   476     n_register_parameters = 6,          // only 6 registers may contain integer parameters
   477     n_float_register_parameters = 16    // Can have up to 16 floating registers
   478   };
   479 #else
   480   enum {
   481     n_register_parameters = 6           // only 6 registers may contain integer parameters
   482   };
   483 #endif
   485   // creation
   486   Argument(int number, bool is_in) : _number(number), _is_in(is_in) {}
   488   int  number() const  { return _number;  }
   489   bool is_in()  const  { return _is_in;   }
   490   bool is_out() const  { return !is_in(); }
   492   Argument successor() const  { return Argument(number() + 1, is_in()); }
   493   Argument as_in()     const  { return Argument(number(), true ); }
   494   Argument as_out()    const  { return Argument(number(), false); }
   496   // locating register-based arguments:
   497   bool is_register() const { return _number < n_register_parameters; }
   499 #ifdef _LP64
   500   // locating Floating Point register-based arguments:
   501   bool is_float_register() const { return _number < n_float_register_parameters; }
   503   FloatRegister as_float_register() const {
   504     assert(is_float_register(), "must be a register argument");
   505     return as_FloatRegister(( number() *2 ) + 1);
   506   }
   507   FloatRegister as_double_register() const {
   508     assert(is_float_register(), "must be a register argument");
   509     return as_FloatRegister(( number() *2 ));
   510   }
   511 #endif
   513   Register as_register() const {
   514     assert(is_register(), "must be a register argument");
   515     return is_in() ? as_iRegister(number()) : as_oRegister(number());
   516   }
   518   // locating memory-based arguments
   519   Address as_address() const {
   520     assert(!is_register(), "must be a memory argument");
   521     return address_in_frame();
   522   }
   524   // When applied to a register-based argument, give the corresponding address
   525   // into the 6-word area "into which callee may store register arguments"
   526   // (This is a different place than the corresponding register-save area location.)
   527   Address address_in_frame() const;
   529   // debugging
   530   const char* name() const;
   532   friend class Assembler;
   533 };
   536 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
   537 // level; i.e., what you write
   538 // is what you get. The Assembler is generating code into a CodeBuffer.
   540 class Assembler : public AbstractAssembler  {
   541  protected:
   543   static void print_instruction(int inst);
   544   static int  patched_branch(int dest_pos, int inst, int inst_pos);
   545   static int  branch_destination(int inst, int pos);
   548   friend class AbstractAssembler;
   549   friend class AddressLiteral;
   551   // code patchers need various routines like inv_wdisp()
   552   friend class NativeInstruction;
   553   friend class NativeGeneralJump;
   554   friend class Relocation;
   555   friend class Label;
   557  public:
   558   // op carries format info; see page 62 & 267
   560   enum ops {
   561     call_op   = 1, // fmt 1
   562     branch_op = 0, // also sethi (fmt2)
   563     arith_op  = 2, // fmt 3, arith & misc
   564     ldst_op   = 3  // fmt 3, load/store
   565   };
   567   enum op2s {
   568     bpr_op2   = 3,
   569     fb_op2    = 6,
   570     fbp_op2   = 5,
   571     br_op2    = 2,
   572     bp_op2    = 1,
   573     cb_op2    = 7, // V8
   574     sethi_op2 = 4
   575   };
   577   enum op3s {
   578     // selected op3s
   579     add_op3      = 0x00,
   580     and_op3      = 0x01,
   581     or_op3       = 0x02,
   582     xor_op3      = 0x03,
   583     sub_op3      = 0x04,
   584     andn_op3     = 0x05,
   585     orn_op3      = 0x06,
   586     xnor_op3     = 0x07,
   587     addc_op3     = 0x08,
   588     mulx_op3     = 0x09,
   589     umul_op3     = 0x0a,
   590     smul_op3     = 0x0b,
   591     subc_op3     = 0x0c,
   592     udivx_op3    = 0x0d,
   593     udiv_op3     = 0x0e,
   594     sdiv_op3     = 0x0f,
   596     addcc_op3    = 0x10,
   597     andcc_op3    = 0x11,
   598     orcc_op3     = 0x12,
   599     xorcc_op3    = 0x13,
   600     subcc_op3    = 0x14,
   601     andncc_op3   = 0x15,
   602     orncc_op3    = 0x16,
   603     xnorcc_op3   = 0x17,
   604     addccc_op3   = 0x18,
   605     umulcc_op3   = 0x1a,
   606     smulcc_op3   = 0x1b,
   607     subccc_op3   = 0x1c,
   608     udivcc_op3   = 0x1e,
   609     sdivcc_op3   = 0x1f,
   611     taddcc_op3   = 0x20,
   612     tsubcc_op3   = 0x21,
   613     taddcctv_op3 = 0x22,
   614     tsubcctv_op3 = 0x23,
   615     mulscc_op3   = 0x24,
   616     sll_op3      = 0x25,
   617     sllx_op3     = 0x25,
   618     srl_op3      = 0x26,
   619     srlx_op3     = 0x26,
   620     sra_op3      = 0x27,
   621     srax_op3     = 0x27,
   622     rdreg_op3    = 0x28,
   623     membar_op3   = 0x28,
   625     flushw_op3   = 0x2b,
   626     movcc_op3    = 0x2c,
   627     sdivx_op3    = 0x2d,
   628     popc_op3     = 0x2e,
   629     movr_op3     = 0x2f,
   631     sir_op3      = 0x30,
   632     wrreg_op3    = 0x30,
   633     saved_op3    = 0x31,
   635     fpop1_op3    = 0x34,
   636     fpop2_op3    = 0x35,
   637     impdep1_op3  = 0x36,
   638     impdep2_op3  = 0x37,
   639     jmpl_op3     = 0x38,
   640     rett_op3     = 0x39,
   641     trap_op3     = 0x3a,
   642     flush_op3    = 0x3b,
   643     save_op3     = 0x3c,
   644     restore_op3  = 0x3d,
   645     done_op3     = 0x3e,
   646     retry_op3    = 0x3e,
   648     lduw_op3     = 0x00,
   649     ldub_op3     = 0x01,
   650     lduh_op3     = 0x02,
   651     ldd_op3      = 0x03,
   652     stw_op3      = 0x04,
   653     stb_op3      = 0x05,
   654     sth_op3      = 0x06,
   655     std_op3      = 0x07,
   656     ldsw_op3     = 0x08,
   657     ldsb_op3     = 0x09,
   658     ldsh_op3     = 0x0a,
   659     ldx_op3      = 0x0b,
   661     ldstub_op3   = 0x0d,
   662     stx_op3      = 0x0e,
   663     swap_op3     = 0x0f,
   665     stwa_op3     = 0x14,
   666     stxa_op3     = 0x1e,
   668     ldf_op3      = 0x20,
   669     ldfsr_op3    = 0x21,
   670     ldqf_op3     = 0x22,
   671     lddf_op3     = 0x23,
   672     stf_op3      = 0x24,
   673     stfsr_op3    = 0x25,
   674     stqf_op3     = 0x26,
   675     stdf_op3     = 0x27,
   677     prefetch_op3 = 0x2d,
   680     ldc_op3      = 0x30,
   681     ldcsr_op3    = 0x31,
   682     lddc_op3     = 0x33,
   683     stc_op3      = 0x34,
   684     stcsr_op3    = 0x35,
   685     stdcq_op3    = 0x36,
   686     stdc_op3     = 0x37,
   688     casa_op3     = 0x3c,
   689     casxa_op3    = 0x3e,
   691     alt_bit_op3  = 0x10,
   692      cc_bit_op3  = 0x10
   693   };
   695   enum opfs {
   696     // selected opfs
   697     fmovs_opf   = 0x01,
   698     fmovd_opf   = 0x02,
   700     fnegs_opf   = 0x05,
   701     fnegd_opf   = 0x06,
   703     fadds_opf   = 0x41,
   704     faddd_opf   = 0x42,
   705     fsubs_opf   = 0x45,
   706     fsubd_opf   = 0x46,
   708     fmuls_opf   = 0x49,
   709     fmuld_opf   = 0x4a,
   710     fdivs_opf   = 0x4d,
   711     fdivd_opf   = 0x4e,
   713     fcmps_opf   = 0x51,
   714     fcmpd_opf   = 0x52,
   716     fstox_opf   = 0x81,
   717     fdtox_opf   = 0x82,
   718     fxtos_opf   = 0x84,
   719     fxtod_opf   = 0x88,
   720     fitos_opf   = 0xc4,
   721     fdtos_opf   = 0xc6,
   722     fitod_opf   = 0xc8,
   723     fstod_opf   = 0xc9,
   724     fstoi_opf   = 0xd1,
   725     fdtoi_opf   = 0xd2
   726   };
   728   enum RCondition {  rc_z = 1,  rc_lez = 2,  rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7  };
   730   enum Condition {
   731      // for FBfcc & FBPfcc instruction
   732     f_never                     = 0,
   733     f_notEqual                  = 1,
   734     f_notZero                   = 1,
   735     f_lessOrGreater             = 2,
   736     f_unorderedOrLess           = 3,
   737     f_less                      = 4,
   738     f_unorderedOrGreater        = 5,
   739     f_greater                   = 6,
   740     f_unordered                 = 7,
   741     f_always                    = 8,
   742     f_equal                     = 9,
   743     f_zero                      = 9,
   744     f_unorderedOrEqual          = 10,
   745     f_greaterOrEqual            = 11,
   746     f_unorderedOrGreaterOrEqual = 12,
   747     f_lessOrEqual               = 13,
   748     f_unorderedOrLessOrEqual    = 14,
   749     f_ordered                   = 15,
   751     // V8 coproc, pp 123 v8 manual
   753     cp_always  = 8,
   754     cp_never   = 0,
   755     cp_3       = 7,
   756     cp_2       = 6,
   757     cp_2or3    = 5,
   758     cp_1       = 4,
   759     cp_1or3    = 3,
   760     cp_1or2    = 2,
   761     cp_1or2or3 = 1,
   762     cp_0       = 9,
   763     cp_0or3    = 10,
   764     cp_0or2    = 11,
   765     cp_0or2or3 = 12,
   766     cp_0or1    = 13,
   767     cp_0or1or3 = 14,
   768     cp_0or1or2 = 15,
   771     // for integers
   773     never                 =  0,
   774     equal                 =  1,
   775     zero                  =  1,
   776     lessEqual             =  2,
   777     less                  =  3,
   778     lessEqualUnsigned     =  4,
   779     lessUnsigned          =  5,
   780     carrySet              =  5,
   781     negative              =  6,
   782     overflowSet           =  7,
   783     always                =  8,
   784     notEqual              =  9,
   785     notZero               =  9,
   786     greater               =  10,
   787     greaterEqual          =  11,
   788     greaterUnsigned       =  12,
   789     greaterEqualUnsigned  =  13,
   790     carryClear            =  13,
   791     positive              =  14,
   792     overflowClear         =  15
   793   };
   795   enum CC {
   796     icc  = 0,  xcc  = 2,
   797     // ptr_cc is the correct condition code for a pointer or intptr_t:
   798     ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
   799     fcc0 = 0,  fcc1 = 1, fcc2 = 2, fcc3 = 3
   800   };
   802   enum PrefetchFcn {
   803     severalReads = 0,  oneRead = 1,  severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
   804   };
   806  public:
   807   // Helper functions for groups of instructions
   809   enum Predict { pt = 1, pn = 0 }; // pt = predict taken
   811   enum Membar_mask_bits { // page 184, v9
   812     StoreStore = 1 << 3,
   813     LoadStore  = 1 << 2,
   814     StoreLoad  = 1 << 1,
   815     LoadLoad   = 1 << 0,
   817     Sync       = 1 << 6,
   818     MemIssue   = 1 << 5,
   819     Lookaside  = 1 << 4
   820   };
   822   // test if x is within signed immediate range for nbits
   823   static bool is_simm(int x, int nbits) { return -( 1 << nbits-1 )  <= x   &&   x  <  ( 1 << nbits-1 ); }
   825   // test if -4096 <= x <= 4095
   826   static bool is_simm13(int x) { return is_simm(x, 13); }
   828   enum ASIs { // page 72, v9
   829     ASI_PRIMARY        = 0x80,
   830     ASI_PRIMARY_LITTLE = 0x88
   831     // add more from book as needed
   832   };
   834  protected:
   835   // helpers
   837   // x is supposed to fit in a field "nbits" wide
   838   // and be sign-extended. Check the range.
   840   static void assert_signed_range(intptr_t x, int nbits) {
   841     assert( nbits == 32
   842         ||  -(1 << nbits-1) <= x  &&  x < ( 1 << nbits-1),
   843       "value out of range");
   844   }
   846   static void assert_signed_word_disp_range(intptr_t x, int nbits) {
   847     assert( (x & 3) == 0, "not word aligned");
   848     assert_signed_range(x, nbits + 2);
   849   }
   851   static void assert_unsigned_const(int x, int nbits) {
   852     assert( juint(x)  <  juint(1 << nbits), "unsigned constant out of range");
   853   }
   855   // fields: note bits numbered from LSB = 0,
   856   //  fields known by inclusive bit range
   858   static int fmask(juint hi_bit, juint lo_bit) {
   859     assert( hi_bit >= lo_bit  &&  0 <= lo_bit  &&  hi_bit < 32, "bad bits");
   860     return (1 << ( hi_bit-lo_bit + 1 )) - 1;
   861   }
   863   // inverse of u_field
   865   static int inv_u_field(int x, int hi_bit, int lo_bit) {
   866     juint r = juint(x) >> lo_bit;
   867     r &= fmask( hi_bit, lo_bit);
   868     return int(r);
   869   }
   872   // signed version: extract from field and sign-extend
   874   static int inv_s_field(int x, int hi_bit, int lo_bit) {
   875     int sign_shift = 31 - hi_bit;
   876     return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
   877   }
   879   // given a field that ranges from hi_bit to lo_bit (inclusive,
   880   // LSB = 0), and an unsigned value for the field,
   881   // shift it into the field
   883 #ifdef ASSERT
   884   static int u_field(int x, int hi_bit, int lo_bit) {
   885     assert( ( x & ~fmask(hi_bit, lo_bit))  == 0,
   886             "value out of range");
   887     int r = x << lo_bit;
   888     assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
   889     return r;
   890   }
   891 #else
   892   // make sure this is inlined as it will reduce code size significantly
   893   #define u_field(x, hi_bit, lo_bit)   ((x) << (lo_bit))
   894 #endif
   896   static int inv_op(  int x ) { return inv_u_field(x, 31, 30); }
   897   static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
   898   static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
   899   static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
   901   static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
   903   static Register inv_rd(  int x ) { return as_Register(inv_u_field(x, 29, 25)); }
   904   static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
   905   static Register inv_rs2( int x ) { return as_Register(inv_u_field(x,  4,  0)); }
   907   static int op(       int         x)  { return  u_field(x,             31, 30); }
   908   static int rd(       Register    r)  { return  u_field(r->encoding(), 29, 25); }
   909   static int fcn(      int         x)  { return  u_field(x,             29, 25); }
   910   static int op3(      int         x)  { return  u_field(x,             24, 19); }
   911   static int rs1(      Register    r)  { return  u_field(r->encoding(), 18, 14); }
   912   static int rs2(      Register    r)  { return  u_field(r->encoding(),  4,  0); }
   913   static int annul(    bool        a)  { return  u_field(a ? 1 : 0,     29, 29); }
   914   static int cond(     int         x)  { return  u_field(x,             28, 25); }
   915   static int cond_mov( int         x)  { return  u_field(x,             17, 14); }
   916   static int rcond(    RCondition  x)  { return  u_field(x,             12, 10); }
   917   static int op2(      int         x)  { return  u_field(x,             24, 22); }
   918   static int predict(  bool        p)  { return  u_field(p ? 1 : 0,     19, 19); }
   919   static int branchcc( CC       fcca)  { return  u_field(fcca,          21, 20); }
   920   static int cmpcc(    CC       fcca)  { return  u_field(fcca,          26, 25); }
   921   static int imm_asi(  int         x)  { return  u_field(x,             12,  5); }
   922   static int immed(    bool        i)  { return  u_field(i ? 1 : 0,     13, 13); }
   923   static int opf_low6( int         w)  { return  u_field(w,             10,  5); }
   924   static int opf_low5( int         w)  { return  u_field(w,              9,  5); }
   925   static int trapcc(   CC         cc)  { return  u_field(cc,            12, 11); }
   926   static int sx(       int         i)  { return  u_field(i,             12, 12); } // shift x=1 means 64-bit
   927   static int opf(      int         x)  { return  u_field(x,             13,  5); }
   929   static int opf_cc(   CC          c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
   930   static int mov_cc(   CC          c, bool useFloat ) { return u_field(useFloat ? 0 : 1,  18, 18) | u_field(c, 12, 11); }
   932   static int fd( FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
   933   static int fs1(FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
   934   static int fs2(FloatRegister r,  FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa),  4,  0); };
   936   // some float instructions use this encoding on the op3 field
   937   static int alt_op3(int op, FloatRegisterImpl::Width w) {
   938     int r;
   939     switch(w) {
   940      case FloatRegisterImpl::S: r = op + 0;  break;
   941      case FloatRegisterImpl::D: r = op + 3;  break;
   942      case FloatRegisterImpl::Q: r = op + 2;  break;
   943      default: ShouldNotReachHere(); break;
   944     }
   945     return op3(r);
   946   }
   949   // compute inverse of simm
   950   static int inv_simm(int x, int nbits) {
   951     return (int)(x << (32 - nbits)) >> (32 - nbits);
   952   }
   954   static int inv_simm13( int x ) { return inv_simm(x, 13); }
   956   // signed immediate, in low bits, nbits long
   957   static int simm(int x, int nbits) {
   958     assert_signed_range(x, nbits);
   959     return x  &  (( 1 << nbits ) - 1);
   960   }
   962   // compute inverse of wdisp16
   963   static intptr_t inv_wdisp16(int x, intptr_t pos) {
   964     int lo = x & (( 1 << 14 ) - 1);
   965     int hi = (x >> 20) & 3;
   966     if (hi >= 2) hi |= ~1;
   967     return (((hi << 14) | lo) << 2) + pos;
   968   }
   970   // word offset, 14 bits at LSend, 2 bits at B21, B20
   971   static int wdisp16(intptr_t x, intptr_t off) {
   972     intptr_t xx = x - off;
   973     assert_signed_word_disp_range(xx, 16);
   974     int r =  (xx >> 2) & ((1 << 14) - 1)
   975            |  (  ( (xx>>(2+14)) & 3 )  <<  20 );
   976     assert( inv_wdisp16(r, off) == x,  "inverse is not inverse");
   977     return r;
   978   }
   981   // word displacement in low-order nbits bits
   983   static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
   984     int pre_sign_extend = x & (( 1 << nbits ) - 1);
   985     int r =  pre_sign_extend >= ( 1 << (nbits-1) )
   986        ?   pre_sign_extend | ~(( 1 << nbits ) - 1)
   987        :   pre_sign_extend;
   988     return (r << 2) + pos;
   989   }
   991   static int wdisp( intptr_t x, intptr_t off, int nbits ) {
   992     intptr_t xx = x - off;
   993     assert_signed_word_disp_range(xx, nbits);
   994     int r =  (xx >> 2) & (( 1 << nbits ) - 1);
   995     assert( inv_wdisp( r, off, nbits )  ==  x, "inverse not inverse");
   996     return r;
   997   }
  1000   // Extract the top 32 bits in a 64 bit word
  1001   static int32_t hi32( int64_t x ) {
  1002     int32_t r = int32_t( (uint64_t)x >> 32 );
  1003     return r;
  1006   // given a sethi instruction, extract the constant, left-justified
  1007   static int inv_hi22( int x ) {
  1008     return x << 10;
  1011   // create an imm22 field, given a 32-bit left-justified constant
  1012   static int hi22( int x ) {
  1013     int r = int( juint(x) >> 10 );
  1014     assert( (r & ~((1 << 22) - 1))  ==  0, "just checkin'");
  1015     return r;
  1018   // create a low10 __value__ (not a field) for a given a 32-bit constant
  1019   static int low10( int x ) {
  1020     return x & ((1 << 10) - 1);
  1023   // instruction only in v9
  1024   static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); }
  1026   // instruction only in v8
  1027   static void v8_only() { assert( VM_Version::v8_instructions_work(), "This instruction only works on SPARC V8"); }
  1029   // instruction deprecated in v9
  1030   static void v9_dep()  { } // do nothing for now
  1032   // some float instructions only exist for single prec. on v8
  1033   static void v8_s_only(FloatRegisterImpl::Width w)  { if (w != FloatRegisterImpl::S)  v9_only(); }
  1035   // v8 has no CC field
  1036   static void v8_no_cc(CC cc)  { if (cc)  v9_only(); }
  1038  protected:
  1039   // Simple delay-slot scheme:
  1040   // In order to check the programmer, the assembler keeps track of deley slots.
  1041   // It forbids CTIs in delay slots (conservative, but should be OK).
  1042   // Also, when putting an instruction into a delay slot, you must say
  1043   // asm->delayed()->add(...), in order to check that you don't omit
  1044   // delay-slot instructions.
  1045   // To implement this, we use a simple FSA
  1047 #ifdef ASSERT
  1048   #define CHECK_DELAY
  1049 #endif
  1050 #ifdef CHECK_DELAY
  1051   enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
  1052 #endif
  1054  public:
  1055   // Tells assembler next instruction must NOT be in delay slot.
  1056   // Use at start of multinstruction macros.
  1057   void assert_not_delayed() {
  1058     // This is a separate overloading to avoid creation of string constants
  1059     // in non-asserted code--with some compilers this pollutes the object code.
  1060 #ifdef CHECK_DELAY
  1061     assert_not_delayed("next instruction should not be a delay slot");
  1062 #endif
  1064   void assert_not_delayed(const char* msg) {
  1065 #ifdef CHECK_DELAY
  1066     assert(delay_state == no_delay, msg);
  1067 #endif
  1070  protected:
  1071   // Delay slot helpers
  1072   // cti is called when emitting control-transfer instruction,
  1073   // BEFORE doing the emitting.
  1074   // Only effective when assertion-checking is enabled.
  1075   void cti() {
  1076 #ifdef CHECK_DELAY
  1077     assert_not_delayed("cti should not be in delay slot");
  1078 #endif
  1081   // called when emitting cti with a delay slot, AFTER emitting
  1082   void has_delay_slot() {
  1083 #ifdef CHECK_DELAY
  1084     assert_not_delayed("just checking");
  1085     delay_state = at_delay_slot;
  1086 #endif
  1089 public:
  1090   // Tells assembler you know that next instruction is delayed
  1091   Assembler* delayed() {
  1092 #ifdef CHECK_DELAY
  1093     assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
  1094     delay_state = filling_delay_slot;
  1095 #endif
  1096     return this;
  1099   void flush() {
  1100 #ifdef CHECK_DELAY
  1101     assert ( delay_state == no_delay, "ending code with a delay slot");
  1102 #endif
  1103     AbstractAssembler::flush();
  1106   inline void emit_long(int);  // shadows AbstractAssembler::emit_long
  1107   inline void emit_data(int x) { emit_long(x); }
  1108   inline void emit_data(int, RelocationHolder const&);
  1109   inline void emit_data(int, relocInfo::relocType rtype);
  1110   // helper for above fcns
  1111   inline void check_delay();
  1114  public:
  1115   // instructions, refer to page numbers in the SPARC Architecture Manual, V9
  1117   // pp 135 (addc was addx in v8)
  1119   inline void add(Register s1, Register s2, Register d );
  1120   inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none);
  1121   inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec);
  1122   inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
  1123   inline void add(const Address& a, Register d, int offset = 0) { add( a.base(), a.disp() + offset, d, a.rspec(offset)); }
  1125   void addcc(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
  1126   void addcc(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1127   void addc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3             ) | rs1(s1) | rs2(s2) ); }
  1128   void addc(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1129   void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
  1130   void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1132   // pp 136
  1134   inline void bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
  1135   inline void bpr( RCondition c, bool a, Predict p, Register s1, Label& L);
  1137  protected: // use MacroAssembler::br instead
  1139   // pp 138
  1141   inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
  1142   inline void fb( Condition c, bool a, Label& L );
  1144   // pp 141
  1146   inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
  1147   inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
  1149  public:
  1151   // pp 144
  1153   inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
  1154   inline void br( Condition c, bool a, Label& L );
  1156   // pp 146
  1158   inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
  1159   inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
  1161   // pp 121 (V8)
  1163   inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
  1164   inline void cb( Condition c, bool a, Label& L );
  1166   // pp 149
  1168   inline void call( address d,  relocInfo::relocType rt = relocInfo::runtime_call_type );
  1169   inline void call( Label& L,   relocInfo::relocType rt = relocInfo::runtime_call_type );
  1171   // pp 150
  1173   // These instructions compare the contents of s2 with the contents of
  1174   // memory at address in s1. If the values are equal, the contents of memory
  1175   // at address s1 is swapped with the data in d. If the values are not equal,
  1176   // the the contents of memory at s1 is loaded into d, without the swap.
  1178   void casa(  Register s1, Register s2, Register d, int ia = -1 ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1  ? immed(true) : imm_asi(ia)) | rs2(s2)); }
  1179   void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1  ? immed(true) : imm_asi(ia)) | rs2(s2)); }
  1181   // pp 152
  1183   void udiv(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3             ) | rs1(s1) | rs2(s2)); }
  1184   void udiv(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1185   void sdiv(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3             ) | rs1(s1) | rs2(s2)); }
  1186   void sdiv(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1187   void udivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
  1188   void udivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1189   void sdivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
  1190   void sdivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1192   // pp 155
  1194   void done()  { v9_only();  cti();  emit_long( op(arith_op) | fcn(0) | op3(done_op3) ); }
  1195   void retry() { v9_only();  cti();  emit_long( op(arith_op) | fcn(1) | op3(retry_op3) ); }
  1197   // pp 156
  1199   void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); }
  1200   void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); }
  1202   // pp 157
  1204   void fcmp(  FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc);  emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
  1205   void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc);  emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
  1207   // pp 159
  1209   void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only();  emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
  1210   void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) {             emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
  1212   // pp 160
  1214   void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
  1216   // pp 161
  1218   void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only();  emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, w)); }
  1219   void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) {             emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, w)); }
  1221   // pp 162
  1223   void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w);  emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
  1225   void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w);  emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
  1227   // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fnegs is the only instruction available
  1228   // on v8 to do negation of single, double and quad precision floats.
  1230   void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) |  opf(0x05) | fs2(sd, w)); }
  1232   void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w);  emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }
  1234   // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fabss is the only instruction available
  1235   // on v8 to do abs operation on single/double/quad precision floats.
  1237   void fabs( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x09) | fs2(sd, w)); }
  1239   // pp 163
  1241   void fmul( FloatRegisterImpl::Width w,                            FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w)  | op3(fpop1_op3) | fs1(s1, w)  | opf(0x48 + w)         | fs2(s2, w)); }
  1242   void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw,  FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
  1243   void fdiv( FloatRegisterImpl::Width w,                            FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w)  | op3(fpop1_op3) | fs1(s1, w)  | opf(0x4c + w)         | fs2(s2, w)); }
  1245   // pp 164
  1247   void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
  1249   // pp 165
  1251   inline void flush( Register s1, Register s2 );
  1252   inline void flush( Register s1, int simm13a);
  1254   // pp 167
  1256   void flushw() { v9_only();  emit_long( op(arith_op) | op3(flushw_op3) ); }
  1258   // pp 168
  1260   void illtrap( int const22a) { if (const22a != 0) v9_only();  emit_long( op(branch_op) | u_field(const22a, 21, 0) ); }
  1261   // v8 unimp == illtrap(0)
  1263   // pp 169
  1265   void impdep1( int id1, int const19a ) { v9_only();  emit_long( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); }
  1266   void impdep2( int id1, int const19a ) { v9_only();  emit_long( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); }
  1268   // pp 149 (v8)
  1270   void cpop1( int opc, int cr1, int cr2, int crd ) { v8_only();  emit_long( op(arith_op) | fcn(crd) | op3(impdep1_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
  1271   void cpop2( int opc, int cr1, int cr2, int crd ) { v8_only();  emit_long( op(arith_op) | fcn(crd) | op3(impdep2_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
  1273   // pp 170
  1275   void jmpl( Register s1, Register s2, Register d );
  1276   void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
  1278   // 171
  1280   inline void ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d);
  1281   inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
  1282   inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
  1284   inline void ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0);
  1287   inline void ldfsr(  Register s1, Register s2 );
  1288   inline void ldfsr(  Register s1, int simm13a);
  1289   inline void ldxfsr( Register s1, Register s2 );
  1290   inline void ldxfsr( Register s1, int simm13a);
  1292   // pp 94 (v8)
  1294   inline void ldc(   Register s1, Register s2, int crd );
  1295   inline void ldc(   Register s1, int simm13a, int crd);
  1296   inline void lddc(  Register s1, Register s2, int crd );
  1297   inline void lddc(  Register s1, int simm13a, int crd);
  1298   inline void ldcsr( Register s1, Register s2, int crd );
  1299   inline void ldcsr( Register s1, int simm13a, int crd);
  1302   // 173
  1304   void ldfa(  FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only();  emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
  1305   void ldfa(  FloatRegisterImpl::Width w, Register s1, int simm13a,         FloatRegister d ) { v9_only();  emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1307   // pp 175, lduw is ld on v8
  1309   inline void ldsb(  Register s1, Register s2, Register d );
  1310   inline void ldsb(  Register s1, int simm13a, Register d);
  1311   inline void ldsh(  Register s1, Register s2, Register d );
  1312   inline void ldsh(  Register s1, int simm13a, Register d);
  1313   inline void ldsw(  Register s1, Register s2, Register d );
  1314   inline void ldsw(  Register s1, int simm13a, Register d);
  1315   inline void ldub(  Register s1, Register s2, Register d );
  1316   inline void ldub(  Register s1, int simm13a, Register d);
  1317   inline void lduh(  Register s1, Register s2, Register d );
  1318   inline void lduh(  Register s1, int simm13a, Register d);
  1319   inline void lduw(  Register s1, Register s2, Register d );
  1320   inline void lduw(  Register s1, int simm13a, Register d);
  1321   inline void ldx(   Register s1, Register s2, Register d );
  1322   inline void ldx(   Register s1, int simm13a, Register d);
  1323   inline void ld(    Register s1, Register s2, Register d );
  1324   inline void ld(    Register s1, int simm13a, Register d);
  1325   inline void ldd(   Register s1, Register s2, Register d );
  1326   inline void ldd(   Register s1, int simm13a, Register d);
  1328 #ifdef ASSERT
  1329   // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
  1330   inline void ld(    Register s1, ByteSize simm13a, Register d);
  1331 #endif
  1333   inline void ldsb(const Address& a, Register d, int offset = 0);
  1334   inline void ldsh(const Address& a, Register d, int offset = 0);
  1335   inline void ldsw(const Address& a, Register d, int offset = 0);
  1336   inline void ldub(const Address& a, Register d, int offset = 0);
  1337   inline void lduh(const Address& a, Register d, int offset = 0);
  1338   inline void lduw(const Address& a, Register d, int offset = 0);
  1339   inline void ldx( const Address& a, Register d, int offset = 0);
  1340   inline void ld(  const Address& a, Register d, int offset = 0);
  1341   inline void ldd( const Address& a, Register d, int offset = 0);
  1343   inline void ldub(  Register s1, RegisterOrConstant s2, Register d );
  1344   inline void ldsb(  Register s1, RegisterOrConstant s2, Register d );
  1345   inline void lduh(  Register s1, RegisterOrConstant s2, Register d );
  1346   inline void ldsh(  Register s1, RegisterOrConstant s2, Register d );
  1347   inline void lduw(  Register s1, RegisterOrConstant s2, Register d );
  1348   inline void ldsw(  Register s1, RegisterOrConstant s2, Register d );
  1349   inline void ldx(   Register s1, RegisterOrConstant s2, Register d );
  1350   inline void ld(    Register s1, RegisterOrConstant s2, Register d );
  1351   inline void ldd(   Register s1, RegisterOrConstant s2, Register d );
  1353   // pp 177
  1355   void ldsba(  Register s1, Register s2, int ia, Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
  1356   void ldsba(  Register s1, int simm13a,         Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1357   void ldsha(  Register s1, Register s2, int ia, Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
  1358   void ldsha(  Register s1, int simm13a,         Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1359   void ldswa(  Register s1, Register s2, int ia, Register d ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
  1360   void ldswa(  Register s1, int simm13a,         Register d ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1361   void lduba(  Register s1, Register s2, int ia, Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
  1362   void lduba(  Register s1, int simm13a,         Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1363   void lduha(  Register s1, Register s2, int ia, Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
  1364   void lduha(  Register s1, int simm13a,         Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1365   void lduwa(  Register s1, Register s2, int ia, Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
  1366   void lduwa(  Register s1, int simm13a,         Register d ) {             emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1367   void ldxa(   Register s1, Register s2, int ia, Register d ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(ldx_op3  | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
  1368   void ldxa(   Register s1, int simm13a,         Register d ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(ldx_op3  | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1369   void ldda(   Register s1, Register s2, int ia, Register d ) { v9_dep();   emit_long( op(ldst_op) | rd(d) | op3(ldd_op3  | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
  1370   void ldda(   Register s1, int simm13a,         Register d ) { v9_dep();   emit_long( op(ldst_op) | rd(d) | op3(ldd_op3  | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1372   // pp 179
  1374   inline void ldstub(  Register s1, Register s2, Register d );
  1375   inline void ldstub(  Register s1, int simm13a, Register d);
  1377   // pp 180
  1379   void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
  1380   void ldstuba( Register s1, int simm13a,         Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1382   // pp 181
  1384   void and3(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3              ) | rs1(s1) | rs2(s2) ); }
  1385   void and3(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1386   void andcc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
  1387   void andcc(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1388   void andn(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3             ) | rs1(s1) | rs2(s2) ); }
  1389   void andn(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1390   void andn(    Register s1, RegisterOrConstant s2, Register d);
  1391   void andncc(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
  1392   void andncc(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1393   void or3(     Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3               ) | rs1(s1) | rs2(s2) ); }
  1394   void or3(     Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3               ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1395   void orcc(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3   | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
  1396   void orcc(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3   | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1397   void orn(     Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
  1398   void orn(     Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1399   void orncc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
  1400   void orncc(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1401   void xor3(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3              ) | rs1(s1) | rs2(s2) ); }
  1402   void xor3(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1403   void xorcc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3  | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
  1404   void xorcc(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3  | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1405   void xnor(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3             ) | rs1(s1) | rs2(s2) ); }
  1406   void xnor(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1407   void xnorcc(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
  1408   void xnorcc(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1410   // pp 183
  1412   void membar( Membar_mask_bits const7a ) { v9_only(); emit_long( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); }
  1414   // pp 185
  1416   void fmov( FloatRegisterImpl::Width w, Condition c,  bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only();  emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); }
  1418   // pp 189
  1420   void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1,  FloatRegister s2, FloatRegister d ) { v9_only();  emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); }
  1422   // pp 191
  1424   void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); }
  1425   void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); }
  1427   // pp 195
  1429   void movr( RCondition c, Register s1, Register s2,  Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); }
  1430   void movr( RCondition c, Register s1, int simm10a,  Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); }
  1432   // pp 196
  1434   void mulx(  Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); }
  1435   void mulx(  Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1436   void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
  1437   void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1438   void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
  1439   void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1441   // pp 197
  1443   void umul(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3             ) | rs1(s1) | rs2(s2) ); }
  1444   void umul(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1445   void smul(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3             ) | rs1(s1) | rs2(s2) ); }
  1446   void smul(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1447   void umulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
  1448   void umulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1449   void smulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
  1450   void smulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1452   // pp 199
  1454   void mulscc(   Register s1, Register s2, Register d ) { v9_dep();  emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | rs2(s2) ); }
  1455   void mulscc(   Register s1, int simm13a, Register d ) { v9_dep();  emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1457   // pp 201
  1459   void nop() { emit_long( op(branch_op) | op2(sethi_op2) ); }
  1462   // pp 202
  1464   void popc( Register s,  Register d) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
  1465   void popc( int simm13a, Register d) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
  1467   // pp 203
  1469   void prefetch(   Register s1, Register s2,         PrefetchFcn f);
  1470   void prefetch(   Register s1, int simm13a,         PrefetchFcn f);
  1471   void prefetcha(  Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only();  emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
  1472   void prefetcha(  Register s1, int simm13a,         PrefetchFcn f ) { v9_only();  emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1474   inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0);
  1476   // pp 208
  1478   // not implementing read privileged register
  1480   inline void rdy(    Register d) { v9_dep();  emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); }
  1481   inline void rdccr(  Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); }
  1482   inline void rdasi(  Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); }
  1483   inline void rdtick( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon!
  1484   inline void rdpc(   Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); }
  1485   inline void rdfprs( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); }
  1487   // pp 213
  1489   inline void rett( Register s1, Register s2);
  1490   inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
  1492   // pp 214
  1494   void save(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); }
  1495   void save(    Register s1, int simm13a, Register d ) {
  1496     // make sure frame is at least large enough for the register save area
  1497     assert(-simm13a >= 16 * wordSize, "frame too small");
  1498     emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) );
  1501   void restore( Register s1 = G0,  Register s2 = G0, Register d = G0 ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); }
  1502   void restore( Register s1,       int simm13a,      Register d      ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1504   // pp 216
  1506   void saved()    { v9_only();  emit_long( op(arith_op) | fcn(0) | op3(saved_op3)); }
  1507   void restored() { v9_only();  emit_long( op(arith_op) | fcn(1) | op3(saved_op3)); }
  1509   // pp 217
  1511   inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
  1512   // pp 218
  1514   void sll(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
  1515   void sll(  Register s1, int imm5a,   Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
  1516   void srl(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
  1517   void srl(  Register s1, int imm5a,   Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
  1518   void sra(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
  1519   void sra(  Register s1, int imm5a,   Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
  1521   void sllx( Register s1, Register s2, Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
  1522   void sllx( Register s1, int imm6a,   Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
  1523   void srlx( Register s1, Register s2, Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
  1524   void srlx( Register s1, int imm6a,   Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
  1525   void srax( Register s1, Register s2, Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
  1526   void srax( Register s1, int imm6a,   Register d ) { v9_only();  emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
  1528   // pp 220
  1530   void sir( int simm13a ) { emit_long( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); }
  1532   // pp 221
  1534   void stbar() { emit_long( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); }
  1536   // pp 222
  1538   inline void stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2);
  1539   inline void stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
  1540   inline void stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
  1541   inline void stf(    FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0);
  1543   inline void stfsr(  Register s1, Register s2 );
  1544   inline void stfsr(  Register s1, int simm13a);
  1545   inline void stxfsr( Register s1, Register s2 );
  1546   inline void stxfsr( Register s1, int simm13a);
  1548   //  pp 224
  1550   void stfa(  FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only();  emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
  1551   void stfa(  FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a         ) { v9_only();  emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1553   // p 226
  1555   inline void stb(  Register d, Register s1, Register s2 );
  1556   inline void stb(  Register d, Register s1, int simm13a);
  1557   inline void sth(  Register d, Register s1, Register s2 );
  1558   inline void sth(  Register d, Register s1, int simm13a);
  1559   inline void stw(  Register d, Register s1, Register s2 );
  1560   inline void stw(  Register d, Register s1, int simm13a);
  1561   inline void st(   Register d, Register s1, Register s2 );
  1562   inline void st(   Register d, Register s1, int simm13a);
  1563   inline void stx(  Register d, Register s1, Register s2 );
  1564   inline void stx(  Register d, Register s1, int simm13a);
  1565   inline void std(  Register d, Register s1, Register s2 );
  1566   inline void std(  Register d, Register s1, int simm13a);
  1568 #ifdef ASSERT
  1569   // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
  1570   inline void st(   Register d, Register s1, ByteSize simm13a);
  1571 #endif
  1573   inline void stb(  Register d, const Address& a, int offset = 0 );
  1574   inline void sth(  Register d, const Address& a, int offset = 0 );
  1575   inline void stw(  Register d, const Address& a, int offset = 0 );
  1576   inline void stx(  Register d, const Address& a, int offset = 0 );
  1577   inline void st(   Register d, const Address& a, int offset = 0 );
  1578   inline void std(  Register d, const Address& a, int offset = 0 );
  1580   inline void stb(  Register d, Register s1, RegisterOrConstant s2 );
  1581   inline void sth(  Register d, Register s1, RegisterOrConstant s2 );
  1582   inline void stw(  Register d, Register s1, RegisterOrConstant s2 );
  1583   inline void stx(  Register d, Register s1, RegisterOrConstant s2 );
  1584   inline void std(  Register d, Register s1, RegisterOrConstant s2 );
  1585   inline void st(   Register d, Register s1, RegisterOrConstant s2 );
  1587   // pp 177
  1589   void stba(  Register d, Register s1, Register s2, int ia ) {             emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
  1590   void stba(  Register d, Register s1, int simm13a         ) {             emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1591   void stha(  Register d, Register s1, Register s2, int ia ) {             emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
  1592   void stha(  Register d, Register s1, int simm13a         ) {             emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1593   void stwa(  Register d, Register s1, Register s2, int ia ) {             emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
  1594   void stwa(  Register d, Register s1, int simm13a         ) {             emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1595   void stxa(  Register d, Register s1, Register s2, int ia ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
  1596   void stxa(  Register d, Register s1, int simm13a         ) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1597   void stda(  Register d, Register s1, Register s2, int ia ) {             emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
  1598   void stda(  Register d, Register s1, int simm13a         ) {             emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1600   // pp 97 (v8)
  1602   inline void stc(   int crd, Register s1, Register s2 );
  1603   inline void stc(   int crd, Register s1, int simm13a);
  1604   inline void stdc(  int crd, Register s1, Register s2 );
  1605   inline void stdc(  int crd, Register s1, int simm13a);
  1606   inline void stcsr( int crd, Register s1, Register s2 );
  1607   inline void stcsr( int crd, Register s1, int simm13a);
  1608   inline void stdcq( int crd, Register s1, Register s2 );
  1609   inline void stdcq( int crd, Register s1, int simm13a);
  1611   // pp 230
  1613   void sub(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3              ) | rs1(s1) | rs2(s2) ); }
  1614   void sub(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1615   void subcc(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
  1616   void subcc(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1617   void subc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3             ) | rs1(s1) | rs2(s2) ); }
  1618   void subc(   Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3             ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1619   void subccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
  1620   void subccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1622   // pp 231
  1624   inline void swap( Register s1, Register s2, Register d );
  1625   inline void swap( Register s1, int simm13a, Register d);
  1626   inline void swap( Address& a,               Register d, int offset = 0 );
  1628   // pp 232
  1630   void swapa(   Register s1, Register s2, int ia, Register d ) { v9_dep();  emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
  1631   void swapa(   Register s1, int simm13a,         Register d ) { v9_dep();  emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1633   // pp 234, note op in book is wrong, see pp 268
  1635   void taddcc(    Register s1, Register s2, Register d ) {            emit_long( op(arith_op) | rd(d) | op3(taddcc_op3  ) | rs1(s1) | rs2(s2) ); }
  1636   void taddcc(    Register s1, int simm13a, Register d ) {            emit_long( op(arith_op) | rd(d) | op3(taddcc_op3  ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1637   void taddcctv(  Register s1, Register s2, Register d ) { v9_dep();  emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | rs2(s2) ); }
  1638   void taddcctv(  Register s1, int simm13a, Register d ) { v9_dep();  emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1640   // pp 235
  1642   void tsubcc(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3  ) | rs1(s1) | rs2(s2) ); }
  1643   void tsubcc(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3  ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1644   void tsubcctv(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | rs2(s2) ); }
  1645   void tsubcctv(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
  1647   // pp 237
  1649   void trap( Condition c, CC cc, Register s1, Register s2 ) { v8_no_cc(cc);  emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
  1650   void trap( Condition c, CC cc, Register s1, int trapa   ) { v8_no_cc(cc);  emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
  1651   // simple uncond. trap
  1652   void trap( int trapa ) { trap( always, icc, G0, trapa ); }
  1654   // pp 239 omit write priv register for now
  1656   inline void wry(    Register d) { v9_dep();  emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
  1657   inline void wrccr(Register s) { v9_only(); emit_long( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
  1658   inline void wrccr(Register s, int simm13a) { v9_only(); emit_long( op(arith_op) |
  1659                                                                            rs1(s) |
  1660                                                                            op3(wrreg_op3) |
  1661                                                                            u_field(2, 29, 25) |
  1662                                                                            u_field(1, 13, 13) |
  1663                                                                            simm(simm13a, 13)); }
  1664   inline void wrasi(  Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
  1665   inline void wrfprs( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
  1667   // For a given register condition, return the appropriate condition code
  1668   // Condition (the one you would use to get the same effect after "tst" on
  1669   // the target register.)
  1670   Assembler::Condition reg_cond_to_cc_cond(RCondition in);
  1673   // Creation
  1674   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
  1675 #ifdef CHECK_DELAY
  1676     delay_state = no_delay;
  1677 #endif
  1680   // Testing
  1681 #ifndef PRODUCT
  1682   void test_v9();
  1683   void test_v8_onlys();
  1684 #endif
  1685 };
  1688 class RegistersForDebugging : public StackObj {
  1689  public:
  1690   intptr_t i[8], l[8], o[8], g[8];
  1691   float    f[32];
  1692   double   d[32];
  1694   void print(outputStream* s);
  1696   static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); }
  1697   static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); }
  1698   static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); }
  1699   static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); }
  1700   static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); }
  1701   static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); }
  1703   // gen asm code to save regs
  1704   static void save_registers(MacroAssembler* a);
  1706   // restore global registers in case C code disturbed them
  1707   static void restore_registers(MacroAssembler* a, Register r);
  1710 };
  1713 // MacroAssembler extends Assembler by a few frequently used macros.
  1714 //
  1715 // Most of the standard SPARC synthetic ops are defined here.
  1716 // Instructions for which a 'better' code sequence exists depending
  1717 // on arguments should also go in here.
  1719 #define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__)
  1720 #define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__)
  1721 #define JUMP(a, temp, off)     jump(a, temp, off, __FILE__, __LINE__)
  1722 #define JUMPL(a, temp, d, off) jumpl(a, temp, d, off, __FILE__, __LINE__)
  1725 class MacroAssembler: public Assembler {
  1726  protected:
  1727   // Support for VM calls
  1728   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  1729   // may customize this version by overriding it for its purposes (e.g., to save/restore
  1730   // additional registers when doing a VM call).
  1731 #ifdef CC_INTERP
  1732   #define VIRTUAL
  1733 #else
  1734   #define VIRTUAL virtual
  1735 #endif
  1737   VIRTUAL void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments);
  1739   //
  1740   // It is imperative that all calls into the VM are handled via the call_VM macros.
  1741   // They make sure that the stack linkage is setup correctly. call_VM's correspond
  1742   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
  1743   //
  1744   // This is the base routine called by the different versions of call_VM. The interpreter
  1745   // may customize this version by overriding it for its purposes (e.g., to save/restore
  1746   // additional registers when doing a VM call).
  1747   //
  1748   // A non-volatile java_thread_cache register should be specified so
  1749   // that the G2_thread value can be preserved across the call.
  1750   // (If java_thread_cache is noreg, then a slow get_thread call
  1751   // will re-initialize the G2_thread.) call_VM_base returns the register that contains the
  1752   // thread.
  1753   //
  1754   // If no last_java_sp is specified (noreg) than SP will be used instead.
  1756   virtual void call_VM_base(
  1757     Register        oop_result,             // where an oop-result ends up if any; use noreg otherwise
  1758     Register        java_thread_cache,      // the thread if computed before     ; use noreg otherwise
  1759     Register        last_java_sp,           // to set up last_Java_frame in stubs; use noreg otherwise
  1760     address         entry_point,            // the entry point
  1761     int             number_of_arguments,    // the number of arguments (w/o thread) to pop after call
  1762     bool            check_exception=true    // flag which indicates if exception should be checked
  1763   );
  1765   // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  1766   // The implementation is only non-empty for the InterpreterMacroAssembler,
  1767   // as only the interpreter handles and ForceEarlyReturn PopFrame requests.
  1768   virtual void check_and_handle_popframe(Register scratch_reg);
  1769   virtual void check_and_handle_earlyret(Register scratch_reg);
  1771  public:
  1772   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
  1774   // Support for NULL-checks
  1775   //
  1776   // Generates code that causes a NULL OS exception if the content of reg is NULL.
  1777   // If the accessed location is M[reg + offset] and the offset is known, provide the
  1778   // offset.  No explicit code generation is needed if the offset is within a certain
  1779   // range (0 <= offset <= page_size).
  1780   //
  1781   // %%%%%% Currently not done for SPARC
  1783   void null_check(Register reg, int offset = -1);
  1784   static bool needs_explicit_null_check(intptr_t offset);
  1786   // support for delayed instructions
  1787   MacroAssembler* delayed() { Assembler::delayed();  return this; }
  1789   // branches that use right instruction for v8 vs. v9
  1790   inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
  1791   inline void br( Condition c, bool a, Predict p, Label& L );
  1792   inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
  1793   inline void fb( Condition c, bool a, Predict p, Label& L );
  1795   // compares register with zero and branches (V9 and V8 instructions)
  1796   void br_zero( Condition c, bool a, Predict p, Register s1, Label& L);
  1797   // Compares a pointer register with zero and branches on (not)null.
  1798   // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
  1799   void br_null   ( Register s1, bool a, Predict p, Label& L );
  1800   void br_notnull( Register s1, bool a, Predict p, Label& L );
  1802   // These versions will do the most efficient thing on v8 and v9.  Perhaps
  1803   // this is what the routine above was meant to do, but it didn't (and
  1804   // didn't cover both target address kinds.)
  1805   void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
  1806   void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, Label& L);
  1808   inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
  1809   inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
  1811   // Branch that tests xcc in LP64 and icc in !LP64
  1812   inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
  1813   inline void brx( Condition c, bool a, Predict p, Label& L );
  1815   // unconditional short branch
  1816   inline void ba( bool a, Label& L );
  1818   // Branch that tests fp condition codes
  1819   inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
  1820   inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
  1822   // get PC the best way
  1823   inline int get_pc( Register d );
  1825   // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual)
  1826   inline void cmp(  Register s1, Register s2 ) { subcc( s1, s2, G0 ); }
  1827   inline void cmp(  Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); }
  1829   inline void jmp( Register s1, Register s2 );
  1830   inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
  1832   inline void call( address d,  relocInfo::relocType rt = relocInfo::runtime_call_type );
  1833   inline void call( Label& L,   relocInfo::relocType rt = relocInfo::runtime_call_type );
  1834   inline void callr( Register s1, Register s2 );
  1835   inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
  1837   // Emits nothing on V8
  1838   inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none );
  1839   inline void iprefetch( Label& L);
  1841   inline void tst( Register s ) { orcc( G0, s, G0 ); }
  1843 #ifdef PRODUCT
  1844   inline void ret(  bool trace = TraceJumps )   { if (trace) {
  1845                                                     mov(I7, O7); // traceable register
  1846                                                     JMP(O7, 2 * BytesPerInstWord);
  1847                                                   } else {
  1848                                                     jmpl( I7, 2 * BytesPerInstWord, G0 );
  1852   inline void retl( bool trace = TraceJumps )  { if (trace) JMP(O7, 2 * BytesPerInstWord);
  1853                                                  else jmpl( O7, 2 * BytesPerInstWord, G0 ); }
  1854 #else
  1855   void ret(  bool trace = TraceJumps );
  1856   void retl( bool trace = TraceJumps );
  1857 #endif /* PRODUCT */
  1859   // Required platform-specific helpers for Label::patch_instructions.
  1860   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
  1861   void pd_patch_instruction(address branch, address target);
  1862 #ifndef PRODUCT
  1863   static void pd_print_patched_instruction(address branch);
  1864 #endif
  1866   // sethi Macro handles optimizations and relocations
  1867 private:
  1868   void internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable);
  1869 public:
  1870   void sethi(const AddressLiteral& addrlit, Register d);
  1871   void patchable_sethi(const AddressLiteral& addrlit, Register d);
  1873   // compute the size of a sethi/set
  1874   static int  size_of_sethi( address a, bool worst_case = false );
  1875   static int  worst_case_size_of_set();
  1877   // set may be either setsw or setuw (high 32 bits may be zero or sign)
  1878 private:
  1879   void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable);
  1880 public:
  1881   void set(const AddressLiteral& addrlit, Register d);
  1882   void set(intptr_t value, Register d);
  1883   void set(address addr, Register d, RelocationHolder const& rspec);
  1884   void patchable_set(const AddressLiteral& addrlit, Register d);
  1885   void patchable_set(intptr_t value, Register d);
  1886   void set64(jlong value, Register d, Register tmp);
  1888   // sign-extend 32 to 64
  1889   inline void signx( Register s, Register d ) { sra( s, G0, d); }
  1890   inline void signx( Register d )             { sra( d, G0, d); }
  1892   inline void not1( Register s, Register d ) { xnor( s, G0, d ); }
  1893   inline void not1( Register d )             { xnor( d, G0, d ); }
  1895   inline void neg( Register s, Register d ) { sub( G0, s, d ); }
  1896   inline void neg( Register d )             { sub( G0, d, d ); }
  1898   inline void cas(  Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); }
  1899   inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); }
  1900   // Functions for isolating 64 bit atomic swaps for LP64
  1901   // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's
  1902   inline void cas_ptr(  Register s1, Register s2, Register d) {
  1903 #ifdef _LP64
  1904     casx( s1, s2, d );
  1905 #else
  1906     cas( s1, s2, d );
  1907 #endif
  1910   // Functions for isolating 64 bit shifts for LP64
  1911   inline void sll_ptr( Register s1, Register s2, Register d );
  1912   inline void sll_ptr( Register s1, int imm6a,   Register d );
  1913   inline void sll_ptr( Register s1, RegisterOrConstant s2, Register d );
  1914   inline void srl_ptr( Register s1, Register s2, Register d );
  1915   inline void srl_ptr( Register s1, int imm6a,   Register d );
  1917   // little-endian
  1918   inline void casl(  Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); }
  1919   inline void casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); }
  1921   inline void inc(   Register d,  int const13 = 1 ) { add(   d, const13, d); }
  1922   inline void inccc( Register d,  int const13 = 1 ) { addcc( d, const13, d); }
  1924   inline void dec(   Register d,  int const13 = 1 ) { sub(   d, const13, d); }
  1925   inline void deccc( Register d,  int const13 = 1 ) { subcc( d, const13, d); }
  1927   inline void btst( Register s1,  Register s2 ) { andcc( s1, s2, G0 ); }
  1928   inline void btst( int simm13a,  Register s )  { andcc( s,  simm13a, G0 ); }
  1930   inline void bset( Register s1,  Register s2 ) { or3( s1, s2, s2 ); }
  1931   inline void bset( int simm13a,  Register s )  { or3( s,  simm13a, s ); }
  1933   inline void bclr( Register s1,  Register s2 ) { andn( s1, s2, s2 ); }
  1934   inline void bclr( int simm13a,  Register s )  { andn( s,  simm13a, s ); }
  1936   inline void btog( Register s1,  Register s2 ) { xor3( s1, s2, s2 ); }
  1937   inline void btog( int simm13a,  Register s )  { xor3( s,  simm13a, s ); }
  1939   inline void clr( Register d ) { or3( G0, G0, d ); }
  1941   inline void clrb( Register s1, Register s2);
  1942   inline void clrh( Register s1, Register s2);
  1943   inline void clr(  Register s1, Register s2);
  1944   inline void clrx( Register s1, Register s2);
  1946   inline void clrb( Register s1, int simm13a);
  1947   inline void clrh( Register s1, int simm13a);
  1948   inline void clr(  Register s1, int simm13a);
  1949   inline void clrx( Register s1, int simm13a);
  1951   // copy & clear upper word
  1952   inline void clruw( Register s, Register d ) { srl( s, G0, d); }
  1953   // clear upper word
  1954   inline void clruwu( Register d ) { srl( d, G0, d); }
  1956   // membar psuedo instruction.  takes into account target memory model.
  1957   inline void membar( Assembler::Membar_mask_bits const7a );
  1959   // returns if membar generates anything.
  1960   inline bool membar_has_effect( Assembler::Membar_mask_bits const7a );
  1962   // mov pseudo instructions
  1963   inline void mov( Register s,  Register d) {
  1964     if ( s != d )    or3( G0, s, d);
  1965     else             assert_not_delayed();  // Put something useful in the delay slot!
  1968   inline void mov_or_nop( Register s,  Register d) {
  1969     if ( s != d )    or3( G0, s, d);
  1970     else             nop();
  1973   inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); }
  1975   // address pseudos: make these names unlike instruction names to avoid confusion
  1976   inline intptr_t load_pc_address( Register reg, int bytes_to_skip );
  1977   inline void load_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
  1978   inline void load_ptr_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
  1979   inline void store_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0);
  1980   inline void store_ptr_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0);
  1981   inline void jumpl_to(const AddressLiteral& addrlit, Register temp, Register d, int offset = 0);
  1982   inline void jump_to(const AddressLiteral& addrlit, Register temp, int offset = 0);
  1983   inline void jump_indirect_to(Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0);
  1985   // ring buffer traceable jumps
  1987   void jmp2( Register r1, Register r2, const char* file, int line );
  1988   void jmp ( Register r1, int offset,  const char* file, int line );
  1990   void jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line);
  1991   void jump (const AddressLiteral& addrlit, Register temp,             int offset, const char* file, int line);
  1994   // argument pseudos:
  1996   inline void load_argument( Argument& a, Register  d );
  1997   inline void store_argument( Register s, Argument& a );
  1998   inline void store_ptr_argument( Register s, Argument& a );
  1999   inline void store_float_argument( FloatRegister s, Argument& a );
  2000   inline void store_double_argument( FloatRegister s, Argument& a );
  2001   inline void store_long_argument( Register s, Argument& a );
  2003   // handy macros:
  2005   inline void round_to( Register r, int modulus ) {
  2006     assert_not_delayed();
  2007     inc( r, modulus - 1 );
  2008     and3( r, -modulus, r );
  2011   // --------------------------------------------------
  2013   // Functions for isolating 64 bit loads for LP64
  2014   // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's
  2015   // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's
  2016   inline void ld_ptr(Register s1, Register s2, Register d);
  2017   inline void ld_ptr(Register s1, int simm13a, Register d);
  2018   inline void ld_ptr(Register s1, RegisterOrConstant s2, Register d);
  2019   inline void ld_ptr(const Address& a, Register d, int offset = 0);
  2020   inline void st_ptr(Register d, Register s1, Register s2);
  2021   inline void st_ptr(Register d, Register s1, int simm13a);
  2022   inline void st_ptr(Register d, Register s1, RegisterOrConstant s2);
  2023   inline void st_ptr(Register d, const Address& a, int offset = 0);
  2025 #ifdef ASSERT
  2026   // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
  2027   inline void ld_ptr(Register s1, ByteSize simm13a, Register d);
  2028   inline void st_ptr(Register d, Register s1, ByteSize simm13a);
  2029 #endif
  2031   // ld_long will perform ldd for 32 bit VM's and ldx for 64 bit VM's
  2032   // st_long will perform std for 32 bit VM's and stx for 64 bit VM's
  2033   inline void ld_long(Register s1, Register s2, Register d);
  2034   inline void ld_long(Register s1, int simm13a, Register d);
  2035   inline void ld_long(Register s1, RegisterOrConstant s2, Register d);
  2036   inline void ld_long(const Address& a, Register d, int offset = 0);
  2037   inline void st_long(Register d, Register s1, Register s2);
  2038   inline void st_long(Register d, Register s1, int simm13a);
  2039   inline void st_long(Register d, Register s1, RegisterOrConstant s2);
  2040   inline void st_long(Register d, const Address& a, int offset = 0);
  2042   // Helpers for address formation.
  2043   // - They emit only a move if s2 is a constant zero.
  2044   // - If dest is a constant and either s1 or s2 is a register, the temp argument is required and becomes the result.
  2045   // - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant.
  2046   RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
  2047   RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
  2048   RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
  2050   RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) {
  2051     if (is_simm13(src.constant_or_zero()))
  2052       return src;               // register or short constant
  2053     guarantee(temp != noreg, "constant offset overflow");
  2054     set(src.as_constant(), temp);
  2055     return temp;
  2058   // --------------------------------------------------
  2060  public:
  2061   // traps as per trap.h (SPARC ABI?)
  2063   void breakpoint_trap();
  2064   void breakpoint_trap(Condition c, CC cc = icc);
  2065   void flush_windows_trap();
  2066   void clean_windows_trap();
  2067   void get_psr_trap();
  2068   void set_psr_trap();
  2070   // V8/V9 flush_windows
  2071   void flush_windows();
  2073   // Support for serializing memory accesses between threads
  2074   void serialize_memory(Register thread, Register tmp1, Register tmp2);
  2076   // Stack frame creation/removal
  2077   void enter();
  2078   void leave();
  2080   // V8/V9 integer multiply
  2081   void mult(Register s1, Register s2, Register d);
  2082   void mult(Register s1, int simm13a, Register d);
  2084   // V8/V9 read and write of condition codes.
  2085   void read_ccr(Register d);
  2086   void write_ccr(Register s);
  2088   // Manipulation of C++ bools
  2089   // These are idioms to flag the need for care with accessing bools but on
  2090   // this platform we assume byte size
  2092   inline void stbool(Register d, const Address& a) { stb(d, a); }
  2093   inline void ldbool(const Address& a, Register d) { ldsb(a, d); }
  2094   inline void tstbool( Register s ) { tst(s); }
  2095   inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); }
  2097   // klass oop manipulations if compressed
  2098   void load_klass(Register src_oop, Register klass);
  2099   void store_klass(Register klass, Register dst_oop);
  2100   void store_klass_gap(Register s, Register dst_oop);
  2102    // oop manipulations
  2103   void load_heap_oop(const Address& s, Register d);
  2104   void load_heap_oop(Register s1, Register s2, Register d);
  2105   void load_heap_oop(Register s1, int simm13a, Register d);
  2106   void store_heap_oop(Register d, Register s1, Register s2);
  2107   void store_heap_oop(Register d, Register s1, int simm13a);
  2108   void store_heap_oop(Register d, const Address& a, int offset = 0);
  2110   void encode_heap_oop(Register src, Register dst);
  2111   void encode_heap_oop(Register r) {
  2112     encode_heap_oop(r, r);
  2114   void decode_heap_oop(Register src, Register dst);
  2115   void decode_heap_oop(Register r) {
  2116     decode_heap_oop(r, r);
  2118   void encode_heap_oop_not_null(Register r);
  2119   void decode_heap_oop_not_null(Register r);
  2120   void encode_heap_oop_not_null(Register src, Register dst);
  2121   void decode_heap_oop_not_null(Register src, Register dst);
  2123   // Support for managing the JavaThread pointer (i.e.; the reference to
  2124   // thread-local information).
  2125   void get_thread();                                // load G2_thread
  2126   void verify_thread();                             // verify G2_thread contents
  2127   void save_thread   (const Register threache); // save to cache
  2128   void restore_thread(const Register thread_cache); // restore from cache
  2130   // Support for last Java frame (but use call_VM instead where possible)
  2131   void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
  2132   void reset_last_Java_frame(void);
  2134   // Call into the VM.
  2135   // Passes the thread pointer (in O0) as a prepended argument.
  2136   // Makes sure oop return values are visible to the GC.
  2137   void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
  2138   void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
  2139   void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
  2140   void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
  2142   // these overloadings are not presently used on SPARC:
  2143   void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
  2144   void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
  2145   void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
  2146   void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
  2148   void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0);
  2149   void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1);
  2150   void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2);
  2151   void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3);
  2153   void get_vm_result  (Register oop_result);
  2154   void get_vm_result_2(Register oop_result);
  2156   // vm result is currently getting hijacked to for oop preservation
  2157   void set_vm_result(Register oop_result);
  2159   // if call_VM_base was called with check_exceptions=false, then call
  2160   // check_and_forward_exception to handle exceptions when it is safe
  2161   void check_and_forward_exception(Register scratch_reg);
  2163  private:
  2164   // For V8
  2165   void read_ccr_trap(Register ccr_save);
  2166   void write_ccr_trap(Register ccr_save1, Register scratch1, Register scratch2);
  2168 #ifdef ASSERT
  2169   // For V8 debugging.  Uses V8 instruction sequence and checks
  2170   // result with V9 insturctions rdccr and wrccr.
  2171   // Uses Gscatch and Gscatch2
  2172   void read_ccr_v8_assert(Register ccr_save);
  2173   void write_ccr_v8_assert(Register ccr_save);
  2174 #endif // ASSERT
  2176  public:
  2178   // Write to card table for - register is destroyed afterwards.
  2179   void card_table_write(jbyte* byte_map_base, Register tmp, Register obj);
  2181   void card_write_barrier_post(Register store_addr, Register new_val, Register tmp);
  2183 #ifndef SERIALGC
  2184   // Array store and offset
  2185   void g1_write_barrier_pre(Register obj, Register index, int offset, Register tmp, bool preserve_o_regs);
  2187   void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp);
  2189   // May do filtering, depending on the boolean arguments.
  2190   void g1_card_table_write(jbyte* byte_map_base,
  2191                            Register tmp, Register obj, Register new_val,
  2192                            bool region_filter, bool null_filter);
  2193 #endif // SERIALGC
  2195   // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
  2196   void push_fTOS();
  2198   // pops double TOS element from CPU stack and pushes on FPU stack
  2199   void pop_fTOS();
  2201   void empty_FPU_stack();
  2203   void push_IU_state();
  2204   void pop_IU_state();
  2206   void push_FPU_state();
  2207   void pop_FPU_state();
  2209   void push_CPU_state();
  2210   void pop_CPU_state();
  2212   // if heap base register is used - reinit it with the correct value
  2213   void reinit_heapbase();
  2215   // Debugging
  2216   void _verify_oop(Register reg, const char * msg, const char * file, int line);
  2217   void _verify_oop_addr(Address addr, const char * msg, const char * file, int line);
  2219 #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__)
  2220 #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__)
  2222         // only if +VerifyOops
  2223   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
  2224         // only if +VerifyFPU
  2225   void stop(const char* msg);                          // prints msg, dumps registers and stops execution
  2226   void warn(const char* msg);                          // prints msg, but don't stop
  2227   void untested(const char* what = "");
  2228   void unimplemented(const char* what = "")              { char* b = new char[1024];  sprintf(b, "unimplemented: %s", what);  stop(b); }
  2229   void should_not_reach_here()                   { stop("should not reach here"); }
  2230   void print_CPU_state();
  2232   // oops in code
  2233   AddressLiteral allocate_oop_address(jobject obj);                          // allocate_index
  2234   AddressLiteral constant_oop_address(jobject obj);                          // find_index
  2235   inline void    set_oop             (jobject obj, Register d);              // uses allocate_oop_address
  2236   inline void    set_oop_constant    (jobject obj, Register d);              // uses constant_oop_address
  2237   inline void    set_oop             (const AddressLiteral& obj_addr, Register d); // same as load_address
  2239   void set_narrow_oop( jobject obj, Register d );
  2241   // nop padding
  2242   void align(int modulus);
  2244   // declare a safepoint
  2245   void safepoint();
  2247   // factor out part of stop into subroutine to save space
  2248   void stop_subroutine();
  2249   // factor out part of verify_oop into subroutine to save space
  2250   void verify_oop_subroutine();
  2252   // side-door communication with signalHandler in os_solaris.cpp
  2253   static address _verify_oop_implicit_branch[3];
  2255 #ifndef PRODUCT
  2256   static void test();
  2257 #endif
  2259   // convert an incoming arglist to varargs format; put the pointer in d
  2260   void set_varargs( Argument a, Register d );
  2262   int total_frame_size_in_bytes(int extraWords);
  2264   // used when extraWords known statically
  2265   void save_frame(int extraWords);
  2266   void save_frame_c1(int size_in_bytes);
  2267   // make a frame, and simultaneously pass up one or two register value
  2268   // into the new register window
  2269   void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register());
  2271   // give no. (outgoing) params, calc # of words will need on frame
  2272   void calc_mem_param_words(Register Rparam_words, Register Rresult);
  2274   // used to calculate frame size dynamically
  2275   // result is in bytes and must be negated for save inst
  2276   void calc_frame_size(Register extraWords, Register resultReg);
  2278   // calc and also save
  2279   void calc_frame_size_and_save(Register extraWords, Register resultReg);
  2281   static void debug(char* msg, RegistersForDebugging* outWindow);
  2283   // implementations of bytecodes used by both interpreter and compiler
  2285   void lcmp( Register Ra_hi, Register Ra_low,
  2286              Register Rb_hi, Register Rb_low,
  2287              Register Rresult);
  2289   void lneg( Register Rhi, Register Rlow );
  2291   void lshl(  Register Rin_high,  Register Rin_low,  Register Rcount,
  2292               Register Rout_high, Register Rout_low, Register Rtemp );
  2294   void lshr(  Register Rin_high,  Register Rin_low,  Register Rcount,
  2295               Register Rout_high, Register Rout_low, Register Rtemp );
  2297   void lushr( Register Rin_high,  Register Rin_low,  Register Rcount,
  2298               Register Rout_high, Register Rout_low, Register Rtemp );
  2300 #ifdef _LP64
  2301   void lcmp( Register Ra, Register Rb, Register Rresult);
  2302 #endif
  2304   // Loading values by size and signed-ness
  2305   void load_sized_value(Address src, Register dst, size_t size_in_bytes, bool is_signed);
  2307   void float_cmp( bool is_float, int unordered_result,
  2308                   FloatRegister Fa, FloatRegister Fb,
  2309                   Register Rresult);
  2311   void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
  2312   void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { Assembler::fneg(w, sd); }
  2313   void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
  2314   void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
  2316   void save_all_globals_into_locals();
  2317   void restore_globals_from_locals();
  2319   void casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
  2320     address lock_addr=0, bool use_call_vm=false);
  2321   void cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
  2322     address lock_addr=0, bool use_call_vm=false);
  2323   void casn (Register addr_reg, Register cmp_reg, Register set_reg) ;
  2325   // These set the icc condition code to equal if the lock succeeded
  2326   // and notEqual if it failed and requires a slow case
  2327   void compiler_lock_object(Register Roop, Register Rmark, Register Rbox,
  2328                             Register Rscratch,
  2329                             BiasedLockingCounters* counters = NULL,
  2330                             bool try_bias = UseBiasedLocking);
  2331   void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox,
  2332                               Register Rscratch,
  2333                               bool try_bias = UseBiasedLocking);
  2335   // Biased locking support
  2336   // Upon entry, lock_reg must point to the lock record on the stack,
  2337   // obj_reg must contain the target object, and mark_reg must contain
  2338   // the target object's header.
  2339   // Destroys mark_reg if an attempt is made to bias an anonymously
  2340   // biased lock. In this case a failure will go either to the slow
  2341   // case or fall through with the notEqual condition code set with
  2342   // the expectation that the slow case in the runtime will be called.
  2343   // In the fall-through case where the CAS-based lock is done,
  2344   // mark_reg is not destroyed.
  2345   void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg,
  2346                             Label& done, Label* slow_case = NULL,
  2347                             BiasedLockingCounters* counters = NULL);
  2348   // Upon entry, the base register of mark_addr must contain the oop.
  2349   // Destroys temp_reg.
  2351   // If allow_delay_slot_filling is set to true, the next instruction
  2352   // emitted after this one will go in an annulled delay slot if the
  2353   // biased locking exit case failed.
  2354   void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false);
  2356   // allocation
  2357   void eden_allocate(
  2358     Register obj,                      // result: pointer to object after successful allocation
  2359     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
  2360     int      con_size_in_bytes,        // object size in bytes if   known at compile time
  2361     Register t1,                       // temp register
  2362     Register t2,                       // temp register
  2363     Label&   slow_case                 // continuation point if fast allocation fails
  2364   );
  2365   void tlab_allocate(
  2366     Register obj,                      // result: pointer to object after successful allocation
  2367     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
  2368     int      con_size_in_bytes,        // object size in bytes if   known at compile time
  2369     Register t1,                       // temp register
  2370     Label&   slow_case                 // continuation point if fast allocation fails
  2371   );
  2372   void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
  2374   // interface method calling
  2375   void lookup_interface_method(Register recv_klass,
  2376                                Register intf_klass,
  2377                                RegisterOrConstant itable_index,
  2378                                Register method_result,
  2379                                Register temp_reg, Register temp2_reg,
  2380                                Label& no_such_interface);
  2382   // Test sub_klass against super_klass, with fast and slow paths.
  2384   // The fast path produces a tri-state answer: yes / no / maybe-slow.
  2385   // One of the three labels can be NULL, meaning take the fall-through.
  2386   // If super_check_offset is -1, the value is loaded up from super_klass.
  2387   // No registers are killed, except temp_reg and temp2_reg.
  2388   // If super_check_offset is not -1, temp2_reg is not used and can be noreg.
  2389   void check_klass_subtype_fast_path(Register sub_klass,
  2390                                      Register super_klass,
  2391                                      Register temp_reg,
  2392                                      Register temp2_reg,
  2393                                      Label* L_success,
  2394                                      Label* L_failure,
  2395                                      Label* L_slow_path,
  2396                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1),
  2397                 Register instanceof_hack = noreg);
  2399   // The rest of the type check; must be wired to a corresponding fast path.
  2400   // It does not repeat the fast path logic, so don't use it standalone.
  2401   // The temp_reg can be noreg, if no temps are available.
  2402   // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
  2403   // Updates the sub's secondary super cache as necessary.
  2404   void check_klass_subtype_slow_path(Register sub_klass,
  2405                                      Register super_klass,
  2406                                      Register temp_reg,
  2407                                      Register temp2_reg,
  2408                                      Register temp3_reg,
  2409                                      Register temp4_reg,
  2410                                      Label* L_success,
  2411                                      Label* L_failure);
  2413   // Simplified, combined version, good for typical uses.
  2414   // Falls through on failure.
  2415   void check_klass_subtype(Register sub_klass,
  2416                            Register super_klass,
  2417                            Register temp_reg,
  2418                            Register temp2_reg,
  2419                            Label& L_success);
  2421   // method handles (JSR 292)
  2422   void check_method_handle_type(Register mtype_reg, Register mh_reg,
  2423                                 Register temp_reg,
  2424                                 Label& wrong_method_type);
  2425   void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
  2426                                   Register temp_reg);
  2427   void jump_to_method_handle_entry(Register mh_reg, Register temp_reg, bool emit_delayed_nop = true);
  2428   // offset relative to Gargs of argument at tos[arg_slot].
  2429   // (arg_slot == 0 means the last argument, not the first).
  2430   RegisterOrConstant argument_offset(RegisterOrConstant arg_slot,
  2431                                      int extra_slot_offset = 0);
  2432   // Address of Gargs and argument_offset.
  2433   Address            argument_address(RegisterOrConstant arg_slot,
  2434                                       int extra_slot_offset = 0);
  2436   // Stack overflow checking
  2438   // Note: this clobbers G3_scratch
  2439   void bang_stack_with_offset(int offset) {
  2440     // stack grows down, caller passes positive offset
  2441     assert(offset > 0, "must bang with negative offset");
  2442     set((-offset)+STACK_BIAS, G3_scratch);
  2443     st(G0, SP, G3_scratch);
  2446   // Writes to stack successive pages until offset reached to check for
  2447   // stack overflow + shadow pages.  Clobbers tsp and scratch registers.
  2448   void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch);
  2450   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset);
  2452   void verify_tlab();
  2454   Condition negate_condition(Condition cond);
  2456   // Helper functions for statistics gathering.
  2457   // Conditionally (non-atomically) increments passed counter address, preserving condition codes.
  2458   void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2);
  2459   // Unconditional increment.
  2460   void inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2);
  2461   void inc_counter(int*    counter_addr, Register Rtmp1, Register Rtmp2);
  2463   // Compare char[] arrays aligned to 4 bytes.
  2464   void char_arrays_equals(Register ary1, Register ary2,
  2465                           Register limit, Register result,
  2466                           Register chr1, Register chr2, Label& Ldone);
  2468 #undef VIRTUAL
  2470 };
  2472 /**
  2473  * class SkipIfEqual:
  2475  * Instantiating this class will result in assembly code being output that will
  2476  * jump around any code emitted between the creation of the instance and it's
  2477  * automatic destruction at the end of a scope block, depending on the value of
  2478  * the flag passed to the constructor, which will be checked at run-time.
  2479  */
  2480 class SkipIfEqual : public StackObj {
  2481  private:
  2482   MacroAssembler* _masm;
  2483   Label _label;
  2485  public:
  2486    // 'temp' is a temp register that this object can use (and trash)
  2487    SkipIfEqual(MacroAssembler*, Register temp,
  2488                const bool* flag_addr, Assembler::Condition condition);
  2489    ~SkipIfEqual();
  2490 };
  2492 #ifdef ASSERT
  2493 // On RISC, there's no benefit to verifying instruction boundaries.
  2494 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
  2495 #endif

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