Thu, 05 Mar 2009 22:07:29 -0500
Merge
1 /*
2 * Copyright 2003-2008 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
25 #include "incls/_precompiled.incl"
26 #include "incls/_sharedRuntime_x86_64.cpp.incl"
28 DeoptimizationBlob *SharedRuntime::_deopt_blob;
29 #ifdef COMPILER2
30 UncommonTrapBlob *SharedRuntime::_uncommon_trap_blob;
31 ExceptionBlob *OptoRuntime::_exception_blob;
32 #endif // COMPILER2
34 SafepointBlob *SharedRuntime::_polling_page_safepoint_handler_blob;
35 SafepointBlob *SharedRuntime::_polling_page_return_handler_blob;
36 RuntimeStub* SharedRuntime::_wrong_method_blob;
37 RuntimeStub* SharedRuntime::_ic_miss_blob;
38 RuntimeStub* SharedRuntime::_resolve_opt_virtual_call_blob;
39 RuntimeStub* SharedRuntime::_resolve_virtual_call_blob;
40 RuntimeStub* SharedRuntime::_resolve_static_call_blob;
42 const int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size;
44 #define __ masm->
46 class SimpleRuntimeFrame {
48 public:
50 // Most of the runtime stubs have this simple frame layout.
51 // This class exists to make the layout shared in one place.
52 // Offsets are for compiler stack slots, which are jints.
53 enum layout {
54 // The frame sender code expects that rbp will be in the "natural" place and
55 // will override any oopMap setting for it. We must therefore force the layout
56 // so that it agrees with the frame sender code.
57 rbp_off = frame::arg_reg_save_area_bytes/BytesPerInt,
58 rbp_off2,
59 return_off, return_off2,
60 framesize
61 };
62 };
64 class RegisterSaver {
65 // Capture info about frame layout. Layout offsets are in jint
66 // units because compiler frame slots are jints.
67 #define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off
68 enum layout {
69 fpu_state_off = frame::arg_reg_save_area_bytes/BytesPerInt, // fxsave save area
70 xmm_off = fpu_state_off + 160/BytesPerInt, // offset in fxsave save area
71 DEF_XMM_OFFS(0),
72 DEF_XMM_OFFS(1),
73 DEF_XMM_OFFS(2),
74 DEF_XMM_OFFS(3),
75 DEF_XMM_OFFS(4),
76 DEF_XMM_OFFS(5),
77 DEF_XMM_OFFS(6),
78 DEF_XMM_OFFS(7),
79 DEF_XMM_OFFS(8),
80 DEF_XMM_OFFS(9),
81 DEF_XMM_OFFS(10),
82 DEF_XMM_OFFS(11),
83 DEF_XMM_OFFS(12),
84 DEF_XMM_OFFS(13),
85 DEF_XMM_OFFS(14),
86 DEF_XMM_OFFS(15),
87 fpu_state_end = fpu_state_off + ((FPUStateSizeInWords-1)*wordSize / BytesPerInt),
88 fpu_stateH_end,
89 r15_off, r15H_off,
90 r14_off, r14H_off,
91 r13_off, r13H_off,
92 r12_off, r12H_off,
93 r11_off, r11H_off,
94 r10_off, r10H_off,
95 r9_off, r9H_off,
96 r8_off, r8H_off,
97 rdi_off, rdiH_off,
98 rsi_off, rsiH_off,
99 ignore_off, ignoreH_off, // extra copy of rbp
100 rsp_off, rspH_off,
101 rbx_off, rbxH_off,
102 rdx_off, rdxH_off,
103 rcx_off, rcxH_off,
104 rax_off, raxH_off,
105 // 16-byte stack alignment fill word: see MacroAssembler::push/pop_IU_state
106 align_off, alignH_off,
107 flags_off, flagsH_off,
108 // The frame sender code expects that rbp will be in the "natural" place and
109 // will override any oopMap setting for it. We must therefore force the layout
110 // so that it agrees with the frame sender code.
111 rbp_off, rbpH_off, // copy of rbp we will restore
112 return_off, returnH_off, // slot for return address
113 reg_save_size // size in compiler stack slots
114 };
116 public:
117 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);
118 static void restore_live_registers(MacroAssembler* masm);
120 // Offsets into the register save area
121 // Used by deoptimization when it is managing result register
122 // values on its own
124 static int rax_offset_in_bytes(void) { return BytesPerInt * rax_off; }
125 static int rdx_offset_in_bytes(void) { return BytesPerInt * rdx_off; }
126 static int rbx_offset_in_bytes(void) { return BytesPerInt * rbx_off; }
127 static int xmm0_offset_in_bytes(void) { return BytesPerInt * xmm0_off; }
128 static int return_offset_in_bytes(void) { return BytesPerInt * return_off; }
130 // During deoptimization only the result registers need to be restored,
131 // all the other values have already been extracted.
132 static void restore_result_registers(MacroAssembler* masm);
133 };
135 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) {
137 // Always make the frame size 16-byte aligned
138 int frame_size_in_bytes = round_to(additional_frame_words*wordSize +
139 reg_save_size*BytesPerInt, 16);
140 // OopMap frame size is in compiler stack slots (jint's) not bytes or words
141 int frame_size_in_slots = frame_size_in_bytes / BytesPerInt;
142 // The caller will allocate additional_frame_words
143 int additional_frame_slots = additional_frame_words*wordSize / BytesPerInt;
144 // CodeBlob frame size is in words.
145 int frame_size_in_words = frame_size_in_bytes / wordSize;
146 *total_frame_words = frame_size_in_words;
148 // Save registers, fpu state, and flags.
149 // We assume caller has already pushed the return address onto the
150 // stack, so rsp is 8-byte aligned here.
151 // We push rpb twice in this sequence because we want the real rbp
152 // to be under the return like a normal enter.
154 __ enter(); // rsp becomes 16-byte aligned here
155 __ push_CPU_state(); // Push a multiple of 16 bytes
156 if (frame::arg_reg_save_area_bytes != 0) {
157 // Allocate argument register save area
158 __ subptr(rsp, frame::arg_reg_save_area_bytes);
159 }
161 // Set an oopmap for the call site. This oopmap will map all
162 // oop-registers and debug-info registers as callee-saved. This
163 // will allow deoptimization at this safepoint to find all possible
164 // debug-info recordings, as well as let GC find all oops.
166 OopMapSet *oop_maps = new OopMapSet();
167 OopMap* map = new OopMap(frame_size_in_slots, 0);
168 map->set_callee_saved(VMRegImpl::stack2reg( rax_off + additional_frame_slots), rax->as_VMReg());
169 map->set_callee_saved(VMRegImpl::stack2reg( rcx_off + additional_frame_slots), rcx->as_VMReg());
170 map->set_callee_saved(VMRegImpl::stack2reg( rdx_off + additional_frame_slots), rdx->as_VMReg());
171 map->set_callee_saved(VMRegImpl::stack2reg( rbx_off + additional_frame_slots), rbx->as_VMReg());
172 // rbp location is known implicitly by the frame sender code, needs no oopmap
173 // and the location where rbp was saved by is ignored
174 map->set_callee_saved(VMRegImpl::stack2reg( rsi_off + additional_frame_slots), rsi->as_VMReg());
175 map->set_callee_saved(VMRegImpl::stack2reg( rdi_off + additional_frame_slots), rdi->as_VMReg());
176 map->set_callee_saved(VMRegImpl::stack2reg( r8_off + additional_frame_slots), r8->as_VMReg());
177 map->set_callee_saved(VMRegImpl::stack2reg( r9_off + additional_frame_slots), r9->as_VMReg());
178 map->set_callee_saved(VMRegImpl::stack2reg( r10_off + additional_frame_slots), r10->as_VMReg());
179 map->set_callee_saved(VMRegImpl::stack2reg( r11_off + additional_frame_slots), r11->as_VMReg());
180 map->set_callee_saved(VMRegImpl::stack2reg( r12_off + additional_frame_slots), r12->as_VMReg());
181 map->set_callee_saved(VMRegImpl::stack2reg( r13_off + additional_frame_slots), r13->as_VMReg());
182 map->set_callee_saved(VMRegImpl::stack2reg( r14_off + additional_frame_slots), r14->as_VMReg());
183 map->set_callee_saved(VMRegImpl::stack2reg( r15_off + additional_frame_slots), r15->as_VMReg());
184 map->set_callee_saved(VMRegImpl::stack2reg(xmm0_off + additional_frame_slots), xmm0->as_VMReg());
185 map->set_callee_saved(VMRegImpl::stack2reg(xmm1_off + additional_frame_slots), xmm1->as_VMReg());
186 map->set_callee_saved(VMRegImpl::stack2reg(xmm2_off + additional_frame_slots), xmm2->as_VMReg());
187 map->set_callee_saved(VMRegImpl::stack2reg(xmm3_off + additional_frame_slots), xmm3->as_VMReg());
188 map->set_callee_saved(VMRegImpl::stack2reg(xmm4_off + additional_frame_slots), xmm4->as_VMReg());
189 map->set_callee_saved(VMRegImpl::stack2reg(xmm5_off + additional_frame_slots), xmm5->as_VMReg());
190 map->set_callee_saved(VMRegImpl::stack2reg(xmm6_off + additional_frame_slots), xmm6->as_VMReg());
191 map->set_callee_saved(VMRegImpl::stack2reg(xmm7_off + additional_frame_slots), xmm7->as_VMReg());
192 map->set_callee_saved(VMRegImpl::stack2reg(xmm8_off + additional_frame_slots), xmm8->as_VMReg());
193 map->set_callee_saved(VMRegImpl::stack2reg(xmm9_off + additional_frame_slots), xmm9->as_VMReg());
194 map->set_callee_saved(VMRegImpl::stack2reg(xmm10_off + additional_frame_slots), xmm10->as_VMReg());
195 map->set_callee_saved(VMRegImpl::stack2reg(xmm11_off + additional_frame_slots), xmm11->as_VMReg());
196 map->set_callee_saved(VMRegImpl::stack2reg(xmm12_off + additional_frame_slots), xmm12->as_VMReg());
197 map->set_callee_saved(VMRegImpl::stack2reg(xmm13_off + additional_frame_slots), xmm13->as_VMReg());
198 map->set_callee_saved(VMRegImpl::stack2reg(xmm14_off + additional_frame_slots), xmm14->as_VMReg());
199 map->set_callee_saved(VMRegImpl::stack2reg(xmm15_off + additional_frame_slots), xmm15->as_VMReg());
201 // %%% These should all be a waste but we'll keep things as they were for now
202 if (true) {
203 map->set_callee_saved(VMRegImpl::stack2reg( raxH_off + additional_frame_slots),
204 rax->as_VMReg()->next());
205 map->set_callee_saved(VMRegImpl::stack2reg( rcxH_off + additional_frame_slots),
206 rcx->as_VMReg()->next());
207 map->set_callee_saved(VMRegImpl::stack2reg( rdxH_off + additional_frame_slots),
208 rdx->as_VMReg()->next());
209 map->set_callee_saved(VMRegImpl::stack2reg( rbxH_off + additional_frame_slots),
210 rbx->as_VMReg()->next());
211 // rbp location is known implicitly by the frame sender code, needs no oopmap
212 map->set_callee_saved(VMRegImpl::stack2reg( rsiH_off + additional_frame_slots),
213 rsi->as_VMReg()->next());
214 map->set_callee_saved(VMRegImpl::stack2reg( rdiH_off + additional_frame_slots),
215 rdi->as_VMReg()->next());
216 map->set_callee_saved(VMRegImpl::stack2reg( r8H_off + additional_frame_slots),
217 r8->as_VMReg()->next());
218 map->set_callee_saved(VMRegImpl::stack2reg( r9H_off + additional_frame_slots),
219 r9->as_VMReg()->next());
220 map->set_callee_saved(VMRegImpl::stack2reg( r10H_off + additional_frame_slots),
221 r10->as_VMReg()->next());
222 map->set_callee_saved(VMRegImpl::stack2reg( r11H_off + additional_frame_slots),
223 r11->as_VMReg()->next());
224 map->set_callee_saved(VMRegImpl::stack2reg( r12H_off + additional_frame_slots),
225 r12->as_VMReg()->next());
226 map->set_callee_saved(VMRegImpl::stack2reg( r13H_off + additional_frame_slots),
227 r13->as_VMReg()->next());
228 map->set_callee_saved(VMRegImpl::stack2reg( r14H_off + additional_frame_slots),
229 r14->as_VMReg()->next());
230 map->set_callee_saved(VMRegImpl::stack2reg( r15H_off + additional_frame_slots),
231 r15->as_VMReg()->next());
232 map->set_callee_saved(VMRegImpl::stack2reg(xmm0H_off + additional_frame_slots),
233 xmm0->as_VMReg()->next());
234 map->set_callee_saved(VMRegImpl::stack2reg(xmm1H_off + additional_frame_slots),
235 xmm1->as_VMReg()->next());
236 map->set_callee_saved(VMRegImpl::stack2reg(xmm2H_off + additional_frame_slots),
237 xmm2->as_VMReg()->next());
238 map->set_callee_saved(VMRegImpl::stack2reg(xmm3H_off + additional_frame_slots),
239 xmm3->as_VMReg()->next());
240 map->set_callee_saved(VMRegImpl::stack2reg(xmm4H_off + additional_frame_slots),
241 xmm4->as_VMReg()->next());
242 map->set_callee_saved(VMRegImpl::stack2reg(xmm5H_off + additional_frame_slots),
243 xmm5->as_VMReg()->next());
244 map->set_callee_saved(VMRegImpl::stack2reg(xmm6H_off + additional_frame_slots),
245 xmm6->as_VMReg()->next());
246 map->set_callee_saved(VMRegImpl::stack2reg(xmm7H_off + additional_frame_slots),
247 xmm7->as_VMReg()->next());
248 map->set_callee_saved(VMRegImpl::stack2reg(xmm8H_off + additional_frame_slots),
249 xmm8->as_VMReg()->next());
250 map->set_callee_saved(VMRegImpl::stack2reg(xmm9H_off + additional_frame_slots),
251 xmm9->as_VMReg()->next());
252 map->set_callee_saved(VMRegImpl::stack2reg(xmm10H_off + additional_frame_slots),
253 xmm10->as_VMReg()->next());
254 map->set_callee_saved(VMRegImpl::stack2reg(xmm11H_off + additional_frame_slots),
255 xmm11->as_VMReg()->next());
256 map->set_callee_saved(VMRegImpl::stack2reg(xmm12H_off + additional_frame_slots),
257 xmm12->as_VMReg()->next());
258 map->set_callee_saved(VMRegImpl::stack2reg(xmm13H_off + additional_frame_slots),
259 xmm13->as_VMReg()->next());
260 map->set_callee_saved(VMRegImpl::stack2reg(xmm14H_off + additional_frame_slots),
261 xmm14->as_VMReg()->next());
262 map->set_callee_saved(VMRegImpl::stack2reg(xmm15H_off + additional_frame_slots),
263 xmm15->as_VMReg()->next());
264 }
266 return map;
267 }
269 void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
270 if (frame::arg_reg_save_area_bytes != 0) {
271 // Pop arg register save area
272 __ addptr(rsp, frame::arg_reg_save_area_bytes);
273 }
274 // Recover CPU state
275 __ pop_CPU_state();
276 // Get the rbp described implicitly by the calling convention (no oopMap)
277 __ pop(rbp);
278 }
280 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
282 // Just restore result register. Only used by deoptimization. By
283 // now any callee save register that needs to be restored to a c2
284 // caller of the deoptee has been extracted into the vframeArray
285 // and will be stuffed into the c2i adapter we create for later
286 // restoration so only result registers need to be restored here.
288 // Restore fp result register
289 __ movdbl(xmm0, Address(rsp, xmm0_offset_in_bytes()));
290 // Restore integer result register
291 __ movptr(rax, Address(rsp, rax_offset_in_bytes()));
292 __ movptr(rdx, Address(rsp, rdx_offset_in_bytes()));
294 // Pop all of the register save are off the stack except the return address
295 __ addptr(rsp, return_offset_in_bytes());
296 }
298 // The java_calling_convention describes stack locations as ideal slots on
299 // a frame with no abi restrictions. Since we must observe abi restrictions
300 // (like the placement of the register window) the slots must be biased by
301 // the following value.
302 static int reg2offset_in(VMReg r) {
303 // Account for saved rbp and return address
304 // This should really be in_preserve_stack_slots
305 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
306 }
308 static int reg2offset_out(VMReg r) {
309 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
310 }
312 // ---------------------------------------------------------------------------
313 // Read the array of BasicTypes from a signature, and compute where the
314 // arguments should go. Values in the VMRegPair regs array refer to 4-byte
315 // quantities. Values less than VMRegImpl::stack0 are registers, those above
316 // refer to 4-byte stack slots. All stack slots are based off of the stack pointer
317 // as framesizes are fixed.
318 // VMRegImpl::stack0 refers to the first slot 0(sp).
319 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
320 // up to RegisterImpl::number_of_registers) are the 64-bit
321 // integer registers.
323 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
324 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
325 // units regardless of build. Of course for i486 there is no 64 bit build
327 // The Java calling convention is a "shifted" version of the C ABI.
328 // By skipping the first C ABI register we can call non-static jni methods
329 // with small numbers of arguments without having to shuffle the arguments
330 // at all. Since we control the java ABI we ought to at least get some
331 // advantage out of it.
333 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
334 VMRegPair *regs,
335 int total_args_passed,
336 int is_outgoing) {
338 // Create the mapping between argument positions and
339 // registers.
340 static const Register INT_ArgReg[Argument::n_int_register_parameters_j] = {
341 j_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4, j_rarg5
342 };
343 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_j] = {
344 j_farg0, j_farg1, j_farg2, j_farg3,
345 j_farg4, j_farg5, j_farg6, j_farg7
346 };
349 uint int_args = 0;
350 uint fp_args = 0;
351 uint stk_args = 0; // inc by 2 each time
353 for (int i = 0; i < total_args_passed; i++) {
354 switch (sig_bt[i]) {
355 case T_BOOLEAN:
356 case T_CHAR:
357 case T_BYTE:
358 case T_SHORT:
359 case T_INT:
360 if (int_args < Argument::n_int_register_parameters_j) {
361 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
362 } else {
363 regs[i].set1(VMRegImpl::stack2reg(stk_args));
364 stk_args += 2;
365 }
366 break;
367 case T_VOID:
368 // halves of T_LONG or T_DOUBLE
369 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
370 regs[i].set_bad();
371 break;
372 case T_LONG:
373 assert(sig_bt[i + 1] == T_VOID, "expecting half");
374 // fall through
375 case T_OBJECT:
376 case T_ARRAY:
377 case T_ADDRESS:
378 if (int_args < Argument::n_int_register_parameters_j) {
379 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
380 } else {
381 regs[i].set2(VMRegImpl::stack2reg(stk_args));
382 stk_args += 2;
383 }
384 break;
385 case T_FLOAT:
386 if (fp_args < Argument::n_float_register_parameters_j) {
387 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
388 } else {
389 regs[i].set1(VMRegImpl::stack2reg(stk_args));
390 stk_args += 2;
391 }
392 break;
393 case T_DOUBLE:
394 assert(sig_bt[i + 1] == T_VOID, "expecting half");
395 if (fp_args < Argument::n_float_register_parameters_j) {
396 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
397 } else {
398 regs[i].set2(VMRegImpl::stack2reg(stk_args));
399 stk_args += 2;
400 }
401 break;
402 default:
403 ShouldNotReachHere();
404 break;
405 }
406 }
408 return round_to(stk_args, 2);
409 }
411 // Patch the callers callsite with entry to compiled code if it exists.
412 static void patch_callers_callsite(MacroAssembler *masm) {
413 Label L;
414 __ verify_oop(rbx);
415 __ cmpptr(Address(rbx, in_bytes(methodOopDesc::code_offset())), (int32_t)NULL_WORD);
416 __ jcc(Assembler::equal, L);
418 // Save the current stack pointer
419 __ mov(r13, rsp);
420 // Schedule the branch target address early.
421 // Call into the VM to patch the caller, then jump to compiled callee
422 // rax isn't live so capture return address while we easily can
423 __ movptr(rax, Address(rsp, 0));
425 // align stack so push_CPU_state doesn't fault
426 __ andptr(rsp, -(StackAlignmentInBytes));
427 __ push_CPU_state();
430 __ verify_oop(rbx);
431 // VM needs caller's callsite
432 // VM needs target method
433 // This needs to be a long call since we will relocate this adapter to
434 // the codeBuffer and it may not reach
436 // Allocate argument register save area
437 if (frame::arg_reg_save_area_bytes != 0) {
438 __ subptr(rsp, frame::arg_reg_save_area_bytes);
439 }
440 __ mov(c_rarg0, rbx);
441 __ mov(c_rarg1, rax);
442 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
444 // De-allocate argument register save area
445 if (frame::arg_reg_save_area_bytes != 0) {
446 __ addptr(rsp, frame::arg_reg_save_area_bytes);
447 }
449 __ pop_CPU_state();
450 // restore sp
451 __ mov(rsp, r13);
452 __ bind(L);
453 }
455 // Helper function to put tags in interpreter stack.
456 static void tag_stack(MacroAssembler *masm, const BasicType sig, int st_off) {
457 if (TaggedStackInterpreter) {
458 int tag_offset = st_off + Interpreter::expr_tag_offset_in_bytes(0);
459 if (sig == T_OBJECT || sig == T_ARRAY) {
460 __ movptr(Address(rsp, tag_offset), (int32_t) frame::TagReference);
461 } else if (sig == T_LONG || sig == T_DOUBLE) {
462 int next_tag_offset = st_off + Interpreter::expr_tag_offset_in_bytes(1);
463 __ movptr(Address(rsp, next_tag_offset), (int32_t) frame::TagValue);
464 __ movptr(Address(rsp, tag_offset), (int32_t) frame::TagValue);
465 } else {
466 __ movptr(Address(rsp, tag_offset), (int32_t) frame::TagValue);
467 }
468 }
469 }
472 static void gen_c2i_adapter(MacroAssembler *masm,
473 int total_args_passed,
474 int comp_args_on_stack,
475 const BasicType *sig_bt,
476 const VMRegPair *regs,
477 Label& skip_fixup) {
478 // Before we get into the guts of the C2I adapter, see if we should be here
479 // at all. We've come from compiled code and are attempting to jump to the
480 // interpreter, which means the caller made a static call to get here
481 // (vcalls always get a compiled target if there is one). Check for a
482 // compiled target. If there is one, we need to patch the caller's call.
483 patch_callers_callsite(masm);
485 __ bind(skip_fixup);
487 // Since all args are passed on the stack, total_args_passed *
488 // Interpreter::stackElementSize is the space we need. Plus 1 because
489 // we also account for the return address location since
490 // we store it first rather than hold it in rax across all the shuffling
492 int extraspace = (total_args_passed * Interpreter::stackElementSize()) + wordSize;
494 // stack is aligned, keep it that way
495 extraspace = round_to(extraspace, 2*wordSize);
497 // Get return address
498 __ pop(rax);
500 // set senderSP value
501 __ mov(r13, rsp);
503 __ subptr(rsp, extraspace);
505 // Store the return address in the expected location
506 __ movptr(Address(rsp, 0), rax);
508 // Now write the args into the outgoing interpreter space
509 for (int i = 0; i < total_args_passed; i++) {
510 if (sig_bt[i] == T_VOID) {
511 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
512 continue;
513 }
515 // offset to start parameters
516 int st_off = (total_args_passed - i) * Interpreter::stackElementSize() +
517 Interpreter::value_offset_in_bytes();
518 int next_off = st_off - Interpreter::stackElementSize();
520 // Say 4 args:
521 // i st_off
522 // 0 32 T_LONG
523 // 1 24 T_VOID
524 // 2 16 T_OBJECT
525 // 3 8 T_BOOL
526 // - 0 return address
527 //
528 // However to make thing extra confusing. Because we can fit a long/double in
529 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
530 // leaves one slot empty and only stores to a single slot. In this case the
531 // slot that is occupied is the T_VOID slot. See I said it was confusing.
533 VMReg r_1 = regs[i].first();
534 VMReg r_2 = regs[i].second();
535 if (!r_1->is_valid()) {
536 assert(!r_2->is_valid(), "");
537 continue;
538 }
539 if (r_1->is_stack()) {
540 // memory to memory use rax
541 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
542 if (!r_2->is_valid()) {
543 // sign extend??
544 __ movl(rax, Address(rsp, ld_off));
545 __ movptr(Address(rsp, st_off), rax);
546 tag_stack(masm, sig_bt[i], st_off);
548 } else {
550 __ movq(rax, Address(rsp, ld_off));
552 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
553 // T_DOUBLE and T_LONG use two slots in the interpreter
554 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
555 // ld_off == LSW, ld_off+wordSize == MSW
556 // st_off == MSW, next_off == LSW
557 __ movq(Address(rsp, next_off), rax);
558 #ifdef ASSERT
559 // Overwrite the unused slot with known junk
560 __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
561 __ movptr(Address(rsp, st_off), rax);
562 #endif /* ASSERT */
563 tag_stack(masm, sig_bt[i], next_off);
564 } else {
565 __ movq(Address(rsp, st_off), rax);
566 tag_stack(masm, sig_bt[i], st_off);
567 }
568 }
569 } else if (r_1->is_Register()) {
570 Register r = r_1->as_Register();
571 if (!r_2->is_valid()) {
572 // must be only an int (or less ) so move only 32bits to slot
573 // why not sign extend??
574 __ movl(Address(rsp, st_off), r);
575 tag_stack(masm, sig_bt[i], st_off);
576 } else {
577 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
578 // T_DOUBLE and T_LONG use two slots in the interpreter
579 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
580 // long/double in gpr
581 #ifdef ASSERT
582 // Overwrite the unused slot with known junk
583 __ mov64(rax, CONST64(0xdeadffffdeadaaab));
584 __ movptr(Address(rsp, st_off), rax);
585 #endif /* ASSERT */
586 __ movq(Address(rsp, next_off), r);
587 tag_stack(masm, sig_bt[i], next_off);
588 } else {
589 __ movptr(Address(rsp, st_off), r);
590 tag_stack(masm, sig_bt[i], st_off);
591 }
592 }
593 } else {
594 assert(r_1->is_XMMRegister(), "");
595 if (!r_2->is_valid()) {
596 // only a float use just part of the slot
597 __ movflt(Address(rsp, st_off), r_1->as_XMMRegister());
598 tag_stack(masm, sig_bt[i], st_off);
599 } else {
600 #ifdef ASSERT
601 // Overwrite the unused slot with known junk
602 __ mov64(rax, CONST64(0xdeadffffdeadaaac));
603 __ movptr(Address(rsp, st_off), rax);
604 #endif /* ASSERT */
605 __ movdbl(Address(rsp, next_off), r_1->as_XMMRegister());
606 tag_stack(masm, sig_bt[i], next_off);
607 }
608 }
609 }
611 // Schedule the branch target address early.
612 __ movptr(rcx, Address(rbx, in_bytes(methodOopDesc::interpreter_entry_offset())));
613 __ jmp(rcx);
614 }
616 static void gen_i2c_adapter(MacroAssembler *masm,
617 int total_args_passed,
618 int comp_args_on_stack,
619 const BasicType *sig_bt,
620 const VMRegPair *regs) {
622 //
623 // We will only enter here from an interpreted frame and never from after
624 // passing thru a c2i. Azul allowed this but we do not. If we lose the
625 // race and use a c2i we will remain interpreted for the race loser(s).
626 // This removes all sorts of headaches on the x86 side and also eliminates
627 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions.
630 // Note: r13 contains the senderSP on entry. We must preserve it since
631 // we may do a i2c -> c2i transition if we lose a race where compiled
632 // code goes non-entrant while we get args ready.
633 // In addition we use r13 to locate all the interpreter args as
634 // we must align the stack to 16 bytes on an i2c entry else we
635 // lose alignment we expect in all compiled code and register
636 // save code can segv when fxsave instructions find improperly
637 // aligned stack pointer.
639 __ movptr(rax, Address(rsp, 0));
641 // Cut-out for having no stack args. Since up to 2 int/oop args are passed
642 // in registers, we will occasionally have no stack args.
643 int comp_words_on_stack = 0;
644 if (comp_args_on_stack) {
645 // Sig words on the stack are greater-than VMRegImpl::stack0. Those in
646 // registers are below. By subtracting stack0, we either get a negative
647 // number (all values in registers) or the maximum stack slot accessed.
649 // Convert 4-byte c2 stack slots to words.
650 comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
651 // Round up to miminum stack alignment, in wordSize
652 comp_words_on_stack = round_to(comp_words_on_stack, 2);
653 __ subptr(rsp, comp_words_on_stack * wordSize);
654 }
657 // Ensure compiled code always sees stack at proper alignment
658 __ andptr(rsp, -16);
660 // push the return address and misalign the stack that youngest frame always sees
661 // as far as the placement of the call instruction
662 __ push(rax);
664 // Will jump to the compiled code just as if compiled code was doing it.
665 // Pre-load the register-jump target early, to schedule it better.
666 __ movptr(r11, Address(rbx, in_bytes(methodOopDesc::from_compiled_offset())));
668 // Now generate the shuffle code. Pick up all register args and move the
669 // rest through the floating point stack top.
670 for (int i = 0; i < total_args_passed; i++) {
671 if (sig_bt[i] == T_VOID) {
672 // Longs and doubles are passed in native word order, but misaligned
673 // in the 32-bit build.
674 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
675 continue;
676 }
678 // Pick up 0, 1 or 2 words from SP+offset.
680 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
681 "scrambled load targets?");
682 // Load in argument order going down.
683 // int ld_off = (total_args_passed + comp_words_on_stack -i)*wordSize;
684 // base ld_off on r13 (sender_sp) as the stack alignment makes offsets from rsp
685 // unpredictable
686 int ld_off = ((total_args_passed - 1) - i)*Interpreter::stackElementSize();
688 // Point to interpreter value (vs. tag)
689 int next_off = ld_off - Interpreter::stackElementSize();
690 //
691 //
692 //
693 VMReg r_1 = regs[i].first();
694 VMReg r_2 = regs[i].second();
695 if (!r_1->is_valid()) {
696 assert(!r_2->is_valid(), "");
697 continue;
698 }
699 if (r_1->is_stack()) {
700 // Convert stack slot to an SP offset (+ wordSize to account for return address )
701 int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
702 if (!r_2->is_valid()) {
703 // sign extend???
704 __ movl(rax, Address(r13, ld_off));
705 __ movptr(Address(rsp, st_off), rax);
706 } else {
707 //
708 // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
709 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
710 // So we must adjust where to pick up the data to match the interpreter.
711 //
712 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
713 // are accessed as negative so LSW is at LOW address
715 // ld_off is MSW so get LSW
716 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
717 next_off : ld_off;
718 __ movq(rax, Address(r13, offset));
719 // st_off is LSW (i.e. reg.first())
720 __ movq(Address(rsp, st_off), rax);
721 }
722 } else if (r_1->is_Register()) { // Register argument
723 Register r = r_1->as_Register();
724 assert(r != rax, "must be different");
725 if (r_2->is_valid()) {
726 //
727 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
728 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
729 // So we must adjust where to pick up the data to match the interpreter.
731 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
732 next_off : ld_off;
734 // this can be a misaligned move
735 __ movq(r, Address(r13, offset));
736 } else {
737 // sign extend and use a full word?
738 __ movl(r, Address(r13, ld_off));
739 }
740 } else {
741 if (!r_2->is_valid()) {
742 __ movflt(r_1->as_XMMRegister(), Address(r13, ld_off));
743 } else {
744 __ movdbl(r_1->as_XMMRegister(), Address(r13, next_off));
745 }
746 }
747 }
749 // 6243940 We might end up in handle_wrong_method if
750 // the callee is deoptimized as we race thru here. If that
751 // happens we don't want to take a safepoint because the
752 // caller frame will look interpreted and arguments are now
753 // "compiled" so it is much better to make this transition
754 // invisible to the stack walking code. Unfortunately if
755 // we try and find the callee by normal means a safepoint
756 // is possible. So we stash the desired callee in the thread
757 // and the vm will find there should this case occur.
759 __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx);
761 // put methodOop where a c2i would expect should we end up there
762 // only needed becaus eof c2 resolve stubs return methodOop as a result in
763 // rax
764 __ mov(rax, rbx);
765 __ jmp(r11);
766 }
768 // ---------------------------------------------------------------
769 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
770 int total_args_passed,
771 int comp_args_on_stack,
772 const BasicType *sig_bt,
773 const VMRegPair *regs) {
774 address i2c_entry = __ pc();
776 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
778 // -------------------------------------------------------------------------
779 // Generate a C2I adapter. On entry we know rbx holds the methodOop during calls
780 // to the interpreter. The args start out packed in the compiled layout. They
781 // need to be unpacked into the interpreter layout. This will almost always
782 // require some stack space. We grow the current (compiled) stack, then repack
783 // the args. We finally end in a jump to the generic interpreter entry point.
784 // On exit from the interpreter, the interpreter will restore our SP (lest the
785 // compiled code, which relys solely on SP and not RBP, get sick).
787 address c2i_unverified_entry = __ pc();
788 Label skip_fixup;
789 Label ok;
791 Register holder = rax;
792 Register receiver = j_rarg0;
793 Register temp = rbx;
795 {
796 __ verify_oop(holder);
797 __ load_klass(temp, receiver);
798 __ verify_oop(temp);
800 __ cmpptr(temp, Address(holder, compiledICHolderOopDesc::holder_klass_offset()));
801 __ movptr(rbx, Address(holder, compiledICHolderOopDesc::holder_method_offset()));
802 __ jcc(Assembler::equal, ok);
803 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
805 __ bind(ok);
806 // Method might have been compiled since the call site was patched to
807 // interpreted if that is the case treat it as a miss so we can get
808 // the call site corrected.
809 __ cmpptr(Address(rbx, in_bytes(methodOopDesc::code_offset())), (int32_t)NULL_WORD);
810 __ jcc(Assembler::equal, skip_fixup);
811 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
812 }
814 address c2i_entry = __ pc();
816 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
818 __ flush();
819 return new AdapterHandlerEntry(i2c_entry, c2i_entry, c2i_unverified_entry);
820 }
822 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
823 VMRegPair *regs,
824 int total_args_passed) {
825 // We return the amount of VMRegImpl stack slots we need to reserve for all
826 // the arguments NOT counting out_preserve_stack_slots.
828 // NOTE: These arrays will have to change when c1 is ported
829 #ifdef _WIN64
830 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
831 c_rarg0, c_rarg1, c_rarg2, c_rarg3
832 };
833 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
834 c_farg0, c_farg1, c_farg2, c_farg3
835 };
836 #else
837 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
838 c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5
839 };
840 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
841 c_farg0, c_farg1, c_farg2, c_farg3,
842 c_farg4, c_farg5, c_farg6, c_farg7
843 };
844 #endif // _WIN64
847 uint int_args = 0;
848 uint fp_args = 0;
849 uint stk_args = 0; // inc by 2 each time
851 for (int i = 0; i < total_args_passed; i++) {
852 switch (sig_bt[i]) {
853 case T_BOOLEAN:
854 case T_CHAR:
855 case T_BYTE:
856 case T_SHORT:
857 case T_INT:
858 if (int_args < Argument::n_int_register_parameters_c) {
859 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
860 #ifdef _WIN64
861 fp_args++;
862 // Allocate slots for callee to stuff register args the stack.
863 stk_args += 2;
864 #endif
865 } else {
866 regs[i].set1(VMRegImpl::stack2reg(stk_args));
867 stk_args += 2;
868 }
869 break;
870 case T_LONG:
871 assert(sig_bt[i + 1] == T_VOID, "expecting half");
872 // fall through
873 case T_OBJECT:
874 case T_ARRAY:
875 case T_ADDRESS:
876 if (int_args < Argument::n_int_register_parameters_c) {
877 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
878 #ifdef _WIN64
879 fp_args++;
880 stk_args += 2;
881 #endif
882 } else {
883 regs[i].set2(VMRegImpl::stack2reg(stk_args));
884 stk_args += 2;
885 }
886 break;
887 case T_FLOAT:
888 if (fp_args < Argument::n_float_register_parameters_c) {
889 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
890 #ifdef _WIN64
891 int_args++;
892 // Allocate slots for callee to stuff register args the stack.
893 stk_args += 2;
894 #endif
895 } else {
896 regs[i].set1(VMRegImpl::stack2reg(stk_args));
897 stk_args += 2;
898 }
899 break;
900 case T_DOUBLE:
901 assert(sig_bt[i + 1] == T_VOID, "expecting half");
902 if (fp_args < Argument::n_float_register_parameters_c) {
903 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
904 #ifdef _WIN64
905 int_args++;
906 // Allocate slots for callee to stuff register args the stack.
907 stk_args += 2;
908 #endif
909 } else {
910 regs[i].set2(VMRegImpl::stack2reg(stk_args));
911 stk_args += 2;
912 }
913 break;
914 case T_VOID: // Halves of longs and doubles
915 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
916 regs[i].set_bad();
917 break;
918 default:
919 ShouldNotReachHere();
920 break;
921 }
922 }
923 #ifdef _WIN64
924 // windows abi requires that we always allocate enough stack space
925 // for 4 64bit registers to be stored down.
926 if (stk_args < 8) {
927 stk_args = 8;
928 }
929 #endif // _WIN64
931 return stk_args;
932 }
934 // On 64 bit we will store integer like items to the stack as
935 // 64 bits items (sparc abi) even though java would only store
936 // 32bits for a parameter. On 32bit it will simply be 32 bits
937 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
938 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
939 if (src.first()->is_stack()) {
940 if (dst.first()->is_stack()) {
941 // stack to stack
942 __ movslq(rax, Address(rbp, reg2offset_in(src.first())));
943 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
944 } else {
945 // stack to reg
946 __ movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
947 }
948 } else if (dst.first()->is_stack()) {
949 // reg to stack
950 // Do we really have to sign extend???
951 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
952 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
953 } else {
954 // Do we really have to sign extend???
955 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
956 if (dst.first() != src.first()) {
957 __ movq(dst.first()->as_Register(), src.first()->as_Register());
958 }
959 }
960 }
963 // An oop arg. Must pass a handle not the oop itself
964 static void object_move(MacroAssembler* masm,
965 OopMap* map,
966 int oop_handle_offset,
967 int framesize_in_slots,
968 VMRegPair src,
969 VMRegPair dst,
970 bool is_receiver,
971 int* receiver_offset) {
973 // must pass a handle. First figure out the location we use as a handle
975 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
977 // See if oop is NULL if it is we need no handle
979 if (src.first()->is_stack()) {
981 // Oop is already on the stack as an argument
982 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
983 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
984 if (is_receiver) {
985 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
986 }
988 __ cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD);
989 __ lea(rHandle, Address(rbp, reg2offset_in(src.first())));
990 // conditionally move a NULL
991 __ cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
992 } else {
994 // Oop is in an a register we must store it to the space we reserve
995 // on the stack for oop_handles and pass a handle if oop is non-NULL
997 const Register rOop = src.first()->as_Register();
998 int oop_slot;
999 if (rOop == j_rarg0)
1000 oop_slot = 0;
1001 else if (rOop == j_rarg1)
1002 oop_slot = 1;
1003 else if (rOop == j_rarg2)
1004 oop_slot = 2;
1005 else if (rOop == j_rarg3)
1006 oop_slot = 3;
1007 else if (rOop == j_rarg4)
1008 oop_slot = 4;
1009 else {
1010 assert(rOop == j_rarg5, "wrong register");
1011 oop_slot = 5;
1012 }
1014 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1015 int offset = oop_slot*VMRegImpl::stack_slot_size;
1017 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1018 // Store oop in handle area, may be NULL
1019 __ movptr(Address(rsp, offset), rOop);
1020 if (is_receiver) {
1021 *receiver_offset = offset;
1022 }
1024 __ cmpptr(rOop, (int32_t)NULL_WORD);
1025 __ lea(rHandle, Address(rsp, offset));
1026 // conditionally move a NULL from the handle area where it was just stored
1027 __ cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1028 }
1030 // If arg is on the stack then place it otherwise it is already in correct reg.
1031 if (dst.first()->is_stack()) {
1032 __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1033 }
1034 }
1036 // A float arg may have to do float reg int reg conversion
1037 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1038 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
1040 // The calling conventions assures us that each VMregpair is either
1041 // all really one physical register or adjacent stack slots.
1042 // This greatly simplifies the cases here compared to sparc.
1044 if (src.first()->is_stack()) {
1045 if (dst.first()->is_stack()) {
1046 __ movl(rax, Address(rbp, reg2offset_in(src.first())));
1047 __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
1048 } else {
1049 // stack to reg
1050 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1051 __ movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first())));
1052 }
1053 } else if (dst.first()->is_stack()) {
1054 // reg to stack
1055 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1056 __ movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1057 } else {
1058 // reg to reg
1059 // In theory these overlap but the ordering is such that this is likely a nop
1060 if ( src.first() != dst.first()) {
1061 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
1062 }
1063 }
1064 }
1066 // A long move
1067 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1069 // The calling conventions assures us that each VMregpair is either
1070 // all really one physical register or adjacent stack slots.
1071 // This greatly simplifies the cases here compared to sparc.
1073 if (src.is_single_phys_reg() ) {
1074 if (dst.is_single_phys_reg()) {
1075 if (dst.first() != src.first()) {
1076 __ mov(dst.first()->as_Register(), src.first()->as_Register());
1077 }
1078 } else {
1079 assert(dst.is_single_reg(), "not a stack pair");
1080 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1081 }
1082 } else if (dst.is_single_phys_reg()) {
1083 assert(src.is_single_reg(), "not a stack pair");
1084 __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first())));
1085 } else {
1086 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
1087 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
1088 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1089 }
1090 }
1092 // A double move
1093 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1095 // The calling conventions assures us that each VMregpair is either
1096 // all really one physical register or adjacent stack slots.
1097 // This greatly simplifies the cases here compared to sparc.
1099 if (src.is_single_phys_reg() ) {
1100 if (dst.is_single_phys_reg()) {
1101 // In theory these overlap but the ordering is such that this is likely a nop
1102 if ( src.first() != dst.first()) {
1103 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
1104 }
1105 } else {
1106 assert(dst.is_single_reg(), "not a stack pair");
1107 __ movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1108 }
1109 } else if (dst.is_single_phys_reg()) {
1110 assert(src.is_single_reg(), "not a stack pair");
1111 __ movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first())));
1112 } else {
1113 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
1114 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
1115 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1116 }
1117 }
1120 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1121 // We always ignore the frame_slots arg and just use the space just below frame pointer
1122 // which by this time is free to use
1123 switch (ret_type) {
1124 case T_FLOAT:
1125 __ movflt(Address(rbp, -wordSize), xmm0);
1126 break;
1127 case T_DOUBLE:
1128 __ movdbl(Address(rbp, -wordSize), xmm0);
1129 break;
1130 case T_VOID: break;
1131 default: {
1132 __ movptr(Address(rbp, -wordSize), rax);
1133 }
1134 }
1135 }
1137 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1138 // We always ignore the frame_slots arg and just use the space just below frame pointer
1139 // which by this time is free to use
1140 switch (ret_type) {
1141 case T_FLOAT:
1142 __ movflt(xmm0, Address(rbp, -wordSize));
1143 break;
1144 case T_DOUBLE:
1145 __ movdbl(xmm0, Address(rbp, -wordSize));
1146 break;
1147 case T_VOID: break;
1148 default: {
1149 __ movptr(rax, Address(rbp, -wordSize));
1150 }
1151 }
1152 }
1154 static void save_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
1155 for ( int i = first_arg ; i < arg_count ; i++ ) {
1156 if (args[i].first()->is_Register()) {
1157 __ push(args[i].first()->as_Register());
1158 } else if (args[i].first()->is_XMMRegister()) {
1159 __ subptr(rsp, 2*wordSize);
1160 __ movdbl(Address(rsp, 0), args[i].first()->as_XMMRegister());
1161 }
1162 }
1163 }
1165 static void restore_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
1166 for ( int i = arg_count - 1 ; i >= first_arg ; i-- ) {
1167 if (args[i].first()->is_Register()) {
1168 __ pop(args[i].first()->as_Register());
1169 } else if (args[i].first()->is_XMMRegister()) {
1170 __ movdbl(args[i].first()->as_XMMRegister(), Address(rsp, 0));
1171 __ addptr(rsp, 2*wordSize);
1172 }
1173 }
1174 }
1176 // ---------------------------------------------------------------------------
1177 // Generate a native wrapper for a given method. The method takes arguments
1178 // in the Java compiled code convention, marshals them to the native
1179 // convention (handlizes oops, etc), transitions to native, makes the call,
1180 // returns to java state (possibly blocking), unhandlizes any result and
1181 // returns.
1182 nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler *masm,
1183 methodHandle method,
1184 int total_in_args,
1185 int comp_args_on_stack,
1186 BasicType *in_sig_bt,
1187 VMRegPair *in_regs,
1188 BasicType ret_type) {
1189 // Native nmethod wrappers never take possesion of the oop arguments.
1190 // So the caller will gc the arguments. The only thing we need an
1191 // oopMap for is if the call is static
1192 //
1193 // An OopMap for lock (and class if static)
1194 OopMapSet *oop_maps = new OopMapSet();
1195 intptr_t start = (intptr_t)__ pc();
1197 // We have received a description of where all the java arg are located
1198 // on entry to the wrapper. We need to convert these args to where
1199 // the jni function will expect them. To figure out where they go
1200 // we convert the java signature to a C signature by inserting
1201 // the hidden arguments as arg[0] and possibly arg[1] (static method)
1203 int total_c_args = total_in_args + 1;
1204 if (method->is_static()) {
1205 total_c_args++;
1206 }
1208 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
1209 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
1211 int argc = 0;
1212 out_sig_bt[argc++] = T_ADDRESS;
1213 if (method->is_static()) {
1214 out_sig_bt[argc++] = T_OBJECT;
1215 }
1217 for (int i = 0; i < total_in_args ; i++ ) {
1218 out_sig_bt[argc++] = in_sig_bt[i];
1219 }
1221 // Now figure out where the args must be stored and how much stack space
1222 // they require.
1223 //
1224 int out_arg_slots;
1225 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
1227 // Compute framesize for the wrapper. We need to handlize all oops in
1228 // incoming registers
1230 // Calculate the total number of stack slots we will need.
1232 // First count the abi requirement plus all of the outgoing args
1233 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
1235 // Now the space for the inbound oop handle area
1237 int oop_handle_offset = stack_slots;
1238 stack_slots += 6*VMRegImpl::slots_per_word;
1240 // Now any space we need for handlizing a klass if static method
1242 int oop_temp_slot_offset = 0;
1243 int klass_slot_offset = 0;
1244 int klass_offset = -1;
1245 int lock_slot_offset = 0;
1246 bool is_static = false;
1248 if (method->is_static()) {
1249 klass_slot_offset = stack_slots;
1250 stack_slots += VMRegImpl::slots_per_word;
1251 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
1252 is_static = true;
1253 }
1255 // Plus a lock if needed
1257 if (method->is_synchronized()) {
1258 lock_slot_offset = stack_slots;
1259 stack_slots += VMRegImpl::slots_per_word;
1260 }
1262 // Now a place (+2) to save return values or temp during shuffling
1263 // + 4 for return address (which we own) and saved rbp
1264 stack_slots += 6;
1266 // Ok The space we have allocated will look like:
1267 //
1268 //
1269 // FP-> | |
1270 // |---------------------|
1271 // | 2 slots for moves |
1272 // |---------------------|
1273 // | lock box (if sync) |
1274 // |---------------------| <- lock_slot_offset
1275 // | klass (if static) |
1276 // |---------------------| <- klass_slot_offset
1277 // | oopHandle area |
1278 // |---------------------| <- oop_handle_offset (6 java arg registers)
1279 // | outbound memory |
1280 // | based arguments |
1281 // | |
1282 // |---------------------|
1283 // | |
1284 // SP-> | out_preserved_slots |
1285 //
1286 //
1289 // Now compute actual number of stack words we need rounding to make
1290 // stack properly aligned.
1291 stack_slots = round_to(stack_slots, StackAlignmentInSlots);
1293 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
1296 // First thing make an ic check to see if we should even be here
1298 // We are free to use all registers as temps without saving them and
1299 // restoring them except rbp. rbp is the only callee save register
1300 // as far as the interpreter and the compiler(s) are concerned.
1303 const Register ic_reg = rax;
1304 const Register receiver = j_rarg0;
1305 const Register tmp = rdx;
1307 Label ok;
1308 Label exception_pending;
1310 __ verify_oop(receiver);
1311 __ push(tmp); // spill (any other registers free here???)
1312 __ load_klass(tmp, receiver);
1313 __ cmpq(ic_reg, tmp);
1314 __ jcc(Assembler::equal, ok);
1316 __ pop(tmp);
1317 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1319 __ bind(ok);
1320 __ pop(tmp);
1322 // Verified entry point must be aligned
1323 __ align(8);
1325 int vep_offset = ((intptr_t)__ pc()) - start;
1327 // The instruction at the verified entry point must be 5 bytes or longer
1328 // because it can be patched on the fly by make_non_entrant. The stack bang
1329 // instruction fits that requirement.
1331 // Generate stack overflow check
1333 if (UseStackBanging) {
1334 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size());
1335 } else {
1336 // need a 5 byte instruction to allow MT safe patching to non-entrant
1337 __ fat_nop();
1338 }
1340 // Generate a new frame for the wrapper.
1341 __ enter();
1342 // -2 because return address is already present and so is saved rbp
1343 __ subptr(rsp, stack_size - 2*wordSize);
1345 // Frame is now completed as far as size and linkage.
1347 int frame_complete = ((intptr_t)__ pc()) - start;
1349 #ifdef ASSERT
1350 {
1351 Label L;
1352 __ mov(rax, rsp);
1353 __ andptr(rax, -16); // must be 16 byte boundary (see amd64 ABI)
1354 __ cmpptr(rax, rsp);
1355 __ jcc(Assembler::equal, L);
1356 __ stop("improperly aligned stack");
1357 __ bind(L);
1358 }
1359 #endif /* ASSERT */
1362 // We use r14 as the oop handle for the receiver/klass
1363 // It is callee save so it survives the call to native
1365 const Register oop_handle_reg = r14;
1369 //
1370 // We immediately shuffle the arguments so that any vm call we have to
1371 // make from here on out (sync slow path, jvmti, etc.) we will have
1372 // captured the oops from our caller and have a valid oopMap for
1373 // them.
1375 // -----------------
1376 // The Grand Shuffle
1378 // The Java calling convention is either equal (linux) or denser (win64) than the
1379 // c calling convention. However the because of the jni_env argument the c calling
1380 // convention always has at least one more (and two for static) arguments than Java.
1381 // Therefore if we move the args from java -> c backwards then we will never have
1382 // a register->register conflict and we don't have to build a dependency graph
1383 // and figure out how to break any cycles.
1384 //
1386 // Record esp-based slot for receiver on stack for non-static methods
1387 int receiver_offset = -1;
1389 // This is a trick. We double the stack slots so we can claim
1390 // the oops in the caller's frame. Since we are sure to have
1391 // more args than the caller doubling is enough to make
1392 // sure we can capture all the incoming oop args from the
1393 // caller.
1394 //
1395 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1397 // Mark location of rbp (someday)
1398 // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, vmreg(rbp));
1400 // Use eax, ebx as temporaries during any memory-memory moves we have to do
1401 // All inbound args are referenced based on rbp and all outbound args via rsp.
1404 #ifdef ASSERT
1405 bool reg_destroyed[RegisterImpl::number_of_registers];
1406 bool freg_destroyed[XMMRegisterImpl::number_of_registers];
1407 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
1408 reg_destroyed[r] = false;
1409 }
1410 for ( int f = 0 ; f < XMMRegisterImpl::number_of_registers ; f++ ) {
1411 freg_destroyed[f] = false;
1412 }
1414 #endif /* ASSERT */
1417 int c_arg = total_c_args - 1;
1418 for ( int i = total_in_args - 1; i >= 0 ; i--, c_arg-- ) {
1419 #ifdef ASSERT
1420 if (in_regs[i].first()->is_Register()) {
1421 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "destroyed reg!");
1422 } else if (in_regs[i].first()->is_XMMRegister()) {
1423 assert(!freg_destroyed[in_regs[i].first()->as_XMMRegister()->encoding()], "destroyed reg!");
1424 }
1425 if (out_regs[c_arg].first()->is_Register()) {
1426 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
1427 } else if (out_regs[c_arg].first()->is_XMMRegister()) {
1428 freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true;
1429 }
1430 #endif /* ASSERT */
1431 switch (in_sig_bt[i]) {
1432 case T_ARRAY:
1433 case T_OBJECT:
1434 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
1435 ((i == 0) && (!is_static)),
1436 &receiver_offset);
1437 break;
1438 case T_VOID:
1439 break;
1441 case T_FLOAT:
1442 float_move(masm, in_regs[i], out_regs[c_arg]);
1443 break;
1445 case T_DOUBLE:
1446 assert( i + 1 < total_in_args &&
1447 in_sig_bt[i + 1] == T_VOID &&
1448 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
1449 double_move(masm, in_regs[i], out_regs[c_arg]);
1450 break;
1452 case T_LONG :
1453 long_move(masm, in_regs[i], out_regs[c_arg]);
1454 break;
1456 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
1458 default:
1459 move32_64(masm, in_regs[i], out_regs[c_arg]);
1460 }
1461 }
1463 // point c_arg at the first arg that is already loaded in case we
1464 // need to spill before we call out
1465 c_arg++;
1467 // Pre-load a static method's oop into r14. Used both by locking code and
1468 // the normal JNI call code.
1469 if (method->is_static()) {
1471 // load oop into a register
1472 __ movoop(oop_handle_reg, JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror()));
1474 // Now handlize the static class mirror it's known not-null.
1475 __ movptr(Address(rsp, klass_offset), oop_handle_reg);
1476 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
1478 // Now get the handle
1479 __ lea(oop_handle_reg, Address(rsp, klass_offset));
1480 // store the klass handle as second argument
1481 __ movptr(c_rarg1, oop_handle_reg);
1482 // and protect the arg if we must spill
1483 c_arg--;
1484 }
1486 // Change state to native (we save the return address in the thread, since it might not
1487 // be pushed on the stack when we do a a stack traversal). It is enough that the pc()
1488 // points into the right code segment. It does not have to be the correct return pc.
1489 // We use the same pc/oopMap repeatedly when we call out
1491 intptr_t the_pc = (intptr_t) __ pc();
1492 oop_maps->add_gc_map(the_pc - start, map);
1494 __ set_last_Java_frame(rsp, noreg, (address)the_pc);
1497 // We have all of the arguments setup at this point. We must not touch any register
1498 // argument registers at this point (what if we save/restore them there are no oop?
1500 {
1501 SkipIfEqual skip(masm, &DTraceMethodProbes, false);
1502 // protect the args we've loaded
1503 save_args(masm, total_c_args, c_arg, out_regs);
1504 __ movoop(c_rarg1, JNIHandles::make_local(method()));
1505 __ call_VM_leaf(
1506 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
1507 r15_thread, c_rarg1);
1508 restore_args(masm, total_c_args, c_arg, out_regs);
1509 }
1511 // RedefineClasses() tracing support for obsolete method entry
1512 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
1513 // protect the args we've loaded
1514 save_args(masm, total_c_args, c_arg, out_regs);
1515 __ movoop(c_rarg1, JNIHandles::make_local(method()));
1516 __ call_VM_leaf(
1517 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
1518 r15_thread, c_rarg1);
1519 restore_args(masm, total_c_args, c_arg, out_regs);
1520 }
1522 // Lock a synchronized method
1524 // Register definitions used by locking and unlocking
1526 const Register swap_reg = rax; // Must use rax for cmpxchg instruction
1527 const Register obj_reg = rbx; // Will contain the oop
1528 const Register lock_reg = r13; // Address of compiler lock object (BasicLock)
1529 const Register old_hdr = r13; // value of old header at unlock time
1531 Label slow_path_lock;
1532 Label lock_done;
1534 if (method->is_synchronized()) {
1537 const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes();
1539 // Get the handle (the 2nd argument)
1540 __ mov(oop_handle_reg, c_rarg1);
1542 // Get address of the box
1544 __ lea(lock_reg, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
1546 // Load the oop from the handle
1547 __ movptr(obj_reg, Address(oop_handle_reg, 0));
1549 if (UseBiasedLocking) {
1550 __ biased_locking_enter(lock_reg, obj_reg, swap_reg, rscratch1, false, lock_done, &slow_path_lock);
1551 }
1553 // Load immediate 1 into swap_reg %rax
1554 __ movl(swap_reg, 1);
1556 // Load (object->mark() | 1) into swap_reg %rax
1557 __ orptr(swap_reg, Address(obj_reg, 0));
1559 // Save (object->mark() | 1) into BasicLock's displaced header
1560 __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
1562 if (os::is_MP()) {
1563 __ lock();
1564 }
1566 // src -> dest iff dest == rax else rax <- dest
1567 __ cmpxchgptr(lock_reg, Address(obj_reg, 0));
1568 __ jcc(Assembler::equal, lock_done);
1570 // Hmm should this move to the slow path code area???
1572 // Test if the oopMark is an obvious stack pointer, i.e.,
1573 // 1) (mark & 3) == 0, and
1574 // 2) rsp <= mark < mark + os::pagesize()
1575 // These 3 tests can be done by evaluating the following
1576 // expression: ((mark - rsp) & (3 - os::vm_page_size())),
1577 // assuming both stack pointer and pagesize have their
1578 // least significant 2 bits clear.
1579 // NOTE: the oopMark is in swap_reg %rax as the result of cmpxchg
1581 __ subptr(swap_reg, rsp);
1582 __ andptr(swap_reg, 3 - os::vm_page_size());
1584 // Save the test result, for recursive case, the result is zero
1585 __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
1586 __ jcc(Assembler::notEqual, slow_path_lock);
1588 // Slow path will re-enter here
1590 __ bind(lock_done);
1591 }
1594 // Finally just about ready to make the JNI call
1597 // get JNIEnv* which is first argument to native
1599 __ lea(c_rarg0, Address(r15_thread, in_bytes(JavaThread::jni_environment_offset())));
1601 // Now set thread in native
1602 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native);
1604 __ call(RuntimeAddress(method->native_function()));
1606 // Either restore the MXCSR register after returning from the JNI Call
1607 // or verify that it wasn't changed.
1608 if (RestoreMXCSROnJNICalls) {
1609 __ ldmxcsr(ExternalAddress(StubRoutines::x86::mxcsr_std()));
1611 }
1612 else if (CheckJNICalls ) {
1613 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::verify_mxcsr_entry())));
1614 }
1617 // Unpack native results.
1618 switch (ret_type) {
1619 case T_BOOLEAN: __ c2bool(rax); break;
1620 case T_CHAR : __ movzwl(rax, rax); break;
1621 case T_BYTE : __ sign_extend_byte (rax); break;
1622 case T_SHORT : __ sign_extend_short(rax); break;
1623 case T_INT : /* nothing to do */ break;
1624 case T_DOUBLE :
1625 case T_FLOAT :
1626 // Result is in xmm0 we'll save as needed
1627 break;
1628 case T_ARRAY: // Really a handle
1629 case T_OBJECT: // Really a handle
1630 break; // can't de-handlize until after safepoint check
1631 case T_VOID: break;
1632 case T_LONG: break;
1633 default : ShouldNotReachHere();
1634 }
1636 // Switch thread to "native transition" state before reading the synchronization state.
1637 // This additional state is necessary because reading and testing the synchronization
1638 // state is not atomic w.r.t. GC, as this scenario demonstrates:
1639 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
1640 // VM thread changes sync state to synchronizing and suspends threads for GC.
1641 // Thread A is resumed to finish this native method, but doesn't block here since it
1642 // didn't see any synchronization is progress, and escapes.
1643 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native_trans);
1645 if(os::is_MP()) {
1646 if (UseMembar) {
1647 // Force this write out before the read below
1648 __ membar(Assembler::Membar_mask_bits(
1649 Assembler::LoadLoad | Assembler::LoadStore |
1650 Assembler::StoreLoad | Assembler::StoreStore));
1651 } else {
1652 // Write serialization page so VM thread can do a pseudo remote membar.
1653 // We use the current thread pointer to calculate a thread specific
1654 // offset to write to within the page. This minimizes bus traffic
1655 // due to cache line collision.
1656 __ serialize_memory(r15_thread, rcx);
1657 }
1658 }
1661 // check for safepoint operation in progress and/or pending suspend requests
1662 {
1663 Label Continue;
1665 __ cmp32(ExternalAddress((address)SafepointSynchronize::address_of_state()),
1666 SafepointSynchronize::_not_synchronized);
1668 Label L;
1669 __ jcc(Assembler::notEqual, L);
1670 __ cmpl(Address(r15_thread, JavaThread::suspend_flags_offset()), 0);
1671 __ jcc(Assembler::equal, Continue);
1672 __ bind(L);
1674 // Don't use call_VM as it will see a possible pending exception and forward it
1675 // and never return here preventing us from clearing _last_native_pc down below.
1676 // Also can't use call_VM_leaf either as it will check to see if rsi & rdi are
1677 // preserved and correspond to the bcp/locals pointers. So we do a runtime call
1678 // by hand.
1679 //
1680 save_native_result(masm, ret_type, stack_slots);
1681 __ mov(c_rarg0, r15_thread);
1682 __ mov(r12, rsp); // remember sp
1683 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
1684 __ andptr(rsp, -16); // align stack as required by ABI
1685 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans)));
1686 __ mov(rsp, r12); // restore sp
1687 __ reinit_heapbase();
1688 // Restore any method result value
1689 restore_native_result(masm, ret_type, stack_slots);
1690 __ bind(Continue);
1691 }
1693 // change thread state
1694 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_Java);
1696 Label reguard;
1697 Label reguard_done;
1698 __ cmpl(Address(r15_thread, JavaThread::stack_guard_state_offset()), JavaThread::stack_guard_yellow_disabled);
1699 __ jcc(Assembler::equal, reguard);
1700 __ bind(reguard_done);
1702 // native result if any is live
1704 // Unlock
1705 Label unlock_done;
1706 Label slow_path_unlock;
1707 if (method->is_synchronized()) {
1709 // Get locked oop from the handle we passed to jni
1710 __ movptr(obj_reg, Address(oop_handle_reg, 0));
1712 Label done;
1714 if (UseBiasedLocking) {
1715 __ biased_locking_exit(obj_reg, old_hdr, done);
1716 }
1718 // Simple recursive lock?
1720 __ cmpptr(Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size), (int32_t)NULL_WORD);
1721 __ jcc(Assembler::equal, done);
1723 // Must save rax if if it is live now because cmpxchg must use it
1724 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
1725 save_native_result(masm, ret_type, stack_slots);
1726 }
1729 // get address of the stack lock
1730 __ lea(rax, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
1731 // get old displaced header
1732 __ movptr(old_hdr, Address(rax, 0));
1734 // Atomic swap old header if oop still contains the stack lock
1735 if (os::is_MP()) {
1736 __ lock();
1737 }
1738 __ cmpxchgptr(old_hdr, Address(obj_reg, 0));
1739 __ jcc(Assembler::notEqual, slow_path_unlock);
1741 // slow path re-enters here
1742 __ bind(unlock_done);
1743 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
1744 restore_native_result(masm, ret_type, stack_slots);
1745 }
1747 __ bind(done);
1749 }
1750 {
1751 SkipIfEqual skip(masm, &DTraceMethodProbes, false);
1752 save_native_result(masm, ret_type, stack_slots);
1753 __ movoop(c_rarg1, JNIHandles::make_local(method()));
1754 __ call_VM_leaf(
1755 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
1756 r15_thread, c_rarg1);
1757 restore_native_result(masm, ret_type, stack_slots);
1758 }
1760 __ reset_last_Java_frame(false, true);
1762 // Unpack oop result
1763 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
1764 Label L;
1765 __ testptr(rax, rax);
1766 __ jcc(Assembler::zero, L);
1767 __ movptr(rax, Address(rax, 0));
1768 __ bind(L);
1769 __ verify_oop(rax);
1770 }
1772 // reset handle block
1773 __ movptr(rcx, Address(r15_thread, JavaThread::active_handles_offset()));
1774 __ movptr(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), (int32_t)NULL_WORD);
1776 // pop our frame
1778 __ leave();
1780 // Any exception pending?
1781 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
1782 __ jcc(Assembler::notEqual, exception_pending);
1784 // Return
1786 __ ret(0);
1788 // Unexpected paths are out of line and go here
1790 // forward the exception
1791 __ bind(exception_pending);
1793 // and forward the exception
1794 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1797 // Slow path locking & unlocking
1798 if (method->is_synchronized()) {
1800 // BEGIN Slow path lock
1801 __ bind(slow_path_lock);
1803 // has last_Java_frame setup. No exceptions so do vanilla call not call_VM
1804 // args are (oop obj, BasicLock* lock, JavaThread* thread)
1806 // protect the args we've loaded
1807 save_args(masm, total_c_args, c_arg, out_regs);
1809 __ mov(c_rarg0, obj_reg);
1810 __ mov(c_rarg1, lock_reg);
1811 __ mov(c_rarg2, r15_thread);
1813 // Not a leaf but we have last_Java_frame setup as we want
1814 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), 3);
1815 restore_args(masm, total_c_args, c_arg, out_regs);
1817 #ifdef ASSERT
1818 { Label L;
1819 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
1820 __ jcc(Assembler::equal, L);
1821 __ stop("no pending exception allowed on exit from monitorenter");
1822 __ bind(L);
1823 }
1824 #endif
1825 __ jmp(lock_done);
1827 // END Slow path lock
1829 // BEGIN Slow path unlock
1830 __ bind(slow_path_unlock);
1832 // If we haven't already saved the native result we must save it now as xmm registers
1833 // are still exposed.
1835 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
1836 save_native_result(masm, ret_type, stack_slots);
1837 }
1839 __ lea(c_rarg1, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
1841 __ mov(c_rarg0, obj_reg);
1842 __ mov(r12, rsp); // remember sp
1843 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
1844 __ andptr(rsp, -16); // align stack as required by ABI
1846 // Save pending exception around call to VM (which contains an EXCEPTION_MARK)
1847 // NOTE that obj_reg == rbx currently
1848 __ movptr(rbx, Address(r15_thread, in_bytes(Thread::pending_exception_offset())));
1849 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
1851 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C)));
1852 __ mov(rsp, r12); // restore sp
1853 __ reinit_heapbase();
1854 #ifdef ASSERT
1855 {
1856 Label L;
1857 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD);
1858 __ jcc(Assembler::equal, L);
1859 __ stop("no pending exception allowed on exit complete_monitor_unlocking_C");
1860 __ bind(L);
1861 }
1862 #endif /* ASSERT */
1864 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), rbx);
1866 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
1867 restore_native_result(masm, ret_type, stack_slots);
1868 }
1869 __ jmp(unlock_done);
1871 // END Slow path unlock
1873 } // synchronized
1875 // SLOW PATH Reguard the stack if needed
1877 __ bind(reguard);
1878 save_native_result(masm, ret_type, stack_slots);
1879 __ mov(r12, rsp); // remember sp
1880 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
1881 __ andptr(rsp, -16); // align stack as required by ABI
1882 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)));
1883 __ mov(rsp, r12); // restore sp
1884 __ reinit_heapbase();
1885 restore_native_result(masm, ret_type, stack_slots);
1886 // and continue
1887 __ jmp(reguard_done);
1891 __ flush();
1893 nmethod *nm = nmethod::new_native_nmethod(method,
1894 masm->code(),
1895 vep_offset,
1896 frame_complete,
1897 stack_slots / VMRegImpl::slots_per_word,
1898 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
1899 in_ByteSize(lock_slot_offset*VMRegImpl::stack_slot_size),
1900 oop_maps);
1901 return nm;
1903 }
1905 #ifdef HAVE_DTRACE_H
1906 // ---------------------------------------------------------------------------
1907 // Generate a dtrace nmethod for a given signature. The method takes arguments
1908 // in the Java compiled code convention, marshals them to the native
1909 // abi and then leaves nops at the position you would expect to call a native
1910 // function. When the probe is enabled the nops are replaced with a trap
1911 // instruction that dtrace inserts and the trace will cause a notification
1912 // to dtrace.
1913 //
1914 // The probes are only able to take primitive types and java/lang/String as
1915 // arguments. No other java types are allowed. Strings are converted to utf8
1916 // strings so that from dtrace point of view java strings are converted to C
1917 // strings. There is an arbitrary fixed limit on the total space that a method
1918 // can use for converting the strings. (256 chars per string in the signature).
1919 // So any java string larger then this is truncated.
1921 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 };
1922 static bool offsets_initialized = false;
1925 nmethod *SharedRuntime::generate_dtrace_nmethod(MacroAssembler *masm,
1926 methodHandle method) {
1929 // generate_dtrace_nmethod is guarded by a mutex so we are sure to
1930 // be single threaded in this method.
1931 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
1933 if (!offsets_initialized) {
1934 fp_offset[c_rarg0->as_VMReg()->value()] = -1 * wordSize;
1935 fp_offset[c_rarg1->as_VMReg()->value()] = -2 * wordSize;
1936 fp_offset[c_rarg2->as_VMReg()->value()] = -3 * wordSize;
1937 fp_offset[c_rarg3->as_VMReg()->value()] = -4 * wordSize;
1938 fp_offset[c_rarg4->as_VMReg()->value()] = -5 * wordSize;
1939 fp_offset[c_rarg5->as_VMReg()->value()] = -6 * wordSize;
1941 fp_offset[c_farg0->as_VMReg()->value()] = -7 * wordSize;
1942 fp_offset[c_farg1->as_VMReg()->value()] = -8 * wordSize;
1943 fp_offset[c_farg2->as_VMReg()->value()] = -9 * wordSize;
1944 fp_offset[c_farg3->as_VMReg()->value()] = -10 * wordSize;
1945 fp_offset[c_farg4->as_VMReg()->value()] = -11 * wordSize;
1946 fp_offset[c_farg5->as_VMReg()->value()] = -12 * wordSize;
1947 fp_offset[c_farg6->as_VMReg()->value()] = -13 * wordSize;
1948 fp_offset[c_farg7->as_VMReg()->value()] = -14 * wordSize;
1950 offsets_initialized = true;
1951 }
1952 // Fill in the signature array, for the calling-convention call.
1953 int total_args_passed = method->size_of_parameters();
1955 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
1956 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
1958 // The signature we are going to use for the trap that dtrace will see
1959 // java/lang/String is converted. We drop "this" and any other object
1960 // is converted to NULL. (A one-slot java/lang/Long object reference
1961 // is converted to a two-slot long, which is why we double the allocation).
1962 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
1963 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
1965 int i=0;
1966 int total_strings = 0;
1967 int first_arg_to_pass = 0;
1968 int total_c_args = 0;
1970 // Skip the receiver as dtrace doesn't want to see it
1971 if( !method->is_static() ) {
1972 in_sig_bt[i++] = T_OBJECT;
1973 first_arg_to_pass = 1;
1974 }
1976 // We need to convert the java args to where a native (non-jni) function
1977 // would expect them. To figure out where they go we convert the java
1978 // signature to a C signature.
1980 SignatureStream ss(method->signature());
1981 for ( ; !ss.at_return_type(); ss.next()) {
1982 BasicType bt = ss.type();
1983 in_sig_bt[i++] = bt; // Collect remaining bits of signature
1984 out_sig_bt[total_c_args++] = bt;
1985 if( bt == T_OBJECT) {
1986 symbolOop s = ss.as_symbol_or_null();
1987 if (s == vmSymbols::java_lang_String()) {
1988 total_strings++;
1989 out_sig_bt[total_c_args-1] = T_ADDRESS;
1990 } else if (s == vmSymbols::java_lang_Boolean() ||
1991 s == vmSymbols::java_lang_Character() ||
1992 s == vmSymbols::java_lang_Byte() ||
1993 s == vmSymbols::java_lang_Short() ||
1994 s == vmSymbols::java_lang_Integer() ||
1995 s == vmSymbols::java_lang_Float()) {
1996 out_sig_bt[total_c_args-1] = T_INT;
1997 } else if (s == vmSymbols::java_lang_Long() ||
1998 s == vmSymbols::java_lang_Double()) {
1999 out_sig_bt[total_c_args-1] = T_LONG;
2000 out_sig_bt[total_c_args++] = T_VOID;
2001 }
2002 } else if ( bt == T_LONG || bt == T_DOUBLE ) {
2003 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
2004 // We convert double to long
2005 out_sig_bt[total_c_args-1] = T_LONG;
2006 out_sig_bt[total_c_args++] = T_VOID;
2007 } else if ( bt == T_FLOAT) {
2008 // We convert float to int
2009 out_sig_bt[total_c_args-1] = T_INT;
2010 }
2011 }
2013 assert(i==total_args_passed, "validly parsed signature");
2015 // Now get the compiled-Java layout as input arguments
2016 int comp_args_on_stack;
2017 comp_args_on_stack = SharedRuntime::java_calling_convention(
2018 in_sig_bt, in_regs, total_args_passed, false);
2020 // Now figure out where the args must be stored and how much stack space
2021 // they require (neglecting out_preserve_stack_slots but space for storing
2022 // the 1st six register arguments). It's weird see int_stk_helper.
2024 int out_arg_slots;
2025 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
2027 // Calculate the total number of stack slots we will need.
2029 // First count the abi requirement plus all of the outgoing args
2030 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
2032 // Now space for the string(s) we must convert
2033 int* string_locs = NEW_RESOURCE_ARRAY(int, total_strings + 1);
2034 for (i = 0; i < total_strings ; i++) {
2035 string_locs[i] = stack_slots;
2036 stack_slots += max_dtrace_string_size / VMRegImpl::stack_slot_size;
2037 }
2039 // Plus the temps we might need to juggle register args
2040 // regs take two slots each
2041 stack_slots += (Argument::n_int_register_parameters_c +
2042 Argument::n_float_register_parameters_c) * 2;
2045 // + 4 for return address (which we own) and saved rbp,
2047 stack_slots += 4;
2049 // Ok The space we have allocated will look like:
2050 //
2051 //
2052 // FP-> | |
2053 // |---------------------|
2054 // | string[n] |
2055 // |---------------------| <- string_locs[n]
2056 // | string[n-1] |
2057 // |---------------------| <- string_locs[n-1]
2058 // | ... |
2059 // | ... |
2060 // |---------------------| <- string_locs[1]
2061 // | string[0] |
2062 // |---------------------| <- string_locs[0]
2063 // | outbound memory |
2064 // | based arguments |
2065 // | |
2066 // |---------------------|
2067 // | |
2068 // SP-> | out_preserved_slots |
2069 //
2070 //
2072 // Now compute actual number of stack words we need rounding to make
2073 // stack properly aligned.
2074 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word);
2076 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
2078 intptr_t start = (intptr_t)__ pc();
2080 // First thing make an ic check to see if we should even be here
2082 // We are free to use all registers as temps without saving them and
2083 // restoring them except rbp. rbp, is the only callee save register
2084 // as far as the interpreter and the compiler(s) are concerned.
2086 const Register ic_reg = rax;
2087 const Register receiver = rcx;
2088 Label hit;
2089 Label exception_pending;
2092 __ verify_oop(receiver);
2093 __ cmpl(ic_reg, Address(receiver, oopDesc::klass_offset_in_bytes()));
2094 __ jcc(Assembler::equal, hit);
2096 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
2098 // verified entry must be aligned for code patching.
2099 // and the first 5 bytes must be in the same cache line
2100 // if we align at 8 then we will be sure 5 bytes are in the same line
2101 __ align(8);
2103 __ bind(hit);
2105 int vep_offset = ((intptr_t)__ pc()) - start;
2108 // The instruction at the verified entry point must be 5 bytes or longer
2109 // because it can be patched on the fly by make_non_entrant. The stack bang
2110 // instruction fits that requirement.
2112 // Generate stack overflow check
2114 if (UseStackBanging) {
2115 if (stack_size <= StackShadowPages*os::vm_page_size()) {
2116 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size());
2117 } else {
2118 __ movl(rax, stack_size);
2119 __ bang_stack_size(rax, rbx);
2120 }
2121 } else {
2122 // need a 5 byte instruction to allow MT safe patching to non-entrant
2123 __ fat_nop();
2124 }
2126 assert(((uintptr_t)__ pc() - start - vep_offset) >= 5,
2127 "valid size for make_non_entrant");
2129 // Generate a new frame for the wrapper.
2130 __ enter();
2132 // -4 because return address is already present and so is saved rbp,
2133 if (stack_size - 2*wordSize != 0) {
2134 __ subq(rsp, stack_size - 2*wordSize);
2135 }
2137 // Frame is now completed as far a size and linkage.
2139 int frame_complete = ((intptr_t)__ pc()) - start;
2141 int c_arg, j_arg;
2143 // State of input register args
2145 bool live[ConcreteRegisterImpl::number_of_registers];
2147 live[j_rarg0->as_VMReg()->value()] = false;
2148 live[j_rarg1->as_VMReg()->value()] = false;
2149 live[j_rarg2->as_VMReg()->value()] = false;
2150 live[j_rarg3->as_VMReg()->value()] = false;
2151 live[j_rarg4->as_VMReg()->value()] = false;
2152 live[j_rarg5->as_VMReg()->value()] = false;
2154 live[j_farg0->as_VMReg()->value()] = false;
2155 live[j_farg1->as_VMReg()->value()] = false;
2156 live[j_farg2->as_VMReg()->value()] = false;
2157 live[j_farg3->as_VMReg()->value()] = false;
2158 live[j_farg4->as_VMReg()->value()] = false;
2159 live[j_farg5->as_VMReg()->value()] = false;
2160 live[j_farg6->as_VMReg()->value()] = false;
2161 live[j_farg7->as_VMReg()->value()] = false;
2164 bool rax_is_zero = false;
2166 // All args (except strings) destined for the stack are moved first
2167 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2168 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2169 VMRegPair src = in_regs[j_arg];
2170 VMRegPair dst = out_regs[c_arg];
2172 // Get the real reg value or a dummy (rsp)
2174 int src_reg = src.first()->is_reg() ?
2175 src.first()->value() :
2176 rsp->as_VMReg()->value();
2178 bool useless = in_sig_bt[j_arg] == T_ARRAY ||
2179 (in_sig_bt[j_arg] == T_OBJECT &&
2180 out_sig_bt[c_arg] != T_INT &&
2181 out_sig_bt[c_arg] != T_ADDRESS &&
2182 out_sig_bt[c_arg] != T_LONG);
2184 live[src_reg] = !useless;
2186 if (dst.first()->is_stack()) {
2188 // Even though a string arg in a register is still live after this loop
2189 // after the string conversion loop (next) it will be dead so we take
2190 // advantage of that now for simpler code to manage live.
2192 live[src_reg] = false;
2193 switch (in_sig_bt[j_arg]) {
2195 case T_ARRAY:
2196 case T_OBJECT:
2197 {
2198 Address stack_dst(rsp, reg2offset_out(dst.first()));
2200 if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
2201 // need to unbox a one-word value
2202 Register in_reg = rax;
2203 if ( src.first()->is_reg() ) {
2204 in_reg = src.first()->as_Register();
2205 } else {
2206 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
2207 rax_is_zero = false;
2208 }
2209 Label skipUnbox;
2210 __ movptr(Address(rsp, reg2offset_out(dst.first())),
2211 (int32_t)NULL_WORD);
2212 __ testq(in_reg, in_reg);
2213 __ jcc(Assembler::zero, skipUnbox);
2215 BasicType bt = out_sig_bt[c_arg];
2216 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
2217 Address src1(in_reg, box_offset);
2218 if ( bt == T_LONG ) {
2219 __ movq(in_reg, src1);
2220 __ movq(stack_dst, in_reg);
2221 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2222 ++c_arg; // skip over T_VOID to keep the loop indices in sync
2223 } else {
2224 __ movl(in_reg, src1);
2225 __ movl(stack_dst, in_reg);
2226 }
2228 __ bind(skipUnbox);
2229 } else if (out_sig_bt[c_arg] != T_ADDRESS) {
2230 // Convert the arg to NULL
2231 if (!rax_is_zero) {
2232 __ xorq(rax, rax);
2233 rax_is_zero = true;
2234 }
2235 __ movq(stack_dst, rax);
2236 }
2237 }
2238 break;
2240 case T_VOID:
2241 break;
2243 case T_FLOAT:
2244 // This does the right thing since we know it is destined for the
2245 // stack
2246 float_move(masm, src, dst);
2247 break;
2249 case T_DOUBLE:
2250 // This does the right thing since we know it is destined for the
2251 // stack
2252 double_move(masm, src, dst);
2253 break;
2255 case T_LONG :
2256 long_move(masm, src, dst);
2257 break;
2259 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2261 default:
2262 move32_64(masm, src, dst);
2263 }
2264 }
2266 }
2268 // If we have any strings we must store any register based arg to the stack
2269 // This includes any still live xmm registers too.
2271 int sid = 0;
2273 if (total_strings > 0 ) {
2274 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2275 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2276 VMRegPair src = in_regs[j_arg];
2277 VMRegPair dst = out_regs[c_arg];
2279 if (src.first()->is_reg()) {
2280 Address src_tmp(rbp, fp_offset[src.first()->value()]);
2282 // string oops were left untouched by the previous loop even if the
2283 // eventual (converted) arg is destined for the stack so park them
2284 // away now (except for first)
2286 if (out_sig_bt[c_arg] == T_ADDRESS) {
2287 Address utf8_addr = Address(
2288 rsp, string_locs[sid++] * VMRegImpl::stack_slot_size);
2289 if (sid != 1) {
2290 // The first string arg won't be killed until after the utf8
2291 // conversion
2292 __ movq(utf8_addr, src.first()->as_Register());
2293 }
2294 } else if (dst.first()->is_reg()) {
2295 if (in_sig_bt[j_arg] == T_FLOAT || in_sig_bt[j_arg] == T_DOUBLE) {
2297 // Convert the xmm register to an int and store it in the reserved
2298 // location for the eventual c register arg
2299 XMMRegister f = src.first()->as_XMMRegister();
2300 if (in_sig_bt[j_arg] == T_FLOAT) {
2301 __ movflt(src_tmp, f);
2302 } else {
2303 __ movdbl(src_tmp, f);
2304 }
2305 } else {
2306 // If the arg is an oop type we don't support don't bother to store
2307 // it remember string was handled above.
2308 bool useless = in_sig_bt[j_arg] == T_ARRAY ||
2309 (in_sig_bt[j_arg] == T_OBJECT &&
2310 out_sig_bt[c_arg] != T_INT &&
2311 out_sig_bt[c_arg] != T_LONG);
2313 if (!useless) {
2314 __ movq(src_tmp, src.first()->as_Register());
2315 }
2316 }
2317 }
2318 }
2319 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
2320 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2321 ++c_arg; // skip over T_VOID to keep the loop indices in sync
2322 }
2323 }
2325 // Now that the volatile registers are safe, convert all the strings
2326 sid = 0;
2328 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2329 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2330 if (out_sig_bt[c_arg] == T_ADDRESS) {
2331 // It's a string
2332 Address utf8_addr = Address(
2333 rsp, string_locs[sid++] * VMRegImpl::stack_slot_size);
2334 // The first string we find might still be in the original java arg
2335 // register
2337 VMReg src = in_regs[j_arg].first();
2339 // We will need to eventually save the final argument to the trap
2340 // in the von-volatile location dedicated to src. This is the offset
2341 // from fp we will use.
2342 int src_off = src->is_reg() ?
2343 fp_offset[src->value()] : reg2offset_in(src);
2345 // This is where the argument will eventually reside
2346 VMRegPair dst = out_regs[c_arg];
2348 if (src->is_reg()) {
2349 if (sid == 1) {
2350 __ movq(c_rarg0, src->as_Register());
2351 } else {
2352 __ movq(c_rarg0, utf8_addr);
2353 }
2354 } else {
2355 // arg is still in the original location
2356 __ movq(c_rarg0, Address(rbp, reg2offset_in(src)));
2357 }
2358 Label done, convert;
2360 // see if the oop is NULL
2361 __ testq(c_rarg0, c_rarg0);
2362 __ jcc(Assembler::notEqual, convert);
2364 if (dst.first()->is_reg()) {
2365 // Save the ptr to utf string in the origina src loc or the tmp
2366 // dedicated to it
2367 __ movq(Address(rbp, src_off), c_rarg0);
2368 } else {
2369 __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg0);
2370 }
2371 __ jmp(done);
2373 __ bind(convert);
2375 __ lea(c_rarg1, utf8_addr);
2376 if (dst.first()->is_reg()) {
2377 __ movq(Address(rbp, src_off), c_rarg1);
2378 } else {
2379 __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg1);
2380 }
2381 // And do the conversion
2382 __ call(RuntimeAddress(
2383 CAST_FROM_FN_PTR(address, SharedRuntime::get_utf)));
2385 __ bind(done);
2386 }
2387 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
2388 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2389 ++c_arg; // skip over T_VOID to keep the loop indices in sync
2390 }
2391 }
2392 // The get_utf call killed all the c_arg registers
2393 live[c_rarg0->as_VMReg()->value()] = false;
2394 live[c_rarg1->as_VMReg()->value()] = false;
2395 live[c_rarg2->as_VMReg()->value()] = false;
2396 live[c_rarg3->as_VMReg()->value()] = false;
2397 live[c_rarg4->as_VMReg()->value()] = false;
2398 live[c_rarg5->as_VMReg()->value()] = false;
2400 live[c_farg0->as_VMReg()->value()] = false;
2401 live[c_farg1->as_VMReg()->value()] = false;
2402 live[c_farg2->as_VMReg()->value()] = false;
2403 live[c_farg3->as_VMReg()->value()] = false;
2404 live[c_farg4->as_VMReg()->value()] = false;
2405 live[c_farg5->as_VMReg()->value()] = false;
2406 live[c_farg6->as_VMReg()->value()] = false;
2407 live[c_farg7->as_VMReg()->value()] = false;
2408 }
2410 // Now we can finally move the register args to their desired locations
2412 rax_is_zero = false;
2414 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2415 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2417 VMRegPair src = in_regs[j_arg];
2418 VMRegPair dst = out_regs[c_arg];
2420 // Only need to look for args destined for the interger registers (since we
2421 // convert float/double args to look like int/long outbound)
2422 if (dst.first()->is_reg()) {
2423 Register r = dst.first()->as_Register();
2425 // Check if the java arg is unsupported and thereofre useless
2426 bool useless = in_sig_bt[j_arg] == T_ARRAY ||
2427 (in_sig_bt[j_arg] == T_OBJECT &&
2428 out_sig_bt[c_arg] != T_INT &&
2429 out_sig_bt[c_arg] != T_ADDRESS &&
2430 out_sig_bt[c_arg] != T_LONG);
2433 // If we're going to kill an existing arg save it first
2434 if (live[dst.first()->value()]) {
2435 // you can't kill yourself
2436 if (src.first() != dst.first()) {
2437 __ movq(Address(rbp, fp_offset[dst.first()->value()]), r);
2438 }
2439 }
2440 if (src.first()->is_reg()) {
2441 if (live[src.first()->value()] ) {
2442 if (in_sig_bt[j_arg] == T_FLOAT) {
2443 __ movdl(r, src.first()->as_XMMRegister());
2444 } else if (in_sig_bt[j_arg] == T_DOUBLE) {
2445 __ movdq(r, src.first()->as_XMMRegister());
2446 } else if (r != src.first()->as_Register()) {
2447 if (!useless) {
2448 __ movq(r, src.first()->as_Register());
2449 }
2450 }
2451 } else {
2452 // If the arg is an oop type we don't support don't bother to store
2453 // it
2454 if (!useless) {
2455 if (in_sig_bt[j_arg] == T_DOUBLE ||
2456 in_sig_bt[j_arg] == T_LONG ||
2457 in_sig_bt[j_arg] == T_OBJECT ) {
2458 __ movq(r, Address(rbp, fp_offset[src.first()->value()]));
2459 } else {
2460 __ movl(r, Address(rbp, fp_offset[src.first()->value()]));
2461 }
2462 }
2463 }
2464 live[src.first()->value()] = false;
2465 } else if (!useless) {
2466 // full sized move even for int should be ok
2467 __ movq(r, Address(rbp, reg2offset_in(src.first())));
2468 }
2470 // At this point r has the original java arg in the final location
2471 // (assuming it wasn't useless). If the java arg was an oop
2472 // we have a bit more to do
2474 if (in_sig_bt[j_arg] == T_ARRAY || in_sig_bt[j_arg] == T_OBJECT ) {
2475 if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
2476 // need to unbox a one-word value
2477 Label skip;
2478 __ testq(r, r);
2479 __ jcc(Assembler::equal, skip);
2480 BasicType bt = out_sig_bt[c_arg];
2481 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
2482 Address src1(r, box_offset);
2483 if ( bt == T_LONG ) {
2484 __ movq(r, src1);
2485 } else {
2486 __ movl(r, src1);
2487 }
2488 __ bind(skip);
2490 } else if (out_sig_bt[c_arg] != T_ADDRESS) {
2491 // Convert the arg to NULL
2492 __ xorq(r, r);
2493 }
2494 }
2496 // dst can longer be holding an input value
2497 live[dst.first()->value()] = false;
2498 }
2499 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
2500 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2501 ++c_arg; // skip over T_VOID to keep the loop indices in sync
2502 }
2503 }
2506 // Ok now we are done. Need to place the nop that dtrace wants in order to
2507 // patch in the trap
2508 int patch_offset = ((intptr_t)__ pc()) - start;
2510 __ nop();
2513 // Return
2515 __ leave();
2516 __ ret(0);
2518 __ flush();
2520 nmethod *nm = nmethod::new_dtrace_nmethod(
2521 method, masm->code(), vep_offset, patch_offset, frame_complete,
2522 stack_slots / VMRegImpl::slots_per_word);
2523 return nm;
2525 }
2527 #endif // HAVE_DTRACE_H
2529 // this function returns the adjust size (in number of words) to a c2i adapter
2530 // activation for use during deoptimization
2531 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals ) {
2532 return (callee_locals - callee_parameters) * Interpreter::stackElementWords();
2533 }
2536 uint SharedRuntime::out_preserve_stack_slots() {
2537 return 0;
2538 }
2541 //------------------------------generate_deopt_blob----------------------------
2542 void SharedRuntime::generate_deopt_blob() {
2543 // Allocate space for the code
2544 ResourceMark rm;
2545 // Setup code generation tools
2546 CodeBuffer buffer("deopt_blob", 2048, 1024);
2547 MacroAssembler* masm = new MacroAssembler(&buffer);
2548 int frame_size_in_words;
2549 OopMap* map = NULL;
2550 OopMapSet *oop_maps = new OopMapSet();
2552 // -------------
2553 // This code enters when returning to a de-optimized nmethod. A return
2554 // address has been pushed on the the stack, and return values are in
2555 // registers.
2556 // If we are doing a normal deopt then we were called from the patched
2557 // nmethod from the point we returned to the nmethod. So the return
2558 // address on the stack is wrong by NativeCall::instruction_size
2559 // We will adjust the value so it looks like we have the original return
2560 // address on the stack (like when we eagerly deoptimized).
2561 // In the case of an exception pending when deoptimizing, we enter
2562 // with a return address on the stack that points after the call we patched
2563 // into the exception handler. We have the following register state from,
2564 // e.g., the forward exception stub (see stubGenerator_x86_64.cpp).
2565 // rax: exception oop
2566 // rbx: exception handler
2567 // rdx: throwing pc
2568 // So in this case we simply jam rdx into the useless return address and
2569 // the stack looks just like we want.
2570 //
2571 // At this point we need to de-opt. We save the argument return
2572 // registers. We call the first C routine, fetch_unroll_info(). This
2573 // routine captures the return values and returns a structure which
2574 // describes the current frame size and the sizes of all replacement frames.
2575 // The current frame is compiled code and may contain many inlined
2576 // functions, each with their own JVM state. We pop the current frame, then
2577 // push all the new frames. Then we call the C routine unpack_frames() to
2578 // populate these frames. Finally unpack_frames() returns us the new target
2579 // address. Notice that callee-save registers are BLOWN here; they have
2580 // already been captured in the vframeArray at the time the return PC was
2581 // patched.
2582 address start = __ pc();
2583 Label cont;
2585 // Prolog for non exception case!
2587 // Save everything in sight.
2588 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
2590 // Normal deoptimization. Save exec mode for unpack_frames.
2591 __ movl(r14, Deoptimization::Unpack_deopt); // callee-saved
2592 __ jmp(cont);
2594 int reexecute_offset = __ pc() - start;
2596 // Reexecute case
2597 // return address is the pc describes what bci to do re-execute at
2599 // No need to update map as each call to save_live_registers will produce identical oopmap
2600 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
2602 __ movl(r14, Deoptimization::Unpack_reexecute); // callee-saved
2603 __ jmp(cont);
2605 int exception_offset = __ pc() - start;
2607 // Prolog for exception case
2609 // all registers are dead at this entry point, except for rax, and
2610 // rdx which contain the exception oop and exception pc
2611 // respectively. Set them in TLS and fall thru to the
2612 // unpack_with_exception_in_tls entry point.
2614 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
2615 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), rax);
2617 int exception_in_tls_offset = __ pc() - start;
2619 // new implementation because exception oop is now passed in JavaThread
2621 // Prolog for exception case
2622 // All registers must be preserved because they might be used by LinearScan
2623 // Exceptiop oop and throwing PC are passed in JavaThread
2624 // tos: stack at point of call to method that threw the exception (i.e. only
2625 // args are on the stack, no return address)
2627 // make room on stack for the return address
2628 // It will be patched later with the throwing pc. The correct value is not
2629 // available now because loading it from memory would destroy registers.
2630 __ push(0);
2632 // Save everything in sight.
2633 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
2635 // Now it is safe to overwrite any register
2637 // Deopt during an exception. Save exec mode for unpack_frames.
2638 __ movl(r14, Deoptimization::Unpack_exception); // callee-saved
2640 // load throwing pc from JavaThread and patch it as the return address
2641 // of the current frame. Then clear the field in JavaThread
2643 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
2644 __ movptr(Address(rbp, wordSize), rdx);
2645 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
2647 #ifdef ASSERT
2648 // verify that there is really an exception oop in JavaThread
2649 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
2650 __ verify_oop(rax);
2652 // verify that there is no pending exception
2653 Label no_pending_exception;
2654 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
2655 __ testptr(rax, rax);
2656 __ jcc(Assembler::zero, no_pending_exception);
2657 __ stop("must not have pending exception here");
2658 __ bind(no_pending_exception);
2659 #endif
2661 __ bind(cont);
2663 // Call C code. Need thread and this frame, but NOT official VM entry
2664 // crud. We cannot block on this call, no GC can happen.
2665 //
2666 // UnrollBlock* fetch_unroll_info(JavaThread* thread)
2668 // fetch_unroll_info needs to call last_java_frame().
2670 __ set_last_Java_frame(noreg, noreg, NULL);
2671 #ifdef ASSERT
2672 { Label L;
2673 __ cmpptr(Address(r15_thread,
2674 JavaThread::last_Java_fp_offset()),
2675 (int32_t)0);
2676 __ jcc(Assembler::equal, L);
2677 __ stop("SharedRuntime::generate_deopt_blob: last_Java_fp not cleared");
2678 __ bind(L);
2679 }
2680 #endif // ASSERT
2681 __ mov(c_rarg0, r15_thread);
2682 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info)));
2684 // Need to have an oopmap that tells fetch_unroll_info where to
2685 // find any register it might need.
2686 oop_maps->add_gc_map(__ pc() - start, map);
2688 __ reset_last_Java_frame(false, false);
2690 // Load UnrollBlock* into rdi
2691 __ mov(rdi, rax);
2693 Label noException;
2694 __ cmpl(r12, Deoptimization::Unpack_exception); // Was exception pending?
2695 __ jcc(Assembler::notEqual, noException);
2696 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
2697 // QQQ this is useless it was NULL above
2698 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
2699 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
2700 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
2702 __ verify_oop(rax);
2704 // Overwrite the result registers with the exception results.
2705 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
2706 // I think this is useless
2707 __ movptr(Address(rsp, RegisterSaver::rdx_offset_in_bytes()), rdx);
2709 __ bind(noException);
2711 // Only register save data is on the stack.
2712 // Now restore the result registers. Everything else is either dead
2713 // or captured in the vframeArray.
2714 RegisterSaver::restore_result_registers(masm);
2716 // All of the register save area has been popped of the stack. Only the
2717 // return address remains.
2719 // Pop all the frames we must move/replace.
2720 //
2721 // Frame picture (youngest to oldest)
2722 // 1: self-frame (no frame link)
2723 // 2: deopting frame (no frame link)
2724 // 3: caller of deopting frame (could be compiled/interpreted).
2725 //
2726 // Note: by leaving the return address of self-frame on the stack
2727 // and using the size of frame 2 to adjust the stack
2728 // when we are done the return to frame 3 will still be on the stack.
2730 // Pop deoptimized frame
2731 __ movl(rcx, Address(rdi, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
2732 __ addptr(rsp, rcx);
2734 // rsp should be pointing at the return address to the caller (3)
2736 // Stack bang to make sure there's enough room for these interpreter frames.
2737 if (UseStackBanging) {
2738 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
2739 __ bang_stack_size(rbx, rcx);
2740 }
2742 // Load address of array of frame pcs into rcx
2743 __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
2745 // Trash the old pc
2746 __ addptr(rsp, wordSize);
2748 // Load address of array of frame sizes into rsi
2749 __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
2751 // Load counter into rdx
2752 __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()));
2754 // Pick up the initial fp we should save
2755 __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_fp_offset_in_bytes()));
2757 // Now adjust the caller's stack to make up for the extra locals
2758 // but record the original sp so that we can save it in the skeletal interpreter
2759 // frame and the stack walking of interpreter_sender will get the unextended sp
2760 // value and not the "real" sp value.
2762 const Register sender_sp = r8;
2764 __ mov(sender_sp, rsp);
2765 __ movl(rbx, Address(rdi,
2766 Deoptimization::UnrollBlock::
2767 caller_adjustment_offset_in_bytes()));
2768 __ subptr(rsp, rbx);
2770 // Push interpreter frames in a loop
2771 Label loop;
2772 __ bind(loop);
2773 __ movptr(rbx, Address(rsi, 0)); // Load frame size
2774 #ifdef CC_INTERP
2775 __ subptr(rbx, 4*wordSize); // we'll push pc and ebp by hand and
2776 #ifdef ASSERT
2777 __ push(0xDEADDEAD); // Make a recognizable pattern
2778 __ push(0xDEADDEAD);
2779 #else /* ASSERT */
2780 __ subptr(rsp, 2*wordSize); // skip the "static long no_param"
2781 #endif /* ASSERT */
2782 #else
2783 __ subptr(rbx, 2*wordSize); // We'll push pc and ebp by hand
2784 #endif // CC_INTERP
2785 __ pushptr(Address(rcx, 0)); // Save return address
2786 __ enter(); // Save old & set new ebp
2787 __ subptr(rsp, rbx); // Prolog
2788 #ifdef CC_INTERP
2789 __ movptr(Address(rbp,
2790 -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
2791 sender_sp); // Make it walkable
2792 #else /* CC_INTERP */
2793 // This value is corrected by layout_activation_impl
2794 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
2795 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), sender_sp); // Make it walkable
2796 #endif /* CC_INTERP */
2797 __ mov(sender_sp, rsp); // Pass sender_sp to next frame
2798 __ addptr(rsi, wordSize); // Bump array pointer (sizes)
2799 __ addptr(rcx, wordSize); // Bump array pointer (pcs)
2800 __ decrementl(rdx); // Decrement counter
2801 __ jcc(Assembler::notZero, loop);
2802 __ pushptr(Address(rcx, 0)); // Save final return address
2804 // Re-push self-frame
2805 __ enter(); // Save old & set new ebp
2807 // Allocate a full sized register save area.
2808 // Return address and rbp are in place, so we allocate two less words.
2809 __ subptr(rsp, (frame_size_in_words - 2) * wordSize);
2811 // Restore frame locals after moving the frame
2812 __ movdbl(Address(rsp, RegisterSaver::xmm0_offset_in_bytes()), xmm0);
2813 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
2815 // Call C code. Need thread but NOT official VM entry
2816 // crud. We cannot block on this call, no GC can happen. Call should
2817 // restore return values to their stack-slots with the new SP.
2818 //
2819 // void Deoptimization::unpack_frames(JavaThread* thread, int exec_mode)
2821 // Use rbp because the frames look interpreted now
2822 __ set_last_Java_frame(noreg, rbp, NULL);
2824 __ mov(c_rarg0, r15_thread);
2825 __ movl(c_rarg1, r14); // second arg: exec_mode
2826 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
2828 // Set an oopmap for the call site
2829 oop_maps->add_gc_map(__ pc() - start,
2830 new OopMap( frame_size_in_words, 0 ));
2832 __ reset_last_Java_frame(true, false);
2834 // Collect return values
2835 __ movdbl(xmm0, Address(rsp, RegisterSaver::xmm0_offset_in_bytes()));
2836 __ movptr(rax, Address(rsp, RegisterSaver::rax_offset_in_bytes()));
2837 // I think this is useless (throwing pc?)
2838 __ movptr(rdx, Address(rsp, RegisterSaver::rdx_offset_in_bytes()));
2840 // Pop self-frame.
2841 __ leave(); // Epilog
2843 // Jump to interpreter
2844 __ ret(0);
2846 // Make sure all code is generated
2847 masm->flush();
2849 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_in_words);
2850 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
2851 }
2853 #ifdef COMPILER2
2854 //------------------------------generate_uncommon_trap_blob--------------------
2855 void SharedRuntime::generate_uncommon_trap_blob() {
2856 // Allocate space for the code
2857 ResourceMark rm;
2858 // Setup code generation tools
2859 CodeBuffer buffer("uncommon_trap_blob", 2048, 1024);
2860 MacroAssembler* masm = new MacroAssembler(&buffer);
2862 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
2864 address start = __ pc();
2866 // Push self-frame. We get here with a return address on the
2867 // stack, so rsp is 8-byte aligned until we allocate our frame.
2868 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog!
2870 // No callee saved registers. rbp is assumed implicitly saved
2871 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
2873 // compiler left unloaded_class_index in j_rarg0 move to where the
2874 // runtime expects it.
2875 __ movl(c_rarg1, j_rarg0);
2877 __ set_last_Java_frame(noreg, noreg, NULL);
2879 // Call C code. Need thread but NOT official VM entry
2880 // crud. We cannot block on this call, no GC can happen. Call should
2881 // capture callee-saved registers as well as return values.
2882 // Thread is in rdi already.
2883 //
2884 // UnrollBlock* uncommon_trap(JavaThread* thread, jint unloaded_class_index);
2886 __ mov(c_rarg0, r15_thread);
2887 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap)));
2889 // Set an oopmap for the call site
2890 OopMapSet* oop_maps = new OopMapSet();
2891 OopMap* map = new OopMap(SimpleRuntimeFrame::framesize, 0);
2893 // location of rbp is known implicitly by the frame sender code
2895 oop_maps->add_gc_map(__ pc() - start, map);
2897 __ reset_last_Java_frame(false, false);
2899 // Load UnrollBlock* into rdi
2900 __ mov(rdi, rax);
2902 // Pop all the frames we must move/replace.
2903 //
2904 // Frame picture (youngest to oldest)
2905 // 1: self-frame (no frame link)
2906 // 2: deopting frame (no frame link)
2907 // 3: caller of deopting frame (could be compiled/interpreted).
2909 // Pop self-frame. We have no frame, and must rely only on rax and rsp.
2910 __ addptr(rsp, (SimpleRuntimeFrame::framesize - 2) << LogBytesPerInt); // Epilog!
2912 // Pop deoptimized frame (int)
2913 __ movl(rcx, Address(rdi,
2914 Deoptimization::UnrollBlock::
2915 size_of_deoptimized_frame_offset_in_bytes()));
2916 __ addptr(rsp, rcx);
2918 // rsp should be pointing at the return address to the caller (3)
2920 // Stack bang to make sure there's enough room for these interpreter frames.
2921 if (UseStackBanging) {
2922 __ movl(rbx, Address(rdi ,Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
2923 __ bang_stack_size(rbx, rcx);
2924 }
2926 // Load address of array of frame pcs into rcx (address*)
2927 __ movptr(rcx,
2928 Address(rdi,
2929 Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
2931 // Trash the return pc
2932 __ addptr(rsp, wordSize);
2934 // Load address of array of frame sizes into rsi (intptr_t*)
2935 __ movptr(rsi, Address(rdi,
2936 Deoptimization::UnrollBlock::
2937 frame_sizes_offset_in_bytes()));
2939 // Counter
2940 __ movl(rdx, Address(rdi,
2941 Deoptimization::UnrollBlock::
2942 number_of_frames_offset_in_bytes())); // (int)
2944 // Pick up the initial fp we should save
2945 __ movptr(rbp,
2946 Address(rdi,
2947 Deoptimization::UnrollBlock::initial_fp_offset_in_bytes()));
2949 // Now adjust the caller's stack to make up for the extra locals but
2950 // record the original sp so that we can save it in the skeletal
2951 // interpreter frame and the stack walking of interpreter_sender
2952 // will get the unextended sp value and not the "real" sp value.
2954 const Register sender_sp = r8;
2956 __ mov(sender_sp, rsp);
2957 __ movl(rbx, Address(rdi,
2958 Deoptimization::UnrollBlock::
2959 caller_adjustment_offset_in_bytes())); // (int)
2960 __ subptr(rsp, rbx);
2962 // Push interpreter frames in a loop
2963 Label loop;
2964 __ bind(loop);
2965 __ movptr(rbx, Address(rsi, 0)); // Load frame size
2966 __ subptr(rbx, 2 * wordSize); // We'll push pc and rbp by hand
2967 __ pushptr(Address(rcx, 0)); // Save return address
2968 __ enter(); // Save old & set new rbp
2969 __ subptr(rsp, rbx); // Prolog
2970 #ifdef CC_INTERP
2971 __ movptr(Address(rbp,
2972 -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
2973 sender_sp); // Make it walkable
2974 #else // CC_INTERP
2975 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize),
2976 sender_sp); // Make it walkable
2977 // This value is corrected by layout_activation_impl
2978 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
2979 #endif // CC_INTERP
2980 __ mov(sender_sp, rsp); // Pass sender_sp to next frame
2981 __ addptr(rsi, wordSize); // Bump array pointer (sizes)
2982 __ addptr(rcx, wordSize); // Bump array pointer (pcs)
2983 __ decrementl(rdx); // Decrement counter
2984 __ jcc(Assembler::notZero, loop);
2985 __ pushptr(Address(rcx, 0)); // Save final return address
2987 // Re-push self-frame
2988 __ enter(); // Save old & set new rbp
2989 __ subptr(rsp, (SimpleRuntimeFrame::framesize - 4) << LogBytesPerInt);
2990 // Prolog
2992 // Use rbp because the frames look interpreted now
2993 __ set_last_Java_frame(noreg, rbp, NULL);
2995 // Call C code. Need thread but NOT official VM entry
2996 // crud. We cannot block on this call, no GC can happen. Call should
2997 // restore return values to their stack-slots with the new SP.
2998 // Thread is in rdi already.
2999 //
3000 // BasicType unpack_frames(JavaThread* thread, int exec_mode);
3002 __ mov(c_rarg0, r15_thread);
3003 __ movl(c_rarg1, Deoptimization::Unpack_uncommon_trap);
3004 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
3006 // Set an oopmap for the call site
3007 oop_maps->add_gc_map(__ pc() - start, new OopMap(SimpleRuntimeFrame::framesize, 0));
3009 __ reset_last_Java_frame(true, false);
3011 // Pop self-frame.
3012 __ leave(); // Epilog
3014 // Jump to interpreter
3015 __ ret(0);
3017 // Make sure all code is generated
3018 masm->flush();
3020 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps,
3021 SimpleRuntimeFrame::framesize >> 1);
3022 }
3023 #endif // COMPILER2
3026 //------------------------------generate_handler_blob------
3027 //
3028 // Generate a special Compile2Runtime blob that saves all registers,
3029 // and setup oopmap.
3030 //
3031 static SafepointBlob* generate_handler_blob(address call_ptr, bool cause_return) {
3032 assert(StubRoutines::forward_exception_entry() != NULL,
3033 "must be generated before");
3035 ResourceMark rm;
3036 OopMapSet *oop_maps = new OopMapSet();
3037 OopMap* map;
3039 // Allocate space for the code. Setup code generation tools.
3040 CodeBuffer buffer("handler_blob", 2048, 1024);
3041 MacroAssembler* masm = new MacroAssembler(&buffer);
3043 address start = __ pc();
3044 address call_pc = NULL;
3045 int frame_size_in_words;
3047 // Make room for return address (or push it again)
3048 if (!cause_return) {
3049 __ push(rbx);
3050 }
3052 // Save registers, fpu state, and flags
3053 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3055 // The following is basically a call_VM. However, we need the precise
3056 // address of the call in order to generate an oopmap. Hence, we do all the
3057 // work outselves.
3059 __ set_last_Java_frame(noreg, noreg, NULL);
3061 // The return address must always be correct so that frame constructor never
3062 // sees an invalid pc.
3064 if (!cause_return) {
3065 // overwrite the dummy value we pushed on entry
3066 __ movptr(c_rarg0, Address(r15_thread, JavaThread::saved_exception_pc_offset()));
3067 __ movptr(Address(rbp, wordSize), c_rarg0);
3068 }
3070 // Do the call
3071 __ mov(c_rarg0, r15_thread);
3072 __ call(RuntimeAddress(call_ptr));
3074 // Set an oopmap for the call site. This oopmap will map all
3075 // oop-registers and debug-info registers as callee-saved. This
3076 // will allow deoptimization at this safepoint to find all possible
3077 // debug-info recordings, as well as let GC find all oops.
3079 oop_maps->add_gc_map( __ pc() - start, map);
3081 Label noException;
3083 __ reset_last_Java_frame(false, false);
3085 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
3086 __ jcc(Assembler::equal, noException);
3088 // Exception pending
3090 RegisterSaver::restore_live_registers(masm);
3092 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
3094 // No exception case
3095 __ bind(noException);
3097 // Normal exit, restore registers and exit.
3098 RegisterSaver::restore_live_registers(masm);
3100 __ ret(0);
3102 // Make sure all code is generated
3103 masm->flush();
3105 // Fill-out other meta info
3106 return SafepointBlob::create(&buffer, oop_maps, frame_size_in_words);
3107 }
3109 //
3110 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss
3111 //
3112 // Generate a stub that calls into vm to find out the proper destination
3113 // of a java call. All the argument registers are live at this point
3114 // but since this is generic code we don't know what they are and the caller
3115 // must do any gc of the args.
3116 //
3117 static RuntimeStub* generate_resolve_blob(address destination, const char* name) {
3118 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3120 // allocate space for the code
3121 ResourceMark rm;
3123 CodeBuffer buffer(name, 1000, 512);
3124 MacroAssembler* masm = new MacroAssembler(&buffer);
3126 int frame_size_in_words;
3128 OopMapSet *oop_maps = new OopMapSet();
3129 OopMap* map = NULL;
3131 int start = __ offset();
3133 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3135 int frame_complete = __ offset();
3137 __ set_last_Java_frame(noreg, noreg, NULL);
3139 __ mov(c_rarg0, r15_thread);
3141 __ call(RuntimeAddress(destination));
3144 // Set an oopmap for the call site.
3145 // We need this not only for callee-saved registers, but also for volatile
3146 // registers that the compiler might be keeping live across a safepoint.
3148 oop_maps->add_gc_map( __ offset() - start, map);
3150 // rax contains the address we are going to jump to assuming no exception got installed
3152 // clear last_Java_sp
3153 __ reset_last_Java_frame(false, false);
3154 // check for pending exceptions
3155 Label pending;
3156 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
3157 __ jcc(Assembler::notEqual, pending);
3159 // get the returned methodOop
3160 __ movptr(rbx, Address(r15_thread, JavaThread::vm_result_offset()));
3161 __ movptr(Address(rsp, RegisterSaver::rbx_offset_in_bytes()), rbx);
3163 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
3165 RegisterSaver::restore_live_registers(masm);
3167 // We are back the the original state on entry and ready to go.
3169 __ jmp(rax);
3171 // Pending exception after the safepoint
3173 __ bind(pending);
3175 RegisterSaver::restore_live_registers(masm);
3177 // exception pending => remove activation and forward to exception handler
3179 __ movptr(Address(r15_thread, JavaThread::vm_result_offset()), (int)NULL_WORD);
3181 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
3182 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
3184 // -------------
3185 // make sure all code is generated
3186 masm->flush();
3188 // return the blob
3189 // frame_size_words or bytes??
3190 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_in_words, oop_maps, true);
3191 }
3194 void SharedRuntime::generate_stubs() {
3196 _wrong_method_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::handle_wrong_method),
3197 "wrong_method_stub");
3198 _ic_miss_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::handle_wrong_method_ic_miss),
3199 "ic_miss_stub");
3200 _resolve_opt_virtual_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_opt_virtual_call_C),
3201 "resolve_opt_virtual_call");
3203 _resolve_virtual_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_virtual_call_C),
3204 "resolve_virtual_call");
3206 _resolve_static_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_static_call_C),
3207 "resolve_static_call");
3208 _polling_page_safepoint_handler_blob =
3209 generate_handler_blob(CAST_FROM_FN_PTR(address,
3210 SafepointSynchronize::handle_polling_page_exception), false);
3212 _polling_page_return_handler_blob =
3213 generate_handler_blob(CAST_FROM_FN_PTR(address,
3214 SafepointSynchronize::handle_polling_page_exception), true);
3216 generate_deopt_blob();
3218 #ifdef COMPILER2
3219 generate_uncommon_trap_blob();
3220 #endif // COMPILER2
3221 }
3224 #ifdef COMPILER2
3225 // This is here instead of runtime_x86_64.cpp because it uses SimpleRuntimeFrame
3226 //
3227 //------------------------------generate_exception_blob---------------------------
3228 // creates exception blob at the end
3229 // Using exception blob, this code is jumped from a compiled method.
3230 // (see emit_exception_handler in x86_64.ad file)
3231 //
3232 // Given an exception pc at a call we call into the runtime for the
3233 // handler in this method. This handler might merely restore state
3234 // (i.e. callee save registers) unwind the frame and jump to the
3235 // exception handler for the nmethod if there is no Java level handler
3236 // for the nmethod.
3237 //
3238 // This code is entered with a jmp.
3239 //
3240 // Arguments:
3241 // rax: exception oop
3242 // rdx: exception pc
3243 //
3244 // Results:
3245 // rax: exception oop
3246 // rdx: exception pc in caller or ???
3247 // destination: exception handler of caller
3248 //
3249 // Note: the exception pc MUST be at a call (precise debug information)
3250 // Registers rax, rdx, rcx, rsi, rdi, r8-r11 are not callee saved.
3251 //
3253 void OptoRuntime::generate_exception_blob() {
3254 assert(!OptoRuntime::is_callee_saved_register(RDX_num), "");
3255 assert(!OptoRuntime::is_callee_saved_register(RAX_num), "");
3256 assert(!OptoRuntime::is_callee_saved_register(RCX_num), "");
3258 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
3260 // Allocate space for the code
3261 ResourceMark rm;
3262 // Setup code generation tools
3263 CodeBuffer buffer("exception_blob", 2048, 1024);
3264 MacroAssembler* masm = new MacroAssembler(&buffer);
3267 address start = __ pc();
3269 // Exception pc is 'return address' for stack walker
3270 __ push(rdx);
3271 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Prolog
3273 // Save callee-saved registers. See x86_64.ad.
3275 // rbp is an implicitly saved callee saved register (i.e. the calling
3276 // convention will save restore it in prolog/epilog) Other than that
3277 // there are no callee save registers now that adapter frames are gone.
3279 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
3281 // Store exception in Thread object. We cannot pass any arguments to the
3282 // handle_exception call, since we do not want to make any assumption
3283 // about the size of the frame where the exception happened in.
3284 // c_rarg0 is either rdi (Linux) or rcx (Windows).
3285 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()),rax);
3286 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
3288 // This call does all the hard work. It checks if an exception handler
3289 // exists in the method.
3290 // If so, it returns the handler address.
3291 // If not, it prepares for stack-unwinding, restoring the callee-save
3292 // registers of the frame being removed.
3293 //
3294 // address OptoRuntime::handle_exception_C(JavaThread* thread)
3296 __ set_last_Java_frame(noreg, noreg, NULL);
3297 __ mov(c_rarg0, r15_thread);
3298 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, OptoRuntime::handle_exception_C)));
3300 // Set an oopmap for the call site. This oopmap will only be used if we
3301 // are unwinding the stack. Hence, all locations will be dead.
3302 // Callee-saved registers will be the same as the frame above (i.e.,
3303 // handle_exception_stub), since they were restored when we got the
3304 // exception.
3306 OopMapSet* oop_maps = new OopMapSet();
3308 oop_maps->add_gc_map( __ pc()-start, new OopMap(SimpleRuntimeFrame::framesize, 0));
3310 __ reset_last_Java_frame(false, false);
3312 // Restore callee-saved registers
3314 // rbp is an implicitly saved callee saved register (i.e. the calling
3315 // convention will save restore it in prolog/epilog) Other than that
3316 // there are no callee save registers no that adapter frames are gone.
3318 __ movptr(rbp, Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt));
3320 __ addptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog
3321 __ pop(rdx); // No need for exception pc anymore
3323 // rax: exception handler
3325 // We have a handler in rax (could be deopt blob).
3326 __ mov(r8, rax);
3328 // Get the exception oop
3329 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
3330 // Get the exception pc in case we are deoptimized
3331 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
3332 #ifdef ASSERT
3333 __ movptr(Address(r15_thread, JavaThread::exception_handler_pc_offset()), (int)NULL_WORD);
3334 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int)NULL_WORD);
3335 #endif
3336 // Clear the exception oop so GC no longer processes it as a root.
3337 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int)NULL_WORD);
3339 // rax: exception oop
3340 // r8: exception handler
3341 // rdx: exception pc
3342 // Jump to handler
3344 __ jmp(r8);
3346 // Make sure all code is generated
3347 masm->flush();
3349 // Set exception blob
3350 _exception_blob = ExceptionBlob::create(&buffer, oop_maps, SimpleRuntimeFrame::framesize >> 1);
3351 }
3352 #endif // COMPILER2