Mercurial > jdk8-mips64-public > hotspot / file revision
src/cpu/x86/vm/vm_version_x86_64.cpp@3d62cb85208d
src/cpu/x86/vm/vm_version_x86_64.cpp
Wed, 19 Mar 2008 15:33:25 -0700
- author
- kvn
- date
- Wed, 19 Mar 2008 15:33:25 -0700
- changeset 506
- 3d62cb85208d
- parent 435
- a61af66fc99e
- child 631
- d1605aabd0a1
- permissions
- -rw-r--r--
6662967: Optimize I2D conversion on new x86
Summary: Use CVTDQ2PS and CVTDQ2PD for integer values conversions to float and double values on new AMD cpu.
Reviewed-by: sgoldman, never
1 /*
2 * Copyright 2003-2007 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
25 # include "incls/_precompiled.incl"
26 # include "incls/_vm_version_x86_64.cpp.incl"
28 int VM_Version::_cpu;
29 int VM_Version::_model;
30 int VM_Version::_stepping;
31 int VM_Version::_cpuFeatures;
32 const char* VM_Version::_features_str = "";
33 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
35 static BufferBlob* stub_blob;
36 static const int stub_size = 300;
38 extern "C" {
39 typedef void (*getPsrInfo_stub_t)(void*);
40 }
41 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
44 class VM_Version_StubGenerator: public StubCodeGenerator {
45 public:
47 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
49 address generate_getPsrInfo() {
51 Label std_cpuid1, ext_cpuid1, ext_cpuid5, done;
53 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
54 # define __ _masm->
56 address start = __ pc();
58 //
59 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
60 //
61 // rcx and rdx are first and second argument registers on windows
63 __ pushq(rbp);
64 __ movq(rbp, c_rarg0); // cpuid_info address
65 __ pushq(rbx);
66 __ pushq(rsi);
68 //
69 // we have a chip which supports the "cpuid" instruction
70 //
71 __ xorl(rax, rax);
72 __ cpuid();
73 __ leaq(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
74 __ movl(Address(rsi, 0), rax);
75 __ movl(Address(rsi, 4), rbx);
76 __ movl(Address(rsi, 8), rcx);
77 __ movl(Address(rsi,12), rdx);
79 __ cmpl(rax, 3); // Is cpuid(0x4) supported?
80 __ jccb(Assembler::belowEqual, std_cpuid1);
82 //
83 // cpuid(0x4) Deterministic cache params
84 //
85 __ movl(rax, 4);
86 __ xorl(rcx, rcx); // L1 cache
87 __ cpuid();
88 __ pushq(rax);
89 __ andl(rax, 0x1f); // Determine if valid cache parameters used
90 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
91 __ popq(rax);
92 __ jccb(Assembler::equal, std_cpuid1);
94 __ leaq(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
95 __ movl(Address(rsi, 0), rax);
96 __ movl(Address(rsi, 4), rbx);
97 __ movl(Address(rsi, 8), rcx);
98 __ movl(Address(rsi,12), rdx);
100 //
101 // Standard cpuid(0x1)
102 //
103 __ bind(std_cpuid1);
104 __ movl(rax, 1);
105 __ cpuid();
106 __ leaq(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
107 __ movl(Address(rsi, 0), rax);
108 __ movl(Address(rsi, 4), rbx);
109 __ movl(Address(rsi, 8), rcx);
110 __ movl(Address(rsi,12), rdx);
112 __ movl(rax, 0x80000000);
113 __ cpuid();
114 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
115 __ jcc(Assembler::belowEqual, done);
116 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
117 __ jccb(Assembler::belowEqual, ext_cpuid1);
118 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
119 __ jccb(Assembler::belowEqual, ext_cpuid5);
120 //
121 // Extended cpuid(0x80000008)
122 //
123 __ movl(rax, 0x80000008);
124 __ cpuid();
125 __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
126 __ movl(Address(rsi, 0), rax);
127 __ movl(Address(rsi, 4), rbx);
128 __ movl(Address(rsi, 8), rcx);
129 __ movl(Address(rsi,12), rdx);
131 //
132 // Extended cpuid(0x80000005)
133 //
134 __ bind(ext_cpuid5);
135 __ movl(rax, 0x80000005);
136 __ cpuid();
137 __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
138 __ movl(Address(rsi, 0), rax);
139 __ movl(Address(rsi, 4), rbx);
140 __ movl(Address(rsi, 8), rcx);
141 __ movl(Address(rsi,12), rdx);
143 //
144 // Extended cpuid(0x80000001)
145 //
146 __ bind(ext_cpuid1);
147 __ movl(rax, 0x80000001);
148 __ cpuid();
149 __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
150 __ movl(Address(rsi, 0), rax);
151 __ movl(Address(rsi, 4), rbx);
152 __ movl(Address(rsi, 8), rcx);
153 __ movl(Address(rsi,12), rdx);
155 //
156 // return
157 //
158 __ bind(done);
159 __ popq(rsi);
160 __ popq(rbx);
161 __ popq(rbp);
162 __ ret(0);
164 # undef __
166 return start;
167 };
168 };
171 void VM_Version::get_processor_features() {
173 _logical_processors_per_package = 1;
174 // Get raw processor info
175 getPsrInfo_stub(&_cpuid_info);
176 assert_is_initialized();
177 _cpu = extended_cpu_family();
178 _model = extended_cpu_model();
179 _stepping = cpu_stepping();
180 _cpuFeatures = feature_flags();
181 // Logical processors are only available on P4s and above,
182 // and only if hyperthreading is available.
183 _logical_processors_per_package = logical_processor_count();
184 _supports_cx8 = supports_cmpxchg8();
185 // OS should support SSE for x64 and hardware should support at least SSE2.
186 if (!VM_Version::supports_sse2()) {
187 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
188 }
189 if (UseSSE < 4)
190 _cpuFeatures &= ~CPU_SSE4;
191 if (UseSSE < 3) {
192 _cpuFeatures &= ~CPU_SSE3;
193 _cpuFeatures &= ~CPU_SSSE3;
194 _cpuFeatures &= ~CPU_SSE4A;
195 }
196 if (UseSSE < 2)
197 _cpuFeatures &= ~CPU_SSE2;
198 if (UseSSE < 1)
199 _cpuFeatures &= ~CPU_SSE;
201 if (logical_processors_per_package() == 1) {
202 // HT processor could be installed on a system which doesn't support HT.
203 _cpuFeatures &= ~CPU_HT;
204 }
206 char buf[256];
207 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
208 cores_per_cpu(), threads_per_core(),
209 cpu_family(), _model, _stepping,
210 (supports_cmov() ? ", cmov" : ""),
211 (supports_cmpxchg8() ? ", cx8" : ""),
212 (supports_fxsr() ? ", fxsr" : ""),
213 (supports_mmx() ? ", mmx" : ""),
214 (supports_sse() ? ", sse" : ""),
215 (supports_sse2() ? ", sse2" : ""),
216 (supports_sse3() ? ", sse3" : ""),
217 (supports_ssse3()? ", ssse3": ""),
218 (supports_sse4() ? ", sse4" : ""),
219 (supports_mmx_ext() ? ", mmxext" : ""),
220 (supports_3dnow() ? ", 3dnow" : ""),
221 (supports_3dnow2() ? ", 3dnowext" : ""),
222 (supports_sse4a() ? ", sse4a": ""),
223 (supports_ht() ? ", ht": ""));
224 _features_str = strdup(buf);
226 // UseSSE is set to the smaller of what hardware supports and what
227 // the command line requires. I.e., you cannot set UseSSE to 2 on
228 // older Pentiums which do not support it.
229 if( UseSSE > 4 ) UseSSE=4;
230 if( UseSSE < 0 ) UseSSE=0;
231 if( !supports_sse4() ) // Drop to 3 if no SSE4 support
232 UseSSE = MIN2((intx)3,UseSSE);
233 if( !supports_sse3() ) // Drop to 2 if no SSE3 support
234 UseSSE = MIN2((intx)2,UseSSE);
235 if( !supports_sse2() ) // Drop to 1 if no SSE2 support
236 UseSSE = MIN2((intx)1,UseSSE);
237 if( !supports_sse () ) // Drop to 0 if no SSE support
238 UseSSE = 0;
240 // On new cpus instructions which update whole XMM register should be used
241 // to prevent partial register stall due to dependencies on high half.
242 //
243 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
244 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
245 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
246 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
248 if( is_amd() ) { // AMD cpus specific settings
249 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
250 // Use it on all AMD cpus starting from Opteron (don't need
251 // a cpu check since only Opteron and new cpus support 64-bits mode).
252 UseAddressNop = true;
253 }
254 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
255 if( supports_sse4a() ) {
256 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
257 } else {
258 UseXmmLoadAndClearUpper = false;
259 }
260 }
261 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
262 if( supports_sse4a() ) {
263 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
264 } else {
265 UseXmmRegToRegMoveAll = false;
266 }
267 }
268 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
269 if( supports_sse4a() ) {
270 UseXmmI2F = true;
271 } else {
272 UseXmmI2F = false;
273 }
274 }
275 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
276 if( supports_sse4a() ) {
277 UseXmmI2D = true;
278 } else {
279 UseXmmI2D = false;
280 }
281 }
282 }
284 if( is_intel() ) { // Intel cpus specific settings
285 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
286 UseStoreImmI16 = false; // don't use it on Intel cpus
287 }
288 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
289 // Use it on all Intel cpus starting from PentiumPro
290 // (don't need a cpu check since only new cpus support 64-bits mode).
291 UseAddressNop = true;
292 }
293 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
294 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
295 }
296 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
297 if( supports_sse3() ) {
298 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
299 } else {
300 UseXmmRegToRegMoveAll = false;
301 }
302 }
303 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
304 #ifdef COMPILER2
305 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
306 // For new Intel cpus do the next optimization:
307 // don't align the beginning of a loop if there are enough instructions
308 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
309 // in current fetch line (OptoLoopAlignment) or the padding
310 // is big (> MaxLoopPad).
311 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
312 // generated NOP instructions. 11 is the largest size of one
313 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
314 MaxLoopPad = 11;
315 }
316 #endif // COMPILER2
317 }
318 }
320 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
321 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
323 // set valid Prefetch instruction
324 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
325 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
326 if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0;
328 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
329 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
330 if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0;
332 // Allocation prefetch settings
333 intx cache_line_size = L1_data_cache_line_size();
334 if( cache_line_size > AllocatePrefetchStepSize )
335 AllocatePrefetchStepSize = cache_line_size;
336 if( FLAG_IS_DEFAULT(AllocatePrefetchLines) )
337 AllocatePrefetchLines = 3; // Optimistic value
338 assert(AllocatePrefetchLines > 0, "invalid value");
339 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
340 AllocatePrefetchLines = 1; // Conservative value
342 AllocatePrefetchDistance = allocate_prefetch_distance();
343 AllocatePrefetchStyle = allocate_prefetch_style();
345 if( AllocatePrefetchStyle == 2 && is_intel() &&
346 cpu_family() == 6 && supports_sse3() ) { // watermark prefetching on Core
347 AllocatePrefetchDistance = 384;
348 }
349 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
351 // Prefetch settings
352 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
353 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
354 PrefetchFieldsAhead = prefetch_fields_ahead();
356 #ifndef PRODUCT
357 if (PrintMiscellaneous && Verbose) {
358 tty->print_cr("Logical CPUs per package: %u",
359 logical_processors_per_package());
360 tty->print_cr("UseSSE=%d",UseSSE);
361 tty->print("Allocation: ");
362 if (AllocatePrefetchStyle <= 0) {
363 tty->print_cr("no prefetching");
364 } else {
365 if (AllocatePrefetchInstr == 0) {
366 tty->print("PREFETCHNTA");
367 } else if (AllocatePrefetchInstr == 1) {
368 tty->print("PREFETCHT0");
369 } else if (AllocatePrefetchInstr == 2) {
370 tty->print("PREFETCHT2");
371 } else if (AllocatePrefetchInstr == 3) {
372 tty->print("PREFETCHW");
373 }
374 if (AllocatePrefetchLines > 1) {
375 tty->print_cr(" %d, %d lines with step %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
376 } else {
377 tty->print_cr(" %d, one line", AllocatePrefetchDistance);
378 }
379 }
380 if (PrefetchCopyIntervalInBytes > 0) {
381 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
382 }
383 if (PrefetchScanIntervalInBytes > 0) {
384 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
385 }
386 if (PrefetchFieldsAhead > 0) {
387 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
388 }
389 }
390 #endif // !PRODUCT
391 }
393 void VM_Version::initialize() {
394 ResourceMark rm;
395 // Making this stub must be FIRST use of assembler
397 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
398 if (stub_blob == NULL) {
399 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
400 }
401 CodeBuffer c(stub_blob->instructions_begin(),
402 stub_blob->instructions_size());
403 VM_Version_StubGenerator g(&c);
404 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
405 g.generate_getPsrInfo());
407 get_processor_features();
408 }
