jdk8-mips64-public/hotspot: src/share/vm/c1/c1

     1 /*

     2  * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.

     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

     4  *

     5  * This code is free software; you can redistribute it and/or modify it

     6  * under the terms of the GNU General Public License version 2 only, as

     7  * published by the Free Software Foundation.

     8  *

     9  * This code is distributed in the hope that it will be useful, but WITHOUT

    10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

    12  * version 2 for more details (a copy is included in the LICENSE file that

    13  * accompanied this code).

    14  *

    15  * You should have received a copy of the GNU General Public License version

    16  * 2 along with this work; if not, write to the Free Software Foundation,

    17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

    18  *

    19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

    20  * or visit www.oracle.com if you need additional information or have any

    21  * questions.

    22  *

    23  */

    25 /*

    26  * This file has been modified by Loongson Technology in 2015. These

    27  * modifications are Copyright (c) 2015 Loongson Technology, and are made

    28  * available on the same license terms set forth above.

    29  */

    31 #ifndef SHARE_VM_C1_C1_LIRASSEMBLER_HPP

    32 #define SHARE_VM_C1_C1_LIRASSEMBLER_HPP

    34 #include "c1/c1_CodeStubs.hpp"

    35 #include "ci/ciMethodData.hpp"

    36 #include "oops/methodData.hpp"

    37 #include "utilities/top.hpp"

    39 class Compilation;

    40 class ScopeValue;

    41 class BarrierSet;

    43 class LIR_Assembler: public CompilationResourceObj {

    44  private:

    45   C1_MacroAssembler* _masm;

    46   CodeStubList*      _slow_case_stubs;

    47   BarrierSet*        _bs;

    49   Compilation*       _compilation;

    50   FrameMap*          _frame_map;

    51   BlockBegin*        _current_block;

    53   Instruction*       _pending_non_safepoint;

    54   int                _pending_non_safepoint_offset;

    56   Label              _unwind_handler_entry;

    58 #ifdef ASSERT

    59   BlockList          _branch_target_blocks;

    60   void check_no_unbound_labels();

    61 #endif

    63   FrameMap* frame_map() const { return _frame_map; }

    65   void set_current_block(BlockBegin* b) { _current_block = b; }

    66   BlockBegin* current_block() const { return _current_block; }

    68   // non-safepoint debug info management

    69   void flush_debug_info(int before_pc_offset) {

    70     if (_pending_non_safepoint != NULL) {

    71       if (_pending_non_safepoint_offset < before_pc_offset)

    72         record_non_safepoint_debug_info();

    73       _pending_non_safepoint = NULL;

    74     }

    75   }

    76   void process_debug_info(LIR_Op* op);

    77   void record_non_safepoint_debug_info();

    79   // unified bailout support

    80   void bailout(const char* msg) const            { compilation()->bailout(msg); }

    81   bool bailed_out() const                        { return compilation()->bailed_out(); }

    83   // code emission patterns and accessors

    84   void check_codespace();

    85   bool needs_icache(ciMethod* method) const;

    87   // returns offset of icache check

    88   int check_icache();

    90   void jobject2reg(jobject o, Register reg);

    91   void jobject2reg_with_patching(Register reg, CodeEmitInfo* info);

    93   void metadata2reg(Metadata* o, Register reg);

    94   void klass2reg_with_patching(Register reg, CodeEmitInfo* info);

    96   void emit_stubs(CodeStubList* stub_list);

    98   // addresses

    99   Address as_Address(LIR_Address* addr);

   100   Address as_Address_lo(LIR_Address* addr);

   101   Address as_Address_hi(LIR_Address* addr);

   103   // debug information

   104   void add_call_info(int pc_offset, CodeEmitInfo* cinfo);

   105   void add_debug_info_for_branch(CodeEmitInfo* info);

   106   void add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo);

   107   void add_debug_info_for_div0_here(CodeEmitInfo* info);

   108   void add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo);

   109   void add_debug_info_for_null_check_here(CodeEmitInfo* info);

   111   void set_24bit_FPU();

   112   void reset_FPU();

   113   void fpop();

   114   void fxch(int i);

   115   void fld(int i);

   116   void ffree(int i);

   118   void breakpoint();

   119   void push(LIR_Opr opr);

   120   void pop(LIR_Opr opr);

   122   // patching

   123   void append_patching_stub(PatchingStub* stub);

   124   void patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info);

   126   void comp_op(LIR_Condition condition, LIR_Opr src, LIR_Opr result, LIR_Op2* op);

   128   PatchingStub::PatchID patching_id(CodeEmitInfo* info);

   130  public:

   131   LIR_Assembler(Compilation* c);

   132   ~LIR_Assembler();

   133   C1_MacroAssembler* masm() const                { return _masm; }

   134   Compilation* compilation() const               { return _compilation; }

   135   ciMethod* method() const                       { return compilation()->method(); }

   137   CodeOffsets* offsets() const                   { return _compilation->offsets(); }

   138   int code_offset() const;

   139   address pc() const;

   141   int  initial_frame_size_in_bytes() const;

   142   int  bang_size_in_bytes() const;

   144   // test for constants which can be encoded directly in instructions

   145   static bool is_small_constant(LIR_Opr opr);

   147   static LIR_Opr receiverOpr();

   148   static LIR_Opr osrBufferPointer();

   150   // stubs

   151   void emit_slow_case_stubs();

   152   void emit_static_call_stub();

   153   void append_code_stub(CodeStub* op);

   154   void add_call_info_here(CodeEmitInfo* info)                              { add_call_info(code_offset(), info); }

   156   // code patterns

   157   int  emit_exception_handler();

   158   int  emit_unwind_handler();

   159   void emit_exception_entries(ExceptionInfoList* info_list);

   160   int  emit_deopt_handler();

   162   void emit_code(BlockList* hir);

   163   void emit_block(BlockBegin* block);

   164   void emit_lir_list(LIR_List* list);

   166   // any last minute peephole optimizations are performed here.  In

   167   // particular sparc uses this for delay slot filling.

   168   void peephole(LIR_List* list);

   170   void emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info);

   172   void return_op(LIR_Opr result);

   174   // returns offset of poll instruction

   175   int safepoint_poll(LIR_Opr result, CodeEmitInfo* info);

   177   void const2reg  (LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info);

   178   void const2stack(LIR_Opr src, LIR_Opr dest);

   179   void const2mem  (LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide);

   180   void reg2stack  (LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack);

   181   void reg2reg    (LIR_Opr src, LIR_Opr dest);

   182   void reg2mem    (LIR_Opr src, LIR_Opr dest, BasicType type,

   183                    LIR_PatchCode patch_code, CodeEmitInfo* info,

   184                    bool pop_fpu_stack, bool wide, bool unaligned);

   185   void stack2reg  (LIR_Opr src, LIR_Opr dest, BasicType type);

   186   void stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type);

   187   void mem2reg    (LIR_Opr src, LIR_Opr dest, BasicType type,

   188                    LIR_PatchCode patch_code,

   189                    CodeEmitInfo* info, bool wide, bool unaligned);

   191   void prefetchr  (LIR_Opr src);

   192   void prefetchw  (LIR_Opr src);

   194   void shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp);

   195   void shift_op(LIR_Code code, LIR_Opr left, jint  count, LIR_Opr dest);

   197   void move_regs(Register from_reg, Register to_reg);

   198   void swap_reg(Register a, Register b);

   200   void emit_op0(LIR_Op0* op);

   201   void emit_op1(LIR_Op1* op);

   202   void emit_op2(LIR_Op2* op);

   203   void emit_op3(LIR_Op3* op);

   204   void emit_opBranch(LIR_OpBranch* op);

   205   void emit_opLabel(LIR_OpLabel* op);

   206   void emit_arraycopy(LIR_OpArrayCopy* op);

   207   void emit_updatecrc32(LIR_OpUpdateCRC32* op);

   208   void emit_opConvert(LIR_OpConvert* op);

   209   void emit_alloc_obj(LIR_OpAllocObj* op);

   210   void emit_alloc_array(LIR_OpAllocArray* op);

   211   void emit_opTypeCheck(LIR_OpTypeCheck* op);

   212   void emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null);

   213   void emit_compare_and_swap(LIR_OpCompareAndSwap* op);

   214   void emit_lock(LIR_OpLock* op);

   215   void emit_call(LIR_OpJavaCall* op);

   216   void emit_rtcall(LIR_OpRTCall* op);

   217   void emit_profile_call(LIR_OpProfileCall* op);

   218   void emit_profile_type(LIR_OpProfileType* op);

   219   void emit_delay(LIR_OpDelay* op);

   221   void arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack);

   222 #ifdef MIPS64

   223   void arithmetic_frem(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info = NULL);

   224 #endif

   225   void arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info);

   226   void intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op);

   227 #ifdef ASSERT

   228   void emit_assert(LIR_OpAssert* op);

   229 #endif

   231   void logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest);

   233   void roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack);

   234   void move_op(LIR_Opr src, LIR_Opr result, BasicType type,

   235                LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned, bool wide);

   236   void volatile_move_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info);

   237   void comp_mem_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info);  // info set for null exceptions

   238   void comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr result, LIR_Op2* op);

   239   void cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr result, BasicType type);

   241   void call(        LIR_OpJavaCall* op, relocInfo::relocType rtype);

   242   void ic_call(     LIR_OpJavaCall* op);

   243   void vtable_call( LIR_OpJavaCall* op);

   245   void osr_entry();

   247   void build_frame();

   249   void throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info);

   250   void unwind_op(LIR_Opr exceptionOop);

   251   void monitor_address(int monitor_ix, LIR_Opr dst);

   253   void align_backward_branch_target();

   254   void align_call(LIR_Code code);

   256   void negate(LIR_Opr left, LIR_Opr dest);

   257   void leal(LIR_Opr left, LIR_Opr dest);

   259   void rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info);

   261   void membar();

   262   void membar_acquire();

   263   void membar_release();

   264   void membar_loadload();

   265   void membar_storestore();

   266   void membar_loadstore();

   267   void membar_storeload();

   268   void get_thread(LIR_Opr result);

   270   void verify_oop_map(CodeEmitInfo* info);

   272   void atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp);

   274 #ifdef TARGET_ARCH_x86

   275 # include "c1_LIRAssembler_x86.hpp"

   276 #endif

   277 #ifdef TARGET_ARCH_mips

   278 # include "c1_LIRAssembler_mips.hpp"

   279 #endif

   280 #ifdef TARGET_ARCH_sparc

   281 # include "c1_LIRAssembler_sparc.hpp"

   282 #endif

   283 #ifdef TARGET_ARCH_arm

   284 # include "c1_LIRAssembler_arm.hpp"

   285 #endif

   286 #ifdef TARGET_ARCH_ppc

   287 # include "c1_LIRAssembler_ppc.hpp"

   288 #endif

   290 };

   292 #endif // SHARE_VM_C1_C1_LIRASSEMBLER_HPP

src/share/vm/c1/c1_LIRAssembler.hpp@2d8a650513c2

src/share/vm/c1/c1_LIRAssembler.hpp

Mercurial > jdk8-mips64-public > hotspot / file revision

src/share/vm/c1/c1_LIRAssembler.hpp@2d8a650513c2

src/share/vm/c1/c1_LIRAssembler.hpp