Mercurial > jdk8-mips64-public > hotspot / file revision

 /*

  * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.

  * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.

  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

  *

  * This code is free software; you can redistribute it and/or modify it

  * under the terms of the GNU General Public License version 2 only, as

  * published by the Free Software Foundation.

  *

  * This code is distributed in the hope that it will be useful, but WITHOUT

  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

  * version 2 for more details (a copy is included in the LICENSE file that

  * accompanied this code).

  *

  * You should have received a copy of the GNU General Public License version

  * 2 along with this work; if not, write to the Free Software Foundation,

  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

  *

  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

  * or visit www.oracle.com if you need additional information or have any

  * questions.

  *

  */

 #include "precompiled.hpp"

 #include "asm/macroAssembler.hpp"

 #include "asm/macroAssembler.inline.hpp"

 #include "c1/c1_Compilation.hpp"

 #include "c1/c1_LIRAssembler.hpp"

 #include "c1/c1_MacroAssembler.hpp"

 #include "c1/c1_Runtime1.hpp"

 #include "c1/c1_ValueStack.hpp"

 #include "ci/ciArrayKlass.hpp"

 #include "ci/ciInstance.hpp"

 #include "gc_interface/collectedHeap.hpp"

 #include "memory/barrierSet.hpp"

 #include "memory/cardTableModRefBS.hpp"

 #include "nativeInst_mips.hpp"

 #include "oops/objArrayKlass.hpp"

 #include "runtime/sharedRuntime.hpp"

 #define __ _masm->

 static void select_different_registers(Register preserve,

 		Register extra,

 		Register &tmp1,

 		Register &tmp2) {

 	if (tmp1 == preserve) {

 		assert_different_registers(tmp1, tmp2, extra);

 		tmp1 = extra;

 	} else if (tmp2 == preserve) {

 		assert_different_registers(tmp1, tmp2, extra);

 		tmp2 = extra;

 	}

 	assert_different_registers(preserve, tmp1, tmp2);

 }

 static void select_different_registers(Register preserve,

 		Register extra,

 		Register &tmp1,

 		Register &tmp2,

 		Register &tmp3) {

 	if (tmp1 == preserve) {

 		assert_different_registers(tmp1, tmp2, tmp3, extra);

 		tmp1 = extra;

 	} else if (tmp2 == preserve) {

 		tmp2 = extra;

 	} else if (tmp3 == preserve) {

 		assert_different_registers(tmp1, tmp2, tmp3, extra);

 		tmp3 = extra;

 	}

 	assert_different_registers(preserve, tmp1, tmp2, tmp3);

 }

 // need add method Assembler::is_simm16 in assembler_gs2.hpp

 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {

 	if (opr->is_constant()) {

 		LIR_Const* constant = opr->as_constant_ptr();

 		switch (constant->type()) {

 			case T_INT: {

 				jint value = constant->as_jint();

 				return Assembler::is_simm16(value);

 				    }

 			default:

 				    return false;

 		}

 	}

 	return false;

 }

 //FIXME, which register should be used?

 LIR_Opr LIR_Assembler::receiverOpr() {

 	return FrameMap::_t0_oop_opr;

 }

 /*

 LIR_Opr LIR_Assembler::incomingReceiverOpr() {

 	return receiverOpr();

 }*/

 LIR_Opr LIR_Assembler::osrBufferPointer() {

 #ifdef _LP64

   Register r = receiverOpr()->as_register();

   return FrameMap::as_long_opr(r, r);

 #else

   return FrameMap::as_opr(receiverOpr()->as_register());

 #endif

 }

 //--------------fpu register translations-----------------------

 // FIXME:I do not know what's to do for mips fpu

 address LIR_Assembler::float_constant(float f) {

 	address const_addr = __ float_constant(f);

 	if (const_addr == NULL) {

 		bailout("const section overflow");

 		return __ code()->consts()->start();

 	} else {

 		return const_addr;

 	}

 }

 address LIR_Assembler::double_constant(double d) {

 	address const_addr = __ double_constant(d);

 	if (const_addr == NULL) {

 		bailout("const section overflow");

 		return __ code()->consts()->start();

 	} else {

 		return const_addr;

 	}

 }

 void LIR_Assembler::reset_FPU() {

 	Unimplemented();

 }

 void LIR_Assembler::set_24bit_FPU() {

 	Unimplemented();

 }

 //FIXME.

 void LIR_Assembler::fpop() {

 	// do nothing

 }

 void LIR_Assembler::fxch(int i) {

 	// do nothing

 }

 void LIR_Assembler::fld(int i) {

 	// do nothing

 }

 void LIR_Assembler::ffree(int i) {

 	// do nothing

 }

 void LIR_Assembler::breakpoint() {

   __ brk(17);

 }

 //FIXME, opr can not be float?

 void LIR_Assembler::push(LIR_Opr opr) {

 	if (opr->is_single_cpu()) {

 		__ push_reg(opr->as_register());

 	} else if (opr->is_double_cpu()) {

 		__ push_reg(opr->as_register_hi());

 		__ push_reg(opr->as_register_lo());

 	} else if (opr->is_stack()) {

 		__ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));

 	} else if (opr->is_constant()) {

 		LIR_Const* const_opr = opr->as_constant_ptr();

 		if (const_opr->type() == T_OBJECT) {

 			__ push_oop(const_opr->as_jobject());

 		} else if (const_opr->type() == T_INT) {

 			__ push_jint(const_opr->as_jint());

 		} else {

 			ShouldNotReachHere();

 		}

 	} else {

 		ShouldNotReachHere();

 	}

 }

 void LIR_Assembler::pop(LIR_Opr opr) {

 	if (opr->is_single_cpu() ) { 

 		__ pop(opr->as_register());

 	} else {

 		assert(false, "Must be single word register or floating-point register");

 	}

 }

 Address LIR_Assembler::as_Address(LIR_Address* addr) {

 #ifndef _LP64

   Register reg = addr->base()->as_register();

 #else

 //FIXME aoqi

   Register reg = addr->base()->is_single_cpu()? addr->base()->as_register() : addr->base()->as_register_lo();

 #endif

   // now we need this for parameter pass

   return Address(reg, addr->disp());

 }

 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {

   return as_Address(addr);

 }

 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {

 	Register reg = addr->base()->as_register();

 	return Address(reg, addr->disp()+longSize/2);

 }

 //void LIR_Assembler::osr_entry(IRScope* scope, int number_of_locks, Label* continuation, int osr_bci) { 

 void LIR_Assembler::osr_entry() { 

 	//  assert(scope->is_top_scope(), "inlined OSR not yet implemented");

 	offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());

 	BlockBegin* osr_entry = compilation()->hir()->osr_entry();

 	ValueStack* entry_state = osr_entry->state();

 	int number_of_locks = entry_state->locks_size();

 	// we jump here if osr happens with the interpreter

 	// state set up to continue at the beginning of the

 	// loop that triggered osr - in particular, we have

 	// the following registers setup:

 	//

 	// S7: interpreter locals pointer

 	// V1: interpreter locks pointer

 	// RA: return address

 	//T0: OSR buffer

 	// build frame

 	// ciMethod* m = scope->method();

 	ciMethod* m = compilation()->method();

 	__ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());

   // OSR buffer is

   //

   // locals[nlocals-1..0]

   // monitors[0..number_of_locks]

   //

   // locals is a direct copy of the interpreter frame so in the osr buffer

   // so first slot in the local array is the last local from the interpreter

   // and last slot is local[0] (receiver) from the interpreter

   //

   // Similarly with locks. The first lock slot in the osr buffer is the nth lock

   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock

   // in the interpreter frame (the method lock if a sync method)

   // Initialize monitors in the compiled activation.

   //   T0: pointer to osr buffer

   //

   // All other registers are dead at this point and the locals will be

   // copied into place by code emitted in the IR.

   Register OSR_buf = osrBufferPointer()->as_pointer_register();

   // note: we do osr only if the expression stack at the loop beginning is empty,

   //       in which case the spill area is empty too and we don't have to setup

   //       spilled locals

   //

   // copy monitors

   // V1: pointer to locks

   { 

 	  assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");

 	  int monitor_offset = BytesPerWord * method()->max_locals()+

 		  (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);

 	  for (int i = 0; i < number_of_locks; i++) {

 		  int slot_offset =monitor_offset - (i * BasicObjectLock::size())*BytesPerWord;

 #ifdef ASSERT

 		  { 

 			  Label L;

 			  //__ lw(AT, V1, slot_offset * BytesPerWord + BasicObjectLock::obj_offset_in_bytes());

 			  __ ld_ptr(AT, OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes());

 			  __ bne(AT, R0, L);

 			  __ delayed()->nop();

 			  __ stop("locked object is NULL");

 			  __ bind(L);

 		  }

 #endif

 		  __ ld_ptr(AT, OSR_buf, slot_offset + BasicObjectLock::lock_offset_in_bytes());

 		  __ st_ptr(AT, frame_map()->address_for_monitor_lock(i));

 		  __ ld_ptr(AT, OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes());

 		  __ st_ptr(AT, frame_map()->address_for_monitor_object(i));

 	  }

   }

 }

 int LIR_Assembler::check_icache() {

 	Register receiver = FrameMap::receiver_opr->as_register();

 	Register ic_klass = IC_Klass;

 	/*const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);

 	const bool do_post_padding = VerifyOops || UseCompressedOops;

 	if (!do_post_padding) {

 	    // insert some nops so that the verified entry point is aligned on CodeEntryAlignment

 	    while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {

 		__ nop();

 	    }

 	}*/

 	int offset = __ offset();

 	__ inline_cache_check(receiver, IC_Klass);

 	__ align(CodeEntryAlignment);

 	return offset;

 }

 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {

 	jobject o = NULL;

 	PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);

 	int oop_index = __ oop_recorder()->allocate_oop_index(o);

 	RelocationHolder rspec = oop_Relocation::spec(oop_index);

 	__ relocate(rspec);

 #ifndef _LP64

 //by_css

 	__ lui(reg, Assembler::split_high((int)o));

 	__ addiu(reg, reg, Assembler::split_low((int)o));

 #else

 //li may not pass NativeMovConstReg::verify. see nativeMovConstReg_at(pc_start()); in PatchingStub::install. by aoqi 

 	__ li48(reg, (long)o);

 #endif

 	// patching_epilog(patch, LIR_Op1::patch_normal, noreg, info);

 	patching_epilog(patch, lir_patch_normal, reg, info);

 }

 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register unused, int monitor_no, Register exception) {

 	if (exception->is_valid()) {

 		// preserve exception

 		// note: the monitor_exit runtime call is a leaf routine

 		//       and cannot block => no GC can happen

 		// The slow case (MonitorAccessStub) uses the first two stack slots

 		// ([SP+0] and [SP+4]), therefore we store the exception at [esp+8]

 		__ st_ptr(exception, SP, 2 * wordSize);

 	}

 	Register obj_reg  = obj_opr->as_register();

 	Register lock_reg = lock_opr->as_register();

 	// compute pointer to BasicLock

 	//Address lock_addr = frame_map()->address_for_monitor_lock_index(monitor_no);

 	Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no);

 	__ lea(lock_reg, lock_addr);

 	// unlock object

 	MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no);

 	// temporary fix: must be created after exceptionhandler, therefore as call stub

 	_slow_case_stubs->append(slow_case);

 	if (UseFastLocking) {

 		// try inlined fast unlocking first, revert to slow locking if it fails

 		// note: lock_reg points to the displaced header since the displaced header offset is 0!

 		assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");

 		__ unlock_object(NOREG, obj_reg, lock_reg, *slow_case->entry());

 	} else {

 		// always do slow unlocking

 		// note: the slow unlocking code could be inlined here, however if we use

 		//       slow unlocking, speed doesn't matter anyway and this solution is

 		//       simpler and requires less duplicated code - additionally, the

 		//       slow unlocking code is the same in either case which simplifies

 		//       debugging

 		__ b_far(*slow_case->entry());

 		__ delayed()->nop();

 	}

 	// done

 	__ bind(*slow_case->continuation());

 	if (exception->is_valid()) {

 		// restore exception

 		__ ld_ptr(exception, SP, 2 * wordSize);

 	}

 }

 // This specifies the esp decrement needed to build the frame

 int LIR_Assembler::initial_frame_size_in_bytes() const {

 	// if rounding, must let FrameMap know!

 //	return (frame_map()->framesize() - 2)  * BytesPerWord; // subtract two words to account for return address and link

   return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word))  * VMRegImpl::stack_slot_size;

 }

 int LIR_Assembler::emit_exception_handler() { 

   // if the last instruction is a call (typically to do a throw which

   // is coming at the end after block reordering) the return address

   // must still point into the code area in order to avoid assertion

   // failures when searching for the corresponding bci => add a nop

   // (was bug 5/14/1999 - gri)

   // Lazy deopt bug 4932387. If last instruction is a call then we

   // need an area to patch where we won't overwrite the exception

   // handler. This means we need 5 bytes. Could use a fat_nop 

   // but since this never gets executed it doesn't really make

   // much difference.

   // 

 	for (int i = 0; i < (NativeCall::instruction_size/BytesPerInstWord + 1) ; i++ ) {

 		__ nop();

 	}

   // generate code for exception handler

 	address handler_base = __ start_a_stub(exception_handler_size);

 	if (handler_base == NULL) {

 		//no enough space 

 		bailout("exception handler overflow");

 		return -1;

 	}

 	//compilation()->offsets()->set_value(CodeOffsets::Exceptions, code_offset()); 

 	// if the method does not have an exception handler, then there is

 	// no reason to search for one

 	//if (compilation()->has_exception_handlers() || JvmtiExport::can_post_exceptions()) {

 	     		// the exception oop and pc are in V0 and V1

 		// no other registers need to be preserved, so invalidate them

 		// check that there is really an exception

 //		__ verify_not_null_oop(V0);

 		// search an exception handler (V0: exception oop, V1: throwing pc)

 //		__ call(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id), 

 //				relocInfo::runtime_call_type);

 //		__ delayed()->nop();

     // if the call returns here, then the exception handler for particular

     // exception doesn't exist -> unwind activation and forward exception to caller

  // }

        int offset = code_offset();

 	// the exception oop is in V0

 	// no other registers need to be preserved, so invalidate them

 	// check that there is really an exception

 	__ verify_not_null_oop(V0);

         //FIXME:wuhui??

         //__ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));

         //__ delayed()->nop();

         __ should_not_reach_here();

         guarantee(code_offset() - offset <= exception_handler_size, "overflow");

         __ end_a_stub();

         return offset;

 	// unlock the receiver/klass if necessary

 	// V0: exception

 //	ciMethod* method = compilation()->method();

 //	if (method->is_synchronized() && GenerateSynchronizationCode) {

 //#ifndef _LP64

 //by_css

 //		monitorexit(FrameMap::_t0_oop_opr, FrameMap::_t6_opr, NOREG, 0, V0);

 //#else

 //		monitorexit(FrameMap::_t0_oop_opr, FrameMap::_a6_opr, NOREG, 0, V0);

 //#endif

 //	}

 	// unwind activation and forward exception to caller

 	// V0: exception

 //	__ jmp(Runtime1::entry_for(Runtime1::unwind_exception_id), 

 //				relocInfo::runtime_call_type);

 //	__ delayed()->nop();

 //	__ end_a_stub();

 }

 // Emit the code to remove the frame from the stack in the exception

 // // unwind path.

 int LIR_Assembler::emit_unwind_handler() {

 #ifndef PRODUCT

   if (CommentedAssembly) {

     _masm->block_comment("Unwind handler");

   }

 #endif

   int offset = code_offset();

  /* // Fetch the exception from TLS and clear out exception related thread state

     __ get_thread(rsi);

   __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset()));

   __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);

   __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);

   __ bind(_unwind_handler_entry);

   __ verify_not_null_oop(rax);

   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {

     __ mov(rsi, rax);  // Preserve the exception

   }

  // Preform needed unlocking

    MonitorExitStub* stub = NULL;

   if (method()->is_synchronized()) {

     monitor_address(0, FrameMap::rax_opr);

     stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);

     __ unlock_object(rdi, rbx, rax, *stub->entry());

     __ bind(*stub->continuation());

   }

   if (compilation()->env()->dtrace_method_probes()) {

     __ get_thread(rax);

     __ movptr(Address(rsp, 0), rax);

     __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());

     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));

   }

   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {

     __ mov(rax, rsi);  // Restore the exception

   }

   // remove the activation and dispatch to the unwind handler

     __ remove_frame(initial_frame_size_in_bytes());

   __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));

   // Emit the slow path assembly

     if (stub != NULL) {

     stub->emit_code(this);

   }

 */

   return offset;

 }

 int LIR_Assembler::emit_deopt_handler() {

 	// if the last instruction is a call (typically to do a throw which

 	// is coming at the end after block reordering) the return address

  	// must still point into the code area in order to avoid assertion

  	// failures when searching for the corresponding bci => add a nop

  	// (was bug 5/14/1999 - gri)

  	__ nop();

  	// generate code for exception handler

 	address handler_base = __ start_a_stub(deopt_handler_size);

 	if (handler_base == NULL) {

 		// not enough space left for the handler

 		bailout("deopt handler overflow");

 		return -1;

 	}

 	int offset = code_offset();

 //	compilation()->offsets()->set_value(CodeOffsets::Deopt, code_offset());

 	__ call(SharedRuntime::deopt_blob()->unpack());

 	__ delayed()->nop(); 

 	guarantee(code_offset() - offset <= deopt_handler_size, "overflow");

  	__ end_a_stub();

         return offset;

 }

 // Optimized Library calls

 // This is the fast version of java.lang.String.compare; it has not

 // OSR-entry and therefore, we generate a slow version for OSR's

 //void LIR_Assembler::emit_string_compare(IRScope* scope) {

 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {

 	// get two string object in T0&T1

 	//receiver already in T0

 	__ ld_ptr(T1, arg1->as_register());

 	//__ ld_ptr(T2, T0, java_lang_String::value_offset_in_bytes());	//value, T_CHAR array

 	__ load_heap_oop(T2, Address(T0, java_lang_String::value_offset_in_bytes()));

 	__ ld_ptr(AT, T0, java_lang_String::offset_offset_in_bytes());	//offset

 	__ shl(AT, 1);

 	__ add(T2, T2, AT);

 	__ addi(T2, T2, arrayOopDesc::base_offset_in_bytes(T_CHAR));

 	// Now T2 is the address of the first char in first string(T0)

 	add_debug_info_for_null_check_here(info);

 	//__ ld_ptr(T3, T1, java_lang_String::value_offset_in_bytes());

 	__ load_heap_oop(T3, Address(T1, java_lang_String::value_offset_in_bytes()));

 	__ ld_ptr(AT, T1, java_lang_String::offset_offset_in_bytes());

 	__ shl(AT, 1);

 	__ add(T3, T3, AT);

 	__ addi(T3, T3, arrayOopDesc::base_offset_in_bytes(T_CHAR));

 	// Now T3 is the address of the first char in second string(T1)

 #ifndef _LP64

 //by_css

 	// compute minimum length (in T4) and difference of lengths (V0)

 	Label L;

 	__ lw (T4, Address(T0, java_lang_String::count_offset_in_bytes())); 

 	// the length of the first string(T0)

 	__ lw (T5, Address(T1, java_lang_String::count_offset_in_bytes()));	

 	// the length of the second string(T1)

 	__ subu(V0, T4, T5);

 	__ blez(V0, L);

 	__ delayed()->nop();

 	__ move (T4, T5);

 	__ bind (L);

 	Label Loop, haveResult, LoopEnd;

 	__ bind(Loop);

 	__ beq(T4, R0, LoopEnd);

 	__ delayed();

 	__ addi(T2, T2, 2);

 	// compare current character

 	__ lhu(T5, T2, -2);

 	__ lhu(T6, T3, 0);

 	__ bne(T5, T6, haveResult);

 	__ delayed();

 	__ addi(T3, T3, 2);

 	__ b(Loop);

 	__ delayed()->addi(T4, T4, -1);

 	__ bind(haveResult);

 	__ subu(V0, T5, T6);

 	__ bind(LoopEnd);

 #else

 	// compute minimum length (in T4) and difference of lengths (V0)

 	Label L;

 	__ lw (A4, Address(T0, java_lang_String::count_offset_in_bytes())); 

 	// the length of the first string(T0)

 	__ lw (A5, Address(T1, java_lang_String::count_offset_in_bytes()));	

 	// the length of the second string(T1)

 	__ dsubu(V0, A4, A5);

 	__ blez(V0, L);

 	__ delayed()->nop();

 	__ move (A4, A5);

 	__ bind (L);

 	Label Loop, haveResult, LoopEnd;

 	__ bind(Loop);

 	__ beq(A4, R0, LoopEnd);

 	__ delayed();

 	__ daddi(T2, T2, 2);

 	// compare current character

 	__ lhu(A5, T2, -2);

 	__ lhu(A6, T3, 0);

 	__ bne(A5, A6, haveResult);

 	__ delayed();

 	__ daddi(T3, T3, 2);

 	__ b(Loop);

 	__ delayed()->addi(A4, A4, -1);

 	__ bind(haveResult);

 	__ dsubu(V0, A5, A6);

 	__ bind(LoopEnd);

 #endif

 	return_op(FrameMap::_v0_opr);

 }

 void LIR_Assembler::return_op(LIR_Opr result) {

   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == V0, "word returns are in V0");

   // Pop the stack before the safepoint code

   __ leave();

 #ifndef _LP64

   //by aoqi

   __ lui(AT, Assembler::split_high((intptr_t)os::get_polling_page() 

 	+ (SafepointPollOffset % os::vm_page_size())));

   __ relocate(relocInfo::poll_return_type);

   __ lw(AT, AT, Assembler::split_low((intptr_t)os::get_polling_page() 

 	+ (SafepointPollOffset % os::vm_page_size())));

 #else

   #ifndef OPT_SAFEPOINT

   // do not know how to handle relocate yet. do not know li or li64 should be used neither. by aoqi. 20111207 FIXME.

   __ li48(AT, (intptr_t)os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()));

   __ relocate(relocInfo::poll_return_type);

   __ lw(AT, AT, 0); 

   #else

   __ lui(AT, Assembler::split_high((intptr_t)os::get_polling_page() + (SafepointPollOffset % os::vm_page_size())));

   __ relocate(relocInfo::poll_return_type);

   __ lw(AT, AT, Assembler::split_low((intptr_t)os::get_polling_page() + (SafepointPollOffset % os::vm_page_size())));

   #endif

 #endif

   __ jr(RA);

   __ delayed()->nop();

 }

 //read protect mem to R0 won't cause the exception only in godson-2e, So I modify R0 to AT .@jerome,11/25,2006

 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {

   assert(info != NULL, "info must not be null for safepoint poll");

   int offset = __ offset();

   Register r = tmp->as_register();

 #ifndef _LP64

 //by aoqi

   __ lui(r, Assembler::split_high((intptr_t)os::get_polling_page() + (SafepointPollOffset % os::vm_page_size())));

   add_debug_info_for_branch(info);

   __ relocate(relocInfo::poll_type);

   __ lw(AT, r, Assembler::split_low((intptr_t)os::get_polling_page() + (SafepointPollOffset % os::vm_page_size())));

 #else

   #ifndef OPT_SAFEPOINT

   // do not know how to handle relocate yet. do not know li or li64 should be used neither. by aoqi. 20111207 FIXME.

   //__ lui(r, Assembler::split_high((intptr_t)os::get_polling_page() + (SafepointPollOffset % os::vm_page_size())));

   __ li48(r, (intptr_t)os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()));

   add_debug_info_for_branch(info);

   __ relocate(relocInfo::poll_type);

   //__ lw(AT, r, Assembler::split_low((intptr_t)os::get_polling_page() + (SafepointPollOffset % os::vm_page_size())));

   __ lw(AT, r, 0);

   #else

   __ lui(r, Assembler::split_high((intptr_t)os::get_polling_page() + (SafepointPollOffset % os::vm_page_size())));

   add_debug_info_for_branch(info);

   __ relocate(relocInfo::poll_type);

   __ lw(AT, r, Assembler::split_low((intptr_t)os::get_polling_page() + (SafepointPollOffset % os::vm_page_size())));

   #endif

 #endif

   return offset; 

 }

 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {

 	if (from_reg != to_reg) __ move(to_reg, from_reg);

 }

 void LIR_Assembler::swap_reg(Register a, Register b) {

 	__ xorr(a, a, b);

 	__ xorr(b, a, b);

 	__ xorr(a, a, b);

 }

 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {

   assert(src->is_constant(), "should not call otherwise");

   assert(dest->is_register(), "should not call otherwise");

   LIR_Const* c = src->as_constant_ptr();

   switch (c->type()) {

     case T_INT:

       {

 	jint con = c->as_jint();

 	if (dest->is_single_cpu()) {

 	  assert(patch_code == lir_patch_none, "no patching handled here");

 	  __ move(dest->as_register(), con);

 	} else {

 	  assert(dest->is_single_fpu(), "wrong register kind");

 	  __ move(AT, con);

 	  __ mtc1(AT, dest->as_float_reg());

 	}

       }

       break;

     case T_LONG:

       {

 #ifndef _LP64

 	jlong con = c->as_jlong();

 	jint* conhi = (jint*)&con + 1;

 	jint* conlow = (jint*)&con;

 	if (dest->is_double_cpu()) {

 	  __ move(dest->as_register_lo(), *conlow);

 	  __ move(dest->as_register_hi(), *conhi);

 	} else {

 	  //	assert(dest->is_double(), "wrong register kind");

 	  __ move(AT, *conlow);

 	  __ mtc1(AT, dest->as_double_reg());

 	  __ move(AT, *conhi);

 	  __ mtc1(AT, dest->as_double_reg()+1);

 	}

 #else

 	if (dest->is_double_cpu()) {

 	  __ li(dest->as_register_lo(), c->as_jlong());

 	} else {

 	  __ li(dest->as_register(), c->as_jlong());

 	}

 #endif

       }

       break;

     case T_OBJECT:

       {

 	if (patch_code == lir_patch_none) {

 	  jobject2reg(c->as_jobject(), dest->as_register());

 	} else {

 	  jobject2reg_with_patching(dest->as_register(), info);

 	}

       }

       break;

     case T_FLOAT:

       {

 	address const_addr = float_constant(c->as_jfloat());

 	assert (const_addr != NULL, "must create float constant in the constant table");

 	if (dest->is_single_fpu()) {

 	  __ relocate(relocInfo::internal_pc_type);

 #ifndef _LP64

 	  //by_css

 	  __ lui(AT, Assembler::split_high((int)const_addr));

 	  __ addiu(AT, AT, Assembler::split_low((int)const_addr));

 #else

 	  __ li48(AT, (long)const_addr);

 #endif

 	  __ lwc1(dest->as_float_reg(), AT, 0);

 	} else {

 	  assert(dest->is_single_cpu(), "Must be a cpu register.");

 	  assert(dest->as_register() != AT, "AT can not be allocated.");

 	  __ relocate(relocInfo::internal_pc_type);

 #ifndef _LP64

 	  //by_css

 	  __ lui(AT, Assembler::split_high((int)const_addr));

 	  __ addiu(AT, AT, Assembler::split_low((int)const_addr));

 #else

 	  __ li48(AT, (long)const_addr);

 #endif

 	  __ lw(dest->as_register(), AT, 0); 

 	}

       }

       break;

     case T_DOUBLE:

       {

 	address const_addr = double_constant(c->as_jdouble());

 	assert (const_addr != NULL, "must create double constant in the constant table");

 	if (dest->is_double_fpu()) {

 	  __ relocate(relocInfo::internal_pc_type);

 #ifndef _LP64

 	  //by_css

 	  __ lui(AT, Assembler::split_high((int)const_addr));

 	  __ addiu(AT, AT, Assembler::split_low((int)const_addr));

 	  __ lwc1(dest->as_double_reg(), AT, 0);

 	  __ lwc1(dest->as_double_reg()+1, AT, 4);					

 #else

 	  __ li48(AT, (long)const_addr);

 	  __ ldc1(dest->as_double_reg(), AT, 0);

 #endif

 	} else {

 	  assert(dest->as_register_lo() != AT, "AT can not be allocated.");

 	  assert(dest->as_register_hi() != AT, "AT can not be allocated.");

 	  __ relocate(relocInfo::internal_pc_type);

 #ifndef _LP64

 	  //by_css

 	  __ lui(AT, Assembler::split_high((int)const_addr));

 	  __ addiu(AT, AT, Assembler::split_low((int)const_addr));

 	  __ lw(dest->as_register_lo(), AT, 0);

 	  __ lw(dest->as_register_hi(), AT, 4);

 #else

 	  __ li48(AT, (long)const_addr);

 	  __ ld(dest->as_register_lo(), AT, 0);

 #endif

 	}

       }

       break;

     default:

       ShouldNotReachHere();

   }

 }

 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {

   assert(src->is_constant(), "should not call otherwise");

   assert(dest->is_stack(), "should not call otherwise");

   LIR_Const* c = src->as_constant_ptr();

   switch (c->type()) {

     case T_INT:  // fall through

     case T_FLOAT:

       __ move(AT, c->as_jint_bits());

       __ sw(AT, frame_map()->address_for_slot(dest->single_stack_ix()));

       break;

     case T_OBJECT:

       if (c->as_jobject() == NULL) {

 	__ st_ptr(R0, frame_map()->address_for_slot(dest->single_stack_ix()));

       } else {

 	int oop_index = __ oop_recorder()->find_index(c->as_jobject());

 	RelocationHolder rspec = oop_Relocation::spec(oop_index);

 	__ relocate(rspec);

 #ifndef _LP64

 	//by_css

 	__ lui(AT, Assembler::split_high((int)c->as_jobject()));

 	__ addiu(AT, AT, Assembler::split_low((int)c->as_jobject()));

 #else

 	__ li48(AT, (long)c->as_jobject());

 #endif

 	__ st_ptr(AT, frame_map()->address_for_slot(dest->single_stack_ix()));

       }

       break;

     case T_LONG:  // fall through

     case T_DOUBLE:

 #ifndef _LP64

       __ move(AT, c->as_jint_lo_bits());

       __ sw(AT, frame_map()->address_for_slot(dest->double_stack_ix(),

 	    lo_word_offset_in_bytes));

       __ move(AT, c->as_jint_hi_bits());

       __ sw(AT, frame_map()->address_for_slot(dest->double_stack_ix(),

 	    hi_word_offset_in_bytes));

 #else

       __ move(AT, c->as_jlong_bits());

       __ sd(AT, frame_map()->address_for_slot(dest->double_stack_ix(),

 	    lo_word_offset_in_bytes));

 #endif

       break;

     default:

       ShouldNotReachHere();

   }

 }

 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {

   assert(src->is_constant(), "should not call otherwise");

   assert(dest->is_address(), "should not call otherwise");

   LIR_Const* c = src->as_constant_ptr();

   LIR_Address* addr = dest->as_address_ptr();

   int null_check_here = code_offset();

   switch (type) {

     case T_LONG: // fall through

     case T_DOUBLE:

 #ifndef _LP64

       __ move(AT, c->as_jint_hi_bits());

       __ sw(AT, as_Address_hi(addr));

       __ move(AT, c->as_jint_lo_bits());

       __ sw(AT, as_Address_lo(addr));

 #else

       if(c->as_jlong_bits() != 0)

       {

         /* DoublePrint: -0.0

          *   (gdb) print /x -9223372036854775808

          *   $1 = 0x8000000000000000

          */

         __ li64(AT, c->as_jlong_bits());

         __ sd(AT, as_Address_lo(addr));

       }

       else 

         __ sd(R0, as_Address(addr));

 #endif

       break; 

     case T_OBJECT:  // fall through

     case T_ARRAY:   

       if (c->as_jobject() == NULL){

 	  if (UseCompressedOops && !wide) {

 	    __ sw(R0, as_Address(addr));

 	  } else {

 	      __ st_ptr(R0, as_Address(addr));

 	  }

       } else {

 	int oop_index = __ oop_recorder()->find_index(c->as_jobject());

 	RelocationHolder rspec = oop_Relocation::spec(oop_index);

 	__ relocate(rspec);

 #ifndef _LP64

 	__ lui(AT, Assembler::split_high((int)c->as_jobject()));

 	__ addiu(AT, AT, Assembler::split_low((int)c->as_jobject()));

 	__ st_ptr(AT, as_Address(addr));

 	null_check_here = code_offset();

 #else

 	//by_css

 	__ li64(AT, (long)c->as_jobject());

 	if (UseCompressedOops && !wide) {

 	    __ encode_heap_oop(AT);

 	    null_check_here = code_offset();

 	    __ sw(AT, as_Address(addr));

 	} else {

 	    __ st_ptr(AT, as_Address(addr));

 	}

 #endif

       }

       break;

     case T_INT:     // fall through

     case T_FLOAT:  

       if(c->as_jint_bits() != 0)

       {

         __ move(AT, c->as_jint_bits());

         __ sw(AT, as_Address(addr));

       }

       else

         __ sw(R0, as_Address(addr));

       break;

     case T_BOOLEAN: // fall through

     case T_BYTE:    

       if(c->as_jint() != 0)

       {

         __ move(AT, c->as_jint());

         __ sb(AT, as_Address(addr));

       }

       else

         __ sb(R0, as_Address(addr));

       break;

     case T_CHAR:    // fall through

     case T_SHORT:   

       if(c->as_jint() != 0)

       {

         __ move(AT, c->as_jint());

         __ sh(AT, as_Address(addr));

       }

       else

         __ sh(R0, as_Address(addr));

       break;

     default: ShouldNotReachHere();

   };

   if (info != NULL) add_debug_info_for_null_check(null_check_here, info);

 }

 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {

   assert(src->is_register(), "should not call otherwise");

   assert(dest->is_register(), "should not call otherwise");

   if (dest->is_float_kind() && src->is_float_kind()) {

   // float to float moves

     if (dest->is_single_fpu()) {

       assert(src->is_single_fpu(), "must both be float");

       __ mov_s(dest->as_float_reg(), src->as_float_reg());

     } else {

       assert(src->is_double_fpu(), "must bothe be double");

       __ mov_d( dest->as_double_reg(),src->as_double_reg());

     }

   } else if (!dest->is_float_kind() && !src->is_float_kind()) {

     // int to int moves

     if (dest->is_single_cpu()) {

 #ifdef _LP64

 //FIXME aoqi: copy from x86

       if (src->type() == T_LONG) {

 	// Can do LONG -> OBJECT

 	move_regs(src->as_register_lo(), dest->as_register());

 	return;

       }

 #endif

       assert(src->is_single_cpu(), "must match");

       if (dest->type() == T_INT) {

 	__ move_u32(dest->as_register(), src->as_register());

       }

       else

 	move_regs(src->as_register(), dest->as_register());

     } else if (dest->is_double_cpu()) {

 #ifdef _LP64

       if (src->type() == T_OBJECT || src->type() == T_ARRAY) {

 	// Surprising to me but we can see move of a long to t_object

 	__ verify_oop(src->as_register());

 	move_regs(src->as_register(), dest->as_register_lo());

 	return;

       }

 #endif

       Register f_lo;

       Register f_hi;

       Register t_lo;

       Register t_hi;

       if (src->is_single_cpu())

       {

         f_lo = src->as_register();

         t_lo = dest->as_register_lo();

       }

       else

       {

         f_lo = src->as_register_lo();

         f_hi = src->as_register_hi();

         t_lo = dest->as_register_lo();

         t_hi = dest->as_register_hi();

         assert(f_hi == f_lo, "must be same");

         assert(t_hi == t_lo, "must be same");

       }

 #ifdef _LP64

       move_regs(f_lo, t_lo);

 #else

       /*

 	 if (src->as_register_hi() != dest->as_register_lo()) {

 	 move_regs(src->as_register_lo(), dest->as_register_lo());

 	 move_regs(src->as_register_hi(), dest->as_register_hi());

 	 } else if (src->as_register_lo() != dest->as_register_hi()) {

 	 move_regs(src->as_register_hi(), dest->as_register_hi());     

 	 move_regs(src->as_register_lo(), dest->as_register_lo());

 	 } else {

 	 swap_reg(src->as_register_lo(), src->as_register_hi());

 	 }

        */

       assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");

       if (f_lo == t_hi && f_hi == t_lo) {

 	swap_reg(f_lo, f_hi);

       } else if (f_hi == t_lo) {

 	assert(f_lo != t_hi, "overwriting register");

 	move_regs(f_hi, t_hi);

 	move_regs(f_lo, t_lo);

       } else {

 	assert(f_hi != t_lo, "overwriting register");

 	move_regs(f_lo, t_lo);

 	move_regs(f_hi, t_hi);

       }

 #endif // LP64

     }

   } else {

     // float to int or int to float moves

     if (dest->is_double_cpu()) {

       assert(src->is_double_fpu(), "must match");

       __ mfc1(dest->as_register_lo(), src->as_double_reg());

 #ifndef _LP64

       __ mfc1(dest->as_register_hi(), src->as_double_reg() + 1);

 #endif

     } else if (dest->is_single_cpu()) {

       assert(src->is_single_fpu(), "must match");

       __ mfc1(dest->as_register(), src->as_float_reg());

     } else if (dest->is_double_fpu()) {

       assert(src->is_double_cpu(), "must match");

       __ mtc1(src->as_register_lo(), dest->as_double_reg());

 #ifndef _LP64

       __ mtc1(src->as_register_hi(), dest->as_double_reg() + 1);

 #endif

     } else if (dest->is_single_fpu()) {

       assert(src->is_single_cpu(), "must match");

       __ mtc1(src->as_register(), dest->as_float_reg());

     }

   }

 }

 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type,bool pop_fpu_stack) {

   assert(src->is_register(), "should not call otherwise");

   assert(dest->is_stack(), "should not call otherwise");

   if (src->is_single_cpu()) {

     Address dst = frame_map()->address_for_slot(dest->single_stack_ix());

     if (type == T_OBJECT || type == T_ARRAY) {

       __ verify_oop(src->as_register());

     }

 #ifdef _LP64

     if (type == T_INT)

     __ sw(src->as_register(),dst);  

     else

 #endif

     __ st_ptr(src->as_register(),dst);  

   } else if (src->is_double_cpu()) {

     Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);

     Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);

      __ st_ptr(src->as_register_lo(),dstLO);

      NOT_LP64(__ st_ptr(src->as_register_hi(),dstHI));

   }else if (src->is_single_fpu()) {

     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());

     __ swc1(src->as_float_reg(), dst_addr);

   } else if (src->is_double_fpu()) {

     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());

 #ifndef _LP64

     __ swc1(src->as_double_reg(), dst_addr);

     __ swc1(src->as_double_reg() + 1, dst_addr.base(), dst_addr.disp() + 4);

 #else

     __ sdc1(src->as_double_reg(), dst_addr);

 #endif

   } else {

     ShouldNotReachHere();

   }

 }

 //FIXME

 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info,bool pop_fpu_stack, bool wide,  bool/*unaliged*/) {

   LIR_Address* to_addr = dest->as_address_ptr();

   //Register dest_reg = to_addr->base()->as_register();	

   // FIXME aoqi

   Register dest_reg = to_addr->base()->is_single_cpu()? to_addr->base()->as_register() : to_addr->base()->as_register_lo();

   PatchingStub* patch = NULL;

   bool needs_patching = (patch_code != lir_patch_none);

   Register disp_reg = NOREG;

   int disp_value = to_addr->disp();

   /*

    the start position of patch template is labeled by "new PatchingStub(...)"

    during patch, T9 will be changed and not restore

    that's why we use S7 but not T9 as compressed_src here

    */

   Register compressed_src = S7;

   if (type == T_ARRAY || type == T_OBJECT) {

     __ verify_oop(src->as_register());

 #ifdef _LP64

     if (UseCompressedOops && !wide) {

 	__ move(compressed_src, src->as_register());

 	__ encode_heap_oop(compressed_src);

     }

 #endif

   }

   if (needs_patching) {

     patch = new PatchingStub(_masm, PatchingStub::access_field_id);

     assert(!src->is_double_cpu() || 

 	patch_code == lir_patch_none || 

 	patch_code == lir_patch_normal, 

 	"patching doesn't match register");

     Address toa = as_Address(to_addr);

     assert(toa.disp() != 0, "must have");

   }

   if (info != NULL) {

     add_debug_info_for_null_check_here(info);

   }

   if (needs_patching) {

     disp_reg = AT;

     __ lui(AT, Assembler::split_high(disp_value));

     __ addiu(AT, AT, Assembler::split_low(disp_value));

   } else if (!Assembler::is_simm16(disp_value)) { 

     disp_reg = AT;

     __ lui(AT, Assembler::split_high(disp_value));

   }

   int offset = code_offset();

   switch(type) {

     case T_DOUBLE:

       assert(src->is_double_fpu(), "just check");

       if (disp_reg == noreg) {

 #ifndef _LP64

 	__ swc1(src->as_double_reg(), dest_reg, disp_value);

 	__ swc1(src->as_double_reg()+1, dest_reg, disp_value+4);

 #else

 	__ sdc1(src->as_double_reg(), dest_reg, disp_value);

 #endif

       } else if (needs_patching) {

 	__ add(AT, dest_reg, disp_reg);

 #ifndef _LP64

 	__ swc1(src->as_double_reg(), AT, 0);

 	__ swc1(src->as_double_reg()+1, AT, 4);

 #else

 	__ sdc1(src->as_double_reg(), AT, 0);

 #endif

       } else {

 	__ add(AT, dest_reg, disp_reg);

 #ifndef _LP64

 	__ swc1(src->as_double_reg(), AT, Assembler::split_low(disp_value));

 	__ swc1(src->as_double_reg()+1, AT, Assembler::split_low(disp_value) + 4);

 #else

 	__ sdc1(src->as_double_reg(), AT, Assembler::split_low(disp_value));

 #endif

       }

       break;

     case T_FLOAT:

       if (disp_reg == noreg) {

 	__ swc1(src->as_float_reg(), dest_reg, disp_value);

       } else if(needs_patching) {

 	__ add(AT, dest_reg, disp_reg);

 	__ swc1(src->as_float_reg(), AT, 0);

       } else {

 	__ add(AT, dest_reg, disp_reg);

 	__ swc1(src->as_float_reg(), AT, Assembler::split_low(disp_value));

       }

       break;

     case T_LONG: {

 		   Register from_lo = src->as_register_lo();

 		   Register from_hi = src->as_register_hi();

 #ifdef _LP64

 		   if (needs_patching) {

 		     __ add(AT, dest_reg, disp_reg);

 		     __ st_ptr(from_lo, AT, 0);

 		   } else {

 		     __ st_ptr(from_lo, as_Address_lo(to_addr));

 		   }

 #else

 		   Register base = to_addr->base()->as_register();

 		   Register index = noreg;

 		   if (to_addr->index()->is_register()) {

 		     index = to_addr->index()->as_register();

 		   }

 		   if (base == from_lo || index == from_lo) {

 		     assert(base != from_hi, "can't be");

 		     assert(index == noreg || (index != base && index != from_hi), "can't handle this");

 		     if (needs_patching) {

 		       __ add(AT, dest_reg, disp_reg);

 		       NOT_LP64(__ st_ptr(from_hi, AT, longSize/2);)

 			 __ st_ptr(from_lo, AT, 0);

 		     } else {

 		       __ st_ptr(from_hi, as_Address_hi(to_addr));  

 		       __ st_ptr(from_lo, as_Address_lo(to_addr));

 		     }

 		   } else {

 		     assert(index == noreg || (index != base && index != from_lo), "can't handle this");

 		     if (needs_patching) {

 		       __ add(AT, dest_reg, disp_reg);

 		       __ st_ptr(from_lo, AT, 0);

 		       __ st_ptr(from_hi, AT, longSize/2);  

 		     } else {

 		       __ st_ptr(from_lo, as_Address_lo(to_addr)); 

 		       __ st_ptr(from_hi, as_Address_hi(to_addr));  

 		     }

 		   }

 #endif

 		   break;

 		 }

     case T_ARRAY:

     case T_OBJECT:

 #ifdef _LP64

 		 if (UseCompressedOops && !wide) {

 		     if (disp_reg == noreg) {

 			 __ sw(compressed_src, dest_reg, disp_value);

 		     } else if (needs_patching) {

 			 __ add(AT, dest_reg, disp_reg);

 			 __ sw(compressed_src, AT, 0);

 		     } else {

 			 __ add(AT, dest_reg, disp_reg);

 			 __ sw(compressed_src, AT, Assembler::split_low(disp_value));

 		     } 

 		 } else {

 		     if (disp_reg == noreg) {

 			 __ st_ptr(src->as_register(), dest_reg, disp_value);

 		     } else if (needs_patching) {

 			 __ add(AT, dest_reg, disp_reg);

 			 __ st_ptr(src->as_register(), AT, 0);

 		     } else {

 			 __ add(AT, dest_reg, disp_reg);

 			 __ st_ptr(src->as_register(), AT, Assembler::split_low(disp_value));

 		     } 

 		 }

 		 break;

 #endif

     case T_ADDRESS:

 #ifdef _LP64

 		 if (disp_reg == noreg) {

 		   __ st_ptr(src->as_register(), dest_reg, disp_value);

 		 } else if (needs_patching) {

 		   __ add(AT, dest_reg, disp_reg);

 		   __ st_ptr(src->as_register(), AT, 0);

 		 } else {

 		   __ add(AT, dest_reg, disp_reg);

 		   __ st_ptr(src->as_register(), AT, Assembler::split_low(disp_value));

 		 }

 		 break;

 #endif

     case T_INT:

 		 if (disp_reg == noreg) {

 		   __ sw(src->as_register(), dest_reg, disp_value);

 		 } else if (needs_patching) {

 		   __ add(AT, dest_reg, disp_reg);

 		   __ sw(src->as_register(), AT, 0);

 		 } else {

 		   __ add(AT, dest_reg, disp_reg);

 		   __ sw(src->as_register(), AT, Assembler::split_low(disp_value));

 		 }

 		 break;

     case T_CHAR:

     case T_SHORT:

 		 if (disp_reg == noreg) {

 		   __ sh(src->as_register(), dest_reg, disp_value);

 		 } else if (needs_patching) {

 		   __ add(AT, dest_reg, disp_reg);

 		   __ sh(src->as_register(), AT, 0);

 		 } else {

 		   __ add(AT, dest_reg, disp_reg);

 		   __ sh(src->as_register(), AT, Assembler::split_low(disp_value));

 		 }

 		 break;

     case T_BYTE:

     case T_BOOLEAN:

 		 assert(src->is_single_cpu(), "just check");

 		 if (disp_reg == noreg) {

 		   __ sb(src->as_register(), dest_reg, disp_value);

 		 } else if (needs_patching) {

 		   __ add(AT, dest_reg, disp_reg);

 		   __ sb(src->as_register(), AT, 0);

 		 } else {

 		   __ add(AT, dest_reg, disp_reg);

 		   __ sb(src->as_register(), AT, Assembler::split_low(disp_value));

 		 }

 		 break;

     default:

 		 ShouldNotReachHere();

   }

   if (needs_patching) {

     patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);

   }

 }

 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {

   assert(src->is_stack(), "should not call otherwise");

   assert(dest->is_register(), "should not call otherwise");

   if (dest->is_single_cpu()) {

 #ifdef _LP64

     if (type == T_INT)

       __ lw(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));

     else

 #endif

     __ ld_ptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));

     if (type == T_ARRAY || type == T_OBJECT) {

       __ verify_oop(dest->as_register());

     }

   } else if (dest->is_double_cpu()) {

 #ifdef _LP64

 /* java.util.concurrent.locks.ReentrantReadWriteLock$Sync::tryAcquire

    88 move [stack:2|L] [a5a5|J] 

 OpenJDK 64-Bit Client VM warning: /mnt/openjdk6-mips/hotspot/src/share/c1/c1_LIR.hpp, 397 , assert(is_double_stack() && !is_virtual(),"type check")

 OpenJDK 64-Bit Client VM warning: /mnt/openjdk6-mips/hotspot/src/share/c1/c1_LIR.hpp, 397 , assert(is_double_stack() && !is_virtual(),"type check")

    0x000000556197af8c: ld a5, 0x50(sp)

 */

     Address src_addr_LO;

     if (src->is_single_stack())

        src_addr_LO = frame_map()->address_for_slot(src->single_stack_ix(),lo_word_offset_in_bytes);

     else if (src->is_double_stack())

        src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(),lo_word_offset_in_bytes);

     else

        ShouldNotReachHere();

 #else

     Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(),lo_word_offset_in_bytes);

     Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);

 #endif

 #ifdef _LP64

     if (src->type() == T_INT)

       __ lw(dest->as_register_lo(), src_addr_LO);

     else

 #endif

     __ ld_ptr(dest->as_register_lo(), src_addr_LO);

     NOT_LP64(__ ld_ptr(dest->as_register_hi(), src_addr_HI));

   }else if (dest->is_single_fpu()) {

     Address addr = frame_map()->address_for_slot(src->single_stack_ix());

     __ lwc1(dest->as_float_reg(), addr);

   } else if (dest->is_double_fpu())  {

     Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(),lo_word_offset_in_bytes);

 #ifndef _LP64

     Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);

     __ lwc1(dest->as_double_reg(), src_addr_LO);

     __ lwc1(dest->as_double_reg()+1, src_addr_HI);

 #else

     __ ldc1(dest->as_double_reg(), src_addr_LO);

 #endif

   } else {

     ShouldNotReachHere();

     /*

     assert(dest->is_single_cpu(), "cannot be anything else but a single cpu");

     assert(type!= T_ILLEGAL, "Bad type in stack2reg")

     Address addr = frame_map()->address_for_slot(src->single_stack_ix());

     __ lw(dest->as_register(), addr);

     */

   }

 }

 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {

   if (src->is_single_stack()) {

       /*

        * 2012/5/23 Jin: YozoOffice(-Xcomp) corrupts in "New File -> word"

        *

        *      [b.q.e.a.z::bw()]

        *      move [stack:15|L] [stack:17|L]

        *         0x00000055584e7cf4: lw at, 0x78(sp)  <--- error!

        *         0x00000055584e7cf8: sw at, 0x88(sp)

        */

       if (type == T_OBJECT )

       {

         __ ld(AT, frame_map()->address_for_slot(src ->single_stack_ix())); 

         __ sd(AT, frame_map()->address_for_slot(dest->single_stack_ix()));

       }

       else

       {

         __ lw(AT, frame_map()->address_for_slot(src ->single_stack_ix())); 

         __ sw(AT, frame_map()->address_for_slot(dest->single_stack_ix()));

       }

   } else if (src->is_double_stack()) {

 #ifndef _LP64

       __ lw(AT, frame_map()->address_for_slot(src ->double_stack_ix())); 

       __ sw(AT, frame_map()->address_for_slot(dest->double_stack_ix())); 

       __ lw(AT, frame_map()->address_for_slot(src ->double_stack_ix(),4)); 

       __ sw(AT, frame_map()->address_for_slot(dest ->double_stack_ix(),4)); 

 #else

       __ ld_ptr(AT, frame_map()->address_for_slot(src ->double_stack_ix())); 

       __ st_ptr(AT, frame_map()->address_for_slot(dest->double_stack_ix())); 

 #endif

   } else {

     ShouldNotReachHere();

   }

 }

 // if patching needed, be sure the instruction at offset is a MoveMemReg

 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool) {

   assert(src->is_address(), "should not call otherwise");

   assert(dest->is_register(), "should not call otherwise");

   LIR_Address* addr = src->as_address_ptr();

   //Address from_addr = as_Address(addr);

   //Register src_reg = addr->base()->as_register();

   // FIXME aoqi

   Register src_reg = addr->base()->is_single_cpu()? addr->base()->as_register() : addr->base()->as_register_lo();

   Register disp_reg = noreg;

   int disp_value = addr->disp();

   bool needs_patching = (patch_code != lir_patch_none);

   PatchingStub* patch = NULL;

   if (needs_patching) {

     patch = new PatchingStub(_masm, PatchingStub::access_field_id);

   }

   // we must use lui&addiu, 

   if (needs_patching) {

     disp_reg = AT;

     __ lui(AT, Assembler::split_high(disp_value));

     __ addiu(AT, AT, Assembler::split_low(disp_value));

   } else if (!Assembler::is_simm16(disp_value)) {

     disp_reg = AT;

     __ lui(AT, Assembler::split_high(disp_value));

   }

   // remember the offset of the load.  The patching_epilog must be done

   // before the call to add_debug_info, otherwise the PcDescs don't get

   // entered in increasing order.

   int offset = code_offset();

   switch(type) {

     case T_BOOLEAN:

     case T_BYTE: {

 		   //assert(to_reg.is_word(), "just check");

 		   if (disp_reg == noreg) {

 		     __ lb(dest->as_register(), src_reg, disp_value);

 		   } else if (needs_patching) {

 		     __ add(AT, src_reg, disp_reg);

 		     offset = code_offset();

 		     __ lb(dest->as_register(), AT, 0);

 		   } else {

 		     __ add(AT, src_reg, disp_reg);

 		     offset = code_offset();

 		     __ lb(dest->as_register(), AT, Assembler::split_low(disp_value));

 		   }

 		 }

 		 break;

     case T_CHAR: {

 		   //assert(to_reg.is_word(), "just check");

 		   if (disp_reg == noreg) {

 		     __ lhu(dest->as_register(), src_reg, disp_value);

 		   } else if (needs_patching) {

 		     __ add(AT, src_reg, disp_reg);

 		     offset = code_offset();

 		     __ lhu(dest->as_register(), AT, 0);

 		   } else {

 		     __ add(AT, src_reg, disp_reg);

 		     offset = code_offset();

 		     __ lhu(dest->as_register(), AT, Assembler::split_low(disp_value));

 		   }

 		 }

 		 break;

     case T_SHORT: {

 		    //	assert(to_reg.is_word(), "just check");

 		    if (disp_reg == noreg) {

 		      __ lh(dest->as_register(), src_reg, disp_value);

 		    } else if (needs_patching) {

 		      __ add(AT, src_reg, disp_reg);

 		      offset = code_offset();

 		      __ lh(dest->as_register(), AT, 0);

 		    } else {

 		      __ add(AT, src_reg, disp_reg);

 		      offset = code_offset();

 		      __ lh(dest->as_register(), AT, Assembler::split_low(disp_value));

 		    }

 		  }

 		  break;

     case T_OBJECT:

     case T_ARRAY: 

 		  if (UseCompressedOops && !wide) {

 		      if (disp_reg == noreg) {

 			  __ lw(dest->as_register(), src_reg, disp_value);

 		      } else if (needs_patching) {

 			  __ dadd(AT, src_reg, disp_reg);

 			  offset = code_offset();

 			  __ lw(dest->as_register(), AT, 0);

 		      } else {

 			  __ dadd(AT, src_reg, disp_reg);

 			  offset = code_offset();

 			  __ lw(dest->as_register(), AT, Assembler::split_low(disp_value));

 		      }

 		  } else {

 		      if (disp_reg == noreg) {

 			  __ ld_ptr(dest->as_register(), src_reg, disp_value);

 		      } else if (needs_patching) {

 			  __ dadd(AT, src_reg, disp_reg);

 			  offset = code_offset();

 			  __ ld_ptr(dest->as_register(), AT, 0);

 		      } else {

 			  __ dadd(AT, src_reg, disp_reg);

 			  offset = code_offset();

 			  __ ld_ptr(dest->as_register(), AT, Assembler::split_low(disp_value));

 		      }

 		  }

 		  break;

     case T_ADDRESS:

 		  if (disp_reg == noreg) {

 		      __ ld_ptr(dest->as_register(), src_reg, disp_value);

 		  } else if (needs_patching) {

 		      __ dadd(AT, src_reg, disp_reg);

 		      offset = code_offset();

 		      __ ld_ptr(dest->as_register(), AT, 0);

 		  } else {

 		      __ dadd(AT, src_reg, disp_reg);

 		      offset = code_offset();

 		      __ ld_ptr(dest->as_register(), AT, Assembler::split_low(disp_value));

 		  }

 		  break;

     case T_INT:	{

 		  //assert(to_reg.is_word(), "just check");

 		  if (disp_reg == noreg) {

 		    __ lw(dest->as_register(), src_reg, disp_value);

 		  } else if (needs_patching) {

 		    __ add(AT, src_reg, disp_reg);

 		    offset = code_offset();

 		    __ lw(dest->as_register(), AT, 0);

 		  } else {

 		    __ add(AT, src_reg, disp_reg);

 		    offset = code_offset();

 		    __ lw(dest->as_register(), AT, Assembler::split_low(disp_value));

 		  }

 		}

 		break;

     case T_LONG: {

 		   Register to_lo = dest->as_register_lo();

 		   Register to_hi = dest->as_register_hi();

 #ifdef _LP64

 		   if (needs_patching) {

 		     __ add(AT, src_reg, disp_reg);

 		     __ ld_ptr(to_lo, AT, 0);

 		   } else {

 		     __ ld_ptr(to_lo, as_Address_lo(addr));

 		   }

 #else

 		   Register base = addr->base()->as_register();

 		   Register index = noreg;

 		   if (addr->index()->is_register()) {

 		     index = addr->index()->as_register();

 		   }

 		   if ((base == to_lo && index == to_hi) ||(base == to_hi && index == to_lo)) {

 		     // addresses with 2 registers are only formed as a result of

 		     // array access so this code will never have to deal with

 		     // patches or null checks.

 		     assert(info == NULL && patch == NULL, "must be");

 		     __ lea(to_hi, as_Address(addr));

 		     __ lw(to_lo, Address(to_hi));

 		     __ lw(to_hi, Address(to_hi, BytesPerWord));

 		   } else if (base == to_lo || index == to_lo) {

 		     assert(base != to_hi, "can't be");

 		     assert(index == noreg || (index != base && index != to_hi), "can't handle this");

 		     if (needs_patching) {

 		       __ add(AT, src_reg, disp_reg);

 		       offset = code_offset();

 		       __ lw(to_hi, AT, longSize/2);

 		       __ lw(to_lo, AT, 0);

 		     } else {

 		       __ lw(to_hi, as_Address_hi(addr));

 		       __ lw(to_lo, as_Address_lo(addr));

 		     }

 		   } else {

 		     assert(index == noreg || (index != base && index != to_lo), "can't handle this");

 		     if (needs_patching) {

 		       __ add(AT, src_reg, disp_reg);

 		       offset = code_offset();

 		       __ lw(to_lo, AT, 0);

 		       __ lw(to_hi, AT, longSize/2);

 		     } else {

 		       __ lw(to_lo, as_Address_lo(addr));

 		       __ lw(to_hi, as_Address_hi(addr));

 		     }

 		   }

 #endif

 		 }

 		 break;

     case T_FLOAT: {

 		    //assert(to_reg.is_float(), "just check");

 		    if (disp_reg == noreg) {

 		      __ lwc1(dest->as_float_reg(), src_reg, disp_value);

 		    } else if (needs_patching) {

 		      __ add(AT, src_reg, disp_reg);

 		      offset = code_offset();

 		      __ lwc1(dest->as_float_reg(), AT, 0);

 		    } else {

 		      __ add(AT, src_reg, disp_reg);

 		      offset = code_offset();

 		      __ lwc1(dest->as_float_reg(), AT, Assembler::split_low(disp_value));

 		    }

 		  }

 		  break;

     case T_DOUBLE: {

 		     //assert(to_reg.is_double(), "just check");

 		     if (disp_reg == noreg) {

 #ifndef _LP64

 		       __ lwc1(dest->as_double_reg(), src_reg, disp_value);

 		       __ lwc1(dest->as_double_reg()+1, src_reg, disp_value+4);

 #else

 		       __ ldc1(dest->as_double_reg(), src_reg, disp_value);

 #endif

 		     } else if (needs_patching) {

 		       __ add(AT, src_reg, disp_reg);

 		       offset = code_offset();

 #ifndef _LP64

 		       __ lwc1(dest->as_double_reg(), AT, 0);

 		       __ lwc1(dest->as_double_reg()+1, AT, 4);

 #else

 		       __ ldc1(dest->as_double_reg(), AT, 0);

 #endif

 		     } else {

 		       __ add(AT, src_reg, disp_reg);

 		       offset = code_offset();

 #ifndef _LP64

 		       __ lwc1(dest->as_double_reg(), AT, Assembler::split_low(disp_value));

 		       __ lwc1(dest->as_double_reg()+1, AT, Assembler::split_low(disp_value) + 4);

 #else

 		       __ ldc1(dest->as_double_reg(), AT, Assembler::split_low(disp_value));

 #endif

 		     }

 		   }

 		   break;

     default:

 		   ShouldNotReachHere();

   }

   if (needs_patching) {

     patching_epilog(patch, patch_code, src_reg, info);

   }

   if (type == T_ARRAY || type == T_OBJECT) {

 #ifdef _LP64

       if (UseCompressedOops && !wide) {

 	  __ decode_heap_oop(dest->as_register());

       }

 #endif

       __ verify_oop(dest->as_register());

   }

   if (info != NULL) add_debug_info_for_null_check(offset, info);

 }

 void LIR_Assembler::prefetchr(LIR_Opr src) {

   LIR_Address* addr = src->as_address_ptr();

   Address from_addr = as_Address(addr);

 }

 void LIR_Assembler::prefetchw(LIR_Opr src) {

 }

 NEEDS_CLEANUP; // This could be static? 

 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {

   int elem_size = type2aelembytes(type);

   switch (elem_size) {

     case 1: return Address::times_1;

     case 2: return Address::times_2;

     case 4: return Address::times_4;

     case 8: return Address::times_8;

   }

   ShouldNotReachHere();

   return Address::no_scale;

 }

 void LIR_Assembler::emit_op3(LIR_Op3* op) {

  switch (op->code()) {

     case lir_frem:

       arithmetic_frem(

         op->code(),

         op->in_opr1(),

         op->in_opr2(),

         op->in_opr3(),

         op->result_opr(),

         op->info());

       break;

     case lir_idiv:

     case lir_irem:

       arithmetic_idiv(

         op->code(),

         op->in_opr1(),

         op->in_opr2(),

         op->in_opr3(),

         op->result_opr(),

         op->info());

       break;

     default:      ShouldNotReachHere(); break;

   }

 }

 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {

   LIR_Opr opr1 = op->left();

   LIR_Opr opr2 = op->right();

   LIR_Condition condition = op->cond();

 #ifdef ASSERT

   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");

   if (op->block() != NULL)  _branch_target_blocks.append(op->block());

   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());

 #endif	

   if (op->cond() == lir_cond_always) {

     if(op->label()==NULL)           //by liaob1

 	 __ b(*op->label());

     else                            

 	__ b_far(*op->label());

     __ delayed()->nop();

     return;

   }

   if (opr1->is_single_cpu()) {

     Register reg_op1 = opr1->as_register();

     if (opr2->is_single_cpu()) {

 #ifdef OPT_RANGECHECK

       assert(!op->check(), "just check");

 #endif

       Register reg_op2 = opr2->as_register();

       switch (condition) {

 	case lir_cond_equal:

 	  __ beq(reg_op1, reg_op2, *op->label());

 	  break;

 	case lir_cond_notEqual:

 	  if(op->label()==NULL) 

 		__ bne(reg_op1, reg_op2, *op->label());//liaobin1

 	  else 

 		__ bne_far(reg_op1, reg_op2, *op->label());//liaobin1

 	  break;

 	case lir_cond_less:

 	  // AT = 1 TRUE

 	  __ slt(AT, reg_op1, reg_op2);

 	  __ bne_far(AT, R0, *op->label());

 	  break;

 	case lir_cond_lessEqual:

 	  // AT = 0 TRUE

 	  __ slt(AT, reg_op2, reg_op1);

 	  __ beq_far(AT, R0, *op->label());

 	  break;

 	case lir_cond_belowEqual:

 	  // AT = 0 TRUE

 	  __ sltu(AT, reg_op2, reg_op1);

 	  __ beq(AT, R0, *op->label());

 	  break;

 	case lir_cond_greaterEqual:

 	  // AT = 0 TRUE

 	  __ slt(AT, reg_op1, reg_op2);

 	  __ beq_far(AT, R0, *op->label());

 	  break;

 	case lir_cond_aboveEqual:

 	  // AT = 0 TRUE

 	  __ sltu(AT, reg_op1, reg_op2);

 	  __ beq_far(AT, R0, *op->label());

 	  break;

 	case lir_cond_greater:

 	  // AT = 1 TRUE

 	  __ slt(AT, reg_op2, reg_op1);

 	  __ bne_far(AT, R0, *op->label());

 	  break;				

 	default: ShouldNotReachHere();

       }

     } else if (opr2->is_constant()) {

       NOT_LP64(jint) LP64_ONLY(jlong) temp_value;

       bool is_object = false;

       if (opr2->pointer()->as_constant()->type() == T_INT) {

 	temp_value = (jint)(opr2->as_jint());

       } else if (opr2->pointer()->as_constant()->type() == T_LONG) {

 	temp_value = (jlong)(opr2->as_jlong());

       } else if (opr2->pointer()->as_constant()->type() == T_OBJECT) {

 	is_object = true;

 	temp_value = NOT_LP64((jint)) LP64_ONLY((jlong))(opr2->as_jobject());

       } else {

 	ShouldNotReachHere();

       }

       switch (condition) {

 	case lir_cond_equal:

 #ifdef OPT_RANGECHECK

 	  assert(!op->check(), "just check");

 #endif

 	  if (temp_value) {

 	    if (is_object) {

 	      int oop_index = __ oop_recorder()->allocate_oop_index((jobject)temp_value);

 	      RelocationHolder rspec = oop_Relocation::spec(oop_index);

 	      __ relocate(rspec);

 	    }

 	    __ li(AT, temp_value);

 	    __ beq_far(reg_op1, AT, *op->label());

 	  } else {

 	    __ beq_far(reg_op1, R0, *op->label());

 	  }

 	  break;

 	case lir_cond_notEqual:

 #ifdef OPT_RANGECHECK

 	  assert(!op->check(), "just check");

 #endif

 	  if (temp_value) {

 	    if (is_object) {

 	      int oop_index = __ oop_recorder()->allocate_oop_index((jobject)temp_value);

 	      RelocationHolder rspec = oop_Relocation::spec(oop_index);

 	      __ relocate(rspec);

 	    }

 	    __ li(AT, temp_value);

 	    __ bne_far(reg_op1, AT, *op->label());

 	  } else {

 	    __ bne_far(reg_op1, R0, *op->label());

 	  }

 	  break;

 	case lir_cond_less:

 #ifdef OPT_RANGECHECK

 	  assert(!op->check(), "just check");

 #endif

 	  // AT = 1 TRUE

 	  if (Assembler::is_simm16(temp_value)) {

 	    __ slti(AT, reg_op1, temp_value);

 	  } else {

 	    __ move(AT, temp_value);

 	    __ slt(AT, reg_op1, AT);

 	  }

 	  __ bne_far(AT, R0, *op->label());

 	  break;

 	case lir_cond_lessEqual:

 #ifdef OPT_RANGECHECK

 	  assert(!op->check(), "just check");

 #endif

 	  // AT = 0 TRUE

 	  __ li(AT, temp_value);

 	  __ slt(AT, AT, reg_op1);

 	  __ beq(AT, R0, *op->label());

 	  break;

 	case lir_cond_belowEqual:

 	  // AT = 0 TRUE

 #ifdef OPT_RANGECHECK

 	  if (op->check()) {

 	    __ li(AT, temp_value);

 	    add_debug_info_for_range_check_here(op->info(), temp_value);

 	    __ tgeu(AT, reg_op1, 29);

 	  } else {

 #endif

 	    __ li(AT, temp_value);

 	    __ sltu(AT, AT, reg_op1);

 	    __ beq(AT, R0, *op->label());

 #ifdef OPT_RANGECHECK

 	  }

 #endif

 	  break;

 	case lir_cond_greaterEqual:

 #ifdef OPT_RANGECHECK

 	  assert(!op->check(), "just check");

 #endif

 	  // AT = 0 TRUE

 	  if (Assembler::is_simm16(temp_value)) {

 	    __ slti(AT, reg_op1, temp_value);

 	  } else {

 	    __ li(AT, temp_value);

 	    __ slt(AT, reg_op1, AT);

 	  }

 	  __ beq(AT, R0, *op->label());

 	  break;

 	case lir_cond_aboveEqual:

 #ifdef OPT_RANGECHECK

 	  assert(!op->check(), "just check");

 #endif

 	  // AT = 0 TRUE

 	  if (Assembler::is_simm16(temp_value)) {

 	    __ sltiu(AT, reg_op1, temp_value);

 	  } else {

 	    __ li(AT, temp_value);

 	    __ sltu(AT, reg_op1, AT);

 	  }

 	  __ beq(AT, R0, *op->label());

 	  break;

 	case lir_cond_greater:

 #ifdef OPT_RANGECHECK

 	  assert(!op->check(), "just check");

 #endif

 	  // AT = 1 TRUE

 	  __ li(AT, temp_value);

 	  __ slt(AT, AT, reg_op1);

 	  __ bne_far(AT, R0, *op->label());

 	  break;				

 	default: ShouldNotReachHere();

       }

     } else {

       if (opr2->is_address()) {

 	//FIXME. aoqi lw or ld_ptr?

 	if (op->type() == T_INT)

 	__ lw(AT, as_Address(opr2->pointer()->as_address()));

 	else

 	__ ld_ptr(AT, as_Address(opr2->pointer()->as_address()));

       } else if (opr2->is_stack()) {

 	//FIXME. aoqi

 	__ ld_ptr(AT, frame_map()->address_for_slot(opr2->single_stack_ix()));

       } else {

 	ShouldNotReachHere();

       }

       switch (condition) {

 	case lir_cond_equal:

 #ifdef OPT_RANGECHECK

 	  assert(!op->check(), "just check");

 #endif

 	  __ beq(reg_op1, AT, *op->label());

 	  break;

 	case lir_cond_notEqual:

 #ifdef OPT_RANGECHECK

 	  assert(!op->check(), "just check");

 #endif

 	  __ bne_far(reg_op1, AT, *op->label());

 	  break;

 	case lir_cond_less:

 #ifdef OPT_RANGECHECK

 	  assert(!op->check(), "just check");

 #endif

 	  // AT = 1 TRUE

 	  __ slt(AT, reg_op1, AT);

 	  __ bne_far(AT, R0, *op->label());

 	  break;

 	case lir_cond_lessEqual:

 #ifdef OPT_RANGECHECK

 	  assert(!op->check(), "just check");

 #endif

 	  // AT = 0 TRUE

 	  __ slt(AT, AT, reg_op1);

 	  __ beq(AT, R0, *op->label());

 	  break;

 	case lir_cond_belowEqual:

 #ifdef OPT_RANGECHECK

 	  assert(!op->check(), "just check");

 #endif

 	  // AT = 0 TRUE

 	  __ sltu(AT, AT, reg_op1);

 	  __ beq(AT, R0, *op->label());

 	  break;

 	case lir_cond_greaterEqual:

 #ifdef OPT_RANGECHECK

 	  assert(!op->check(), "just check");

 #endif

 	  // AT = 0 TRUE

 	  __ slt(AT, reg_op1, AT);

 	  __ beq(AT, R0, *op->label());

 	  break;

 	case lir_cond_aboveEqual:

 	  // AT = 0 TRUE

 #ifdef OPT_RANGECHECK

 	  if (op->check()) {

 	    add_debug_info_for_range_check_here(op->info(), opr1->rinfo());

 	    __ tgeu(reg_op1, AT, 29);

 	  } else {

 #endif

 	    __ sltu(AT, reg_op1, AT);

 	    __ beq_far(AT, R0, *op->label());

 #ifdef OPT_RANGECHECK

 	  }

 #endif

 	  break;

 	case lir_cond_greater:

 #ifdef OPT_RANGECHECK

 	  assert(!op->check(), "just check");

 #endif

 	  // AT = 1 TRUE

 	  __ slt(AT, AT, reg_op1);

 	  __ bne_far(AT, R0, *op->label());

 	  break;				

 	default: ShouldNotReachHere();

       }

     }

 #ifdef OPT_RANGECHECK

     if (!op->check())

 #endif

       __ delayed()->nop();

   } else if(opr1->is_address() || opr1->is_stack()) {

 #ifdef OPT_RANGECHECK

     assert(!op->check(), "just check");

 #endif

     if (opr2->is_constant()) {

       NOT_LP64(jint) LP64_ONLY(jlong) temp_value;

       if (opr2->as_constant_ptr()->type() == T_INT) {

 	temp_value = (jint)opr2->as_constant_ptr()->as_jint();

       } else if (opr2->as_constant_ptr()->type() == T_OBJECT) {

 	temp_value = NOT_LP64((jint)) LP64_ONLY((jlong))(opr2->as_constant_ptr()->as_jobject());

       } else {

 	ShouldNotReachHere();

       }

       if (Assembler::is_simm16(temp_value)) {

 	if (opr1->is_address()) {

 	  __ lw(AT, as_Address(opr1->pointer()->as_address()));

 	} else {

 	  __ lw(AT, frame_map()->address_for_slot(opr1->single_stack_ix()));

 	}

 	switch(condition) {

 	  case lir_cond_equal:

 	    __ addi(AT, AT, -(int)temp_value);	

 	    __ beq(AT, R0, *op->label());

 	    break;

 	  case lir_cond_notEqual:

 	    __ addi(AT, AT, -(int)temp_value);	

 	    __ bne_far(AT, R0, *op->label());

 	    break;

 	  case lir_cond_less:

 	    // AT = 1 TRUE

 	    __ slti(AT, AT, temp_value);

 	    __ bne_far(AT, R0, *op->label());

 	    break;

 	  case lir_cond_lessEqual:

 	    // AT = 0 TRUE

 	    __ addi(AT, AT, -temp_value);	

 	    __ slt(AT, R0, AT);

 	    __ beq(AT, R0, *op->label());

 	    break;

 	  case lir_cond_belowEqual:

 	    // AT = 0 TRUE

 	    __ addiu(AT, AT, -temp_value);	

 	    __ sltu(AT, R0, AT);

 	    __ beq(AT, R0, *op->label());

 	    break;

 	  case lir_cond_greaterEqual:

 	    // AT = 0 TRUE

 	    __ slti(AT, AT, temp_value);

 	    __ beq(AT, R0, *op->label());

 	    break;

 	  case lir_cond_aboveEqual:

 	    // AT = 0 TRUE

 	    __ sltiu(AT, AT, temp_value);

 	    __ beq(AT, R0, *op->label());

 	    break;

 	  case lir_cond_greater:

 	    // AT = 1 TRUE

 	    __ addi(AT, AT, -temp_value);		

 	    __ slt(AT, R0, AT);

 	    __ bne_far(AT, R0, *op->label());

 	    break;				

 	  default:

 	    Unimplemented();

 	}

       } else {

 	Unimplemented();

       }

     } else {

       Unimplemented();

     }

     __ delayed()->nop();

   } else if(opr1->is_double_cpu()) {

 #ifdef OPT_RANGECHECK

     assert(!op->check(), "just check");

 #endif

     Register opr1_lo = opr1->as_register_lo();

     Register opr1_hi = opr1->as_register_hi();

     if (opr2->is_double_cpu()) {

       Register opr2_lo = opr2->as_register_lo();

       Register opr2_hi = opr2->as_register_hi();

       switch (condition) {

 	case lir_cond_equal: {

 			       Label L;

 #ifndef _LP64

 			       __ bne(opr1_lo, opr2_lo, L);

 			       __ delayed()->nop();

 			       __ beq(opr1_hi, opr2_hi, *op->label());

 #else

 /* static jobject java.lang.Long.toString(jlong)

   10 move [t0t0|J] [a4a4|J] 

   12 move [lng:-9223372036854775808|J] [a6a6|J] 

   14 branch [EQ] [a4a4|J] [a6a6|J] [B1]

    0x000000555e8532e4: bne a4, a6, 0x000000555e8532e4	<-- error

    0x000000555e8532e8: sll zero, zero, 0

 */

 			      // __ beq(opr1_lo, opr2_lo, *op->label());

 			       __ beq(opr1_lo, opr2_lo, *op->label());

 #endif

 			       __ delayed()->nop();

 			       __ bind(L);

 			     }

 			     break;

 	case lir_cond_notEqual:

 			     if (op->label()==NULL)

 			     	__ bne(opr1_lo, opr2_lo, *op->label());//by liaobin2

 			     else

                              	__ bne_far(opr1_lo, opr2_lo, *op->label());//by liaobin2

 			     __ delayed()->nop();

 			     if (op->label()==NULL)

 			     	NOT_LP64(__ bne(opr1_hi, opr2_hi, *op->label()));//by liaobin3

 			     else

                              	NOT_LP64(__ bne_far(opr1_hi, opr2_hi, *op->label()));//by liaobin3

 			     NOT_LP64(__ delayed()->nop());

 			     break;

 	case lir_cond_less: { 

 #ifdef _LP64

 			      __ slt(AT, opr1_lo, opr2_lo);

 			      __ bne_far(AT, R0, *op->label());

 			      __ delayed()->nop();

 #else

 			      Label L;

 			      // if hi less then jump

 			      __ slt(AT, opr1_hi, opr2_hi);

 			      __ bne(AT, R0, *op->label());

 			      __ delayed()->nop();

 			      // if hi great then fail

 			      __ bne(opr1_hi, opr2_hi, L);

 			      __ delayed();

 			      // now just comp lo as unsigned

 			      __ sltu(AT, opr1_lo, opr2_lo);

 			      __ bne_far(AT, R0, *op->label());

 			      __ delayed()->nop();

 			      __ bind(L);

 #endif

 			    }

 			    break;

 	case lir_cond_lessEqual: {

 #ifdef _LP64

 				   __ slt(AT, opr2_lo, opr1_lo);

 				   __ beq_far(AT, R0, *op->label());

 				   __ delayed()->nop();

 #else

 				   Label L;

 				   // if hi great then fail

 				   __ slt(AT, opr2_hi, opr1_hi);

 				   __ bne(AT, R0, L);

 				   __ delayed()->nop();

 				   // if hi less then jump

 				   if(op->label()==NULL)

 				   	__ bne(opr2_hi, opr1_hi, *op->label());//by liaobin4

 				   else		

 				   	__ bne_far(opr2_hi, opr1_hi, *op->label());//by liaobin4

 				   __ delayed();

 				   // now just comp lo as unsigned

 				   __ sltu(AT, opr2_lo, opr1_lo);

 				   __ beq(AT, R0, *op->label());

 				   __ delayed()->nop();

 				   __ bind(L);

 #endif

 				 }

 				 break;

 	case lir_cond_belowEqual: {

 #ifdef _LP64

 				    __ sltu(AT, opr2_lo, opr1_lo);

 				    __ beq(AT, R0, *op->label());

 				    __ delayed()->nop();

 #else

 				    Label L;

 				    // if hi great then fail

 				    __ sltu(AT, opr2_hi, opr1_hi);

 				    __ bne_far(AT, R0, L);

 				    __ delayed()->nop();

 				    // if hi less then jump

 				    if(op->label()==NULL)

 				    	__ bne(opr2_hi, opr1_hi, *op->label());//by liaobin5

 				    else

                                     	__ bne_far(opr2_hi, opr1_hi, *op->label());//by liaobin5

 				    __ delayed();

 				    // now just comp lo as unsigned

 				    __ sltu(AT, opr2_lo, opr1_lo);

 				    __ beq(AT, R0, *op->label());

 				    __ delayed()->nop();

 				    __ bind(L);

 #endif

 				  }

 				  break;

 	case lir_cond_greaterEqual: {

 #ifdef _LP64

 				      __ slt(AT, opr1_lo, opr2_lo);

 				      __ beq_far(AT, R0, *op->label());

 				      __ delayed()->nop();

 #else

 				      Label L;

 				      // if hi less then fail

 				      __ slt(AT, opr1_hi, opr2_hi);

 				      __ bne_far(AT, R0, L);

 				      __ delayed()->nop();

 				      // if hi great then jump

 				      if(op->label()==NULL)

 				      	__ bne(opr2_hi, opr1_hi, *op->label());//by liaobin6

 				      else

 				      	__ bne_far(opr2_hi, opr1_hi, *op->label());//by liaobin6

 				      __ delayed();

 				      // now just comp lo as unsigned

 				      __ sltu(AT, opr1_lo, opr2_lo);

 				      __ beq(AT, R0, *op->label());

 				      __ delayed()->nop();

 				      __ bind(L);

 #endif

 				    }

 				    break;

 	case lir_cond_aboveEqual: {

 #ifdef _LP64

 				    __ sltu(AT, opr1_lo, opr2_lo);

 				    __ beq_far(AT, R0, *op->label());

 				    __ delayed()->nop();

 #else

 				    Label L;

 				    // if hi less then fail

 				    __ sltu(AT, opr1_hi, opr2_hi);

 				    __ bne(AT, R0, L);

 				    __ delayed()->nop();

 				    // if hi great then jump

 				    if(op->label()==NULL)

 				   	__ bne(opr2_hi, opr1_hi, *op->label());//by liaobin7

 				    else

 				    	__ bne_far(opr2_hi, opr1_hi, *op->label());//by liaobin7

 				    __ delayed();

 				    // now just comp lo as unsigned

 				    __ sltu(AT, opr1_lo, opr2_lo);

 				    __ beq(AT, R0, *op->label());

 				    __ delayed()->nop();

 				    __ bind(L);

 #endif

 				  }

 				  break;

 	case lir_cond_greater: {

 #ifdef _LP64

 				 __ slt(AT, opr2_lo, opr1_lo);

 				 __ bne_far(AT, R0, *op->label());

 				 __ delayed()->nop();

 #else

 				 Label L;

 				 // if hi great then jump

 				 __ slt(AT, opr2_hi, opr1_hi);

 				 __ bne(AT, R0, *op->label());

 				 __ delayed()->nop();

 				 // if hi less then fail

 				 __ bne(opr2_hi, opr1_hi, L);

 				 __ delayed();

 				 // now just comp lo as unsigned

 				 __ sltu(AT, opr2_lo, opr1_lo);

 				 __ bne(AT, R0, *op->label());

 				 __ delayed()->nop();

 				 __ bind(L);

 #endif

 			       }

 			       break;				

 	default: ShouldNotReachHere();

       }

     } else if(opr2->is_constant()) {

       jlong lv = opr2->as_jlong();

 #ifndef _LP64

       jint iv_lo = (jint)lv;

       jint iv_hi = (jint)(lv>>32);

       bool is_zero = (lv==0);

 #endif

       switch (condition) {

 	case lir_cond_equal: 

 #ifdef _LP64

 	  __ li(T8, lv);

 	  __ beq(opr1_lo, T8, *op->label());

 	  __ delayed()->nop();

 #else

 	  if (is_zero) {

 	    __ orr(AT, opr1_lo, opr1_hi);

 	    __ beq(AT, R0, *op->label());

 	    __ delayed()->nop();

 	  } else {

 	    Label L;

 	    __ move(T8, iv_lo);

 	    __ bne(opr1_lo, T8, L);

 	    __ delayed();

 	    __ move(T8, iv_hi);

 	    __ beq(opr1_hi, T8, *op->label());

 	    __ delayed()->nop();

 	    __ bind(L);

 	  }

 #endif

 	  break;

 	case lir_cond_notEqual:

 #ifdef _LP64

 	  __ li(T8, lv);

 	  __ bne(opr1_lo, T8, *op->label());

 	  __ delayed()->nop();

 #else

 	  if (is_zero) {

 	    __ orr(AT, opr1_lo, opr1_hi);

 	    __ bne(AT, R0, *op->label());

 	    __ delayed()->nop();

 	  } else {

 	    __ move(T8, iv_lo);

 	    __ bne(opr1_lo, T8, *op->label());

 	    __ delayed();

 	    __ move(T8, iv_hi);

 	    __ bne(opr1_hi, T8, *op->label());

 	    __ delayed()->nop();

 	  }

 #endif

 	  break;

 	case lir_cond_less:

 #ifdef _LP64

 	  __ li(T8, lv);

 	  __ slt(AT, opr1_lo, T8);

 	  __ bne_far(AT, R0, *op->label());

 	  __ delayed()->nop();

 #else

 	  if (is_zero) {

 	    __ bltz(opr1_hi, *op->label());

 	    __ bltz(opr1_lo, *op->label());

 	    __ delayed()->nop();

 	  } else { 

 	    Label L;

 	    // if hi less then jump

 	    __ move(T8, iv_hi);

 	    __ slt(AT, opr1_hi, T8);

 	    __ bne_far(AT, R0, *op->label());

 	    __ delayed()->nop();

 	    // if hi great then fail

 	    __ bne(opr1_hi, T8, L);

 	    __ delayed();

 	    // now just comp lo as unsigned

 	    if (Assembler::is_simm16(iv_lo)) {

 	      __ sltiu(AT, opr1_lo, iv_lo);

 	    } else {

 	      __ move(T8, iv_lo);

 	      __ sltu(AT, opr1_lo, T8);

 	    }

 	    __ bne(AT, R0, *op->label());

 	    __ delayed()->nop();

 	    __ bind(L);

 	  }

 #endif

 	  break;

 	case lir_cond_lessEqual:

 #ifdef _LP64

 	  __ li(T8, lv);

 	  __ slt(AT, T8, opr1_lo);

 	  __ beq(AT, R0, *op->label());

 	  __ delayed()->nop();

 #else

 	  if (is_zero) {

 	    __ bltz(opr1_hi, *op->label());

 	    __ delayed()->nop();

 	    __ orr(AT, opr1_hi, opr1_lo);

 	    __ beq(AT, R0, *op->label());

 	    __ delayed();

 	  } else {

 	    Label L;

 	    // if hi great then fail

 	    __ move(T8, iv_hi);

 	    __ slt(AT, T8, opr1_hi);

 	    __ bne(AT, R0, L);

 	    __ delayed()->nop();

 	    // if hi less then jump

 	    __ bne(T8, opr1_hi, *op->label());

 	    __ delayed();

 	    // now just comp lo as unsigned

 	    __ move(T8, iv_lo);

 	    __ sltu(AT, T8, opr1_lo);

 	    __ beq(AT, R0, *op->label());

 	    __ delayed()->nop();

 	    __ bind(L);

 	  }

 #endif

 	  break;

 	case lir_cond_belowEqual:

 #ifdef _LP64

 	  __ li(T8, lv);

 	  __ sltu(AT, T8, opr1_lo);

 	  __ beq(AT, R0, *op->label());

 	  __ delayed()->nop();

 #else

 	  if (is_zero) {

 	    __ orr(AT, opr1_hi, opr1_lo);

 	    __ beq(AT, R0, *op->label());

 	    __ delayed()->nop();

 	  } else {

 	    Label L;

 	    // if hi great then fail

 	    __ move(T8, iv_hi);

 	    __ sltu(AT, T8, opr1_hi);

 	    __ bne(AT, R0, L);

 	    __ delayed()->nop();

 	    // if hi less then jump

 	    __ bne(T8, opr1_hi, *op->label());

 	    __ delayed();

 	    // now just comp lo as unsigned

 	    __ move(T8, iv_lo);

 	    __ sltu(AT, T8, opr1_lo);

 	    __ beq(AT, R0, *op->label());

 	    __ delayed()->nop();

 	    __ bind(L);

 	  }

 #endif

 	  break;

 	case lir_cond_greaterEqual:

 #ifdef _LP64

 	  __ li(T8, lv);

 	  __ slt(AT, opr1_lo, T8);

 	  __ beq(AT, R0, *op->label());

 	  __ delayed()->nop();

 #else

 	  if (is_zero) {

 	    __ bgez(opr1_hi, *op->label());

 	    __ delayed()->nop();

 	  } else {

 	    Label L;

 	    // if hi less then fail

 	    __ move(T8, iv_hi);

 	    __ slt(AT, opr1_hi, T8);

 	    __ bne(AT, R0, L);

 	    __ delayed()->nop();

 	    // if hi great then jump

 	    __ bne(T8, opr1_hi, *op->label());

 	    __ delayed();

 	    // now just comp lo as unsigned

 	    if (Assembler::is_simm16(iv_lo)) {

 	      __ sltiu(AT, opr1_lo, iv_lo);

 	    } else {

 	      __ move(T8, iv_lo);

 	      __ sltu(AT, opr1_lo, T8);

 	    }

 	    __ beq(AT, R0, *op->label());

 	    __ delayed()->nop();

 	    __ bind(L);

 	  }

 #endif

 	  break;

 	case lir_cond_aboveEqual:

 #ifdef _LP64

 	  __ li(T8, lv);

 	  __ sltu(AT, opr1_lo, T8);

 	  __ beq(AT, R0, *op->label());

 	  __ delayed()->nop();

 #else

 	  if (is_zero) {

             if(op->label()==NULL)  //by liaob2

 		__ b(*op->label());

 	    else 

 		__ b_far(*op->label());

 	    __ delayed()->nop();

 	  } else {

 	    Label L;

 	    // if hi less then fail

 	    __ move(T8, iv_hi);

 	    __ sltu(AT, opr1_hi, T8);

 	    __ bne(AT, R0, L);

 	    __ delayed()->nop();

 	    // if hi great then jump

 	    __ bne(T8, opr1_hi, *op->label());

 	    __ delayed();

 	    // now just comp lo as unsigned

 	    if (Assembler::is_simm16(iv_lo)) {

 	      __ sltiu(AT, opr1_lo, iv_lo);

 	    } else {

 	      __ move(T8, iv_lo);

 	      __ sltu(AT, opr1_lo, T8);

 	    }

 	    __ beq(AT, R0, *op->label());

 	    __ delayed()->nop();

 	    __ bind(L);

 	  }

 #endif

 	  break;

 	case lir_cond_greater:

 #ifdef _LP64

 	  __ li(T8, lv);

 	  __ slt(AT, T8, opr1_lo);

 	  __ bne_far(AT, R0, *op->label());

 	  __ delayed()->nop();

 #else

 	  if (is_zero) {

 	    Label L;

 	    __ bgtz(opr1_hi, *op->label());

 	    __ delayed()->nop();

 	    __ bne(opr1_hi, R0, L);

 	    __ delayed()->nop();

 	    __ bne(opr1_lo, R0, *op->label());

 	    __ delayed()->nop();

 	    __ bind(L);

 	  } else {

 	    Label L;

 	    // if hi great then jump

 	    __ move(T8, iv_hi);

 	    __ slt(AT, T8, opr1_hi);

 	    __ bne(AT, R0, *op->label());

 	    __ delayed()->nop();

 	    // if hi less then fail

 	    __ bne(T8, opr1_hi, L);

 	    __ delayed();

 	    // now just comp lo as unsigned

 	    __ move(T8, iv_lo);

 	    __ sltu(AT, T8, opr1_lo);

 	    __ bne(AT, R0, *op->label());

 	    __ delayed()->nop();

 	    __ bind(L);

 	  }

 #endif

 	  break;				

 	default: 

 	  ShouldNotReachHere();

       }

     } else {