Tue, 05 Nov 2013 17:38:04 -0800
Merge
1 //
2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
25 // X86 Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
186 %}
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
201 #define __ _masm.
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
230 // Offset hacking within calls.
231 static int pre_call_resets_size() {
232 int size = 0;
233 Compile* C = Compile::current();
234 if (C->in_24_bit_fp_mode()) {
235 size += 6; // fldcw
236 }
237 if (C->max_vector_size() > 16) {
238 size += 3; // vzeroupper
239 }
240 return size;
241 }
243 static int preserve_SP_size() {
244 return 2; // op, rm(reg/reg)
245 }
247 // !!!!! Special hack to get all type of calls to specify the byte offset
248 // from the start of the call to the point where the return address
249 // will point.
250 int MachCallStaticJavaNode::ret_addr_offset() {
251 int offset = 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points
252 if (_method_handle_invoke)
253 offset += preserve_SP_size();
254 return offset;
255 }
257 int MachCallDynamicJavaNode::ret_addr_offset() {
258 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points
259 }
261 static int sizeof_FFree_Float_Stack_All = -1;
263 int MachCallRuntimeNode::ret_addr_offset() {
264 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
265 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
266 }
268 // Indicate if the safepoint node needs the polling page as an input.
269 // Since x86 does have absolute addressing, it doesn't.
270 bool SafePointNode::needs_polling_address_input() {
271 return false;
272 }
274 //
275 // Compute padding required for nodes which need alignment
276 //
278 // The address of the call instruction needs to be 4-byte aligned to
279 // ensure that it does not span a cache line so that it can be patched.
280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
281 current_offset += pre_call_resets_size(); // skip fldcw, if any
282 current_offset += 1; // skip call opcode byte
283 return round_to(current_offset, alignment_required()) - current_offset;
284 }
286 // The address of the call instruction needs to be 4-byte aligned to
287 // ensure that it does not span a cache line so that it can be patched.
288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
289 current_offset += pre_call_resets_size(); // skip fldcw, if any
290 current_offset += preserve_SP_size(); // skip mov rbp, rsp
291 current_offset += 1; // skip call opcode byte
292 return round_to(current_offset, alignment_required()) - current_offset;
293 }
295 // The address of the call instruction needs to be 4-byte aligned to
296 // ensure that it does not span a cache line so that it can be patched.
297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
298 current_offset += pre_call_resets_size(); // skip fldcw, if any
299 current_offset += 5; // skip MOV instruction
300 current_offset += 1; // skip call opcode byte
301 return round_to(current_offset, alignment_required()) - current_offset;
302 }
304 // EMIT_RM()
305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
306 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
307 cbuf.insts()->emit_int8(c);
308 }
310 // EMIT_CC()
311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
312 unsigned char c = (unsigned char)( f1 | f2 );
313 cbuf.insts()->emit_int8(c);
314 }
316 // EMIT_OPCODE()
317 void emit_opcode(CodeBuffer &cbuf, int code) {
318 cbuf.insts()->emit_int8((unsigned char) code);
319 }
321 // EMIT_OPCODE() w/ relocation information
322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
323 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
324 emit_opcode(cbuf, code);
325 }
327 // EMIT_D8()
328 void emit_d8(CodeBuffer &cbuf, int d8) {
329 cbuf.insts()->emit_int8((unsigned char) d8);
330 }
332 // EMIT_D16()
333 void emit_d16(CodeBuffer &cbuf, int d16) {
334 cbuf.insts()->emit_int16(d16);
335 }
337 // EMIT_D32()
338 void emit_d32(CodeBuffer &cbuf, int d32) {
339 cbuf.insts()->emit_int32(d32);
340 }
342 // emit 32 bit value and construct relocation entry from relocInfo::relocType
343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
344 int format) {
345 cbuf.relocate(cbuf.insts_mark(), reloc, format);
346 cbuf.insts()->emit_int32(d32);
347 }
349 // emit 32 bit value and construct relocation entry from RelocationHolder
350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
351 int format) {
352 #ifdef ASSERT
353 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
354 assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
355 }
356 #endif
357 cbuf.relocate(cbuf.insts_mark(), rspec, format);
358 cbuf.insts()->emit_int32(d32);
359 }
361 // Access stack slot for load or store
362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
363 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
364 if( -128 <= disp && disp <= 127 ) {
365 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
366 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
367 emit_d8 (cbuf, disp); // Displacement // R/M byte
368 } else {
369 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
370 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
371 emit_d32(cbuf, disp); // Displacement // R/M byte
372 }
373 }
375 // rRegI ereg, memory mem) %{ // emit_reg_mem
376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
377 // There is no index & no scale, use form without SIB byte
378 if ((index == 0x4) &&
379 (scale == 0) && (base != ESP_enc)) {
380 // If no displacement, mode is 0x0; unless base is [EBP]
381 if ( (displace == 0) && (base != EBP_enc) ) {
382 emit_rm(cbuf, 0x0, reg_encoding, base);
383 }
384 else { // If 8-bit displacement, mode 0x1
385 if ((displace >= -128) && (displace <= 127)
386 && (disp_reloc == relocInfo::none) ) {
387 emit_rm(cbuf, 0x1, reg_encoding, base);
388 emit_d8(cbuf, displace);
389 }
390 else { // If 32-bit displacement
391 if (base == -1) { // Special flag for absolute address
392 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
393 // (manual lies; no SIB needed here)
394 if ( disp_reloc != relocInfo::none ) {
395 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
396 } else {
397 emit_d32 (cbuf, displace);
398 }
399 }
400 else { // Normal base + offset
401 emit_rm(cbuf, 0x2, reg_encoding, base);
402 if ( disp_reloc != relocInfo::none ) {
403 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
404 } else {
405 emit_d32 (cbuf, displace);
406 }
407 }
408 }
409 }
410 }
411 else { // Else, encode with the SIB byte
412 // If no displacement, mode is 0x0; unless base is [EBP]
413 if (displace == 0 && (base != EBP_enc)) { // If no displacement
414 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 }
417 else { // If 8-bit displacement, mode 0x1
418 if ((displace >= -128) && (displace <= 127)
419 && (disp_reloc == relocInfo::none) ) {
420 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, base);
422 emit_d8(cbuf, displace);
423 }
424 else { // If 32-bit displacement
425 if (base == 0x04 ) {
426 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
427 emit_rm(cbuf, scale, index, 0x04);
428 } else {
429 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
430 emit_rm(cbuf, scale, index, base);
431 }
432 if ( disp_reloc != relocInfo::none ) {
433 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
444 if( dst_encoding == src_encoding ) {
445 // reg-reg copy, use an empty encoding
446 } else {
447 emit_opcode( cbuf, 0x8B );
448 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
449 }
450 }
452 void emit_cmpfp_fixup(MacroAssembler& _masm) {
453 Label exit;
454 __ jccb(Assembler::noParity, exit);
455 __ pushf();
456 //
457 // comiss/ucomiss instructions set ZF,PF,CF flags and
458 // zero OF,AF,SF for NaN values.
459 // Fixup flags by zeroing ZF,PF so that compare of NaN
460 // values returns 'less than' result (CF is set).
461 // Leave the rest of flags unchanged.
462 //
463 // 7 6 5 4 3 2 1 0
464 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
465 // 0 0 1 0 1 0 1 1 (0x2B)
466 //
467 __ andl(Address(rsp, 0), 0xffffff2b);
468 __ popf();
469 __ bind(exit);
470 }
472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
473 Label done;
474 __ movl(dst, -1);
475 __ jcc(Assembler::parity, done);
476 __ jcc(Assembler::below, done);
477 __ setb(Assembler::notEqual, dst);
478 __ movzbl(dst, dst);
479 __ bind(done);
480 }
483 //=============================================================================
484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
486 int Compile::ConstantTable::calculate_table_base_offset() const {
487 return 0; // absolute addressing, no offset
488 }
490 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
491 // Empty encoding
492 }
494 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
495 return 0;
496 }
498 #ifndef PRODUCT
499 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
500 st->print("# MachConstantBaseNode (empty encoding)");
501 }
502 #endif
505 //=============================================================================
506 #ifndef PRODUCT
507 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
508 Compile* C = ra_->C;
510 int framesize = C->frame_slots() << LogBytesPerInt;
511 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
512 // Remove wordSize for return addr which is already pushed.
513 framesize -= wordSize;
515 if (C->need_stack_bang(framesize)) {
516 framesize -= wordSize;
517 st->print("# stack bang");
518 st->print("\n\t");
519 st->print("PUSH EBP\t# Save EBP");
520 if (framesize) {
521 st->print("\n\t");
522 st->print("SUB ESP, #%d\t# Create frame",framesize);
523 }
524 } else {
525 st->print("SUB ESP, #%d\t# Create frame",framesize);
526 st->print("\n\t");
527 framesize -= wordSize;
528 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
529 }
531 if (VerifyStackAtCalls) {
532 st->print("\n\t");
533 framesize -= wordSize;
534 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
535 }
537 if( C->in_24_bit_fp_mode() ) {
538 st->print("\n\t");
539 st->print("FLDCW \t# load 24 bit fpu control word");
540 }
541 if (UseSSE >= 2 && VerifyFPU) {
542 st->print("\n\t");
543 st->print("# verify FPU stack (must be clean on entry)");
544 }
546 #ifdef ASSERT
547 if (VerifyStackAtCalls) {
548 st->print("\n\t");
549 st->print("# stack alignment check");
550 }
551 #endif
552 st->cr();
553 }
554 #endif
557 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
558 Compile* C = ra_->C;
559 MacroAssembler _masm(&cbuf);
561 int framesize = C->frame_slots() << LogBytesPerInt;
563 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
565 C->set_frame_complete(cbuf.insts_size());
567 if (C->has_mach_constant_base_node()) {
568 // NOTE: We set the table base offset here because users might be
569 // emitted before MachConstantBaseNode.
570 Compile::ConstantTable& constant_table = C->constant_table();
571 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
572 }
573 }
575 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
576 return MachNode::size(ra_); // too many variables; just compute it the hard way
577 }
579 int MachPrologNode::reloc() const {
580 return 0; // a large enough number
581 }
583 //=============================================================================
584 #ifndef PRODUCT
585 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
586 Compile *C = ra_->C;
587 int framesize = C->frame_slots() << LogBytesPerInt;
588 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
589 // Remove two words for return addr and rbp,
590 framesize -= 2*wordSize;
592 if (C->max_vector_size() > 16) {
593 st->print("VZEROUPPER");
594 st->cr(); st->print("\t");
595 }
596 if (C->in_24_bit_fp_mode()) {
597 st->print("FLDCW standard control word");
598 st->cr(); st->print("\t");
599 }
600 if (framesize) {
601 st->print("ADD ESP,%d\t# Destroy frame",framesize);
602 st->cr(); st->print("\t");
603 }
604 st->print_cr("POPL EBP"); st->print("\t");
605 if (do_polling() && C->is_method_compilation()) {
606 st->print("TEST PollPage,EAX\t! Poll Safepoint");
607 st->cr(); st->print("\t");
608 }
609 }
610 #endif
612 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
613 Compile *C = ra_->C;
615 if (C->max_vector_size() > 16) {
616 // Clear upper bits of YMM registers when current compiled code uses
617 // wide vectors to avoid AVX <-> SSE transition penalty during call.
618 MacroAssembler masm(&cbuf);
619 masm.vzeroupper();
620 }
621 // If method set FPU control word, restore to standard control word
622 if (C->in_24_bit_fp_mode()) {
623 MacroAssembler masm(&cbuf);
624 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
625 }
627 int framesize = C->frame_slots() << LogBytesPerInt;
628 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
629 // Remove two words for return addr and rbp,
630 framesize -= 2*wordSize;
632 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
634 if (framesize >= 128) {
635 emit_opcode(cbuf, 0x81); // add SP, #framesize
636 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
637 emit_d32(cbuf, framesize);
638 } else if (framesize) {
639 emit_opcode(cbuf, 0x83); // add SP, #framesize
640 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
641 emit_d8(cbuf, framesize);
642 }
644 emit_opcode(cbuf, 0x58 | EBP_enc);
646 if (do_polling() && C->is_method_compilation()) {
647 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
648 emit_opcode(cbuf,0x85);
649 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
650 emit_d32(cbuf, (intptr_t)os::get_polling_page());
651 }
652 }
654 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
655 Compile *C = ra_->C;
656 // If method set FPU control word, restore to standard control word
657 int size = C->in_24_bit_fp_mode() ? 6 : 0;
658 if (C->max_vector_size() > 16) size += 3; // vzeroupper
659 if (do_polling() && C->is_method_compilation()) size += 6;
661 int framesize = C->frame_slots() << LogBytesPerInt;
662 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
663 // Remove two words for return addr and rbp,
664 framesize -= 2*wordSize;
666 size++; // popl rbp,
668 if (framesize >= 128) {
669 size += 6;
670 } else {
671 size += framesize ? 3 : 0;
672 }
673 return size;
674 }
676 int MachEpilogNode::reloc() const {
677 return 0; // a large enough number
678 }
680 const Pipeline * MachEpilogNode::pipeline() const {
681 return MachNode::pipeline_class();
682 }
684 int MachEpilogNode::safepoint_offset() const { return 0; }
686 //=============================================================================
688 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
689 static enum RC rc_class( OptoReg::Name reg ) {
691 if( !OptoReg::is_valid(reg) ) return rc_bad;
692 if (OptoReg::is_stack(reg)) return rc_stack;
694 VMReg r = OptoReg::as_VMReg(reg);
695 if (r->is_Register()) return rc_int;
696 if (r->is_FloatRegister()) {
697 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
698 return rc_float;
699 }
700 assert(r->is_XMMRegister(), "must be");
701 return rc_xmm;
702 }
704 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
705 int opcode, const char *op_str, int size, outputStream* st ) {
706 if( cbuf ) {
707 emit_opcode (*cbuf, opcode );
708 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
709 #ifndef PRODUCT
710 } else if( !do_size ) {
711 if( size != 0 ) st->print("\n\t");
712 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
713 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
714 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
715 } else { // FLD, FST, PUSH, POP
716 st->print("%s [ESP + #%d]",op_str,offset);
717 }
718 #endif
719 }
720 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
721 return size+3+offset_size;
722 }
724 // Helper for XMM registers. Extra opcode bits, limited syntax.
725 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
726 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
727 if (cbuf) {
728 MacroAssembler _masm(cbuf);
729 if (reg_lo+1 == reg_hi) { // double move?
730 if (is_load) {
731 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
732 } else {
733 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
734 }
735 } else {
736 if (is_load) {
737 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
738 } else {
739 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
740 }
741 }
742 #ifndef PRODUCT
743 } else if (!do_size) {
744 if (size != 0) st->print("\n\t");
745 if (reg_lo+1 == reg_hi) { // double move?
746 if (is_load) st->print("%s %s,[ESP + #%d]",
747 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
748 Matcher::regName[reg_lo], offset);
749 else st->print("MOVSD [ESP + #%d],%s",
750 offset, Matcher::regName[reg_lo]);
751 } else {
752 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
753 Matcher::regName[reg_lo], offset);
754 else st->print("MOVSS [ESP + #%d],%s",
755 offset, Matcher::regName[reg_lo]);
756 }
757 #endif
758 }
759 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
760 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
761 return size+5+offset_size;
762 }
765 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
766 int src_hi, int dst_hi, int size, outputStream* st ) {
767 if (cbuf) {
768 MacroAssembler _masm(cbuf);
769 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
770 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
771 as_XMMRegister(Matcher::_regEncode[src_lo]));
772 } else {
773 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
774 as_XMMRegister(Matcher::_regEncode[src_lo]));
775 }
776 #ifndef PRODUCT
777 } else if (!do_size) {
778 if (size != 0) st->print("\n\t");
779 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
780 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
781 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
782 } else {
783 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
784 }
785 } else {
786 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
787 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
788 } else {
789 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
790 }
791 }
792 #endif
793 }
794 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
795 // Only MOVAPS SSE prefix uses 1 byte.
796 int sz = 4;
797 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
798 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
799 return size + sz;
800 }
802 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
803 int src_hi, int dst_hi, int size, outputStream* st ) {
804 // 32-bit
805 if (cbuf) {
806 MacroAssembler _masm(cbuf);
807 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
808 as_Register(Matcher::_regEncode[src_lo]));
809 #ifndef PRODUCT
810 } else if (!do_size) {
811 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
812 #endif
813 }
814 return 4;
815 }
818 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
819 int src_hi, int dst_hi, int size, outputStream* st ) {
820 // 32-bit
821 if (cbuf) {
822 MacroAssembler _masm(cbuf);
823 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
824 as_XMMRegister(Matcher::_regEncode[src_lo]));
825 #ifndef PRODUCT
826 } else if (!do_size) {
827 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
828 #endif
829 }
830 return 4;
831 }
833 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
834 if( cbuf ) {
835 emit_opcode(*cbuf, 0x8B );
836 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
837 #ifndef PRODUCT
838 } else if( !do_size ) {
839 if( size != 0 ) st->print("\n\t");
840 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
841 #endif
842 }
843 return size+2;
844 }
846 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
847 int offset, int size, outputStream* st ) {
848 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
849 if( cbuf ) {
850 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
851 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
852 #ifndef PRODUCT
853 } else if( !do_size ) {
854 if( size != 0 ) st->print("\n\t");
855 st->print("FLD %s",Matcher::regName[src_lo]);
856 #endif
857 }
858 size += 2;
859 }
861 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
862 const char *op_str;
863 int op;
864 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
865 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
866 op = 0xDD;
867 } else { // 32-bit store
868 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
869 op = 0xD9;
870 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
871 }
873 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
874 }
876 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
877 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
878 int src_hi, int dst_hi, uint ireg, outputStream* st);
880 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
881 int stack_offset, int reg, uint ireg, outputStream* st);
883 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
884 int dst_offset, uint ireg, outputStream* st) {
885 int calc_size = 0;
886 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
887 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
888 switch (ireg) {
889 case Op_VecS:
890 calc_size = 3+src_offset_size + 3+dst_offset_size;
891 break;
892 case Op_VecD:
893 calc_size = 3+src_offset_size + 3+dst_offset_size;
894 src_offset += 4;
895 dst_offset += 4;
896 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
897 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
898 calc_size += 3+src_offset_size + 3+dst_offset_size;
899 break;
900 case Op_VecX:
901 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
902 break;
903 case Op_VecY:
904 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
905 break;
906 default:
907 ShouldNotReachHere();
908 }
909 if (cbuf) {
910 MacroAssembler _masm(cbuf);
911 int offset = __ offset();
912 switch (ireg) {
913 case Op_VecS:
914 __ pushl(Address(rsp, src_offset));
915 __ popl (Address(rsp, dst_offset));
916 break;
917 case Op_VecD:
918 __ pushl(Address(rsp, src_offset));
919 __ popl (Address(rsp, dst_offset));
920 __ pushl(Address(rsp, src_offset+4));
921 __ popl (Address(rsp, dst_offset+4));
922 break;
923 case Op_VecX:
924 __ movdqu(Address(rsp, -16), xmm0);
925 __ movdqu(xmm0, Address(rsp, src_offset));
926 __ movdqu(Address(rsp, dst_offset), xmm0);
927 __ movdqu(xmm0, Address(rsp, -16));
928 break;
929 case Op_VecY:
930 __ vmovdqu(Address(rsp, -32), xmm0);
931 __ vmovdqu(xmm0, Address(rsp, src_offset));
932 __ vmovdqu(Address(rsp, dst_offset), xmm0);
933 __ vmovdqu(xmm0, Address(rsp, -32));
934 break;
935 default:
936 ShouldNotReachHere();
937 }
938 int size = __ offset() - offset;
939 assert(size == calc_size, "incorrect size calculattion");
940 return size;
941 #ifndef PRODUCT
942 } else if (!do_size) {
943 switch (ireg) {
944 case Op_VecS:
945 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
946 "popl [rsp + #%d]",
947 src_offset, dst_offset);
948 break;
949 case Op_VecD:
950 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
951 "popq [rsp + #%d]\n\t"
952 "pushl [rsp + #%d]\n\t"
953 "popq [rsp + #%d]",
954 src_offset, dst_offset, src_offset+4, dst_offset+4);
955 break;
956 case Op_VecX:
957 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
958 "movdqu xmm0, [rsp + #%d]\n\t"
959 "movdqu [rsp + #%d], xmm0\n\t"
960 "movdqu xmm0, [rsp - #16]",
961 src_offset, dst_offset);
962 break;
963 case Op_VecY:
964 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
965 "vmovdqu xmm0, [rsp + #%d]\n\t"
966 "vmovdqu [rsp + #%d], xmm0\n\t"
967 "vmovdqu xmm0, [rsp - #32]",
968 src_offset, dst_offset);
969 break;
970 default:
971 ShouldNotReachHere();
972 }
973 #endif
974 }
975 return calc_size;
976 }
978 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
979 // Get registers to move
980 OptoReg::Name src_second = ra_->get_reg_second(in(1));
981 OptoReg::Name src_first = ra_->get_reg_first(in(1));
982 OptoReg::Name dst_second = ra_->get_reg_second(this );
983 OptoReg::Name dst_first = ra_->get_reg_first(this );
985 enum RC src_second_rc = rc_class(src_second);
986 enum RC src_first_rc = rc_class(src_first);
987 enum RC dst_second_rc = rc_class(dst_second);
988 enum RC dst_first_rc = rc_class(dst_first);
990 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
992 // Generate spill code!
993 int size = 0;
995 if( src_first == dst_first && src_second == dst_second )
996 return size; // Self copy, no move
998 if (bottom_type()->isa_vect() != NULL) {
999 uint ireg = ideal_reg();
1000 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1001 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
1002 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1003 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1004 // mem -> mem
1005 int src_offset = ra_->reg2offset(src_first);
1006 int dst_offset = ra_->reg2offset(dst_first);
1007 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
1008 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1009 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
1010 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1011 int stack_offset = ra_->reg2offset(dst_first);
1012 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
1013 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
1014 int stack_offset = ra_->reg2offset(src_first);
1015 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1016 } else {
1017 ShouldNotReachHere();
1018 }
1019 }
1021 // --------------------------------------
1022 // Check for mem-mem move. push/pop to move.
1023 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1024 if( src_second == dst_first ) { // overlapping stack copy ranges
1025 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1026 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1027 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1028 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1029 }
1030 // move low bits
1031 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1032 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1033 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1034 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1035 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1036 }
1037 return size;
1038 }
1040 // --------------------------------------
1041 // Check for integer reg-reg copy
1042 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1043 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1045 // Check for integer store
1046 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1047 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1049 // Check for integer load
1050 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1051 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1053 // Check for integer reg-xmm reg copy
1054 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1055 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1056 "no 64 bit integer-float reg moves" );
1057 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1058 }
1059 // --------------------------------------
1060 // Check for float reg-reg copy
1061 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1062 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1063 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1064 if( cbuf ) {
1066 // Note the mucking with the register encode to compensate for the 0/1
1067 // indexing issue mentioned in a comment in the reg_def sections
1068 // for FPR registers many lines above here.
1070 if( src_first != FPR1L_num ) {
1071 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1072 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1073 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1074 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1075 } else {
1076 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1077 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1078 }
1079 #ifndef PRODUCT
1080 } else if( !do_size ) {
1081 if( size != 0 ) st->print("\n\t");
1082 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1083 else st->print( "FST %s", Matcher::regName[dst_first]);
1084 #endif
1085 }
1086 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1087 }
1089 // Check for float store
1090 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1091 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1092 }
1094 // Check for float load
1095 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1096 int offset = ra_->reg2offset(src_first);
1097 const char *op_str;
1098 int op;
1099 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1100 op_str = "FLD_D";
1101 op = 0xDD;
1102 } else { // 32-bit load
1103 op_str = "FLD_S";
1104 op = 0xD9;
1105 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1106 }
1107 if( cbuf ) {
1108 emit_opcode (*cbuf, op );
1109 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1110 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1111 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1112 #ifndef PRODUCT
1113 } else if( !do_size ) {
1114 if( size != 0 ) st->print("\n\t");
1115 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1116 #endif
1117 }
1118 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1119 return size + 3+offset_size+2;
1120 }
1122 // Check for xmm reg-reg copy
1123 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1124 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1125 (src_first+1 == src_second && dst_first+1 == dst_second),
1126 "no non-adjacent float-moves" );
1127 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1128 }
1130 // Check for xmm reg-integer reg copy
1131 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1132 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1133 "no 64 bit float-integer reg moves" );
1134 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1135 }
1137 // Check for xmm store
1138 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1139 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1140 }
1142 // Check for float xmm load
1143 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1144 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1145 }
1147 // Copy from float reg to xmm reg
1148 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1149 // copy to the top of stack from floating point reg
1150 // and use LEA to preserve flags
1151 if( cbuf ) {
1152 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1153 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1154 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1155 emit_d8(*cbuf,0xF8);
1156 #ifndef PRODUCT
1157 } else if( !do_size ) {
1158 if( size != 0 ) st->print("\n\t");
1159 st->print("LEA ESP,[ESP-8]");
1160 #endif
1161 }
1162 size += 4;
1164 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1166 // Copy from the temp memory to the xmm reg.
1167 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1169 if( cbuf ) {
1170 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1171 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1172 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1173 emit_d8(*cbuf,0x08);
1174 #ifndef PRODUCT
1175 } else if( !do_size ) {
1176 if( size != 0 ) st->print("\n\t");
1177 st->print("LEA ESP,[ESP+8]");
1178 #endif
1179 }
1180 size += 4;
1181 return size;
1182 }
1184 assert( size > 0, "missed a case" );
1186 // --------------------------------------------------------------------
1187 // Check for second bits still needing moving.
1188 if( src_second == dst_second )
1189 return size; // Self copy; no move
1190 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1192 // Check for second word int-int move
1193 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1194 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1196 // Check for second word integer store
1197 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1198 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1200 // Check for second word integer load
1201 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1202 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1205 Unimplemented();
1206 }
1208 #ifndef PRODUCT
1209 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1210 implementation( NULL, ra_, false, st );
1211 }
1212 #endif
1214 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1215 implementation( &cbuf, ra_, false, NULL );
1216 }
1218 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1219 return implementation( NULL, ra_, true, NULL );
1220 }
1223 //=============================================================================
1224 #ifndef PRODUCT
1225 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1226 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1227 int reg = ra_->get_reg_first(this);
1228 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1229 }
1230 #endif
1232 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1233 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1234 int reg = ra_->get_encode(this);
1235 if( offset >= 128 ) {
1236 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1237 emit_rm(cbuf, 0x2, reg, 0x04);
1238 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1239 emit_d32(cbuf, offset);
1240 }
1241 else {
1242 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1243 emit_rm(cbuf, 0x1, reg, 0x04);
1244 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1245 emit_d8(cbuf, offset);
1246 }
1247 }
1249 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1250 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1251 if( offset >= 128 ) {
1252 return 7;
1253 }
1254 else {
1255 return 4;
1256 }
1257 }
1259 //=============================================================================
1260 #ifndef PRODUCT
1261 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1262 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1263 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1264 st->print_cr("\tNOP");
1265 st->print_cr("\tNOP");
1266 if( !OptoBreakpoint )
1267 st->print_cr("\tNOP");
1268 }
1269 #endif
1271 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1272 MacroAssembler masm(&cbuf);
1273 #ifdef ASSERT
1274 uint insts_size = cbuf.insts_size();
1275 #endif
1276 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1277 masm.jump_cc(Assembler::notEqual,
1278 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1279 /* WARNING these NOPs are critical so that verified entry point is properly
1280 aligned for patching by NativeJump::patch_verified_entry() */
1281 int nops_cnt = 2;
1282 if( !OptoBreakpoint ) // Leave space for int3
1283 nops_cnt += 1;
1284 masm.nop(nops_cnt);
1286 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1287 }
1289 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1290 return OptoBreakpoint ? 11 : 12;
1291 }
1294 //=============================================================================
1295 uint size_exception_handler() {
1296 // NativeCall instruction size is the same as NativeJump.
1297 // exception handler starts out as jump and can be patched to
1298 // a call be deoptimization. (4932387)
1299 // Note that this value is also credited (in output.cpp) to
1300 // the size of the code section.
1301 return NativeJump::instruction_size;
1302 }
1304 // Emit exception handler code. Stuff framesize into a register
1305 // and call a VM stub routine.
1306 int emit_exception_handler(CodeBuffer& cbuf) {
1308 // Note that the code buffer's insts_mark is always relative to insts.
1309 // That's why we must use the macroassembler to generate a handler.
1310 MacroAssembler _masm(&cbuf);
1311 address base =
1312 __ start_a_stub(size_exception_handler());
1313 if (base == NULL) return 0; // CodeBuffer::expand failed
1314 int offset = __ offset();
1315 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1316 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1317 __ end_a_stub();
1318 return offset;
1319 }
1321 uint size_deopt_handler() {
1322 // NativeCall instruction size is the same as NativeJump.
1323 // exception handler starts out as jump and can be patched to
1324 // a call be deoptimization. (4932387)
1325 // Note that this value is also credited (in output.cpp) to
1326 // the size of the code section.
1327 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1328 }
1330 // Emit deopt handler code.
1331 int emit_deopt_handler(CodeBuffer& cbuf) {
1333 // Note that the code buffer's insts_mark is always relative to insts.
1334 // That's why we must use the macroassembler to generate a handler.
1335 MacroAssembler _masm(&cbuf);
1336 address base =
1337 __ start_a_stub(size_exception_handler());
1338 if (base == NULL) return 0; // CodeBuffer::expand failed
1339 int offset = __ offset();
1340 InternalAddress here(__ pc());
1341 __ pushptr(here.addr());
1343 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1344 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1345 __ end_a_stub();
1346 return offset;
1347 }
1349 int Matcher::regnum_to_fpu_offset(int regnum) {
1350 return regnum - 32; // The FP registers are in the second chunk
1351 }
1353 // This is UltraSparc specific, true just means we have fast l2f conversion
1354 const bool Matcher::convL2FSupported(void) {
1355 return true;
1356 }
1358 // Is this branch offset short enough that a short branch can be used?
1359 //
1360 // NOTE: If the platform does not provide any short branch variants, then
1361 // this method should return false for offset 0.
1362 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1363 // The passed offset is relative to address of the branch.
1364 // On 86 a branch displacement is calculated relative to address
1365 // of a next instruction.
1366 offset -= br_size;
1368 // the short version of jmpConUCF2 contains multiple branches,
1369 // making the reach slightly less
1370 if (rule == jmpConUCF2_rule)
1371 return (-126 <= offset && offset <= 125);
1372 return (-128 <= offset && offset <= 127);
1373 }
1375 const bool Matcher::isSimpleConstant64(jlong value) {
1376 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1377 return false;
1378 }
1380 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1381 const bool Matcher::init_array_count_is_in_bytes = false;
1383 // Threshold size for cleararray.
1384 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1386 // Needs 2 CMOV's for longs.
1387 const int Matcher::long_cmove_cost() { return 1; }
1389 // No CMOVF/CMOVD with SSE/SSE2
1390 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1392 // Should the Matcher clone shifts on addressing modes, expecting them to
1393 // be subsumed into complex addressing expressions or compute them into
1394 // registers? True for Intel but false for most RISCs
1395 const bool Matcher::clone_shift_expressions = true;
1397 // Do we need to mask the count passed to shift instructions or does
1398 // the cpu only look at the lower 5/6 bits anyway?
1399 const bool Matcher::need_masked_shift_count = false;
1401 bool Matcher::narrow_oop_use_complex_address() {
1402 ShouldNotCallThis();
1403 return true;
1404 }
1406 bool Matcher::narrow_klass_use_complex_address() {
1407 ShouldNotCallThis();
1408 return true;
1409 }
1412 // Is it better to copy float constants, or load them directly from memory?
1413 // Intel can load a float constant from a direct address, requiring no
1414 // extra registers. Most RISCs will have to materialize an address into a
1415 // register first, so they would do better to copy the constant from stack.
1416 const bool Matcher::rematerialize_float_constants = true;
1418 // If CPU can load and store mis-aligned doubles directly then no fixup is
1419 // needed. Else we split the double into 2 integer pieces and move it
1420 // piece-by-piece. Only happens when passing doubles into C code as the
1421 // Java calling convention forces doubles to be aligned.
1422 const bool Matcher::misaligned_doubles_ok = true;
1425 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1426 // Get the memory operand from the node
1427 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1428 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1429 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1430 uint opcnt = 1; // First operand
1431 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1432 while( idx >= skipped+num_edges ) {
1433 skipped += num_edges;
1434 opcnt++; // Bump operand count
1435 assert( opcnt < numopnds, "Accessing non-existent operand" );
1436 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1437 }
1439 MachOper *memory = node->_opnds[opcnt];
1440 MachOper *new_memory = NULL;
1441 switch (memory->opcode()) {
1442 case DIRECT:
1443 case INDOFFSET32X:
1444 // No transformation necessary.
1445 return;
1446 case INDIRECT:
1447 new_memory = new (C) indirect_win95_safeOper( );
1448 break;
1449 case INDOFFSET8:
1450 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1451 break;
1452 case INDOFFSET32:
1453 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1454 break;
1455 case INDINDEXOFFSET:
1456 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1457 break;
1458 case INDINDEXSCALE:
1459 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1460 break;
1461 case INDINDEXSCALEOFFSET:
1462 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1463 break;
1464 case LOAD_LONG_INDIRECT:
1465 case LOAD_LONG_INDOFFSET32:
1466 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1467 return;
1468 default:
1469 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1470 return;
1471 }
1472 node->_opnds[opcnt] = new_memory;
1473 }
1475 // Advertise here if the CPU requires explicit rounding operations
1476 // to implement the UseStrictFP mode.
1477 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1479 // Are floats conerted to double when stored to stack during deoptimization?
1480 // On x32 it is stored with convertion only when FPU is used for floats.
1481 bool Matcher::float_in_double() { return (UseSSE == 0); }
1483 // Do ints take an entire long register or just half?
1484 const bool Matcher::int_in_long = false;
1486 // Return whether or not this register is ever used as an argument. This
1487 // function is used on startup to build the trampoline stubs in generateOptoStub.
1488 // Registers not mentioned will be killed by the VM call in the trampoline, and
1489 // arguments in those registers not be available to the callee.
1490 bool Matcher::can_be_java_arg( int reg ) {
1491 if( reg == ECX_num || reg == EDX_num ) return true;
1492 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1493 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1494 return false;
1495 }
1497 bool Matcher::is_spillable_arg( int reg ) {
1498 return can_be_java_arg(reg);
1499 }
1501 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1502 // Use hardware integer DIV instruction when
1503 // it is faster than a code which use multiply.
1504 // Only when constant divisor fits into 32 bit
1505 // (min_jint is excluded to get only correct
1506 // positive 32 bit values from negative).
1507 return VM_Version::has_fast_idiv() &&
1508 (divisor == (int)divisor && divisor != min_jint);
1509 }
1511 // Register for DIVI projection of divmodI
1512 RegMask Matcher::divI_proj_mask() {
1513 return EAX_REG_mask();
1514 }
1516 // Register for MODI projection of divmodI
1517 RegMask Matcher::modI_proj_mask() {
1518 return EDX_REG_mask();
1519 }
1521 // Register for DIVL projection of divmodL
1522 RegMask Matcher::divL_proj_mask() {
1523 ShouldNotReachHere();
1524 return RegMask();
1525 }
1527 // Register for MODL projection of divmodL
1528 RegMask Matcher::modL_proj_mask() {
1529 ShouldNotReachHere();
1530 return RegMask();
1531 }
1533 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1534 return EBP_REG_mask();
1535 }
1537 const RegMask Matcher::mathExactI_result_proj_mask() {
1538 return EAX_REG_mask();
1539 }
1541 const RegMask Matcher::mathExactL_result_proj_mask() {
1542 ShouldNotReachHere();
1543 return RegMask();
1544 }
1546 const RegMask Matcher::mathExactI_flags_proj_mask() {
1547 return INT_FLAGS_mask();
1548 }
1550 // Returns true if the high 32 bits of the value is known to be zero.
1551 bool is_operand_hi32_zero(Node* n) {
1552 int opc = n->Opcode();
1553 if (opc == Op_AndL) {
1554 Node* o2 = n->in(2);
1555 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1556 return true;
1557 }
1558 }
1559 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1560 return true;
1561 }
1562 return false;
1563 }
1565 %}
1567 //----------ENCODING BLOCK-----------------------------------------------------
1568 // This block specifies the encoding classes used by the compiler to output
1569 // byte streams. Encoding classes generate functions which are called by
1570 // Machine Instruction Nodes in order to generate the bit encoding of the
1571 // instruction. Operands specify their base encoding interface with the
1572 // interface keyword. There are currently supported four interfaces,
1573 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1574 // operand to generate a function which returns its register number when
1575 // queried. CONST_INTER causes an operand to generate a function which
1576 // returns the value of the constant when queried. MEMORY_INTER causes an
1577 // operand to generate four functions which return the Base Register, the
1578 // Index Register, the Scale Value, and the Offset Value of the operand when
1579 // queried. COND_INTER causes an operand to generate six functions which
1580 // return the encoding code (ie - encoding bits for the instruction)
1581 // associated with each basic boolean condition for a conditional instruction.
1582 // Instructions specify two basic values for encoding. They use the
1583 // ins_encode keyword to specify their encoding class (which must be one of
1584 // the class names specified in the encoding block), and they use the
1585 // opcode keyword to specify, in order, their primary, secondary, and
1586 // tertiary opcode. Only the opcode sections which a particular instruction
1587 // needs for encoding need to be specified.
1588 encode %{
1589 // Build emit functions for each basic byte or larger field in the intel
1590 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1591 // code in the enc_class source block. Emit functions will live in the
1592 // main source block for now. In future, we can generalize this by
1593 // adding a syntax that specifies the sizes of fields in an order,
1594 // so that the adlc can build the emit functions automagically
1596 // Emit primary opcode
1597 enc_class OpcP %{
1598 emit_opcode(cbuf, $primary);
1599 %}
1601 // Emit secondary opcode
1602 enc_class OpcS %{
1603 emit_opcode(cbuf, $secondary);
1604 %}
1606 // Emit opcode directly
1607 enc_class Opcode(immI d8) %{
1608 emit_opcode(cbuf, $d8$$constant);
1609 %}
1611 enc_class SizePrefix %{
1612 emit_opcode(cbuf,0x66);
1613 %}
1615 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1616 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1617 %}
1619 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1620 emit_opcode(cbuf,$opcode$$constant);
1621 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1622 %}
1624 enc_class mov_r32_imm0( rRegI dst ) %{
1625 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1626 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1627 %}
1629 enc_class cdq_enc %{
1630 // Full implementation of Java idiv and irem; checks for
1631 // special case as described in JVM spec., p.243 & p.271.
1632 //
1633 // normal case special case
1634 //
1635 // input : rax,: dividend min_int
1636 // reg: divisor -1
1637 //
1638 // output: rax,: quotient (= rax, idiv reg) min_int
1639 // rdx: remainder (= rax, irem reg) 0
1640 //
1641 // Code sequnce:
1642 //
1643 // 81 F8 00 00 00 80 cmp rax,80000000h
1644 // 0F 85 0B 00 00 00 jne normal_case
1645 // 33 D2 xor rdx,edx
1646 // 83 F9 FF cmp rcx,0FFh
1647 // 0F 84 03 00 00 00 je done
1648 // normal_case:
1649 // 99 cdq
1650 // F7 F9 idiv rax,ecx
1651 // done:
1652 //
1653 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1654 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1655 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1656 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1657 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1658 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1659 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1660 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1661 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1662 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1663 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1664 // normal_case:
1665 emit_opcode(cbuf,0x99); // cdq
1666 // idiv (note: must be emitted by the user of this rule)
1667 // normal:
1668 %}
1670 // Dense encoding for older common ops
1671 enc_class Opc_plus(immI opcode, rRegI reg) %{
1672 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1673 %}
1676 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1677 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1678 // Check for 8-bit immediate, and set sign extend bit in opcode
1679 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1680 emit_opcode(cbuf, $primary | 0x02);
1681 }
1682 else { // If 32-bit immediate
1683 emit_opcode(cbuf, $primary);
1684 }
1685 %}
1687 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1688 // Emit primary opcode and set sign-extend bit
1689 // Check for 8-bit immediate, and set sign extend bit in opcode
1690 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1691 emit_opcode(cbuf, $primary | 0x02); }
1692 else { // If 32-bit immediate
1693 emit_opcode(cbuf, $primary);
1694 }
1695 // Emit r/m byte with secondary opcode, after primary opcode.
1696 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1697 %}
1699 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1700 // Check for 8-bit immediate, and set sign extend bit in opcode
1701 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1702 $$$emit8$imm$$constant;
1703 }
1704 else { // If 32-bit immediate
1705 // Output immediate
1706 $$$emit32$imm$$constant;
1707 }
1708 %}
1710 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1711 // Emit primary opcode and set sign-extend bit
1712 // Check for 8-bit immediate, and set sign extend bit in opcode
1713 int con = (int)$imm$$constant; // Throw away top bits
1714 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1715 // Emit r/m byte with secondary opcode, after primary opcode.
1716 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1717 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1718 else emit_d32(cbuf,con);
1719 %}
1721 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1722 // Emit primary opcode and set sign-extend bit
1723 // Check for 8-bit immediate, and set sign extend bit in opcode
1724 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1725 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1726 // Emit r/m byte with tertiary opcode, after primary opcode.
1727 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1728 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1729 else emit_d32(cbuf,con);
1730 %}
1732 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1733 emit_cc(cbuf, $secondary, $dst$$reg );
1734 %}
1736 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1737 int destlo = $dst$$reg;
1738 int desthi = HIGH_FROM_LOW(destlo);
1739 // bswap lo
1740 emit_opcode(cbuf, 0x0F);
1741 emit_cc(cbuf, 0xC8, destlo);
1742 // bswap hi
1743 emit_opcode(cbuf, 0x0F);
1744 emit_cc(cbuf, 0xC8, desthi);
1745 // xchg lo and hi
1746 emit_opcode(cbuf, 0x87);
1747 emit_rm(cbuf, 0x3, destlo, desthi);
1748 %}
1750 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1751 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1752 %}
1754 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1755 $$$emit8$primary;
1756 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1757 %}
1759 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1760 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1761 emit_d8(cbuf, op >> 8 );
1762 emit_d8(cbuf, op & 255);
1763 %}
1765 // emulate a CMOV with a conditional branch around a MOV
1766 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1767 // Invert sense of branch from sense of CMOV
1768 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1769 emit_d8( cbuf, $brOffs$$constant );
1770 %}
1772 enc_class enc_PartialSubtypeCheck( ) %{
1773 Register Redi = as_Register(EDI_enc); // result register
1774 Register Reax = as_Register(EAX_enc); // super class
1775 Register Recx = as_Register(ECX_enc); // killed
1776 Register Resi = as_Register(ESI_enc); // sub class
1777 Label miss;
1779 MacroAssembler _masm(&cbuf);
1780 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1781 NULL, &miss,
1782 /*set_cond_codes:*/ true);
1783 if ($primary) {
1784 __ xorptr(Redi, Redi);
1785 }
1786 __ bind(miss);
1787 %}
1789 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1790 MacroAssembler masm(&cbuf);
1791 int start = masm.offset();
1792 if (UseSSE >= 2) {
1793 if (VerifyFPU) {
1794 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1795 }
1796 } else {
1797 // External c_calling_convention expects the FPU stack to be 'clean'.
1798 // Compiled code leaves it dirty. Do cleanup now.
1799 masm.empty_FPU_stack();
1800 }
1801 if (sizeof_FFree_Float_Stack_All == -1) {
1802 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1803 } else {
1804 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1805 }
1806 %}
1808 enc_class Verify_FPU_For_Leaf %{
1809 if( VerifyFPU ) {
1810 MacroAssembler masm(&cbuf);
1811 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1812 }
1813 %}
1815 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1816 // This is the instruction starting address for relocation info.
1817 cbuf.set_insts_mark();
1818 $$$emit8$primary;
1819 // CALL directly to the runtime
1820 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1821 runtime_call_Relocation::spec(), RELOC_IMM32 );
1823 if (UseSSE >= 2) {
1824 MacroAssembler _masm(&cbuf);
1825 BasicType rt = tf()->return_type();
1827 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1828 // A C runtime call where the return value is unused. In SSE2+
1829 // mode the result needs to be removed from the FPU stack. It's
1830 // likely that this function call could be removed by the
1831 // optimizer if the C function is a pure function.
1832 __ ffree(0);
1833 } else if (rt == T_FLOAT) {
1834 __ lea(rsp, Address(rsp, -4));
1835 __ fstp_s(Address(rsp, 0));
1836 __ movflt(xmm0, Address(rsp, 0));
1837 __ lea(rsp, Address(rsp, 4));
1838 } else if (rt == T_DOUBLE) {
1839 __ lea(rsp, Address(rsp, -8));
1840 __ fstp_d(Address(rsp, 0));
1841 __ movdbl(xmm0, Address(rsp, 0));
1842 __ lea(rsp, Address(rsp, 8));
1843 }
1844 }
1845 %}
1848 enc_class pre_call_resets %{
1849 // If method sets FPU control word restore it here
1850 debug_only(int off0 = cbuf.insts_size());
1851 if (ra_->C->in_24_bit_fp_mode()) {
1852 MacroAssembler _masm(&cbuf);
1853 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1854 }
1855 if (ra_->C->max_vector_size() > 16) {
1856 // Clear upper bits of YMM registers when current compiled code uses
1857 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1858 MacroAssembler _masm(&cbuf);
1859 __ vzeroupper();
1860 }
1861 debug_only(int off1 = cbuf.insts_size());
1862 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction");
1863 %}
1865 enc_class post_call_FPU %{
1866 // If method sets FPU control word do it here also
1867 if (Compile::current()->in_24_bit_fp_mode()) {
1868 MacroAssembler masm(&cbuf);
1869 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1870 }
1871 %}
1873 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1874 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1875 // who we intended to call.
1876 cbuf.set_insts_mark();
1877 $$$emit8$primary;
1878 if (!_method) {
1879 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1880 runtime_call_Relocation::spec(), RELOC_IMM32 );
1881 } else if (_optimized_virtual) {
1882 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1883 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1884 } else {
1885 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1886 static_call_Relocation::spec(), RELOC_IMM32 );
1887 }
1888 if (_method) { // Emit stub for static call.
1889 CompiledStaticCall::emit_to_interp_stub(cbuf);
1890 }
1891 %}
1893 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1894 MacroAssembler _masm(&cbuf);
1895 __ ic_call((address)$meth$$method);
1896 %}
1898 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1899 int disp = in_bytes(Method::from_compiled_offset());
1900 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1902 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1903 cbuf.set_insts_mark();
1904 $$$emit8$primary;
1905 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1906 emit_d8(cbuf, disp); // Displacement
1908 %}
1910 // Following encoding is no longer used, but may be restored if calling
1911 // convention changes significantly.
1912 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1913 //
1914 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1915 // // int ic_reg = Matcher::inline_cache_reg();
1916 // // int ic_encode = Matcher::_regEncode[ic_reg];
1917 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1918 // // int imo_encode = Matcher::_regEncode[imo_reg];
1919 //
1920 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1921 // // // so we load it immediately before the call
1922 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1923 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1924 //
1925 // // xor rbp,ebp
1926 // emit_opcode(cbuf, 0x33);
1927 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1928 //
1929 // // CALL to interpreter.
1930 // cbuf.set_insts_mark();
1931 // $$$emit8$primary;
1932 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1933 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1934 // %}
1936 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1937 $$$emit8$primary;
1938 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1939 $$$emit8$shift$$constant;
1940 %}
1942 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1943 // Load immediate does not have a zero or sign extended version
1944 // for 8-bit immediates
1945 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1946 $$$emit32$src$$constant;
1947 %}
1949 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1950 // Load immediate does not have a zero or sign extended version
1951 // for 8-bit immediates
1952 emit_opcode(cbuf, $primary + $dst$$reg);
1953 $$$emit32$src$$constant;
1954 %}
1956 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1957 // Load immediate does not have a zero or sign extended version
1958 // for 8-bit immediates
1959 int dst_enc = $dst$$reg;
1960 int src_con = $src$$constant & 0x0FFFFFFFFL;
1961 if (src_con == 0) {
1962 // xor dst, dst
1963 emit_opcode(cbuf, 0x33);
1964 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1965 } else {
1966 emit_opcode(cbuf, $primary + dst_enc);
1967 emit_d32(cbuf, src_con);
1968 }
1969 %}
1971 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1972 // Load immediate does not have a zero or sign extended version
1973 // for 8-bit immediates
1974 int dst_enc = $dst$$reg + 2;
1975 int src_con = ((julong)($src$$constant)) >> 32;
1976 if (src_con == 0) {
1977 // xor dst, dst
1978 emit_opcode(cbuf, 0x33);
1979 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1980 } else {
1981 emit_opcode(cbuf, $primary + dst_enc);
1982 emit_d32(cbuf, src_con);
1983 }
1984 %}
1987 // Encode a reg-reg copy. If it is useless, then empty encoding.
1988 enc_class enc_Copy( rRegI dst, rRegI src ) %{
1989 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1990 %}
1992 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
1993 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1994 %}
1996 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1997 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1998 %}
2000 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2001 $$$emit8$primary;
2002 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2003 %}
2005 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2006 $$$emit8$secondary;
2007 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2008 %}
2010 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2011 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2012 %}
2014 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2015 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2016 %}
2018 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2019 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2020 %}
2022 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2023 // Output immediate
2024 $$$emit32$src$$constant;
2025 %}
2027 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
2028 // Output Float immediate bits
2029 jfloat jf = $src$$constant;
2030 int jf_as_bits = jint_cast( jf );
2031 emit_d32(cbuf, jf_as_bits);
2032 %}
2034 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
2035 // Output Float immediate bits
2036 jfloat jf = $src$$constant;
2037 int jf_as_bits = jint_cast( jf );
2038 emit_d32(cbuf, jf_as_bits);
2039 %}
2041 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2042 // Output immediate
2043 $$$emit16$src$$constant;
2044 %}
2046 enc_class Con_d32(immI src) %{
2047 emit_d32(cbuf,$src$$constant);
2048 %}
2050 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2051 // Output immediate memory reference
2052 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2053 emit_d32(cbuf, 0x00);
2054 %}
2056 enc_class lock_prefix( ) %{
2057 if( os::is_MP() )
2058 emit_opcode(cbuf,0xF0); // [Lock]
2059 %}
2061 // Cmp-xchg long value.
2062 // Note: we need to swap rbx, and rcx before and after the
2063 // cmpxchg8 instruction because the instruction uses
2064 // rcx as the high order word of the new value to store but
2065 // our register encoding uses rbx,.
2066 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2068 // XCHG rbx,ecx
2069 emit_opcode(cbuf,0x87);
2070 emit_opcode(cbuf,0xD9);
2071 // [Lock]
2072 if( os::is_MP() )
2073 emit_opcode(cbuf,0xF0);
2074 // CMPXCHG8 [Eptr]
2075 emit_opcode(cbuf,0x0F);
2076 emit_opcode(cbuf,0xC7);
2077 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2078 // XCHG rbx,ecx
2079 emit_opcode(cbuf,0x87);
2080 emit_opcode(cbuf,0xD9);
2081 %}
2083 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2084 // [Lock]
2085 if( os::is_MP() )
2086 emit_opcode(cbuf,0xF0);
2088 // CMPXCHG [Eptr]
2089 emit_opcode(cbuf,0x0F);
2090 emit_opcode(cbuf,0xB1);
2091 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2092 %}
2094 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2095 int res_encoding = $res$$reg;
2097 // MOV res,0
2098 emit_opcode( cbuf, 0xB8 + res_encoding);
2099 emit_d32( cbuf, 0 );
2100 // JNE,s fail
2101 emit_opcode(cbuf,0x75);
2102 emit_d8(cbuf, 5 );
2103 // MOV res,1
2104 emit_opcode( cbuf, 0xB8 + res_encoding);
2105 emit_d32( cbuf, 1 );
2106 // fail:
2107 %}
2109 enc_class set_instruction_start( ) %{
2110 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2111 %}
2113 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2114 int reg_encoding = $ereg$$reg;
2115 int base = $mem$$base;
2116 int index = $mem$$index;
2117 int scale = $mem$$scale;
2118 int displace = $mem$$disp;
2119 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2120 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2121 %}
2123 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2124 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2125 int base = $mem$$base;
2126 int index = $mem$$index;
2127 int scale = $mem$$scale;
2128 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2129 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2130 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2131 %}
2133 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2134 int r1, r2;
2135 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2136 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2137 emit_opcode(cbuf,0x0F);
2138 emit_opcode(cbuf,$tertiary);
2139 emit_rm(cbuf, 0x3, r1, r2);
2140 emit_d8(cbuf,$cnt$$constant);
2141 emit_d8(cbuf,$primary);
2142 emit_rm(cbuf, 0x3, $secondary, r1);
2143 emit_d8(cbuf,$cnt$$constant);
2144 %}
2146 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2147 emit_opcode( cbuf, 0x8B ); // Move
2148 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2149 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2150 emit_d8(cbuf,$primary);
2151 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2152 emit_d8(cbuf,$cnt$$constant-32);
2153 }
2154 emit_d8(cbuf,$primary);
2155 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2156 emit_d8(cbuf,31);
2157 %}
2159 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2160 int r1, r2;
2161 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2162 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2164 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2165 emit_rm(cbuf, 0x3, r1, r2);
2166 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2167 emit_opcode(cbuf,$primary);
2168 emit_rm(cbuf, 0x3, $secondary, r1);
2169 emit_d8(cbuf,$cnt$$constant-32);
2170 }
2171 emit_opcode(cbuf,0x33); // XOR r2,r2
2172 emit_rm(cbuf, 0x3, r2, r2);
2173 %}
2175 // Clone of RegMem but accepts an extra parameter to access each
2176 // half of a double in memory; it never needs relocation info.
2177 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2178 emit_opcode(cbuf,$opcode$$constant);
2179 int reg_encoding = $rm_reg$$reg;
2180 int base = $mem$$base;
2181 int index = $mem$$index;
2182 int scale = $mem$$scale;
2183 int displace = $mem$$disp + $disp_for_half$$constant;
2184 relocInfo::relocType disp_reloc = relocInfo::none;
2185 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2186 %}
2188 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2189 //
2190 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2191 // and it never needs relocation information.
2192 // Frequently used to move data between FPU's Stack Top and memory.
2193 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2194 int rm_byte_opcode = $rm_opcode$$constant;
2195 int base = $mem$$base;
2196 int index = $mem$$index;
2197 int scale = $mem$$scale;
2198 int displace = $mem$$disp;
2199 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2200 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2201 %}
2203 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2204 int rm_byte_opcode = $rm_opcode$$constant;
2205 int base = $mem$$base;
2206 int index = $mem$$index;
2207 int scale = $mem$$scale;
2208 int displace = $mem$$disp;
2209 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2210 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2211 %}
2213 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2214 int reg_encoding = $dst$$reg;
2215 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2216 int index = 0x04; // 0x04 indicates no index
2217 int scale = 0x00; // 0x00 indicates no scale
2218 int displace = $src1$$constant; // 0x00 indicates no displacement
2219 relocInfo::relocType disp_reloc = relocInfo::none;
2220 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2221 %}
2223 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2224 // Compare dst,src
2225 emit_opcode(cbuf,0x3B);
2226 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2227 // jmp dst < src around move
2228 emit_opcode(cbuf,0x7C);
2229 emit_d8(cbuf,2);
2230 // move dst,src
2231 emit_opcode(cbuf,0x8B);
2232 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2233 %}
2235 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2236 // Compare dst,src
2237 emit_opcode(cbuf,0x3B);
2238 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2239 // jmp dst > src around move
2240 emit_opcode(cbuf,0x7F);
2241 emit_d8(cbuf,2);
2242 // move dst,src
2243 emit_opcode(cbuf,0x8B);
2244 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2245 %}
2247 enc_class enc_FPR_store(memory mem, regDPR src) %{
2248 // If src is FPR1, we can just FST to store it.
2249 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2250 int reg_encoding = 0x2; // Just store
2251 int base = $mem$$base;
2252 int index = $mem$$index;
2253 int scale = $mem$$scale;
2254 int displace = $mem$$disp;
2255 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2256 if( $src$$reg != FPR1L_enc ) {
2257 reg_encoding = 0x3; // Store & pop
2258 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2259 emit_d8( cbuf, 0xC0-1+$src$$reg );
2260 }
2261 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2262 emit_opcode(cbuf,$primary);
2263 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2264 %}
2266 enc_class neg_reg(rRegI dst) %{
2267 // NEG $dst
2268 emit_opcode(cbuf,0xF7);
2269 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2270 %}
2272 enc_class setLT_reg(eCXRegI dst) %{
2273 // SETLT $dst
2274 emit_opcode(cbuf,0x0F);
2275 emit_opcode(cbuf,0x9C);
2276 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2277 %}
2279 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2280 int tmpReg = $tmp$$reg;
2282 // SUB $p,$q
2283 emit_opcode(cbuf,0x2B);
2284 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2285 // SBB $tmp,$tmp
2286 emit_opcode(cbuf,0x1B);
2287 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2288 // AND $tmp,$y
2289 emit_opcode(cbuf,0x23);
2290 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2291 // ADD $p,$tmp
2292 emit_opcode(cbuf,0x03);
2293 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2294 %}
2296 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2297 // TEST shift,32
2298 emit_opcode(cbuf,0xF7);
2299 emit_rm(cbuf, 0x3, 0, ECX_enc);
2300 emit_d32(cbuf,0x20);
2301 // JEQ,s small
2302 emit_opcode(cbuf, 0x74);
2303 emit_d8(cbuf, 0x04);
2304 // MOV $dst.hi,$dst.lo
2305 emit_opcode( cbuf, 0x8B );
2306 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2307 // CLR $dst.lo
2308 emit_opcode(cbuf, 0x33);
2309 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2310 // small:
2311 // SHLD $dst.hi,$dst.lo,$shift
2312 emit_opcode(cbuf,0x0F);
2313 emit_opcode(cbuf,0xA5);
2314 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2315 // SHL $dst.lo,$shift"
2316 emit_opcode(cbuf,0xD3);
2317 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2318 %}
2320 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2321 // TEST shift,32
2322 emit_opcode(cbuf,0xF7);
2323 emit_rm(cbuf, 0x3, 0, ECX_enc);
2324 emit_d32(cbuf,0x20);
2325 // JEQ,s small
2326 emit_opcode(cbuf, 0x74);
2327 emit_d8(cbuf, 0x04);
2328 // MOV $dst.lo,$dst.hi
2329 emit_opcode( cbuf, 0x8B );
2330 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2331 // CLR $dst.hi
2332 emit_opcode(cbuf, 0x33);
2333 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2334 // small:
2335 // SHRD $dst.lo,$dst.hi,$shift
2336 emit_opcode(cbuf,0x0F);
2337 emit_opcode(cbuf,0xAD);
2338 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2339 // SHR $dst.hi,$shift"
2340 emit_opcode(cbuf,0xD3);
2341 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2342 %}
2344 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2345 // TEST shift,32
2346 emit_opcode(cbuf,0xF7);
2347 emit_rm(cbuf, 0x3, 0, ECX_enc);
2348 emit_d32(cbuf,0x20);
2349 // JEQ,s small
2350 emit_opcode(cbuf, 0x74);
2351 emit_d8(cbuf, 0x05);
2352 // MOV $dst.lo,$dst.hi
2353 emit_opcode( cbuf, 0x8B );
2354 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2355 // SAR $dst.hi,31
2356 emit_opcode(cbuf, 0xC1);
2357 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2358 emit_d8(cbuf, 0x1F );
2359 // small:
2360 // SHRD $dst.lo,$dst.hi,$shift
2361 emit_opcode(cbuf,0x0F);
2362 emit_opcode(cbuf,0xAD);
2363 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2364 // SAR $dst.hi,$shift"
2365 emit_opcode(cbuf,0xD3);
2366 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2367 %}
2370 // ----------------- Encodings for floating point unit -----------------
2371 // May leave result in FPU-TOS or FPU reg depending on opcodes
2372 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2373 $$$emit8$primary;
2374 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2375 %}
2377 // Pop argument in FPR0 with FSTP ST(0)
2378 enc_class PopFPU() %{
2379 emit_opcode( cbuf, 0xDD );
2380 emit_d8( cbuf, 0xD8 );
2381 %}
2383 // !!!!! equivalent to Pop_Reg_F
2384 enc_class Pop_Reg_DPR( regDPR dst ) %{
2385 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2386 emit_d8( cbuf, 0xD8+$dst$$reg );
2387 %}
2389 enc_class Push_Reg_DPR( regDPR dst ) %{
2390 emit_opcode( cbuf, 0xD9 );
2391 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2392 %}
2394 enc_class strictfp_bias1( regDPR dst ) %{
2395 emit_opcode( cbuf, 0xDB ); // FLD m80real
2396 emit_opcode( cbuf, 0x2D );
2397 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2398 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2399 emit_opcode( cbuf, 0xC8+$dst$$reg );
2400 %}
2402 enc_class strictfp_bias2( regDPR dst ) %{
2403 emit_opcode( cbuf, 0xDB ); // FLD m80real
2404 emit_opcode( cbuf, 0x2D );
2405 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2406 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2407 emit_opcode( cbuf, 0xC8+$dst$$reg );
2408 %}
2410 // Special case for moving an integer register to a stack slot.
2411 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2412 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2413 %}
2415 // Special case for moving a register to a stack slot.
2416 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2417 // Opcode already emitted
2418 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2419 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2420 emit_d32(cbuf, $dst$$disp); // Displacement
2421 %}
2423 // Push the integer in stackSlot 'src' onto FP-stack
2424 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2425 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2426 %}
2428 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2429 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2430 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2431 %}
2433 // Same as Pop_Mem_F except for opcode
2434 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2435 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2436 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2437 %}
2439 enc_class Pop_Reg_FPR( regFPR dst ) %{
2440 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2441 emit_d8( cbuf, 0xD8+$dst$$reg );
2442 %}
2444 enc_class Push_Reg_FPR( regFPR dst ) %{
2445 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2446 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2447 %}
2449 // Push FPU's float to a stack-slot, and pop FPU-stack
2450 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2451 int pop = 0x02;
2452 if ($src$$reg != FPR1L_enc) {
2453 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2454 emit_d8( cbuf, 0xC0-1+$src$$reg );
2455 pop = 0x03;
2456 }
2457 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2458 %}
2460 // Push FPU's double to a stack-slot, and pop FPU-stack
2461 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2462 int pop = 0x02;
2463 if ($src$$reg != FPR1L_enc) {
2464 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2465 emit_d8( cbuf, 0xC0-1+$src$$reg );
2466 pop = 0x03;
2467 }
2468 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2469 %}
2471 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2472 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2473 int pop = 0xD0 - 1; // -1 since we skip FLD
2474 if ($src$$reg != FPR1L_enc) {
2475 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2476 emit_d8( cbuf, 0xC0-1+$src$$reg );
2477 pop = 0xD8;
2478 }
2479 emit_opcode( cbuf, 0xDD );
2480 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2481 %}
2484 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2485 // load dst in FPR0
2486 emit_opcode( cbuf, 0xD9 );
2487 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2488 if ($src$$reg != FPR1L_enc) {
2489 // fincstp
2490 emit_opcode (cbuf, 0xD9);
2491 emit_opcode (cbuf, 0xF7);
2492 // swap src with FPR1:
2493 // FXCH FPR1 with src
2494 emit_opcode(cbuf, 0xD9);
2495 emit_d8(cbuf, 0xC8-1+$src$$reg );
2496 // fdecstp
2497 emit_opcode (cbuf, 0xD9);
2498 emit_opcode (cbuf, 0xF6);
2499 }
2500 %}
2502 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2503 MacroAssembler _masm(&cbuf);
2504 __ subptr(rsp, 8);
2505 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2506 __ fld_d(Address(rsp, 0));
2507 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2508 __ fld_d(Address(rsp, 0));
2509 %}
2511 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2512 MacroAssembler _masm(&cbuf);
2513 __ subptr(rsp, 4);
2514 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2515 __ fld_s(Address(rsp, 0));
2516 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2517 __ fld_s(Address(rsp, 0));
2518 %}
2520 enc_class Push_ResultD(regD dst) %{
2521 MacroAssembler _masm(&cbuf);
2522 __ fstp_d(Address(rsp, 0));
2523 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2524 __ addptr(rsp, 8);
2525 %}
2527 enc_class Push_ResultF(regF dst, immI d8) %{
2528 MacroAssembler _masm(&cbuf);
2529 __ fstp_s(Address(rsp, 0));
2530 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2531 __ addptr(rsp, $d8$$constant);
2532 %}
2534 enc_class Push_SrcD(regD src) %{
2535 MacroAssembler _masm(&cbuf);
2536 __ subptr(rsp, 8);
2537 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2538 __ fld_d(Address(rsp, 0));
2539 %}
2541 enc_class push_stack_temp_qword() %{
2542 MacroAssembler _masm(&cbuf);
2543 __ subptr(rsp, 8);
2544 %}
2546 enc_class pop_stack_temp_qword() %{
2547 MacroAssembler _masm(&cbuf);
2548 __ addptr(rsp, 8);
2549 %}
2551 enc_class push_xmm_to_fpr1(regD src) %{
2552 MacroAssembler _masm(&cbuf);
2553 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2554 __ fld_d(Address(rsp, 0));
2555 %}
2557 enc_class Push_Result_Mod_DPR( regDPR src) %{
2558 if ($src$$reg != FPR1L_enc) {
2559 // fincstp
2560 emit_opcode (cbuf, 0xD9);
2561 emit_opcode (cbuf, 0xF7);
2562 // FXCH FPR1 with src
2563 emit_opcode(cbuf, 0xD9);
2564 emit_d8(cbuf, 0xC8-1+$src$$reg );
2565 // fdecstp
2566 emit_opcode (cbuf, 0xD9);
2567 emit_opcode (cbuf, 0xF6);
2568 }
2569 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2570 // // FSTP FPR$dst$$reg
2571 // emit_opcode( cbuf, 0xDD );
2572 // emit_d8( cbuf, 0xD8+$dst$$reg );
2573 %}
2575 enc_class fnstsw_sahf_skip_parity() %{
2576 // fnstsw ax
2577 emit_opcode( cbuf, 0xDF );
2578 emit_opcode( cbuf, 0xE0 );
2579 // sahf
2580 emit_opcode( cbuf, 0x9E );
2581 // jnp ::skip
2582 emit_opcode( cbuf, 0x7B );
2583 emit_opcode( cbuf, 0x05 );
2584 %}
2586 enc_class emitModDPR() %{
2587 // fprem must be iterative
2588 // :: loop
2589 // fprem
2590 emit_opcode( cbuf, 0xD9 );
2591 emit_opcode( cbuf, 0xF8 );
2592 // wait
2593 emit_opcode( cbuf, 0x9b );
2594 // fnstsw ax
2595 emit_opcode( cbuf, 0xDF );
2596 emit_opcode( cbuf, 0xE0 );
2597 // sahf
2598 emit_opcode( cbuf, 0x9E );
2599 // jp ::loop
2600 emit_opcode( cbuf, 0x0F );
2601 emit_opcode( cbuf, 0x8A );
2602 emit_opcode( cbuf, 0xF4 );
2603 emit_opcode( cbuf, 0xFF );
2604 emit_opcode( cbuf, 0xFF );
2605 emit_opcode( cbuf, 0xFF );
2606 %}
2608 enc_class fpu_flags() %{
2609 // fnstsw_ax
2610 emit_opcode( cbuf, 0xDF);
2611 emit_opcode( cbuf, 0xE0);
2612 // test ax,0x0400
2613 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2614 emit_opcode( cbuf, 0xA9 );
2615 emit_d16 ( cbuf, 0x0400 );
2616 // // // This sequence works, but stalls for 12-16 cycles on PPro
2617 // // test rax,0x0400
2618 // emit_opcode( cbuf, 0xA9 );
2619 // emit_d32 ( cbuf, 0x00000400 );
2620 //
2621 // jz exit (no unordered comparison)
2622 emit_opcode( cbuf, 0x74 );
2623 emit_d8 ( cbuf, 0x02 );
2624 // mov ah,1 - treat as LT case (set carry flag)
2625 emit_opcode( cbuf, 0xB4 );
2626 emit_d8 ( cbuf, 0x01 );
2627 // sahf
2628 emit_opcode( cbuf, 0x9E);
2629 %}
2631 enc_class cmpF_P6_fixup() %{
2632 // Fixup the integer flags in case comparison involved a NaN
2633 //
2634 // JNP exit (no unordered comparison, P-flag is set by NaN)
2635 emit_opcode( cbuf, 0x7B );
2636 emit_d8 ( cbuf, 0x03 );
2637 // MOV AH,1 - treat as LT case (set carry flag)
2638 emit_opcode( cbuf, 0xB4 );
2639 emit_d8 ( cbuf, 0x01 );
2640 // SAHF
2641 emit_opcode( cbuf, 0x9E);
2642 // NOP // target for branch to avoid branch to branch
2643 emit_opcode( cbuf, 0x90);
2644 %}
2646 // fnstsw_ax();
2647 // sahf();
2648 // movl(dst, nan_result);
2649 // jcc(Assembler::parity, exit);
2650 // movl(dst, less_result);
2651 // jcc(Assembler::below, exit);
2652 // movl(dst, equal_result);
2653 // jcc(Assembler::equal, exit);
2654 // movl(dst, greater_result);
2656 // less_result = 1;
2657 // greater_result = -1;
2658 // equal_result = 0;
2659 // nan_result = -1;
2661 enc_class CmpF_Result(rRegI dst) %{
2662 // fnstsw_ax();
2663 emit_opcode( cbuf, 0xDF);
2664 emit_opcode( cbuf, 0xE0);
2665 // sahf
2666 emit_opcode( cbuf, 0x9E);
2667 // movl(dst, nan_result);
2668 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2669 emit_d32( cbuf, -1 );
2670 // jcc(Assembler::parity, exit);
2671 emit_opcode( cbuf, 0x7A );
2672 emit_d8 ( cbuf, 0x13 );
2673 // movl(dst, less_result);
2674 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2675 emit_d32( cbuf, -1 );
2676 // jcc(Assembler::below, exit);
2677 emit_opcode( cbuf, 0x72 );
2678 emit_d8 ( cbuf, 0x0C );
2679 // movl(dst, equal_result);
2680 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2681 emit_d32( cbuf, 0 );
2682 // jcc(Assembler::equal, exit);
2683 emit_opcode( cbuf, 0x74 );
2684 emit_d8 ( cbuf, 0x05 );
2685 // movl(dst, greater_result);
2686 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2687 emit_d32( cbuf, 1 );
2688 %}
2691 // Compare the longs and set flags
2692 // BROKEN! Do Not use as-is
2693 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2694 // CMP $src1.hi,$src2.hi
2695 emit_opcode( cbuf, 0x3B );
2696 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2697 // JNE,s done
2698 emit_opcode(cbuf,0x75);
2699 emit_d8(cbuf, 2 );
2700 // CMP $src1.lo,$src2.lo
2701 emit_opcode( cbuf, 0x3B );
2702 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2703 // done:
2704 %}
2706 enc_class convert_int_long( regL dst, rRegI src ) %{
2707 // mov $dst.lo,$src
2708 int dst_encoding = $dst$$reg;
2709 int src_encoding = $src$$reg;
2710 encode_Copy( cbuf, dst_encoding , src_encoding );
2711 // mov $dst.hi,$src
2712 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2713 // sar $dst.hi,31
2714 emit_opcode( cbuf, 0xC1 );
2715 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2716 emit_d8(cbuf, 0x1F );
2717 %}
2719 enc_class convert_long_double( eRegL src ) %{
2720 // push $src.hi
2721 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2722 // push $src.lo
2723 emit_opcode(cbuf, 0x50+$src$$reg );
2724 // fild 64-bits at [SP]
2725 emit_opcode(cbuf,0xdf);
2726 emit_d8(cbuf, 0x6C);
2727 emit_d8(cbuf, 0x24);
2728 emit_d8(cbuf, 0x00);
2729 // pop stack
2730 emit_opcode(cbuf, 0x83); // add SP, #8
2731 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2732 emit_d8(cbuf, 0x8);
2733 %}
2735 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2736 // IMUL EDX:EAX,$src1
2737 emit_opcode( cbuf, 0xF7 );
2738 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2739 // SAR EDX,$cnt-32
2740 int shift_count = ((int)$cnt$$constant) - 32;
2741 if (shift_count > 0) {
2742 emit_opcode(cbuf, 0xC1);
2743 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2744 emit_d8(cbuf, shift_count);
2745 }
2746 %}
2748 // this version doesn't have add sp, 8
2749 enc_class convert_long_double2( eRegL src ) %{
2750 // push $src.hi
2751 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2752 // push $src.lo
2753 emit_opcode(cbuf, 0x50+$src$$reg );
2754 // fild 64-bits at [SP]
2755 emit_opcode(cbuf,0xdf);
2756 emit_d8(cbuf, 0x6C);
2757 emit_d8(cbuf, 0x24);
2758 emit_d8(cbuf, 0x00);
2759 %}
2761 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2762 // Basic idea: long = (long)int * (long)int
2763 // IMUL EDX:EAX, src
2764 emit_opcode( cbuf, 0xF7 );
2765 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2766 %}
2768 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2769 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2770 // MUL EDX:EAX, src
2771 emit_opcode( cbuf, 0xF7 );
2772 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2773 %}
2775 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2776 // Basic idea: lo(result) = lo(x_lo * y_lo)
2777 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2778 // MOV $tmp,$src.lo
2779 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2780 // IMUL $tmp,EDX
2781 emit_opcode( cbuf, 0x0F );
2782 emit_opcode( cbuf, 0xAF );
2783 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2784 // MOV EDX,$src.hi
2785 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2786 // IMUL EDX,EAX
2787 emit_opcode( cbuf, 0x0F );
2788 emit_opcode( cbuf, 0xAF );
2789 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2790 // ADD $tmp,EDX
2791 emit_opcode( cbuf, 0x03 );
2792 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2793 // MUL EDX:EAX,$src.lo
2794 emit_opcode( cbuf, 0xF7 );
2795 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2796 // ADD EDX,ESI
2797 emit_opcode( cbuf, 0x03 );
2798 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2799 %}
2801 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2802 // Basic idea: lo(result) = lo(src * y_lo)
2803 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2804 // IMUL $tmp,EDX,$src
2805 emit_opcode( cbuf, 0x6B );
2806 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2807 emit_d8( cbuf, (int)$src$$constant );
2808 // MOV EDX,$src
2809 emit_opcode(cbuf, 0xB8 + EDX_enc);
2810 emit_d32( cbuf, (int)$src$$constant );
2811 // MUL EDX:EAX,EDX
2812 emit_opcode( cbuf, 0xF7 );
2813 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2814 // ADD EDX,ESI
2815 emit_opcode( cbuf, 0x03 );
2816 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2817 %}
2819 enc_class long_div( eRegL src1, eRegL src2 ) %{
2820 // PUSH src1.hi
2821 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2822 // PUSH src1.lo
2823 emit_opcode(cbuf, 0x50+$src1$$reg );
2824 // PUSH src2.hi
2825 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2826 // PUSH src2.lo
2827 emit_opcode(cbuf, 0x50+$src2$$reg );
2828 // CALL directly to the runtime
2829 cbuf.set_insts_mark();
2830 emit_opcode(cbuf,0xE8); // Call into runtime
2831 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2832 // Restore stack
2833 emit_opcode(cbuf, 0x83); // add SP, #framesize
2834 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2835 emit_d8(cbuf, 4*4);
2836 %}
2838 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2839 // PUSH src1.hi
2840 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2841 // PUSH src1.lo
2842 emit_opcode(cbuf, 0x50+$src1$$reg );
2843 // PUSH src2.hi
2844 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2845 // PUSH src2.lo
2846 emit_opcode(cbuf, 0x50+$src2$$reg );
2847 // CALL directly to the runtime
2848 cbuf.set_insts_mark();
2849 emit_opcode(cbuf,0xE8); // Call into runtime
2850 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2851 // Restore stack
2852 emit_opcode(cbuf, 0x83); // add SP, #framesize
2853 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2854 emit_d8(cbuf, 4*4);
2855 %}
2857 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2858 // MOV $tmp,$src.lo
2859 emit_opcode(cbuf, 0x8B);
2860 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2861 // OR $tmp,$src.hi
2862 emit_opcode(cbuf, 0x0B);
2863 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2864 %}
2866 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2867 // CMP $src1.lo,$src2.lo
2868 emit_opcode( cbuf, 0x3B );
2869 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2870 // JNE,s skip
2871 emit_cc(cbuf, 0x70, 0x5);
2872 emit_d8(cbuf,2);
2873 // CMP $src1.hi,$src2.hi
2874 emit_opcode( cbuf, 0x3B );
2875 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2876 %}
2878 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2879 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2880 emit_opcode( cbuf, 0x3B );
2881 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2882 // MOV $tmp,$src1.hi
2883 emit_opcode( cbuf, 0x8B );
2884 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2885 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2886 emit_opcode( cbuf, 0x1B );
2887 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2888 %}
2890 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2891 // XOR $tmp,$tmp
2892 emit_opcode(cbuf,0x33); // XOR
2893 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2894 // CMP $tmp,$src.lo
2895 emit_opcode( cbuf, 0x3B );
2896 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2897 // SBB $tmp,$src.hi
2898 emit_opcode( cbuf, 0x1B );
2899 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2900 %}
2902 // Sniff, sniff... smells like Gnu Superoptimizer
2903 enc_class neg_long( eRegL dst ) %{
2904 emit_opcode(cbuf,0xF7); // NEG hi
2905 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2906 emit_opcode(cbuf,0xF7); // NEG lo
2907 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2908 emit_opcode(cbuf,0x83); // SBB hi,0
2909 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2910 emit_d8 (cbuf,0 );
2911 %}
2914 // Because the transitions from emitted code to the runtime
2915 // monitorenter/exit helper stubs are so slow it's critical that
2916 // we inline both the stack-locking fast-path and the inflated fast path.
2917 //
2918 // See also: cmpFastLock and cmpFastUnlock.
2919 //
2920 // What follows is a specialized inline transliteration of the code
2921 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2922 // another option would be to emit TrySlowEnter and TrySlowExit methods
2923 // at startup-time. These methods would accept arguments as
2924 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2925 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2926 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2927 // In practice, however, the # of lock sites is bounded and is usually small.
2928 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2929 // if the processor uses simple bimodal branch predictors keyed by EIP
2930 // Since the helper routines would be called from multiple synchronization
2931 // sites.
2932 //
2933 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2934 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2935 // to those specialized methods. That'd give us a mostly platform-independent
2936 // implementation that the JITs could optimize and inline at their pleasure.
2937 // Done correctly, the only time we'd need to cross to native could would be
2938 // to park() or unpark() threads. We'd also need a few more unsafe operators
2939 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2940 // (b) explicit barriers or fence operations.
2941 //
2942 // TODO:
2943 //
2944 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2945 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2946 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2947 // the lock operators would typically be faster than reifying Self.
2948 //
2949 // * Ideally I'd define the primitives as:
2950 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2951 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2952 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
2953 // Instead, we're stuck with a rather awkward and brittle register assignments below.
2954 // Furthermore the register assignments are overconstrained, possibly resulting in
2955 // sub-optimal code near the synchronization site.
2956 //
2957 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
2958 // Alternately, use a better sp-proximity test.
2959 //
2960 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
2961 // Either one is sufficient to uniquely identify a thread.
2962 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
2963 //
2964 // * Intrinsify notify() and notifyAll() for the common cases where the
2965 // object is locked by the calling thread but the waitlist is empty.
2966 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
2967 //
2968 // * use jccb and jmpb instead of jcc and jmp to improve code density.
2969 // But beware of excessive branch density on AMD Opterons.
2970 //
2971 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
2972 // or failure of the fast-path. If the fast-path fails then we pass
2973 // control to the slow-path, typically in C. In Fast_Lock and
2974 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
2975 // will emit a conditional branch immediately after the node.
2976 // So we have branches to branches and lots of ICC.ZF games.
2977 // Instead, it might be better to have C2 pass a "FailureLabel"
2978 // into Fast_Lock and Fast_Unlock. In the case of success, control
2979 // will drop through the node. ICC.ZF is undefined at exit.
2980 // In the case of failure, the node will branch directly to the
2981 // FailureLabel
2984 // obj: object to lock
2985 // box: on-stack box address (displaced header location) - KILLED
2986 // rax,: tmp -- KILLED
2987 // scr: tmp -- KILLED
2988 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
2990 Register objReg = as_Register($obj$$reg);
2991 Register boxReg = as_Register($box$$reg);
2992 Register tmpReg = as_Register($tmp$$reg);
2993 Register scrReg = as_Register($scr$$reg);
2995 // Ensure the register assignents are disjoint
2996 guarantee (objReg != boxReg, "") ;
2997 guarantee (objReg != tmpReg, "") ;
2998 guarantee (objReg != scrReg, "") ;
2999 guarantee (boxReg != tmpReg, "") ;
3000 guarantee (boxReg != scrReg, "") ;
3001 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3003 MacroAssembler masm(&cbuf);
3005 if (_counters != NULL) {
3006 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3007 }
3008 if (EmitSync & 1) {
3009 // set box->dhw = unused_mark (3)
3010 // Force all sync thru slow-path: slow_enter() and slow_exit()
3011 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3012 masm.cmpptr (rsp, (int32_t)0) ;
3013 } else
3014 if (EmitSync & 2) {
3015 Label DONE_LABEL ;
3016 if (UseBiasedLocking) {
3017 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3018 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3019 }
3021 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3022 masm.orptr (tmpReg, 0x1);
3023 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3024 if (os::is_MP()) { masm.lock(); }
3025 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3026 masm.jcc(Assembler::equal, DONE_LABEL);
3027 // Recursive locking
3028 masm.subptr(tmpReg, rsp);
3029 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3030 masm.movptr(Address(boxReg, 0), tmpReg);
3031 masm.bind(DONE_LABEL) ;
3032 } else {
3033 // Possible cases that we'll encounter in fast_lock
3034 // ------------------------------------------------
3035 // * Inflated
3036 // -- unlocked
3037 // -- Locked
3038 // = by self
3039 // = by other
3040 // * biased
3041 // -- by Self
3042 // -- by other
3043 // * neutral
3044 // * stack-locked
3045 // -- by self
3046 // = sp-proximity test hits
3047 // = sp-proximity test generates false-negative
3048 // -- by other
3049 //
3051 Label IsInflated, DONE_LABEL, PopDone ;
3053 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3054 // order to reduce the number of conditional branches in the most common cases.
3055 // Beware -- there's a subtle invariant that fetch of the markword
3056 // at [FETCH], below, will never observe a biased encoding (*101b).
3057 // If this invariant is not held we risk exclusion (safety) failure.
3058 if (UseBiasedLocking && !UseOptoBiasInlining) {
3059 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3060 }
3062 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3063 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3064 masm.jccb (Assembler::notZero, IsInflated) ;
3066 // Attempt stack-locking ...
3067 masm.orptr (tmpReg, 0x1);
3068 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3069 if (os::is_MP()) { masm.lock(); }
3070 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3071 if (_counters != NULL) {
3072 masm.cond_inc32(Assembler::equal,
3073 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3074 }
3075 masm.jccb (Assembler::equal, DONE_LABEL);
3077 // Recursive locking
3078 masm.subptr(tmpReg, rsp);
3079 masm.andptr(tmpReg, 0xFFFFF003 );
3080 masm.movptr(Address(boxReg, 0), tmpReg);
3081 if (_counters != NULL) {
3082 masm.cond_inc32(Assembler::equal,
3083 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3084 }
3085 masm.jmp (DONE_LABEL) ;
3087 masm.bind (IsInflated) ;
3089 // The object is inflated.
3090 //
3091 // TODO-FIXME: eliminate the ugly use of manifest constants:
3092 // Use markOopDesc::monitor_value instead of "2".
3093 // use markOop::unused_mark() instead of "3".
3094 // The tmpReg value is an objectMonitor reference ORed with
3095 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3096 // objectmonitor pointer by masking off the "2" bit or we can just
3097 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3098 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3099 //
3100 // I use the latter as it avoids AGI stalls.
3101 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3102 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3103 //
3104 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3106 // boxReg refers to the on-stack BasicLock in the current frame.
3107 // We'd like to write:
3108 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3109 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3110 // additional latency as we have another ST in the store buffer that must drain.
3112 if (EmitSync & 8192) {
3113 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3114 masm.get_thread (scrReg) ;
3115 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3116 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3117 if (os::is_MP()) { masm.lock(); }
3118 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3119 } else
3120 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3121 masm.movptr(scrReg, boxReg) ;
3122 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3124 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3125 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3126 // prefetchw [eax + Offset(_owner)-2]
3127 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3128 }
3130 if ((EmitSync & 64) == 0) {
3131 // Optimistic form: consider XORL tmpReg,tmpReg
3132 masm.movptr(tmpReg, NULL_WORD) ;
3133 } else {
3134 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3135 // Test-And-CAS instead of CAS
3136 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3137 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3138 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3139 }
3141 // Appears unlocked - try to swing _owner from null to non-null.
3142 // Ideally, I'd manifest "Self" with get_thread and then attempt
3143 // to CAS the register containing Self into m->Owner.
3144 // But we don't have enough registers, so instead we can either try to CAS
3145 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3146 // we later store "Self" into m->Owner. Transiently storing a stack address
3147 // (rsp or the address of the box) into m->owner is harmless.
3148 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3149 if (os::is_MP()) { masm.lock(); }
3150 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3151 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3152 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3153 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3154 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3155 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3157 // If the CAS fails we can either retry or pass control to the slow-path.
3158 // We use the latter tactic.
3159 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3160 // If the CAS was successful ...
3161 // Self has acquired the lock
3162 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3163 // Intentional fall-through into DONE_LABEL ...
3164 } else {
3165 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3166 masm.movptr(boxReg, tmpReg) ;
3168 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3169 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3170 // prefetchw [eax + Offset(_owner)-2]
3171 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3172 }
3174 if ((EmitSync & 64) == 0) {
3175 // Optimistic form
3176 masm.xorptr (tmpReg, tmpReg) ;
3177 } else {
3178 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3179 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3180 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3181 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3182 }
3184 // Appears unlocked - try to swing _owner from null to non-null.
3185 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3186 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3187 masm.get_thread (scrReg) ;
3188 if (os::is_MP()) { masm.lock(); }
3189 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3191 // If the CAS fails we can either retry or pass control to the slow-path.
3192 // We use the latter tactic.
3193 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3194 // If the CAS was successful ...
3195 // Self has acquired the lock
3196 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3197 // Intentional fall-through into DONE_LABEL ...
3198 }
3200 // DONE_LABEL is a hot target - we'd really like to place it at the
3201 // start of cache line by padding with NOPs.
3202 // See the AMD and Intel software optimization manuals for the
3203 // most efficient "long" NOP encodings.
3204 // Unfortunately none of our alignment mechanisms suffice.
3205 masm.bind(DONE_LABEL);
3207 // Avoid branch-to-branch on AMD processors
3208 // This appears to be superstition.
3209 if (EmitSync & 32) masm.nop() ;
3212 // At DONE_LABEL the icc ZFlag is set as follows ...
3213 // Fast_Unlock uses the same protocol.
3214 // ZFlag == 1 -> Success
3215 // ZFlag == 0 -> Failure - force control through the slow-path
3216 }
3217 %}
3219 // obj: object to unlock
3220 // box: box address (displaced header location), killed. Must be EAX.
3221 // rbx,: killed tmp; cannot be obj nor box.
3222 //
3223 // Some commentary on balanced locking:
3224 //
3225 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3226 // Methods that don't have provably balanced locking are forced to run in the
3227 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3228 // The interpreter provides two properties:
3229 // I1: At return-time the interpreter automatically and quietly unlocks any
3230 // objects acquired the current activation (frame). Recall that the
3231 // interpreter maintains an on-stack list of locks currently held by
3232 // a frame.
3233 // I2: If a method attempts to unlock an object that is not held by the
3234 // the frame the interpreter throws IMSX.
3235 //
3236 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3237 // B() doesn't have provably balanced locking so it runs in the interpreter.
3238 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3239 // is still locked by A().
3240 //
3241 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3242 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3243 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3244 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3246 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3248 Register objReg = as_Register($obj$$reg);
3249 Register boxReg = as_Register($box$$reg);
3250 Register tmpReg = as_Register($tmp$$reg);
3252 guarantee (objReg != boxReg, "") ;
3253 guarantee (objReg != tmpReg, "") ;
3254 guarantee (boxReg != tmpReg, "") ;
3255 guarantee (boxReg == as_Register(EAX_enc), "") ;
3256 MacroAssembler masm(&cbuf);
3258 if (EmitSync & 4) {
3259 // Disable - inhibit all inlining. Force control through the slow-path
3260 masm.cmpptr (rsp, 0) ;
3261 } else
3262 if (EmitSync & 8) {
3263 Label DONE_LABEL ;
3264 if (UseBiasedLocking) {
3265 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3266 }
3267 // classic stack-locking code ...
3268 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3269 masm.testptr(tmpReg, tmpReg) ;
3270 masm.jcc (Assembler::zero, DONE_LABEL) ;
3271 if (os::is_MP()) { masm.lock(); }
3272 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3273 masm.bind(DONE_LABEL);
3274 } else {
3275 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3277 // Critically, the biased locking test must have precedence over
3278 // and appear before the (box->dhw == 0) recursive stack-lock test.
3279 if (UseBiasedLocking && !UseOptoBiasInlining) {
3280 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3281 }
3283 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3284 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3285 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3287 masm.testptr(tmpReg, 0x02) ; // Inflated?
3288 masm.jccb (Assembler::zero, Stacked) ;
3290 masm.bind (Inflated) ;
3291 // It's inflated.
3292 // Despite our balanced locking property we still check that m->_owner == Self
3293 // as java routines or native JNI code called by this thread might
3294 // have released the lock.
3295 // Refer to the comments in synchronizer.cpp for how we might encode extra
3296 // state in _succ so we can avoid fetching EntryList|cxq.
3297 //
3298 // I'd like to add more cases in fast_lock() and fast_unlock() --
3299 // such as recursive enter and exit -- but we have to be wary of
3300 // I$ bloat, T$ effects and BP$ effects.
3301 //
3302 // If there's no contention try a 1-0 exit. That is, exit without
3303 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3304 // we detect and recover from the race that the 1-0 exit admits.
3305 //
3306 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3307 // before it STs null into _owner, releasing the lock. Updates
3308 // to data protected by the critical section must be visible before
3309 // we drop the lock (and thus before any other thread could acquire
3310 // the lock and observe the fields protected by the lock).
3311 // IA32's memory-model is SPO, so STs are ordered with respect to
3312 // each other and there's no need for an explicit barrier (fence).
3313 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3315 masm.get_thread (boxReg) ;
3316 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3317 // prefetchw [ebx + Offset(_owner)-2]
3318 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3319 }
3321 // Note that we could employ various encoding schemes to reduce
3322 // the number of loads below (currently 4) to just 2 or 3.
3323 // Refer to the comments in synchronizer.cpp.
3324 // In practice the chain of fetches doesn't seem to impact performance, however.
3325 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3326 // Attempt to reduce branch density - AMD's branch predictor.
3327 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3328 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3329 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3330 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3331 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3332 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3333 masm.jmpb (DONE_LABEL) ;
3334 } else {
3335 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3336 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3337 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3338 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3339 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3340 masm.jccb (Assembler::notZero, CheckSucc) ;
3341 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3342 masm.jmpb (DONE_LABEL) ;
3343 }
3345 // The Following code fragment (EmitSync & 65536) improves the performance of
3346 // contended applications and contended synchronization microbenchmarks.
3347 // Unfortunately the emission of the code - even though not executed - causes regressions
3348 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3349 // with an equal number of never-executed NOPs results in the same regression.
3350 // We leave it off by default.
3352 if ((EmitSync & 65536) != 0) {
3353 Label LSuccess, LGoSlowPath ;
3355 masm.bind (CheckSucc) ;
3357 // Optional pre-test ... it's safe to elide this
3358 if ((EmitSync & 16) == 0) {
3359 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3360 masm.jccb (Assembler::zero, LGoSlowPath) ;
3361 }
3363 // We have a classic Dekker-style idiom:
3364 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3365 // There are a number of ways to implement the barrier:
3366 // (1) lock:andl &m->_owner, 0
3367 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3368 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3369 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3370 // (2) If supported, an explicit MFENCE is appealing.
3371 // In older IA32 processors MFENCE is slower than lock:add or xchg
3372 // particularly if the write-buffer is full as might be the case if
3373 // if stores closely precede the fence or fence-equivalent instruction.
3374 // In more modern implementations MFENCE appears faster, however.
3375 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3376 // The $lines underlying the top-of-stack should be in M-state.
3377 // The locked add instruction is serializing, of course.
3378 // (4) Use xchg, which is serializing
3379 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3380 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3381 // The integer condition codes will tell us if succ was 0.
3382 // Since _succ and _owner should reside in the same $line and
3383 // we just stored into _owner, it's likely that the $line
3384 // remains in M-state for the lock:orl.
3385 //
3386 // We currently use (3), although it's likely that switching to (2)
3387 // is correct for the future.
3389 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3390 if (os::is_MP()) {
3391 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3392 masm.mfence();
3393 } else {
3394 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3395 }
3396 }
3397 // Ratify _succ remains non-null
3398 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3399 masm.jccb (Assembler::notZero, LSuccess) ;
3401 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3402 if (os::is_MP()) { masm.lock(); }
3403 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3404 masm.jccb (Assembler::notEqual, LSuccess) ;
3405 // Since we're low on registers we installed rsp as a placeholding in _owner.
3406 // Now install Self over rsp. This is safe as we're transitioning from
3407 // non-null to non=null
3408 masm.get_thread (boxReg) ;
3409 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3410 // Intentional fall-through into LGoSlowPath ...
3412 masm.bind (LGoSlowPath) ;
3413 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3414 masm.jmpb (DONE_LABEL) ;
3416 masm.bind (LSuccess) ;
3417 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3418 masm.jmpb (DONE_LABEL) ;
3419 }
3421 masm.bind (Stacked) ;
3422 // It's not inflated and it's not recursively stack-locked and it's not biased.
3423 // It must be stack-locked.
3424 // Try to reset the header to displaced header.
3425 // The "box" value on the stack is stable, so we can reload
3426 // and be assured we observe the same value as above.
3427 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3428 if (os::is_MP()) { masm.lock(); }
3429 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3430 // Intention fall-thru into DONE_LABEL
3433 // DONE_LABEL is a hot target - we'd really like to place it at the
3434 // start of cache line by padding with NOPs.
3435 // See the AMD and Intel software optimization manuals for the
3436 // most efficient "long" NOP encodings.
3437 // Unfortunately none of our alignment mechanisms suffice.
3438 if ((EmitSync & 65536) == 0) {
3439 masm.bind (CheckSucc) ;
3440 }
3441 masm.bind(DONE_LABEL);
3443 // Avoid branch to branch on AMD processors
3444 if (EmitSync & 32768) { masm.nop() ; }
3445 }
3446 %}
3449 enc_class enc_pop_rdx() %{
3450 emit_opcode(cbuf,0x5A);
3451 %}
3453 enc_class enc_rethrow() %{
3454 cbuf.set_insts_mark();
3455 emit_opcode(cbuf, 0xE9); // jmp entry
3456 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3457 runtime_call_Relocation::spec(), RELOC_IMM32 );
3458 %}
3461 // Convert a double to an int. Java semantics require we do complex
3462 // manglelations in the corner cases. So we set the rounding mode to
3463 // 'zero', store the darned double down as an int, and reset the
3464 // rounding mode to 'nearest'. The hardware throws an exception which
3465 // patches up the correct value directly to the stack.
3466 enc_class DPR2I_encoding( regDPR src ) %{
3467 // Flip to round-to-zero mode. We attempted to allow invalid-op
3468 // exceptions here, so that a NAN or other corner-case value will
3469 // thrown an exception (but normal values get converted at full speed).
3470 // However, I2C adapters and other float-stack manglers leave pending
3471 // invalid-op exceptions hanging. We would have to clear them before
3472 // enabling them and that is more expensive than just testing for the
3473 // invalid value Intel stores down in the corner cases.
3474 emit_opcode(cbuf,0xD9); // FLDCW trunc
3475 emit_opcode(cbuf,0x2D);
3476 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3477 // Allocate a word
3478 emit_opcode(cbuf,0x83); // SUB ESP,4
3479 emit_opcode(cbuf,0xEC);
3480 emit_d8(cbuf,0x04);
3481 // Encoding assumes a double has been pushed into FPR0.
3482 // Store down the double as an int, popping the FPU stack
3483 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3484 emit_opcode(cbuf,0x1C);
3485 emit_d8(cbuf,0x24);
3486 // Restore the rounding mode; mask the exception
3487 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3488 emit_opcode(cbuf,0x2D);
3489 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3490 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3491 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3493 // Load the converted int; adjust CPU stack
3494 emit_opcode(cbuf,0x58); // POP EAX
3495 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3496 emit_d32 (cbuf,0x80000000); // 0x80000000
3497 emit_opcode(cbuf,0x75); // JNE around_slow_call
3498 emit_d8 (cbuf,0x07); // Size of slow_call
3499 // Push src onto stack slow-path
3500 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3501 emit_d8 (cbuf,0xC0-1+$src$$reg );
3502 // CALL directly to the runtime
3503 cbuf.set_insts_mark();
3504 emit_opcode(cbuf,0xE8); // Call into runtime
3505 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3506 // Carry on here...
3507 %}
3509 enc_class DPR2L_encoding( regDPR src ) %{
3510 emit_opcode(cbuf,0xD9); // FLDCW trunc
3511 emit_opcode(cbuf,0x2D);
3512 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3513 // Allocate a word
3514 emit_opcode(cbuf,0x83); // SUB ESP,8
3515 emit_opcode(cbuf,0xEC);
3516 emit_d8(cbuf,0x08);
3517 // Encoding assumes a double has been pushed into FPR0.
3518 // Store down the double as a long, popping the FPU stack
3519 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3520 emit_opcode(cbuf,0x3C);
3521 emit_d8(cbuf,0x24);
3522 // Restore the rounding mode; mask the exception
3523 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3524 emit_opcode(cbuf,0x2D);
3525 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3526 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3527 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3529 // Load the converted int; adjust CPU stack
3530 emit_opcode(cbuf,0x58); // POP EAX
3531 emit_opcode(cbuf,0x5A); // POP EDX
3532 emit_opcode(cbuf,0x81); // CMP EDX,imm
3533 emit_d8 (cbuf,0xFA); // rdx
3534 emit_d32 (cbuf,0x80000000); // 0x80000000
3535 emit_opcode(cbuf,0x75); // JNE around_slow_call
3536 emit_d8 (cbuf,0x07+4); // Size of slow_call
3537 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3538 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3539 emit_opcode(cbuf,0x75); // JNE around_slow_call
3540 emit_d8 (cbuf,0x07); // Size of slow_call
3541 // Push src onto stack slow-path
3542 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3543 emit_d8 (cbuf,0xC0-1+$src$$reg );
3544 // CALL directly to the runtime
3545 cbuf.set_insts_mark();
3546 emit_opcode(cbuf,0xE8); // Call into runtime
3547 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3548 // Carry on here...
3549 %}
3551 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3552 // Operand was loaded from memory into fp ST (stack top)
3553 // FMUL ST,$src /* D8 C8+i */
3554 emit_opcode(cbuf, 0xD8);
3555 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3556 %}
3558 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3559 // FADDP ST,src2 /* D8 C0+i */
3560 emit_opcode(cbuf, 0xD8);
3561 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3562 //could use FADDP src2,fpST /* DE C0+i */
3563 %}
3565 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3566 // FADDP src2,ST /* DE C0+i */
3567 emit_opcode(cbuf, 0xDE);
3568 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3569 %}
3571 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3572 // Operand has been loaded into fp ST (stack top)
3573 // FSUB ST,$src1
3574 emit_opcode(cbuf, 0xD8);
3575 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3577 // FDIV
3578 emit_opcode(cbuf, 0xD8);
3579 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3580 %}
3582 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3583 // Operand was loaded from memory into fp ST (stack top)
3584 // FADD ST,$src /* D8 C0+i */
3585 emit_opcode(cbuf, 0xD8);
3586 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3588 // FMUL ST,src2 /* D8 C*+i */
3589 emit_opcode(cbuf, 0xD8);
3590 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3591 %}
3594 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3595 // Operand was loaded from memory into fp ST (stack top)
3596 // FADD ST,$src /* D8 C0+i */
3597 emit_opcode(cbuf, 0xD8);
3598 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3600 // FMULP src2,ST /* DE C8+i */
3601 emit_opcode(cbuf, 0xDE);
3602 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3603 %}
3605 // Atomically load the volatile long
3606 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3607 emit_opcode(cbuf,0xDF);
3608 int rm_byte_opcode = 0x05;
3609 int base = $mem$$base;
3610 int index = $mem$$index;
3611 int scale = $mem$$scale;
3612 int displace = $mem$$disp;
3613 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3614 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3615 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3616 %}
3618 // Volatile Store Long. Must be atomic, so move it into
3619 // the FP TOS and then do a 64-bit FIST. Has to probe the
3620 // target address before the store (for null-ptr checks)
3621 // so the memory operand is used twice in the encoding.
3622 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3623 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3624 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3625 emit_opcode(cbuf,0xDF);
3626 int rm_byte_opcode = 0x07;
3627 int base = $mem$$base;
3628 int index = $mem$$index;
3629 int scale = $mem$$scale;
3630 int displace = $mem$$disp;
3631 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3632 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3633 %}
3635 // Safepoint Poll. This polls the safepoint page, and causes an
3636 // exception if it is not readable. Unfortunately, it kills the condition code
3637 // in the process
3638 // We current use TESTL [spp],EDI
3639 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3641 enc_class Safepoint_Poll() %{
3642 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3643 emit_opcode(cbuf,0x85);
3644 emit_rm (cbuf, 0x0, 0x7, 0x5);
3645 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3646 %}
3647 %}
3650 //----------FRAME--------------------------------------------------------------
3651 // Definition of frame structure and management information.
3652 //
3653 // S T A C K L A Y O U T Allocators stack-slot number
3654 // | (to get allocators register number
3655 // G Owned by | | v add OptoReg::stack0())
3656 // r CALLER | |
3657 // o | +--------+ pad to even-align allocators stack-slot
3658 // w V | pad0 | numbers; owned by CALLER
3659 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3660 // h ^ | in | 5
3661 // | | args | 4 Holes in incoming args owned by SELF
3662 // | | | | 3
3663 // | | +--------+
3664 // V | | old out| Empty on Intel, window on Sparc
3665 // | old |preserve| Must be even aligned.
3666 // | SP-+--------+----> Matcher::_old_SP, even aligned
3667 // | | in | 3 area for Intel ret address
3668 // Owned by |preserve| Empty on Sparc.
3669 // SELF +--------+
3670 // | | pad2 | 2 pad to align old SP
3671 // | +--------+ 1
3672 // | | locks | 0
3673 // | +--------+----> OptoReg::stack0(), even aligned
3674 // | | pad1 | 11 pad to align new SP
3675 // | +--------+
3676 // | | | 10
3677 // | | spills | 9 spills
3678 // V | | 8 (pad0 slot for callee)
3679 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3680 // ^ | out | 7
3681 // | | args | 6 Holes in outgoing args owned by CALLEE
3682 // Owned by +--------+
3683 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3684 // | new |preserve| Must be even-aligned.
3685 // | SP-+--------+----> Matcher::_new_SP, even aligned
3686 // | | |
3687 //
3688 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3689 // known from SELF's arguments and the Java calling convention.
3690 // Region 6-7 is determined per call site.
3691 // Note 2: If the calling convention leaves holes in the incoming argument
3692 // area, those holes are owned by SELF. Holes in the outgoing area
3693 // are owned by the CALLEE. Holes should not be nessecary in the
3694 // incoming area, as the Java calling convention is completely under
3695 // the control of the AD file. Doubles can be sorted and packed to
3696 // avoid holes. Holes in the outgoing arguments may be nessecary for
3697 // varargs C calling conventions.
3698 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3699 // even aligned with pad0 as needed.
3700 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3701 // region 6-11 is even aligned; it may be padded out more so that
3702 // the region from SP to FP meets the minimum stack alignment.
3704 frame %{
3705 // What direction does stack grow in (assumed to be same for C & Java)
3706 stack_direction(TOWARDS_LOW);
3708 // These three registers define part of the calling convention
3709 // between compiled code and the interpreter.
3710 inline_cache_reg(EAX); // Inline Cache Register
3711 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3713 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3714 cisc_spilling_operand_name(indOffset32);
3716 // Number of stack slots consumed by locking an object
3717 sync_stack_slots(1);
3719 // Compiled code's Frame Pointer
3720 frame_pointer(ESP);
3721 // Interpreter stores its frame pointer in a register which is
3722 // stored to the stack by I2CAdaptors.
3723 // I2CAdaptors convert from interpreted java to compiled java.
3724 interpreter_frame_pointer(EBP);
3726 // Stack alignment requirement
3727 // Alignment size in bytes (128-bit -> 16 bytes)
3728 stack_alignment(StackAlignmentInBytes);
3730 // Number of stack slots between incoming argument block and the start of
3731 // a new frame. The PROLOG must add this many slots to the stack. The
3732 // EPILOG must remove this many slots. Intel needs one slot for
3733 // return address and one for rbp, (must save rbp)
3734 in_preserve_stack_slots(2+VerifyStackAtCalls);
3736 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3737 // for calls to C. Supports the var-args backing area for register parms.
3738 varargs_C_out_slots_killed(0);
3740 // The after-PROLOG location of the return address. Location of
3741 // return address specifies a type (REG or STACK) and a number
3742 // representing the register number (i.e. - use a register name) or
3743 // stack slot.
3744 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3745 // Otherwise, it is above the locks and verification slot and alignment word
3746 return_addr(STACK - 1 +
3747 round_to((Compile::current()->in_preserve_stack_slots() +
3748 Compile::current()->fixed_slots()),
3749 stack_alignment_in_slots()));
3751 // Body of function which returns an integer array locating
3752 // arguments either in registers or in stack slots. Passed an array
3753 // of ideal registers called "sig" and a "length" count. Stack-slot
3754 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3755 // arguments for a CALLEE. Incoming stack arguments are
3756 // automatically biased by the preserve_stack_slots field above.
3757 calling_convention %{
3758 // No difference between ingoing/outgoing just pass false
3759 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3760 %}
3763 // Body of function which returns an integer array locating
3764 // arguments either in registers or in stack slots. Passed an array
3765 // of ideal registers called "sig" and a "length" count. Stack-slot
3766 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3767 // arguments for a CALLEE. Incoming stack arguments are
3768 // automatically biased by the preserve_stack_slots field above.
3769 c_calling_convention %{
3770 // This is obviously always outgoing
3771 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3772 %}
3774 // Location of C & interpreter return values
3775 c_return_value %{
3776 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3777 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3778 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3780 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3781 // that C functions return float and double results in XMM0.
3782 if( ideal_reg == Op_RegD && UseSSE>=2 )
3783 return OptoRegPair(XMM0b_num,XMM0_num);
3784 if( ideal_reg == Op_RegF && UseSSE>=2 )
3785 return OptoRegPair(OptoReg::Bad,XMM0_num);
3787 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3788 %}
3790 // Location of return values
3791 return_value %{
3792 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3793 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3794 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3795 if( ideal_reg == Op_RegD && UseSSE>=2 )
3796 return OptoRegPair(XMM0b_num,XMM0_num);
3797 if( ideal_reg == Op_RegF && UseSSE>=1 )
3798 return OptoRegPair(OptoReg::Bad,XMM0_num);
3799 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3800 %}
3802 %}
3804 //----------ATTRIBUTES---------------------------------------------------------
3805 //----------Operand Attributes-------------------------------------------------
3806 op_attrib op_cost(0); // Required cost attribute
3808 //----------Instruction Attributes---------------------------------------------
3809 ins_attrib ins_cost(100); // Required cost attribute
3810 ins_attrib ins_size(8); // Required size attribute (in bits)
3811 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3812 // non-matching short branch variant of some
3813 // long branch?
3814 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3815 // specifies the alignment that some part of the instruction (not
3816 // necessarily the start) requires. If > 1, a compute_padding()
3817 // function must be provided for the instruction
3819 //----------OPERANDS-----------------------------------------------------------
3820 // Operand definitions must precede instruction definitions for correct parsing
3821 // in the ADLC because operands constitute user defined types which are used in
3822 // instruction definitions.
3824 //----------Simple Operands----------------------------------------------------
3825 // Immediate Operands
3826 // Integer Immediate
3827 operand immI() %{
3828 match(ConI);
3830 op_cost(10);
3831 format %{ %}
3832 interface(CONST_INTER);
3833 %}
3835 // Constant for test vs zero
3836 operand immI0() %{
3837 predicate(n->get_int() == 0);
3838 match(ConI);
3840 op_cost(0);
3841 format %{ %}
3842 interface(CONST_INTER);
3843 %}
3845 // Constant for increment
3846 operand immI1() %{
3847 predicate(n->get_int() == 1);
3848 match(ConI);
3850 op_cost(0);
3851 format %{ %}
3852 interface(CONST_INTER);
3853 %}
3855 // Constant for decrement
3856 operand immI_M1() %{
3857 predicate(n->get_int() == -1);
3858 match(ConI);
3860 op_cost(0);
3861 format %{ %}
3862 interface(CONST_INTER);
3863 %}
3865 // Valid scale values for addressing modes
3866 operand immI2() %{
3867 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3868 match(ConI);
3870 format %{ %}
3871 interface(CONST_INTER);
3872 %}
3874 operand immI8() %{
3875 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3876 match(ConI);
3878 op_cost(5);
3879 format %{ %}
3880 interface(CONST_INTER);
3881 %}
3883 operand immI16() %{
3884 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3885 match(ConI);
3887 op_cost(10);
3888 format %{ %}
3889 interface(CONST_INTER);
3890 %}
3892 // Constant for long shifts
3893 operand immI_32() %{
3894 predicate( n->get_int() == 32 );
3895 match(ConI);
3897 op_cost(0);
3898 format %{ %}
3899 interface(CONST_INTER);
3900 %}
3902 operand immI_1_31() %{
3903 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3904 match(ConI);
3906 op_cost(0);
3907 format %{ %}
3908 interface(CONST_INTER);
3909 %}
3911 operand immI_32_63() %{
3912 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3913 match(ConI);
3914 op_cost(0);
3916 format %{ %}
3917 interface(CONST_INTER);
3918 %}
3920 operand immI_1() %{
3921 predicate( n->get_int() == 1 );
3922 match(ConI);
3924 op_cost(0);
3925 format %{ %}
3926 interface(CONST_INTER);
3927 %}
3929 operand immI_2() %{
3930 predicate( n->get_int() == 2 );
3931 match(ConI);
3933 op_cost(0);
3934 format %{ %}
3935 interface(CONST_INTER);
3936 %}
3938 operand immI_3() %{
3939 predicate( n->get_int() == 3 );
3940 match(ConI);
3942 op_cost(0);
3943 format %{ %}
3944 interface(CONST_INTER);
3945 %}
3947 // Pointer Immediate
3948 operand immP() %{
3949 match(ConP);
3951 op_cost(10);
3952 format %{ %}
3953 interface(CONST_INTER);
3954 %}
3956 // NULL Pointer Immediate
3957 operand immP0() %{
3958 predicate( n->get_ptr() == 0 );
3959 match(ConP);
3960 op_cost(0);
3962 format %{ %}
3963 interface(CONST_INTER);
3964 %}
3966 // Long Immediate
3967 operand immL() %{
3968 match(ConL);
3970 op_cost(20);
3971 format %{ %}
3972 interface(CONST_INTER);
3973 %}
3975 // Long Immediate zero
3976 operand immL0() %{
3977 predicate( n->get_long() == 0L );
3978 match(ConL);
3979 op_cost(0);
3981 format %{ %}
3982 interface(CONST_INTER);
3983 %}
3985 // Long Immediate zero
3986 operand immL_M1() %{
3987 predicate( n->get_long() == -1L );
3988 match(ConL);
3989 op_cost(0);
3991 format %{ %}
3992 interface(CONST_INTER);
3993 %}
3995 // Long immediate from 0 to 127.
3996 // Used for a shorter form of long mul by 10.
3997 operand immL_127() %{
3998 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
3999 match(ConL);
4000 op_cost(0);
4002 format %{ %}
4003 interface(CONST_INTER);
4004 %}
4006 // Long Immediate: low 32-bit mask
4007 operand immL_32bits() %{
4008 predicate(n->get_long() == 0xFFFFFFFFL);
4009 match(ConL);
4010 op_cost(0);
4012 format %{ %}
4013 interface(CONST_INTER);
4014 %}
4016 // Long Immediate: low 32-bit mask
4017 operand immL32() %{
4018 predicate(n->get_long() == (int)(n->get_long()));
4019 match(ConL);
4020 op_cost(20);
4022 format %{ %}
4023 interface(CONST_INTER);
4024 %}
4026 //Double Immediate zero
4027 operand immDPR0() %{
4028 // Do additional (and counter-intuitive) test against NaN to work around VC++
4029 // bug that generates code such that NaNs compare equal to 0.0
4030 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4031 match(ConD);
4033 op_cost(5);
4034 format %{ %}
4035 interface(CONST_INTER);
4036 %}
4038 // Double Immediate one
4039 operand immDPR1() %{
4040 predicate( UseSSE<=1 && n->getd() == 1.0 );
4041 match(ConD);
4043 op_cost(5);
4044 format %{ %}
4045 interface(CONST_INTER);
4046 %}
4048 // Double Immediate
4049 operand immDPR() %{
4050 predicate(UseSSE<=1);
4051 match(ConD);
4053 op_cost(5);
4054 format %{ %}
4055 interface(CONST_INTER);
4056 %}
4058 operand immD() %{
4059 predicate(UseSSE>=2);
4060 match(ConD);
4062 op_cost(5);
4063 format %{ %}
4064 interface(CONST_INTER);
4065 %}
4067 // Double Immediate zero
4068 operand immD0() %{
4069 // Do additional (and counter-intuitive) test against NaN to work around VC++
4070 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4071 // compare equal to -0.0.
4072 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4073 match(ConD);
4075 format %{ %}
4076 interface(CONST_INTER);
4077 %}
4079 // Float Immediate zero
4080 operand immFPR0() %{
4081 predicate(UseSSE == 0 && n->getf() == 0.0F);
4082 match(ConF);
4084 op_cost(5);
4085 format %{ %}
4086 interface(CONST_INTER);
4087 %}
4089 // Float Immediate one
4090 operand immFPR1() %{
4091 predicate(UseSSE == 0 && n->getf() == 1.0F);
4092 match(ConF);
4094 op_cost(5);
4095 format %{ %}
4096 interface(CONST_INTER);
4097 %}
4099 // Float Immediate
4100 operand immFPR() %{
4101 predicate( UseSSE == 0 );
4102 match(ConF);
4104 op_cost(5);
4105 format %{ %}
4106 interface(CONST_INTER);
4107 %}
4109 // Float Immediate
4110 operand immF() %{
4111 predicate(UseSSE >= 1);
4112 match(ConF);
4114 op_cost(5);
4115 format %{ %}
4116 interface(CONST_INTER);
4117 %}
4119 // Float Immediate zero. Zero and not -0.0
4120 operand immF0() %{
4121 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4122 match(ConF);
4124 op_cost(5);
4125 format %{ %}
4126 interface(CONST_INTER);
4127 %}
4129 // Immediates for special shifts (sign extend)
4131 // Constants for increment
4132 operand immI_16() %{
4133 predicate( n->get_int() == 16 );
4134 match(ConI);
4136 format %{ %}
4137 interface(CONST_INTER);
4138 %}
4140 operand immI_24() %{
4141 predicate( n->get_int() == 24 );
4142 match(ConI);
4144 format %{ %}
4145 interface(CONST_INTER);
4146 %}
4148 // Constant for byte-wide masking
4149 operand immI_255() %{
4150 predicate( n->get_int() == 255 );
4151 match(ConI);
4153 format %{ %}
4154 interface(CONST_INTER);
4155 %}
4157 // Constant for short-wide masking
4158 operand immI_65535() %{
4159 predicate(n->get_int() == 65535);
4160 match(ConI);
4162 format %{ %}
4163 interface(CONST_INTER);
4164 %}
4166 // Register Operands
4167 // Integer Register
4168 operand rRegI() %{
4169 constraint(ALLOC_IN_RC(int_reg));
4170 match(RegI);
4171 match(xRegI);
4172 match(eAXRegI);
4173 match(eBXRegI);
4174 match(eCXRegI);
4175 match(eDXRegI);
4176 match(eDIRegI);
4177 match(eSIRegI);
4179 format %{ %}
4180 interface(REG_INTER);
4181 %}
4183 // Subset of Integer Register
4184 operand xRegI(rRegI reg) %{
4185 constraint(ALLOC_IN_RC(int_x_reg));
4186 match(reg);
4187 match(eAXRegI);
4188 match(eBXRegI);
4189 match(eCXRegI);
4190 match(eDXRegI);
4192 format %{ %}
4193 interface(REG_INTER);
4194 %}
4196 // Special Registers
4197 operand eAXRegI(xRegI reg) %{
4198 constraint(ALLOC_IN_RC(eax_reg));
4199 match(reg);
4200 match(rRegI);
4202 format %{ "EAX" %}
4203 interface(REG_INTER);
4204 %}
4206 // Special Registers
4207 operand eBXRegI(xRegI reg) %{
4208 constraint(ALLOC_IN_RC(ebx_reg));
4209 match(reg);
4210 match(rRegI);
4212 format %{ "EBX" %}
4213 interface(REG_INTER);
4214 %}
4216 operand eCXRegI(xRegI reg) %{
4217 constraint(ALLOC_IN_RC(ecx_reg));
4218 match(reg);
4219 match(rRegI);
4221 format %{ "ECX" %}
4222 interface(REG_INTER);
4223 %}
4225 operand eDXRegI(xRegI reg) %{
4226 constraint(ALLOC_IN_RC(edx_reg));
4227 match(reg);
4228 match(rRegI);
4230 format %{ "EDX" %}
4231 interface(REG_INTER);
4232 %}
4234 operand eDIRegI(xRegI reg) %{
4235 constraint(ALLOC_IN_RC(edi_reg));
4236 match(reg);
4237 match(rRegI);
4239 format %{ "EDI" %}
4240 interface(REG_INTER);
4241 %}
4243 operand naxRegI() %{
4244 constraint(ALLOC_IN_RC(nax_reg));
4245 match(RegI);
4246 match(eCXRegI);
4247 match(eDXRegI);
4248 match(eSIRegI);
4249 match(eDIRegI);
4251 format %{ %}
4252 interface(REG_INTER);
4253 %}
4255 operand nadxRegI() %{
4256 constraint(ALLOC_IN_RC(nadx_reg));
4257 match(RegI);
4258 match(eBXRegI);
4259 match(eCXRegI);
4260 match(eSIRegI);
4261 match(eDIRegI);
4263 format %{ %}
4264 interface(REG_INTER);
4265 %}
4267 operand ncxRegI() %{
4268 constraint(ALLOC_IN_RC(ncx_reg));
4269 match(RegI);
4270 match(eAXRegI);
4271 match(eDXRegI);
4272 match(eSIRegI);
4273 match(eDIRegI);
4275 format %{ %}
4276 interface(REG_INTER);
4277 %}
4279 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4280 // //
4281 operand eSIRegI(xRegI reg) %{
4282 constraint(ALLOC_IN_RC(esi_reg));
4283 match(reg);
4284 match(rRegI);
4286 format %{ "ESI" %}
4287 interface(REG_INTER);
4288 %}
4290 // Pointer Register
4291 operand anyRegP() %{
4292 constraint(ALLOC_IN_RC(any_reg));
4293 match(RegP);
4294 match(eAXRegP);
4295 match(eBXRegP);
4296 match(eCXRegP);
4297 match(eDIRegP);
4298 match(eRegP);
4300 format %{ %}
4301 interface(REG_INTER);
4302 %}
4304 operand eRegP() %{
4305 constraint(ALLOC_IN_RC(int_reg));
4306 match(RegP);
4307 match(eAXRegP);
4308 match(eBXRegP);
4309 match(eCXRegP);
4310 match(eDIRegP);
4312 format %{ %}
4313 interface(REG_INTER);
4314 %}
4316 // On windows95, EBP is not safe to use for implicit null tests.
4317 operand eRegP_no_EBP() %{
4318 constraint(ALLOC_IN_RC(int_reg_no_rbp));
4319 match(RegP);
4320 match(eAXRegP);
4321 match(eBXRegP);
4322 match(eCXRegP);
4323 match(eDIRegP);
4325 op_cost(100);
4326 format %{ %}
4327 interface(REG_INTER);
4328 %}
4330 operand naxRegP() %{
4331 constraint(ALLOC_IN_RC(nax_reg));
4332 match(RegP);
4333 match(eBXRegP);
4334 match(eDXRegP);
4335 match(eCXRegP);
4336 match(eSIRegP);
4337 match(eDIRegP);
4339 format %{ %}
4340 interface(REG_INTER);
4341 %}
4343 operand nabxRegP() %{
4344 constraint(ALLOC_IN_RC(nabx_reg));
4345 match(RegP);
4346 match(eCXRegP);
4347 match(eDXRegP);
4348 match(eSIRegP);
4349 match(eDIRegP);
4351 format %{ %}
4352 interface(REG_INTER);
4353 %}
4355 operand pRegP() %{
4356 constraint(ALLOC_IN_RC(p_reg));
4357 match(RegP);
4358 match(eBXRegP);
4359 match(eDXRegP);
4360 match(eSIRegP);
4361 match(eDIRegP);
4363 format %{ %}
4364 interface(REG_INTER);
4365 %}
4367 // Special Registers
4368 // Return a pointer value
4369 operand eAXRegP(eRegP reg) %{
4370 constraint(ALLOC_IN_RC(eax_reg));
4371 match(reg);
4372 format %{ "EAX" %}
4373 interface(REG_INTER);
4374 %}
4376 // Used in AtomicAdd
4377 operand eBXRegP(eRegP reg) %{
4378 constraint(ALLOC_IN_RC(ebx_reg));
4379 match(reg);
4380 format %{ "EBX" %}
4381 interface(REG_INTER);
4382 %}
4384 // Tail-call (interprocedural jump) to interpreter
4385 operand eCXRegP(eRegP reg) %{
4386 constraint(ALLOC_IN_RC(ecx_reg));
4387 match(reg);
4388 format %{ "ECX" %}
4389 interface(REG_INTER);
4390 %}
4392 operand eSIRegP(eRegP reg) %{
4393 constraint(ALLOC_IN_RC(esi_reg));
4394 match(reg);
4395 format %{ "ESI" %}
4396 interface(REG_INTER);
4397 %}
4399 // Used in rep stosw
4400 operand eDIRegP(eRegP reg) %{
4401 constraint(ALLOC_IN_RC(edi_reg));
4402 match(reg);
4403 format %{ "EDI" %}
4404 interface(REG_INTER);
4405 %}
4407 operand eBPRegP() %{
4408 constraint(ALLOC_IN_RC(ebp_reg));
4409 match(RegP);
4410 format %{ "EBP" %}
4411 interface(REG_INTER);
4412 %}
4414 operand eRegL() %{
4415 constraint(ALLOC_IN_RC(long_reg));
4416 match(RegL);
4417 match(eADXRegL);
4419 format %{ %}
4420 interface(REG_INTER);
4421 %}
4423 operand eADXRegL( eRegL reg ) %{
4424 constraint(ALLOC_IN_RC(eadx_reg));
4425 match(reg);
4427 format %{ "EDX:EAX" %}
4428 interface(REG_INTER);
4429 %}
4431 operand eBCXRegL( eRegL reg ) %{
4432 constraint(ALLOC_IN_RC(ebcx_reg));
4433 match(reg);
4435 format %{ "EBX:ECX" %}
4436 interface(REG_INTER);
4437 %}
4439 // Special case for integer high multiply
4440 operand eADXRegL_low_only() %{
4441 constraint(ALLOC_IN_RC(eadx_reg));
4442 match(RegL);
4444 format %{ "EAX" %}
4445 interface(REG_INTER);
4446 %}
4448 // Flags register, used as output of compare instructions
4449 operand eFlagsReg() %{
4450 constraint(ALLOC_IN_RC(int_flags));
4451 match(RegFlags);
4453 format %{ "EFLAGS" %}
4454 interface(REG_INTER);
4455 %}
4457 // Flags register, used as output of FLOATING POINT compare instructions
4458 operand eFlagsRegU() %{
4459 constraint(ALLOC_IN_RC(int_flags));
4460 match(RegFlags);
4462 format %{ "EFLAGS_U" %}
4463 interface(REG_INTER);
4464 %}
4466 operand eFlagsRegUCF() %{
4467 constraint(ALLOC_IN_RC(int_flags));
4468 match(RegFlags);
4469 predicate(false);
4471 format %{ "EFLAGS_U_CF" %}
4472 interface(REG_INTER);
4473 %}
4475 // Condition Code Register used by long compare
4476 operand flagsReg_long_LTGE() %{
4477 constraint(ALLOC_IN_RC(int_flags));
4478 match(RegFlags);
4479 format %{ "FLAGS_LTGE" %}
4480 interface(REG_INTER);
4481 %}
4482 operand flagsReg_long_EQNE() %{
4483 constraint(ALLOC_IN_RC(int_flags));
4484 match(RegFlags);
4485 format %{ "FLAGS_EQNE" %}
4486 interface(REG_INTER);
4487 %}
4488 operand flagsReg_long_LEGT() %{
4489 constraint(ALLOC_IN_RC(int_flags));
4490 match(RegFlags);
4491 format %{ "FLAGS_LEGT" %}
4492 interface(REG_INTER);
4493 %}
4495 // Float register operands
4496 operand regDPR() %{
4497 predicate( UseSSE < 2 );
4498 constraint(ALLOC_IN_RC(fp_dbl_reg));
4499 match(RegD);
4500 match(regDPR1);
4501 match(regDPR2);
4502 format %{ %}
4503 interface(REG_INTER);
4504 %}
4506 operand regDPR1(regDPR reg) %{
4507 predicate( UseSSE < 2 );
4508 constraint(ALLOC_IN_RC(fp_dbl_reg0));
4509 match(reg);
4510 format %{ "FPR1" %}
4511 interface(REG_INTER);
4512 %}
4514 operand regDPR2(regDPR reg) %{
4515 predicate( UseSSE < 2 );
4516 constraint(ALLOC_IN_RC(fp_dbl_reg1));
4517 match(reg);
4518 format %{ "FPR2" %}
4519 interface(REG_INTER);
4520 %}
4522 operand regnotDPR1(regDPR reg) %{
4523 predicate( UseSSE < 2 );
4524 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
4525 match(reg);
4526 format %{ %}
4527 interface(REG_INTER);
4528 %}
4530 // Float register operands
4531 operand regFPR() %{
4532 predicate( UseSSE < 2 );
4533 constraint(ALLOC_IN_RC(fp_flt_reg));
4534 match(RegF);
4535 match(regFPR1);
4536 format %{ %}
4537 interface(REG_INTER);
4538 %}
4540 // Float register operands
4541 operand regFPR1(regFPR reg) %{
4542 predicate( UseSSE < 2 );
4543 constraint(ALLOC_IN_RC(fp_flt_reg0));
4544 match(reg);
4545 format %{ "FPR1" %}
4546 interface(REG_INTER);
4547 %}
4549 // XMM Float register operands
4550 operand regF() %{
4551 predicate( UseSSE>=1 );
4552 constraint(ALLOC_IN_RC(float_reg));
4553 match(RegF);
4554 format %{ %}
4555 interface(REG_INTER);
4556 %}
4558 // XMM Double register operands
4559 operand regD() %{
4560 predicate( UseSSE>=2 );
4561 constraint(ALLOC_IN_RC(double_reg));
4562 match(RegD);
4563 format %{ %}
4564 interface(REG_INTER);
4565 %}
4568 //----------Memory Operands----------------------------------------------------
4569 // Direct Memory Operand
4570 operand direct(immP addr) %{
4571 match(addr);
4573 format %{ "[$addr]" %}
4574 interface(MEMORY_INTER) %{
4575 base(0xFFFFFFFF);
4576 index(0x4);
4577 scale(0x0);
4578 disp($addr);
4579 %}
4580 %}
4582 // Indirect Memory Operand
4583 operand indirect(eRegP reg) %{
4584 constraint(ALLOC_IN_RC(int_reg));
4585 match(reg);
4587 format %{ "[$reg]" %}
4588 interface(MEMORY_INTER) %{
4589 base($reg);
4590 index(0x4);
4591 scale(0x0);
4592 disp(0x0);
4593 %}
4594 %}
4596 // Indirect Memory Plus Short Offset Operand
4597 operand indOffset8(eRegP reg, immI8 off) %{
4598 match(AddP reg off);
4600 format %{ "[$reg + $off]" %}
4601 interface(MEMORY_INTER) %{
4602 base($reg);
4603 index(0x4);
4604 scale(0x0);
4605 disp($off);
4606 %}
4607 %}
4609 // Indirect Memory Plus Long Offset Operand
4610 operand indOffset32(eRegP reg, immI off) %{
4611 match(AddP reg off);
4613 format %{ "[$reg + $off]" %}
4614 interface(MEMORY_INTER) %{
4615 base($reg);
4616 index(0x4);
4617 scale(0x0);
4618 disp($off);
4619 %}
4620 %}
4622 // Indirect Memory Plus Long Offset Operand
4623 operand indOffset32X(rRegI reg, immP off) %{
4624 match(AddP off reg);
4626 format %{ "[$reg + $off]" %}
4627 interface(MEMORY_INTER) %{
4628 base($reg);
4629 index(0x4);
4630 scale(0x0);
4631 disp($off);
4632 %}
4633 %}
4635 // Indirect Memory Plus Index Register Plus Offset Operand
4636 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4637 match(AddP (AddP reg ireg) off);
4639 op_cost(10);
4640 format %{"[$reg + $off + $ireg]" %}
4641 interface(MEMORY_INTER) %{
4642 base($reg);
4643 index($ireg);
4644 scale(0x0);
4645 disp($off);
4646 %}
4647 %}
4649 // Indirect Memory Plus Index Register Plus Offset Operand
4650 operand indIndex(eRegP reg, rRegI ireg) %{
4651 match(AddP reg ireg);
4653 op_cost(10);
4654 format %{"[$reg + $ireg]" %}
4655 interface(MEMORY_INTER) %{
4656 base($reg);
4657 index($ireg);
4658 scale(0x0);
4659 disp(0x0);
4660 %}
4661 %}
4663 // // -------------------------------------------------------------------------
4664 // // 486 architecture doesn't support "scale * index + offset" with out a base
4665 // // -------------------------------------------------------------------------
4666 // // Scaled Memory Operands
4667 // // Indirect Memory Times Scale Plus Offset Operand
4668 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4669 // match(AddP off (LShiftI ireg scale));
4670 //
4671 // op_cost(10);
4672 // format %{"[$off + $ireg << $scale]" %}
4673 // interface(MEMORY_INTER) %{
4674 // base(0x4);
4675 // index($ireg);
4676 // scale($scale);
4677 // disp($off);
4678 // %}
4679 // %}
4681 // Indirect Memory Times Scale Plus Index Register
4682 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4683 match(AddP reg (LShiftI ireg scale));
4685 op_cost(10);
4686 format %{"[$reg + $ireg << $scale]" %}
4687 interface(MEMORY_INTER) %{
4688 base($reg);
4689 index($ireg);
4690 scale($scale);
4691 disp(0x0);
4692 %}
4693 %}
4695 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4696 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4697 match(AddP (AddP reg (LShiftI ireg scale)) off);
4699 op_cost(10);
4700 format %{"[$reg + $off + $ireg << $scale]" %}
4701 interface(MEMORY_INTER) %{
4702 base($reg);
4703 index($ireg);
4704 scale($scale);
4705 disp($off);
4706 %}
4707 %}
4709 //----------Load Long Memory Operands------------------------------------------
4710 // The load-long idiom will use it's address expression again after loading
4711 // the first word of the long. If the load-long destination overlaps with
4712 // registers used in the addressing expression, the 2nd half will be loaded
4713 // from a clobbered address. Fix this by requiring that load-long use
4714 // address registers that do not overlap with the load-long target.
4716 // load-long support
4717 operand load_long_RegP() %{
4718 constraint(ALLOC_IN_RC(esi_reg));
4719 match(RegP);
4720 match(eSIRegP);
4721 op_cost(100);
4722 format %{ %}
4723 interface(REG_INTER);
4724 %}
4726 // Indirect Memory Operand Long
4727 operand load_long_indirect(load_long_RegP reg) %{
4728 constraint(ALLOC_IN_RC(esi_reg));
4729 match(reg);
4731 format %{ "[$reg]" %}
4732 interface(MEMORY_INTER) %{
4733 base($reg);
4734 index(0x4);
4735 scale(0x0);
4736 disp(0x0);
4737 %}
4738 %}
4740 // Indirect Memory Plus Long Offset Operand
4741 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4742 match(AddP reg off);
4744 format %{ "[$reg + $off]" %}
4745 interface(MEMORY_INTER) %{
4746 base($reg);
4747 index(0x4);
4748 scale(0x0);
4749 disp($off);
4750 %}
4751 %}
4753 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4756 //----------Special Memory Operands--------------------------------------------
4757 // Stack Slot Operand - This operand is used for loading and storing temporary
4758 // values on the stack where a match requires a value to
4759 // flow through memory.
4760 operand stackSlotP(sRegP reg) %{
4761 constraint(ALLOC_IN_RC(stack_slots));
4762 // No match rule because this operand is only generated in matching
4763 format %{ "[$reg]" %}
4764 interface(MEMORY_INTER) %{
4765 base(0x4); // ESP
4766 index(0x4); // No Index
4767 scale(0x0); // No Scale
4768 disp($reg); // Stack Offset
4769 %}
4770 %}
4772 operand stackSlotI(sRegI reg) %{
4773 constraint(ALLOC_IN_RC(stack_slots));
4774 // No match rule because this operand is only generated in matching
4775 format %{ "[$reg]" %}
4776 interface(MEMORY_INTER) %{
4777 base(0x4); // ESP
4778 index(0x4); // No Index
4779 scale(0x0); // No Scale
4780 disp($reg); // Stack Offset
4781 %}
4782 %}
4784 operand stackSlotF(sRegF reg) %{
4785 constraint(ALLOC_IN_RC(stack_slots));
4786 // No match rule because this operand is only generated in matching
4787 format %{ "[$reg]" %}
4788 interface(MEMORY_INTER) %{
4789 base(0x4); // ESP
4790 index(0x4); // No Index
4791 scale(0x0); // No Scale
4792 disp($reg); // Stack Offset
4793 %}
4794 %}
4796 operand stackSlotD(sRegD reg) %{
4797 constraint(ALLOC_IN_RC(stack_slots));
4798 // No match rule because this operand is only generated in matching
4799 format %{ "[$reg]" %}
4800 interface(MEMORY_INTER) %{
4801 base(0x4); // ESP
4802 index(0x4); // No Index
4803 scale(0x0); // No Scale
4804 disp($reg); // Stack Offset
4805 %}
4806 %}
4808 operand stackSlotL(sRegL reg) %{
4809 constraint(ALLOC_IN_RC(stack_slots));
4810 // No match rule because this operand is only generated in matching
4811 format %{ "[$reg]" %}
4812 interface(MEMORY_INTER) %{
4813 base(0x4); // ESP
4814 index(0x4); // No Index
4815 scale(0x0); // No Scale
4816 disp($reg); // Stack Offset
4817 %}
4818 %}
4820 //----------Memory Operands - Win95 Implicit Null Variants----------------
4821 // Indirect Memory Operand
4822 operand indirect_win95_safe(eRegP_no_EBP reg)
4823 %{
4824 constraint(ALLOC_IN_RC(int_reg));
4825 match(reg);
4827 op_cost(100);
4828 format %{ "[$reg]" %}
4829 interface(MEMORY_INTER) %{
4830 base($reg);
4831 index(0x4);
4832 scale(0x0);
4833 disp(0x0);
4834 %}
4835 %}
4837 // Indirect Memory Plus Short Offset Operand
4838 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4839 %{
4840 match(AddP reg off);
4842 op_cost(100);
4843 format %{ "[$reg + $off]" %}
4844 interface(MEMORY_INTER) %{
4845 base($reg);
4846 index(0x4);
4847 scale(0x0);
4848 disp($off);
4849 %}
4850 %}
4852 // Indirect Memory Plus Long Offset Operand
4853 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4854 %{
4855 match(AddP reg off);
4857 op_cost(100);
4858 format %{ "[$reg + $off]" %}
4859 interface(MEMORY_INTER) %{
4860 base($reg);
4861 index(0x4);
4862 scale(0x0);
4863 disp($off);
4864 %}
4865 %}
4867 // Indirect Memory Plus Index Register Plus Offset Operand
4868 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4869 %{
4870 match(AddP (AddP reg ireg) off);
4872 op_cost(100);
4873 format %{"[$reg + $off + $ireg]" %}
4874 interface(MEMORY_INTER) %{
4875 base($reg);
4876 index($ireg);
4877 scale(0x0);
4878 disp($off);
4879 %}
4880 %}
4882 // Indirect Memory Times Scale Plus Index Register
4883 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4884 %{
4885 match(AddP reg (LShiftI ireg scale));
4887 op_cost(100);
4888 format %{"[$reg + $ireg << $scale]" %}
4889 interface(MEMORY_INTER) %{
4890 base($reg);
4891 index($ireg);
4892 scale($scale);
4893 disp(0x0);
4894 %}
4895 %}
4897 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4898 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4899 %{
4900 match(AddP (AddP reg (LShiftI ireg scale)) off);
4902 op_cost(100);
4903 format %{"[$reg + $off + $ireg << $scale]" %}
4904 interface(MEMORY_INTER) %{
4905 base($reg);
4906 index($ireg);
4907 scale($scale);
4908 disp($off);
4909 %}
4910 %}
4912 //----------Conditional Branch Operands----------------------------------------
4913 // Comparison Op - This is the operation of the comparison, and is limited to
4914 // the following set of codes:
4915 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4916 //
4917 // Other attributes of the comparison, such as unsignedness, are specified
4918 // by the comparison instruction that sets a condition code flags register.
4919 // That result is represented by a flags operand whose subtype is appropriate
4920 // to the unsignedness (etc.) of the comparison.
4921 //
4922 // Later, the instruction which matches both the Comparison Op (a Bool) and
4923 // the flags (produced by the Cmp) specifies the coding of the comparison op
4924 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4926 // Comparision Code
4927 operand cmpOp() %{
4928 match(Bool);
4930 format %{ "" %}
4931 interface(COND_INTER) %{
4932 equal(0x4, "e");
4933 not_equal(0x5, "ne");
4934 less(0xC, "l");
4935 greater_equal(0xD, "ge");
4936 less_equal(0xE, "le");
4937 greater(0xF, "g");
4938 overflow(0x0, "o");
4939 no_overflow(0x1, "no");
4940 %}
4941 %}
4943 // Comparison Code, unsigned compare. Used by FP also, with
4944 // C2 (unordered) turned into GT or LT already. The other bits
4945 // C0 and C3 are turned into Carry & Zero flags.
4946 operand cmpOpU() %{
4947 match(Bool);
4949 format %{ "" %}
4950 interface(COND_INTER) %{
4951 equal(0x4, "e");
4952 not_equal(0x5, "ne");
4953 less(0x2, "b");
4954 greater_equal(0x3, "nb");
4955 less_equal(0x6, "be");
4956 greater(0x7, "nbe");
4957 overflow(0x0, "o");
4958 no_overflow(0x1, "no");
4959 %}
4960 %}
4962 // Floating comparisons that don't require any fixup for the unordered case
4963 operand cmpOpUCF() %{
4964 match(Bool);
4965 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4966 n->as_Bool()->_test._test == BoolTest::ge ||
4967 n->as_Bool()->_test._test == BoolTest::le ||
4968 n->as_Bool()->_test._test == BoolTest::gt);
4969 format %{ "" %}
4970 interface(COND_INTER) %{
4971 equal(0x4, "e");
4972 not_equal(0x5, "ne");
4973 less(0x2, "b");
4974 greater_equal(0x3, "nb");
4975 less_equal(0x6, "be");
4976 greater(0x7, "nbe");
4977 overflow(0x0, "o");
4978 no_overflow(0x1, "no");
4979 %}
4980 %}
4983 // Floating comparisons that can be fixed up with extra conditional jumps
4984 operand cmpOpUCF2() %{
4985 match(Bool);
4986 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4987 n->as_Bool()->_test._test == BoolTest::eq);
4988 format %{ "" %}
4989 interface(COND_INTER) %{
4990 equal(0x4, "e");
4991 not_equal(0x5, "ne");
4992 less(0x2, "b");
4993 greater_equal(0x3, "nb");
4994 less_equal(0x6, "be");
4995 greater(0x7, "nbe");
4996 overflow(0x0, "o");
4997 no_overflow(0x1, "no");
4998 %}
4999 %}
5001 // Comparison Code for FP conditional move
5002 operand cmpOp_fcmov() %{
5003 match(Bool);
5005 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
5006 n->as_Bool()->_test._test != BoolTest::no_overflow);
5007 format %{ "" %}
5008 interface(COND_INTER) %{
5009 equal (0x0C8);
5010 not_equal (0x1C8);
5011 less (0x0C0);
5012 greater_equal(0x1C0);
5013 less_equal (0x0D0);
5014 greater (0x1D0);
5015 overflow(0x0, "o"); // not really supported by the instruction
5016 no_overflow(0x1, "no"); // not really supported by the instruction
5017 %}
5018 %}
5020 // Comparision Code used in long compares
5021 operand cmpOp_commute() %{
5022 match(Bool);
5024 format %{ "" %}
5025 interface(COND_INTER) %{
5026 equal(0x4, "e");
5027 not_equal(0x5, "ne");
5028 less(0xF, "g");
5029 greater_equal(0xE, "le");
5030 less_equal(0xD, "ge");
5031 greater(0xC, "l");
5032 overflow(0x0, "o");
5033 no_overflow(0x1, "no");
5034 %}
5035 %}
5037 //----------OPERAND CLASSES----------------------------------------------------
5038 // Operand Classes are groups of operands that are used as to simplify
5039 // instruction definitions by not requiring the AD writer to specify separate
5040 // instructions for every form of operand when the instruction accepts
5041 // multiple operand types with the same basic encoding and format. The classic
5042 // case of this is memory operands.
5044 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5045 indIndex, indIndexScale, indIndexScaleOffset);
5047 // Long memory operations are encoded in 2 instructions and a +4 offset.
5048 // This means some kind of offset is always required and you cannot use
5049 // an oop as the offset (done when working on static globals).
5050 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5051 indIndex, indIndexScale, indIndexScaleOffset);
5054 //----------PIPELINE-----------------------------------------------------------
5055 // Rules which define the behavior of the target architectures pipeline.
5056 pipeline %{
5058 //----------ATTRIBUTES---------------------------------------------------------
5059 attributes %{
5060 variable_size_instructions; // Fixed size instructions
5061 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5062 instruction_unit_size = 1; // An instruction is 1 bytes long
5063 instruction_fetch_unit_size = 16; // The processor fetches one line
5064 instruction_fetch_units = 1; // of 16 bytes
5066 // List of nop instructions
5067 nops( MachNop );
5068 %}
5070 //----------RESOURCES----------------------------------------------------------
5071 // Resources are the functional units available to the machine
5073 // Generic P2/P3 pipeline
5074 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5075 // 3 instructions decoded per cycle.
5076 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5077 // 2 ALU op, only ALU0 handles mul/div instructions.
5078 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5079 MS0, MS1, MEM = MS0 | MS1,
5080 BR, FPU,
5081 ALU0, ALU1, ALU = ALU0 | ALU1 );
5083 //----------PIPELINE DESCRIPTION-----------------------------------------------
5084 // Pipeline Description specifies the stages in the machine's pipeline
5086 // Generic P2/P3 pipeline
5087 pipe_desc(S0, S1, S2, S3, S4, S5);
5089 //----------PIPELINE CLASSES---------------------------------------------------
5090 // Pipeline Classes describe the stages in which input and output are
5091 // referenced by the hardware pipeline.
5093 // Naming convention: ialu or fpu
5094 // Then: _reg
5095 // Then: _reg if there is a 2nd register
5096 // Then: _long if it's a pair of instructions implementing a long
5097 // Then: _fat if it requires the big decoder
5098 // Or: _mem if it requires the big decoder and a memory unit.
5100 // Integer ALU reg operation
5101 pipe_class ialu_reg(rRegI dst) %{
5102 single_instruction;
5103 dst : S4(write);
5104 dst : S3(read);
5105 DECODE : S0; // any decoder
5106 ALU : S3; // any alu
5107 %}
5109 // Long ALU reg operation
5110 pipe_class ialu_reg_long(eRegL dst) %{
5111 instruction_count(2);
5112 dst : S4(write);
5113 dst : S3(read);
5114 DECODE : S0(2); // any 2 decoders
5115 ALU : S3(2); // both alus
5116 %}
5118 // Integer ALU reg operation using big decoder
5119 pipe_class ialu_reg_fat(rRegI dst) %{
5120 single_instruction;
5121 dst : S4(write);
5122 dst : S3(read);
5123 D0 : S0; // big decoder only
5124 ALU : S3; // any alu
5125 %}
5127 // Long ALU reg operation using big decoder
5128 pipe_class ialu_reg_long_fat(eRegL dst) %{
5129 instruction_count(2);
5130 dst : S4(write);
5131 dst : S3(read);
5132 D0 : S0(2); // big decoder only; twice
5133 ALU : S3(2); // any 2 alus
5134 %}
5136 // Integer ALU reg-reg operation
5137 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
5138 single_instruction;
5139 dst : S4(write);
5140 src : S3(read);
5141 DECODE : S0; // any decoder
5142 ALU : S3; // any alu
5143 %}
5145 // Long ALU reg-reg operation
5146 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5147 instruction_count(2);
5148 dst : S4(write);
5149 src : S3(read);
5150 DECODE : S0(2); // any 2 decoders
5151 ALU : S3(2); // both alus
5152 %}
5154 // Integer ALU reg-reg operation
5155 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
5156 single_instruction;
5157 dst : S4(write);
5158 src : S3(read);
5159 D0 : S0; // big decoder only
5160 ALU : S3; // any alu
5161 %}
5163 // Long ALU reg-reg operation
5164 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5165 instruction_count(2);
5166 dst : S4(write);
5167 src : S3(read);
5168 D0 : S0(2); // big decoder only; twice
5169 ALU : S3(2); // both alus
5170 %}
5172 // Integer ALU reg-mem operation
5173 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
5174 single_instruction;
5175 dst : S5(write);
5176 mem : S3(read);
5177 D0 : S0; // big decoder only
5178 ALU : S4; // any alu
5179 MEM : S3; // any mem
5180 %}
5182 // Long ALU reg-mem operation
5183 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5184 instruction_count(2);
5185 dst : S5(write);
5186 mem : S3(read);
5187 D0 : S0(2); // big decoder only; twice
5188 ALU : S4(2); // any 2 alus
5189 MEM : S3(2); // both mems
5190 %}
5192 // Integer mem operation (prefetch)
5193 pipe_class ialu_mem(memory mem)
5194 %{
5195 single_instruction;
5196 mem : S3(read);
5197 D0 : S0; // big decoder only
5198 MEM : S3; // any mem
5199 %}
5201 // Integer Store to Memory
5202 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
5203 single_instruction;
5204 mem : S3(read);
5205 src : S5(read);
5206 D0 : S0; // big decoder only
5207 ALU : S4; // any alu
5208 MEM : S3;
5209 %}
5211 // Long Store to Memory
5212 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5213 instruction_count(2);
5214 mem : S3(read);
5215 src : S5(read);
5216 D0 : S0(2); // big decoder only; twice
5217 ALU : S4(2); // any 2 alus
5218 MEM : S3(2); // Both mems
5219 %}
5221 // Integer Store to Memory
5222 pipe_class ialu_mem_imm(memory mem) %{
5223 single_instruction;
5224 mem : S3(read);
5225 D0 : S0; // big decoder only
5226 ALU : S4; // any alu
5227 MEM : S3;
5228 %}
5230 // Integer ALU0 reg-reg operation
5231 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
5232 single_instruction;
5233 dst : S4(write);
5234 src : S3(read);
5235 D0 : S0; // Big decoder only
5236 ALU0 : S3; // only alu0
5237 %}
5239 // Integer ALU0 reg-mem operation
5240 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
5241 single_instruction;
5242 dst : S5(write);
5243 mem : S3(read);
5244 D0 : S0; // big decoder only
5245 ALU0 : S4; // ALU0 only
5246 MEM : S3; // any mem
5247 %}
5249 // Integer ALU reg-reg operation
5250 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
5251 single_instruction;
5252 cr : S4(write);
5253 src1 : S3(read);
5254 src2 : S3(read);
5255 DECODE : S0; // any decoder
5256 ALU : S3; // any alu
5257 %}
5259 // Integer ALU reg-imm operation
5260 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
5261 single_instruction;
5262 cr : S4(write);
5263 src1 : S3(read);
5264 DECODE : S0; // any decoder
5265 ALU : S3; // any alu
5266 %}
5268 // Integer ALU reg-mem operation
5269 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
5270 single_instruction;
5271 cr : S4(write);
5272 src1 : S3(read);
5273 src2 : S3(read);
5274 D0 : S0; // big decoder only
5275 ALU : S4; // any alu
5276 MEM : S3;
5277 %}
5279 // Conditional move reg-reg
5280 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
5281 instruction_count(4);
5282 y : S4(read);
5283 q : S3(read);
5284 p : S3(read);
5285 DECODE : S0(4); // any decoder
5286 %}
5288 // Conditional move reg-reg
5289 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
5290 single_instruction;
5291 dst : S4(write);
5292 src : S3(read);
5293 cr : S3(read);
5294 DECODE : S0; // any decoder
5295 %}
5297 // Conditional move reg-mem
5298 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
5299 single_instruction;
5300 dst : S4(write);
5301 src : S3(read);
5302 cr : S3(read);
5303 DECODE : S0; // any decoder
5304 MEM : S3;
5305 %}
5307 // Conditional move reg-reg long
5308 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5309 single_instruction;
5310 dst : S4(write);
5311 src : S3(read);
5312 cr : S3(read);
5313 DECODE : S0(2); // any 2 decoders
5314 %}
5316 // Conditional move double reg-reg
5317 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5318 single_instruction;
5319 dst : S4(write);
5320 src : S3(read);
5321 cr : S3(read);
5322 DECODE : S0; // any decoder
5323 %}
5325 // Float reg-reg operation
5326 pipe_class fpu_reg(regDPR dst) %{
5327 instruction_count(2);
5328 dst : S3(read);
5329 DECODE : S0(2); // any 2 decoders
5330 FPU : S3;
5331 %}
5333 // Float reg-reg operation
5334 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5335 instruction_count(2);
5336 dst : S4(write);
5337 src : S3(read);
5338 DECODE : S0(2); // any 2 decoders
5339 FPU : S3;
5340 %}
5342 // Float reg-reg operation
5343 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5344 instruction_count(3);
5345 dst : S4(write);
5346 src1 : S3(read);
5347 src2 : S3(read);
5348 DECODE : S0(3); // any 3 decoders
5349 FPU : S3(2);
5350 %}
5352 // Float reg-reg operation
5353 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5354 instruction_count(4);
5355 dst : S4(write);
5356 src1 : S3(read);
5357 src2 : S3(read);
5358 src3 : S3(read);
5359 DECODE : S0(4); // any 3 decoders
5360 FPU : S3(2);
5361 %}
5363 // Float reg-reg operation
5364 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5365 instruction_count(4);
5366 dst : S4(write);
5367 src1 : S3(read);
5368 src2 : S3(read);
5369 src3 : S3(read);
5370 DECODE : S1(3); // any 3 decoders
5371 D0 : S0; // Big decoder only
5372 FPU : S3(2);
5373 MEM : S3;
5374 %}
5376 // Float reg-mem operation
5377 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5378 instruction_count(2);
5379 dst : S5(write);
5380 mem : S3(read);
5381 D0 : S0; // big decoder only
5382 DECODE : S1; // any decoder for FPU POP
5383 FPU : S4;
5384 MEM : S3; // any mem
5385 %}
5387 // Float reg-mem operation
5388 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5389 instruction_count(3);
5390 dst : S5(write);
5391 src1 : S3(read);
5392 mem : S3(read);
5393 D0 : S0; // big decoder only
5394 DECODE : S1(2); // any decoder for FPU POP
5395 FPU : S4;
5396 MEM : S3; // any mem
5397 %}
5399 // Float mem-reg operation
5400 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5401 instruction_count(2);
5402 src : S5(read);
5403 mem : S3(read);
5404 DECODE : S0; // any decoder for FPU PUSH
5405 D0 : S1; // big decoder only
5406 FPU : S4;
5407 MEM : S3; // any mem
5408 %}
5410 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5411 instruction_count(3);
5412 src1 : S3(read);
5413 src2 : S3(read);
5414 mem : S3(read);
5415 DECODE : S0(2); // any decoder for FPU PUSH
5416 D0 : S1; // big decoder only
5417 FPU : S4;
5418 MEM : S3; // any mem
5419 %}
5421 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5422 instruction_count(3);
5423 src1 : S3(read);
5424 src2 : S3(read);
5425 mem : S4(read);
5426 DECODE : S0; // any decoder for FPU PUSH
5427 D0 : S0(2); // big decoder only
5428 FPU : S4;
5429 MEM : S3(2); // any mem
5430 %}
5432 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5433 instruction_count(2);
5434 src1 : S3(read);
5435 dst : S4(read);
5436 D0 : S0(2); // big decoder only
5437 MEM : S3(2); // any mem
5438 %}
5440 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5441 instruction_count(3);
5442 src1 : S3(read);
5443 src2 : S3(read);
5444 dst : S4(read);
5445 D0 : S0(3); // big decoder only
5446 FPU : S4;
5447 MEM : S3(3); // any mem
5448 %}
5450 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5451 instruction_count(3);
5452 src1 : S4(read);
5453 mem : S4(read);
5454 DECODE : S0; // any decoder for FPU PUSH
5455 D0 : S0(2); // big decoder only
5456 FPU : S4;
5457 MEM : S3(2); // any mem
5458 %}
5460 // Float load constant
5461 pipe_class fpu_reg_con(regDPR dst) %{
5462 instruction_count(2);
5463 dst : S5(write);
5464 D0 : S0; // big decoder only for the load
5465 DECODE : S1; // any decoder for FPU POP
5466 FPU : S4;
5467 MEM : S3; // any mem
5468 %}
5470 // Float load constant
5471 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5472 instruction_count(3);
5473 dst : S5(write);
5474 src : S3(read);
5475 D0 : S0; // big decoder only for the load
5476 DECODE : S1(2); // any decoder for FPU POP
5477 FPU : S4;
5478 MEM : S3; // any mem
5479 %}
5481 // UnConditional branch
5482 pipe_class pipe_jmp( label labl ) %{
5483 single_instruction;
5484 BR : S3;
5485 %}
5487 // Conditional branch
5488 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5489 single_instruction;
5490 cr : S1(read);
5491 BR : S3;
5492 %}
5494 // Allocation idiom
5495 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5496 instruction_count(1); force_serialization;
5497 fixed_latency(6);
5498 heap_ptr : S3(read);
5499 DECODE : S0(3);
5500 D0 : S2;
5501 MEM : S3;
5502 ALU : S3(2);
5503 dst : S5(write);
5504 BR : S5;
5505 %}
5507 // Generic big/slow expanded idiom
5508 pipe_class pipe_slow( ) %{
5509 instruction_count(10); multiple_bundles; force_serialization;
5510 fixed_latency(100);
5511 D0 : S0(2);
5512 MEM : S3(2);
5513 %}
5515 // The real do-nothing guy
5516 pipe_class empty( ) %{
5517 instruction_count(0);
5518 %}
5520 // Define the class for the Nop node
5521 define %{
5522 MachNop = empty;
5523 %}
5525 %}
5527 //----------INSTRUCTIONS-------------------------------------------------------
5528 //
5529 // match -- States which machine-independent subtree may be replaced
5530 // by this instruction.
5531 // ins_cost -- The estimated cost of this instruction is used by instruction
5532 // selection to identify a minimum cost tree of machine
5533 // instructions that matches a tree of machine-independent
5534 // instructions.
5535 // format -- A string providing the disassembly for this instruction.
5536 // The value of an instruction's operand may be inserted
5537 // by referring to it with a '$' prefix.
5538 // opcode -- Three instruction opcodes may be provided. These are referred
5539 // to within an encode class as $primary, $secondary, and $tertiary
5540 // respectively. The primary opcode is commonly used to
5541 // indicate the type of machine instruction, while secondary
5542 // and tertiary are often used for prefix options or addressing
5543 // modes.
5544 // ins_encode -- A list of encode classes with parameters. The encode class
5545 // name must have been defined in an 'enc_class' specification
5546 // in the encode section of the architecture description.
5548 //----------BSWAP-Instruction--------------------------------------------------
5549 instruct bytes_reverse_int(rRegI dst) %{
5550 match(Set dst (ReverseBytesI dst));
5552 format %{ "BSWAP $dst" %}
5553 opcode(0x0F, 0xC8);
5554 ins_encode( OpcP, OpcSReg(dst) );
5555 ins_pipe( ialu_reg );
5556 %}
5558 instruct bytes_reverse_long(eRegL dst) %{
5559 match(Set dst (ReverseBytesL dst));
5561 format %{ "BSWAP $dst.lo\n\t"
5562 "BSWAP $dst.hi\n\t"
5563 "XCHG $dst.lo $dst.hi" %}
5565 ins_cost(125);
5566 ins_encode( bswap_long_bytes(dst) );
5567 ins_pipe( ialu_reg_reg);
5568 %}
5570 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5571 match(Set dst (ReverseBytesUS dst));
5572 effect(KILL cr);
5574 format %{ "BSWAP $dst\n\t"
5575 "SHR $dst,16\n\t" %}
5576 ins_encode %{
5577 __ bswapl($dst$$Register);
5578 __ shrl($dst$$Register, 16);
5579 %}
5580 ins_pipe( ialu_reg );
5581 %}
5583 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5584 match(Set dst (ReverseBytesS dst));
5585 effect(KILL cr);
5587 format %{ "BSWAP $dst\n\t"
5588 "SAR $dst,16\n\t" %}
5589 ins_encode %{
5590 __ bswapl($dst$$Register);
5591 __ sarl($dst$$Register, 16);
5592 %}
5593 ins_pipe( ialu_reg );
5594 %}
5597 //---------- Zeros Count Instructions ------------------------------------------
5599 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5600 predicate(UseCountLeadingZerosInstruction);
5601 match(Set dst (CountLeadingZerosI src));
5602 effect(KILL cr);
5604 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5605 ins_encode %{
5606 __ lzcntl($dst$$Register, $src$$Register);
5607 %}
5608 ins_pipe(ialu_reg);
5609 %}
5611 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5612 predicate(!UseCountLeadingZerosInstruction);
5613 match(Set dst (CountLeadingZerosI src));
5614 effect(KILL cr);
5616 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5617 "JNZ skip\n\t"
5618 "MOV $dst, -1\n"
5619 "skip:\n\t"
5620 "NEG $dst\n\t"
5621 "ADD $dst, 31" %}
5622 ins_encode %{
5623 Register Rdst = $dst$$Register;
5624 Register Rsrc = $src$$Register;
5625 Label skip;
5626 __ bsrl(Rdst, Rsrc);
5627 __ jccb(Assembler::notZero, skip);
5628 __ movl(Rdst, -1);
5629 __ bind(skip);
5630 __ negl(Rdst);
5631 __ addl(Rdst, BitsPerInt - 1);
5632 %}
5633 ins_pipe(ialu_reg);
5634 %}
5636 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5637 predicate(UseCountLeadingZerosInstruction);
5638 match(Set dst (CountLeadingZerosL src));
5639 effect(TEMP dst, KILL cr);
5641 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5642 "JNC done\n\t"
5643 "LZCNT $dst, $src.lo\n\t"
5644 "ADD $dst, 32\n"
5645 "done:" %}
5646 ins_encode %{
5647 Register Rdst = $dst$$Register;
5648 Register Rsrc = $src$$Register;
5649 Label done;
5650 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5651 __ jccb(Assembler::carryClear, done);
5652 __ lzcntl(Rdst, Rsrc);
5653 __ addl(Rdst, BitsPerInt);
5654 __ bind(done);
5655 %}
5656 ins_pipe(ialu_reg);
5657 %}
5659 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5660 predicate(!UseCountLeadingZerosInstruction);
5661 match(Set dst (CountLeadingZerosL src));
5662 effect(TEMP dst, KILL cr);
5664 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5665 "JZ msw_is_zero\n\t"
5666 "ADD $dst, 32\n\t"
5667 "JMP not_zero\n"
5668 "msw_is_zero:\n\t"
5669 "BSR $dst, $src.lo\n\t"
5670 "JNZ not_zero\n\t"
5671 "MOV $dst, -1\n"
5672 "not_zero:\n\t"
5673 "NEG $dst\n\t"
5674 "ADD $dst, 63\n" %}
5675 ins_encode %{
5676 Register Rdst = $dst$$Register;
5677 Register Rsrc = $src$$Register;
5678 Label msw_is_zero;
5679 Label not_zero;
5680 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5681 __ jccb(Assembler::zero, msw_is_zero);
5682 __ addl(Rdst, BitsPerInt);
5683 __ jmpb(not_zero);
5684 __ bind(msw_is_zero);
5685 __ bsrl(Rdst, Rsrc);
5686 __ jccb(Assembler::notZero, not_zero);
5687 __ movl(Rdst, -1);
5688 __ bind(not_zero);
5689 __ negl(Rdst);
5690 __ addl(Rdst, BitsPerLong - 1);
5691 %}
5692 ins_pipe(ialu_reg);
5693 %}
5695 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5696 match(Set dst (CountTrailingZerosI src));
5697 effect(KILL cr);
5699 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5700 "JNZ done\n\t"
5701 "MOV $dst, 32\n"
5702 "done:" %}
5703 ins_encode %{
5704 Register Rdst = $dst$$Register;
5705 Label done;
5706 __ bsfl(Rdst, $src$$Register);
5707 __ jccb(Assembler::notZero, done);
5708 __ movl(Rdst, BitsPerInt);
5709 __ bind(done);
5710 %}
5711 ins_pipe(ialu_reg);
5712 %}
5714 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5715 match(Set dst (CountTrailingZerosL src));
5716 effect(TEMP dst, KILL cr);
5718 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5719 "JNZ done\n\t"
5720 "BSF $dst, $src.hi\n\t"
5721 "JNZ msw_not_zero\n\t"
5722 "MOV $dst, 32\n"
5723 "msw_not_zero:\n\t"
5724 "ADD $dst, 32\n"
5725 "done:" %}
5726 ins_encode %{
5727 Register Rdst = $dst$$Register;
5728 Register Rsrc = $src$$Register;
5729 Label msw_not_zero;
5730 Label done;
5731 __ bsfl(Rdst, Rsrc);
5732 __ jccb(Assembler::notZero, done);
5733 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5734 __ jccb(Assembler::notZero, msw_not_zero);
5735 __ movl(Rdst, BitsPerInt);
5736 __ bind(msw_not_zero);
5737 __ addl(Rdst, BitsPerInt);
5738 __ bind(done);
5739 %}
5740 ins_pipe(ialu_reg);
5741 %}
5744 //---------- Population Count Instructions -------------------------------------
5746 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5747 predicate(UsePopCountInstruction);
5748 match(Set dst (PopCountI src));
5749 effect(KILL cr);
5751 format %{ "POPCNT $dst, $src" %}
5752 ins_encode %{
5753 __ popcntl($dst$$Register, $src$$Register);
5754 %}
5755 ins_pipe(ialu_reg);
5756 %}
5758 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5759 predicate(UsePopCountInstruction);
5760 match(Set dst (PopCountI (LoadI mem)));
5761 effect(KILL cr);
5763 format %{ "POPCNT $dst, $mem" %}
5764 ins_encode %{
5765 __ popcntl($dst$$Register, $mem$$Address);
5766 %}
5767 ins_pipe(ialu_reg);
5768 %}
5770 // Note: Long.bitCount(long) returns an int.
5771 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5772 predicate(UsePopCountInstruction);
5773 match(Set dst (PopCountL src));
5774 effect(KILL cr, TEMP tmp, TEMP dst);
5776 format %{ "POPCNT $dst, $src.lo\n\t"
5777 "POPCNT $tmp, $src.hi\n\t"
5778 "ADD $dst, $tmp" %}
5779 ins_encode %{
5780 __ popcntl($dst$$Register, $src$$Register);
5781 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5782 __ addl($dst$$Register, $tmp$$Register);
5783 %}
5784 ins_pipe(ialu_reg);
5785 %}
5787 // Note: Long.bitCount(long) returns an int.
5788 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5789 predicate(UsePopCountInstruction);
5790 match(Set dst (PopCountL (LoadL mem)));
5791 effect(KILL cr, TEMP tmp, TEMP dst);
5793 format %{ "POPCNT $dst, $mem\n\t"
5794 "POPCNT $tmp, $mem+4\n\t"
5795 "ADD $dst, $tmp" %}
5796 ins_encode %{
5797 //__ popcntl($dst$$Register, $mem$$Address$$first);
5798 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5799 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5800 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5801 __ addl($dst$$Register, $tmp$$Register);
5802 %}
5803 ins_pipe(ialu_reg);
5804 %}
5807 //----------Load/Store/Move Instructions---------------------------------------
5808 //----------Load Instructions--------------------------------------------------
5809 // Load Byte (8bit signed)
5810 instruct loadB(xRegI dst, memory mem) %{
5811 match(Set dst (LoadB mem));
5813 ins_cost(125);
5814 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5816 ins_encode %{
5817 __ movsbl($dst$$Register, $mem$$Address);
5818 %}
5820 ins_pipe(ialu_reg_mem);
5821 %}
5823 // Load Byte (8bit signed) into Long Register
5824 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5825 match(Set dst (ConvI2L (LoadB mem)));
5826 effect(KILL cr);
5828 ins_cost(375);
5829 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5830 "MOV $dst.hi,$dst.lo\n\t"
5831 "SAR $dst.hi,7" %}
5833 ins_encode %{
5834 __ movsbl($dst$$Register, $mem$$Address);
5835 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5836 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5837 %}
5839 ins_pipe(ialu_reg_mem);
5840 %}
5842 // Load Unsigned Byte (8bit UNsigned)
5843 instruct loadUB(xRegI dst, memory mem) %{
5844 match(Set dst (LoadUB mem));
5846 ins_cost(125);
5847 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5849 ins_encode %{
5850 __ movzbl($dst$$Register, $mem$$Address);
5851 %}
5853 ins_pipe(ialu_reg_mem);
5854 %}
5856 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5857 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5858 match(Set dst (ConvI2L (LoadUB mem)));
5859 effect(KILL cr);
5861 ins_cost(250);
5862 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5863 "XOR $dst.hi,$dst.hi" %}
5865 ins_encode %{
5866 Register Rdst = $dst$$Register;
5867 __ movzbl(Rdst, $mem$$Address);
5868 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5869 %}
5871 ins_pipe(ialu_reg_mem);
5872 %}
5874 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5875 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5876 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5877 effect(KILL cr);
5879 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5880 "XOR $dst.hi,$dst.hi\n\t"
5881 "AND $dst.lo,$mask" %}
5882 ins_encode %{
5883 Register Rdst = $dst$$Register;
5884 __ movzbl(Rdst, $mem$$Address);
5885 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5886 __ andl(Rdst, $mask$$constant);
5887 %}
5888 ins_pipe(ialu_reg_mem);
5889 %}
5891 // Load Short (16bit signed)
5892 instruct loadS(rRegI dst, memory mem) %{
5893 match(Set dst (LoadS mem));
5895 ins_cost(125);
5896 format %{ "MOVSX $dst,$mem\t# short" %}
5898 ins_encode %{
5899 __ movswl($dst$$Register, $mem$$Address);
5900 %}
5902 ins_pipe(ialu_reg_mem);
5903 %}
5905 // Load Short (16 bit signed) to Byte (8 bit signed)
5906 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5907 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5909 ins_cost(125);
5910 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5911 ins_encode %{
5912 __ movsbl($dst$$Register, $mem$$Address);
5913 %}
5914 ins_pipe(ialu_reg_mem);
5915 %}
5917 // Load Short (16bit signed) into Long Register
5918 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5919 match(Set dst (ConvI2L (LoadS mem)));
5920 effect(KILL cr);
5922 ins_cost(375);
5923 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5924 "MOV $dst.hi,$dst.lo\n\t"
5925 "SAR $dst.hi,15" %}
5927 ins_encode %{
5928 __ movswl($dst$$Register, $mem$$Address);
5929 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5930 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5931 %}
5933 ins_pipe(ialu_reg_mem);
5934 %}
5936 // Load Unsigned Short/Char (16bit unsigned)
5937 instruct loadUS(rRegI dst, memory mem) %{
5938 match(Set dst (LoadUS mem));
5940 ins_cost(125);
5941 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5943 ins_encode %{
5944 __ movzwl($dst$$Register, $mem$$Address);
5945 %}
5947 ins_pipe(ialu_reg_mem);
5948 %}
5950 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5951 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5952 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5954 ins_cost(125);
5955 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5956 ins_encode %{
5957 __ movsbl($dst$$Register, $mem$$Address);
5958 %}
5959 ins_pipe(ialu_reg_mem);
5960 %}
5962 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5963 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5964 match(Set dst (ConvI2L (LoadUS mem)));
5965 effect(KILL cr);
5967 ins_cost(250);
5968 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
5969 "XOR $dst.hi,$dst.hi" %}
5971 ins_encode %{
5972 __ movzwl($dst$$Register, $mem$$Address);
5973 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5974 %}
5976 ins_pipe(ialu_reg_mem);
5977 %}
5979 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5980 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5981 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5982 effect(KILL cr);
5984 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
5985 "XOR $dst.hi,$dst.hi" %}
5986 ins_encode %{
5987 Register Rdst = $dst$$Register;
5988 __ movzbl(Rdst, $mem$$Address);
5989 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5990 %}
5991 ins_pipe(ialu_reg_mem);
5992 %}
5994 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
5995 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
5996 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5997 effect(KILL cr);
5999 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6000 "XOR $dst.hi,$dst.hi\n\t"
6001 "AND $dst.lo,$mask" %}
6002 ins_encode %{
6003 Register Rdst = $dst$$Register;
6004 __ movzwl(Rdst, $mem$$Address);
6005 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6006 __ andl(Rdst, $mask$$constant);
6007 %}
6008 ins_pipe(ialu_reg_mem);
6009 %}
6011 // Load Integer
6012 instruct loadI(rRegI dst, memory mem) %{
6013 match(Set dst (LoadI mem));
6015 ins_cost(125);
6016 format %{ "MOV $dst,$mem\t# int" %}
6018 ins_encode %{
6019 __ movl($dst$$Register, $mem$$Address);
6020 %}
6022 ins_pipe(ialu_reg_mem);
6023 %}
6025 // Load Integer (32 bit signed) to Byte (8 bit signed)
6026 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6027 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6029 ins_cost(125);
6030 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6031 ins_encode %{
6032 __ movsbl($dst$$Register, $mem$$Address);
6033 %}
6034 ins_pipe(ialu_reg_mem);
6035 %}
6037 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6038 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
6039 match(Set dst (AndI (LoadI mem) mask));
6041 ins_cost(125);
6042 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6043 ins_encode %{
6044 __ movzbl($dst$$Register, $mem$$Address);
6045 %}
6046 ins_pipe(ialu_reg_mem);
6047 %}
6049 // Load Integer (32 bit signed) to Short (16 bit signed)
6050 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6051 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6053 ins_cost(125);
6054 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6055 ins_encode %{
6056 __ movswl($dst$$Register, $mem$$Address);
6057 %}
6058 ins_pipe(ialu_reg_mem);
6059 %}
6061 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6062 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6063 match(Set dst (AndI (LoadI mem) mask));
6065 ins_cost(125);
6066 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6067 ins_encode %{
6068 __ movzwl($dst$$Register, $mem$$Address);
6069 %}
6070 ins_pipe(ialu_reg_mem);
6071 %}
6073 // Load Integer into Long Register
6074 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6075 match(Set dst (ConvI2L (LoadI mem)));
6076 effect(KILL cr);
6078 ins_cost(375);
6079 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6080 "MOV $dst.hi,$dst.lo\n\t"
6081 "SAR $dst.hi,31" %}
6083 ins_encode %{
6084 __ movl($dst$$Register, $mem$$Address);
6085 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6086 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6087 %}
6089 ins_pipe(ialu_reg_mem);
6090 %}
6092 // Load Integer with mask 0xFF into Long Register
6093 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6094 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6095 effect(KILL cr);
6097 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6098 "XOR $dst.hi,$dst.hi" %}
6099 ins_encode %{
6100 Register Rdst = $dst$$Register;
6101 __ movzbl(Rdst, $mem$$Address);
6102 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6103 %}
6104 ins_pipe(ialu_reg_mem);
6105 %}
6107 // Load Integer with mask 0xFFFF into Long Register
6108 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6109 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6110 effect(KILL cr);
6112 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6113 "XOR $dst.hi,$dst.hi" %}
6114 ins_encode %{
6115 Register Rdst = $dst$$Register;
6116 __ movzwl(Rdst, $mem$$Address);
6117 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6118 %}
6119 ins_pipe(ialu_reg_mem);
6120 %}
6122 // Load Integer with 32-bit mask into Long Register
6123 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6124 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6125 effect(KILL cr);
6127 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6128 "XOR $dst.hi,$dst.hi\n\t"
6129 "AND $dst.lo,$mask" %}
6130 ins_encode %{
6131 Register Rdst = $dst$$Register;
6132 __ movl(Rdst, $mem$$Address);
6133 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6134 __ andl(Rdst, $mask$$constant);
6135 %}
6136 ins_pipe(ialu_reg_mem);
6137 %}
6139 // Load Unsigned Integer into Long Register
6140 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{
6141 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
6142 effect(KILL cr);
6144 ins_cost(250);
6145 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6146 "XOR $dst.hi,$dst.hi" %}
6148 ins_encode %{
6149 __ movl($dst$$Register, $mem$$Address);
6150 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6151 %}
6153 ins_pipe(ialu_reg_mem);
6154 %}
6156 // Load Long. Cannot clobber address while loading, so restrict address
6157 // register to ESI
6158 instruct loadL(eRegL dst, load_long_memory mem) %{
6159 predicate(!((LoadLNode*)n)->require_atomic_access());
6160 match(Set dst (LoadL mem));
6162 ins_cost(250);
6163 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6164 "MOV $dst.hi,$mem+4" %}
6166 ins_encode %{
6167 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
6168 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
6169 __ movl($dst$$Register, Amemlo);
6170 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6171 %}
6173 ins_pipe(ialu_reg_long_mem);
6174 %}
6176 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6177 // then store it down to the stack and reload on the int
6178 // side.
6179 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6180 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6181 match(Set dst (LoadL mem));
6183 ins_cost(200);
6184 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6185 "FISTp $dst" %}
6186 ins_encode(enc_loadL_volatile(mem,dst));
6187 ins_pipe( fpu_reg_mem );
6188 %}
6190 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6191 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6192 match(Set dst (LoadL mem));
6193 effect(TEMP tmp);
6194 ins_cost(180);
6195 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6196 "MOVSD $dst,$tmp" %}
6197 ins_encode %{
6198 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6199 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6200 %}
6201 ins_pipe( pipe_slow );
6202 %}
6204 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6205 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6206 match(Set dst (LoadL mem));
6207 effect(TEMP tmp);
6208 ins_cost(160);
6209 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6210 "MOVD $dst.lo,$tmp\n\t"
6211 "PSRLQ $tmp,32\n\t"
6212 "MOVD $dst.hi,$tmp" %}
6213 ins_encode %{
6214 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6215 __ movdl($dst$$Register, $tmp$$XMMRegister);
6216 __ psrlq($tmp$$XMMRegister, 32);
6217 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6218 %}
6219 ins_pipe( pipe_slow );
6220 %}
6222 // Load Range
6223 instruct loadRange(rRegI dst, memory mem) %{
6224 match(Set dst (LoadRange mem));
6226 ins_cost(125);
6227 format %{ "MOV $dst,$mem" %}
6228 opcode(0x8B);
6229 ins_encode( OpcP, RegMem(dst,mem));
6230 ins_pipe( ialu_reg_mem );
6231 %}
6234 // Load Pointer
6235 instruct loadP(eRegP dst, memory mem) %{
6236 match(Set dst (LoadP mem));
6238 ins_cost(125);
6239 format %{ "MOV $dst,$mem" %}
6240 opcode(0x8B);
6241 ins_encode( OpcP, RegMem(dst,mem));
6242 ins_pipe( ialu_reg_mem );
6243 %}
6245 // Load Klass Pointer
6246 instruct loadKlass(eRegP dst, memory mem) %{
6247 match(Set dst (LoadKlass mem));
6249 ins_cost(125);
6250 format %{ "MOV $dst,$mem" %}
6251 opcode(0x8B);
6252 ins_encode( OpcP, RegMem(dst,mem));
6253 ins_pipe( ialu_reg_mem );
6254 %}
6256 // Load Double
6257 instruct loadDPR(regDPR dst, memory mem) %{
6258 predicate(UseSSE<=1);
6259 match(Set dst (LoadD mem));
6261 ins_cost(150);
6262 format %{ "FLD_D ST,$mem\n\t"
6263 "FSTP $dst" %}
6264 opcode(0xDD); /* DD /0 */
6265 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6266 Pop_Reg_DPR(dst) );
6267 ins_pipe( fpu_reg_mem );
6268 %}
6270 // Load Double to XMM
6271 instruct loadD(regD dst, memory mem) %{
6272 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6273 match(Set dst (LoadD mem));
6274 ins_cost(145);
6275 format %{ "MOVSD $dst,$mem" %}
6276 ins_encode %{
6277 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6278 %}
6279 ins_pipe( pipe_slow );
6280 %}
6282 instruct loadD_partial(regD dst, memory mem) %{
6283 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6284 match(Set dst (LoadD mem));
6285 ins_cost(145);
6286 format %{ "MOVLPD $dst,$mem" %}
6287 ins_encode %{
6288 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6289 %}
6290 ins_pipe( pipe_slow );
6291 %}
6293 // Load to XMM register (single-precision floating point)
6294 // MOVSS instruction
6295 instruct loadF(regF dst, memory mem) %{
6296 predicate(UseSSE>=1);
6297 match(Set dst (LoadF mem));
6298 ins_cost(145);
6299 format %{ "MOVSS $dst,$mem" %}
6300 ins_encode %{
6301 __ movflt ($dst$$XMMRegister, $mem$$Address);
6302 %}
6303 ins_pipe( pipe_slow );
6304 %}
6306 // Load Float
6307 instruct loadFPR(regFPR dst, memory mem) %{
6308 predicate(UseSSE==0);
6309 match(Set dst (LoadF mem));
6311 ins_cost(150);
6312 format %{ "FLD_S ST,$mem\n\t"
6313 "FSTP $dst" %}
6314 opcode(0xD9); /* D9 /0 */
6315 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6316 Pop_Reg_FPR(dst) );
6317 ins_pipe( fpu_reg_mem );
6318 %}
6320 // Load Effective Address
6321 instruct leaP8(eRegP dst, indOffset8 mem) %{
6322 match(Set dst mem);
6324 ins_cost(110);
6325 format %{ "LEA $dst,$mem" %}
6326 opcode(0x8D);
6327 ins_encode( OpcP, RegMem(dst,mem));
6328 ins_pipe( ialu_reg_reg_fat );
6329 %}
6331 instruct leaP32(eRegP dst, indOffset32 mem) %{
6332 match(Set dst mem);
6334 ins_cost(110);
6335 format %{ "LEA $dst,$mem" %}
6336 opcode(0x8D);
6337 ins_encode( OpcP, RegMem(dst,mem));
6338 ins_pipe( ialu_reg_reg_fat );
6339 %}
6341 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6342 match(Set dst mem);
6344 ins_cost(110);
6345 format %{ "LEA $dst,$mem" %}
6346 opcode(0x8D);
6347 ins_encode( OpcP, RegMem(dst,mem));
6348 ins_pipe( ialu_reg_reg_fat );
6349 %}
6351 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6352 match(Set dst mem);
6354 ins_cost(110);
6355 format %{ "LEA $dst,$mem" %}
6356 opcode(0x8D);
6357 ins_encode( OpcP, RegMem(dst,mem));
6358 ins_pipe( ialu_reg_reg_fat );
6359 %}
6361 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6362 match(Set dst mem);
6364 ins_cost(110);
6365 format %{ "LEA $dst,$mem" %}
6366 opcode(0x8D);
6367 ins_encode( OpcP, RegMem(dst,mem));
6368 ins_pipe( ialu_reg_reg_fat );
6369 %}
6371 // Load Constant
6372 instruct loadConI(rRegI dst, immI src) %{
6373 match(Set dst src);
6375 format %{ "MOV $dst,$src" %}
6376 ins_encode( LdImmI(dst, src) );
6377 ins_pipe( ialu_reg_fat );
6378 %}
6380 // Load Constant zero
6381 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
6382 match(Set dst src);
6383 effect(KILL cr);
6385 ins_cost(50);
6386 format %{ "XOR $dst,$dst" %}
6387 opcode(0x33); /* + rd */
6388 ins_encode( OpcP, RegReg( dst, dst ) );
6389 ins_pipe( ialu_reg );
6390 %}
6392 instruct loadConP(eRegP dst, immP src) %{
6393 match(Set dst src);
6395 format %{ "MOV $dst,$src" %}
6396 opcode(0xB8); /* + rd */
6397 ins_encode( LdImmP(dst, src) );
6398 ins_pipe( ialu_reg_fat );
6399 %}
6401 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6402 match(Set dst src);
6403 effect(KILL cr);
6404 ins_cost(200);
6405 format %{ "MOV $dst.lo,$src.lo\n\t"
6406 "MOV $dst.hi,$src.hi" %}
6407 opcode(0xB8);
6408 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6409 ins_pipe( ialu_reg_long_fat );
6410 %}
6412 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6413 match(Set dst src);
6414 effect(KILL cr);
6415 ins_cost(150);
6416 format %{ "XOR $dst.lo,$dst.lo\n\t"
6417 "XOR $dst.hi,$dst.hi" %}
6418 opcode(0x33,0x33);
6419 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6420 ins_pipe( ialu_reg_long );
6421 %}
6423 // The instruction usage is guarded by predicate in operand immFPR().
6424 instruct loadConFPR(regFPR dst, immFPR con) %{
6425 match(Set dst con);
6426 ins_cost(125);
6427 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6428 "FSTP $dst" %}
6429 ins_encode %{
6430 __ fld_s($constantaddress($con));
6431 __ fstp_d($dst$$reg);
6432 %}
6433 ins_pipe(fpu_reg_con);
6434 %}
6436 // The instruction usage is guarded by predicate in operand immFPR0().
6437 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6438 match(Set dst con);
6439 ins_cost(125);
6440 format %{ "FLDZ ST\n\t"
6441 "FSTP $dst" %}
6442 ins_encode %{
6443 __ fldz();
6444 __ fstp_d($dst$$reg);
6445 %}
6446 ins_pipe(fpu_reg_con);
6447 %}
6449 // The instruction usage is guarded by predicate in operand immFPR1().
6450 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6451 match(Set dst con);
6452 ins_cost(125);
6453 format %{ "FLD1 ST\n\t"
6454 "FSTP $dst" %}
6455 ins_encode %{
6456 __ fld1();
6457 __ fstp_d($dst$$reg);
6458 %}
6459 ins_pipe(fpu_reg_con);
6460 %}
6462 // The instruction usage is guarded by predicate in operand immF().
6463 instruct loadConF(regF dst, immF con) %{
6464 match(Set dst con);
6465 ins_cost(125);
6466 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6467 ins_encode %{
6468 __ movflt($dst$$XMMRegister, $constantaddress($con));
6469 %}
6470 ins_pipe(pipe_slow);
6471 %}
6473 // The instruction usage is guarded by predicate in operand immF0().
6474 instruct loadConF0(regF dst, immF0 src) %{
6475 match(Set dst src);
6476 ins_cost(100);
6477 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6478 ins_encode %{
6479 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6480 %}
6481 ins_pipe(pipe_slow);
6482 %}
6484 // The instruction usage is guarded by predicate in operand immDPR().
6485 instruct loadConDPR(regDPR dst, immDPR con) %{
6486 match(Set dst con);
6487 ins_cost(125);
6489 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6490 "FSTP $dst" %}
6491 ins_encode %{
6492 __ fld_d($constantaddress($con));
6493 __ fstp_d($dst$$reg);
6494 %}
6495 ins_pipe(fpu_reg_con);
6496 %}
6498 // The instruction usage is guarded by predicate in operand immDPR0().
6499 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6500 match(Set dst con);
6501 ins_cost(125);
6503 format %{ "FLDZ ST\n\t"
6504 "FSTP $dst" %}
6505 ins_encode %{
6506 __ fldz();
6507 __ fstp_d($dst$$reg);
6508 %}
6509 ins_pipe(fpu_reg_con);
6510 %}
6512 // The instruction usage is guarded by predicate in operand immDPR1().
6513 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6514 match(Set dst con);
6515 ins_cost(125);
6517 format %{ "FLD1 ST\n\t"
6518 "FSTP $dst" %}
6519 ins_encode %{
6520 __ fld1();
6521 __ fstp_d($dst$$reg);
6522 %}
6523 ins_pipe(fpu_reg_con);
6524 %}
6526 // The instruction usage is guarded by predicate in operand immD().
6527 instruct loadConD(regD dst, immD con) %{
6528 match(Set dst con);
6529 ins_cost(125);
6530 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6531 ins_encode %{
6532 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6533 %}
6534 ins_pipe(pipe_slow);
6535 %}
6537 // The instruction usage is guarded by predicate in operand immD0().
6538 instruct loadConD0(regD dst, immD0 src) %{
6539 match(Set dst src);
6540 ins_cost(100);
6541 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6542 ins_encode %{
6543 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6544 %}
6545 ins_pipe( pipe_slow );
6546 %}
6548 // Load Stack Slot
6549 instruct loadSSI(rRegI dst, stackSlotI src) %{
6550 match(Set dst src);
6551 ins_cost(125);
6553 format %{ "MOV $dst,$src" %}
6554 opcode(0x8B);
6555 ins_encode( OpcP, RegMem(dst,src));
6556 ins_pipe( ialu_reg_mem );
6557 %}
6559 instruct loadSSL(eRegL dst, stackSlotL src) %{
6560 match(Set dst src);
6562 ins_cost(200);
6563 format %{ "MOV $dst,$src.lo\n\t"
6564 "MOV $dst+4,$src.hi" %}
6565 opcode(0x8B, 0x8B);
6566 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6567 ins_pipe( ialu_mem_long_reg );
6568 %}
6570 // Load Stack Slot
6571 instruct loadSSP(eRegP dst, stackSlotP src) %{
6572 match(Set dst src);
6573 ins_cost(125);
6575 format %{ "MOV $dst,$src" %}
6576 opcode(0x8B);
6577 ins_encode( OpcP, RegMem(dst,src));
6578 ins_pipe( ialu_reg_mem );
6579 %}
6581 // Load Stack Slot
6582 instruct loadSSF(regFPR dst, stackSlotF src) %{
6583 match(Set dst src);
6584 ins_cost(125);
6586 format %{ "FLD_S $src\n\t"
6587 "FSTP $dst" %}
6588 opcode(0xD9); /* D9 /0, FLD m32real */
6589 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6590 Pop_Reg_FPR(dst) );
6591 ins_pipe( fpu_reg_mem );
6592 %}
6594 // Load Stack Slot
6595 instruct loadSSD(regDPR dst, stackSlotD src) %{
6596 match(Set dst src);
6597 ins_cost(125);
6599 format %{ "FLD_D $src\n\t"
6600 "FSTP $dst" %}
6601 opcode(0xDD); /* DD /0, FLD m64real */
6602 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6603 Pop_Reg_DPR(dst) );
6604 ins_pipe( fpu_reg_mem );
6605 %}
6607 // Prefetch instructions.
6608 // Must be safe to execute with invalid address (cannot fault).
6610 instruct prefetchr0( memory mem ) %{
6611 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6612 match(PrefetchRead mem);
6613 ins_cost(0);
6614 size(0);
6615 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6616 ins_encode();
6617 ins_pipe(empty);
6618 %}
6620 instruct prefetchr( memory mem ) %{
6621 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6622 match(PrefetchRead mem);
6623 ins_cost(100);
6625 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6626 ins_encode %{
6627 __ prefetchr($mem$$Address);
6628 %}
6629 ins_pipe(ialu_mem);
6630 %}
6632 instruct prefetchrNTA( memory mem ) %{
6633 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6634 match(PrefetchRead mem);
6635 ins_cost(100);
6637 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6638 ins_encode %{
6639 __ prefetchnta($mem$$Address);
6640 %}
6641 ins_pipe(ialu_mem);
6642 %}
6644 instruct prefetchrT0( memory mem ) %{
6645 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6646 match(PrefetchRead mem);
6647 ins_cost(100);
6649 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6650 ins_encode %{
6651 __ prefetcht0($mem$$Address);
6652 %}
6653 ins_pipe(ialu_mem);
6654 %}
6656 instruct prefetchrT2( memory mem ) %{
6657 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6658 match(PrefetchRead mem);
6659 ins_cost(100);
6661 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6662 ins_encode %{
6663 __ prefetcht2($mem$$Address);
6664 %}
6665 ins_pipe(ialu_mem);
6666 %}
6668 instruct prefetchw0( memory mem ) %{
6669 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6670 match(PrefetchWrite mem);
6671 ins_cost(0);
6672 size(0);
6673 format %{ "Prefetch (non-SSE is empty encoding)" %}
6674 ins_encode();
6675 ins_pipe(empty);
6676 %}
6678 instruct prefetchw( memory mem ) %{
6679 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6680 match( PrefetchWrite mem );
6681 ins_cost(100);
6683 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6684 ins_encode %{
6685 __ prefetchw($mem$$Address);
6686 %}
6687 ins_pipe(ialu_mem);
6688 %}
6690 instruct prefetchwNTA( memory mem ) %{
6691 predicate(UseSSE>=1);
6692 match(PrefetchWrite mem);
6693 ins_cost(100);
6695 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6696 ins_encode %{
6697 __ prefetchnta($mem$$Address);
6698 %}
6699 ins_pipe(ialu_mem);
6700 %}
6702 // Prefetch instructions for allocation.
6704 instruct prefetchAlloc0( memory mem ) %{
6705 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6706 match(PrefetchAllocation mem);
6707 ins_cost(0);
6708 size(0);
6709 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6710 ins_encode();
6711 ins_pipe(empty);
6712 %}
6714 instruct prefetchAlloc( memory mem ) %{
6715 predicate(AllocatePrefetchInstr==3);
6716 match( PrefetchAllocation mem );
6717 ins_cost(100);
6719 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6720 ins_encode %{
6721 __ prefetchw($mem$$Address);
6722 %}
6723 ins_pipe(ialu_mem);
6724 %}
6726 instruct prefetchAllocNTA( memory mem ) %{
6727 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6728 match(PrefetchAllocation mem);
6729 ins_cost(100);
6731 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6732 ins_encode %{
6733 __ prefetchnta($mem$$Address);
6734 %}
6735 ins_pipe(ialu_mem);
6736 %}
6738 instruct prefetchAllocT0( memory mem ) %{
6739 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6740 match(PrefetchAllocation mem);
6741 ins_cost(100);
6743 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6744 ins_encode %{
6745 __ prefetcht0($mem$$Address);
6746 %}
6747 ins_pipe(ialu_mem);
6748 %}
6750 instruct prefetchAllocT2( memory mem ) %{
6751 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6752 match(PrefetchAllocation mem);
6753 ins_cost(100);
6755 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6756 ins_encode %{
6757 __ prefetcht2($mem$$Address);
6758 %}
6759 ins_pipe(ialu_mem);
6760 %}
6762 //----------Store Instructions-------------------------------------------------
6764 // Store Byte
6765 instruct storeB(memory mem, xRegI src) %{
6766 match(Set mem (StoreB mem src));
6768 ins_cost(125);
6769 format %{ "MOV8 $mem,$src" %}
6770 opcode(0x88);
6771 ins_encode( OpcP, RegMem( src, mem ) );
6772 ins_pipe( ialu_mem_reg );
6773 %}
6775 // Store Char/Short
6776 instruct storeC(memory mem, rRegI src) %{
6777 match(Set mem (StoreC mem src));
6779 ins_cost(125);
6780 format %{ "MOV16 $mem,$src" %}
6781 opcode(0x89, 0x66);
6782 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6783 ins_pipe( ialu_mem_reg );
6784 %}
6786 // Store Integer
6787 instruct storeI(memory mem, rRegI src) %{
6788 match(Set mem (StoreI mem src));
6790 ins_cost(125);
6791 format %{ "MOV $mem,$src" %}
6792 opcode(0x89);
6793 ins_encode( OpcP, RegMem( src, mem ) );
6794 ins_pipe( ialu_mem_reg );
6795 %}
6797 // Store Long
6798 instruct storeL(long_memory mem, eRegL src) %{
6799 predicate(!((StoreLNode*)n)->require_atomic_access());
6800 match(Set mem (StoreL mem src));
6802 ins_cost(200);
6803 format %{ "MOV $mem,$src.lo\n\t"
6804 "MOV $mem+4,$src.hi" %}
6805 opcode(0x89, 0x89);
6806 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6807 ins_pipe( ialu_mem_long_reg );
6808 %}
6810 // Store Long to Integer
6811 instruct storeL2I(memory mem, eRegL src) %{
6812 match(Set mem (StoreI mem (ConvL2I src)));
6814 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6815 ins_encode %{
6816 __ movl($mem$$Address, $src$$Register);
6817 %}
6818 ins_pipe(ialu_mem_reg);
6819 %}
6821 // Volatile Store Long. Must be atomic, so move it into
6822 // the FP TOS and then do a 64-bit FIST. Has to probe the
6823 // target address before the store (for null-ptr checks)
6824 // so the memory operand is used twice in the encoding.
6825 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6826 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6827 match(Set mem (StoreL mem src));
6828 effect( KILL cr );
6829 ins_cost(400);
6830 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6831 "FILD $src\n\t"
6832 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6833 opcode(0x3B);
6834 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6835 ins_pipe( fpu_reg_mem );
6836 %}
6838 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6839 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6840 match(Set mem (StoreL mem src));
6841 effect( TEMP tmp, KILL cr );
6842 ins_cost(380);
6843 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6844 "MOVSD $tmp,$src\n\t"
6845 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6846 ins_encode %{
6847 __ cmpl(rax, $mem$$Address);
6848 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6849 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6850 %}
6851 ins_pipe( pipe_slow );
6852 %}
6854 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6855 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6856 match(Set mem (StoreL mem src));
6857 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6858 ins_cost(360);
6859 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6860 "MOVD $tmp,$src.lo\n\t"
6861 "MOVD $tmp2,$src.hi\n\t"
6862 "PUNPCKLDQ $tmp,$tmp2\n\t"
6863 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6864 ins_encode %{
6865 __ cmpl(rax, $mem$$Address);
6866 __ movdl($tmp$$XMMRegister, $src$$Register);
6867 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6868 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6869 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6870 %}
6871 ins_pipe( pipe_slow );
6872 %}
6874 // Store Pointer; for storing unknown oops and raw pointers
6875 instruct storeP(memory mem, anyRegP src) %{
6876 match(Set mem (StoreP mem src));
6878 ins_cost(125);
6879 format %{ "MOV $mem,$src" %}
6880 opcode(0x89);
6881 ins_encode( OpcP, RegMem( src, mem ) );
6882 ins_pipe( ialu_mem_reg );
6883 %}
6885 // Store Integer Immediate
6886 instruct storeImmI(memory mem, immI src) %{
6887 match(Set mem (StoreI mem src));
6889 ins_cost(150);
6890 format %{ "MOV $mem,$src" %}
6891 opcode(0xC7); /* C7 /0 */
6892 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6893 ins_pipe( ialu_mem_imm );
6894 %}
6896 // Store Short/Char Immediate
6897 instruct storeImmI16(memory mem, immI16 src) %{
6898 predicate(UseStoreImmI16);
6899 match(Set mem (StoreC mem src));
6901 ins_cost(150);
6902 format %{ "MOV16 $mem,$src" %}
6903 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6904 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6905 ins_pipe( ialu_mem_imm );
6906 %}
6908 // Store Pointer Immediate; null pointers or constant oops that do not
6909 // need card-mark barriers.
6910 instruct storeImmP(memory mem, immP src) %{
6911 match(Set mem (StoreP mem src));
6913 ins_cost(150);
6914 format %{ "MOV $mem,$src" %}
6915 opcode(0xC7); /* C7 /0 */
6916 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6917 ins_pipe( ialu_mem_imm );
6918 %}
6920 // Store Byte Immediate
6921 instruct storeImmB(memory mem, immI8 src) %{
6922 match(Set mem (StoreB mem src));
6924 ins_cost(150);
6925 format %{ "MOV8 $mem,$src" %}
6926 opcode(0xC6); /* C6 /0 */
6927 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6928 ins_pipe( ialu_mem_imm );
6929 %}
6931 // Store CMS card-mark Immediate
6932 instruct storeImmCM(memory mem, immI8 src) %{
6933 match(Set mem (StoreCM mem src));
6935 ins_cost(150);
6936 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6937 opcode(0xC6); /* C6 /0 */
6938 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6939 ins_pipe( ialu_mem_imm );
6940 %}
6942 // Store Double
6943 instruct storeDPR( memory mem, regDPR1 src) %{
6944 predicate(UseSSE<=1);
6945 match(Set mem (StoreD mem src));
6947 ins_cost(100);
6948 format %{ "FST_D $mem,$src" %}
6949 opcode(0xDD); /* DD /2 */
6950 ins_encode( enc_FPR_store(mem,src) );
6951 ins_pipe( fpu_mem_reg );
6952 %}
6954 // Store double does rounding on x86
6955 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6956 predicate(UseSSE<=1);
6957 match(Set mem (StoreD mem (RoundDouble src)));
6959 ins_cost(100);
6960 format %{ "FST_D $mem,$src\t# round" %}
6961 opcode(0xDD); /* DD /2 */
6962 ins_encode( enc_FPR_store(mem,src) );
6963 ins_pipe( fpu_mem_reg );
6964 %}
6966 // Store XMM register to memory (double-precision floating points)
6967 // MOVSD instruction
6968 instruct storeD(memory mem, regD src) %{
6969 predicate(UseSSE>=2);
6970 match(Set mem (StoreD mem src));
6971 ins_cost(95);
6972 format %{ "MOVSD $mem,$src" %}
6973 ins_encode %{
6974 __ movdbl($mem$$Address, $src$$XMMRegister);
6975 %}
6976 ins_pipe( pipe_slow );
6977 %}
6979 // Store XMM register to memory (single-precision floating point)
6980 // MOVSS instruction
6981 instruct storeF(memory mem, regF src) %{
6982 predicate(UseSSE>=1);
6983 match(Set mem (StoreF mem src));
6984 ins_cost(95);
6985 format %{ "MOVSS $mem,$src" %}
6986 ins_encode %{
6987 __ movflt($mem$$Address, $src$$XMMRegister);
6988 %}
6989 ins_pipe( pipe_slow );
6990 %}
6992 // Store Float
6993 instruct storeFPR( memory mem, regFPR1 src) %{
6994 predicate(UseSSE==0);
6995 match(Set mem (StoreF mem src));
6997 ins_cost(100);
6998 format %{ "FST_S $mem,$src" %}
6999 opcode(0xD9); /* D9 /2 */
7000 ins_encode( enc_FPR_store(mem,src) );
7001 ins_pipe( fpu_mem_reg );
7002 %}
7004 // Store Float does rounding on x86
7005 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7006 predicate(UseSSE==0);
7007 match(Set mem (StoreF mem (RoundFloat src)));
7009 ins_cost(100);
7010 format %{ "FST_S $mem,$src\t# round" %}
7011 opcode(0xD9); /* D9 /2 */
7012 ins_encode( enc_FPR_store(mem,src) );
7013 ins_pipe( fpu_mem_reg );
7014 %}
7016 // Store Float does rounding on x86
7017 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7018 predicate(UseSSE<=1);
7019 match(Set mem (StoreF mem (ConvD2F src)));
7021 ins_cost(100);
7022 format %{ "FST_S $mem,$src\t# D-round" %}
7023 opcode(0xD9); /* D9 /2 */
7024 ins_encode( enc_FPR_store(mem,src) );
7025 ins_pipe( fpu_mem_reg );
7026 %}
7028 // Store immediate Float value (it is faster than store from FPU register)
7029 // The instruction usage is guarded by predicate in operand immFPR().
7030 instruct storeFPR_imm( memory mem, immFPR src) %{
7031 match(Set mem (StoreF mem src));
7033 ins_cost(50);
7034 format %{ "MOV $mem,$src\t# store float" %}
7035 opcode(0xC7); /* C7 /0 */
7036 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
7037 ins_pipe( ialu_mem_imm );
7038 %}
7040 // Store immediate Float value (it is faster than store from XMM register)
7041 // The instruction usage is guarded by predicate in operand immF().
7042 instruct storeF_imm( memory mem, immF src) %{
7043 match(Set mem (StoreF mem src));
7045 ins_cost(50);
7046 format %{ "MOV $mem,$src\t# store float" %}
7047 opcode(0xC7); /* C7 /0 */
7048 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7049 ins_pipe( ialu_mem_imm );
7050 %}
7052 // Store Integer to stack slot
7053 instruct storeSSI(stackSlotI dst, rRegI src) %{
7054 match(Set dst src);
7056 ins_cost(100);
7057 format %{ "MOV $dst,$src" %}
7058 opcode(0x89);
7059 ins_encode( OpcPRegSS( dst, src ) );
7060 ins_pipe( ialu_mem_reg );
7061 %}
7063 // Store Integer to stack slot
7064 instruct storeSSP(stackSlotP dst, eRegP src) %{
7065 match(Set dst src);
7067 ins_cost(100);
7068 format %{ "MOV $dst,$src" %}
7069 opcode(0x89);
7070 ins_encode( OpcPRegSS( dst, src ) );
7071 ins_pipe( ialu_mem_reg );
7072 %}
7074 // Store Long to stack slot
7075 instruct storeSSL(stackSlotL dst, eRegL src) %{
7076 match(Set dst src);
7078 ins_cost(200);
7079 format %{ "MOV $dst,$src.lo\n\t"
7080 "MOV $dst+4,$src.hi" %}
7081 opcode(0x89, 0x89);
7082 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7083 ins_pipe( ialu_mem_long_reg );
7084 %}
7086 //----------MemBar Instructions-----------------------------------------------
7087 // Memory barrier flavors
7089 instruct membar_acquire() %{
7090 match(MemBarAcquire);
7091 ins_cost(400);
7093 size(0);
7094 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7095 ins_encode();
7096 ins_pipe(empty);
7097 %}
7099 instruct membar_acquire_lock() %{
7100 match(MemBarAcquireLock);
7101 ins_cost(0);
7103 size(0);
7104 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7105 ins_encode( );
7106 ins_pipe(empty);
7107 %}
7109 instruct membar_release() %{
7110 match(MemBarRelease);
7111 ins_cost(400);
7113 size(0);
7114 format %{ "MEMBAR-release ! (empty encoding)" %}
7115 ins_encode( );
7116 ins_pipe(empty);
7117 %}
7119 instruct membar_release_lock() %{
7120 match(MemBarReleaseLock);
7121 ins_cost(0);
7123 size(0);
7124 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7125 ins_encode( );
7126 ins_pipe(empty);
7127 %}
7129 instruct membar_volatile(eFlagsReg cr) %{
7130 match(MemBarVolatile);
7131 effect(KILL cr);
7132 ins_cost(400);
7134 format %{
7135 $$template
7136 if (os::is_MP()) {
7137 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7138 } else {
7139 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7140 }
7141 %}
7142 ins_encode %{
7143 __ membar(Assembler::StoreLoad);
7144 %}
7145 ins_pipe(pipe_slow);
7146 %}
7148 instruct unnecessary_membar_volatile() %{
7149 match(MemBarVolatile);
7150 predicate(Matcher::post_store_load_barrier(n));
7151 ins_cost(0);
7153 size(0);
7154 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7155 ins_encode( );
7156 ins_pipe(empty);
7157 %}
7159 instruct membar_storestore() %{
7160 match(MemBarStoreStore);
7161 ins_cost(0);
7163 size(0);
7164 format %{ "MEMBAR-storestore (empty encoding)" %}
7165 ins_encode( );
7166 ins_pipe(empty);
7167 %}
7169 //----------Move Instructions--------------------------------------------------
7170 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7171 match(Set dst (CastX2P src));
7172 format %{ "# X2P $dst, $src" %}
7173 ins_encode( /*empty encoding*/ );
7174 ins_cost(0);
7175 ins_pipe(empty);
7176 %}
7178 instruct castP2X(rRegI dst, eRegP src ) %{
7179 match(Set dst (CastP2X src));
7180 ins_cost(50);
7181 format %{ "MOV $dst, $src\t# CastP2X" %}
7182 ins_encode( enc_Copy( dst, src) );
7183 ins_pipe( ialu_reg_reg );
7184 %}
7186 //----------Conditional Move---------------------------------------------------
7187 // Conditional move
7188 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
7189 predicate(!VM_Version::supports_cmov() );
7190 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7191 ins_cost(200);
7192 format %{ "J$cop,us skip\t# signed cmove\n\t"
7193 "MOV $dst,$src\n"
7194 "skip:" %}
7195 ins_encode %{
7196 Label Lskip;
7197 // Invert sense of branch from sense of CMOV
7198 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7199 __ movl($dst$$Register, $src$$Register);
7200 __ bind(Lskip);
7201 %}
7202 ins_pipe( pipe_cmov_reg );
7203 %}
7205 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
7206 predicate(!VM_Version::supports_cmov() );
7207 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7208 ins_cost(200);
7209 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7210 "MOV $dst,$src\n"
7211 "skip:" %}
7212 ins_encode %{
7213 Label Lskip;
7214 // Invert sense of branch from sense of CMOV
7215 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7216 __ movl($dst$$Register, $src$$Register);
7217 __ bind(Lskip);
7218 %}
7219 ins_pipe( pipe_cmov_reg );
7220 %}
7222 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
7223 predicate(VM_Version::supports_cmov() );
7224 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7225 ins_cost(200);
7226 format %{ "CMOV$cop $dst,$src" %}
7227 opcode(0x0F,0x40);
7228 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7229 ins_pipe( pipe_cmov_reg );
7230 %}
7232 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
7233 predicate(VM_Version::supports_cmov() );
7234 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7235 ins_cost(200);
7236 format %{ "CMOV$cop $dst,$src" %}
7237 opcode(0x0F,0x40);
7238 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7239 ins_pipe( pipe_cmov_reg );
7240 %}
7242 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
7243 predicate(VM_Version::supports_cmov() );
7244 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7245 ins_cost(200);
7246 expand %{
7247 cmovI_regU(cop, cr, dst, src);
7248 %}
7249 %}
7251 // Conditional move
7252 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
7253 predicate(VM_Version::supports_cmov() );
7254 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7255 ins_cost(250);
7256 format %{ "CMOV$cop $dst,$src" %}
7257 opcode(0x0F,0x40);
7258 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7259 ins_pipe( pipe_cmov_mem );
7260 %}
7262 // Conditional move
7263 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
7264 predicate(VM_Version::supports_cmov() );
7265 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7266 ins_cost(250);
7267 format %{ "CMOV$cop $dst,$src" %}
7268 opcode(0x0F,0x40);
7269 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7270 ins_pipe( pipe_cmov_mem );
7271 %}
7273 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
7274 predicate(VM_Version::supports_cmov() );
7275 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7276 ins_cost(250);
7277 expand %{
7278 cmovI_memU(cop, cr, dst, src);
7279 %}
7280 %}
7282 // Conditional move
7283 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7284 predicate(VM_Version::supports_cmov() );
7285 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7286 ins_cost(200);
7287 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7288 opcode(0x0F,0x40);
7289 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7290 ins_pipe( pipe_cmov_reg );
7291 %}
7293 // Conditional move (non-P6 version)
7294 // Note: a CMoveP is generated for stubs and native wrappers
7295 // regardless of whether we are on a P6, so we
7296 // emulate a cmov here
7297 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7298 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7299 ins_cost(300);
7300 format %{ "Jn$cop skip\n\t"
7301 "MOV $dst,$src\t# pointer\n"
7302 "skip:" %}
7303 opcode(0x8b);
7304 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7305 ins_pipe( pipe_cmov_reg );
7306 %}
7308 // Conditional move
7309 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7310 predicate(VM_Version::supports_cmov() );
7311 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7312 ins_cost(200);
7313 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7314 opcode(0x0F,0x40);
7315 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7316 ins_pipe( pipe_cmov_reg );
7317 %}
7319 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7320 predicate(VM_Version::supports_cmov() );
7321 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7322 ins_cost(200);
7323 expand %{
7324 cmovP_regU(cop, cr, dst, src);
7325 %}
7326 %}
7328 // DISABLED: Requires the ADLC to emit a bottom_type call that
7329 // correctly meets the two pointer arguments; one is an incoming
7330 // register but the other is a memory operand. ALSO appears to
7331 // be buggy with implicit null checks.
7332 //
7333 //// Conditional move
7334 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7335 // predicate(VM_Version::supports_cmov() );
7336 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7337 // ins_cost(250);
7338 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7339 // opcode(0x0F,0x40);
7340 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7341 // ins_pipe( pipe_cmov_mem );
7342 //%}
7343 //
7344 //// Conditional move
7345 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7346 // predicate(VM_Version::supports_cmov() );
7347 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7348 // ins_cost(250);
7349 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7350 // opcode(0x0F,0x40);
7351 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7352 // ins_pipe( pipe_cmov_mem );
7353 //%}
7355 // Conditional move
7356 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7357 predicate(UseSSE<=1);
7358 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7359 ins_cost(200);
7360 format %{ "FCMOV$cop $dst,$src\t# double" %}
7361 opcode(0xDA);
7362 ins_encode( enc_cmov_dpr(cop,src) );
7363 ins_pipe( pipe_cmovDPR_reg );
7364 %}
7366 // Conditional move
7367 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7368 predicate(UseSSE==0);
7369 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7370 ins_cost(200);
7371 format %{ "FCMOV$cop $dst,$src\t# float" %}
7372 opcode(0xDA);
7373 ins_encode( enc_cmov_dpr(cop,src) );
7374 ins_pipe( pipe_cmovDPR_reg );
7375 %}
7377 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7378 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7379 predicate(UseSSE<=1);
7380 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7381 ins_cost(200);
7382 format %{ "Jn$cop skip\n\t"
7383 "MOV $dst,$src\t# double\n"
7384 "skip:" %}
7385 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7386 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7387 ins_pipe( pipe_cmovDPR_reg );
7388 %}
7390 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7391 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7392 predicate(UseSSE==0);
7393 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7394 ins_cost(200);
7395 format %{ "Jn$cop skip\n\t"
7396 "MOV $dst,$src\t# float\n"
7397 "skip:" %}
7398 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7399 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7400 ins_pipe( pipe_cmovDPR_reg );
7401 %}
7403 // No CMOVE with SSE/SSE2
7404 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7405 predicate (UseSSE>=1);
7406 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7407 ins_cost(200);
7408 format %{ "Jn$cop skip\n\t"
7409 "MOVSS $dst,$src\t# float\n"
7410 "skip:" %}
7411 ins_encode %{
7412 Label skip;
7413 // Invert sense of branch from sense of CMOV
7414 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7415 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7416 __ bind(skip);
7417 %}
7418 ins_pipe( pipe_slow );
7419 %}
7421 // No CMOVE with SSE/SSE2
7422 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7423 predicate (UseSSE>=2);
7424 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7425 ins_cost(200);
7426 format %{ "Jn$cop skip\n\t"
7427 "MOVSD $dst,$src\t# float\n"
7428 "skip:" %}
7429 ins_encode %{
7430 Label skip;
7431 // Invert sense of branch from sense of CMOV
7432 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7433 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7434 __ bind(skip);
7435 %}
7436 ins_pipe( pipe_slow );
7437 %}
7439 // unsigned version
7440 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7441 predicate (UseSSE>=1);
7442 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7443 ins_cost(200);
7444 format %{ "Jn$cop skip\n\t"
7445 "MOVSS $dst,$src\t# float\n"
7446 "skip:" %}
7447 ins_encode %{
7448 Label skip;
7449 // Invert sense of branch from sense of CMOV
7450 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7451 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7452 __ bind(skip);
7453 %}
7454 ins_pipe( pipe_slow );
7455 %}
7457 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7458 predicate (UseSSE>=1);
7459 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7460 ins_cost(200);
7461 expand %{
7462 fcmovF_regU(cop, cr, dst, src);
7463 %}
7464 %}
7466 // unsigned version
7467 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7468 predicate (UseSSE>=2);
7469 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7470 ins_cost(200);
7471 format %{ "Jn$cop skip\n\t"
7472 "MOVSD $dst,$src\t# float\n"
7473 "skip:" %}
7474 ins_encode %{
7475 Label skip;
7476 // Invert sense of branch from sense of CMOV
7477 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7478 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7479 __ bind(skip);
7480 %}
7481 ins_pipe( pipe_slow );
7482 %}
7484 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7485 predicate (UseSSE>=2);
7486 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7487 ins_cost(200);
7488 expand %{
7489 fcmovD_regU(cop, cr, dst, src);
7490 %}
7491 %}
7493 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7494 predicate(VM_Version::supports_cmov() );
7495 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7496 ins_cost(200);
7497 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7498 "CMOV$cop $dst.hi,$src.hi" %}
7499 opcode(0x0F,0x40);
7500 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7501 ins_pipe( pipe_cmov_reg_long );
7502 %}
7504 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7505 predicate(VM_Version::supports_cmov() );
7506 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7507 ins_cost(200);
7508 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7509 "CMOV$cop $dst.hi,$src.hi" %}
7510 opcode(0x0F,0x40);
7511 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7512 ins_pipe( pipe_cmov_reg_long );
7513 %}
7515 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7516 predicate(VM_Version::supports_cmov() );
7517 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7518 ins_cost(200);
7519 expand %{
7520 cmovL_regU(cop, cr, dst, src);
7521 %}
7522 %}
7524 //----------Arithmetic Instructions--------------------------------------------
7525 //----------Addition Instructions----------------------------------------------
7527 instruct addExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7528 %{
7529 match(AddExactI dst src);
7530 effect(DEF cr);
7532 format %{ "ADD $dst, $src\t# addExact int" %}
7533 ins_encode %{
7534 __ addl($dst$$Register, $src$$Register);
7535 %}
7536 ins_pipe(ialu_reg_reg);
7537 %}
7539 instruct addExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
7540 %{
7541 match(AddExactI dst src);
7542 effect(DEF cr);
7544 format %{ "ADD $dst, $src\t# addExact int" %}
7545 ins_encode %{
7546 __ addl($dst$$Register, $src$$constant);
7547 %}
7548 ins_pipe(ialu_reg_reg);
7549 %}
7551 instruct addExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
7552 %{
7553 match(AddExactI dst (LoadI src));
7554 effect(DEF cr);
7556 ins_cost(125);
7557 format %{ "ADD $dst,$src\t# addExact int" %}
7558 ins_encode %{
7559 __ addl($dst$$Register, $src$$Address);
7560 %}
7561 ins_pipe( ialu_reg_mem );
7562 %}
7565 // Integer Addition Instructions
7566 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7567 match(Set dst (AddI dst src));
7568 effect(KILL cr);
7570 size(2);
7571 format %{ "ADD $dst,$src" %}
7572 opcode(0x03);
7573 ins_encode( OpcP, RegReg( dst, src) );
7574 ins_pipe( ialu_reg_reg );
7575 %}
7577 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7578 match(Set dst (AddI dst src));
7579 effect(KILL cr);
7581 format %{ "ADD $dst,$src" %}
7582 opcode(0x81, 0x00); /* /0 id */
7583 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7584 ins_pipe( ialu_reg );
7585 %}
7587 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7588 predicate(UseIncDec);
7589 match(Set dst (AddI dst src));
7590 effect(KILL cr);
7592 size(1);
7593 format %{ "INC $dst" %}
7594 opcode(0x40); /* */
7595 ins_encode( Opc_plus( primary, dst ) );
7596 ins_pipe( ialu_reg );
7597 %}
7599 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7600 match(Set dst (AddI src0 src1));
7601 ins_cost(110);
7603 format %{ "LEA $dst,[$src0 + $src1]" %}
7604 opcode(0x8D); /* 0x8D /r */
7605 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7606 ins_pipe( ialu_reg_reg );
7607 %}
7609 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7610 match(Set dst (AddP src0 src1));
7611 ins_cost(110);
7613 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7614 opcode(0x8D); /* 0x8D /r */
7615 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7616 ins_pipe( ialu_reg_reg );
7617 %}
7619 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7620 predicate(UseIncDec);
7621 match(Set dst (AddI dst src));
7622 effect(KILL cr);
7624 size(1);
7625 format %{ "DEC $dst" %}
7626 opcode(0x48); /* */
7627 ins_encode( Opc_plus( primary, dst ) );
7628 ins_pipe( ialu_reg );
7629 %}
7631 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7632 match(Set dst (AddP dst src));
7633 effect(KILL cr);
7635 size(2);
7636 format %{ "ADD $dst,$src" %}
7637 opcode(0x03);
7638 ins_encode( OpcP, RegReg( dst, src) );
7639 ins_pipe( ialu_reg_reg );
7640 %}
7642 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7643 match(Set dst (AddP dst src));
7644 effect(KILL cr);
7646 format %{ "ADD $dst,$src" %}
7647 opcode(0x81,0x00); /* Opcode 81 /0 id */
7648 // ins_encode( RegImm( dst, src) );
7649 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7650 ins_pipe( ialu_reg );
7651 %}
7653 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7654 match(Set dst (AddI dst (LoadI src)));
7655 effect(KILL cr);
7657 ins_cost(125);
7658 format %{ "ADD $dst,$src" %}
7659 opcode(0x03);
7660 ins_encode( OpcP, RegMem( dst, src) );
7661 ins_pipe( ialu_reg_mem );
7662 %}
7664 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7665 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7666 effect(KILL cr);
7668 ins_cost(150);
7669 format %{ "ADD $dst,$src" %}
7670 opcode(0x01); /* Opcode 01 /r */
7671 ins_encode( OpcP, RegMem( src, dst ) );
7672 ins_pipe( ialu_mem_reg );
7673 %}
7675 // Add Memory with Immediate
7676 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7677 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7678 effect(KILL cr);
7680 ins_cost(125);
7681 format %{ "ADD $dst,$src" %}
7682 opcode(0x81); /* Opcode 81 /0 id */
7683 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7684 ins_pipe( ialu_mem_imm );
7685 %}
7687 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7688 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7689 effect(KILL cr);
7691 ins_cost(125);
7692 format %{ "INC $dst" %}
7693 opcode(0xFF); /* Opcode FF /0 */
7694 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7695 ins_pipe( ialu_mem_imm );
7696 %}
7698 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7699 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7700 effect(KILL cr);
7702 ins_cost(125);
7703 format %{ "DEC $dst" %}
7704 opcode(0xFF); /* Opcode FF /1 */
7705 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7706 ins_pipe( ialu_mem_imm );
7707 %}
7710 instruct checkCastPP( eRegP dst ) %{
7711 match(Set dst (CheckCastPP dst));
7713 size(0);
7714 format %{ "#checkcastPP of $dst" %}
7715 ins_encode( /*empty encoding*/ );
7716 ins_pipe( empty );
7717 %}
7719 instruct castPP( eRegP dst ) %{
7720 match(Set dst (CastPP dst));
7721 format %{ "#castPP of $dst" %}
7722 ins_encode( /*empty encoding*/ );
7723 ins_pipe( empty );
7724 %}
7726 instruct castII( rRegI dst ) %{
7727 match(Set dst (CastII dst));
7728 format %{ "#castII of $dst" %}
7729 ins_encode( /*empty encoding*/ );
7730 ins_cost(0);
7731 ins_pipe( empty );
7732 %}
7735 // Load-locked - same as a regular pointer load when used with compare-swap
7736 instruct loadPLocked(eRegP dst, memory mem) %{
7737 match(Set dst (LoadPLocked mem));
7739 ins_cost(125);
7740 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7741 opcode(0x8B);
7742 ins_encode( OpcP, RegMem(dst,mem));
7743 ins_pipe( ialu_reg_mem );
7744 %}
7746 // Conditional-store of the updated heap-top.
7747 // Used during allocation of the shared heap.
7748 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7749 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7750 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7751 // EAX is killed if there is contention, but then it's also unused.
7752 // In the common case of no contention, EAX holds the new oop address.
7753 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7754 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7755 ins_pipe( pipe_cmpxchg );
7756 %}
7758 // Conditional-store of an int value.
7759 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7760 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7761 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7762 effect(KILL oldval);
7763 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7764 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7765 ins_pipe( pipe_cmpxchg );
7766 %}
7768 // Conditional-store of a long value.
7769 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7770 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7771 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7772 effect(KILL oldval);
7773 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7774 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7775 "XCHG EBX,ECX"
7776 %}
7777 ins_encode %{
7778 // Note: we need to swap rbx, and rcx before and after the
7779 // cmpxchg8 instruction because the instruction uses
7780 // rcx as the high order word of the new value to store but
7781 // our register encoding uses rbx.
7782 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7783 if( os::is_MP() )
7784 __ lock();
7785 __ cmpxchg8($mem$$Address);
7786 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7787 %}
7788 ins_pipe( pipe_cmpxchg );
7789 %}
7791 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7793 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7794 predicate(VM_Version::supports_cx8());
7795 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7796 effect(KILL cr, KILL oldval);
7797 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7798 "MOV $res,0\n\t"
7799 "JNE,s fail\n\t"
7800 "MOV $res,1\n"
7801 "fail:" %}
7802 ins_encode( enc_cmpxchg8(mem_ptr),
7803 enc_flags_ne_to_boolean(res) );
7804 ins_pipe( pipe_cmpxchg );
7805 %}
7807 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7808 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7809 effect(KILL cr, KILL oldval);
7810 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7811 "MOV $res,0\n\t"
7812 "JNE,s fail\n\t"
7813 "MOV $res,1\n"
7814 "fail:" %}
7815 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7816 ins_pipe( pipe_cmpxchg );
7817 %}
7819 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7820 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7821 effect(KILL cr, KILL oldval);
7822 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7823 "MOV $res,0\n\t"
7824 "JNE,s fail\n\t"
7825 "MOV $res,1\n"
7826 "fail:" %}
7827 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7828 ins_pipe( pipe_cmpxchg );
7829 %}
7831 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7832 predicate(n->as_LoadStore()->result_not_used());
7833 match(Set dummy (GetAndAddI mem add));
7834 effect(KILL cr);
7835 format %{ "ADDL [$mem],$add" %}
7836 ins_encode %{
7837 if (os::is_MP()) { __ lock(); }
7838 __ addl($mem$$Address, $add$$constant);
7839 %}
7840 ins_pipe( pipe_cmpxchg );
7841 %}
7843 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7844 match(Set newval (GetAndAddI mem newval));
7845 effect(KILL cr);
7846 format %{ "XADDL [$mem],$newval" %}
7847 ins_encode %{
7848 if (os::is_MP()) { __ lock(); }
7849 __ xaddl($mem$$Address, $newval$$Register);
7850 %}
7851 ins_pipe( pipe_cmpxchg );
7852 %}
7854 instruct xchgI( memory mem, rRegI newval) %{
7855 match(Set newval (GetAndSetI mem newval));
7856 format %{ "XCHGL $newval,[$mem]" %}
7857 ins_encode %{
7858 __ xchgl($newval$$Register, $mem$$Address);
7859 %}
7860 ins_pipe( pipe_cmpxchg );
7861 %}
7863 instruct xchgP( memory mem, pRegP newval) %{
7864 match(Set newval (GetAndSetP mem newval));
7865 format %{ "XCHGL $newval,[$mem]" %}
7866 ins_encode %{
7867 __ xchgl($newval$$Register, $mem$$Address);
7868 %}
7869 ins_pipe( pipe_cmpxchg );
7870 %}
7872 //----------Subtraction Instructions-------------------------------------------
7874 instruct subExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7875 %{
7876 match(SubExactI dst src);
7877 effect(DEF cr);
7879 format %{ "SUB $dst, $src\t# subExact int" %}
7880 ins_encode %{
7881 __ subl($dst$$Register, $src$$Register);
7882 %}
7883 ins_pipe(ialu_reg_reg);
7884 %}
7886 instruct subExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
7887 %{
7888 match(SubExactI dst src);
7889 effect(DEF cr);
7891 format %{ "SUB $dst, $src\t# subExact int" %}
7892 ins_encode %{
7893 __ subl($dst$$Register, $src$$constant);
7894 %}
7895 ins_pipe(ialu_reg_reg);
7896 %}
7898 instruct subExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
7899 %{
7900 match(SubExactI dst (LoadI src));
7901 effect(DEF cr);
7903 ins_cost(125);
7904 format %{ "SUB $dst,$src\t# subExact int" %}
7905 ins_encode %{
7906 __ subl($dst$$Register, $src$$Address);
7907 %}
7908 ins_pipe( ialu_reg_mem );
7909 %}
7911 // Integer Subtraction Instructions
7912 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7913 match(Set dst (SubI dst src));
7914 effect(KILL cr);
7916 size(2);
7917 format %{ "SUB $dst,$src" %}
7918 opcode(0x2B);
7919 ins_encode( OpcP, RegReg( dst, src) );
7920 ins_pipe( ialu_reg_reg );
7921 %}
7923 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7924 match(Set dst (SubI dst src));
7925 effect(KILL cr);
7927 format %{ "SUB $dst,$src" %}
7928 opcode(0x81,0x05); /* Opcode 81 /5 */
7929 // ins_encode( RegImm( dst, src) );
7930 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7931 ins_pipe( ialu_reg );
7932 %}
7934 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7935 match(Set dst (SubI dst (LoadI src)));
7936 effect(KILL cr);
7938 ins_cost(125);
7939 format %{ "SUB $dst,$src" %}
7940 opcode(0x2B);
7941 ins_encode( OpcP, RegMem( dst, src) );
7942 ins_pipe( ialu_reg_mem );
7943 %}
7945 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7946 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7947 effect(KILL cr);
7949 ins_cost(150);
7950 format %{ "SUB $dst,$src" %}
7951 opcode(0x29); /* Opcode 29 /r */
7952 ins_encode( OpcP, RegMem( src, dst ) );
7953 ins_pipe( ialu_mem_reg );
7954 %}
7956 // Subtract from a pointer
7957 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7958 match(Set dst (AddP dst (SubI zero src)));
7959 effect(KILL cr);
7961 size(2);
7962 format %{ "SUB $dst,$src" %}
7963 opcode(0x2B);
7964 ins_encode( OpcP, RegReg( dst, src) );
7965 ins_pipe( ialu_reg_reg );
7966 %}
7968 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7969 match(Set dst (SubI zero dst));
7970 effect(KILL cr);
7972 size(2);
7973 format %{ "NEG $dst" %}
7974 opcode(0xF7,0x03); // Opcode F7 /3
7975 ins_encode( OpcP, RegOpc( dst ) );
7976 ins_pipe( ialu_reg );
7977 %}
7979 instruct negExactI_eReg(eAXRegI dst, eFlagsReg cr) %{
7980 match(NegExactI dst);
7981 effect(DEF cr);
7983 format %{ "NEG $dst\t# negExact int"%}
7984 ins_encode %{
7985 __ negl($dst$$Register);
7986 %}
7987 ins_pipe(ialu_reg);
7988 %}
7990 //----------Multiplication/Division Instructions-------------------------------
7991 // Integer Multiplication Instructions
7992 // Multiply Register
7993 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7994 match(Set dst (MulI dst src));
7995 effect(KILL cr);
7997 size(3);
7998 ins_cost(300);
7999 format %{ "IMUL $dst,$src" %}
8000 opcode(0xAF, 0x0F);
8001 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8002 ins_pipe( ialu_reg_reg_alu0 );
8003 %}
8005 // Multiply 32-bit Immediate
8006 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
8007 match(Set dst (MulI src imm));
8008 effect(KILL cr);
8010 ins_cost(300);
8011 format %{ "IMUL $dst,$src,$imm" %}
8012 opcode(0x69); /* 69 /r id */
8013 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8014 ins_pipe( ialu_reg_reg_alu0 );
8015 %}
8017 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8018 match(Set dst src);
8019 effect(KILL cr);
8021 // Note that this is artificially increased to make it more expensive than loadConL
8022 ins_cost(250);
8023 format %{ "MOV EAX,$src\t// low word only" %}
8024 opcode(0xB8);
8025 ins_encode( LdImmL_Lo(dst, src) );
8026 ins_pipe( ialu_reg_fat );
8027 %}
8029 // Multiply by 32-bit Immediate, taking the shifted high order results
8030 // (special case for shift by 32)
8031 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8032 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8033 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8034 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8035 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8036 effect(USE src1, KILL cr);
8038 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8039 ins_cost(0*100 + 1*400 - 150);
8040 format %{ "IMUL EDX:EAX,$src1" %}
8041 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8042 ins_pipe( pipe_slow );
8043 %}
8045 // Multiply by 32-bit Immediate, taking the shifted high order results
8046 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8047 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8048 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8049 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8050 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8051 effect(USE src1, KILL cr);
8053 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8054 ins_cost(1*100 + 1*400 - 150);
8055 format %{ "IMUL EDX:EAX,$src1\n\t"
8056 "SAR EDX,$cnt-32" %}
8057 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8058 ins_pipe( pipe_slow );
8059 %}
8061 // Multiply Memory 32-bit Immediate
8062 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
8063 match(Set dst (MulI (LoadI src) imm));
8064 effect(KILL cr);
8066 ins_cost(300);
8067 format %{ "IMUL $dst,$src,$imm" %}
8068 opcode(0x69); /* 69 /r id */
8069 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8070 ins_pipe( ialu_reg_mem_alu0 );
8071 %}
8073 // Multiply Memory
8074 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
8075 match(Set dst (MulI dst (LoadI src)));
8076 effect(KILL cr);
8078 ins_cost(350);
8079 format %{ "IMUL $dst,$src" %}
8080 opcode(0xAF, 0x0F);
8081 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8082 ins_pipe( ialu_reg_mem_alu0 );
8083 %}
8085 // Multiply Register Int to Long
8086 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8087 // Basic Idea: long = (long)int * (long)int
8088 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8089 effect(DEF dst, USE src, USE src1, KILL flags);
8091 ins_cost(300);
8092 format %{ "IMUL $dst,$src1" %}
8094 ins_encode( long_int_multiply( dst, src1 ) );
8095 ins_pipe( ialu_reg_reg_alu0 );
8096 %}
8098 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8099 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8100 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8101 effect(KILL flags);
8103 ins_cost(300);
8104 format %{ "MUL $dst,$src1" %}
8106 ins_encode( long_uint_multiply(dst, src1) );
8107 ins_pipe( ialu_reg_reg_alu0 );
8108 %}
8110 // Multiply Register Long
8111 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8112 match(Set dst (MulL dst src));
8113 effect(KILL cr, TEMP tmp);
8114 ins_cost(4*100+3*400);
8115 // Basic idea: lo(result) = lo(x_lo * y_lo)
8116 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8117 format %{ "MOV $tmp,$src.lo\n\t"
8118 "IMUL $tmp,EDX\n\t"
8119 "MOV EDX,$src.hi\n\t"
8120 "IMUL EDX,EAX\n\t"
8121 "ADD $tmp,EDX\n\t"
8122 "MUL EDX:EAX,$src.lo\n\t"
8123 "ADD EDX,$tmp" %}
8124 ins_encode( long_multiply( dst, src, tmp ) );
8125 ins_pipe( pipe_slow );
8126 %}
8128 // Multiply Register Long where the left operand's high 32 bits are zero
8129 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8130 predicate(is_operand_hi32_zero(n->in(1)));
8131 match(Set dst (MulL dst src));
8132 effect(KILL cr, TEMP tmp);
8133 ins_cost(2*100+2*400);
8134 // Basic idea: lo(result) = lo(x_lo * y_lo)
8135 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8136 format %{ "MOV $tmp,$src.hi\n\t"
8137 "IMUL $tmp,EAX\n\t"
8138 "MUL EDX:EAX,$src.lo\n\t"
8139 "ADD EDX,$tmp" %}
8140 ins_encode %{
8141 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8142 __ imull($tmp$$Register, rax);
8143 __ mull($src$$Register);
8144 __ addl(rdx, $tmp$$Register);
8145 %}
8146 ins_pipe( pipe_slow );
8147 %}
8149 // Multiply Register Long where the right operand's high 32 bits are zero
8150 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8151 predicate(is_operand_hi32_zero(n->in(2)));
8152 match(Set dst (MulL dst src));
8153 effect(KILL cr, TEMP tmp);
8154 ins_cost(2*100+2*400);
8155 // Basic idea: lo(result) = lo(x_lo * y_lo)
8156 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8157 format %{ "MOV $tmp,$src.lo\n\t"
8158 "IMUL $tmp,EDX\n\t"
8159 "MUL EDX:EAX,$src.lo\n\t"
8160 "ADD EDX,$tmp" %}
8161 ins_encode %{
8162 __ movl($tmp$$Register, $src$$Register);
8163 __ imull($tmp$$Register, rdx);
8164 __ mull($src$$Register);
8165 __ addl(rdx, $tmp$$Register);
8166 %}
8167 ins_pipe( pipe_slow );
8168 %}
8170 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8171 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8172 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8173 match(Set dst (MulL dst src));
8174 effect(KILL cr);
8175 ins_cost(1*400);
8176 // Basic idea: lo(result) = lo(x_lo * y_lo)
8177 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8178 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8179 ins_encode %{
8180 __ mull($src$$Register);
8181 %}
8182 ins_pipe( pipe_slow );
8183 %}
8185 // Multiply Register Long by small constant
8186 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8187 match(Set dst (MulL dst src));
8188 effect(KILL cr, TEMP tmp);
8189 ins_cost(2*100+2*400);
8190 size(12);
8191 // Basic idea: lo(result) = lo(src * EAX)
8192 // hi(result) = hi(src * EAX) + lo(src * EDX)
8193 format %{ "IMUL $tmp,EDX,$src\n\t"
8194 "MOV EDX,$src\n\t"
8195 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8196 "ADD EDX,$tmp" %}
8197 ins_encode( long_multiply_con( dst, src, tmp ) );
8198 ins_pipe( pipe_slow );
8199 %}
8201 instruct mulExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
8202 %{
8203 match(MulExactI dst src);
8204 effect(DEF cr);
8206 ins_cost(300);
8207 format %{ "IMUL $dst, $src\t# mulExact int" %}
8208 ins_encode %{
8209 __ imull($dst$$Register, $src$$Register);
8210 %}
8211 ins_pipe(ialu_reg_reg_alu0);
8212 %}
8214 instruct mulExactI_eReg_imm(eAXRegI dst, rRegI src, immI imm, eFlagsReg cr)
8215 %{
8216 match(MulExactI src imm);
8217 effect(DEF cr);
8219 ins_cost(300);
8220 format %{ "IMUL $dst, $src, $imm\t# mulExact int" %}
8221 ins_encode %{
8222 __ imull($dst$$Register, $src$$Register, $imm$$constant);
8223 %}
8224 ins_pipe(ialu_reg_reg_alu0);
8225 %}
8227 instruct mulExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
8228 %{
8229 match(MulExactI dst (LoadI src));
8230 effect(DEF cr);
8232 ins_cost(350);
8233 format %{ "IMUL $dst, $src\t# mulExact int" %}
8234 ins_encode %{
8235 __ imull($dst$$Register, $src$$Address);
8236 %}
8237 ins_pipe(ialu_reg_mem_alu0);
8238 %}
8241 // Integer DIV with Register
8242 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8243 match(Set rax (DivI rax div));
8244 effect(KILL rdx, KILL cr);
8245 size(26);
8246 ins_cost(30*100+10*100);
8247 format %{ "CMP EAX,0x80000000\n\t"
8248 "JNE,s normal\n\t"
8249 "XOR EDX,EDX\n\t"
8250 "CMP ECX,-1\n\t"
8251 "JE,s done\n"
8252 "normal: CDQ\n\t"
8253 "IDIV $div\n\t"
8254 "done:" %}
8255 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8256 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8257 ins_pipe( ialu_reg_reg_alu0 );
8258 %}
8260 // Divide Register Long
8261 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8262 match(Set dst (DivL src1 src2));
8263 effect( KILL cr, KILL cx, KILL bx );
8264 ins_cost(10000);
8265 format %{ "PUSH $src1.hi\n\t"
8266 "PUSH $src1.lo\n\t"
8267 "PUSH $src2.hi\n\t"
8268 "PUSH $src2.lo\n\t"
8269 "CALL SharedRuntime::ldiv\n\t"
8270 "ADD ESP,16" %}
8271 ins_encode( long_div(src1,src2) );
8272 ins_pipe( pipe_slow );
8273 %}
8275 // Integer DIVMOD with Register, both quotient and mod results
8276 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8277 match(DivModI rax div);
8278 effect(KILL cr);
8279 size(26);
8280 ins_cost(30*100+10*100);
8281 format %{ "CMP EAX,0x80000000\n\t"
8282 "JNE,s normal\n\t"
8283 "XOR EDX,EDX\n\t"
8284 "CMP ECX,-1\n\t"
8285 "JE,s done\n"
8286 "normal: CDQ\n\t"
8287 "IDIV $div\n\t"
8288 "done:" %}
8289 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8290 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8291 ins_pipe( pipe_slow );
8292 %}
8294 // Integer MOD with Register
8295 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8296 match(Set rdx (ModI rax div));
8297 effect(KILL rax, KILL cr);
8299 size(26);
8300 ins_cost(300);
8301 format %{ "CDQ\n\t"
8302 "IDIV $div" %}
8303 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8304 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8305 ins_pipe( ialu_reg_reg_alu0 );
8306 %}
8308 // Remainder Register Long
8309 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8310 match(Set dst (ModL src1 src2));
8311 effect( KILL cr, KILL cx, KILL bx );
8312 ins_cost(10000);
8313 format %{ "PUSH $src1.hi\n\t"
8314 "PUSH $src1.lo\n\t"
8315 "PUSH $src2.hi\n\t"
8316 "PUSH $src2.lo\n\t"
8317 "CALL SharedRuntime::lrem\n\t"
8318 "ADD ESP,16" %}
8319 ins_encode( long_mod(src1,src2) );
8320 ins_pipe( pipe_slow );
8321 %}
8323 // Divide Register Long (no special case since divisor != -1)
8324 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8325 match(Set dst (DivL dst imm));
8326 effect( TEMP tmp, TEMP tmp2, KILL cr );
8327 ins_cost(1000);
8328 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8329 "XOR $tmp2,$tmp2\n\t"
8330 "CMP $tmp,EDX\n\t"
8331 "JA,s fast\n\t"
8332 "MOV $tmp2,EAX\n\t"
8333 "MOV EAX,EDX\n\t"
8334 "MOV EDX,0\n\t"
8335 "JLE,s pos\n\t"
8336 "LNEG EAX : $tmp2\n\t"
8337 "DIV $tmp # unsigned division\n\t"
8338 "XCHG EAX,$tmp2\n\t"
8339 "DIV $tmp\n\t"
8340 "LNEG $tmp2 : EAX\n\t"
8341 "JMP,s done\n"
8342 "pos:\n\t"
8343 "DIV $tmp\n\t"
8344 "XCHG EAX,$tmp2\n"
8345 "fast:\n\t"
8346 "DIV $tmp\n"
8347 "done:\n\t"
8348 "MOV EDX,$tmp2\n\t"
8349 "NEG EDX:EAX # if $imm < 0" %}
8350 ins_encode %{
8351 int con = (int)$imm$$constant;
8352 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8353 int pcon = (con > 0) ? con : -con;
8354 Label Lfast, Lpos, Ldone;
8356 __ movl($tmp$$Register, pcon);
8357 __ xorl($tmp2$$Register,$tmp2$$Register);
8358 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8359 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8361 __ movl($tmp2$$Register, $dst$$Register); // save
8362 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8363 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8364 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8366 // Negative dividend.
8367 // convert value to positive to use unsigned division
8368 __ lneg($dst$$Register, $tmp2$$Register);
8369 __ divl($tmp$$Register);
8370 __ xchgl($dst$$Register, $tmp2$$Register);
8371 __ divl($tmp$$Register);
8372 // revert result back to negative
8373 __ lneg($tmp2$$Register, $dst$$Register);
8374 __ jmpb(Ldone);
8376 __ bind(Lpos);
8377 __ divl($tmp$$Register); // Use unsigned division
8378 __ xchgl($dst$$Register, $tmp2$$Register);
8379 // Fallthrow for final divide, tmp2 has 32 bit hi result
8381 __ bind(Lfast);
8382 // fast path: src is positive
8383 __ divl($tmp$$Register); // Use unsigned division
8385 __ bind(Ldone);
8386 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8387 if (con < 0) {
8388 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8389 }
8390 %}
8391 ins_pipe( pipe_slow );
8392 %}
8394 // Remainder Register Long (remainder fit into 32 bits)
8395 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8396 match(Set dst (ModL dst imm));
8397 effect( TEMP tmp, TEMP tmp2, KILL cr );
8398 ins_cost(1000);
8399 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8400 "CMP $tmp,EDX\n\t"
8401 "JA,s fast\n\t"
8402 "MOV $tmp2,EAX\n\t"
8403 "MOV EAX,EDX\n\t"
8404 "MOV EDX,0\n\t"
8405 "JLE,s pos\n\t"
8406 "LNEG EAX : $tmp2\n\t"
8407 "DIV $tmp # unsigned division\n\t"
8408 "MOV EAX,$tmp2\n\t"
8409 "DIV $tmp\n\t"
8410 "NEG EDX\n\t"
8411 "JMP,s done\n"
8412 "pos:\n\t"
8413 "DIV $tmp\n\t"
8414 "MOV EAX,$tmp2\n"
8415 "fast:\n\t"
8416 "DIV $tmp\n"
8417 "done:\n\t"
8418 "MOV EAX,EDX\n\t"
8419 "SAR EDX,31\n\t" %}
8420 ins_encode %{
8421 int con = (int)$imm$$constant;
8422 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8423 int pcon = (con > 0) ? con : -con;
8424 Label Lfast, Lpos, Ldone;
8426 __ movl($tmp$$Register, pcon);
8427 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8428 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8430 __ movl($tmp2$$Register, $dst$$Register); // save
8431 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8432 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8433 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8435 // Negative dividend.
8436 // convert value to positive to use unsigned division
8437 __ lneg($dst$$Register, $tmp2$$Register);
8438 __ divl($tmp$$Register);
8439 __ movl($dst$$Register, $tmp2$$Register);
8440 __ divl($tmp$$Register);
8441 // revert remainder back to negative
8442 __ negl(HIGH_FROM_LOW($dst$$Register));
8443 __ jmpb(Ldone);
8445 __ bind(Lpos);
8446 __ divl($tmp$$Register);
8447 __ movl($dst$$Register, $tmp2$$Register);
8449 __ bind(Lfast);
8450 // fast path: src is positive
8451 __ divl($tmp$$Register);
8453 __ bind(Ldone);
8454 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8455 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8457 %}
8458 ins_pipe( pipe_slow );
8459 %}
8461 // Integer Shift Instructions
8462 // Shift Left by one
8463 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8464 match(Set dst (LShiftI dst shift));
8465 effect(KILL cr);
8467 size(2);
8468 format %{ "SHL $dst,$shift" %}
8469 opcode(0xD1, 0x4); /* D1 /4 */
8470 ins_encode( OpcP, RegOpc( dst ) );
8471 ins_pipe( ialu_reg );
8472 %}
8474 // Shift Left by 8-bit immediate
8475 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8476 match(Set dst (LShiftI dst shift));
8477 effect(KILL cr);
8479 size(3);
8480 format %{ "SHL $dst,$shift" %}
8481 opcode(0xC1, 0x4); /* C1 /4 ib */
8482 ins_encode( RegOpcImm( dst, shift) );
8483 ins_pipe( ialu_reg );
8484 %}
8486 // Shift Left by variable
8487 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8488 match(Set dst (LShiftI dst shift));
8489 effect(KILL cr);
8491 size(2);
8492 format %{ "SHL $dst,$shift" %}
8493 opcode(0xD3, 0x4); /* D3 /4 */
8494 ins_encode( OpcP, RegOpc( dst ) );
8495 ins_pipe( ialu_reg_reg );
8496 %}
8498 // Arithmetic shift right by one
8499 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8500 match(Set dst (RShiftI dst shift));
8501 effect(KILL cr);
8503 size(2);
8504 format %{ "SAR $dst,$shift" %}
8505 opcode(0xD1, 0x7); /* D1 /7 */
8506 ins_encode( OpcP, RegOpc( dst ) );
8507 ins_pipe( ialu_reg );
8508 %}
8510 // Arithmetic shift right by one
8511 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8512 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8513 effect(KILL cr);
8514 format %{ "SAR $dst,$shift" %}
8515 opcode(0xD1, 0x7); /* D1 /7 */
8516 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8517 ins_pipe( ialu_mem_imm );
8518 %}
8520 // Arithmetic Shift Right by 8-bit immediate
8521 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8522 match(Set dst (RShiftI dst shift));
8523 effect(KILL cr);
8525 size(3);
8526 format %{ "SAR $dst,$shift" %}
8527 opcode(0xC1, 0x7); /* C1 /7 ib */
8528 ins_encode( RegOpcImm( dst, shift ) );
8529 ins_pipe( ialu_mem_imm );
8530 %}
8532 // Arithmetic Shift Right by 8-bit immediate
8533 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8534 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8535 effect(KILL cr);
8537 format %{ "SAR $dst,$shift" %}
8538 opcode(0xC1, 0x7); /* C1 /7 ib */
8539 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8540 ins_pipe( ialu_mem_imm );
8541 %}
8543 // Arithmetic Shift Right by variable
8544 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8545 match(Set dst (RShiftI dst shift));
8546 effect(KILL cr);
8548 size(2);
8549 format %{ "SAR $dst,$shift" %}
8550 opcode(0xD3, 0x7); /* D3 /7 */
8551 ins_encode( OpcP, RegOpc( dst ) );
8552 ins_pipe( ialu_reg_reg );
8553 %}
8555 // Logical shift right by one
8556 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8557 match(Set dst (URShiftI dst shift));
8558 effect(KILL cr);
8560 size(2);
8561 format %{ "SHR $dst,$shift" %}
8562 opcode(0xD1, 0x5); /* D1 /5 */
8563 ins_encode( OpcP, RegOpc( dst ) );
8564 ins_pipe( ialu_reg );
8565 %}
8567 // Logical Shift Right by 8-bit immediate
8568 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8569 match(Set dst (URShiftI dst shift));
8570 effect(KILL cr);
8572 size(3);
8573 format %{ "SHR $dst,$shift" %}
8574 opcode(0xC1, 0x5); /* C1 /5 ib */
8575 ins_encode( RegOpcImm( dst, shift) );
8576 ins_pipe( ialu_reg );
8577 %}
8580 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8581 // This idiom is used by the compiler for the i2b bytecode.
8582 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
8583 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8585 size(3);
8586 format %{ "MOVSX $dst,$src :8" %}
8587 ins_encode %{
8588 __ movsbl($dst$$Register, $src$$Register);
8589 %}
8590 ins_pipe(ialu_reg_reg);
8591 %}
8593 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8594 // This idiom is used by the compiler the i2s bytecode.
8595 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
8596 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8598 size(3);
8599 format %{ "MOVSX $dst,$src :16" %}
8600 ins_encode %{
8601 __ movswl($dst$$Register, $src$$Register);
8602 %}
8603 ins_pipe(ialu_reg_reg);
8604 %}
8607 // Logical Shift Right by variable
8608 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8609 match(Set dst (URShiftI dst shift));
8610 effect(KILL cr);
8612 size(2);
8613 format %{ "SHR $dst,$shift" %}
8614 opcode(0xD3, 0x5); /* D3 /5 */
8615 ins_encode( OpcP, RegOpc( dst ) );
8616 ins_pipe( ialu_reg_reg );
8617 %}
8620 //----------Logical Instructions-----------------------------------------------
8621 //----------Integer Logical Instructions---------------------------------------
8622 // And Instructions
8623 // And Register with Register
8624 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8625 match(Set dst (AndI dst src));
8626 effect(KILL cr);
8628 size(2);
8629 format %{ "AND $dst,$src" %}
8630 opcode(0x23);
8631 ins_encode( OpcP, RegReg( dst, src) );
8632 ins_pipe( ialu_reg_reg );
8633 %}
8635 // And Register with Immediate
8636 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8637 match(Set dst (AndI dst src));
8638 effect(KILL cr);
8640 format %{ "AND $dst,$src" %}
8641 opcode(0x81,0x04); /* Opcode 81 /4 */
8642 // ins_encode( RegImm( dst, src) );
8643 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8644 ins_pipe( ialu_reg );
8645 %}
8647 // And Register with Memory
8648 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8649 match(Set dst (AndI dst (LoadI src)));
8650 effect(KILL cr);
8652 ins_cost(125);
8653 format %{ "AND $dst,$src" %}
8654 opcode(0x23);
8655 ins_encode( OpcP, RegMem( dst, src) );
8656 ins_pipe( ialu_reg_mem );
8657 %}
8659 // And Memory with Register
8660 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8661 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8662 effect(KILL cr);
8664 ins_cost(150);
8665 format %{ "AND $dst,$src" %}
8666 opcode(0x21); /* Opcode 21 /r */
8667 ins_encode( OpcP, RegMem( src, dst ) );
8668 ins_pipe( ialu_mem_reg );
8669 %}
8671 // And Memory with Immediate
8672 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8673 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8674 effect(KILL cr);
8676 ins_cost(125);
8677 format %{ "AND $dst,$src" %}
8678 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8679 // ins_encode( MemImm( dst, src) );
8680 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8681 ins_pipe( ialu_mem_imm );
8682 %}
8684 // Or Instructions
8685 // Or Register with Register
8686 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8687 match(Set dst (OrI dst src));
8688 effect(KILL cr);
8690 size(2);
8691 format %{ "OR $dst,$src" %}
8692 opcode(0x0B);
8693 ins_encode( OpcP, RegReg( dst, src) );
8694 ins_pipe( ialu_reg_reg );
8695 %}
8697 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8698 match(Set dst (OrI dst (CastP2X src)));
8699 effect(KILL cr);
8701 size(2);
8702 format %{ "OR $dst,$src" %}
8703 opcode(0x0B);
8704 ins_encode( OpcP, RegReg( dst, src) );
8705 ins_pipe( ialu_reg_reg );
8706 %}
8709 // Or Register with Immediate
8710 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8711 match(Set dst (OrI dst src));
8712 effect(KILL cr);
8714 format %{ "OR $dst,$src" %}
8715 opcode(0x81,0x01); /* Opcode 81 /1 id */
8716 // ins_encode( RegImm( dst, src) );
8717 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8718 ins_pipe( ialu_reg );
8719 %}
8721 // Or Register with Memory
8722 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8723 match(Set dst (OrI dst (LoadI src)));
8724 effect(KILL cr);
8726 ins_cost(125);
8727 format %{ "OR $dst,$src" %}
8728 opcode(0x0B);
8729 ins_encode( OpcP, RegMem( dst, src) );
8730 ins_pipe( ialu_reg_mem );
8731 %}
8733 // Or Memory with Register
8734 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8735 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8736 effect(KILL cr);
8738 ins_cost(150);
8739 format %{ "OR $dst,$src" %}
8740 opcode(0x09); /* Opcode 09 /r */
8741 ins_encode( OpcP, RegMem( src, dst ) );
8742 ins_pipe( ialu_mem_reg );
8743 %}
8745 // Or Memory with Immediate
8746 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8747 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8748 effect(KILL cr);
8750 ins_cost(125);
8751 format %{ "OR $dst,$src" %}
8752 opcode(0x81,0x1); /* Opcode 81 /1 id */
8753 // ins_encode( MemImm( dst, src) );
8754 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8755 ins_pipe( ialu_mem_imm );
8756 %}
8758 // ROL/ROR
8759 // ROL expand
8760 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8761 effect(USE_DEF dst, USE shift, KILL cr);
8763 format %{ "ROL $dst, $shift" %}
8764 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8765 ins_encode( OpcP, RegOpc( dst ));
8766 ins_pipe( ialu_reg );
8767 %}
8769 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8770 effect(USE_DEF dst, USE shift, KILL cr);
8772 format %{ "ROL $dst, $shift" %}
8773 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8774 ins_encode( RegOpcImm(dst, shift) );
8775 ins_pipe(ialu_reg);
8776 %}
8778 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8779 effect(USE_DEF dst, USE shift, KILL cr);
8781 format %{ "ROL $dst, $shift" %}
8782 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8783 ins_encode(OpcP, RegOpc(dst));
8784 ins_pipe( ialu_reg_reg );
8785 %}
8786 // end of ROL expand
8788 // ROL 32bit by one once
8789 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8790 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8792 expand %{
8793 rolI_eReg_imm1(dst, lshift, cr);
8794 %}
8795 %}
8797 // ROL 32bit var by imm8 once
8798 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8799 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8800 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8802 expand %{
8803 rolI_eReg_imm8(dst, lshift, cr);
8804 %}
8805 %}
8807 // ROL 32bit var by var once
8808 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8809 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8811 expand %{
8812 rolI_eReg_CL(dst, shift, cr);
8813 %}
8814 %}
8816 // ROL 32bit var by var once
8817 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8818 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8820 expand %{
8821 rolI_eReg_CL(dst, shift, cr);
8822 %}
8823 %}
8825 // ROR expand
8826 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8827 effect(USE_DEF dst, USE shift, KILL cr);
8829 format %{ "ROR $dst, $shift" %}
8830 opcode(0xD1,0x1); /* Opcode D1 /1 */
8831 ins_encode( OpcP, RegOpc( dst ) );
8832 ins_pipe( ialu_reg );
8833 %}
8835 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8836 effect (USE_DEF dst, USE shift, KILL cr);
8838 format %{ "ROR $dst, $shift" %}
8839 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8840 ins_encode( RegOpcImm(dst, shift) );
8841 ins_pipe( ialu_reg );
8842 %}
8844 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8845 effect(USE_DEF dst, USE shift, KILL cr);
8847 format %{ "ROR $dst, $shift" %}
8848 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8849 ins_encode(OpcP, RegOpc(dst));
8850 ins_pipe( ialu_reg_reg );
8851 %}
8852 // end of ROR expand
8854 // ROR right once
8855 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8856 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8858 expand %{
8859 rorI_eReg_imm1(dst, rshift, cr);
8860 %}
8861 %}
8863 // ROR 32bit by immI8 once
8864 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8865 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8866 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8868 expand %{
8869 rorI_eReg_imm8(dst, rshift, cr);
8870 %}
8871 %}
8873 // ROR 32bit var by var once
8874 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8875 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8877 expand %{
8878 rorI_eReg_CL(dst, shift, cr);
8879 %}
8880 %}
8882 // ROR 32bit var by var once
8883 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8884 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8886 expand %{
8887 rorI_eReg_CL(dst, shift, cr);
8888 %}
8889 %}
8891 // Xor Instructions
8892 // Xor Register with Register
8893 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8894 match(Set dst (XorI dst src));
8895 effect(KILL cr);
8897 size(2);
8898 format %{ "XOR $dst,$src" %}
8899 opcode(0x33);
8900 ins_encode( OpcP, RegReg( dst, src) );
8901 ins_pipe( ialu_reg_reg );
8902 %}
8904 // Xor Register with Immediate -1
8905 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8906 match(Set dst (XorI dst imm));
8908 size(2);
8909 format %{ "NOT $dst" %}
8910 ins_encode %{
8911 __ notl($dst$$Register);
8912 %}
8913 ins_pipe( ialu_reg );
8914 %}
8916 // Xor Register with Immediate
8917 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8918 match(Set dst (XorI dst src));
8919 effect(KILL cr);
8921 format %{ "XOR $dst,$src" %}
8922 opcode(0x81,0x06); /* Opcode 81 /6 id */
8923 // ins_encode( RegImm( dst, src) );
8924 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8925 ins_pipe( ialu_reg );
8926 %}
8928 // Xor Register with Memory
8929 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8930 match(Set dst (XorI dst (LoadI src)));
8931 effect(KILL cr);
8933 ins_cost(125);
8934 format %{ "XOR $dst,$src" %}
8935 opcode(0x33);
8936 ins_encode( OpcP, RegMem(dst, src) );
8937 ins_pipe( ialu_reg_mem );
8938 %}
8940 // Xor Memory with Register
8941 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8942 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8943 effect(KILL cr);
8945 ins_cost(150);
8946 format %{ "XOR $dst,$src" %}
8947 opcode(0x31); /* Opcode 31 /r */
8948 ins_encode( OpcP, RegMem( src, dst ) );
8949 ins_pipe( ialu_mem_reg );
8950 %}
8952 // Xor Memory with Immediate
8953 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8954 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8955 effect(KILL cr);
8957 ins_cost(125);
8958 format %{ "XOR $dst,$src" %}
8959 opcode(0x81,0x6); /* Opcode 81 /6 id */
8960 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8961 ins_pipe( ialu_mem_imm );
8962 %}
8964 //----------Convert Int to Boolean---------------------------------------------
8966 instruct movI_nocopy(rRegI dst, rRegI src) %{
8967 effect( DEF dst, USE src );
8968 format %{ "MOV $dst,$src" %}
8969 ins_encode( enc_Copy( dst, src) );
8970 ins_pipe( ialu_reg_reg );
8971 %}
8973 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8974 effect( USE_DEF dst, USE src, KILL cr );
8976 size(4);
8977 format %{ "NEG $dst\n\t"
8978 "ADC $dst,$src" %}
8979 ins_encode( neg_reg(dst),
8980 OpcRegReg(0x13,dst,src) );
8981 ins_pipe( ialu_reg_reg_long );
8982 %}
8984 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8985 match(Set dst (Conv2B src));
8987 expand %{
8988 movI_nocopy(dst,src);
8989 ci2b(dst,src,cr);
8990 %}
8991 %}
8993 instruct movP_nocopy(rRegI dst, eRegP src) %{
8994 effect( DEF dst, USE src );
8995 format %{ "MOV $dst,$src" %}
8996 ins_encode( enc_Copy( dst, src) );
8997 ins_pipe( ialu_reg_reg );
8998 %}
9000 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
9001 effect( USE_DEF dst, USE src, KILL cr );
9002 format %{ "NEG $dst\n\t"
9003 "ADC $dst,$src" %}
9004 ins_encode( neg_reg(dst),
9005 OpcRegReg(0x13,dst,src) );
9006 ins_pipe( ialu_reg_reg_long );
9007 %}
9009 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
9010 match(Set dst (Conv2B src));
9012 expand %{
9013 movP_nocopy(dst,src);
9014 cp2b(dst,src,cr);
9015 %}
9016 %}
9018 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{
9019 match(Set dst (CmpLTMask p q));
9020 effect(KILL cr);
9021 ins_cost(400);
9023 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9024 format %{ "XOR $dst,$dst\n\t"
9025 "CMP $p,$q\n\t"
9026 "SETlt $dst\n\t"
9027 "NEG $dst" %}
9028 ins_encode %{
9029 Register Rp = $p$$Register;
9030 Register Rq = $q$$Register;
9031 Register Rd = $dst$$Register;
9032 Label done;
9033 __ xorl(Rd, Rd);
9034 __ cmpl(Rp, Rq);
9035 __ setb(Assembler::less, Rd);
9036 __ negl(Rd);
9037 %}
9039 ins_pipe(pipe_slow);
9040 %}
9042 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{
9043 match(Set dst (CmpLTMask dst zero));
9044 effect(DEF dst, KILL cr);
9045 ins_cost(100);
9047 format %{ "SAR $dst,31\t# cmpLTMask0" %}
9048 ins_encode %{
9049 __ sarl($dst$$Register, 31);
9050 %}
9051 ins_pipe(ialu_reg);
9052 %}
9054 /* better to save a register than avoid a branch */
9055 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
9056 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9057 effect(KILL cr);
9058 ins_cost(400);
9059 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t"
9060 "JGE done\n\t"
9061 "ADD $p,$y\n"
9062 "done: " %}
9063 ins_encode %{
9064 Register Rp = $p$$Register;
9065 Register Rq = $q$$Register;
9066 Register Ry = $y$$Register;
9067 Label done;
9068 __ subl(Rp, Rq);
9069 __ jccb(Assembler::greaterEqual, done);
9070 __ addl(Rp, Ry);
9071 __ bind(done);
9072 %}
9074 ins_pipe(pipe_cmplt);
9075 %}
9077 /* better to save a register than avoid a branch */
9078 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
9079 match(Set y (AndI (CmpLTMask p q) y));
9080 effect(KILL cr);
9082 ins_cost(300);
9084 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t"
9085 "JLT done\n\t"
9086 "XORL $y, $y\n"
9087 "done: " %}
9088 ins_encode %{
9089 Register Rp = $p$$Register;
9090 Register Rq = $q$$Register;
9091 Register Ry = $y$$Register;
9092 Label done;
9093 __ cmpl(Rp, Rq);
9094 __ jccb(Assembler::less, done);
9095 __ xorl(Ry, Ry);
9096 __ bind(done);
9097 %}
9099 ins_pipe(pipe_cmplt);
9100 %}
9102 /* If I enable this, I encourage spilling in the inner loop of compress.
9103 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{
9104 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9105 */
9107 //----------Long Instructions------------------------------------------------
9108 // Add Long Register with Register
9109 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9110 match(Set dst (AddL dst src));
9111 effect(KILL cr);
9112 ins_cost(200);
9113 format %{ "ADD $dst.lo,$src.lo\n\t"
9114 "ADC $dst.hi,$src.hi" %}
9115 opcode(0x03, 0x13);
9116 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9117 ins_pipe( ialu_reg_reg_long );
9118 %}
9120 // Add Long Register with Immediate
9121 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9122 match(Set dst (AddL dst src));
9123 effect(KILL cr);
9124 format %{ "ADD $dst.lo,$src.lo\n\t"
9125 "ADC $dst.hi,$src.hi" %}
9126 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9127 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9128 ins_pipe( ialu_reg_long );
9129 %}
9131 // Add Long Register with Memory
9132 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9133 match(Set dst (AddL dst (LoadL mem)));
9134 effect(KILL cr);
9135 ins_cost(125);
9136 format %{ "ADD $dst.lo,$mem\n\t"
9137 "ADC $dst.hi,$mem+4" %}
9138 opcode(0x03, 0x13);
9139 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9140 ins_pipe( ialu_reg_long_mem );
9141 %}
9143 // Subtract Long Register with Register.
9144 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9145 match(Set dst (SubL dst src));
9146 effect(KILL cr);
9147 ins_cost(200);
9148 format %{ "SUB $dst.lo,$src.lo\n\t"
9149 "SBB $dst.hi,$src.hi" %}
9150 opcode(0x2B, 0x1B);
9151 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9152 ins_pipe( ialu_reg_reg_long );
9153 %}
9155 // Subtract Long Register with Immediate
9156 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9157 match(Set dst (SubL dst src));
9158 effect(KILL cr);
9159 format %{ "SUB $dst.lo,$src.lo\n\t"
9160 "SBB $dst.hi,$src.hi" %}
9161 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9162 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9163 ins_pipe( ialu_reg_long );
9164 %}
9166 // Subtract Long Register with Memory
9167 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9168 match(Set dst (SubL dst (LoadL mem)));
9169 effect(KILL cr);
9170 ins_cost(125);
9171 format %{ "SUB $dst.lo,$mem\n\t"
9172 "SBB $dst.hi,$mem+4" %}
9173 opcode(0x2B, 0x1B);
9174 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9175 ins_pipe( ialu_reg_long_mem );
9176 %}
9178 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9179 match(Set dst (SubL zero dst));
9180 effect(KILL cr);
9181 ins_cost(300);
9182 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9183 ins_encode( neg_long(dst) );
9184 ins_pipe( ialu_reg_reg_long );
9185 %}
9187 // And Long Register with Register
9188 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9189 match(Set dst (AndL dst src));
9190 effect(KILL cr);
9191 format %{ "AND $dst.lo,$src.lo\n\t"
9192 "AND $dst.hi,$src.hi" %}
9193 opcode(0x23,0x23);
9194 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9195 ins_pipe( ialu_reg_reg_long );
9196 %}
9198 // And Long Register with Immediate
9199 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9200 match(Set dst (AndL dst src));
9201 effect(KILL cr);
9202 format %{ "AND $dst.lo,$src.lo\n\t"
9203 "AND $dst.hi,$src.hi" %}
9204 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9205 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9206 ins_pipe( ialu_reg_long );
9207 %}
9209 // And Long Register with Memory
9210 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9211 match(Set dst (AndL dst (LoadL mem)));
9212 effect(KILL cr);
9213 ins_cost(125);
9214 format %{ "AND $dst.lo,$mem\n\t"
9215 "AND $dst.hi,$mem+4" %}
9216 opcode(0x23, 0x23);
9217 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9218 ins_pipe( ialu_reg_long_mem );
9219 %}
9221 // Or Long Register with Register
9222 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9223 match(Set dst (OrL dst src));
9224 effect(KILL cr);
9225 format %{ "OR $dst.lo,$src.lo\n\t"
9226 "OR $dst.hi,$src.hi" %}
9227 opcode(0x0B,0x0B);
9228 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9229 ins_pipe( ialu_reg_reg_long );
9230 %}
9232 // Or Long Register with Immediate
9233 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9234 match(Set dst (OrL dst src));
9235 effect(KILL cr);
9236 format %{ "OR $dst.lo,$src.lo\n\t"
9237 "OR $dst.hi,$src.hi" %}
9238 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9239 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9240 ins_pipe( ialu_reg_long );
9241 %}
9243 // Or Long Register with Memory
9244 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9245 match(Set dst (OrL dst (LoadL mem)));
9246 effect(KILL cr);
9247 ins_cost(125);
9248 format %{ "OR $dst.lo,$mem\n\t"
9249 "OR $dst.hi,$mem+4" %}
9250 opcode(0x0B,0x0B);
9251 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9252 ins_pipe( ialu_reg_long_mem );
9253 %}
9255 // Xor Long Register with Register
9256 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9257 match(Set dst (XorL dst src));
9258 effect(KILL cr);
9259 format %{ "XOR $dst.lo,$src.lo\n\t"
9260 "XOR $dst.hi,$src.hi" %}
9261 opcode(0x33,0x33);
9262 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9263 ins_pipe( ialu_reg_reg_long );
9264 %}
9266 // Xor Long Register with Immediate -1
9267 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9268 match(Set dst (XorL dst imm));
9269 format %{ "NOT $dst.lo\n\t"
9270 "NOT $dst.hi" %}
9271 ins_encode %{
9272 __ notl($dst$$Register);
9273 __ notl(HIGH_FROM_LOW($dst$$Register));
9274 %}
9275 ins_pipe( ialu_reg_long );
9276 %}
9278 // Xor Long Register with Immediate
9279 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9280 match(Set dst (XorL dst src));
9281 effect(KILL cr);
9282 format %{ "XOR $dst.lo,$src.lo\n\t"
9283 "XOR $dst.hi,$src.hi" %}
9284 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9285 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9286 ins_pipe( ialu_reg_long );
9287 %}
9289 // Xor Long Register with Memory
9290 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9291 match(Set dst (XorL dst (LoadL mem)));
9292 effect(KILL cr);
9293 ins_cost(125);
9294 format %{ "XOR $dst.lo,$mem\n\t"
9295 "XOR $dst.hi,$mem+4" %}
9296 opcode(0x33,0x33);
9297 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9298 ins_pipe( ialu_reg_long_mem );
9299 %}
9301 // Shift Left Long by 1
9302 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9303 predicate(UseNewLongLShift);
9304 match(Set dst (LShiftL dst cnt));
9305 effect(KILL cr);
9306 ins_cost(100);
9307 format %{ "ADD $dst.lo,$dst.lo\n\t"
9308 "ADC $dst.hi,$dst.hi" %}
9309 ins_encode %{
9310 __ addl($dst$$Register,$dst$$Register);
9311 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9312 %}
9313 ins_pipe( ialu_reg_long );
9314 %}
9316 // Shift Left Long by 2
9317 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9318 predicate(UseNewLongLShift);
9319 match(Set dst (LShiftL dst cnt));
9320 effect(KILL cr);
9321 ins_cost(100);
9322 format %{ "ADD $dst.lo,$dst.lo\n\t"
9323 "ADC $dst.hi,$dst.hi\n\t"
9324 "ADD $dst.lo,$dst.lo\n\t"
9325 "ADC $dst.hi,$dst.hi" %}
9326 ins_encode %{
9327 __ addl($dst$$Register,$dst$$Register);
9328 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9329 __ addl($dst$$Register,$dst$$Register);
9330 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9331 %}
9332 ins_pipe( ialu_reg_long );
9333 %}
9335 // Shift Left Long by 3
9336 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9337 predicate(UseNewLongLShift);
9338 match(Set dst (LShiftL dst cnt));
9339 effect(KILL cr);
9340 ins_cost(100);
9341 format %{ "ADD $dst.lo,$dst.lo\n\t"
9342 "ADC $dst.hi,$dst.hi\n\t"
9343 "ADD $dst.lo,$dst.lo\n\t"
9344 "ADC $dst.hi,$dst.hi\n\t"
9345 "ADD $dst.lo,$dst.lo\n\t"
9346 "ADC $dst.hi,$dst.hi" %}
9347 ins_encode %{
9348 __ addl($dst$$Register,$dst$$Register);
9349 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9350 __ addl($dst$$Register,$dst$$Register);
9351 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9352 __ addl($dst$$Register,$dst$$Register);
9353 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9354 %}
9355 ins_pipe( ialu_reg_long );
9356 %}
9358 // Shift Left Long by 1-31
9359 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9360 match(Set dst (LShiftL dst cnt));
9361 effect(KILL cr);
9362 ins_cost(200);
9363 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9364 "SHL $dst.lo,$cnt" %}
9365 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9366 ins_encode( move_long_small_shift(dst,cnt) );
9367 ins_pipe( ialu_reg_long );
9368 %}
9370 // Shift Left Long by 32-63
9371 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9372 match(Set dst (LShiftL dst cnt));
9373 effect(KILL cr);
9374 ins_cost(300);
9375 format %{ "MOV $dst.hi,$dst.lo\n"
9376 "\tSHL $dst.hi,$cnt-32\n"
9377 "\tXOR $dst.lo,$dst.lo" %}
9378 opcode(0xC1, 0x4); /* C1 /4 ib */
9379 ins_encode( move_long_big_shift_clr(dst,cnt) );
9380 ins_pipe( ialu_reg_long );
9381 %}
9383 // Shift Left Long by variable
9384 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9385 match(Set dst (LShiftL dst shift));
9386 effect(KILL cr);
9387 ins_cost(500+200);
9388 size(17);
9389 format %{ "TEST $shift,32\n\t"
9390 "JEQ,s small\n\t"
9391 "MOV $dst.hi,$dst.lo\n\t"
9392 "XOR $dst.lo,$dst.lo\n"
9393 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9394 "SHL $dst.lo,$shift" %}
9395 ins_encode( shift_left_long( dst, shift ) );
9396 ins_pipe( pipe_slow );
9397 %}
9399 // Shift Right Long by 1-31
9400 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9401 match(Set dst (URShiftL dst cnt));
9402 effect(KILL cr);
9403 ins_cost(200);
9404 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9405 "SHR $dst.hi,$cnt" %}
9406 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9407 ins_encode( move_long_small_shift(dst,cnt) );
9408 ins_pipe( ialu_reg_long );
9409 %}
9411 // Shift Right Long by 32-63
9412 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9413 match(Set dst (URShiftL dst cnt));
9414 effect(KILL cr);
9415 ins_cost(300);
9416 format %{ "MOV $dst.lo,$dst.hi\n"
9417 "\tSHR $dst.lo,$cnt-32\n"
9418 "\tXOR $dst.hi,$dst.hi" %}
9419 opcode(0xC1, 0x5); /* C1 /5 ib */
9420 ins_encode( move_long_big_shift_clr(dst,cnt) );
9421 ins_pipe( ialu_reg_long );
9422 %}
9424 // Shift Right Long by variable
9425 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9426 match(Set dst (URShiftL dst shift));
9427 effect(KILL cr);
9428 ins_cost(600);
9429 size(17);
9430 format %{ "TEST $shift,32\n\t"
9431 "JEQ,s small\n\t"
9432 "MOV $dst.lo,$dst.hi\n\t"
9433 "XOR $dst.hi,$dst.hi\n"
9434 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9435 "SHR $dst.hi,$shift" %}
9436 ins_encode( shift_right_long( dst, shift ) );
9437 ins_pipe( pipe_slow );
9438 %}
9440 // Shift Right Long by 1-31
9441 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9442 match(Set dst (RShiftL dst cnt));
9443 effect(KILL cr);
9444 ins_cost(200);
9445 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9446 "SAR $dst.hi,$cnt" %}
9447 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9448 ins_encode( move_long_small_shift(dst,cnt) );
9449 ins_pipe( ialu_reg_long );
9450 %}
9452 // Shift Right Long by 32-63
9453 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9454 match(Set dst (RShiftL dst cnt));
9455 effect(KILL cr);
9456 ins_cost(300);
9457 format %{ "MOV $dst.lo,$dst.hi\n"
9458 "\tSAR $dst.lo,$cnt-32\n"
9459 "\tSAR $dst.hi,31" %}
9460 opcode(0xC1, 0x7); /* C1 /7 ib */
9461 ins_encode( move_long_big_shift_sign(dst,cnt) );
9462 ins_pipe( ialu_reg_long );
9463 %}
9465 // Shift Right arithmetic Long by variable
9466 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9467 match(Set dst (RShiftL dst shift));
9468 effect(KILL cr);
9469 ins_cost(600);
9470 size(18);
9471 format %{ "TEST $shift,32\n\t"
9472 "JEQ,s small\n\t"
9473 "MOV $dst.lo,$dst.hi\n\t"
9474 "SAR $dst.hi,31\n"
9475 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9476 "SAR $dst.hi,$shift" %}
9477 ins_encode( shift_right_arith_long( dst, shift ) );
9478 ins_pipe( pipe_slow );
9479 %}
9482 //----------Double Instructions------------------------------------------------
9483 // Double Math
9485 // Compare & branch
9487 // P6 version of float compare, sets condition codes in EFLAGS
9488 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9489 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9490 match(Set cr (CmpD src1 src2));
9491 effect(KILL rax);
9492 ins_cost(150);
9493 format %{ "FLD $src1\n\t"
9494 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9495 "JNP exit\n\t"
9496 "MOV ah,1 // saw a NaN, set CF\n\t"
9497 "SAHF\n"
9498 "exit:\tNOP // avoid branch to branch" %}
9499 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9500 ins_encode( Push_Reg_DPR(src1),
9501 OpcP, RegOpc(src2),
9502 cmpF_P6_fixup );
9503 ins_pipe( pipe_slow );
9504 %}
9506 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9507 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9508 match(Set cr (CmpD src1 src2));
9509 ins_cost(150);
9510 format %{ "FLD $src1\n\t"
9511 "FUCOMIP ST,$src2 // P6 instruction" %}
9512 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9513 ins_encode( Push_Reg_DPR(src1),
9514 OpcP, RegOpc(src2));
9515 ins_pipe( pipe_slow );
9516 %}
9518 // Compare & branch
9519 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9520 predicate(UseSSE<=1);
9521 match(Set cr (CmpD src1 src2));
9522 effect(KILL rax);
9523 ins_cost(200);
9524 format %{ "FLD $src1\n\t"
9525 "FCOMp $src2\n\t"
9526 "FNSTSW AX\n\t"
9527 "TEST AX,0x400\n\t"
9528 "JZ,s flags\n\t"
9529 "MOV AH,1\t# unordered treat as LT\n"
9530 "flags:\tSAHF" %}
9531 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9532 ins_encode( Push_Reg_DPR(src1),
9533 OpcP, RegOpc(src2),
9534 fpu_flags);
9535 ins_pipe( pipe_slow );
9536 %}
9538 // Compare vs zero into -1,0,1
9539 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9540 predicate(UseSSE<=1);
9541 match(Set dst (CmpD3 src1 zero));
9542 effect(KILL cr, KILL rax);
9543 ins_cost(280);
9544 format %{ "FTSTD $dst,$src1" %}
9545 opcode(0xE4, 0xD9);
9546 ins_encode( Push_Reg_DPR(src1),
9547 OpcS, OpcP, PopFPU,
9548 CmpF_Result(dst));
9549 ins_pipe( pipe_slow );
9550 %}
9552 // Compare into -1,0,1
9553 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9554 predicate(UseSSE<=1);
9555 match(Set dst (CmpD3 src1 src2));
9556 effect(KILL cr, KILL rax);
9557 ins_cost(300);
9558 format %{ "FCMPD $dst,$src1,$src2" %}
9559 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9560 ins_encode( Push_Reg_DPR(src1),
9561 OpcP, RegOpc(src2),
9562 CmpF_Result(dst));
9563 ins_pipe( pipe_slow );
9564 %}
9566 // float compare and set condition codes in EFLAGS by XMM regs
9567 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9568 predicate(UseSSE>=2);
9569 match(Set cr (CmpD src1 src2));
9570 ins_cost(145);
9571 format %{ "UCOMISD $src1,$src2\n\t"
9572 "JNP,s exit\n\t"
9573 "PUSHF\t# saw NaN, set CF\n\t"
9574 "AND [rsp], #0xffffff2b\n\t"
9575 "POPF\n"
9576 "exit:" %}
9577 ins_encode %{
9578 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9579 emit_cmpfp_fixup(_masm);
9580 %}
9581 ins_pipe( pipe_slow );
9582 %}
9584 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9585 predicate(UseSSE>=2);
9586 match(Set cr (CmpD src1 src2));
9587 ins_cost(100);
9588 format %{ "UCOMISD $src1,$src2" %}
9589 ins_encode %{
9590 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9591 %}
9592 ins_pipe( pipe_slow );
9593 %}
9595 // float compare and set condition codes in EFLAGS by XMM regs
9596 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9597 predicate(UseSSE>=2);
9598 match(Set cr (CmpD src1 (LoadD src2)));
9599 ins_cost(145);
9600 format %{ "UCOMISD $src1,$src2\n\t"
9601 "JNP,s exit\n\t"
9602 "PUSHF\t# saw NaN, set CF\n\t"
9603 "AND [rsp], #0xffffff2b\n\t"
9604 "POPF\n"
9605 "exit:" %}
9606 ins_encode %{
9607 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9608 emit_cmpfp_fixup(_masm);
9609 %}
9610 ins_pipe( pipe_slow );
9611 %}
9613 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9614 predicate(UseSSE>=2);
9615 match(Set cr (CmpD src1 (LoadD src2)));
9616 ins_cost(100);
9617 format %{ "UCOMISD $src1,$src2" %}
9618 ins_encode %{
9619 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9620 %}
9621 ins_pipe( pipe_slow );
9622 %}
9624 // Compare into -1,0,1 in XMM
9625 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9626 predicate(UseSSE>=2);
9627 match(Set dst (CmpD3 src1 src2));
9628 effect(KILL cr);
9629 ins_cost(255);
9630 format %{ "UCOMISD $src1, $src2\n\t"
9631 "MOV $dst, #-1\n\t"
9632 "JP,s done\n\t"
9633 "JB,s done\n\t"
9634 "SETNE $dst\n\t"
9635 "MOVZB $dst, $dst\n"
9636 "done:" %}
9637 ins_encode %{
9638 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9639 emit_cmpfp3(_masm, $dst$$Register);
9640 %}
9641 ins_pipe( pipe_slow );
9642 %}
9644 // Compare into -1,0,1 in XMM and memory
9645 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9646 predicate(UseSSE>=2);
9647 match(Set dst (CmpD3 src1 (LoadD src2)));
9648 effect(KILL cr);
9649 ins_cost(275);
9650 format %{ "UCOMISD $src1, $src2\n\t"
9651 "MOV $dst, #-1\n\t"
9652 "JP,s done\n\t"
9653 "JB,s done\n\t"
9654 "SETNE $dst\n\t"
9655 "MOVZB $dst, $dst\n"
9656 "done:" %}
9657 ins_encode %{
9658 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9659 emit_cmpfp3(_masm, $dst$$Register);
9660 %}
9661 ins_pipe( pipe_slow );
9662 %}
9665 instruct subDPR_reg(regDPR dst, regDPR src) %{
9666 predicate (UseSSE <=1);
9667 match(Set dst (SubD dst src));
9669 format %{ "FLD $src\n\t"
9670 "DSUBp $dst,ST" %}
9671 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9672 ins_cost(150);
9673 ins_encode( Push_Reg_DPR(src),
9674 OpcP, RegOpc(dst) );
9675 ins_pipe( fpu_reg_reg );
9676 %}
9678 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9679 predicate (UseSSE <=1);
9680 match(Set dst (RoundDouble (SubD src1 src2)));
9681 ins_cost(250);
9683 format %{ "FLD $src2\n\t"
9684 "DSUB ST,$src1\n\t"
9685 "FSTP_D $dst\t# D-round" %}
9686 opcode(0xD8, 0x5);
9687 ins_encode( Push_Reg_DPR(src2),
9688 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9689 ins_pipe( fpu_mem_reg_reg );
9690 %}
9693 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9694 predicate (UseSSE <=1);
9695 match(Set dst (SubD dst (LoadD src)));
9696 ins_cost(150);
9698 format %{ "FLD $src\n\t"
9699 "DSUBp $dst,ST" %}
9700 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9701 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9702 OpcP, RegOpc(dst) );
9703 ins_pipe( fpu_reg_mem );
9704 %}
9706 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9707 predicate (UseSSE<=1);
9708 match(Set dst (AbsD src));
9709 ins_cost(100);
9710 format %{ "FABS" %}
9711 opcode(0xE1, 0xD9);
9712 ins_encode( OpcS, OpcP );
9713 ins_pipe( fpu_reg_reg );
9714 %}
9716 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9717 predicate(UseSSE<=1);
9718 match(Set dst (NegD src));
9719 ins_cost(100);
9720 format %{ "FCHS" %}
9721 opcode(0xE0, 0xD9);
9722 ins_encode( OpcS, OpcP );
9723 ins_pipe( fpu_reg_reg );
9724 %}
9726 instruct addDPR_reg(regDPR dst, regDPR src) %{
9727 predicate(UseSSE<=1);
9728 match(Set dst (AddD dst src));
9729 format %{ "FLD $src\n\t"
9730 "DADD $dst,ST" %}
9731 size(4);
9732 ins_cost(150);
9733 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9734 ins_encode( Push_Reg_DPR(src),
9735 OpcP, RegOpc(dst) );
9736 ins_pipe( fpu_reg_reg );
9737 %}
9740 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9741 predicate(UseSSE<=1);
9742 match(Set dst (RoundDouble (AddD src1 src2)));
9743 ins_cost(250);
9745 format %{ "FLD $src2\n\t"
9746 "DADD ST,$src1\n\t"
9747 "FSTP_D $dst\t# D-round" %}
9748 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9749 ins_encode( Push_Reg_DPR(src2),
9750 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9751 ins_pipe( fpu_mem_reg_reg );
9752 %}
9755 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9756 predicate(UseSSE<=1);
9757 match(Set dst (AddD dst (LoadD src)));
9758 ins_cost(150);
9760 format %{ "FLD $src\n\t"
9761 "DADDp $dst,ST" %}
9762 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9763 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9764 OpcP, RegOpc(dst) );
9765 ins_pipe( fpu_reg_mem );
9766 %}
9768 // add-to-memory
9769 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9770 predicate(UseSSE<=1);
9771 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9772 ins_cost(150);
9774 format %{ "FLD_D $dst\n\t"
9775 "DADD ST,$src\n\t"
9776 "FST_D $dst" %}
9777 opcode(0xDD, 0x0);
9778 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9779 Opcode(0xD8), RegOpc(src),
9780 set_instruction_start,
9781 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9782 ins_pipe( fpu_reg_mem );
9783 %}
9785 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9786 predicate(UseSSE<=1);
9787 match(Set dst (AddD dst con));
9788 ins_cost(125);
9789 format %{ "FLD1\n\t"
9790 "DADDp $dst,ST" %}
9791 ins_encode %{
9792 __ fld1();
9793 __ faddp($dst$$reg);
9794 %}
9795 ins_pipe(fpu_reg);
9796 %}
9798 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9799 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9800 match(Set dst (AddD dst con));
9801 ins_cost(200);
9802 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9803 "DADDp $dst,ST" %}
9804 ins_encode %{
9805 __ fld_d($constantaddress($con));
9806 __ faddp($dst$$reg);
9807 %}
9808 ins_pipe(fpu_reg_mem);
9809 %}
9811 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9812 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9813 match(Set dst (RoundDouble (AddD src con)));
9814 ins_cost(200);
9815 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9816 "DADD ST,$src\n\t"
9817 "FSTP_D $dst\t# D-round" %}
9818 ins_encode %{
9819 __ fld_d($constantaddress($con));
9820 __ fadd($src$$reg);
9821 __ fstp_d(Address(rsp, $dst$$disp));
9822 %}
9823 ins_pipe(fpu_mem_reg_con);
9824 %}
9826 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9827 predicate(UseSSE<=1);
9828 match(Set dst (MulD dst src));
9829 format %{ "FLD $src\n\t"
9830 "DMULp $dst,ST" %}
9831 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9832 ins_cost(150);
9833 ins_encode( Push_Reg_DPR(src),
9834 OpcP, RegOpc(dst) );
9835 ins_pipe( fpu_reg_reg );
9836 %}
9838 // Strict FP instruction biases argument before multiply then
9839 // biases result to avoid double rounding of subnormals.
9840 //
9841 // scale arg1 by multiplying arg1 by 2^(-15360)
9842 // load arg2
9843 // multiply scaled arg1 by arg2
9844 // rescale product by 2^(15360)
9845 //
9846 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9847 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9848 match(Set dst (MulD dst src));
9849 ins_cost(1); // Select this instruction for all strict FP double multiplies
9851 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9852 "DMULp $dst,ST\n\t"
9853 "FLD $src\n\t"
9854 "DMULp $dst,ST\n\t"
9855 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9856 "DMULp $dst,ST\n\t" %}
9857 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9858 ins_encode( strictfp_bias1(dst),
9859 Push_Reg_DPR(src),
9860 OpcP, RegOpc(dst),
9861 strictfp_bias2(dst) );
9862 ins_pipe( fpu_reg_reg );
9863 %}
9865 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9866 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9867 match(Set dst (MulD dst con));
9868 ins_cost(200);
9869 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9870 "DMULp $dst,ST" %}
9871 ins_encode %{
9872 __ fld_d($constantaddress($con));
9873 __ fmulp($dst$$reg);
9874 %}
9875 ins_pipe(fpu_reg_mem);
9876 %}
9879 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9880 predicate( UseSSE<=1 );
9881 match(Set dst (MulD dst (LoadD src)));
9882 ins_cost(200);
9883 format %{ "FLD_D $src\n\t"
9884 "DMULp $dst,ST" %}
9885 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9886 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9887 OpcP, RegOpc(dst) );
9888 ins_pipe( fpu_reg_mem );
9889 %}
9891 //
9892 // Cisc-alternate to reg-reg multiply
9893 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9894 predicate( UseSSE<=1 );
9895 match(Set dst (MulD src (LoadD mem)));
9896 ins_cost(250);
9897 format %{ "FLD_D $mem\n\t"
9898 "DMUL ST,$src\n\t"
9899 "FSTP_D $dst" %}
9900 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9901 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9902 OpcReg_FPR(src),
9903 Pop_Reg_DPR(dst) );
9904 ins_pipe( fpu_reg_reg_mem );
9905 %}
9908 // MACRO3 -- addDPR a mulDPR
9909 // This instruction is a '2-address' instruction in that the result goes
9910 // back to src2. This eliminates a move from the macro; possibly the
9911 // register allocator will have to add it back (and maybe not).
9912 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9913 predicate( UseSSE<=1 );
9914 match(Set src2 (AddD (MulD src0 src1) src2));
9915 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9916 "DMUL ST,$src1\n\t"
9917 "DADDp $src2,ST" %}
9918 ins_cost(250);
9919 opcode(0xDD); /* LoadD DD /0 */
9920 ins_encode( Push_Reg_FPR(src0),
9921 FMul_ST_reg(src1),
9922 FAddP_reg_ST(src2) );
9923 ins_pipe( fpu_reg_reg_reg );
9924 %}
9927 // MACRO3 -- subDPR a mulDPR
9928 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9929 predicate( UseSSE<=1 );
9930 match(Set src2 (SubD (MulD src0 src1) src2));
9931 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9932 "DMUL ST,$src1\n\t"
9933 "DSUBRp $src2,ST" %}
9934 ins_cost(250);
9935 ins_encode( Push_Reg_FPR(src0),
9936 FMul_ST_reg(src1),
9937 Opcode(0xDE), Opc_plus(0xE0,src2));
9938 ins_pipe( fpu_reg_reg_reg );
9939 %}
9942 instruct divDPR_reg(regDPR dst, regDPR src) %{
9943 predicate( UseSSE<=1 );
9944 match(Set dst (DivD dst src));
9946 format %{ "FLD $src\n\t"
9947 "FDIVp $dst,ST" %}
9948 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9949 ins_cost(150);
9950 ins_encode( Push_Reg_DPR(src),
9951 OpcP, RegOpc(dst) );
9952 ins_pipe( fpu_reg_reg );
9953 %}
9955 // Strict FP instruction biases argument before division then
9956 // biases result, to avoid double rounding of subnormals.
9957 //
9958 // scale dividend by multiplying dividend by 2^(-15360)
9959 // load divisor
9960 // divide scaled dividend by divisor
9961 // rescale quotient by 2^(15360)
9962 //
9963 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9964 predicate (UseSSE<=1);
9965 match(Set dst (DivD dst src));
9966 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9967 ins_cost(01);
9969 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9970 "DMULp $dst,ST\n\t"
9971 "FLD $src\n\t"
9972 "FDIVp $dst,ST\n\t"
9973 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9974 "DMULp $dst,ST\n\t" %}
9975 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9976 ins_encode( strictfp_bias1(dst),
9977 Push_Reg_DPR(src),
9978 OpcP, RegOpc(dst),
9979 strictfp_bias2(dst) );
9980 ins_pipe( fpu_reg_reg );
9981 %}
9983 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9984 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9985 match(Set dst (RoundDouble (DivD src1 src2)));
9987 format %{ "FLD $src1\n\t"
9988 "FDIV ST,$src2\n\t"
9989 "FSTP_D $dst\t# D-round" %}
9990 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9991 ins_encode( Push_Reg_DPR(src1),
9992 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9993 ins_pipe( fpu_mem_reg_reg );
9994 %}
9997 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9998 predicate(UseSSE<=1);
9999 match(Set dst (ModD dst src));
10000 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10002 format %{ "DMOD $dst,$src" %}
10003 ins_cost(250);
10004 ins_encode(Push_Reg_Mod_DPR(dst, src),
10005 emitModDPR(),
10006 Push_Result_Mod_DPR(src),
10007 Pop_Reg_DPR(dst));
10008 ins_pipe( pipe_slow );
10009 %}
10011 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
10012 predicate(UseSSE>=2);
10013 match(Set dst (ModD src0 src1));
10014 effect(KILL rax, KILL cr);
10016 format %{ "SUB ESP,8\t # DMOD\n"
10017 "\tMOVSD [ESP+0],$src1\n"
10018 "\tFLD_D [ESP+0]\n"
10019 "\tMOVSD [ESP+0],$src0\n"
10020 "\tFLD_D [ESP+0]\n"
10021 "loop:\tFPREM\n"
10022 "\tFWAIT\n"
10023 "\tFNSTSW AX\n"
10024 "\tSAHF\n"
10025 "\tJP loop\n"
10026 "\tFSTP_D [ESP+0]\n"
10027 "\tMOVSD $dst,[ESP+0]\n"
10028 "\tADD ESP,8\n"
10029 "\tFSTP ST0\t # Restore FPU Stack"
10030 %}
10031 ins_cost(250);
10032 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
10033 ins_pipe( pipe_slow );
10034 %}
10036 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
10037 predicate (UseSSE<=1);
10038 match(Set dst (SinD src));
10039 ins_cost(1800);
10040 format %{ "DSIN $dst" %}
10041 opcode(0xD9, 0xFE);
10042 ins_encode( OpcP, OpcS );
10043 ins_pipe( pipe_slow );
10044 %}
10046 instruct sinD_reg(regD dst, eFlagsReg cr) %{
10047 predicate (UseSSE>=2);
10048 match(Set dst (SinD dst));
10049 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10050 ins_cost(1800);
10051 format %{ "DSIN $dst" %}
10052 opcode(0xD9, 0xFE);
10053 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10054 ins_pipe( pipe_slow );
10055 %}
10057 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
10058 predicate (UseSSE<=1);
10059 match(Set dst (CosD src));
10060 ins_cost(1800);
10061 format %{ "DCOS $dst" %}
10062 opcode(0xD9, 0xFF);
10063 ins_encode( OpcP, OpcS );
10064 ins_pipe( pipe_slow );
10065 %}
10067 instruct cosD_reg(regD dst, eFlagsReg cr) %{
10068 predicate (UseSSE>=2);
10069 match(Set dst (CosD dst));
10070 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10071 ins_cost(1800);
10072 format %{ "DCOS $dst" %}
10073 opcode(0xD9, 0xFF);
10074 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10075 ins_pipe( pipe_slow );
10076 %}
10078 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
10079 predicate (UseSSE<=1);
10080 match(Set dst(TanD src));
10081 format %{ "DTAN $dst" %}
10082 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10083 Opcode(0xDD), Opcode(0xD8)); // fstp st
10084 ins_pipe( pipe_slow );
10085 %}
10087 instruct tanD_reg(regD dst, eFlagsReg cr) %{
10088 predicate (UseSSE>=2);
10089 match(Set dst(TanD dst));
10090 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10091 format %{ "DTAN $dst" %}
10092 ins_encode( Push_SrcD(dst),
10093 Opcode(0xD9), Opcode(0xF2), // fptan
10094 Opcode(0xDD), Opcode(0xD8), // fstp st
10095 Push_ResultD(dst) );
10096 ins_pipe( pipe_slow );
10097 %}
10099 instruct atanDPR_reg(regDPR dst, regDPR src) %{
10100 predicate (UseSSE<=1);
10101 match(Set dst(AtanD dst src));
10102 format %{ "DATA $dst,$src" %}
10103 opcode(0xD9, 0xF3);
10104 ins_encode( Push_Reg_DPR(src),
10105 OpcP, OpcS, RegOpc(dst) );
10106 ins_pipe( pipe_slow );
10107 %}
10109 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
10110 predicate (UseSSE>=2);
10111 match(Set dst(AtanD dst src));
10112 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10113 format %{ "DATA $dst,$src" %}
10114 opcode(0xD9, 0xF3);
10115 ins_encode( Push_SrcD(src),
10116 OpcP, OpcS, Push_ResultD(dst) );
10117 ins_pipe( pipe_slow );
10118 %}
10120 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
10121 predicate (UseSSE<=1);
10122 match(Set dst (SqrtD src));
10123 format %{ "DSQRT $dst,$src" %}
10124 opcode(0xFA, 0xD9);
10125 ins_encode( Push_Reg_DPR(src),
10126 OpcS, OpcP, Pop_Reg_DPR(dst) );
10127 ins_pipe( pipe_slow );
10128 %}
10130 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10131 predicate (UseSSE<=1);
10132 match(Set Y (PowD X Y)); // Raise X to the Yth power
10133 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10134 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
10135 ins_encode %{
10136 __ subptr(rsp, 8);
10137 __ fld_s($X$$reg - 1);
10138 __ fast_pow();
10139 __ addptr(rsp, 8);
10140 %}
10141 ins_pipe( pipe_slow );
10142 %}
10144 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10145 predicate (UseSSE>=2);
10146 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10147 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10148 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
10149 ins_encode %{
10150 __ subptr(rsp, 8);
10151 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
10152 __ fld_d(Address(rsp, 0));
10153 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
10154 __ fld_d(Address(rsp, 0));
10155 __ fast_pow();
10156 __ fstp_d(Address(rsp, 0));
10157 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10158 __ addptr(rsp, 8);
10159 %}
10160 ins_pipe( pipe_slow );
10161 %}
10164 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10165 predicate (UseSSE<=1);
10166 match(Set dpr1 (ExpD dpr1));
10167 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10168 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
10169 ins_encode %{
10170 __ fast_exp();
10171 %}
10172 ins_pipe( pipe_slow );
10173 %}
10175 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10176 predicate (UseSSE>=2);
10177 match(Set dst (ExpD src));
10178 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10179 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
10180 ins_encode %{
10181 __ subptr(rsp, 8);
10182 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10183 __ fld_d(Address(rsp, 0));
10184 __ fast_exp();
10185 __ fstp_d(Address(rsp, 0));
10186 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10187 __ addptr(rsp, 8);
10188 %}
10189 ins_pipe( pipe_slow );
10190 %}
10192 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10193 predicate (UseSSE<=1);
10194 // The source Double operand on FPU stack
10195 match(Set dst (Log10D src));
10196 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10197 // fxch ; swap ST(0) with ST(1)
10198 // fyl2x ; compute log_10(2) * log_2(x)
10199 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10200 "FXCH \n\t"
10201 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10202 %}
10203 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10204 Opcode(0xD9), Opcode(0xC9), // fxch
10205 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10207 ins_pipe( pipe_slow );
10208 %}
10210 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10211 predicate (UseSSE>=2);
10212 effect(KILL cr);
10213 match(Set dst (Log10D src));
10214 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10215 // fyl2x ; compute log_10(2) * log_2(x)
10216 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10217 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10218 %}
10219 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10220 Push_SrcD(src),
10221 Opcode(0xD9), Opcode(0xF1), // fyl2x
10222 Push_ResultD(dst));
10224 ins_pipe( pipe_slow );
10225 %}
10227 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10228 predicate (UseSSE<=1);
10229 // The source Double operand on FPU stack
10230 match(Set dst (LogD src));
10231 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10232 // fxch ; swap ST(0) with ST(1)
10233 // fyl2x ; compute log_e(2) * log_2(x)
10234 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10235 "FXCH \n\t"
10236 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10237 %}
10238 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10239 Opcode(0xD9), Opcode(0xC9), // fxch
10240 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10242 ins_pipe( pipe_slow );
10243 %}
10245 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10246 predicate (UseSSE>=2);
10247 effect(KILL cr);
10248 // The source and result Double operands in XMM registers
10249 match(Set dst (LogD src));
10250 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10251 // fyl2x ; compute log_e(2) * log_2(x)
10252 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10253 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10254 %}
10255 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10256 Push_SrcD(src),
10257 Opcode(0xD9), Opcode(0xF1), // fyl2x
10258 Push_ResultD(dst));
10259 ins_pipe( pipe_slow );
10260 %}
10262 //-------------Float Instructions-------------------------------
10263 // Float Math
10265 // Code for float compare:
10266 // fcompp();
10267 // fwait(); fnstsw_ax();
10268 // sahf();
10269 // movl(dst, unordered_result);
10270 // jcc(Assembler::parity, exit);
10271 // movl(dst, less_result);
10272 // jcc(Assembler::below, exit);
10273 // movl(dst, equal_result);
10274 // jcc(Assembler::equal, exit);
10275 // movl(dst, greater_result);
10276 // exit:
10278 // P6 version of float compare, sets condition codes in EFLAGS
10279 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10280 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10281 match(Set cr (CmpF src1 src2));
10282 effect(KILL rax);
10283 ins_cost(150);
10284 format %{ "FLD $src1\n\t"
10285 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10286 "JNP exit\n\t"
10287 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10288 "SAHF\n"
10289 "exit:\tNOP // avoid branch to branch" %}
10290 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10291 ins_encode( Push_Reg_DPR(src1),
10292 OpcP, RegOpc(src2),
10293 cmpF_P6_fixup );
10294 ins_pipe( pipe_slow );
10295 %}
10297 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10298 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10299 match(Set cr (CmpF src1 src2));
10300 ins_cost(100);
10301 format %{ "FLD $src1\n\t"
10302 "FUCOMIP ST,$src2 // P6 instruction" %}
10303 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10304 ins_encode( Push_Reg_DPR(src1),
10305 OpcP, RegOpc(src2));
10306 ins_pipe( pipe_slow );
10307 %}
10310 // Compare & branch
10311 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10312 predicate(UseSSE == 0);
10313 match(Set cr (CmpF src1 src2));
10314 effect(KILL rax);
10315 ins_cost(200);
10316 format %{ "FLD $src1\n\t"
10317 "FCOMp $src2\n\t"
10318 "FNSTSW AX\n\t"
10319 "TEST AX,0x400\n\t"
10320 "JZ,s flags\n\t"
10321 "MOV AH,1\t# unordered treat as LT\n"
10322 "flags:\tSAHF" %}
10323 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10324 ins_encode( Push_Reg_DPR(src1),
10325 OpcP, RegOpc(src2),
10326 fpu_flags);
10327 ins_pipe( pipe_slow );
10328 %}
10330 // Compare vs zero into -1,0,1
10331 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10332 predicate(UseSSE == 0);
10333 match(Set dst (CmpF3 src1 zero));
10334 effect(KILL cr, KILL rax);
10335 ins_cost(280);
10336 format %{ "FTSTF $dst,$src1" %}
10337 opcode(0xE4, 0xD9);
10338 ins_encode( Push_Reg_DPR(src1),
10339 OpcS, OpcP, PopFPU,
10340 CmpF_Result(dst));
10341 ins_pipe( pipe_slow );
10342 %}
10344 // Compare into -1,0,1
10345 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10346 predicate(UseSSE == 0);
10347 match(Set dst (CmpF3 src1 src2));
10348 effect(KILL cr, KILL rax);
10349 ins_cost(300);
10350 format %{ "FCMPF $dst,$src1,$src2" %}
10351 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10352 ins_encode( Push_Reg_DPR(src1),
10353 OpcP, RegOpc(src2),
10354 CmpF_Result(dst));
10355 ins_pipe( pipe_slow );
10356 %}
10358 // float compare and set condition codes in EFLAGS by XMM regs
10359 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10360 predicate(UseSSE>=1);
10361 match(Set cr (CmpF src1 src2));
10362 ins_cost(145);
10363 format %{ "UCOMISS $src1,$src2\n\t"
10364 "JNP,s exit\n\t"
10365 "PUSHF\t# saw NaN, set CF\n\t"
10366 "AND [rsp], #0xffffff2b\n\t"
10367 "POPF\n"
10368 "exit:" %}
10369 ins_encode %{
10370 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10371 emit_cmpfp_fixup(_masm);
10372 %}
10373 ins_pipe( pipe_slow );
10374 %}
10376 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10377 predicate(UseSSE>=1);
10378 match(Set cr (CmpF src1 src2));
10379 ins_cost(100);
10380 format %{ "UCOMISS $src1,$src2" %}
10381 ins_encode %{
10382 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10383 %}
10384 ins_pipe( pipe_slow );
10385 %}
10387 // float compare and set condition codes in EFLAGS by XMM regs
10388 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10389 predicate(UseSSE>=1);
10390 match(Set cr (CmpF src1 (LoadF src2)));
10391 ins_cost(165);
10392 format %{ "UCOMISS $src1,$src2\n\t"
10393 "JNP,s exit\n\t"
10394 "PUSHF\t# saw NaN, set CF\n\t"
10395 "AND [rsp], #0xffffff2b\n\t"
10396 "POPF\n"
10397 "exit:" %}
10398 ins_encode %{
10399 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10400 emit_cmpfp_fixup(_masm);
10401 %}
10402 ins_pipe( pipe_slow );
10403 %}
10405 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10406 predicate(UseSSE>=1);
10407 match(Set cr (CmpF src1 (LoadF src2)));
10408 ins_cost(100);
10409 format %{ "UCOMISS $src1,$src2" %}
10410 ins_encode %{
10411 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10412 %}
10413 ins_pipe( pipe_slow );
10414 %}
10416 // Compare into -1,0,1 in XMM
10417 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10418 predicate(UseSSE>=1);
10419 match(Set dst (CmpF3 src1 src2));
10420 effect(KILL cr);
10421 ins_cost(255);
10422 format %{ "UCOMISS $src1, $src2\n\t"
10423 "MOV $dst, #-1\n\t"
10424 "JP,s done\n\t"
10425 "JB,s done\n\t"
10426 "SETNE $dst\n\t"
10427 "MOVZB $dst, $dst\n"
10428 "done:" %}
10429 ins_encode %{
10430 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10431 emit_cmpfp3(_masm, $dst$$Register);
10432 %}
10433 ins_pipe( pipe_slow );
10434 %}
10436 // Compare into -1,0,1 in XMM and memory
10437 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10438 predicate(UseSSE>=1);
10439 match(Set dst (CmpF3 src1 (LoadF src2)));
10440 effect(KILL cr);
10441 ins_cost(275);
10442 format %{ "UCOMISS $src1, $src2\n\t"
10443 "MOV $dst, #-1\n\t"
10444 "JP,s done\n\t"
10445 "JB,s done\n\t"
10446 "SETNE $dst\n\t"
10447 "MOVZB $dst, $dst\n"
10448 "done:" %}
10449 ins_encode %{
10450 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10451 emit_cmpfp3(_masm, $dst$$Register);
10452 %}
10453 ins_pipe( pipe_slow );
10454 %}
10456 // Spill to obtain 24-bit precision
10457 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10458 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10459 match(Set dst (SubF src1 src2));
10461 format %{ "FSUB $dst,$src1 - $src2" %}
10462 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10463 ins_encode( Push_Reg_FPR(src1),
10464 OpcReg_FPR(src2),
10465 Pop_Mem_FPR(dst) );
10466 ins_pipe( fpu_mem_reg_reg );
10467 %}
10468 //
10469 // This instruction does not round to 24-bits
10470 instruct subFPR_reg(regFPR dst, regFPR src) %{
10471 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10472 match(Set dst (SubF dst src));
10474 format %{ "FSUB $dst,$src" %}
10475 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10476 ins_encode( Push_Reg_FPR(src),
10477 OpcP, RegOpc(dst) );
10478 ins_pipe( fpu_reg_reg );
10479 %}
10481 // Spill to obtain 24-bit precision
10482 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10483 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10484 match(Set dst (AddF src1 src2));
10486 format %{ "FADD $dst,$src1,$src2" %}
10487 opcode(0xD8, 0x0); /* D8 C0+i */
10488 ins_encode( Push_Reg_FPR(src2),
10489 OpcReg_FPR(src1),
10490 Pop_Mem_FPR(dst) );
10491 ins_pipe( fpu_mem_reg_reg );
10492 %}
10493 //
10494 // This instruction does not round to 24-bits
10495 instruct addFPR_reg(regFPR dst, regFPR src) %{
10496 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10497 match(Set dst (AddF dst src));
10499 format %{ "FLD $src\n\t"
10500 "FADDp $dst,ST" %}
10501 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10502 ins_encode( Push_Reg_FPR(src),
10503 OpcP, RegOpc(dst) );
10504 ins_pipe( fpu_reg_reg );
10505 %}
10507 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10508 predicate(UseSSE==0);
10509 match(Set dst (AbsF src));
10510 ins_cost(100);
10511 format %{ "FABS" %}
10512 opcode(0xE1, 0xD9);
10513 ins_encode( OpcS, OpcP );
10514 ins_pipe( fpu_reg_reg );
10515 %}
10517 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10518 predicate(UseSSE==0);
10519 match(Set dst (NegF src));
10520 ins_cost(100);
10521 format %{ "FCHS" %}
10522 opcode(0xE0, 0xD9);
10523 ins_encode( OpcS, OpcP );
10524 ins_pipe( fpu_reg_reg );
10525 %}
10527 // Cisc-alternate to addFPR_reg
10528 // Spill to obtain 24-bit precision
10529 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10530 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10531 match(Set dst (AddF src1 (LoadF src2)));
10533 format %{ "FLD $src2\n\t"
10534 "FADD ST,$src1\n\t"
10535 "FSTP_S $dst" %}
10536 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10537 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10538 OpcReg_FPR(src1),
10539 Pop_Mem_FPR(dst) );
10540 ins_pipe( fpu_mem_reg_mem );
10541 %}
10542 //
10543 // Cisc-alternate to addFPR_reg
10544 // This instruction does not round to 24-bits
10545 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10546 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10547 match(Set dst (AddF dst (LoadF src)));
10549 format %{ "FADD $dst,$src" %}
10550 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10551 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10552 OpcP, RegOpc(dst) );
10553 ins_pipe( fpu_reg_mem );
10554 %}
10556 // // Following two instructions for _222_mpegaudio
10557 // Spill to obtain 24-bit precision
10558 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10559 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10560 match(Set dst (AddF src1 src2));
10562 format %{ "FADD $dst,$src1,$src2" %}
10563 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10564 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10565 OpcReg_FPR(src2),
10566 Pop_Mem_FPR(dst) );
10567 ins_pipe( fpu_mem_reg_mem );
10568 %}
10570 // Cisc-spill variant
10571 // Spill to obtain 24-bit precision
10572 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10573 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10574 match(Set dst (AddF src1 (LoadF src2)));
10576 format %{ "FADD $dst,$src1,$src2 cisc" %}
10577 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10578 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10579 set_instruction_start,
10580 OpcP, RMopc_Mem(secondary,src1),
10581 Pop_Mem_FPR(dst) );
10582 ins_pipe( fpu_mem_mem_mem );
10583 %}
10585 // Spill to obtain 24-bit precision
10586 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10587 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10588 match(Set dst (AddF src1 src2));
10590 format %{ "FADD $dst,$src1,$src2" %}
10591 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10592 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10593 set_instruction_start,
10594 OpcP, RMopc_Mem(secondary,src1),
10595 Pop_Mem_FPR(dst) );
10596 ins_pipe( fpu_mem_mem_mem );
10597 %}
10600 // Spill to obtain 24-bit precision
10601 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10602 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10603 match(Set dst (AddF src con));
10604 format %{ "FLD $src\n\t"
10605 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10606 "FSTP_S $dst" %}
10607 ins_encode %{
10608 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10609 __ fadd_s($constantaddress($con));
10610 __ fstp_s(Address(rsp, $dst$$disp));
10611 %}
10612 ins_pipe(fpu_mem_reg_con);
10613 %}
10614 //
10615 // This instruction does not round to 24-bits
10616 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10617 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10618 match(Set dst (AddF src con));
10619 format %{ "FLD $src\n\t"
10620 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10621 "FSTP $dst" %}
10622 ins_encode %{
10623 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10624 __ fadd_s($constantaddress($con));
10625 __ fstp_d($dst$$reg);
10626 %}
10627 ins_pipe(fpu_reg_reg_con);
10628 %}
10630 // Spill to obtain 24-bit precision
10631 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10632 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10633 match(Set dst (MulF src1 src2));
10635 format %{ "FLD $src1\n\t"
10636 "FMUL $src2\n\t"
10637 "FSTP_S $dst" %}
10638 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10639 ins_encode( Push_Reg_FPR(src1),
10640 OpcReg_FPR(src2),
10641 Pop_Mem_FPR(dst) );
10642 ins_pipe( fpu_mem_reg_reg );
10643 %}
10644 //
10645 // This instruction does not round to 24-bits
10646 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10647 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10648 match(Set dst (MulF src1 src2));
10650 format %{ "FLD $src1\n\t"
10651 "FMUL $src2\n\t"
10652 "FSTP_S $dst" %}
10653 opcode(0xD8, 0x1); /* D8 C8+i */
10654 ins_encode( Push_Reg_FPR(src2),
10655 OpcReg_FPR(src1),
10656 Pop_Reg_FPR(dst) );
10657 ins_pipe( fpu_reg_reg_reg );
10658 %}
10661 // Spill to obtain 24-bit precision
10662 // Cisc-alternate to reg-reg multiply
10663 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10664 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10665 match(Set dst (MulF src1 (LoadF src2)));
10667 format %{ "FLD_S $src2\n\t"
10668 "FMUL $src1\n\t"
10669 "FSTP_S $dst" %}
10670 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10671 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10672 OpcReg_FPR(src1),
10673 Pop_Mem_FPR(dst) );
10674 ins_pipe( fpu_mem_reg_mem );
10675 %}
10676 //
10677 // This instruction does not round to 24-bits
10678 // Cisc-alternate to reg-reg multiply
10679 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10680 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10681 match(Set dst (MulF src1 (LoadF src2)));
10683 format %{ "FMUL $dst,$src1,$src2" %}
10684 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10685 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10686 OpcReg_FPR(src1),
10687 Pop_Reg_FPR(dst) );
10688 ins_pipe( fpu_reg_reg_mem );
10689 %}
10691 // Spill to obtain 24-bit precision
10692 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10693 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10694 match(Set dst (MulF src1 src2));
10696 format %{ "FMUL $dst,$src1,$src2" %}
10697 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10698 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10699 set_instruction_start,
10700 OpcP, RMopc_Mem(secondary,src1),
10701 Pop_Mem_FPR(dst) );
10702 ins_pipe( fpu_mem_mem_mem );
10703 %}
10705 // Spill to obtain 24-bit precision
10706 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10707 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10708 match(Set dst (MulF src con));
10710 format %{ "FLD $src\n\t"
10711 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10712 "FSTP_S $dst" %}
10713 ins_encode %{
10714 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10715 __ fmul_s($constantaddress($con));
10716 __ fstp_s(Address(rsp, $dst$$disp));
10717 %}
10718 ins_pipe(fpu_mem_reg_con);
10719 %}
10720 //
10721 // This instruction does not round to 24-bits
10722 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10723 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10724 match(Set dst (MulF src con));
10726 format %{ "FLD $src\n\t"
10727 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10728 "FSTP $dst" %}
10729 ins_encode %{
10730 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10731 __ fmul_s($constantaddress($con));
10732 __ fstp_d($dst$$reg);
10733 %}
10734 ins_pipe(fpu_reg_reg_con);
10735 %}
10738 //
10739 // MACRO1 -- subsume unshared load into mulFPR
10740 // This instruction does not round to 24-bits
10741 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10742 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10743 match(Set dst (MulF (LoadF mem1) src));
10745 format %{ "FLD $mem1 ===MACRO1===\n\t"
10746 "FMUL ST,$src\n\t"
10747 "FSTP $dst" %}
10748 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10749 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10750 OpcReg_FPR(src),
10751 Pop_Reg_FPR(dst) );
10752 ins_pipe( fpu_reg_reg_mem );
10753 %}
10754 //
10755 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10756 // This instruction does not round to 24-bits
10757 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10758 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10759 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10760 ins_cost(95);
10762 format %{ "FLD $mem1 ===MACRO2===\n\t"
10763 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10764 "FADD ST,$src2\n\t"
10765 "FSTP $dst" %}
10766 opcode(0xD9); /* LoadF D9 /0 */
10767 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10768 FMul_ST_reg(src1),
10769 FAdd_ST_reg(src2),
10770 Pop_Reg_FPR(dst) );
10771 ins_pipe( fpu_reg_mem_reg_reg );
10772 %}
10774 // MACRO3 -- addFPR a mulFPR
10775 // This instruction does not round to 24-bits. It is a '2-address'
10776 // instruction in that the result goes back to src2. This eliminates
10777 // a move from the macro; possibly the register allocator will have
10778 // to add it back (and maybe not).
10779 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10780 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10781 match(Set src2 (AddF (MulF src0 src1) src2));
10783 format %{ "FLD $src0 ===MACRO3===\n\t"
10784 "FMUL ST,$src1\n\t"
10785 "FADDP $src2,ST" %}
10786 opcode(0xD9); /* LoadF D9 /0 */
10787 ins_encode( Push_Reg_FPR(src0),
10788 FMul_ST_reg(src1),
10789 FAddP_reg_ST(src2) );
10790 ins_pipe( fpu_reg_reg_reg );
10791 %}
10793 // MACRO4 -- divFPR subFPR
10794 // This instruction does not round to 24-bits
10795 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10796 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10797 match(Set dst (DivF (SubF src2 src1) src3));
10799 format %{ "FLD $src2 ===MACRO4===\n\t"
10800 "FSUB ST,$src1\n\t"
10801 "FDIV ST,$src3\n\t"
10802 "FSTP $dst" %}
10803 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10804 ins_encode( Push_Reg_FPR(src2),
10805 subFPR_divFPR_encode(src1,src3),
10806 Pop_Reg_FPR(dst) );
10807 ins_pipe( fpu_reg_reg_reg_reg );
10808 %}
10810 // Spill to obtain 24-bit precision
10811 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10812 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10813 match(Set dst (DivF src1 src2));
10815 format %{ "FDIV $dst,$src1,$src2" %}
10816 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10817 ins_encode( Push_Reg_FPR(src1),
10818 OpcReg_FPR(src2),
10819 Pop_Mem_FPR(dst) );
10820 ins_pipe( fpu_mem_reg_reg );
10821 %}
10822 //
10823 // This instruction does not round to 24-bits
10824 instruct divFPR_reg(regFPR dst, regFPR src) %{
10825 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10826 match(Set dst (DivF dst src));
10828 format %{ "FDIV $dst,$src" %}
10829 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10830 ins_encode( Push_Reg_FPR(src),
10831 OpcP, RegOpc(dst) );
10832 ins_pipe( fpu_reg_reg );
10833 %}
10836 // Spill to obtain 24-bit precision
10837 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10838 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10839 match(Set dst (ModF src1 src2));
10840 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10842 format %{ "FMOD $dst,$src1,$src2" %}
10843 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10844 emitModDPR(),
10845 Push_Result_Mod_DPR(src2),
10846 Pop_Mem_FPR(dst));
10847 ins_pipe( pipe_slow );
10848 %}
10849 //
10850 // This instruction does not round to 24-bits
10851 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10852 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10853 match(Set dst (ModF dst src));
10854 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10856 format %{ "FMOD $dst,$src" %}
10857 ins_encode(Push_Reg_Mod_DPR(dst, src),
10858 emitModDPR(),
10859 Push_Result_Mod_DPR(src),
10860 Pop_Reg_FPR(dst));
10861 ins_pipe( pipe_slow );
10862 %}
10864 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10865 predicate(UseSSE>=1);
10866 match(Set dst (ModF src0 src1));
10867 effect(KILL rax, KILL cr);
10868 format %{ "SUB ESP,4\t # FMOD\n"
10869 "\tMOVSS [ESP+0],$src1\n"
10870 "\tFLD_S [ESP+0]\n"
10871 "\tMOVSS [ESP+0],$src0\n"
10872 "\tFLD_S [ESP+0]\n"
10873 "loop:\tFPREM\n"
10874 "\tFWAIT\n"
10875 "\tFNSTSW AX\n"
10876 "\tSAHF\n"
10877 "\tJP loop\n"
10878 "\tFSTP_S [ESP+0]\n"
10879 "\tMOVSS $dst,[ESP+0]\n"
10880 "\tADD ESP,4\n"
10881 "\tFSTP ST0\t # Restore FPU Stack"
10882 %}
10883 ins_cost(250);
10884 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10885 ins_pipe( pipe_slow );
10886 %}
10889 //----------Arithmetic Conversion Instructions---------------------------------
10890 // The conversions operations are all Alpha sorted. Please keep it that way!
10892 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10893 predicate(UseSSE==0);
10894 match(Set dst (RoundFloat src));
10895 ins_cost(125);
10896 format %{ "FST_S $dst,$src\t# F-round" %}
10897 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10898 ins_pipe( fpu_mem_reg );
10899 %}
10901 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10902 predicate(UseSSE<=1);
10903 match(Set dst (RoundDouble src));
10904 ins_cost(125);
10905 format %{ "FST_D $dst,$src\t# D-round" %}
10906 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10907 ins_pipe( fpu_mem_reg );
10908 %}
10910 // Force rounding to 24-bit precision and 6-bit exponent
10911 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10912 predicate(UseSSE==0);
10913 match(Set dst (ConvD2F src));
10914 format %{ "FST_S $dst,$src\t# F-round" %}
10915 expand %{
10916 roundFloat_mem_reg(dst,src);
10917 %}
10918 %}
10920 // Force rounding to 24-bit precision and 6-bit exponent
10921 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10922 predicate(UseSSE==1);
10923 match(Set dst (ConvD2F src));
10924 effect( KILL cr );
10925 format %{ "SUB ESP,4\n\t"
10926 "FST_S [ESP],$src\t# F-round\n\t"
10927 "MOVSS $dst,[ESP]\n\t"
10928 "ADD ESP,4" %}
10929 ins_encode %{
10930 __ subptr(rsp, 4);
10931 if ($src$$reg != FPR1L_enc) {
10932 __ fld_s($src$$reg-1);
10933 __ fstp_s(Address(rsp, 0));
10934 } else {
10935 __ fst_s(Address(rsp, 0));
10936 }
10937 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10938 __ addptr(rsp, 4);
10939 %}
10940 ins_pipe( pipe_slow );
10941 %}
10943 // Force rounding double precision to single precision
10944 instruct convD2F_reg(regF dst, regD src) %{
10945 predicate(UseSSE>=2);
10946 match(Set dst (ConvD2F src));
10947 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10948 ins_encode %{
10949 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10950 %}
10951 ins_pipe( pipe_slow );
10952 %}
10954 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10955 predicate(UseSSE==0);
10956 match(Set dst (ConvF2D src));
10957 format %{ "FST_S $dst,$src\t# D-round" %}
10958 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10959 ins_pipe( fpu_reg_reg );
10960 %}
10962 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10963 predicate(UseSSE==1);
10964 match(Set dst (ConvF2D src));
10965 format %{ "FST_D $dst,$src\t# D-round" %}
10966 expand %{
10967 roundDouble_mem_reg(dst,src);
10968 %}
10969 %}
10971 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10972 predicate(UseSSE==1);
10973 match(Set dst (ConvF2D src));
10974 effect( KILL cr );
10975 format %{ "SUB ESP,4\n\t"
10976 "MOVSS [ESP] $src\n\t"
10977 "FLD_S [ESP]\n\t"
10978 "ADD ESP,4\n\t"
10979 "FSTP $dst\t# D-round" %}
10980 ins_encode %{
10981 __ subptr(rsp, 4);
10982 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10983 __ fld_s(Address(rsp, 0));
10984 __ addptr(rsp, 4);
10985 __ fstp_d($dst$$reg);
10986 %}
10987 ins_pipe( pipe_slow );
10988 %}
10990 instruct convF2D_reg(regD dst, regF src) %{
10991 predicate(UseSSE>=2);
10992 match(Set dst (ConvF2D src));
10993 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10994 ins_encode %{
10995 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10996 %}
10997 ins_pipe( pipe_slow );
10998 %}
11000 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11001 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
11002 predicate(UseSSE<=1);
11003 match(Set dst (ConvD2I src));
11004 effect( KILL tmp, KILL cr );
11005 format %{ "FLD $src\t# Convert double to int \n\t"
11006 "FLDCW trunc mode\n\t"
11007 "SUB ESP,4\n\t"
11008 "FISTp [ESP + #0]\n\t"
11009 "FLDCW std/24-bit mode\n\t"
11010 "POP EAX\n\t"
11011 "CMP EAX,0x80000000\n\t"
11012 "JNE,s fast\n\t"
11013 "FLD_D $src\n\t"
11014 "CALL d2i_wrapper\n"
11015 "fast:" %}
11016 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
11017 ins_pipe( pipe_slow );
11018 %}
11020 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11021 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11022 predicate(UseSSE>=2);
11023 match(Set dst (ConvD2I src));
11024 effect( KILL tmp, KILL cr );
11025 format %{ "CVTTSD2SI $dst, $src\n\t"
11026 "CMP $dst,0x80000000\n\t"
11027 "JNE,s fast\n\t"
11028 "SUB ESP, 8\n\t"
11029 "MOVSD [ESP], $src\n\t"
11030 "FLD_D [ESP]\n\t"
11031 "ADD ESP, 8\n\t"
11032 "CALL d2i_wrapper\n"
11033 "fast:" %}
11034 ins_encode %{
11035 Label fast;
11036 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
11037 __ cmpl($dst$$Register, 0x80000000);
11038 __ jccb(Assembler::notEqual, fast);
11039 __ subptr(rsp, 8);
11040 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11041 __ fld_d(Address(rsp, 0));
11042 __ addptr(rsp, 8);
11043 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11044 __ bind(fast);
11045 %}
11046 ins_pipe( pipe_slow );
11047 %}
11049 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
11050 predicate(UseSSE<=1);
11051 match(Set dst (ConvD2L src));
11052 effect( KILL cr );
11053 format %{ "FLD $src\t# Convert double to long\n\t"
11054 "FLDCW trunc mode\n\t"
11055 "SUB ESP,8\n\t"
11056 "FISTp [ESP + #0]\n\t"
11057 "FLDCW std/24-bit mode\n\t"
11058 "POP EAX\n\t"
11059 "POP EDX\n\t"
11060 "CMP EDX,0x80000000\n\t"
11061 "JNE,s fast\n\t"
11062 "TEST EAX,EAX\n\t"
11063 "JNE,s fast\n\t"
11064 "FLD $src\n\t"
11065 "CALL d2l_wrapper\n"
11066 "fast:" %}
11067 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
11068 ins_pipe( pipe_slow );
11069 %}
11071 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11072 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11073 predicate (UseSSE>=2);
11074 match(Set dst (ConvD2L src));
11075 effect( KILL cr );
11076 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11077 "MOVSD [ESP],$src\n\t"
11078 "FLD_D [ESP]\n\t"
11079 "FLDCW trunc mode\n\t"
11080 "FISTp [ESP + #0]\n\t"
11081 "FLDCW std/24-bit mode\n\t"
11082 "POP EAX\n\t"
11083 "POP EDX\n\t"
11084 "CMP EDX,0x80000000\n\t"
11085 "JNE,s fast\n\t"
11086 "TEST EAX,EAX\n\t"
11087 "JNE,s fast\n\t"
11088 "SUB ESP,8\n\t"
11089 "MOVSD [ESP],$src\n\t"
11090 "FLD_D [ESP]\n\t"
11091 "ADD ESP,8\n\t"
11092 "CALL d2l_wrapper\n"
11093 "fast:" %}
11094 ins_encode %{
11095 Label fast;
11096 __ subptr(rsp, 8);
11097 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11098 __ fld_d(Address(rsp, 0));
11099 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11100 __ fistp_d(Address(rsp, 0));
11101 // Restore the rounding mode, mask the exception
11102 if (Compile::current()->in_24_bit_fp_mode()) {
11103 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11104 } else {
11105 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11106 }
11107 // Load the converted long, adjust CPU stack
11108 __ pop(rax);
11109 __ pop(rdx);
11110 __ cmpl(rdx, 0x80000000);
11111 __ jccb(Assembler::notEqual, fast);
11112 __ testl(rax, rax);
11113 __ jccb(Assembler::notEqual, fast);
11114 __ subptr(rsp, 8);
11115 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11116 __ fld_d(Address(rsp, 0));
11117 __ addptr(rsp, 8);
11118 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11119 __ bind(fast);
11120 %}
11121 ins_pipe( pipe_slow );
11122 %}
11124 // Convert a double to an int. Java semantics require we do complex
11125 // manglations in the corner cases. So we set the rounding mode to
11126 // 'zero', store the darned double down as an int, and reset the
11127 // rounding mode to 'nearest'. The hardware stores a flag value down
11128 // if we would overflow or converted a NAN; we check for this and
11129 // and go the slow path if needed.
11130 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
11131 predicate(UseSSE==0);
11132 match(Set dst (ConvF2I src));
11133 effect( KILL tmp, KILL cr );
11134 format %{ "FLD $src\t# Convert float to int \n\t"
11135 "FLDCW trunc mode\n\t"
11136 "SUB ESP,4\n\t"
11137 "FISTp [ESP + #0]\n\t"
11138 "FLDCW std/24-bit mode\n\t"
11139 "POP EAX\n\t"
11140 "CMP EAX,0x80000000\n\t"
11141 "JNE,s fast\n\t"
11142 "FLD $src\n\t"
11143 "CALL d2i_wrapper\n"
11144 "fast:" %}
11145 // DPR2I_encoding works for FPR2I
11146 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
11147 ins_pipe( pipe_slow );
11148 %}
11150 // Convert a float in xmm to an int reg.
11151 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11152 predicate(UseSSE>=1);
11153 match(Set dst (ConvF2I src));
11154 effect( KILL tmp, KILL cr );
11155 format %{ "CVTTSS2SI $dst, $src\n\t"
11156 "CMP $dst,0x80000000\n\t"
11157 "JNE,s fast\n\t"
11158 "SUB ESP, 4\n\t"
11159 "MOVSS [ESP], $src\n\t"
11160 "FLD [ESP]\n\t"
11161 "ADD ESP, 4\n\t"
11162 "CALL d2i_wrapper\n"
11163 "fast:" %}
11164 ins_encode %{
11165 Label fast;
11166 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11167 __ cmpl($dst$$Register, 0x80000000);
11168 __ jccb(Assembler::notEqual, fast);
11169 __ subptr(rsp, 4);
11170 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11171 __ fld_s(Address(rsp, 0));
11172 __ addptr(rsp, 4);
11173 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11174 __ bind(fast);
11175 %}
11176 ins_pipe( pipe_slow );
11177 %}
11179 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11180 predicate(UseSSE==0);
11181 match(Set dst (ConvF2L src));
11182 effect( KILL cr );
11183 format %{ "FLD $src\t# Convert float to long\n\t"
11184 "FLDCW trunc mode\n\t"
11185 "SUB ESP,8\n\t"
11186 "FISTp [ESP + #0]\n\t"
11187 "FLDCW std/24-bit mode\n\t"
11188 "POP EAX\n\t"
11189 "POP EDX\n\t"
11190 "CMP EDX,0x80000000\n\t"
11191 "JNE,s fast\n\t"
11192 "TEST EAX,EAX\n\t"
11193 "JNE,s fast\n\t"
11194 "FLD $src\n\t"
11195 "CALL d2l_wrapper\n"
11196 "fast:" %}
11197 // DPR2L_encoding works for FPR2L
11198 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11199 ins_pipe( pipe_slow );
11200 %}
11202 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11203 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11204 predicate (UseSSE>=1);
11205 match(Set dst (ConvF2L src));
11206 effect( KILL cr );
11207 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11208 "MOVSS [ESP],$src\n\t"
11209 "FLD_S [ESP]\n\t"
11210 "FLDCW trunc mode\n\t"
11211 "FISTp [ESP + #0]\n\t"
11212 "FLDCW std/24-bit mode\n\t"
11213 "POP EAX\n\t"
11214 "POP EDX\n\t"
11215 "CMP EDX,0x80000000\n\t"
11216 "JNE,s fast\n\t"
11217 "TEST EAX,EAX\n\t"
11218 "JNE,s fast\n\t"
11219 "SUB ESP,4\t# Convert float to long\n\t"
11220 "MOVSS [ESP],$src\n\t"
11221 "FLD_S [ESP]\n\t"
11222 "ADD ESP,4\n\t"
11223 "CALL d2l_wrapper\n"
11224 "fast:" %}
11225 ins_encode %{
11226 Label fast;
11227 __ subptr(rsp, 8);
11228 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11229 __ fld_s(Address(rsp, 0));
11230 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11231 __ fistp_d(Address(rsp, 0));
11232 // Restore the rounding mode, mask the exception
11233 if (Compile::current()->in_24_bit_fp_mode()) {
11234 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11235 } else {
11236 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11237 }
11238 // Load the converted long, adjust CPU stack
11239 __ pop(rax);
11240 __ pop(rdx);
11241 __ cmpl(rdx, 0x80000000);
11242 __ jccb(Assembler::notEqual, fast);
11243 __ testl(rax, rax);
11244 __ jccb(Assembler::notEqual, fast);
11245 __ subptr(rsp, 4);
11246 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11247 __ fld_s(Address(rsp, 0));
11248 __ addptr(rsp, 4);
11249 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11250 __ bind(fast);
11251 %}
11252 ins_pipe( pipe_slow );
11253 %}
11255 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11256 predicate( UseSSE<=1 );
11257 match(Set dst (ConvI2D src));
11258 format %{ "FILD $src\n\t"
11259 "FSTP $dst" %}
11260 opcode(0xDB, 0x0); /* DB /0 */
11261 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11262 ins_pipe( fpu_reg_mem );
11263 %}
11265 instruct convI2D_reg(regD dst, rRegI src) %{
11266 predicate( UseSSE>=2 && !UseXmmI2D );
11267 match(Set dst (ConvI2D src));
11268 format %{ "CVTSI2SD $dst,$src" %}
11269 ins_encode %{
11270 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11271 %}
11272 ins_pipe( pipe_slow );
11273 %}
11275 instruct convI2D_mem(regD dst, memory mem) %{
11276 predicate( UseSSE>=2 );
11277 match(Set dst (ConvI2D (LoadI mem)));
11278 format %{ "CVTSI2SD $dst,$mem" %}
11279 ins_encode %{
11280 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11281 %}
11282 ins_pipe( pipe_slow );
11283 %}
11285 instruct convXI2D_reg(regD dst, rRegI src)
11286 %{
11287 predicate( UseSSE>=2 && UseXmmI2D );
11288 match(Set dst (ConvI2D src));
11290 format %{ "MOVD $dst,$src\n\t"
11291 "CVTDQ2PD $dst,$dst\t# i2d" %}
11292 ins_encode %{
11293 __ movdl($dst$$XMMRegister, $src$$Register);
11294 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11295 %}
11296 ins_pipe(pipe_slow); // XXX
11297 %}
11299 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11300 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11301 match(Set dst (ConvI2D (LoadI mem)));
11302 format %{ "FILD $mem\n\t"
11303 "FSTP $dst" %}
11304 opcode(0xDB); /* DB /0 */
11305 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11306 Pop_Reg_DPR(dst));
11307 ins_pipe( fpu_reg_mem );
11308 %}
11310 // Convert a byte to a float; no rounding step needed.
11311 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11312 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11313 match(Set dst (ConvI2F src));
11314 format %{ "FILD $src\n\t"
11315 "FSTP $dst" %}
11317 opcode(0xDB, 0x0); /* DB /0 */
11318 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11319 ins_pipe( fpu_reg_mem );
11320 %}
11322 // In 24-bit mode, force exponent rounding by storing back out
11323 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11324 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11325 match(Set dst (ConvI2F src));
11326 ins_cost(200);
11327 format %{ "FILD $src\n\t"
11328 "FSTP_S $dst" %}
11329 opcode(0xDB, 0x0); /* DB /0 */
11330 ins_encode( Push_Mem_I(src),
11331 Pop_Mem_FPR(dst));
11332 ins_pipe( fpu_mem_mem );
11333 %}
11335 // In 24-bit mode, force exponent rounding by storing back out
11336 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11337 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11338 match(Set dst (ConvI2F (LoadI mem)));
11339 ins_cost(200);
11340 format %{ "FILD $mem\n\t"
11341 "FSTP_S $dst" %}
11342 opcode(0xDB); /* DB /0 */
11343 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11344 Pop_Mem_FPR(dst));
11345 ins_pipe( fpu_mem_mem );
11346 %}
11348 // This instruction does not round to 24-bits
11349 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11350 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11351 match(Set dst (ConvI2F src));
11352 format %{ "FILD $src\n\t"
11353 "FSTP $dst" %}
11354 opcode(0xDB, 0x0); /* DB /0 */
11355 ins_encode( Push_Mem_I(src),
11356 Pop_Reg_FPR(dst));
11357 ins_pipe( fpu_reg_mem );
11358 %}
11360 // This instruction does not round to 24-bits
11361 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11362 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11363 match(Set dst (ConvI2F (LoadI mem)));
11364 format %{ "FILD $mem\n\t"
11365 "FSTP $dst" %}
11366 opcode(0xDB); /* DB /0 */
11367 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11368 Pop_Reg_FPR(dst));
11369 ins_pipe( fpu_reg_mem );
11370 %}
11372 // Convert an int to a float in xmm; no rounding step needed.
11373 instruct convI2F_reg(regF dst, rRegI src) %{
11374 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11375 match(Set dst (ConvI2F src));
11376 format %{ "CVTSI2SS $dst, $src" %}
11377 ins_encode %{
11378 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11379 %}
11380 ins_pipe( pipe_slow );
11381 %}
11383 instruct convXI2F_reg(regF dst, rRegI src)
11384 %{
11385 predicate( UseSSE>=2 && UseXmmI2F );
11386 match(Set dst (ConvI2F src));
11388 format %{ "MOVD $dst,$src\n\t"
11389 "CVTDQ2PS $dst,$dst\t# i2f" %}
11390 ins_encode %{
11391 __ movdl($dst$$XMMRegister, $src$$Register);
11392 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11393 %}
11394 ins_pipe(pipe_slow); // XXX
11395 %}
11397 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11398 match(Set dst (ConvI2L src));
11399 effect(KILL cr);
11400 ins_cost(375);
11401 format %{ "MOV $dst.lo,$src\n\t"
11402 "MOV $dst.hi,$src\n\t"
11403 "SAR $dst.hi,31" %}
11404 ins_encode(convert_int_long(dst,src));
11405 ins_pipe( ialu_reg_reg_long );
11406 %}
11408 // Zero-extend convert int to long
11409 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11410 match(Set dst (AndL (ConvI2L src) mask) );
11411 effect( KILL flags );
11412 ins_cost(250);
11413 format %{ "MOV $dst.lo,$src\n\t"
11414 "XOR $dst.hi,$dst.hi" %}
11415 opcode(0x33); // XOR
11416 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11417 ins_pipe( ialu_reg_reg_long );
11418 %}
11420 // Zero-extend long
11421 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11422 match(Set dst (AndL src mask) );
11423 effect( KILL flags );
11424 ins_cost(250);
11425 format %{ "MOV $dst.lo,$src.lo\n\t"
11426 "XOR $dst.hi,$dst.hi\n\t" %}
11427 opcode(0x33); // XOR
11428 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11429 ins_pipe( ialu_reg_reg_long );
11430 %}
11432 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11433 predicate (UseSSE<=1);
11434 match(Set dst (ConvL2D src));
11435 effect( KILL cr );
11436 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11437 "PUSH $src.lo\n\t"
11438 "FILD ST,[ESP + #0]\n\t"
11439 "ADD ESP,8\n\t"
11440 "FSTP_D $dst\t# D-round" %}
11441 opcode(0xDF, 0x5); /* DF /5 */
11442 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11443 ins_pipe( pipe_slow );
11444 %}
11446 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11447 predicate (UseSSE>=2);
11448 match(Set dst (ConvL2D src));
11449 effect( KILL cr );
11450 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11451 "PUSH $src.lo\n\t"
11452 "FILD_D [ESP]\n\t"
11453 "FSTP_D [ESP]\n\t"
11454 "MOVSD $dst,[ESP]\n\t"
11455 "ADD ESP,8" %}
11456 opcode(0xDF, 0x5); /* DF /5 */
11457 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11458 ins_pipe( pipe_slow );
11459 %}
11461 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11462 predicate (UseSSE>=1);
11463 match(Set dst (ConvL2F src));
11464 effect( KILL cr );
11465 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11466 "PUSH $src.lo\n\t"
11467 "FILD_D [ESP]\n\t"
11468 "FSTP_S [ESP]\n\t"
11469 "MOVSS $dst,[ESP]\n\t"
11470 "ADD ESP,8" %}
11471 opcode(0xDF, 0x5); /* DF /5 */
11472 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11473 ins_pipe( pipe_slow );
11474 %}
11476 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11477 match(Set dst (ConvL2F src));
11478 effect( KILL cr );
11479 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11480 "PUSH $src.lo\n\t"
11481 "FILD ST,[ESP + #0]\n\t"
11482 "ADD ESP,8\n\t"
11483 "FSTP_S $dst\t# F-round" %}
11484 opcode(0xDF, 0x5); /* DF /5 */
11485 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11486 ins_pipe( pipe_slow );
11487 %}
11489 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11490 match(Set dst (ConvL2I src));
11491 effect( DEF dst, USE src );
11492 format %{ "MOV $dst,$src.lo" %}
11493 ins_encode(enc_CopyL_Lo(dst,src));
11494 ins_pipe( ialu_reg_reg );
11495 %}
11498 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11499 match(Set dst (MoveF2I src));
11500 effect( DEF dst, USE src );
11501 ins_cost(100);
11502 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11503 ins_encode %{
11504 __ movl($dst$$Register, Address(rsp, $src$$disp));
11505 %}
11506 ins_pipe( ialu_reg_mem );
11507 %}
11509 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11510 predicate(UseSSE==0);
11511 match(Set dst (MoveF2I src));
11512 effect( DEF dst, USE src );
11514 ins_cost(125);
11515 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11516 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11517 ins_pipe( fpu_mem_reg );
11518 %}
11520 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11521 predicate(UseSSE>=1);
11522 match(Set dst (MoveF2I src));
11523 effect( DEF dst, USE src );
11525 ins_cost(95);
11526 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11527 ins_encode %{
11528 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11529 %}
11530 ins_pipe( pipe_slow );
11531 %}
11533 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11534 predicate(UseSSE>=2);
11535 match(Set dst (MoveF2I src));
11536 effect( DEF dst, USE src );
11537 ins_cost(85);
11538 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11539 ins_encode %{
11540 __ movdl($dst$$Register, $src$$XMMRegister);
11541 %}
11542 ins_pipe( pipe_slow );
11543 %}
11545 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11546 match(Set dst (MoveI2F src));
11547 effect( DEF dst, USE src );
11549 ins_cost(100);
11550 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11551 ins_encode %{
11552 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11553 %}
11554 ins_pipe( ialu_mem_reg );
11555 %}
11558 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11559 predicate(UseSSE==0);
11560 match(Set dst (MoveI2F src));
11561 effect(DEF dst, USE src);
11563 ins_cost(125);
11564 format %{ "FLD_S $src\n\t"
11565 "FSTP $dst\t# MoveI2F_stack_reg" %}
11566 opcode(0xD9); /* D9 /0, FLD m32real */
11567 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11568 Pop_Reg_FPR(dst) );
11569 ins_pipe( fpu_reg_mem );
11570 %}
11572 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11573 predicate(UseSSE>=1);
11574 match(Set dst (MoveI2F src));
11575 effect( DEF dst, USE src );
11577 ins_cost(95);
11578 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11579 ins_encode %{
11580 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11581 %}
11582 ins_pipe( pipe_slow );
11583 %}
11585 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11586 predicate(UseSSE>=2);
11587 match(Set dst (MoveI2F src));
11588 effect( DEF dst, USE src );
11590 ins_cost(85);
11591 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11592 ins_encode %{
11593 __ movdl($dst$$XMMRegister, $src$$Register);
11594 %}
11595 ins_pipe( pipe_slow );
11596 %}
11598 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11599 match(Set dst (MoveD2L src));
11600 effect(DEF dst, USE src);
11602 ins_cost(250);
11603 format %{ "MOV $dst.lo,$src\n\t"
11604 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11605 opcode(0x8B, 0x8B);
11606 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11607 ins_pipe( ialu_mem_long_reg );
11608 %}
11610 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11611 predicate(UseSSE<=1);
11612 match(Set dst (MoveD2L src));
11613 effect(DEF dst, USE src);
11615 ins_cost(125);
11616 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11617 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11618 ins_pipe( fpu_mem_reg );
11619 %}
11621 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11622 predicate(UseSSE>=2);
11623 match(Set dst (MoveD2L src));
11624 effect(DEF dst, USE src);
11625 ins_cost(95);
11626 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11627 ins_encode %{
11628 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11629 %}
11630 ins_pipe( pipe_slow );
11631 %}
11633 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11634 predicate(UseSSE>=2);
11635 match(Set dst (MoveD2L src));
11636 effect(DEF dst, USE src, TEMP tmp);
11637 ins_cost(85);
11638 format %{ "MOVD $dst.lo,$src\n\t"
11639 "PSHUFLW $tmp,$src,0x4E\n\t"
11640 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11641 ins_encode %{
11642 __ movdl($dst$$Register, $src$$XMMRegister);
11643 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11644 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11645 %}
11646 ins_pipe( pipe_slow );
11647 %}
11649 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11650 match(Set dst (MoveL2D src));
11651 effect(DEF dst, USE src);
11653 ins_cost(200);
11654 format %{ "MOV $dst,$src.lo\n\t"
11655 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11656 opcode(0x89, 0x89);
11657 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11658 ins_pipe( ialu_mem_long_reg );
11659 %}
11662 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11663 predicate(UseSSE<=1);
11664 match(Set dst (MoveL2D src));
11665 effect(DEF dst, USE src);
11666 ins_cost(125);
11668 format %{ "FLD_D $src\n\t"
11669 "FSTP $dst\t# MoveL2D_stack_reg" %}
11670 opcode(0xDD); /* DD /0, FLD m64real */
11671 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11672 Pop_Reg_DPR(dst) );
11673 ins_pipe( fpu_reg_mem );
11674 %}
11677 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11678 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11679 match(Set dst (MoveL2D src));
11680 effect(DEF dst, USE src);
11682 ins_cost(95);
11683 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11684 ins_encode %{
11685 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11686 %}
11687 ins_pipe( pipe_slow );
11688 %}
11690 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11691 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11692 match(Set dst (MoveL2D src));
11693 effect(DEF dst, USE src);
11695 ins_cost(95);
11696 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11697 ins_encode %{
11698 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11699 %}
11700 ins_pipe( pipe_slow );
11701 %}
11703 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11704 predicate(UseSSE>=2);
11705 match(Set dst (MoveL2D src));
11706 effect(TEMP dst, USE src, TEMP tmp);
11707 ins_cost(85);
11708 format %{ "MOVD $dst,$src.lo\n\t"
11709 "MOVD $tmp,$src.hi\n\t"
11710 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11711 ins_encode %{
11712 __ movdl($dst$$XMMRegister, $src$$Register);
11713 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11714 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11715 %}
11716 ins_pipe( pipe_slow );
11717 %}
11720 // =======================================================================
11721 // fast clearing of an array
11722 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11723 predicate(!UseFastStosb);
11724 match(Set dummy (ClearArray cnt base));
11725 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11726 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11727 "SHL ECX,1\t# Convert doublewords to words\n\t"
11728 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11729 ins_encode %{
11730 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11731 %}
11732 ins_pipe( pipe_slow );
11733 %}
11735 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11736 predicate(UseFastStosb);
11737 match(Set dummy (ClearArray cnt base));
11738 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11739 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11740 "SHL ECX,3\t# Convert doublewords to bytes\n\t"
11741 "REP STOSB\t# store EAX into [EDI++] while ECX--" %}
11742 ins_encode %{
11743 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11744 %}
11745 ins_pipe( pipe_slow );
11746 %}
11748 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11749 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11750 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11751 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11753 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11754 ins_encode %{
11755 __ string_compare($str1$$Register, $str2$$Register,
11756 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11757 $tmp1$$XMMRegister);
11758 %}
11759 ins_pipe( pipe_slow );
11760 %}
11762 // fast string equals
11763 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11764 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11765 match(Set result (StrEquals (Binary str1 str2) cnt));
11766 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11768 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11769 ins_encode %{
11770 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11771 $cnt$$Register, $result$$Register, $tmp3$$Register,
11772 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11773 %}
11774 ins_pipe( pipe_slow );
11775 %}
11777 // fast search of substring with known size.
11778 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11779 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11780 predicate(UseSSE42Intrinsics);
11781 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11782 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11784 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11785 ins_encode %{
11786 int icnt2 = (int)$int_cnt2$$constant;
11787 if (icnt2 >= 8) {
11788 // IndexOf for constant substrings with size >= 8 elements
11789 // which don't need to be loaded through stack.
11790 __ string_indexofC8($str1$$Register, $str2$$Register,
11791 $cnt1$$Register, $cnt2$$Register,
11792 icnt2, $result$$Register,
11793 $vec$$XMMRegister, $tmp$$Register);
11794 } else {
11795 // Small strings are loaded through stack if they cross page boundary.
11796 __ string_indexof($str1$$Register, $str2$$Register,
11797 $cnt1$$Register, $cnt2$$Register,
11798 icnt2, $result$$Register,
11799 $vec$$XMMRegister, $tmp$$Register);
11800 }
11801 %}
11802 ins_pipe( pipe_slow );
11803 %}
11805 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11806 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11807 predicate(UseSSE42Intrinsics);
11808 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11809 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11811 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11812 ins_encode %{
11813 __ string_indexof($str1$$Register, $str2$$Register,
11814 $cnt1$$Register, $cnt2$$Register,
11815 (-1), $result$$Register,
11816 $vec$$XMMRegister, $tmp$$Register);
11817 %}
11818 ins_pipe( pipe_slow );
11819 %}
11821 // fast array equals
11822 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11823 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11824 %{
11825 match(Set result (AryEq ary1 ary2));
11826 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11827 //ins_cost(300);
11829 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11830 ins_encode %{
11831 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11832 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11833 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11834 %}
11835 ins_pipe( pipe_slow );
11836 %}
11838 // encode char[] to byte[] in ISO_8859_1
11839 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len,
11840 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
11841 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{
11842 match(Set result (EncodeISOArray src (Binary dst len)));
11843 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11845 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %}
11846 ins_encode %{
11847 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11848 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11849 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11850 %}
11851 ins_pipe( pipe_slow );
11852 %}
11855 //----------Control Flow Instructions------------------------------------------
11856 // Signed compare Instructions
11857 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11858 match(Set cr (CmpI op1 op2));
11859 effect( DEF cr, USE op1, USE op2 );
11860 format %{ "CMP $op1,$op2" %}
11861 opcode(0x3B); /* Opcode 3B /r */
11862 ins_encode( OpcP, RegReg( op1, op2) );
11863 ins_pipe( ialu_cr_reg_reg );
11864 %}
11866 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11867 match(Set cr (CmpI op1 op2));
11868 effect( DEF cr, USE op1 );
11869 format %{ "CMP $op1,$op2" %}
11870 opcode(0x81,0x07); /* Opcode 81 /7 */
11871 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11872 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11873 ins_pipe( ialu_cr_reg_imm );
11874 %}
11876 // Cisc-spilled version of cmpI_eReg
11877 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11878 match(Set cr (CmpI op1 (LoadI op2)));
11880 format %{ "CMP $op1,$op2" %}
11881 ins_cost(500);
11882 opcode(0x3B); /* Opcode 3B /r */
11883 ins_encode( OpcP, RegMem( op1, op2) );
11884 ins_pipe( ialu_cr_reg_mem );
11885 %}
11887 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11888 match(Set cr (CmpI src zero));
11889 effect( DEF cr, USE src );
11891 format %{ "TEST $src,$src" %}
11892 opcode(0x85);
11893 ins_encode( OpcP, RegReg( src, src ) );
11894 ins_pipe( ialu_cr_reg_imm );
11895 %}
11897 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11898 match(Set cr (CmpI (AndI src con) zero));
11900 format %{ "TEST $src,$con" %}
11901 opcode(0xF7,0x00);
11902 ins_encode( OpcP, RegOpc(src), Con32(con) );
11903 ins_pipe( ialu_cr_reg_imm );
11904 %}
11906 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11907 match(Set cr (CmpI (AndI src mem) zero));
11909 format %{ "TEST $src,$mem" %}
11910 opcode(0x85);
11911 ins_encode( OpcP, RegMem( src, mem ) );
11912 ins_pipe( ialu_cr_reg_mem );
11913 %}
11915 // Unsigned compare Instructions; really, same as signed except they
11916 // produce an eFlagsRegU instead of eFlagsReg.
11917 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11918 match(Set cr (CmpU op1 op2));
11920 format %{ "CMPu $op1,$op2" %}
11921 opcode(0x3B); /* Opcode 3B /r */
11922 ins_encode( OpcP, RegReg( op1, op2) );
11923 ins_pipe( ialu_cr_reg_reg );
11924 %}
11926 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11927 match(Set cr (CmpU op1 op2));
11929 format %{ "CMPu $op1,$op2" %}
11930 opcode(0x81,0x07); /* Opcode 81 /7 */
11931 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11932 ins_pipe( ialu_cr_reg_imm );
11933 %}
11935 // // Cisc-spilled version of cmpU_eReg
11936 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11937 match(Set cr (CmpU op1 (LoadI op2)));
11939 format %{ "CMPu $op1,$op2" %}
11940 ins_cost(500);
11941 opcode(0x3B); /* Opcode 3B /r */
11942 ins_encode( OpcP, RegMem( op1, op2) );
11943 ins_pipe( ialu_cr_reg_mem );
11944 %}
11946 // // Cisc-spilled version of cmpU_eReg
11947 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11948 // match(Set cr (CmpU (LoadI op1) op2));
11949 //
11950 // format %{ "CMPu $op1,$op2" %}
11951 // ins_cost(500);
11952 // opcode(0x39); /* Opcode 39 /r */
11953 // ins_encode( OpcP, RegMem( op1, op2) );
11954 //%}
11956 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11957 match(Set cr (CmpU src zero));
11959 format %{ "TESTu $src,$src" %}
11960 opcode(0x85);
11961 ins_encode( OpcP, RegReg( src, src ) );
11962 ins_pipe( ialu_cr_reg_imm );
11963 %}
11965 // Unsigned pointer compare Instructions
11966 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11967 match(Set cr (CmpP op1 op2));
11969 format %{ "CMPu $op1,$op2" %}
11970 opcode(0x3B); /* Opcode 3B /r */
11971 ins_encode( OpcP, RegReg( op1, op2) );
11972 ins_pipe( ialu_cr_reg_reg );
11973 %}
11975 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11976 match(Set cr (CmpP op1 op2));
11978 format %{ "CMPu $op1,$op2" %}
11979 opcode(0x81,0x07); /* Opcode 81 /7 */
11980 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11981 ins_pipe( ialu_cr_reg_imm );
11982 %}
11984 // // Cisc-spilled version of cmpP_eReg
11985 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11986 match(Set cr (CmpP op1 (LoadP op2)));
11988 format %{ "CMPu $op1,$op2" %}
11989 ins_cost(500);
11990 opcode(0x3B); /* Opcode 3B /r */
11991 ins_encode( OpcP, RegMem( op1, op2) );
11992 ins_pipe( ialu_cr_reg_mem );
11993 %}
11995 // // Cisc-spilled version of cmpP_eReg
11996 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11997 // match(Set cr (CmpP (LoadP op1) op2));
11998 //
11999 // format %{ "CMPu $op1,$op2" %}
12000 // ins_cost(500);
12001 // opcode(0x39); /* Opcode 39 /r */
12002 // ins_encode( OpcP, RegMem( op1, op2) );
12003 //%}
12005 // Compare raw pointer (used in out-of-heap check).
12006 // Only works because non-oop pointers must be raw pointers
12007 // and raw pointers have no anti-dependencies.
12008 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12009 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
12010 match(Set cr (CmpP op1 (LoadP op2)));
12012 format %{ "CMPu $op1,$op2" %}
12013 opcode(0x3B); /* Opcode 3B /r */
12014 ins_encode( OpcP, RegMem( op1, op2) );
12015 ins_pipe( ialu_cr_reg_mem );
12016 %}
12018 //
12019 // This will generate a signed flags result. This should be ok
12020 // since any compare to a zero should be eq/neq.
12021 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12022 match(Set cr (CmpP src zero));
12024 format %{ "TEST $src,$src" %}
12025 opcode(0x85);
12026 ins_encode( OpcP, RegReg( src, src ) );
12027 ins_pipe( ialu_cr_reg_imm );
12028 %}
12030 // Cisc-spilled version of testP_reg
12031 // This will generate a signed flags result. This should be ok
12032 // since any compare to a zero should be eq/neq.
12033 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12034 match(Set cr (CmpP (LoadP op) zero));
12036 format %{ "TEST $op,0xFFFFFFFF" %}
12037 ins_cost(500);
12038 opcode(0xF7); /* Opcode F7 /0 */
12039 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12040 ins_pipe( ialu_cr_reg_imm );
12041 %}
12043 // Yanked all unsigned pointer compare operations.
12044 // Pointer compares are done with CmpP which is already unsigned.
12046 //----------Max and Min--------------------------------------------------------
12047 // Min Instructions
12048 ////
12049 // *** Min and Max using the conditional move are slower than the
12050 // *** branch version on a Pentium III.
12051 // // Conditional move for min
12052 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
12053 // effect( USE_DEF op2, USE op1, USE cr );
12054 // format %{ "CMOVlt $op2,$op1\t! min" %}
12055 // opcode(0x4C,0x0F);
12056 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12057 // ins_pipe( pipe_cmov_reg );
12058 //%}
12059 //
12060 //// Min Register with Register (P6 version)
12061 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
12062 // predicate(VM_Version::supports_cmov() );
12063 // match(Set op2 (MinI op1 op2));
12064 // ins_cost(200);
12065 // expand %{
12066 // eFlagsReg cr;
12067 // compI_eReg(cr,op1,op2);
12068 // cmovI_reg_lt(op2,op1,cr);
12069 // %}
12070 //%}
12072 // Min Register with Register (generic version)
12073 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
12074 match(Set dst (MinI dst src));
12075 effect(KILL flags);
12076 ins_cost(300);
12078 format %{ "MIN $dst,$src" %}
12079 opcode(0xCC);
12080 ins_encode( min_enc(dst,src) );
12081 ins_pipe( pipe_slow );
12082 %}
12084 // Max Register with Register
12085 // *** Min and Max using the conditional move are slower than the
12086 // *** branch version on a Pentium III.
12087 // // Conditional move for max
12088 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
12089 // effect( USE_DEF op2, USE op1, USE cr );
12090 // format %{ "CMOVgt $op2,$op1\t! max" %}
12091 // opcode(0x4F,0x0F);
12092 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12093 // ins_pipe( pipe_cmov_reg );
12094 //%}
12095 //
12096 // // Max Register with Register (P6 version)
12097 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
12098 // predicate(VM_Version::supports_cmov() );
12099 // match(Set op2 (MaxI op1 op2));
12100 // ins_cost(200);
12101 // expand %{
12102 // eFlagsReg cr;
12103 // compI_eReg(cr,op1,op2);
12104 // cmovI_reg_gt(op2,op1,cr);
12105 // %}
12106 //%}
12108 // Max Register with Register (generic version)
12109 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
12110 match(Set dst (MaxI dst src));
12111 effect(KILL flags);
12112 ins_cost(300);
12114 format %{ "MAX $dst,$src" %}
12115 opcode(0xCC);
12116 ins_encode( max_enc(dst,src) );
12117 ins_pipe( pipe_slow );
12118 %}
12120 // ============================================================================
12121 // Counted Loop limit node which represents exact final iterator value.
12122 // Note: the resulting value should fit into integer range since
12123 // counted loops have limit check on overflow.
12124 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
12125 match(Set limit (LoopLimit (Binary init limit) stride));
12126 effect(TEMP limit_hi, TEMP tmp, KILL flags);
12127 ins_cost(300);
12129 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
12130 ins_encode %{
12131 int strd = (int)$stride$$constant;
12132 assert(strd != 1 && strd != -1, "sanity");
12133 int m1 = (strd > 0) ? 1 : -1;
12134 // Convert limit to long (EAX:EDX)
12135 __ cdql();
12136 // Convert init to long (init:tmp)
12137 __ movl($tmp$$Register, $init$$Register);
12138 __ sarl($tmp$$Register, 31);
12139 // $limit - $init
12140 __ subl($limit$$Register, $init$$Register);
12141 __ sbbl($limit_hi$$Register, $tmp$$Register);
12142 // + ($stride - 1)
12143 if (strd > 0) {
12144 __ addl($limit$$Register, (strd - 1));
12145 __ adcl($limit_hi$$Register, 0);
12146 __ movl($tmp$$Register, strd);
12147 } else {
12148 __ addl($limit$$Register, (strd + 1));
12149 __ adcl($limit_hi$$Register, -1);
12150 __ lneg($limit_hi$$Register, $limit$$Register);
12151 __ movl($tmp$$Register, -strd);
12152 }
12153 // signed devision: (EAX:EDX) / pos_stride
12154 __ idivl($tmp$$Register);
12155 if (strd < 0) {
12156 // restore sign
12157 __ negl($tmp$$Register);
12158 }
12159 // (EAX) * stride
12160 __ mull($tmp$$Register);
12161 // + init (ignore upper bits)
12162 __ addl($limit$$Register, $init$$Register);
12163 %}
12164 ins_pipe( pipe_slow );
12165 %}
12167 // ============================================================================
12168 // Branch Instructions
12169 // Jump Table
12170 instruct jumpXtnd(rRegI switch_val) %{
12171 match(Jump switch_val);
12172 ins_cost(350);
12173 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
12174 ins_encode %{
12175 // Jump to Address(table_base + switch_reg)
12176 Address index(noreg, $switch_val$$Register, Address::times_1);
12177 __ jump(ArrayAddress($constantaddress, index));
12178 %}
12179 ins_pipe(pipe_jmp);
12180 %}
12182 // Jump Direct - Label defines a relative address from JMP+1
12183 instruct jmpDir(label labl) %{
12184 match(Goto);
12185 effect(USE labl);
12187 ins_cost(300);
12188 format %{ "JMP $labl" %}
12189 size(5);
12190 ins_encode %{
12191 Label* L = $labl$$label;
12192 __ jmp(*L, false); // Always long jump
12193 %}
12194 ins_pipe( pipe_jmp );
12195 %}
12197 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12198 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12199 match(If cop cr);
12200 effect(USE labl);
12202 ins_cost(300);
12203 format %{ "J$cop $labl" %}
12204 size(6);
12205 ins_encode %{
12206 Label* L = $labl$$label;
12207 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12208 %}
12209 ins_pipe( pipe_jcc );
12210 %}
12212 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12213 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12214 match(CountedLoopEnd cop cr);
12215 effect(USE labl);
12217 ins_cost(300);
12218 format %{ "J$cop $labl\t# Loop end" %}
12219 size(6);
12220 ins_encode %{
12221 Label* L = $labl$$label;
12222 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12223 %}
12224 ins_pipe( pipe_jcc );
12225 %}
12227 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12228 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12229 match(CountedLoopEnd cop cmp);
12230 effect(USE labl);
12232 ins_cost(300);
12233 format %{ "J$cop,u $labl\t# Loop end" %}
12234 size(6);
12235 ins_encode %{
12236 Label* L = $labl$$label;
12237 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12238 %}
12239 ins_pipe( pipe_jcc );
12240 %}
12242 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12243 match(CountedLoopEnd cop cmp);
12244 effect(USE labl);
12246 ins_cost(200);
12247 format %{ "J$cop,u $labl\t# Loop end" %}
12248 size(6);
12249 ins_encode %{
12250 Label* L = $labl$$label;
12251 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12252 %}
12253 ins_pipe( pipe_jcc );
12254 %}
12256 // Jump Direct Conditional - using unsigned comparison
12257 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12258 match(If cop cmp);
12259 effect(USE labl);
12261 ins_cost(300);
12262 format %{ "J$cop,u $labl" %}
12263 size(6);
12264 ins_encode %{
12265 Label* L = $labl$$label;
12266 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12267 %}
12268 ins_pipe(pipe_jcc);
12269 %}
12271 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12272 match(If cop cmp);
12273 effect(USE labl);
12275 ins_cost(200);
12276 format %{ "J$cop,u $labl" %}
12277 size(6);
12278 ins_encode %{
12279 Label* L = $labl$$label;
12280 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12281 %}
12282 ins_pipe(pipe_jcc);
12283 %}
12285 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12286 match(If cop cmp);
12287 effect(USE labl);
12289 ins_cost(200);
12290 format %{ $$template
12291 if ($cop$$cmpcode == Assembler::notEqual) {
12292 $$emit$$"JP,u $labl\n\t"
12293 $$emit$$"J$cop,u $labl"
12294 } else {
12295 $$emit$$"JP,u done\n\t"
12296 $$emit$$"J$cop,u $labl\n\t"
12297 $$emit$$"done:"
12298 }
12299 %}
12300 ins_encode %{
12301 Label* l = $labl$$label;
12302 if ($cop$$cmpcode == Assembler::notEqual) {
12303 __ jcc(Assembler::parity, *l, false);
12304 __ jcc(Assembler::notEqual, *l, false);
12305 } else if ($cop$$cmpcode == Assembler::equal) {
12306 Label done;
12307 __ jccb(Assembler::parity, done);
12308 __ jcc(Assembler::equal, *l, false);
12309 __ bind(done);
12310 } else {
12311 ShouldNotReachHere();
12312 }
12313 %}
12314 ins_pipe(pipe_jcc);
12315 %}
12317 // ============================================================================
12318 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12319 // array for an instance of the superklass. Set a hidden internal cache on a
12320 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12321 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12322 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12323 match(Set result (PartialSubtypeCheck sub super));
12324 effect( KILL rcx, KILL cr );
12326 ins_cost(1100); // slightly larger than the next version
12327 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12328 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12329 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12330 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12331 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12332 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12333 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12334 "miss:\t" %}
12336 opcode(0x1); // Force a XOR of EDI
12337 ins_encode( enc_PartialSubtypeCheck() );
12338 ins_pipe( pipe_slow );
12339 %}
12341 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12342 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12343 effect( KILL rcx, KILL result );
12345 ins_cost(1000);
12346 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12347 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12348 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12349 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12350 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12351 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12352 "miss:\t" %}
12354 opcode(0x0); // No need to XOR EDI
12355 ins_encode( enc_PartialSubtypeCheck() );
12356 ins_pipe( pipe_slow );
12357 %}
12359 // ============================================================================
12360 // Branch Instructions -- short offset versions
12361 //
12362 // These instructions are used to replace jumps of a long offset (the default
12363 // match) with jumps of a shorter offset. These instructions are all tagged
12364 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12365 // match rules in general matching. Instead, the ADLC generates a conversion
12366 // method in the MachNode which can be used to do in-place replacement of the
12367 // long variant with the shorter variant. The compiler will determine if a
12368 // branch can be taken by the is_short_branch_offset() predicate in the machine
12369 // specific code section of the file.
12371 // Jump Direct - Label defines a relative address from JMP+1
12372 instruct jmpDir_short(label labl) %{
12373 match(Goto);
12374 effect(USE labl);
12376 ins_cost(300);
12377 format %{ "JMP,s $labl" %}
12378 size(2);
12379 ins_encode %{
12380 Label* L = $labl$$label;
12381 __ jmpb(*L);
12382 %}
12383 ins_pipe( pipe_jmp );
12384 ins_short_branch(1);
12385 %}
12387 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12388 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12389 match(If cop cr);
12390 effect(USE labl);
12392 ins_cost(300);
12393 format %{ "J$cop,s $labl" %}
12394 size(2);
12395 ins_encode %{
12396 Label* L = $labl$$label;
12397 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12398 %}
12399 ins_pipe( pipe_jcc );
12400 ins_short_branch(1);
12401 %}
12403 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12404 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12405 match(CountedLoopEnd cop cr);
12406 effect(USE labl);
12408 ins_cost(300);
12409 format %{ "J$cop,s $labl\t# Loop end" %}
12410 size(2);
12411 ins_encode %{
12412 Label* L = $labl$$label;
12413 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12414 %}
12415 ins_pipe( pipe_jcc );
12416 ins_short_branch(1);
12417 %}
12419 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12420 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12421 match(CountedLoopEnd cop cmp);
12422 effect(USE labl);
12424 ins_cost(300);
12425 format %{ "J$cop,us $labl\t# Loop end" %}
12426 size(2);
12427 ins_encode %{
12428 Label* L = $labl$$label;
12429 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12430 %}
12431 ins_pipe( pipe_jcc );
12432 ins_short_branch(1);
12433 %}
12435 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12436 match(CountedLoopEnd cop cmp);
12437 effect(USE labl);
12439 ins_cost(300);
12440 format %{ "J$cop,us $labl\t# Loop end" %}
12441 size(2);
12442 ins_encode %{
12443 Label* L = $labl$$label;
12444 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12445 %}
12446 ins_pipe( pipe_jcc );
12447 ins_short_branch(1);
12448 %}
12450 // Jump Direct Conditional - using unsigned comparison
12451 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12452 match(If cop cmp);
12453 effect(USE labl);
12455 ins_cost(300);
12456 format %{ "J$cop,us $labl" %}
12457 size(2);
12458 ins_encode %{
12459 Label* L = $labl$$label;
12460 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12461 %}
12462 ins_pipe( pipe_jcc );
12463 ins_short_branch(1);
12464 %}
12466 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12467 match(If cop cmp);
12468 effect(USE labl);
12470 ins_cost(300);
12471 format %{ "J$cop,us $labl" %}
12472 size(2);
12473 ins_encode %{
12474 Label* L = $labl$$label;
12475 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12476 %}
12477 ins_pipe( pipe_jcc );
12478 ins_short_branch(1);
12479 %}
12481 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12482 match(If cop cmp);
12483 effect(USE labl);
12485 ins_cost(300);
12486 format %{ $$template
12487 if ($cop$$cmpcode == Assembler::notEqual) {
12488 $$emit$$"JP,u,s $labl\n\t"
12489 $$emit$$"J$cop,u,s $labl"
12490 } else {
12491 $$emit$$"JP,u,s done\n\t"
12492 $$emit$$"J$cop,u,s $labl\n\t"
12493 $$emit$$"done:"
12494 }
12495 %}
12496 size(4);
12497 ins_encode %{
12498 Label* l = $labl$$label;
12499 if ($cop$$cmpcode == Assembler::notEqual) {
12500 __ jccb(Assembler::parity, *l);
12501 __ jccb(Assembler::notEqual, *l);
12502 } else if ($cop$$cmpcode == Assembler::equal) {
12503 Label done;
12504 __ jccb(Assembler::parity, done);
12505 __ jccb(Assembler::equal, *l);
12506 __ bind(done);
12507 } else {
12508 ShouldNotReachHere();
12509 }
12510 %}
12511 ins_pipe(pipe_jcc);
12512 ins_short_branch(1);
12513 %}
12515 // ============================================================================
12516 // Long Compare
12517 //
12518 // Currently we hold longs in 2 registers. Comparing such values efficiently
12519 // is tricky. The flavor of compare used depends on whether we are testing
12520 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12521 // The GE test is the negated LT test. The LE test can be had by commuting
12522 // the operands (yielding a GE test) and then negating; negate again for the
12523 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12524 // NE test is negated from that.
12526 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12527 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12528 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12529 // are collapsed internally in the ADLC's dfa-gen code. The match for
12530 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12531 // foo match ends up with the wrong leaf. One fix is to not match both
12532 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12533 // both forms beat the trinary form of long-compare and both are very useful
12534 // on Intel which has so few registers.
12536 // Manifest a CmpL result in an integer register. Very painful.
12537 // This is the test to avoid.
12538 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12539 match(Set dst (CmpL3 src1 src2));
12540 effect( KILL flags );
12541 ins_cost(1000);
12542 format %{ "XOR $dst,$dst\n\t"
12543 "CMP $src1.hi,$src2.hi\n\t"
12544 "JLT,s m_one\n\t"
12545 "JGT,s p_one\n\t"
12546 "CMP $src1.lo,$src2.lo\n\t"
12547 "JB,s m_one\n\t"
12548 "JEQ,s done\n"
12549 "p_one:\tINC $dst\n\t"
12550 "JMP,s done\n"
12551 "m_one:\tDEC $dst\n"
12552 "done:" %}
12553 ins_encode %{
12554 Label p_one, m_one, done;
12555 __ xorptr($dst$$Register, $dst$$Register);
12556 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12557 __ jccb(Assembler::less, m_one);
12558 __ jccb(Assembler::greater, p_one);
12559 __ cmpl($src1$$Register, $src2$$Register);
12560 __ jccb(Assembler::below, m_one);
12561 __ jccb(Assembler::equal, done);
12562 __ bind(p_one);
12563 __ incrementl($dst$$Register);
12564 __ jmpb(done);
12565 __ bind(m_one);
12566 __ decrementl($dst$$Register);
12567 __ bind(done);
12568 %}
12569 ins_pipe( pipe_slow );
12570 %}
12572 //======
12573 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12574 // compares. Can be used for LE or GT compares by reversing arguments.
12575 // NOT GOOD FOR EQ/NE tests.
12576 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12577 match( Set flags (CmpL src zero ));
12578 ins_cost(100);
12579 format %{ "TEST $src.hi,$src.hi" %}
12580 opcode(0x85);
12581 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12582 ins_pipe( ialu_cr_reg_reg );
12583 %}
12585 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12586 // compares. Can be used for LE or GT compares by reversing arguments.
12587 // NOT GOOD FOR EQ/NE tests.
12588 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12589 match( Set flags (CmpL src1 src2 ));
12590 effect( TEMP tmp );
12591 ins_cost(300);
12592 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12593 "MOV $tmp,$src1.hi\n\t"
12594 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12595 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12596 ins_pipe( ialu_cr_reg_reg );
12597 %}
12599 // Long compares reg < zero/req OR reg >= zero/req.
12600 // Just a wrapper for a normal branch, plus the predicate test.
12601 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12602 match(If cmp flags);
12603 effect(USE labl);
12604 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12605 expand %{
12606 jmpCon(cmp,flags,labl); // JLT or JGE...
12607 %}
12608 %}
12610 // Compare 2 longs and CMOVE longs.
12611 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12612 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12613 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12614 ins_cost(400);
12615 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12616 "CMOV$cmp $dst.hi,$src.hi" %}
12617 opcode(0x0F,0x40);
12618 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12619 ins_pipe( pipe_cmov_reg_long );
12620 %}
12622 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12623 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12624 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12625 ins_cost(500);
12626 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12627 "CMOV$cmp $dst.hi,$src.hi" %}
12628 opcode(0x0F,0x40);
12629 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12630 ins_pipe( pipe_cmov_reg_long );
12631 %}
12633 // Compare 2 longs and CMOVE ints.
12634 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12635 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12636 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12637 ins_cost(200);
12638 format %{ "CMOV$cmp $dst,$src" %}
12639 opcode(0x0F,0x40);
12640 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12641 ins_pipe( pipe_cmov_reg );
12642 %}
12644 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12645 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12646 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12647 ins_cost(250);
12648 format %{ "CMOV$cmp $dst,$src" %}
12649 opcode(0x0F,0x40);
12650 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12651 ins_pipe( pipe_cmov_mem );
12652 %}
12654 // Compare 2 longs and CMOVE ints.
12655 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12656 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12657 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12658 ins_cost(200);
12659 format %{ "CMOV$cmp $dst,$src" %}
12660 opcode(0x0F,0x40);
12661 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12662 ins_pipe( pipe_cmov_reg );
12663 %}
12665 // Compare 2 longs and CMOVE doubles
12666 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12667 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12668 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12669 ins_cost(200);
12670 expand %{
12671 fcmovDPR_regS(cmp,flags,dst,src);
12672 %}
12673 %}
12675 // Compare 2 longs and CMOVE doubles
12676 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12677 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12678 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12679 ins_cost(200);
12680 expand %{
12681 fcmovD_regS(cmp,flags,dst,src);
12682 %}
12683 %}
12685 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12686 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12687 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12688 ins_cost(200);
12689 expand %{
12690 fcmovFPR_regS(cmp,flags,dst,src);
12691 %}
12692 %}
12694 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12695 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12696 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12697 ins_cost(200);
12698 expand %{
12699 fcmovF_regS(cmp,flags,dst,src);
12700 %}
12701 %}
12703 //======
12704 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12705 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12706 match( Set flags (CmpL src zero ));
12707 effect(TEMP tmp);
12708 ins_cost(200);
12709 format %{ "MOV $tmp,$src.lo\n\t"
12710 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12711 ins_encode( long_cmp_flags0( src, tmp ) );
12712 ins_pipe( ialu_reg_reg_long );
12713 %}
12715 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12716 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12717 match( Set flags (CmpL src1 src2 ));
12718 ins_cost(200+300);
12719 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12720 "JNE,s skip\n\t"
12721 "CMP $src1.hi,$src2.hi\n\t"
12722 "skip:\t" %}
12723 ins_encode( long_cmp_flags1( src1, src2 ) );
12724 ins_pipe( ialu_cr_reg_reg );
12725 %}
12727 // Long compare reg == zero/reg OR reg != zero/reg
12728 // Just a wrapper for a normal branch, plus the predicate test.
12729 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12730 match(If cmp flags);
12731 effect(USE labl);
12732 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12733 expand %{
12734 jmpCon(cmp,flags,labl); // JEQ or JNE...
12735 %}
12736 %}
12738 // Compare 2 longs and CMOVE longs.
12739 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12740 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12741 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12742 ins_cost(400);
12743 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12744 "CMOV$cmp $dst.hi,$src.hi" %}
12745 opcode(0x0F,0x40);
12746 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12747 ins_pipe( pipe_cmov_reg_long );
12748 %}
12750 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12751 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12752 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12753 ins_cost(500);
12754 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12755 "CMOV$cmp $dst.hi,$src.hi" %}
12756 opcode(0x0F,0x40);
12757 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12758 ins_pipe( pipe_cmov_reg_long );
12759 %}
12761 // Compare 2 longs and CMOVE ints.
12762 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12763 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12764 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12765 ins_cost(200);
12766 format %{ "CMOV$cmp $dst,$src" %}
12767 opcode(0x0F,0x40);
12768 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12769 ins_pipe( pipe_cmov_reg );
12770 %}
12772 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12773 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12774 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12775 ins_cost(250);
12776 format %{ "CMOV$cmp $dst,$src" %}
12777 opcode(0x0F,0x40);
12778 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12779 ins_pipe( pipe_cmov_mem );
12780 %}
12782 // Compare 2 longs and CMOVE ints.
12783 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12784 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12785 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12786 ins_cost(200);
12787 format %{ "CMOV$cmp $dst,$src" %}
12788 opcode(0x0F,0x40);
12789 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12790 ins_pipe( pipe_cmov_reg );
12791 %}
12793 // Compare 2 longs and CMOVE doubles
12794 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12795 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12796 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12797 ins_cost(200);
12798 expand %{
12799 fcmovDPR_regS(cmp,flags,dst,src);
12800 %}
12801 %}
12803 // Compare 2 longs and CMOVE doubles
12804 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12805 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12806 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12807 ins_cost(200);
12808 expand %{
12809 fcmovD_regS(cmp,flags,dst,src);
12810 %}
12811 %}
12813 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12814 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12815 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12816 ins_cost(200);
12817 expand %{
12818 fcmovFPR_regS(cmp,flags,dst,src);
12819 %}
12820 %}
12822 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12823 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12824 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12825 ins_cost(200);
12826 expand %{
12827 fcmovF_regS(cmp,flags,dst,src);
12828 %}
12829 %}
12831 //======
12832 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12833 // Same as cmpL_reg_flags_LEGT except must negate src
12834 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12835 match( Set flags (CmpL src zero ));
12836 effect( TEMP tmp );
12837 ins_cost(300);
12838 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12839 "CMP $tmp,$src.lo\n\t"
12840 "SBB $tmp,$src.hi\n\t" %}
12841 ins_encode( long_cmp_flags3(src, tmp) );
12842 ins_pipe( ialu_reg_reg_long );
12843 %}
12845 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12846 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12847 // requires a commuted test to get the same result.
12848 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12849 match( Set flags (CmpL src1 src2 ));
12850 effect( TEMP tmp );
12851 ins_cost(300);
12852 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12853 "MOV $tmp,$src2.hi\n\t"
12854 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12855 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12856 ins_pipe( ialu_cr_reg_reg );
12857 %}
12859 // Long compares reg < zero/req OR reg >= zero/req.
12860 // Just a wrapper for a normal branch, plus the predicate test
12861 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12862 match(If cmp flags);
12863 effect(USE labl);
12864 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12865 ins_cost(300);
12866 expand %{
12867 jmpCon(cmp,flags,labl); // JGT or JLE...
12868 %}
12869 %}
12871 // Compare 2 longs and CMOVE longs.
12872 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12873 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12874 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12875 ins_cost(400);
12876 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12877 "CMOV$cmp $dst.hi,$src.hi" %}
12878 opcode(0x0F,0x40);
12879 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12880 ins_pipe( pipe_cmov_reg_long );
12881 %}
12883 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12884 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12885 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12886 ins_cost(500);
12887 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12888 "CMOV$cmp $dst.hi,$src.hi+4" %}
12889 opcode(0x0F,0x40);
12890 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12891 ins_pipe( pipe_cmov_reg_long );
12892 %}
12894 // Compare 2 longs and CMOVE ints.
12895 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12896 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12897 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12898 ins_cost(200);
12899 format %{ "CMOV$cmp $dst,$src" %}
12900 opcode(0x0F,0x40);
12901 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12902 ins_pipe( pipe_cmov_reg );
12903 %}
12905 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12906 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12907 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12908 ins_cost(250);
12909 format %{ "CMOV$cmp $dst,$src" %}
12910 opcode(0x0F,0x40);
12911 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12912 ins_pipe( pipe_cmov_mem );
12913 %}
12915 // Compare 2 longs and CMOVE ptrs.
12916 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12917 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12918 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12919 ins_cost(200);
12920 format %{ "CMOV$cmp $dst,$src" %}
12921 opcode(0x0F,0x40);
12922 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12923 ins_pipe( pipe_cmov_reg );
12924 %}
12926 // Compare 2 longs and CMOVE doubles
12927 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12928 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12929 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12930 ins_cost(200);
12931 expand %{
12932 fcmovDPR_regS(cmp,flags,dst,src);
12933 %}
12934 %}
12936 // Compare 2 longs and CMOVE doubles
12937 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12938 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12939 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12940 ins_cost(200);
12941 expand %{
12942 fcmovD_regS(cmp,flags,dst,src);
12943 %}
12944 %}
12946 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12947 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12948 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12949 ins_cost(200);
12950 expand %{
12951 fcmovFPR_regS(cmp,flags,dst,src);
12952 %}
12953 %}
12956 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12957 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12958 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12959 ins_cost(200);
12960 expand %{
12961 fcmovF_regS(cmp,flags,dst,src);
12962 %}
12963 %}
12966 // ============================================================================
12967 // Procedure Call/Return Instructions
12968 // Call Java Static Instruction
12969 // Note: If this code changes, the corresponding ret_addr_offset() and
12970 // compute_padding() functions will have to be adjusted.
12971 instruct CallStaticJavaDirect(method meth) %{
12972 match(CallStaticJava);
12973 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12974 effect(USE meth);
12976 ins_cost(300);
12977 format %{ "CALL,static " %}
12978 opcode(0xE8); /* E8 cd */
12979 ins_encode( pre_call_resets,
12980 Java_Static_Call( meth ),
12981 call_epilog,
12982 post_call_FPU );
12983 ins_pipe( pipe_slow );
12984 ins_alignment(4);
12985 %}
12987 // Call Java Static Instruction (method handle version)
12988 // Note: If this code changes, the corresponding ret_addr_offset() and
12989 // compute_padding() functions will have to be adjusted.
12990 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
12991 match(CallStaticJava);
12992 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
12993 effect(USE meth);
12994 // EBP is saved by all callees (for interpreter stack correction).
12995 // We use it here for a similar purpose, in {preserve,restore}_SP.
12997 ins_cost(300);
12998 format %{ "CALL,static/MethodHandle " %}
12999 opcode(0xE8); /* E8 cd */
13000 ins_encode( pre_call_resets,
13001 preserve_SP,
13002 Java_Static_Call( meth ),
13003 restore_SP,
13004 call_epilog,
13005 post_call_FPU );
13006 ins_pipe( pipe_slow );
13007 ins_alignment(4);
13008 %}
13010 // Call Java Dynamic Instruction
13011 // Note: If this code changes, the corresponding ret_addr_offset() and
13012 // compute_padding() functions will have to be adjusted.
13013 instruct CallDynamicJavaDirect(method meth) %{
13014 match(CallDynamicJava);
13015 effect(USE meth);
13017 ins_cost(300);
13018 format %{ "MOV EAX,(oop)-1\n\t"
13019 "CALL,dynamic" %}
13020 opcode(0xE8); /* E8 cd */
13021 ins_encode( pre_call_resets,
13022 Java_Dynamic_Call( meth ),
13023 call_epilog,
13024 post_call_FPU );
13025 ins_pipe( pipe_slow );
13026 ins_alignment(4);
13027 %}
13029 // Call Runtime Instruction
13030 instruct CallRuntimeDirect(method meth) %{
13031 match(CallRuntime );
13032 effect(USE meth);
13034 ins_cost(300);
13035 format %{ "CALL,runtime " %}
13036 opcode(0xE8); /* E8 cd */
13037 // Use FFREEs to clear entries in float stack
13038 ins_encode( pre_call_resets,
13039 FFree_Float_Stack_All,
13040 Java_To_Runtime( meth ),
13041 post_call_FPU );
13042 ins_pipe( pipe_slow );
13043 %}
13045 // Call runtime without safepoint
13046 instruct CallLeafDirect(method meth) %{
13047 match(CallLeaf);
13048 effect(USE meth);
13050 ins_cost(300);
13051 format %{ "CALL_LEAF,runtime " %}
13052 opcode(0xE8); /* E8 cd */
13053 ins_encode( pre_call_resets,
13054 FFree_Float_Stack_All,
13055 Java_To_Runtime( meth ),
13056 Verify_FPU_For_Leaf, post_call_FPU );
13057 ins_pipe( pipe_slow );
13058 %}
13060 instruct CallLeafNoFPDirect(method meth) %{
13061 match(CallLeafNoFP);
13062 effect(USE meth);
13064 ins_cost(300);
13065 format %{ "CALL_LEAF_NOFP,runtime " %}
13066 opcode(0xE8); /* E8 cd */
13067 ins_encode(Java_To_Runtime(meth));
13068 ins_pipe( pipe_slow );
13069 %}
13072 // Return Instruction
13073 // Remove the return address & jump to it.
13074 instruct Ret() %{
13075 match(Return);
13076 format %{ "RET" %}
13077 opcode(0xC3);
13078 ins_encode(OpcP);
13079 ins_pipe( pipe_jmp );
13080 %}
13082 // Tail Call; Jump from runtime stub to Java code.
13083 // Also known as an 'interprocedural jump'.
13084 // Target of jump will eventually return to caller.
13085 // TailJump below removes the return address.
13086 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13087 match(TailCall jump_target method_oop );
13088 ins_cost(300);
13089 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13090 opcode(0xFF, 0x4); /* Opcode FF /4 */
13091 ins_encode( OpcP, RegOpc(jump_target) );
13092 ins_pipe( pipe_jmp );
13093 %}
13096 // Tail Jump; remove the return address; jump to target.
13097 // TailCall above leaves the return address around.
13098 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13099 match( TailJump jump_target ex_oop );
13100 ins_cost(300);
13101 format %{ "POP EDX\t# pop return address into dummy\n\t"
13102 "JMP $jump_target " %}
13103 opcode(0xFF, 0x4); /* Opcode FF /4 */
13104 ins_encode( enc_pop_rdx,
13105 OpcP, RegOpc(jump_target) );
13106 ins_pipe( pipe_jmp );
13107 %}
13109 // Create exception oop: created by stack-crawling runtime code.
13110 // Created exception is now available to this handler, and is setup
13111 // just prior to jumping to this handler. No code emitted.
13112 instruct CreateException( eAXRegP ex_oop )
13113 %{
13114 match(Set ex_oop (CreateEx));
13116 size(0);
13117 // use the following format syntax
13118 format %{ "# exception oop is in EAX; no code emitted" %}
13119 ins_encode();
13120 ins_pipe( empty );
13121 %}
13124 // Rethrow exception:
13125 // The exception oop will come in the first argument position.
13126 // Then JUMP (not call) to the rethrow stub code.
13127 instruct RethrowException()
13128 %{
13129 match(Rethrow);
13131 // use the following format syntax
13132 format %{ "JMP rethrow_stub" %}
13133 ins_encode(enc_rethrow);
13134 ins_pipe( pipe_jmp );
13135 %}
13137 // inlined locking and unlocking
13140 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
13141 match( Set cr (FastLock object box) );
13142 effect( TEMP tmp, TEMP scr, USE_KILL box );
13143 ins_cost(300);
13144 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
13145 ins_encode( Fast_Lock(object,box,tmp,scr) );
13146 ins_pipe( pipe_slow );
13147 %}
13149 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13150 match( Set cr (FastUnlock object box) );
13151 effect( TEMP tmp, USE_KILL box );
13152 ins_cost(300);
13153 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
13154 ins_encode( Fast_Unlock(object,box,tmp) );
13155 ins_pipe( pipe_slow );
13156 %}
13160 // ============================================================================
13161 // Safepoint Instruction
13162 instruct safePoint_poll(eFlagsReg cr) %{
13163 match(SafePoint);
13164 effect(KILL cr);
13166 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13167 // On SPARC that might be acceptable as we can generate the address with
13168 // just a sethi, saving an or. By polling at offset 0 we can end up
13169 // putting additional pressure on the index-0 in the D$. Because of
13170 // alignment (just like the situation at hand) the lower indices tend
13171 // to see more traffic. It'd be better to change the polling address
13172 // to offset 0 of the last $line in the polling page.
13174 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13175 ins_cost(125);
13176 size(6) ;
13177 ins_encode( Safepoint_Poll() );
13178 ins_pipe( ialu_reg_mem );
13179 %}
13182 // ============================================================================
13183 // This name is KNOWN by the ADLC and cannot be changed.
13184 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13185 // for this guy.
13186 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
13187 match(Set dst (ThreadLocal));
13188 effect(DEF dst, KILL cr);
13190 format %{ "MOV $dst, Thread::current()" %}
13191 ins_encode %{
13192 Register dstReg = as_Register($dst$$reg);
13193 __ get_thread(dstReg);
13194 %}
13195 ins_pipe( ialu_reg_fat );
13196 %}
13200 //----------PEEPHOLE RULES-----------------------------------------------------
13201 // These must follow all instruction definitions as they use the names
13202 // defined in the instructions definitions.
13203 //
13204 // peepmatch ( root_instr_name [preceding_instruction]* );
13205 //
13206 // peepconstraint %{
13207 // (instruction_number.operand_name relational_op instruction_number.operand_name
13208 // [, ...] );
13209 // // instruction numbers are zero-based using left to right order in peepmatch
13210 //
13211 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13212 // // provide an instruction_number.operand_name for each operand that appears
13213 // // in the replacement instruction's match rule
13214 //
13215 // ---------VM FLAGS---------------------------------------------------------
13216 //
13217 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13218 //
13219 // Each peephole rule is given an identifying number starting with zero and
13220 // increasing by one in the order seen by the parser. An individual peephole
13221 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13222 // on the command-line.
13223 //
13224 // ---------CURRENT LIMITATIONS----------------------------------------------
13225 //
13226 // Only match adjacent instructions in same basic block
13227 // Only equality constraints
13228 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13229 // Only one replacement instruction
13230 //
13231 // ---------EXAMPLE----------------------------------------------------------
13232 //
13233 // // pertinent parts of existing instructions in architecture description
13234 // instruct movI(rRegI dst, rRegI src) %{
13235 // match(Set dst (CopyI src));
13236 // %}
13237 //
13238 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13239 // match(Set dst (AddI dst src));
13240 // effect(KILL cr);
13241 // %}
13242 //
13243 // // Change (inc mov) to lea
13244 // peephole %{
13245 // // increment preceeded by register-register move
13246 // peepmatch ( incI_eReg movI );
13247 // // require that the destination register of the increment
13248 // // match the destination register of the move
13249 // peepconstraint ( 0.dst == 1.dst );
13250 // // construct a replacement instruction that sets
13251 // // the destination to ( move's source register + one )
13252 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13253 // %}
13254 //
13255 // Implementation no longer uses movX instructions since
13256 // machine-independent system no longer uses CopyX nodes.
13257 //
13258 // peephole %{
13259 // peepmatch ( incI_eReg movI );
13260 // peepconstraint ( 0.dst == 1.dst );
13261 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13262 // %}
13263 //
13264 // peephole %{
13265 // peepmatch ( decI_eReg movI );
13266 // peepconstraint ( 0.dst == 1.dst );
13267 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13268 // %}
13269 //
13270 // peephole %{
13271 // peepmatch ( addI_eReg_imm movI );
13272 // peepconstraint ( 0.dst == 1.dst );
13273 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13274 // %}
13275 //
13276 // peephole %{
13277 // peepmatch ( addP_eReg_imm movP );
13278 // peepconstraint ( 0.dst == 1.dst );
13279 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13280 // %}
13282 // // Change load of spilled value to only a spill
13283 // instruct storeI(memory mem, rRegI src) %{
13284 // match(Set mem (StoreI mem src));
13285 // %}
13286 //
13287 // instruct loadI(rRegI dst, memory mem) %{
13288 // match(Set dst (LoadI mem));
13289 // %}
13290 //
13291 peephole %{
13292 peepmatch ( loadI storeI );
13293 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13294 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13295 %}
13297 //----------SMARTSPILL RULES---------------------------------------------------
13298 // These must follow all instruction definitions as they use the names
13299 // defined in the instructions definitions.