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src/cpu/x86/vm/c1_LIRAssembler_x86.cpp@252d541466ea
src/cpu/x86/vm/c1_LIRAssembler_x86.cpp
Fri, 18 Oct 2013 12:15:32 -0700
- author
- morris
- date
- Fri, 18 Oct 2013 12:15:32 -0700
- changeset 5980
- 252d541466ea
- parent 5914
- d13d7aba8c12
- child 5994
- 9acbfe04b5c3
- permissions
- -rw-r--r--
8008242: VerifyOops is broken on SPARC
Summary: Fixed displacement issues in SPARC macroassembler and ensure that getClass intrinsic temporary result is T_METADATA
Reviewed-by: kvn, twisti
1 /*
2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc_interface/collectedHeap.hpp"
36 #include "memory/barrierSet.hpp"
37 #include "memory/cardTableModRefBS.hpp"
38 #include "nativeInst_x86.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/sharedRuntime.hpp"
43 // These masks are used to provide 128-bit aligned bitmasks to the XMM
44 // instructions, to allow sign-masking or sign-bit flipping. They allow
45 // fast versions of NegF/NegD and AbsF/AbsD.
47 // Note: 'double' and 'long long' have 32-bits alignment on x86.
48 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
49 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
50 // of 128-bits operands for SSE instructions.
51 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
52 // Store the value to a 128-bits operand.
53 operand[0] = lo;
54 operand[1] = hi;
55 return operand;
56 }
58 // Buffer for 128-bits masks used by SSE instructions.
59 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
61 // Static initialization during VM startup.
62 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
63 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
64 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
65 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
69 NEEDS_CLEANUP // remove this definitions ?
70 const Register IC_Klass = rax; // where the IC klass is cached
71 const Register SYNC_header = rax; // synchronization header
72 const Register SHIFT_count = rcx; // where count for shift operations must be
74 #define __ _masm->
77 static void select_different_registers(Register preserve,
78 Register extra,
79 Register &tmp1,
80 Register &tmp2) {
81 if (tmp1 == preserve) {
82 assert_different_registers(tmp1, tmp2, extra);
83 tmp1 = extra;
84 } else if (tmp2 == preserve) {
85 assert_different_registers(tmp1, tmp2, extra);
86 tmp2 = extra;
87 }
88 assert_different_registers(preserve, tmp1, tmp2);
89 }
93 static void select_different_registers(Register preserve,
94 Register extra,
95 Register &tmp1,
96 Register &tmp2,
97 Register &tmp3) {
98 if (tmp1 == preserve) {
99 assert_different_registers(tmp1, tmp2, tmp3, extra);
100 tmp1 = extra;
101 } else if (tmp2 == preserve) {
102 assert_different_registers(tmp1, tmp2, tmp3, extra);
103 tmp2 = extra;
104 } else if (tmp3 == preserve) {
105 assert_different_registers(tmp1, tmp2, tmp3, extra);
106 tmp3 = extra;
107 }
108 assert_different_registers(preserve, tmp1, tmp2, tmp3);
109 }
113 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
114 if (opr->is_constant()) {
115 LIR_Const* constant = opr->as_constant_ptr();
116 switch (constant->type()) {
117 case T_INT: {
118 return true;
119 }
121 default:
122 return false;
123 }
124 }
125 return false;
126 }
129 LIR_Opr LIR_Assembler::receiverOpr() {
130 return FrameMap::receiver_opr;
131 }
133 LIR_Opr LIR_Assembler::osrBufferPointer() {
134 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
135 }
137 //--------------fpu register translations-----------------------
140 address LIR_Assembler::float_constant(float f) {
141 address const_addr = __ float_constant(f);
142 if (const_addr == NULL) {
143 bailout("const section overflow");
144 return __ code()->consts()->start();
145 } else {
146 return const_addr;
147 }
148 }
151 address LIR_Assembler::double_constant(double d) {
152 address const_addr = __ double_constant(d);
153 if (const_addr == NULL) {
154 bailout("const section overflow");
155 return __ code()->consts()->start();
156 } else {
157 return const_addr;
158 }
159 }
162 void LIR_Assembler::set_24bit_FPU() {
163 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
164 }
166 void LIR_Assembler::reset_FPU() {
167 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
168 }
170 void LIR_Assembler::fpop() {
171 __ fpop();
172 }
174 void LIR_Assembler::fxch(int i) {
175 __ fxch(i);
176 }
178 void LIR_Assembler::fld(int i) {
179 __ fld_s(i);
180 }
182 void LIR_Assembler::ffree(int i) {
183 __ ffree(i);
184 }
186 void LIR_Assembler::breakpoint() {
187 __ int3();
188 }
190 void LIR_Assembler::push(LIR_Opr opr) {
191 if (opr->is_single_cpu()) {
192 __ push_reg(opr->as_register());
193 } else if (opr->is_double_cpu()) {
194 NOT_LP64(__ push_reg(opr->as_register_hi()));
195 __ push_reg(opr->as_register_lo());
196 } else if (opr->is_stack()) {
197 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
198 } else if (opr->is_constant()) {
199 LIR_Const* const_opr = opr->as_constant_ptr();
200 if (const_opr->type() == T_OBJECT) {
201 __ push_oop(const_opr->as_jobject());
202 } else if (const_opr->type() == T_INT) {
203 __ push_jint(const_opr->as_jint());
204 } else {
205 ShouldNotReachHere();
206 }
208 } else {
209 ShouldNotReachHere();
210 }
211 }
213 void LIR_Assembler::pop(LIR_Opr opr) {
214 if (opr->is_single_cpu()) {
215 __ pop_reg(opr->as_register());
216 } else {
217 ShouldNotReachHere();
218 }
219 }
221 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
222 return addr->base()->is_illegal() && addr->index()->is_illegal();
223 }
225 //-------------------------------------------
227 Address LIR_Assembler::as_Address(LIR_Address* addr) {
228 return as_Address(addr, rscratch1);
229 }
231 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
232 if (addr->base()->is_illegal()) {
233 assert(addr->index()->is_illegal(), "must be illegal too");
234 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
235 if (! __ reachable(laddr)) {
236 __ movptr(tmp, laddr.addr());
237 Address res(tmp, 0);
238 return res;
239 } else {
240 return __ as_Address(laddr);
241 }
242 }
244 Register base = addr->base()->as_pointer_register();
246 if (addr->index()->is_illegal()) {
247 return Address( base, addr->disp());
248 } else if (addr->index()->is_cpu_register()) {
249 Register index = addr->index()->as_pointer_register();
250 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
251 } else if (addr->index()->is_constant()) {
252 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
253 assert(Assembler::is_simm32(addr_offset), "must be");
255 return Address(base, addr_offset);
256 } else {
257 Unimplemented();
258 return Address();
259 }
260 }
263 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
264 Address base = as_Address(addr);
265 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
266 }
269 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
270 return as_Address(addr);
271 }
274 void LIR_Assembler::osr_entry() {
275 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
276 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
277 ValueStack* entry_state = osr_entry->state();
278 int number_of_locks = entry_state->locks_size();
280 // we jump here if osr happens with the interpreter
281 // state set up to continue at the beginning of the
282 // loop that triggered osr - in particular, we have
283 // the following registers setup:
284 //
285 // rcx: osr buffer
286 //
288 // build frame
289 ciMethod* m = compilation()->method();
290 __ build_frame(initial_frame_size_in_bytes());
292 // OSR buffer is
293 //
294 // locals[nlocals-1..0]
295 // monitors[0..number_of_locks]
296 //
297 // locals is a direct copy of the interpreter frame so in the osr buffer
298 // so first slot in the local array is the last local from the interpreter
299 // and last slot is local[0] (receiver) from the interpreter
300 //
301 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
302 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
303 // in the interpreter frame (the method lock if a sync method)
305 // Initialize monitors in the compiled activation.
306 // rcx: pointer to osr buffer
307 //
308 // All other registers are dead at this point and the locals will be
309 // copied into place by code emitted in the IR.
311 Register OSR_buf = osrBufferPointer()->as_pointer_register();
312 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
313 int monitor_offset = BytesPerWord * method()->max_locals() +
314 (2 * BytesPerWord) * (number_of_locks - 1);
315 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
316 // the OSR buffer using 2 word entries: first the lock and then
317 // the oop.
318 for (int i = 0; i < number_of_locks; i++) {
319 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
320 #ifdef ASSERT
321 // verify the interpreter's monitor has a non-null object
322 {
323 Label L;
324 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
325 __ jcc(Assembler::notZero, L);
326 __ stop("locked object is NULL");
327 __ bind(L);
328 }
329 #endif
330 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
331 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
332 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
333 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
334 }
335 }
336 }
339 // inline cache check; done before the frame is built.
340 int LIR_Assembler::check_icache() {
341 Register receiver = FrameMap::receiver_opr->as_register();
342 Register ic_klass = IC_Klass;
343 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
344 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
345 if (!do_post_padding) {
346 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
347 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
348 __ nop();
349 }
350 }
351 int offset = __ offset();
352 __ inline_cache_check(receiver, IC_Klass);
353 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
354 if (do_post_padding) {
355 // force alignment after the cache check.
356 // It's been verified to be aligned if !VerifyOops
357 __ align(CodeEntryAlignment);
358 }
359 return offset;
360 }
363 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
364 jobject o = NULL;
365 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
366 __ movoop(reg, o);
367 patching_epilog(patch, lir_patch_normal, reg, info);
368 }
370 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
371 Metadata* o = NULL;
372 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
373 __ mov_metadata(reg, o);
374 patching_epilog(patch, lir_patch_normal, reg, info);
375 }
377 // This specifies the rsp decrement needed to build the frame
378 int LIR_Assembler::initial_frame_size_in_bytes() {
379 // if rounding, must let FrameMap know!
381 // The frame_map records size in slots (32bit word)
383 // subtract two words to account for return address and link
384 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
385 }
388 int LIR_Assembler::emit_exception_handler() {
389 // if the last instruction is a call (typically to do a throw which
390 // is coming at the end after block reordering) the return address
391 // must still point into the code area in order to avoid assertion
392 // failures when searching for the corresponding bci => add a nop
393 // (was bug 5/14/1999 - gri)
394 __ nop();
396 // generate code for exception handler
397 address handler_base = __ start_a_stub(exception_handler_size);
398 if (handler_base == NULL) {
399 // not enough space left for the handler
400 bailout("exception handler overflow");
401 return -1;
402 }
404 int offset = code_offset();
406 // the exception oop and pc are in rax, and rdx
407 // no other registers need to be preserved, so invalidate them
408 __ invalidate_registers(false, true, true, false, true, true);
410 // check that there is really an exception
411 __ verify_not_null_oop(rax);
413 // search an exception handler (rax: exception oop, rdx: throwing pc)
414 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
415 __ should_not_reach_here();
416 guarantee(code_offset() - offset <= exception_handler_size, "overflow");
417 __ end_a_stub();
419 return offset;
420 }
423 // Emit the code to remove the frame from the stack in the exception
424 // unwind path.
425 int LIR_Assembler::emit_unwind_handler() {
426 #ifndef PRODUCT
427 if (CommentedAssembly) {
428 _masm->block_comment("Unwind handler");
429 }
430 #endif
432 int offset = code_offset();
434 // Fetch the exception from TLS and clear out exception related thread state
435 __ get_thread(rsi);
436 __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset()));
437 __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
438 __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
440 __ bind(_unwind_handler_entry);
441 __ verify_not_null_oop(rax);
442 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
443 __ mov(rsi, rax); // Preserve the exception
444 }
446 // Preform needed unlocking
447 MonitorExitStub* stub = NULL;
448 if (method()->is_synchronized()) {
449 monitor_address(0, FrameMap::rax_opr);
450 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
451 __ unlock_object(rdi, rbx, rax, *stub->entry());
452 __ bind(*stub->continuation());
453 }
455 if (compilation()->env()->dtrace_method_probes()) {
456 __ get_thread(rax);
457 __ movptr(Address(rsp, 0), rax);
458 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
459 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
460 }
462 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
463 __ mov(rax, rsi); // Restore the exception
464 }
466 // remove the activation and dispatch to the unwind handler
467 __ remove_frame(initial_frame_size_in_bytes());
468 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
470 // Emit the slow path assembly
471 if (stub != NULL) {
472 stub->emit_code(this);
473 }
475 return offset;
476 }
479 int LIR_Assembler::emit_deopt_handler() {
480 // if the last instruction is a call (typically to do a throw which
481 // is coming at the end after block reordering) the return address
482 // must still point into the code area in order to avoid assertion
483 // failures when searching for the corresponding bci => add a nop
484 // (was bug 5/14/1999 - gri)
485 __ nop();
487 // generate code for exception handler
488 address handler_base = __ start_a_stub(deopt_handler_size);
489 if (handler_base == NULL) {
490 // not enough space left for the handler
491 bailout("deopt handler overflow");
492 return -1;
493 }
495 int offset = code_offset();
496 InternalAddress here(__ pc());
498 __ pushptr(here.addr());
499 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
500 guarantee(code_offset() - offset <= deopt_handler_size, "overflow");
501 __ end_a_stub();
503 return offset;
504 }
507 // This is the fast version of java.lang.String.compare; it has not
508 // OSR-entry and therefore, we generate a slow version for OSR's
509 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
510 __ movptr (rbx, rcx); // receiver is in rcx
511 __ movptr (rax, arg1->as_register());
513 // Get addresses of first characters from both Strings
514 __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
515 if (java_lang_String::has_offset_field()) {
516 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
517 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
518 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
519 } else {
520 __ movl (rax, Address(rsi, arrayOopDesc::length_offset_in_bytes()));
521 __ lea (rsi, Address(rsi, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
522 }
524 // rbx, may be NULL
525 add_debug_info_for_null_check_here(info);
526 __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
527 if (java_lang_String::has_offset_field()) {
528 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
529 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
530 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
531 } else {
532 __ movl (rbx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
533 __ lea (rdi, Address(rdi, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
534 }
536 // compute minimum length (in rax) and difference of lengths (on top of stack)
537 __ mov (rcx, rbx);
538 __ subptr(rbx, rax); // subtract lengths
539 __ push (rbx); // result
540 __ cmov (Assembler::lessEqual, rax, rcx);
542 // is minimum length 0?
543 Label noLoop, haveResult;
544 __ testptr (rax, rax);
545 __ jcc (Assembler::zero, noLoop);
547 // compare first characters
548 __ load_unsigned_short(rcx, Address(rdi, 0));
549 __ load_unsigned_short(rbx, Address(rsi, 0));
550 __ subl(rcx, rbx);
551 __ jcc(Assembler::notZero, haveResult);
552 // starting loop
553 __ decrement(rax); // we already tested index: skip one
554 __ jcc(Assembler::zero, noLoop);
556 // set rsi.edi to the end of the arrays (arrays have same length)
557 // negate the index
559 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
560 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
561 __ negptr(rax);
563 // compare the strings in a loop
565 Label loop;
566 __ align(wordSize);
567 __ bind(loop);
568 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0));
569 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0));
570 __ subl(rcx, rbx);
571 __ jcc(Assembler::notZero, haveResult);
572 __ increment(rax);
573 __ jcc(Assembler::notZero, loop);
575 // strings are equal up to min length
577 __ bind(noLoop);
578 __ pop(rax);
579 return_op(LIR_OprFact::illegalOpr);
581 __ bind(haveResult);
582 // leave instruction is going to discard the TOS value
583 __ mov (rax, rcx); // result of call is in rax,
584 }
587 void LIR_Assembler::return_op(LIR_Opr result) {
588 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
589 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
590 assert(result->fpu() == 0, "result must already be on TOS");
591 }
593 // Pop the stack before the safepoint code
594 __ remove_frame(initial_frame_size_in_bytes());
596 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
598 // Note: we do not need to round double result; float result has the right precision
599 // the poll sets the condition code, but no data registers
600 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
601 relocInfo::poll_return_type);
603 if (Assembler::is_polling_page_far()) {
604 __ lea(rscratch1, polling_page);
605 __ relocate(relocInfo::poll_return_type);
606 __ testl(rax, Address(rscratch1, 0));
607 } else {
608 __ testl(rax, polling_page);
609 }
610 __ ret(0);
611 }
614 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
615 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
616 relocInfo::poll_type);
617 guarantee(info != NULL, "Shouldn't be NULL");
618 int offset = __ offset();
619 if (Assembler::is_polling_page_far()) {
620 __ lea(rscratch1, polling_page);
621 offset = __ offset();
622 add_debug_info_for_branch(info);
623 __ testl(rax, Address(rscratch1, 0));
624 } else {
625 add_debug_info_for_branch(info);
626 __ testl(rax, polling_page);
627 }
628 return offset;
629 }
632 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
633 if (from_reg != to_reg) __ mov(to_reg, from_reg);
634 }
636 void LIR_Assembler::swap_reg(Register a, Register b) {
637 __ xchgptr(a, b);
638 }
641 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
642 assert(src->is_constant(), "should not call otherwise");
643 assert(dest->is_register(), "should not call otherwise");
644 LIR_Const* c = src->as_constant_ptr();
646 switch (c->type()) {
647 case T_INT: {
648 assert(patch_code == lir_patch_none, "no patching handled here");
649 __ movl(dest->as_register(), c->as_jint());
650 break;
651 }
653 case T_ADDRESS: {
654 assert(patch_code == lir_patch_none, "no patching handled here");
655 __ movptr(dest->as_register(), c->as_jint());
656 break;
657 }
659 case T_LONG: {
660 assert(patch_code == lir_patch_none, "no patching handled here");
661 #ifdef _LP64
662 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
663 #else
664 __ movptr(dest->as_register_lo(), c->as_jint_lo());
665 __ movptr(dest->as_register_hi(), c->as_jint_hi());
666 #endif // _LP64
667 break;
668 }
670 case T_OBJECT: {
671 if (patch_code != lir_patch_none) {
672 jobject2reg_with_patching(dest->as_register(), info);
673 } else {
674 __ movoop(dest->as_register(), c->as_jobject());
675 }
676 break;
677 }
679 case T_METADATA: {
680 if (patch_code != lir_patch_none) {
681 klass2reg_with_patching(dest->as_register(), info);
682 } else {
683 __ mov_metadata(dest->as_register(), c->as_metadata());
684 }
685 break;
686 }
688 case T_FLOAT: {
689 if (dest->is_single_xmm()) {
690 if (c->is_zero_float()) {
691 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
692 } else {
693 __ movflt(dest->as_xmm_float_reg(),
694 InternalAddress(float_constant(c->as_jfloat())));
695 }
696 } else {
697 assert(dest->is_single_fpu(), "must be");
698 assert(dest->fpu_regnr() == 0, "dest must be TOS");
699 if (c->is_zero_float()) {
700 __ fldz();
701 } else if (c->is_one_float()) {
702 __ fld1();
703 } else {
704 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
705 }
706 }
707 break;
708 }
710 case T_DOUBLE: {
711 if (dest->is_double_xmm()) {
712 if (c->is_zero_double()) {
713 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
714 } else {
715 __ movdbl(dest->as_xmm_double_reg(),
716 InternalAddress(double_constant(c->as_jdouble())));
717 }
718 } else {
719 assert(dest->is_double_fpu(), "must be");
720 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
721 if (c->is_zero_double()) {
722 __ fldz();
723 } else if (c->is_one_double()) {
724 __ fld1();
725 } else {
726 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
727 }
728 }
729 break;
730 }
732 default:
733 ShouldNotReachHere();
734 }
735 }
737 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
738 assert(src->is_constant(), "should not call otherwise");
739 assert(dest->is_stack(), "should not call otherwise");
740 LIR_Const* c = src->as_constant_ptr();
742 switch (c->type()) {
743 case T_INT: // fall through
744 case T_FLOAT:
745 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
746 break;
748 case T_ADDRESS:
749 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
750 break;
752 case T_OBJECT:
753 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
754 break;
756 case T_LONG: // fall through
757 case T_DOUBLE:
758 #ifdef _LP64
759 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
760 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
761 #else
762 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
763 lo_word_offset_in_bytes), c->as_jint_lo_bits());
764 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
765 hi_word_offset_in_bytes), c->as_jint_hi_bits());
766 #endif // _LP64
767 break;
769 default:
770 ShouldNotReachHere();
771 }
772 }
774 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
775 assert(src->is_constant(), "should not call otherwise");
776 assert(dest->is_address(), "should not call otherwise");
777 LIR_Const* c = src->as_constant_ptr();
778 LIR_Address* addr = dest->as_address_ptr();
780 int null_check_here = code_offset();
781 switch (type) {
782 case T_INT: // fall through
783 case T_FLOAT:
784 __ movl(as_Address(addr), c->as_jint_bits());
785 break;
787 case T_ADDRESS:
788 __ movptr(as_Address(addr), c->as_jint_bits());
789 break;
791 case T_OBJECT: // fall through
792 case T_ARRAY:
793 if (c->as_jobject() == NULL) {
794 if (UseCompressedOops && !wide) {
795 __ movl(as_Address(addr), (int32_t)NULL_WORD);
796 } else {
797 __ movptr(as_Address(addr), NULL_WORD);
798 }
799 } else {
800 if (is_literal_address(addr)) {
801 ShouldNotReachHere();
802 __ movoop(as_Address(addr, noreg), c->as_jobject());
803 } else {
804 #ifdef _LP64
805 __ movoop(rscratch1, c->as_jobject());
806 if (UseCompressedOops && !wide) {
807 __ encode_heap_oop(rscratch1);
808 null_check_here = code_offset();
809 __ movl(as_Address_lo(addr), rscratch1);
810 } else {
811 null_check_here = code_offset();
812 __ movptr(as_Address_lo(addr), rscratch1);
813 }
814 #else
815 __ movoop(as_Address(addr), c->as_jobject());
816 #endif
817 }
818 }
819 break;
821 case T_LONG: // fall through
822 case T_DOUBLE:
823 #ifdef _LP64
824 if (is_literal_address(addr)) {
825 ShouldNotReachHere();
826 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
827 } else {
828 __ movptr(r10, (intptr_t)c->as_jlong_bits());
829 null_check_here = code_offset();
830 __ movptr(as_Address_lo(addr), r10);
831 }
832 #else
833 // Always reachable in 32bit so this doesn't produce useless move literal
834 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
835 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
836 #endif // _LP64
837 break;
839 case T_BOOLEAN: // fall through
840 case T_BYTE:
841 __ movb(as_Address(addr), c->as_jint() & 0xFF);
842 break;
844 case T_CHAR: // fall through
845 case T_SHORT:
846 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
847 break;
849 default:
850 ShouldNotReachHere();
851 };
853 if (info != NULL) {
854 add_debug_info_for_null_check(null_check_here, info);
855 }
856 }
859 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
860 assert(src->is_register(), "should not call otherwise");
861 assert(dest->is_register(), "should not call otherwise");
863 // move between cpu-registers
864 if (dest->is_single_cpu()) {
865 #ifdef _LP64
866 if (src->type() == T_LONG) {
867 // Can do LONG -> OBJECT
868 move_regs(src->as_register_lo(), dest->as_register());
869 return;
870 }
871 #endif
872 assert(src->is_single_cpu(), "must match");
873 if (src->type() == T_OBJECT) {
874 __ verify_oop(src->as_register());
875 }
876 move_regs(src->as_register(), dest->as_register());
878 } else if (dest->is_double_cpu()) {
879 #ifdef _LP64
880 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
881 // Surprising to me but we can see move of a long to t_object
882 __ verify_oop(src->as_register());
883 move_regs(src->as_register(), dest->as_register_lo());
884 return;
885 }
886 #endif
887 assert(src->is_double_cpu(), "must match");
888 Register f_lo = src->as_register_lo();
889 Register f_hi = src->as_register_hi();
890 Register t_lo = dest->as_register_lo();
891 Register t_hi = dest->as_register_hi();
892 #ifdef _LP64
893 assert(f_hi == f_lo, "must be same");
894 assert(t_hi == t_lo, "must be same");
895 move_regs(f_lo, t_lo);
896 #else
897 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
900 if (f_lo == t_hi && f_hi == t_lo) {
901 swap_reg(f_lo, f_hi);
902 } else if (f_hi == t_lo) {
903 assert(f_lo != t_hi, "overwriting register");
904 move_regs(f_hi, t_hi);
905 move_regs(f_lo, t_lo);
906 } else {
907 assert(f_hi != t_lo, "overwriting register");
908 move_regs(f_lo, t_lo);
909 move_regs(f_hi, t_hi);
910 }
911 #endif // LP64
913 // special moves from fpu-register to xmm-register
914 // necessary for method results
915 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
916 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
917 __ fld_s(Address(rsp, 0));
918 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
919 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
920 __ fld_d(Address(rsp, 0));
921 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
922 __ fstp_s(Address(rsp, 0));
923 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
924 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
925 __ fstp_d(Address(rsp, 0));
926 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
928 // move between xmm-registers
929 } else if (dest->is_single_xmm()) {
930 assert(src->is_single_xmm(), "must match");
931 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
932 } else if (dest->is_double_xmm()) {
933 assert(src->is_double_xmm(), "must match");
934 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
936 // move between fpu-registers (no instruction necessary because of fpu-stack)
937 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
938 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
939 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
940 } else {
941 ShouldNotReachHere();
942 }
943 }
945 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
946 assert(src->is_register(), "should not call otherwise");
947 assert(dest->is_stack(), "should not call otherwise");
949 if (src->is_single_cpu()) {
950 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
951 if (type == T_OBJECT || type == T_ARRAY) {
952 __ verify_oop(src->as_register());
953 __ movptr (dst, src->as_register());
954 } else if (type == T_METADATA) {
955 __ movptr (dst, src->as_register());
956 } else {
957 __ movl (dst, src->as_register());
958 }
960 } else if (src->is_double_cpu()) {
961 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
962 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
963 __ movptr (dstLO, src->as_register_lo());
964 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
966 } else if (src->is_single_xmm()) {
967 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
968 __ movflt(dst_addr, src->as_xmm_float_reg());
970 } else if (src->is_double_xmm()) {
971 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
972 __ movdbl(dst_addr, src->as_xmm_double_reg());
974 } else if (src->is_single_fpu()) {
975 assert(src->fpu_regnr() == 0, "argument must be on TOS");
976 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
977 if (pop_fpu_stack) __ fstp_s (dst_addr);
978 else __ fst_s (dst_addr);
980 } else if (src->is_double_fpu()) {
981 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
982 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
983 if (pop_fpu_stack) __ fstp_d (dst_addr);
984 else __ fst_d (dst_addr);
986 } else {
987 ShouldNotReachHere();
988 }
989 }
992 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
993 LIR_Address* to_addr = dest->as_address_ptr();
994 PatchingStub* patch = NULL;
995 Register compressed_src = rscratch1;
997 if (type == T_ARRAY || type == T_OBJECT) {
998 __ verify_oop(src->as_register());
999 #ifdef _LP64
1000 if (UseCompressedOops && !wide) {
1001 __ movptr(compressed_src, src->as_register());
1002 __ encode_heap_oop(compressed_src);
1003 }
1004 #endif
1005 }
1007 if (patch_code != lir_patch_none) {
1008 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1009 Address toa = as_Address(to_addr);
1010 assert(toa.disp() != 0, "must have");
1011 }
1013 int null_check_here = code_offset();
1014 switch (type) {
1015 case T_FLOAT: {
1016 if (src->is_single_xmm()) {
1017 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1018 } else {
1019 assert(src->is_single_fpu(), "must be");
1020 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1021 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1022 else __ fst_s (as_Address(to_addr));
1023 }
1024 break;
1025 }
1027 case T_DOUBLE: {
1028 if (src->is_double_xmm()) {
1029 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1030 } else {
1031 assert(src->is_double_fpu(), "must be");
1032 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1033 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1034 else __ fst_d (as_Address(to_addr));
1035 }
1036 break;
1037 }
1039 case T_ARRAY: // fall through
1040 case T_OBJECT: // fall through
1041 if (UseCompressedOops && !wide) {
1042 __ movl(as_Address(to_addr), compressed_src);
1043 } else {
1044 __ movptr(as_Address(to_addr), src->as_register());
1045 }
1046 break;
1047 case T_METADATA:
1048 // We get here to store a method pointer to the stack to pass to
1049 // a dtrace runtime call. This can't work on 64 bit with
1050 // compressed klass ptrs: T_METADATA can be a compressed klass
1051 // ptr or a 64 bit method pointer.
1052 LP64_ONLY(ShouldNotReachHere());
1053 __ movptr(as_Address(to_addr), src->as_register());
1054 break;
1055 case T_ADDRESS:
1056 __ movptr(as_Address(to_addr), src->as_register());
1057 break;
1058 case T_INT:
1059 __ movl(as_Address(to_addr), src->as_register());
1060 break;
1062 case T_LONG: {
1063 Register from_lo = src->as_register_lo();
1064 Register from_hi = src->as_register_hi();
1065 #ifdef _LP64
1066 __ movptr(as_Address_lo(to_addr), from_lo);
1067 #else
1068 Register base = to_addr->base()->as_register();
1069 Register index = noreg;
1070 if (to_addr->index()->is_register()) {
1071 index = to_addr->index()->as_register();
1072 }
1073 if (base == from_lo || index == from_lo) {
1074 assert(base != from_hi, "can't be");
1075 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1076 __ movl(as_Address_hi(to_addr), from_hi);
1077 if (patch != NULL) {
1078 patching_epilog(patch, lir_patch_high, base, info);
1079 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1080 patch_code = lir_patch_low;
1081 }
1082 __ movl(as_Address_lo(to_addr), from_lo);
1083 } else {
1084 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1085 __ movl(as_Address_lo(to_addr), from_lo);
1086 if (patch != NULL) {
1087 patching_epilog(patch, lir_patch_low, base, info);
1088 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1089 patch_code = lir_patch_high;
1090 }
1091 __ movl(as_Address_hi(to_addr), from_hi);
1092 }
1093 #endif // _LP64
1094 break;
1095 }
1097 case T_BYTE: // fall through
1098 case T_BOOLEAN: {
1099 Register src_reg = src->as_register();
1100 Address dst_addr = as_Address(to_addr);
1101 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1102 __ movb(dst_addr, src_reg);
1103 break;
1104 }
1106 case T_CHAR: // fall through
1107 case T_SHORT:
1108 __ movw(as_Address(to_addr), src->as_register());
1109 break;
1111 default:
1112 ShouldNotReachHere();
1113 }
1114 if (info != NULL) {
1115 add_debug_info_for_null_check(null_check_here, info);
1116 }
1118 if (patch_code != lir_patch_none) {
1119 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1120 }
1121 }
1124 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1125 assert(src->is_stack(), "should not call otherwise");
1126 assert(dest->is_register(), "should not call otherwise");
1128 if (dest->is_single_cpu()) {
1129 if (type == T_ARRAY || type == T_OBJECT) {
1130 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1131 __ verify_oop(dest->as_register());
1132 } else if (type == T_METADATA) {
1133 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1134 } else {
1135 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1136 }
1138 } else if (dest->is_double_cpu()) {
1139 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1140 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1141 __ movptr(dest->as_register_lo(), src_addr_LO);
1142 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1144 } else if (dest->is_single_xmm()) {
1145 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1146 __ movflt(dest->as_xmm_float_reg(), src_addr);
1148 } else if (dest->is_double_xmm()) {
1149 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1150 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1152 } else if (dest->is_single_fpu()) {
1153 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1154 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1155 __ fld_s(src_addr);
1157 } else if (dest->is_double_fpu()) {
1158 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1159 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1160 __ fld_d(src_addr);
1162 } else {
1163 ShouldNotReachHere();
1164 }
1165 }
1168 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1169 if (src->is_single_stack()) {
1170 if (type == T_OBJECT || type == T_ARRAY) {
1171 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1172 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1173 } else {
1174 #ifndef _LP64
1175 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1176 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1177 #else
1178 //no pushl on 64bits
1179 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1180 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1181 #endif
1182 }
1184 } else if (src->is_double_stack()) {
1185 #ifdef _LP64
1186 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1187 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1188 #else
1189 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1190 // push and pop the part at src + wordSize, adding wordSize for the previous push
1191 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1192 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1193 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1194 #endif // _LP64
1196 } else {
1197 ShouldNotReachHere();
1198 }
1199 }
1202 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1203 assert(src->is_address(), "should not call otherwise");
1204 assert(dest->is_register(), "should not call otherwise");
1206 LIR_Address* addr = src->as_address_ptr();
1207 Address from_addr = as_Address(addr);
1209 if (addr->base()->type() == T_OBJECT) {
1210 __ verify_oop(addr->base()->as_pointer_register());
1211 }
1213 switch (type) {
1214 case T_BOOLEAN: // fall through
1215 case T_BYTE: // fall through
1216 case T_CHAR: // fall through
1217 case T_SHORT:
1218 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1219 // on pre P6 processors we may get partial register stalls
1220 // so blow away the value of to_rinfo before loading a
1221 // partial word into it. Do it here so that it precedes
1222 // the potential patch point below.
1223 __ xorptr(dest->as_register(), dest->as_register());
1224 }
1225 break;
1226 }
1228 PatchingStub* patch = NULL;
1229 if (patch_code != lir_patch_none) {
1230 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1231 assert(from_addr.disp() != 0, "must have");
1232 }
1233 if (info != NULL) {
1234 add_debug_info_for_null_check_here(info);
1235 }
1237 switch (type) {
1238 case T_FLOAT: {
1239 if (dest->is_single_xmm()) {
1240 __ movflt(dest->as_xmm_float_reg(), from_addr);
1241 } else {
1242 assert(dest->is_single_fpu(), "must be");
1243 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1244 __ fld_s(from_addr);
1245 }
1246 break;
1247 }
1249 case T_DOUBLE: {
1250 if (dest->is_double_xmm()) {
1251 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1252 } else {
1253 assert(dest->is_double_fpu(), "must be");
1254 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1255 __ fld_d(from_addr);
1256 }
1257 break;
1258 }
1260 case T_OBJECT: // fall through
1261 case T_ARRAY: // fall through
1262 if (UseCompressedOops && !wide) {
1263 __ movl(dest->as_register(), from_addr);
1264 } else {
1265 __ movptr(dest->as_register(), from_addr);
1266 }
1267 break;
1269 case T_ADDRESS:
1270 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1271 __ movl(dest->as_register(), from_addr);
1272 } else {
1273 __ movptr(dest->as_register(), from_addr);
1274 }
1275 break;
1276 case T_INT:
1277 __ movl(dest->as_register(), from_addr);
1278 break;
1280 case T_LONG: {
1281 Register to_lo = dest->as_register_lo();
1282 Register to_hi = dest->as_register_hi();
1283 #ifdef _LP64
1284 __ movptr(to_lo, as_Address_lo(addr));
1285 #else
1286 Register base = addr->base()->as_register();
1287 Register index = noreg;
1288 if (addr->index()->is_register()) {
1289 index = addr->index()->as_register();
1290 }
1291 if ((base == to_lo && index == to_hi) ||
1292 (base == to_hi && index == to_lo)) {
1293 // addresses with 2 registers are only formed as a result of
1294 // array access so this code will never have to deal with
1295 // patches or null checks.
1296 assert(info == NULL && patch == NULL, "must be");
1297 __ lea(to_hi, as_Address(addr));
1298 __ movl(to_lo, Address(to_hi, 0));
1299 __ movl(to_hi, Address(to_hi, BytesPerWord));
1300 } else if (base == to_lo || index == to_lo) {
1301 assert(base != to_hi, "can't be");
1302 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1303 __ movl(to_hi, as_Address_hi(addr));
1304 if (patch != NULL) {
1305 patching_epilog(patch, lir_patch_high, base, info);
1306 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1307 patch_code = lir_patch_low;
1308 }
1309 __ movl(to_lo, as_Address_lo(addr));
1310 } else {
1311 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1312 __ movl(to_lo, as_Address_lo(addr));
1313 if (patch != NULL) {
1314 patching_epilog(patch, lir_patch_low, base, info);
1315 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1316 patch_code = lir_patch_high;
1317 }
1318 __ movl(to_hi, as_Address_hi(addr));
1319 }
1320 #endif // _LP64
1321 break;
1322 }
1324 case T_BOOLEAN: // fall through
1325 case T_BYTE: {
1326 Register dest_reg = dest->as_register();
1327 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1328 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1329 __ movsbl(dest_reg, from_addr);
1330 } else {
1331 __ movb(dest_reg, from_addr);
1332 __ shll(dest_reg, 24);
1333 __ sarl(dest_reg, 24);
1334 }
1335 break;
1336 }
1338 case T_CHAR: {
1339 Register dest_reg = dest->as_register();
1340 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1341 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1342 __ movzwl(dest_reg, from_addr);
1343 } else {
1344 __ movw(dest_reg, from_addr);
1345 }
1346 break;
1347 }
1349 case T_SHORT: {
1350 Register dest_reg = dest->as_register();
1351 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1352 __ movswl(dest_reg, from_addr);
1353 } else {
1354 __ movw(dest_reg, from_addr);
1355 __ shll(dest_reg, 16);
1356 __ sarl(dest_reg, 16);
1357 }
1358 break;
1359 }
1361 default:
1362 ShouldNotReachHere();
1363 }
1365 if (patch != NULL) {
1366 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1367 }
1369 if (type == T_ARRAY || type == T_OBJECT) {
1370 #ifdef _LP64
1371 if (UseCompressedOops && !wide) {
1372 __ decode_heap_oop(dest->as_register());
1373 }
1374 #endif
1375 __ verify_oop(dest->as_register());
1376 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1377 #ifdef _LP64
1378 if (UseCompressedClassPointers) {
1379 __ decode_klass_not_null(dest->as_register());
1380 }
1381 #endif
1382 }
1383 }
1386 void LIR_Assembler::prefetchr(LIR_Opr src) {
1387 LIR_Address* addr = src->as_address_ptr();
1388 Address from_addr = as_Address(addr);
1390 if (VM_Version::supports_sse()) {
1391 switch (ReadPrefetchInstr) {
1392 case 0:
1393 __ prefetchnta(from_addr); break;
1394 case 1:
1395 __ prefetcht0(from_addr); break;
1396 case 2:
1397 __ prefetcht2(from_addr); break;
1398 default:
1399 ShouldNotReachHere(); break;
1400 }
1401 } else if (VM_Version::supports_3dnow_prefetch()) {
1402 __ prefetchr(from_addr);
1403 }
1404 }
1407 void LIR_Assembler::prefetchw(LIR_Opr src) {
1408 LIR_Address* addr = src->as_address_ptr();
1409 Address from_addr = as_Address(addr);
1411 if (VM_Version::supports_sse()) {
1412 switch (AllocatePrefetchInstr) {
1413 case 0:
1414 __ prefetchnta(from_addr); break;
1415 case 1:
1416 __ prefetcht0(from_addr); break;
1417 case 2:
1418 __ prefetcht2(from_addr); break;
1419 case 3:
1420 __ prefetchw(from_addr); break;
1421 default:
1422 ShouldNotReachHere(); break;
1423 }
1424 } else if (VM_Version::supports_3dnow_prefetch()) {
1425 __ prefetchw(from_addr);
1426 }
1427 }
1430 NEEDS_CLEANUP; // This could be static?
1431 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1432 int elem_size = type2aelembytes(type);
1433 switch (elem_size) {
1434 case 1: return Address::times_1;
1435 case 2: return Address::times_2;
1436 case 4: return Address::times_4;
1437 case 8: return Address::times_8;
1438 }
1439 ShouldNotReachHere();
1440 return Address::no_scale;
1441 }
1444 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1445 switch (op->code()) {
1446 case lir_idiv:
1447 case lir_irem:
1448 arithmetic_idiv(op->code(),
1449 op->in_opr1(),
1450 op->in_opr2(),
1451 op->in_opr3(),
1452 op->result_opr(),
1453 op->info());
1454 break;
1455 default: ShouldNotReachHere(); break;
1456 }
1457 }
1459 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1460 #ifdef ASSERT
1461 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1462 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1463 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1464 #endif
1466 if (op->cond() == lir_cond_always) {
1467 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1468 __ jmp (*(op->label()));
1469 } else {
1470 Assembler::Condition acond = Assembler::zero;
1471 if (op->code() == lir_cond_float_branch) {
1472 assert(op->ublock() != NULL, "must have unordered successor");
1473 __ jcc(Assembler::parity, *(op->ublock()->label()));
1474 switch(op->cond()) {
1475 case lir_cond_equal: acond = Assembler::equal; break;
1476 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1477 case lir_cond_less: acond = Assembler::below; break;
1478 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1479 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1480 case lir_cond_greater: acond = Assembler::above; break;
1481 default: ShouldNotReachHere();
1482 }
1483 } else {
1484 switch (op->cond()) {
1485 case lir_cond_equal: acond = Assembler::equal; break;
1486 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1487 case lir_cond_less: acond = Assembler::less; break;
1488 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1489 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1490 case lir_cond_greater: acond = Assembler::greater; break;
1491 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1492 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1493 default: ShouldNotReachHere();
1494 }
1495 }
1496 __ jcc(acond,*(op->label()));
1497 }
1498 }
1500 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1501 LIR_Opr src = op->in_opr();
1502 LIR_Opr dest = op->result_opr();
1504 switch (op->bytecode()) {
1505 case Bytecodes::_i2l:
1506 #ifdef _LP64
1507 __ movl2ptr(dest->as_register_lo(), src->as_register());
1508 #else
1509 move_regs(src->as_register(), dest->as_register_lo());
1510 move_regs(src->as_register(), dest->as_register_hi());
1511 __ sarl(dest->as_register_hi(), 31);
1512 #endif // LP64
1513 break;
1515 case Bytecodes::_l2i:
1516 #ifdef _LP64
1517 __ movl(dest->as_register(), src->as_register_lo());
1518 #else
1519 move_regs(src->as_register_lo(), dest->as_register());
1520 #endif
1521 break;
1523 case Bytecodes::_i2b:
1524 move_regs(src->as_register(), dest->as_register());
1525 __ sign_extend_byte(dest->as_register());
1526 break;
1528 case Bytecodes::_i2c:
1529 move_regs(src->as_register(), dest->as_register());
1530 __ andl(dest->as_register(), 0xFFFF);
1531 break;
1533 case Bytecodes::_i2s:
1534 move_regs(src->as_register(), dest->as_register());
1535 __ sign_extend_short(dest->as_register());
1536 break;
1539 case Bytecodes::_f2d:
1540 case Bytecodes::_d2f:
1541 if (dest->is_single_xmm()) {
1542 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1543 } else if (dest->is_double_xmm()) {
1544 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1545 } else {
1546 assert(src->fpu() == dest->fpu(), "register must be equal");
1547 // do nothing (float result is rounded later through spilling)
1548 }
1549 break;
1551 case Bytecodes::_i2f:
1552 case Bytecodes::_i2d:
1553 if (dest->is_single_xmm()) {
1554 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1555 } else if (dest->is_double_xmm()) {
1556 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1557 } else {
1558 assert(dest->fpu() == 0, "result must be on TOS");
1559 __ movl(Address(rsp, 0), src->as_register());
1560 __ fild_s(Address(rsp, 0));
1561 }
1562 break;
1564 case Bytecodes::_f2i:
1565 case Bytecodes::_d2i:
1566 if (src->is_single_xmm()) {
1567 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1568 } else if (src->is_double_xmm()) {
1569 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1570 } else {
1571 assert(src->fpu() == 0, "input must be on TOS");
1572 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1573 __ fist_s(Address(rsp, 0));
1574 __ movl(dest->as_register(), Address(rsp, 0));
1575 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1576 }
1578 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1579 assert(op->stub() != NULL, "stub required");
1580 __ cmpl(dest->as_register(), 0x80000000);
1581 __ jcc(Assembler::equal, *op->stub()->entry());
1582 __ bind(*op->stub()->continuation());
1583 break;
1585 case Bytecodes::_l2f:
1586 case Bytecodes::_l2d:
1587 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1588 assert(dest->fpu() == 0, "result must be on TOS");
1590 __ movptr(Address(rsp, 0), src->as_register_lo());
1591 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1592 __ fild_d(Address(rsp, 0));
1593 // float result is rounded later through spilling
1594 break;
1596 case Bytecodes::_f2l:
1597 case Bytecodes::_d2l:
1598 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1599 assert(src->fpu() == 0, "input must be on TOS");
1600 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1602 // instruction sequence too long to inline it here
1603 {
1604 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1605 }
1606 break;
1608 default: ShouldNotReachHere();
1609 }
1610 }
1612 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1613 if (op->init_check()) {
1614 __ cmpb(Address(op->klass()->as_register(),
1615 InstanceKlass::init_state_offset()),
1616 InstanceKlass::fully_initialized);
1617 add_debug_info_for_null_check_here(op->stub()->info());
1618 __ jcc(Assembler::notEqual, *op->stub()->entry());
1619 }
1620 __ allocate_object(op->obj()->as_register(),
1621 op->tmp1()->as_register(),
1622 op->tmp2()->as_register(),
1623 op->header_size(),
1624 op->object_size(),
1625 op->klass()->as_register(),
1626 *op->stub()->entry());
1627 __ bind(*op->stub()->continuation());
1628 }
1630 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1631 Register len = op->len()->as_register();
1632 LP64_ONLY( __ movslq(len, len); )
1634 if (UseSlowPath ||
1635 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1636 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1637 __ jmp(*op->stub()->entry());
1638 } else {
1639 Register tmp1 = op->tmp1()->as_register();
1640 Register tmp2 = op->tmp2()->as_register();
1641 Register tmp3 = op->tmp3()->as_register();
1642 if (len == tmp1) {
1643 tmp1 = tmp3;
1644 } else if (len == tmp2) {
1645 tmp2 = tmp3;
1646 } else if (len == tmp3) {
1647 // everything is ok
1648 } else {
1649 __ mov(tmp3, len);
1650 }
1651 __ allocate_array(op->obj()->as_register(),
1652 len,
1653 tmp1,
1654 tmp2,
1655 arrayOopDesc::header_size(op->type()),
1656 array_element_size(op->type()),
1657 op->klass()->as_register(),
1658 *op->stub()->entry());
1659 }
1660 __ bind(*op->stub()->continuation());
1661 }
1663 void LIR_Assembler::type_profile_helper(Register mdo,
1664 ciMethodData *md, ciProfileData *data,
1665 Register recv, Label* update_done) {
1666 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1667 Label next_test;
1668 // See if the receiver is receiver[n].
1669 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1670 __ jccb(Assembler::notEqual, next_test);
1671 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1672 __ addptr(data_addr, DataLayout::counter_increment);
1673 __ jmp(*update_done);
1674 __ bind(next_test);
1675 }
1677 // Didn't find receiver; find next empty slot and fill it in
1678 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1679 Label next_test;
1680 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1681 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1682 __ jccb(Assembler::notEqual, next_test);
1683 __ movptr(recv_addr, recv);
1684 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1685 __ jmp(*update_done);
1686 __ bind(next_test);
1687 }
1688 }
1690 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1691 // we always need a stub for the failure case.
1692 CodeStub* stub = op->stub();
1693 Register obj = op->object()->as_register();
1694 Register k_RInfo = op->tmp1()->as_register();
1695 Register klass_RInfo = op->tmp2()->as_register();
1696 Register dst = op->result_opr()->as_register();
1697 ciKlass* k = op->klass();
1698 Register Rtmp1 = noreg;
1700 // check if it needs to be profiled
1701 ciMethodData* md;
1702 ciProfileData* data;
1704 if (op->should_profile()) {
1705 ciMethod* method = op->profiled_method();
1706 assert(method != NULL, "Should have method");
1707 int bci = op->profiled_bci();
1708 md = method->method_data_or_null();
1709 assert(md != NULL, "Sanity");
1710 data = md->bci_to_data(bci);
1711 assert(data != NULL, "need data for type check");
1712 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1713 }
1714 Label profile_cast_success, profile_cast_failure;
1715 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1716 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1718 if (obj == k_RInfo) {
1719 k_RInfo = dst;
1720 } else if (obj == klass_RInfo) {
1721 klass_RInfo = dst;
1722 }
1723 if (k->is_loaded() && !UseCompressedClassPointers) {
1724 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1725 } else {
1726 Rtmp1 = op->tmp3()->as_register();
1727 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1728 }
1730 assert_different_registers(obj, k_RInfo, klass_RInfo);
1732 __ cmpptr(obj, (int32_t)NULL_WORD);
1733 if (op->should_profile()) {
1734 Label not_null;
1735 __ jccb(Assembler::notEqual, not_null);
1736 // Object is null; update MDO and exit
1737 Register mdo = klass_RInfo;
1738 __ mov_metadata(mdo, md->constant_encoding());
1739 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1740 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1741 __ orl(data_addr, header_bits);
1742 __ jmp(*obj_is_null);
1743 __ bind(not_null);
1744 } else {
1745 __ jcc(Assembler::equal, *obj_is_null);
1746 }
1748 if (!k->is_loaded()) {
1749 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1750 } else {
1751 #ifdef _LP64
1752 __ mov_metadata(k_RInfo, k->constant_encoding());
1753 #endif // _LP64
1754 }
1755 __ verify_oop(obj);
1757 if (op->fast_check()) {
1758 // get object class
1759 // not a safepoint as obj null check happens earlier
1760 #ifdef _LP64
1761 if (UseCompressedClassPointers) {
1762 __ load_klass(Rtmp1, obj);
1763 __ cmpptr(k_RInfo, Rtmp1);
1764 } else {
1765 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1766 }
1767 #else
1768 if (k->is_loaded()) {
1769 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1770 } else {
1771 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1772 }
1773 #endif
1774 __ jcc(Assembler::notEqual, *failure_target);
1775 // successful cast, fall through to profile or jump
1776 } else {
1777 // get object class
1778 // not a safepoint as obj null check happens earlier
1779 __ load_klass(klass_RInfo, obj);
1780 if (k->is_loaded()) {
1781 // See if we get an immediate positive hit
1782 #ifdef _LP64
1783 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1784 #else
1785 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1786 #endif // _LP64
1787 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1788 __ jcc(Assembler::notEqual, *failure_target);
1789 // successful cast, fall through to profile or jump
1790 } else {
1791 // See if we get an immediate positive hit
1792 __ jcc(Assembler::equal, *success_target);
1793 // check for self
1794 #ifdef _LP64
1795 __ cmpptr(klass_RInfo, k_RInfo);
1796 #else
1797 __ cmpklass(klass_RInfo, k->constant_encoding());
1798 #endif // _LP64
1799 __ jcc(Assembler::equal, *success_target);
1801 __ push(klass_RInfo);
1802 #ifdef _LP64
1803 __ push(k_RInfo);
1804 #else
1805 __ pushklass(k->constant_encoding());
1806 #endif // _LP64
1807 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1808 __ pop(klass_RInfo);
1809 __ pop(klass_RInfo);
1810 // result is a boolean
1811 __ cmpl(klass_RInfo, 0);
1812 __ jcc(Assembler::equal, *failure_target);
1813 // successful cast, fall through to profile or jump
1814 }
1815 } else {
1816 // perform the fast part of the checking logic
1817 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1818 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1819 __ push(klass_RInfo);
1820 __ push(k_RInfo);
1821 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1822 __ pop(klass_RInfo);
1823 __ pop(k_RInfo);
1824 // result is a boolean
1825 __ cmpl(k_RInfo, 0);
1826 __ jcc(Assembler::equal, *failure_target);
1827 // successful cast, fall through to profile or jump
1828 }
1829 }
1830 if (op->should_profile()) {
1831 Register mdo = klass_RInfo, recv = k_RInfo;
1832 __ bind(profile_cast_success);
1833 __ mov_metadata(mdo, md->constant_encoding());
1834 __ load_klass(recv, obj);
1835 Label update_done;
1836 type_profile_helper(mdo, md, data, recv, success);
1837 __ jmp(*success);
1839 __ bind(profile_cast_failure);
1840 __ mov_metadata(mdo, md->constant_encoding());
1841 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1842 __ subptr(counter_addr, DataLayout::counter_increment);
1843 __ jmp(*failure);
1844 }
1845 __ jmp(*success);
1846 }
1849 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1850 LIR_Code code = op->code();
1851 if (code == lir_store_check) {
1852 Register value = op->object()->as_register();
1853 Register array = op->array()->as_register();
1854 Register k_RInfo = op->tmp1()->as_register();
1855 Register klass_RInfo = op->tmp2()->as_register();
1856 Register Rtmp1 = op->tmp3()->as_register();
1858 CodeStub* stub = op->stub();
1860 // check if it needs to be profiled
1861 ciMethodData* md;
1862 ciProfileData* data;
1864 if (op->should_profile()) {
1865 ciMethod* method = op->profiled_method();
1866 assert(method != NULL, "Should have method");
1867 int bci = op->profiled_bci();
1868 md = method->method_data_or_null();
1869 assert(md != NULL, "Sanity");
1870 data = md->bci_to_data(bci);
1871 assert(data != NULL, "need data for type check");
1872 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1873 }
1874 Label profile_cast_success, profile_cast_failure, done;
1875 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1876 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1878 __ cmpptr(value, (int32_t)NULL_WORD);
1879 if (op->should_profile()) {
1880 Label not_null;
1881 __ jccb(Assembler::notEqual, not_null);
1882 // Object is null; update MDO and exit
1883 Register mdo = klass_RInfo;
1884 __ mov_metadata(mdo, md->constant_encoding());
1885 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1886 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1887 __ orl(data_addr, header_bits);
1888 __ jmp(done);
1889 __ bind(not_null);
1890 } else {
1891 __ jcc(Assembler::equal, done);
1892 }
1894 add_debug_info_for_null_check_here(op->info_for_exception());
1895 __ load_klass(k_RInfo, array);
1896 __ load_klass(klass_RInfo, value);
1898 // get instance klass (it's already uncompressed)
1899 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1900 // perform the fast part of the checking logic
1901 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1902 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1903 __ push(klass_RInfo);
1904 __ push(k_RInfo);
1905 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1906 __ pop(klass_RInfo);
1907 __ pop(k_RInfo);
1908 // result is a boolean
1909 __ cmpl(k_RInfo, 0);
1910 __ jcc(Assembler::equal, *failure_target);
1911 // fall through to the success case
1913 if (op->should_profile()) {
1914 Register mdo = klass_RInfo, recv = k_RInfo;
1915 __ bind(profile_cast_success);
1916 __ mov_metadata(mdo, md->constant_encoding());
1917 __ load_klass(recv, value);
1918 Label update_done;
1919 type_profile_helper(mdo, md, data, recv, &done);
1920 __ jmpb(done);
1922 __ bind(profile_cast_failure);
1923 __ mov_metadata(mdo, md->constant_encoding());
1924 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1925 __ subptr(counter_addr, DataLayout::counter_increment);
1926 __ jmp(*stub->entry());
1927 }
1929 __ bind(done);
1930 } else
1931 if (code == lir_checkcast) {
1932 Register obj = op->object()->as_register();
1933 Register dst = op->result_opr()->as_register();
1934 Label success;
1935 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1936 __ bind(success);
1937 if (dst != obj) {
1938 __ mov(dst, obj);
1939 }
1940 } else
1941 if (code == lir_instanceof) {
1942 Register obj = op->object()->as_register();
1943 Register dst = op->result_opr()->as_register();
1944 Label success, failure, done;
1945 emit_typecheck_helper(op, &success, &failure, &failure);
1946 __ bind(failure);
1947 __ xorptr(dst, dst);
1948 __ jmpb(done);
1949 __ bind(success);
1950 __ movptr(dst, 1);
1951 __ bind(done);
1952 } else {
1953 ShouldNotReachHere();
1954 }
1956 }
1959 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1960 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1961 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1962 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1963 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1964 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1965 Register addr = op->addr()->as_register();
1966 if (os::is_MP()) {
1967 __ lock();
1968 }
1969 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1971 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1972 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1973 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1974 Register newval = op->new_value()->as_register();
1975 Register cmpval = op->cmp_value()->as_register();
1976 assert(cmpval == rax, "wrong register");
1977 assert(newval != NULL, "new val must be register");
1978 assert(cmpval != newval, "cmp and new values must be in different registers");
1979 assert(cmpval != addr, "cmp and addr must be in different registers");
1980 assert(newval != addr, "new value and addr must be in different registers");
1982 if ( op->code() == lir_cas_obj) {
1983 #ifdef _LP64
1984 if (UseCompressedOops) {
1985 __ encode_heap_oop(cmpval);
1986 __ mov(rscratch1, newval);
1987 __ encode_heap_oop(rscratch1);
1988 if (os::is_MP()) {
1989 __ lock();
1990 }
1991 // cmpval (rax) is implicitly used by this instruction
1992 __ cmpxchgl(rscratch1, Address(addr, 0));
1993 } else
1994 #endif
1995 {
1996 if (os::is_MP()) {
1997 __ lock();
1998 }
1999 __ cmpxchgptr(newval, Address(addr, 0));
2000 }
2001 } else {
2002 assert(op->code() == lir_cas_int, "lir_cas_int expected");
2003 if (os::is_MP()) {
2004 __ lock();
2005 }
2006 __ cmpxchgl(newval, Address(addr, 0));
2007 }
2008 #ifdef _LP64
2009 } else if (op->code() == lir_cas_long) {
2010 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
2011 Register newval = op->new_value()->as_register_lo();
2012 Register cmpval = op->cmp_value()->as_register_lo();
2013 assert(cmpval == rax, "wrong register");
2014 assert(newval != NULL, "new val must be register");
2015 assert(cmpval != newval, "cmp and new values must be in different registers");
2016 assert(cmpval != addr, "cmp and addr must be in different registers");
2017 assert(newval != addr, "new value and addr must be in different registers");
2018 if (os::is_MP()) {
2019 __ lock();
2020 }
2021 __ cmpxchgq(newval, Address(addr, 0));
2022 #endif // _LP64
2023 } else {
2024 Unimplemented();
2025 }
2026 }
2028 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
2029 Assembler::Condition acond, ncond;
2030 switch (condition) {
2031 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
2032 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
2033 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
2034 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
2035 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
2036 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
2037 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
2038 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
2039 default: ShouldNotReachHere();
2040 }
2042 if (opr1->is_cpu_register()) {
2043 reg2reg(opr1, result);
2044 } else if (opr1->is_stack()) {
2045 stack2reg(opr1, result, result->type());
2046 } else if (opr1->is_constant()) {
2047 const2reg(opr1, result, lir_patch_none, NULL);
2048 } else {
2049 ShouldNotReachHere();
2050 }
2052 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2053 // optimized version that does not require a branch
2054 if (opr2->is_single_cpu()) {
2055 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2056 __ cmov(ncond, result->as_register(), opr2->as_register());
2057 } else if (opr2->is_double_cpu()) {
2058 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2059 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2060 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2061 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2062 } else if (opr2->is_single_stack()) {
2063 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2064 } else if (opr2->is_double_stack()) {
2065 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2066 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2067 } else {
2068 ShouldNotReachHere();
2069 }
2071 } else {
2072 Label skip;
2073 __ jcc (acond, skip);
2074 if (opr2->is_cpu_register()) {
2075 reg2reg(opr2, result);
2076 } else if (opr2->is_stack()) {
2077 stack2reg(opr2, result, result->type());
2078 } else if (opr2->is_constant()) {
2079 const2reg(opr2, result, lir_patch_none, NULL);
2080 } else {
2081 ShouldNotReachHere();
2082 }
2083 __ bind(skip);
2084 }
2085 }
2088 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2089 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2091 if (left->is_single_cpu()) {
2092 assert(left == dest, "left and dest must be equal");
2093 Register lreg = left->as_register();
2095 if (right->is_single_cpu()) {
2096 // cpu register - cpu register
2097 Register rreg = right->as_register();
2098 switch (code) {
2099 case lir_add: __ addl (lreg, rreg); break;
2100 case lir_sub: __ subl (lreg, rreg); break;
2101 case lir_mul: __ imull(lreg, rreg); break;
2102 default: ShouldNotReachHere();
2103 }
2105 } else if (right->is_stack()) {
2106 // cpu register - stack
2107 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2108 switch (code) {
2109 case lir_add: __ addl(lreg, raddr); break;
2110 case lir_sub: __ subl(lreg, raddr); break;
2111 default: ShouldNotReachHere();
2112 }
2114 } else if (right->is_constant()) {
2115 // cpu register - constant
2116 jint c = right->as_constant_ptr()->as_jint();
2117 switch (code) {
2118 case lir_add: {
2119 __ incrementl(lreg, c);
2120 break;
2121 }
2122 case lir_sub: {
2123 __ decrementl(lreg, c);
2124 break;
2125 }
2126 default: ShouldNotReachHere();
2127 }
2129 } else {
2130 ShouldNotReachHere();
2131 }
2133 } else if (left->is_double_cpu()) {
2134 assert(left == dest, "left and dest must be equal");
2135 Register lreg_lo = left->as_register_lo();
2136 Register lreg_hi = left->as_register_hi();
2138 if (right->is_double_cpu()) {
2139 // cpu register - cpu register
2140 Register rreg_lo = right->as_register_lo();
2141 Register rreg_hi = right->as_register_hi();
2142 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2143 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2144 switch (code) {
2145 case lir_add:
2146 __ addptr(lreg_lo, rreg_lo);
2147 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2148 break;
2149 case lir_sub:
2150 __ subptr(lreg_lo, rreg_lo);
2151 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2152 break;
2153 case lir_mul:
2154 #ifdef _LP64
2155 __ imulq(lreg_lo, rreg_lo);
2156 #else
2157 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2158 __ imull(lreg_hi, rreg_lo);
2159 __ imull(rreg_hi, lreg_lo);
2160 __ addl (rreg_hi, lreg_hi);
2161 __ mull (rreg_lo);
2162 __ addl (lreg_hi, rreg_hi);
2163 #endif // _LP64
2164 break;
2165 default:
2166 ShouldNotReachHere();
2167 }
2169 } else if (right->is_constant()) {
2170 // cpu register - constant
2171 #ifdef _LP64
2172 jlong c = right->as_constant_ptr()->as_jlong_bits();
2173 __ movptr(r10, (intptr_t) c);
2174 switch (code) {
2175 case lir_add:
2176 __ addptr(lreg_lo, r10);
2177 break;
2178 case lir_sub:
2179 __ subptr(lreg_lo, r10);
2180 break;
2181 default:
2182 ShouldNotReachHere();
2183 }
2184 #else
2185 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2186 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2187 switch (code) {
2188 case lir_add:
2189 __ addptr(lreg_lo, c_lo);
2190 __ adcl(lreg_hi, c_hi);
2191 break;
2192 case lir_sub:
2193 __ subptr(lreg_lo, c_lo);
2194 __ sbbl(lreg_hi, c_hi);
2195 break;
2196 default:
2197 ShouldNotReachHere();
2198 }
2199 #endif // _LP64
2201 } else {
2202 ShouldNotReachHere();
2203 }
2205 } else if (left->is_single_xmm()) {
2206 assert(left == dest, "left and dest must be equal");
2207 XMMRegister lreg = left->as_xmm_float_reg();
2209 if (right->is_single_xmm()) {
2210 XMMRegister rreg = right->as_xmm_float_reg();
2211 switch (code) {
2212 case lir_add: __ addss(lreg, rreg); break;
2213 case lir_sub: __ subss(lreg, rreg); break;
2214 case lir_mul_strictfp: // fall through
2215 case lir_mul: __ mulss(lreg, rreg); break;
2216 case lir_div_strictfp: // fall through
2217 case lir_div: __ divss(lreg, rreg); break;
2218 default: ShouldNotReachHere();
2219 }
2220 } else {
2221 Address raddr;
2222 if (right->is_single_stack()) {
2223 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2224 } else if (right->is_constant()) {
2225 // hack for now
2226 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2227 } else {
2228 ShouldNotReachHere();
2229 }
2230 switch (code) {
2231 case lir_add: __ addss(lreg, raddr); break;
2232 case lir_sub: __ subss(lreg, raddr); break;
2233 case lir_mul_strictfp: // fall through
2234 case lir_mul: __ mulss(lreg, raddr); break;
2235 case lir_div_strictfp: // fall through
2236 case lir_div: __ divss(lreg, raddr); break;
2237 default: ShouldNotReachHere();
2238 }
2239 }
2241 } else if (left->is_double_xmm()) {
2242 assert(left == dest, "left and dest must be equal");
2244 XMMRegister lreg = left->as_xmm_double_reg();
2245 if (right->is_double_xmm()) {
2246 XMMRegister rreg = right->as_xmm_double_reg();
2247 switch (code) {
2248 case lir_add: __ addsd(lreg, rreg); break;
2249 case lir_sub: __ subsd(lreg, rreg); break;
2250 case lir_mul_strictfp: // fall through
2251 case lir_mul: __ mulsd(lreg, rreg); break;
2252 case lir_div_strictfp: // fall through
2253 case lir_div: __ divsd(lreg, rreg); break;
2254 default: ShouldNotReachHere();
2255 }
2256 } else {
2257 Address raddr;
2258 if (right->is_double_stack()) {
2259 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2260 } else if (right->is_constant()) {
2261 // hack for now
2262 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2263 } else {
2264 ShouldNotReachHere();
2265 }
2266 switch (code) {
2267 case lir_add: __ addsd(lreg, raddr); break;
2268 case lir_sub: __ subsd(lreg, raddr); break;
2269 case lir_mul_strictfp: // fall through
2270 case lir_mul: __ mulsd(lreg, raddr); break;
2271 case lir_div_strictfp: // fall through
2272 case lir_div: __ divsd(lreg, raddr); break;
2273 default: ShouldNotReachHere();
2274 }
2275 }
2277 } else if (left->is_single_fpu()) {
2278 assert(dest->is_single_fpu(), "fpu stack allocation required");
2280 if (right->is_single_fpu()) {
2281 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2283 } else {
2284 assert(left->fpu_regnr() == 0, "left must be on TOS");
2285 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2287 Address raddr;
2288 if (right->is_single_stack()) {
2289 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2290 } else if (right->is_constant()) {
2291 address const_addr = float_constant(right->as_jfloat());
2292 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2293 // hack for now
2294 raddr = __ as_Address(InternalAddress(const_addr));
2295 } else {
2296 ShouldNotReachHere();
2297 }
2299 switch (code) {
2300 case lir_add: __ fadd_s(raddr); break;
2301 case lir_sub: __ fsub_s(raddr); break;
2302 case lir_mul_strictfp: // fall through
2303 case lir_mul: __ fmul_s(raddr); break;
2304 case lir_div_strictfp: // fall through
2305 case lir_div: __ fdiv_s(raddr); break;
2306 default: ShouldNotReachHere();
2307 }
2308 }
2310 } else if (left->is_double_fpu()) {
2311 assert(dest->is_double_fpu(), "fpu stack allocation required");
2313 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2314 // Double values require special handling for strictfp mul/div on x86
2315 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2316 __ fmulp(left->fpu_regnrLo() + 1);
2317 }
2319 if (right->is_double_fpu()) {
2320 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2322 } else {
2323 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2324 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2326 Address raddr;
2327 if (right->is_double_stack()) {
2328 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2329 } else if (right->is_constant()) {
2330 // hack for now
2331 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2332 } else {
2333 ShouldNotReachHere();
2334 }
2336 switch (code) {
2337 case lir_add: __ fadd_d(raddr); break;
2338 case lir_sub: __ fsub_d(raddr); break;
2339 case lir_mul_strictfp: // fall through
2340 case lir_mul: __ fmul_d(raddr); break;
2341 case lir_div_strictfp: // fall through
2342 case lir_div: __ fdiv_d(raddr); break;
2343 default: ShouldNotReachHere();
2344 }
2345 }
2347 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2348 // Double values require special handling for strictfp mul/div on x86
2349 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2350 __ fmulp(dest->fpu_regnrLo() + 1);
2351 }
2353 } else if (left->is_single_stack() || left->is_address()) {
2354 assert(left == dest, "left and dest must be equal");
2356 Address laddr;
2357 if (left->is_single_stack()) {
2358 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2359 } else if (left->is_address()) {
2360 laddr = as_Address(left->as_address_ptr());
2361 } else {
2362 ShouldNotReachHere();
2363 }
2365 if (right->is_single_cpu()) {
2366 Register rreg = right->as_register();
2367 switch (code) {
2368 case lir_add: __ addl(laddr, rreg); break;
2369 case lir_sub: __ subl(laddr, rreg); break;
2370 default: ShouldNotReachHere();
2371 }
2372 } else if (right->is_constant()) {
2373 jint c = right->as_constant_ptr()->as_jint();
2374 switch (code) {
2375 case lir_add: {
2376 __ incrementl(laddr, c);
2377 break;
2378 }
2379 case lir_sub: {
2380 __ decrementl(laddr, c);
2381 break;
2382 }
2383 default: ShouldNotReachHere();
2384 }
2385 } else {
2386 ShouldNotReachHere();
2387 }
2389 } else {
2390 ShouldNotReachHere();
2391 }
2392 }
2394 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2395 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2396 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2397 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2399 bool left_is_tos = (left_index == 0);
2400 bool dest_is_tos = (dest_index == 0);
2401 int non_tos_index = (left_is_tos ? right_index : left_index);
2403 switch (code) {
2404 case lir_add:
2405 if (pop_fpu_stack) __ faddp(non_tos_index);
2406 else if (dest_is_tos) __ fadd (non_tos_index);
2407 else __ fadda(non_tos_index);
2408 break;
2410 case lir_sub:
2411 if (left_is_tos) {
2412 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2413 else if (dest_is_tos) __ fsub (non_tos_index);
2414 else __ fsubra(non_tos_index);
2415 } else {
2416 if (pop_fpu_stack) __ fsubp (non_tos_index);
2417 else if (dest_is_tos) __ fsubr (non_tos_index);
2418 else __ fsuba (non_tos_index);
2419 }
2420 break;
2422 case lir_mul_strictfp: // fall through
2423 case lir_mul:
2424 if (pop_fpu_stack) __ fmulp(non_tos_index);
2425 else if (dest_is_tos) __ fmul (non_tos_index);
2426 else __ fmula(non_tos_index);
2427 break;
2429 case lir_div_strictfp: // fall through
2430 case lir_div:
2431 if (left_is_tos) {
2432 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2433 else if (dest_is_tos) __ fdiv (non_tos_index);
2434 else __ fdivra(non_tos_index);
2435 } else {
2436 if (pop_fpu_stack) __ fdivp (non_tos_index);
2437 else if (dest_is_tos) __ fdivr (non_tos_index);
2438 else __ fdiva (non_tos_index);
2439 }
2440 break;
2442 case lir_rem:
2443 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2444 __ fremr(noreg);
2445 break;
2447 default:
2448 ShouldNotReachHere();
2449 }
2450 }
2453 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2454 if (value->is_double_xmm()) {
2455 switch(code) {
2456 case lir_abs :
2457 {
2458 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2459 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2460 }
2461 __ andpd(dest->as_xmm_double_reg(),
2462 ExternalAddress((address)double_signmask_pool));
2463 }
2464 break;
2466 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2467 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2468 default : ShouldNotReachHere();
2469 }
2471 } else if (value->is_double_fpu()) {
2472 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2473 switch(code) {
2474 case lir_log : __ flog() ; break;
2475 case lir_log10 : __ flog10() ; break;
2476 case lir_abs : __ fabs() ; break;
2477 case lir_sqrt : __ fsqrt(); break;
2478 case lir_sin :
2479 // Should consider not saving rbx, if not necessary
2480 __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2481 break;
2482 case lir_cos :
2483 // Should consider not saving rbx, if not necessary
2484 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2485 __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2486 break;
2487 case lir_tan :
2488 // Should consider not saving rbx, if not necessary
2489 __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2490 break;
2491 case lir_exp :
2492 __ exp_with_fallback(op->as_Op2()->fpu_stack_size());
2493 break;
2494 case lir_pow :
2495 __ pow_with_fallback(op->as_Op2()->fpu_stack_size());
2496 break;
2497 default : ShouldNotReachHere();
2498 }
2499 } else {
2500 Unimplemented();
2501 }
2502 }
2504 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2505 // assert(left->destroys_register(), "check");
2506 if (left->is_single_cpu()) {
2507 Register reg = left->as_register();
2508 if (right->is_constant()) {
2509 int val = right->as_constant_ptr()->as_jint();
2510 switch (code) {
2511 case lir_logic_and: __ andl (reg, val); break;
2512 case lir_logic_or: __ orl (reg, val); break;
2513 case lir_logic_xor: __ xorl (reg, val); break;
2514 default: ShouldNotReachHere();
2515 }
2516 } else if (right->is_stack()) {
2517 // added support for stack operands
2518 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2519 switch (code) {
2520 case lir_logic_and: __ andl (reg, raddr); break;
2521 case lir_logic_or: __ orl (reg, raddr); break;
2522 case lir_logic_xor: __ xorl (reg, raddr); break;
2523 default: ShouldNotReachHere();
2524 }
2525 } else {
2526 Register rright = right->as_register();
2527 switch (code) {
2528 case lir_logic_and: __ andptr (reg, rright); break;
2529 case lir_logic_or : __ orptr (reg, rright); break;
2530 case lir_logic_xor: __ xorptr (reg, rright); break;
2531 default: ShouldNotReachHere();
2532 }
2533 }
2534 move_regs(reg, dst->as_register());
2535 } else {
2536 Register l_lo = left->as_register_lo();
2537 Register l_hi = left->as_register_hi();
2538 if (right->is_constant()) {
2539 #ifdef _LP64
2540 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2541 switch (code) {
2542 case lir_logic_and:
2543 __ andq(l_lo, rscratch1);
2544 break;
2545 case lir_logic_or:
2546 __ orq(l_lo, rscratch1);
2547 break;
2548 case lir_logic_xor:
2549 __ xorq(l_lo, rscratch1);
2550 break;
2551 default: ShouldNotReachHere();
2552 }
2553 #else
2554 int r_lo = right->as_constant_ptr()->as_jint_lo();
2555 int r_hi = right->as_constant_ptr()->as_jint_hi();
2556 switch (code) {
2557 case lir_logic_and:
2558 __ andl(l_lo, r_lo);
2559 __ andl(l_hi, r_hi);
2560 break;
2561 case lir_logic_or:
2562 __ orl(l_lo, r_lo);
2563 __ orl(l_hi, r_hi);
2564 break;
2565 case lir_logic_xor:
2566 __ xorl(l_lo, r_lo);
2567 __ xorl(l_hi, r_hi);
2568 break;
2569 default: ShouldNotReachHere();
2570 }
2571 #endif // _LP64
2572 } else {
2573 #ifdef _LP64
2574 Register r_lo;
2575 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2576 r_lo = right->as_register();
2577 } else {
2578 r_lo = right->as_register_lo();
2579 }
2580 #else
2581 Register r_lo = right->as_register_lo();
2582 Register r_hi = right->as_register_hi();
2583 assert(l_lo != r_hi, "overwriting registers");
2584 #endif
2585 switch (code) {
2586 case lir_logic_and:
2587 __ andptr(l_lo, r_lo);
2588 NOT_LP64(__ andptr(l_hi, r_hi);)
2589 break;
2590 case lir_logic_or:
2591 __ orptr(l_lo, r_lo);
2592 NOT_LP64(__ orptr(l_hi, r_hi);)
2593 break;
2594 case lir_logic_xor:
2595 __ xorptr(l_lo, r_lo);
2596 NOT_LP64(__ xorptr(l_hi, r_hi);)
2597 break;
2598 default: ShouldNotReachHere();
2599 }
2600 }
2602 Register dst_lo = dst->as_register_lo();
2603 Register dst_hi = dst->as_register_hi();
2605 #ifdef _LP64
2606 move_regs(l_lo, dst_lo);
2607 #else
2608 if (dst_lo == l_hi) {
2609 assert(dst_hi != l_lo, "overwriting registers");
2610 move_regs(l_hi, dst_hi);
2611 move_regs(l_lo, dst_lo);
2612 } else {
2613 assert(dst_lo != l_hi, "overwriting registers");
2614 move_regs(l_lo, dst_lo);
2615 move_regs(l_hi, dst_hi);
2616 }
2617 #endif // _LP64
2618 }
2619 }
2622 // we assume that rax, and rdx can be overwritten
2623 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2625 assert(left->is_single_cpu(), "left must be register");
2626 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2627 assert(result->is_single_cpu(), "result must be register");
2629 // assert(left->destroys_register(), "check");
2630 // assert(right->destroys_register(), "check");
2632 Register lreg = left->as_register();
2633 Register dreg = result->as_register();
2635 if (right->is_constant()) {
2636 int divisor = right->as_constant_ptr()->as_jint();
2637 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2638 if (code == lir_idiv) {
2639 assert(lreg == rax, "must be rax,");
2640 assert(temp->as_register() == rdx, "tmp register must be rdx");
2641 __ cdql(); // sign extend into rdx:rax
2642 if (divisor == 2) {
2643 __ subl(lreg, rdx);
2644 } else {
2645 __ andl(rdx, divisor - 1);
2646 __ addl(lreg, rdx);
2647 }
2648 __ sarl(lreg, log2_intptr(divisor));
2649 move_regs(lreg, dreg);
2650 } else if (code == lir_irem) {
2651 Label done;
2652 __ mov(dreg, lreg);
2653 __ andl(dreg, 0x80000000 | (divisor - 1));
2654 __ jcc(Assembler::positive, done);
2655 __ decrement(dreg);
2656 __ orl(dreg, ~(divisor - 1));
2657 __ increment(dreg);
2658 __ bind(done);
2659 } else {
2660 ShouldNotReachHere();
2661 }
2662 } else {
2663 Register rreg = right->as_register();
2664 assert(lreg == rax, "left register must be rax,");
2665 assert(rreg != rdx, "right register must not be rdx");
2666 assert(temp->as_register() == rdx, "tmp register must be rdx");
2668 move_regs(lreg, rax);
2670 int idivl_offset = __ corrected_idivl(rreg);
2671 add_debug_info_for_div0(idivl_offset, info);
2672 if (code == lir_irem) {
2673 move_regs(rdx, dreg); // result is in rdx
2674 } else {
2675 move_regs(rax, dreg);
2676 }
2677 }
2678 }
2681 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2682 if (opr1->is_single_cpu()) {
2683 Register reg1 = opr1->as_register();
2684 if (opr2->is_single_cpu()) {
2685 // cpu register - cpu register
2686 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2687 __ cmpptr(reg1, opr2->as_register());
2688 } else {
2689 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2690 __ cmpl(reg1, opr2->as_register());
2691 }
2692 } else if (opr2->is_stack()) {
2693 // cpu register - stack
2694 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2695 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2696 } else {
2697 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2698 }
2699 } else if (opr2->is_constant()) {
2700 // cpu register - constant
2701 LIR_Const* c = opr2->as_constant_ptr();
2702 if (c->type() == T_INT) {
2703 __ cmpl(reg1, c->as_jint());
2704 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2705 // In 64bit oops are single register
2706 jobject o = c->as_jobject();
2707 if (o == NULL) {
2708 __ cmpptr(reg1, (int32_t)NULL_WORD);
2709 } else {
2710 #ifdef _LP64
2711 __ movoop(rscratch1, o);
2712 __ cmpptr(reg1, rscratch1);
2713 #else
2714 __ cmpoop(reg1, c->as_jobject());
2715 #endif // _LP64
2716 }
2717 } else {
2718 fatal(err_msg("unexpected type: %s", basictype_to_str(c->type())));
2719 }
2720 // cpu register - address
2721 } else if (opr2->is_address()) {
2722 if (op->info() != NULL) {
2723 add_debug_info_for_null_check_here(op->info());
2724 }
2725 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2726 } else {
2727 ShouldNotReachHere();
2728 }
2730 } else if(opr1->is_double_cpu()) {
2731 Register xlo = opr1->as_register_lo();
2732 Register xhi = opr1->as_register_hi();
2733 if (opr2->is_double_cpu()) {
2734 #ifdef _LP64
2735 __ cmpptr(xlo, opr2->as_register_lo());
2736 #else
2737 // cpu register - cpu register
2738 Register ylo = opr2->as_register_lo();
2739 Register yhi = opr2->as_register_hi();
2740 __ subl(xlo, ylo);
2741 __ sbbl(xhi, yhi);
2742 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2743 __ orl(xhi, xlo);
2744 }
2745 #endif // _LP64
2746 } else if (opr2->is_constant()) {
2747 // cpu register - constant 0
2748 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2749 #ifdef _LP64
2750 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2751 #else
2752 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2753 __ orl(xhi, xlo);
2754 #endif // _LP64
2755 } else {
2756 ShouldNotReachHere();
2757 }
2759 } else if (opr1->is_single_xmm()) {
2760 XMMRegister reg1 = opr1->as_xmm_float_reg();
2761 if (opr2->is_single_xmm()) {
2762 // xmm register - xmm register
2763 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2764 } else if (opr2->is_stack()) {
2765 // xmm register - stack
2766 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2767 } else if (opr2->is_constant()) {
2768 // xmm register - constant
2769 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2770 } else if (opr2->is_address()) {
2771 // xmm register - address
2772 if (op->info() != NULL) {
2773 add_debug_info_for_null_check_here(op->info());
2774 }
2775 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2776 } else {
2777 ShouldNotReachHere();
2778 }
2780 } else if (opr1->is_double_xmm()) {
2781 XMMRegister reg1 = opr1->as_xmm_double_reg();
2782 if (opr2->is_double_xmm()) {
2783 // xmm register - xmm register
2784 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2785 } else if (opr2->is_stack()) {
2786 // xmm register - stack
2787 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2788 } else if (opr2->is_constant()) {
2789 // xmm register - constant
2790 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2791 } else if (opr2->is_address()) {
2792 // xmm register - address
2793 if (op->info() != NULL) {
2794 add_debug_info_for_null_check_here(op->info());
2795 }
2796 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2797 } else {
2798 ShouldNotReachHere();
2799 }
2801 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2802 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2803 assert(opr2->is_fpu_register(), "both must be registers");
2804 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2806 } else if (opr1->is_address() && opr2->is_constant()) {
2807 LIR_Const* c = opr2->as_constant_ptr();
2808 #ifdef _LP64
2809 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2810 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2811 __ movoop(rscratch1, c->as_jobject());
2812 }
2813 #endif // LP64
2814 if (op->info() != NULL) {
2815 add_debug_info_for_null_check_here(op->info());
2816 }
2817 // special case: address - constant
2818 LIR_Address* addr = opr1->as_address_ptr();
2819 if (c->type() == T_INT) {
2820 __ cmpl(as_Address(addr), c->as_jint());
2821 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2822 #ifdef _LP64
2823 // %%% Make this explode if addr isn't reachable until we figure out a
2824 // better strategy by giving noreg as the temp for as_Address
2825 __ cmpptr(rscratch1, as_Address(addr, noreg));
2826 #else
2827 __ cmpoop(as_Address(addr), c->as_jobject());
2828 #endif // _LP64
2829 } else {
2830 ShouldNotReachHere();
2831 }
2833 } else {
2834 ShouldNotReachHere();
2835 }
2836 }
2838 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2839 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2840 if (left->is_single_xmm()) {
2841 assert(right->is_single_xmm(), "must match");
2842 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2843 } else if (left->is_double_xmm()) {
2844 assert(right->is_double_xmm(), "must match");
2845 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2847 } else {
2848 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2849 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2851 assert(left->fpu() == 0, "left must be on TOS");
2852 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2853 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2854 }
2855 } else {
2856 assert(code == lir_cmp_l2i, "check");
2857 #ifdef _LP64
2858 Label done;
2859 Register dest = dst->as_register();
2860 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2861 __ movl(dest, -1);
2862 __ jccb(Assembler::less, done);
2863 __ set_byte_if_not_zero(dest);
2864 __ movzbl(dest, dest);
2865 __ bind(done);
2866 #else
2867 __ lcmp2int(left->as_register_hi(),
2868 left->as_register_lo(),
2869 right->as_register_hi(),
2870 right->as_register_lo());
2871 move_regs(left->as_register_hi(), dst->as_register());
2872 #endif // _LP64
2873 }
2874 }
2877 void LIR_Assembler::align_call(LIR_Code code) {
2878 if (os::is_MP()) {
2879 // make sure that the displacement word of the call ends up word aligned
2880 int offset = __ offset();
2881 switch (code) {
2882 case lir_static_call:
2883 case lir_optvirtual_call:
2884 case lir_dynamic_call:
2885 offset += NativeCall::displacement_offset;
2886 break;
2887 case lir_icvirtual_call:
2888 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2889 break;
2890 case lir_virtual_call: // currently, sparc-specific for niagara
2891 default: ShouldNotReachHere();
2892 }
2893 while (offset++ % BytesPerWord != 0) {
2894 __ nop();
2895 }
2896 }
2897 }
2900 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2901 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2902 "must be aligned");
2903 __ call(AddressLiteral(op->addr(), rtype));
2904 add_call_info(code_offset(), op->info());
2905 }
2908 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2909 __ ic_call(op->addr());
2910 add_call_info(code_offset(), op->info());
2911 assert(!os::is_MP() ||
2912 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2913 "must be aligned");
2914 }
2917 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2918 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2919 ShouldNotReachHere();
2920 }
2923 void LIR_Assembler::emit_static_call_stub() {
2924 address call_pc = __ pc();
2925 address stub = __ start_a_stub(call_stub_size);
2926 if (stub == NULL) {
2927 bailout("static call stub overflow");
2928 return;
2929 }
2931 int start = __ offset();
2932 if (os::is_MP()) {
2933 // make sure that the displacement word of the call ends up word aligned
2934 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset;
2935 while (offset++ % BytesPerWord != 0) {
2936 __ nop();
2937 }
2938 }
2939 __ relocate(static_stub_Relocation::spec(call_pc));
2940 __ mov_metadata(rbx, (Metadata*)NULL);
2941 // must be set to -1 at code generation time
2942 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2943 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2944 __ jump(RuntimeAddress(__ pc()));
2946 assert(__ offset() - start <= call_stub_size, "stub too big");
2947 __ end_a_stub();
2948 }
2951 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2952 assert(exceptionOop->as_register() == rax, "must match");
2953 assert(exceptionPC->as_register() == rdx, "must match");
2955 // exception object is not added to oop map by LinearScan
2956 // (LinearScan assumes that no oops are in fixed registers)
2957 info->add_register_oop(exceptionOop);
2958 Runtime1::StubID unwind_id;
2960 // get current pc information
2961 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2962 int pc_for_athrow_offset = __ offset();
2963 InternalAddress pc_for_athrow(__ pc());
2964 __ lea(exceptionPC->as_register(), pc_for_athrow);
2965 add_call_info(pc_for_athrow_offset, info); // for exception handler
2967 __ verify_not_null_oop(rax);
2968 // search an exception handler (rax: exception oop, rdx: throwing pc)
2969 if (compilation()->has_fpu_code()) {
2970 unwind_id = Runtime1::handle_exception_id;
2971 } else {
2972 unwind_id = Runtime1::handle_exception_nofpu_id;
2973 }
2974 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2976 // enough room for two byte trap
2977 __ nop();
2978 }
2981 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2982 assert(exceptionOop->as_register() == rax, "must match");
2984 __ jmp(_unwind_handler_entry);
2985 }
2988 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2990 // optimized version for linear scan:
2991 // * count must be already in ECX (guaranteed by LinearScan)
2992 // * left and dest must be equal
2993 // * tmp must be unused
2994 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2995 assert(left == dest, "left and dest must be equal");
2996 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2998 if (left->is_single_cpu()) {
2999 Register value = left->as_register();
3000 assert(value != SHIFT_count, "left cannot be ECX");
3002 switch (code) {
3003 case lir_shl: __ shll(value); break;
3004 case lir_shr: __ sarl(value); break;
3005 case lir_ushr: __ shrl(value); break;
3006 default: ShouldNotReachHere();
3007 }
3008 } else if (left->is_double_cpu()) {
3009 Register lo = left->as_register_lo();
3010 Register hi = left->as_register_hi();
3011 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
3012 #ifdef _LP64
3013 switch (code) {
3014 case lir_shl: __ shlptr(lo); break;
3015 case lir_shr: __ sarptr(lo); break;
3016 case lir_ushr: __ shrptr(lo); break;
3017 default: ShouldNotReachHere();
3018 }
3019 #else
3021 switch (code) {
3022 case lir_shl: __ lshl(hi, lo); break;
3023 case lir_shr: __ lshr(hi, lo, true); break;
3024 case lir_ushr: __ lshr(hi, lo, false); break;
3025 default: ShouldNotReachHere();
3026 }
3027 #endif // LP64
3028 } else {
3029 ShouldNotReachHere();
3030 }
3031 }
3034 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
3035 if (dest->is_single_cpu()) {
3036 // first move left into dest so that left is not destroyed by the shift
3037 Register value = dest->as_register();
3038 count = count & 0x1F; // Java spec
3040 move_regs(left->as_register(), value);
3041 switch (code) {
3042 case lir_shl: __ shll(value, count); break;
3043 case lir_shr: __ sarl(value, count); break;
3044 case lir_ushr: __ shrl(value, count); break;
3045 default: ShouldNotReachHere();
3046 }
3047 } else if (dest->is_double_cpu()) {
3048 #ifndef _LP64
3049 Unimplemented();
3050 #else
3051 // first move left into dest so that left is not destroyed by the shift
3052 Register value = dest->as_register_lo();
3053 count = count & 0x1F; // Java spec
3055 move_regs(left->as_register_lo(), value);
3056 switch (code) {
3057 case lir_shl: __ shlptr(value, count); break;
3058 case lir_shr: __ sarptr(value, count); break;
3059 case lir_ushr: __ shrptr(value, count); break;
3060 default: ShouldNotReachHere();
3061 }
3062 #endif // _LP64
3063 } else {
3064 ShouldNotReachHere();
3065 }
3066 }
3069 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3070 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3071 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3072 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3073 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3074 }
3077 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3078 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3079 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3080 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3081 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3082 }
3085 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3086 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3087 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3088 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3089 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3090 }
3093 // This code replaces a call to arraycopy; no exception may
3094 // be thrown in this code, they must be thrown in the System.arraycopy
3095 // activation frame; we could save some checks if this would not be the case
3096 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3097 ciArrayKlass* default_type = op->expected_type();
3098 Register src = op->src()->as_register();
3099 Register dst = op->dst()->as_register();
3100 Register src_pos = op->src_pos()->as_register();
3101 Register dst_pos = op->dst_pos()->as_register();
3102 Register length = op->length()->as_register();
3103 Register tmp = op->tmp()->as_register();
3105 CodeStub* stub = op->stub();
3106 int flags = op->flags();
3107 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3108 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3110 // if we don't know anything, just go through the generic arraycopy
3111 if (default_type == NULL) {
3112 Label done;
3113 // save outgoing arguments on stack in case call to System.arraycopy is needed
3114 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3115 // for interpreter calling conventions. Now we have to do it in new style conventions.
3116 // For the moment until C1 gets the new register allocator I just force all the
3117 // args to the right place (except the register args) and then on the back side
3118 // reload the register args properly if we go slow path. Yuck
3120 // These are proper for the calling convention
3121 store_parameter(length, 2);
3122 store_parameter(dst_pos, 1);
3123 store_parameter(dst, 0);
3125 // these are just temporary placements until we need to reload
3126 store_parameter(src_pos, 3);
3127 store_parameter(src, 4);
3128 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3130 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
3132 address copyfunc_addr = StubRoutines::generic_arraycopy();
3134 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3135 #ifdef _LP64
3136 // The arguments are in java calling convention so we can trivially shift them to C
3137 // convention
3138 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3139 __ mov(c_rarg0, j_rarg0);
3140 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3141 __ mov(c_rarg1, j_rarg1);
3142 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3143 __ mov(c_rarg2, j_rarg2);
3144 assert_different_registers(c_rarg3, j_rarg4);
3145 __ mov(c_rarg3, j_rarg3);
3146 #ifdef _WIN64
3147 // Allocate abi space for args but be sure to keep stack aligned
3148 __ subptr(rsp, 6*wordSize);
3149 store_parameter(j_rarg4, 4);
3150 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3151 __ call(RuntimeAddress(C_entry));
3152 } else {
3153 #ifndef PRODUCT
3154 if (PrintC1Statistics) {
3155 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3156 }
3157 #endif
3158 __ call(RuntimeAddress(copyfunc_addr));
3159 }
3160 __ addptr(rsp, 6*wordSize);
3161 #else
3162 __ mov(c_rarg4, j_rarg4);
3163 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3164 __ call(RuntimeAddress(C_entry));
3165 } else {
3166 #ifndef PRODUCT
3167 if (PrintC1Statistics) {
3168 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3169 }
3170 #endif
3171 __ call(RuntimeAddress(copyfunc_addr));
3172 }
3173 #endif // _WIN64
3174 #else
3175 __ push(length);
3176 __ push(dst_pos);
3177 __ push(dst);
3178 __ push(src_pos);
3179 __ push(src);
3181 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3182 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack
3183 } else {
3184 #ifndef PRODUCT
3185 if (PrintC1Statistics) {
3186 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3187 }
3188 #endif
3189 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3190 }
3192 #endif // _LP64
3194 __ cmpl(rax, 0);
3195 __ jcc(Assembler::equal, *stub->continuation());
3197 if (copyfunc_addr != NULL) {
3198 __ mov(tmp, rax);
3199 __ xorl(tmp, -1);
3200 }
3202 // Reload values from the stack so they are where the stub
3203 // expects them.
3204 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3205 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3206 __ movptr (length, Address(rsp, 2*BytesPerWord));
3207 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3208 __ movptr (src, Address(rsp, 4*BytesPerWord));
3210 if (copyfunc_addr != NULL) {
3211 __ subl(length, tmp);
3212 __ addl(src_pos, tmp);
3213 __ addl(dst_pos, tmp);
3214 }
3215 __ jmp(*stub->entry());
3217 __ bind(*stub->continuation());
3218 return;
3219 }
3221 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3223 int elem_size = type2aelembytes(basic_type);
3224 int shift_amount;
3225 Address::ScaleFactor scale;
3227 switch (elem_size) {
3228 case 1 :
3229 shift_amount = 0;
3230 scale = Address::times_1;
3231 break;
3232 case 2 :
3233 shift_amount = 1;
3234 scale = Address::times_2;
3235 break;
3236 case 4 :
3237 shift_amount = 2;
3238 scale = Address::times_4;
3239 break;
3240 case 8 :
3241 shift_amount = 3;
3242 scale = Address::times_8;
3243 break;
3244 default:
3245 ShouldNotReachHere();
3246 }
3248 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3249 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3250 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3251 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3253 // length and pos's are all sign extended at this point on 64bit
3255 // test for NULL
3256 if (flags & LIR_OpArrayCopy::src_null_check) {
3257 __ testptr(src, src);
3258 __ jcc(Assembler::zero, *stub->entry());
3259 }
3260 if (flags & LIR_OpArrayCopy::dst_null_check) {
3261 __ testptr(dst, dst);
3262 __ jcc(Assembler::zero, *stub->entry());
3263 }
3265 // check if negative
3266 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3267 __ testl(src_pos, src_pos);
3268 __ jcc(Assembler::less, *stub->entry());
3269 }
3270 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3271 __ testl(dst_pos, dst_pos);
3272 __ jcc(Assembler::less, *stub->entry());
3273 }
3275 if (flags & LIR_OpArrayCopy::src_range_check) {
3276 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3277 __ cmpl(tmp, src_length_addr);
3278 __ jcc(Assembler::above, *stub->entry());
3279 }
3280 if (flags & LIR_OpArrayCopy::dst_range_check) {
3281 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3282 __ cmpl(tmp, dst_length_addr);
3283 __ jcc(Assembler::above, *stub->entry());
3284 }
3286 if (flags & LIR_OpArrayCopy::length_positive_check) {
3287 __ testl(length, length);
3288 __ jcc(Assembler::less, *stub->entry());
3289 __ jcc(Assembler::zero, *stub->continuation());
3290 }
3292 #ifdef _LP64
3293 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3294 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3295 #endif
3297 if (flags & LIR_OpArrayCopy::type_check) {
3298 // We don't know the array types are compatible
3299 if (basic_type != T_OBJECT) {
3300 // Simple test for basic type arrays
3301 if (UseCompressedClassPointers) {
3302 __ movl(tmp, src_klass_addr);
3303 __ cmpl(tmp, dst_klass_addr);
3304 } else {
3305 __ movptr(tmp, src_klass_addr);
3306 __ cmpptr(tmp, dst_klass_addr);
3307 }
3308 __ jcc(Assembler::notEqual, *stub->entry());
3309 } else {
3310 // For object arrays, if src is a sub class of dst then we can
3311 // safely do the copy.
3312 Label cont, slow;
3314 __ push(src);
3315 __ push(dst);
3317 __ load_klass(src, src);
3318 __ load_klass(dst, dst);
3320 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3322 __ push(src);
3323 __ push(dst);
3324 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3325 __ pop(dst);
3326 __ pop(src);
3328 __ cmpl(src, 0);
3329 __ jcc(Assembler::notEqual, cont);
3331 __ bind(slow);
3332 __ pop(dst);
3333 __ pop(src);
3335 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3336 if (copyfunc_addr != NULL) { // use stub if available
3337 // src is not a sub class of dst so we have to do a
3338 // per-element check.
3340 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3341 if ((flags & mask) != mask) {
3342 // Check that at least both of them object arrays.
3343 assert(flags & mask, "one of the two should be known to be an object array");
3345 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3346 __ load_klass(tmp, src);
3347 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3348 __ load_klass(tmp, dst);
3349 }
3350 int lh_offset = in_bytes(Klass::layout_helper_offset());
3351 Address klass_lh_addr(tmp, lh_offset);
3352 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3353 __ cmpl(klass_lh_addr, objArray_lh);
3354 __ jcc(Assembler::notEqual, *stub->entry());
3355 }
3357 // Spill because stubs can use any register they like and it's
3358 // easier to restore just those that we care about.
3359 store_parameter(dst, 0);
3360 store_parameter(dst_pos, 1);
3361 store_parameter(length, 2);
3362 store_parameter(src_pos, 3);
3363 store_parameter(src, 4);
3365 #ifndef _LP64
3366 __ movptr(tmp, dst_klass_addr);
3367 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3368 __ push(tmp);
3369 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3370 __ push(tmp);
3371 __ push(length);
3372 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3373 __ push(tmp);
3374 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3375 __ push(tmp);
3377 __ call_VM_leaf(copyfunc_addr, 5);
3378 #else
3379 __ movl2ptr(length, length); //higher 32bits must be null
3381 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3382 assert_different_registers(c_rarg0, dst, dst_pos, length);
3383 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3384 assert_different_registers(c_rarg1, dst, length);
3386 __ mov(c_rarg2, length);
3387 assert_different_registers(c_rarg2, dst);
3389 #ifdef _WIN64
3390 // Allocate abi space for args but be sure to keep stack aligned
3391 __ subptr(rsp, 6*wordSize);
3392 __ load_klass(c_rarg3, dst);
3393 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3394 store_parameter(c_rarg3, 4);
3395 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3396 __ call(RuntimeAddress(copyfunc_addr));
3397 __ addptr(rsp, 6*wordSize);
3398 #else
3399 __ load_klass(c_rarg4, dst);
3400 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3401 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3402 __ call(RuntimeAddress(copyfunc_addr));
3403 #endif
3405 #endif
3407 #ifndef PRODUCT
3408 if (PrintC1Statistics) {
3409 Label failed;
3410 __ testl(rax, rax);
3411 __ jcc(Assembler::notZero, failed);
3412 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3413 __ bind(failed);
3414 }
3415 #endif
3417 __ testl(rax, rax);
3418 __ jcc(Assembler::zero, *stub->continuation());
3420 #ifndef PRODUCT
3421 if (PrintC1Statistics) {
3422 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3423 }
3424 #endif
3426 __ mov(tmp, rax);
3428 __ xorl(tmp, -1);
3430 // Restore previously spilled arguments
3431 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3432 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3433 __ movptr (length, Address(rsp, 2*BytesPerWord));
3434 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3435 __ movptr (src, Address(rsp, 4*BytesPerWord));
3438 __ subl(length, tmp);
3439 __ addl(src_pos, tmp);
3440 __ addl(dst_pos, tmp);
3441 }
3443 __ jmp(*stub->entry());
3445 __ bind(cont);
3446 __ pop(dst);
3447 __ pop(src);
3448 }
3449 }
3451 #ifdef ASSERT
3452 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3453 // Sanity check the known type with the incoming class. For the
3454 // primitive case the types must match exactly with src.klass and
3455 // dst.klass each exactly matching the default type. For the
3456 // object array case, if no type check is needed then either the
3457 // dst type is exactly the expected type and the src type is a
3458 // subtype which we can't check or src is the same array as dst
3459 // but not necessarily exactly of type default_type.
3460 Label known_ok, halt;
3461 __ mov_metadata(tmp, default_type->constant_encoding());
3462 #ifdef _LP64
3463 if (UseCompressedClassPointers) {
3464 __ encode_klass_not_null(tmp);
3465 }
3466 #endif
3468 if (basic_type != T_OBJECT) {
3470 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3471 else __ cmpptr(tmp, dst_klass_addr);
3472 __ jcc(Assembler::notEqual, halt);
3473 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3474 else __ cmpptr(tmp, src_klass_addr);
3475 __ jcc(Assembler::equal, known_ok);
3476 } else {
3477 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3478 else __ cmpptr(tmp, dst_klass_addr);
3479 __ jcc(Assembler::equal, known_ok);
3480 __ cmpptr(src, dst);
3481 __ jcc(Assembler::equal, known_ok);
3482 }
3483 __ bind(halt);
3484 __ stop("incorrect type information in arraycopy");
3485 __ bind(known_ok);
3486 }
3487 #endif
3489 #ifndef PRODUCT
3490 if (PrintC1Statistics) {
3491 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3492 }
3493 #endif
3495 #ifdef _LP64
3496 assert_different_registers(c_rarg0, dst, dst_pos, length);
3497 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3498 assert_different_registers(c_rarg1, length);
3499 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3500 __ mov(c_rarg2, length);
3502 #else
3503 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3504 store_parameter(tmp, 0);
3505 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3506 store_parameter(tmp, 1);
3507 store_parameter(length, 2);
3508 #endif // _LP64
3510 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3511 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3512 const char *name;
3513 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3514 __ call_VM_leaf(entry, 0);
3516 __ bind(*stub->continuation());
3517 }
3519 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3520 assert(op->crc()->is_single_cpu(), "crc must be register");
3521 assert(op->val()->is_single_cpu(), "byte value must be register");
3522 assert(op->result_opr()->is_single_cpu(), "result must be register");
3523 Register crc = op->crc()->as_register();
3524 Register val = op->val()->as_register();
3525 Register res = op->result_opr()->as_register();
3527 assert_different_registers(val, crc, res);
3529 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3530 __ notl(crc); // ~crc
3531 __ update_byte_crc32(crc, val, res);
3532 __ notl(crc); // ~crc
3533 __ mov(res, crc);
3534 }
3536 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3537 Register obj = op->obj_opr()->as_register(); // may not be an oop
3538 Register hdr = op->hdr_opr()->as_register();
3539 Register lock = op->lock_opr()->as_register();
3540 if (!UseFastLocking) {
3541 __ jmp(*op->stub()->entry());
3542 } else if (op->code() == lir_lock) {
3543 Register scratch = noreg;
3544 if (UseBiasedLocking) {
3545 scratch = op->scratch_opr()->as_register();
3546 }
3547 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3548 // add debug info for NullPointerException only if one is possible
3549 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3550 if (op->info() != NULL) {
3551 add_debug_info_for_null_check(null_check_offset, op->info());
3552 }
3553 // done
3554 } else if (op->code() == lir_unlock) {
3555 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3556 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3557 } else {
3558 Unimplemented();
3559 }
3560 __ bind(*op->stub()->continuation());
3561 }
3564 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3565 ciMethod* method = op->profiled_method();
3566 int bci = op->profiled_bci();
3567 ciMethod* callee = op->profiled_callee();
3569 // Update counter for all call types
3570 ciMethodData* md = method->method_data_or_null();
3571 assert(md != NULL, "Sanity");
3572 ciProfileData* data = md->bci_to_data(bci);
3573 assert(data->is_CounterData(), "need CounterData for calls");
3574 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3575 Register mdo = op->mdo()->as_register();
3576 __ mov_metadata(mdo, md->constant_encoding());
3577 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3578 Bytecodes::Code bc = method->java_code_at_bci(bci);
3579 const bool callee_is_static = callee->is_loaded() && callee->is_static();
3580 // Perform additional virtual call profiling for invokevirtual and
3581 // invokeinterface bytecodes
3582 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3583 !callee_is_static && // required for optimized MH invokes
3584 C1ProfileVirtualCalls) {
3585 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3586 Register recv = op->recv()->as_register();
3587 assert_different_registers(mdo, recv);
3588 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3589 ciKlass* known_klass = op->known_holder();
3590 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3591 // We know the type that will be seen at this call site; we can
3592 // statically update the MethodData* rather than needing to do
3593 // dynamic tests on the receiver type
3595 // NOTE: we should probably put a lock around this search to
3596 // avoid collisions by concurrent compilations
3597 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3598 uint i;
3599 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3600 ciKlass* receiver = vc_data->receiver(i);
3601 if (known_klass->equals(receiver)) {
3602 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3603 __ addptr(data_addr, DataLayout::counter_increment);
3604 return;
3605 }
3606 }
3608 // Receiver type not found in profile data; select an empty slot
3610 // Note that this is less efficient than it should be because it
3611 // always does a write to the receiver part of the
3612 // VirtualCallData rather than just the first time
3613 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3614 ciKlass* receiver = vc_data->receiver(i);
3615 if (receiver == NULL) {
3616 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3617 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3618 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3619 __ addptr(data_addr, DataLayout::counter_increment);
3620 return;
3621 }
3622 }
3623 } else {
3624 __ load_klass(recv, recv);
3625 Label update_done;
3626 type_profile_helper(mdo, md, data, recv, &update_done);
3627 // Receiver did not match any saved receiver and there is no empty row for it.
3628 // Increment total counter to indicate polymorphic case.
3629 __ addptr(counter_addr, DataLayout::counter_increment);
3631 __ bind(update_done);
3632 }
3633 } else {
3634 // Static call
3635 __ addptr(counter_addr, DataLayout::counter_increment);
3636 }
3637 }
3639 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3640 Register obj = op->obj()->as_register();
3641 Register tmp = op->tmp()->as_pointer_register();
3642 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3643 ciKlass* exact_klass = op->exact_klass();
3644 intptr_t current_klass = op->current_klass();
3645 bool not_null = op->not_null();
3646 bool no_conflict = op->no_conflict();
3648 Label update, next, none;
3650 bool do_null = !not_null;
3651 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3652 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3654 assert(do_null || do_update, "why are we here?");
3655 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3657 __ verify_oop(obj);
3659 if (tmp != obj) {
3660 __ mov(tmp, obj);
3661 }
3662 if (do_null) {
3663 __ testptr(tmp, tmp);
3664 __ jccb(Assembler::notZero, update);
3665 if (!TypeEntries::was_null_seen(current_klass)) {
3666 __ orptr(mdo_addr, TypeEntries::null_seen);
3667 }
3668 if (do_update) {
3669 #ifndef ASSERT
3670 __ jmpb(next);
3671 }
3672 #else
3673 __ jmp(next);
3674 }
3675 } else {
3676 __ testptr(tmp, tmp);
3677 __ jccb(Assembler::notZero, update);
3678 __ stop("unexpect null obj");
3679 #endif
3680 }
3682 __ bind(update);
3684 if (do_update) {
3685 #ifdef ASSERT
3686 if (exact_klass != NULL) {
3687 Label ok;
3688 __ load_klass(tmp, tmp);
3689 __ push(tmp);
3690 __ mov_metadata(tmp, exact_klass->constant_encoding());
3691 __ cmpptr(tmp, Address(rsp, 0));
3692 __ jccb(Assembler::equal, ok);
3693 __ stop("exact klass and actual klass differ");
3694 __ bind(ok);
3695 __ pop(tmp);
3696 }
3697 #endif
3698 if (!no_conflict) {
3699 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3700 if (exact_klass != NULL) {
3701 __ mov_metadata(tmp, exact_klass->constant_encoding());
3702 } else {
3703 __ load_klass(tmp, tmp);
3704 }
3706 __ xorptr(tmp, mdo_addr);
3707 __ testptr(tmp, TypeEntries::type_klass_mask);
3708 // klass seen before, nothing to do. The unknown bit may have been
3709 // set already but no need to check.
3710 __ jccb(Assembler::zero, next);
3712 __ testptr(tmp, TypeEntries::type_unknown);
3713 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3715 if (TypeEntries::is_type_none(current_klass)) {
3716 __ cmpptr(mdo_addr, 0);
3717 __ jccb(Assembler::equal, none);
3718 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3719 __ jccb(Assembler::equal, none);
3720 // There is a chance that the checks above (re-reading profiling
3721 // data from memory) fail if another thread has just set the
3722 // profiling to this obj's klass
3723 __ xorptr(tmp, mdo_addr);
3724 __ testptr(tmp, TypeEntries::type_klass_mask);
3725 __ jccb(Assembler::zero, next);
3726 }
3727 } else {
3728 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3729 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3731 __ movptr(tmp, mdo_addr);
3732 __ testptr(tmp, TypeEntries::type_unknown);
3733 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3734 }
3736 // different than before. Cannot keep accurate profile.
3737 __ orptr(mdo_addr, TypeEntries::type_unknown);
3739 if (TypeEntries::is_type_none(current_klass)) {
3740 __ jmpb(next);
3742 __ bind(none);
3743 // first time here. Set profile type.
3744 __ movptr(mdo_addr, tmp);
3745 }
3746 } else {
3747 // There's a single possible klass at this profile point
3748 assert(exact_klass != NULL, "should be");
3749 if (TypeEntries::is_type_none(current_klass)) {
3750 __ mov_metadata(tmp, exact_klass->constant_encoding());
3751 __ xorptr(tmp, mdo_addr);
3752 __ testptr(tmp, TypeEntries::type_klass_mask);
3753 #ifdef ASSERT
3754 __ jcc(Assembler::zero, next);
3756 {
3757 Label ok;
3758 __ push(tmp);
3759 __ cmpptr(mdo_addr, 0);
3760 __ jcc(Assembler::equal, ok);
3761 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3762 __ jcc(Assembler::equal, ok);
3763 // may have been set by another thread
3764 __ mov_metadata(tmp, exact_klass->constant_encoding());
3765 __ xorptr(tmp, mdo_addr);
3766 __ testptr(tmp, TypeEntries::type_mask);
3767 __ jcc(Assembler::zero, ok);
3769 __ stop("unexpected profiling mismatch");
3770 __ bind(ok);
3771 __ pop(tmp);
3772 }
3773 #else
3774 __ jccb(Assembler::zero, next);
3775 #endif
3776 // first time here. Set profile type.
3777 __ movptr(mdo_addr, tmp);
3778 } else {
3779 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3780 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3782 __ movptr(tmp, mdo_addr);
3783 __ testptr(tmp, TypeEntries::type_unknown);
3784 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3786 __ orptr(mdo_addr, TypeEntries::type_unknown);
3787 }
3788 }
3790 __ bind(next);
3791 }
3792 }
3794 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3795 Unimplemented();
3796 }
3799 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3800 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3801 }
3804 void LIR_Assembler::align_backward_branch_target() {
3805 __ align(BytesPerWord);
3806 }
3809 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3810 if (left->is_single_cpu()) {
3811 __ negl(left->as_register());
3812 move_regs(left->as_register(), dest->as_register());
3814 } else if (left->is_double_cpu()) {
3815 Register lo = left->as_register_lo();
3816 #ifdef _LP64
3817 Register dst = dest->as_register_lo();
3818 __ movptr(dst, lo);
3819 __ negptr(dst);
3820 #else
3821 Register hi = left->as_register_hi();
3822 __ lneg(hi, lo);
3823 if (dest->as_register_lo() == hi) {
3824 assert(dest->as_register_hi() != lo, "destroying register");
3825 move_regs(hi, dest->as_register_hi());
3826 move_regs(lo, dest->as_register_lo());
3827 } else {
3828 move_regs(lo, dest->as_register_lo());
3829 move_regs(hi, dest->as_register_hi());
3830 }
3831 #endif // _LP64
3833 } else if (dest->is_single_xmm()) {
3834 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3835 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3836 }
3837 __ xorps(dest->as_xmm_float_reg(),
3838 ExternalAddress((address)float_signflip_pool));
3840 } else if (dest->is_double_xmm()) {
3841 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3842 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3843 }
3844 __ xorpd(dest->as_xmm_double_reg(),
3845 ExternalAddress((address)double_signflip_pool));
3847 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3848 assert(left->fpu() == 0, "arg must be on TOS");
3849 assert(dest->fpu() == 0, "dest must be TOS");
3850 __ fchs();
3852 } else {
3853 ShouldNotReachHere();
3854 }
3855 }
3858 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3859 assert(addr->is_address() && dest->is_register(), "check");
3860 Register reg;
3861 reg = dest->as_pointer_register();
3862 __ lea(reg, as_Address(addr->as_address_ptr()));
3863 }
3867 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3868 assert(!tmp->is_valid(), "don't need temporary");
3869 __ call(RuntimeAddress(dest));
3870 if (info != NULL) {
3871 add_call_info_here(info);
3872 }
3873 }
3876 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3877 assert(type == T_LONG, "only for volatile long fields");
3879 if (info != NULL) {
3880 add_debug_info_for_null_check_here(info);
3881 }
3883 if (src->is_double_xmm()) {
3884 if (dest->is_double_cpu()) {
3885 #ifdef _LP64
3886 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3887 #else
3888 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3889 __ psrlq(src->as_xmm_double_reg(), 32);
3890 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3891 #endif // _LP64
3892 } else if (dest->is_double_stack()) {
3893 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3894 } else if (dest->is_address()) {
3895 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3896 } else {
3897 ShouldNotReachHere();
3898 }
3900 } else if (dest->is_double_xmm()) {
3901 if (src->is_double_stack()) {
3902 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3903 } else if (src->is_address()) {
3904 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3905 } else {
3906 ShouldNotReachHere();
3907 }
3909 } else if (src->is_double_fpu()) {
3910 assert(src->fpu_regnrLo() == 0, "must be TOS");
3911 if (dest->is_double_stack()) {
3912 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3913 } else if (dest->is_address()) {
3914 __ fistp_d(as_Address(dest->as_address_ptr()));
3915 } else {
3916 ShouldNotReachHere();
3917 }
3919 } else if (dest->is_double_fpu()) {
3920 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3921 if (src->is_double_stack()) {
3922 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3923 } else if (src->is_address()) {
3924 __ fild_d(as_Address(src->as_address_ptr()));
3925 } else {
3926 ShouldNotReachHere();
3927 }
3928 } else {
3929 ShouldNotReachHere();
3930 }
3931 }
3933 #ifdef ASSERT
3934 // emit run-time assertion
3935 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3936 assert(op->code() == lir_assert, "must be");
3938 if (op->in_opr1()->is_valid()) {
3939 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3940 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3941 } else {
3942 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3943 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3944 }
3946 Label ok;
3947 if (op->condition() != lir_cond_always) {
3948 Assembler::Condition acond = Assembler::zero;
3949 switch (op->condition()) {
3950 case lir_cond_equal: acond = Assembler::equal; break;
3951 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3952 case lir_cond_less: acond = Assembler::less; break;
3953 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3954 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3955 case lir_cond_greater: acond = Assembler::greater; break;
3956 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3957 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3958 default: ShouldNotReachHere();
3959 }
3960 __ jcc(acond, ok);
3961 }
3962 if (op->halt()) {
3963 const char* str = __ code_string(op->msg());
3964 __ stop(str);
3965 } else {
3966 breakpoint();
3967 }
3968 __ bind(ok);
3969 }
3970 #endif
3972 void LIR_Assembler::membar() {
3973 // QQQ sparc TSO uses this,
3974 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3975 }
3977 void LIR_Assembler::membar_acquire() {
3978 // No x86 machines currently require load fences
3979 // __ load_fence();
3980 }
3982 void LIR_Assembler::membar_release() {
3983 // No x86 machines currently require store fences
3984 // __ store_fence();
3985 }
3987 void LIR_Assembler::membar_loadload() {
3988 // no-op
3989 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3990 }
3992 void LIR_Assembler::membar_storestore() {
3993 // no-op
3994 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3995 }
3997 void LIR_Assembler::membar_loadstore() {
3998 // no-op
3999 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
4000 }
4002 void LIR_Assembler::membar_storeload() {
4003 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4004 }
4006 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4007 assert(result_reg->is_register(), "check");
4008 #ifdef _LP64
4009 // __ get_thread(result_reg->as_register_lo());
4010 __ mov(result_reg->as_register(), r15_thread);
4011 #else
4012 __ get_thread(result_reg->as_register());
4013 #endif // _LP64
4014 }
4017 void LIR_Assembler::peephole(LIR_List*) {
4018 // do nothing for now
4019 }
4021 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4022 assert(data == dest, "xchg/xadd uses only 2 operands");
4024 if (data->type() == T_INT) {
4025 if (code == lir_xadd) {
4026 if (os::is_MP()) {
4027 __ lock();
4028 }
4029 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4030 } else {
4031 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4032 }
4033 } else if (data->is_oop()) {
4034 assert (code == lir_xchg, "xadd for oops");
4035 Register obj = data->as_register();
4036 #ifdef _LP64
4037 if (UseCompressedOops) {
4038 __ encode_heap_oop(obj);
4039 __ xchgl(obj, as_Address(src->as_address_ptr()));
4040 __ decode_heap_oop(obj);
4041 } else {
4042 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4043 }
4044 #else
4045 __ xchgl(obj, as_Address(src->as_address_ptr()));
4046 #endif
4047 } else if (data->type() == T_LONG) {
4048 #ifdef _LP64
4049 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4050 if (code == lir_xadd) {
4051 if (os::is_MP()) {
4052 __ lock();
4053 }
4054 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4055 } else {
4056 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4057 }
4058 #else
4059 ShouldNotReachHere();
4060 #endif
4061 } else {
4062 ShouldNotReachHere();
4063 }
4064 }
4066 #undef __
