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src/cpu/sparc/vm/assembler_sparc.inline.hpp@2338d41fbd81

src/cpu/sparc/vm/assembler_sparc.inline.hpp

Fri, 30 Apr 2010 08:37:24 -0700

author
twisti
date
Fri, 30 Apr 2010 08:37:24 -0700
changeset 1861
2338d41fbd81
parent 1858
c640000b7cc1
child 1902
fb1a39993f69
permissions
-rw-r--r--

6943304: remove tagged stack interpreter
Reviewed-by: coleenp, never, gbenson

     1 /*

     2  * Copyright 1997-2009 Sun Microsystems, Inc.  All Rights Reserved.

     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

     4  *

     5  * This code is free software; you can redistribute it and/or modify it

     6  * under the terms of the GNU General Public License version 2 only, as

     7  * published by the Free Software Foundation.

     8  *

     9  * This code is distributed in the hope that it will be useful, but WITHOUT

    10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

    12  * version 2 for more details (a copy is included in the LICENSE file that

    13  * accompanied this code).

    14  *

    15  * You should have received a copy of the GNU General Public License version

    16  * 2 along with this work; if not, write to the Free Software Foundation,

    17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

    18  *

    19  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,

    20  * CA 95054 USA or visit www.sun.com if you need additional information or

    21  * have any questions.

    22  *

    23  */

    24 

    25 inline void MacroAssembler::pd_patch_instruction(address branch, address target) {

    26   jint& stub_inst = *(jint*) branch;

    27   stub_inst = patched_branch(target - branch, stub_inst, 0);

    28 }

    29 

    30 #ifndef PRODUCT

    31 inline void MacroAssembler::pd_print_patched_instruction(address branch) {

    32   jint stub_inst = *(jint*) branch;

    33   print_instruction(stub_inst);

    34   ::tty->print("%s", " (unresolved)");

    35 }

    36 #endif // PRODUCT

    37 

    38 inline bool Address::is_simm13(int offset) { return Assembler::is_simm13(disp() + offset); }

    39 

    40 

    41 inline int AddressLiteral::low10() const {

    42   return Assembler::low10(value());

    43 }

    44 

    45 

    46 // inlines for SPARC assembler -- dmu 5/97

    47 

    48 inline void Assembler::check_delay() {

    49 # ifdef CHECK_DELAY

    50   guarantee( delay_state != at_delay_slot, "must say delayed() when filling delay slot");

    51   delay_state = no_delay;

    52 # endif

    53 }

    54 

    55 inline void Assembler::emit_long(int x) {

    56   check_delay();

    57   AbstractAssembler::emit_long(x);

    58 }

    59 

    60 inline void Assembler::emit_data(int x, relocInfo::relocType rtype) {

    61   relocate(rtype);

    62   emit_long(x);

    63 }

    64 

    65 inline void Assembler::emit_data(int x, RelocationHolder const& rspec) {

    66   relocate(rspec);

    67   emit_long(x);

    68 }

    69 

    70 

    71 inline void Assembler::add(Register s1, Register s2, Register d )                             { emit_long( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2) ); }

    72 inline void Assembler::add(Register s1, int simm13a, Register d, relocInfo::relocType rtype ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rtype ); }

    73 inline void Assembler::add(Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec ); }

    74 

    75 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt ) { v9_only();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt);  has_delay_slot(); }

    76 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, Label& L) { bpr( c, a, p, s1, target(L)); }

    77 

    78 inline void Assembler::fb( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);  has_delay_slot(); }

    79 inline void Assembler::fb( Condition c, bool a, Label& L ) { fb(c, a, target(L)); }

    80 

    81 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt);  has_delay_slot(); }

    82 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) { fbp(c, a, cc, p, target(L)); }

    83 

    84 inline void Assembler::cb( Condition c, bool a, address d, relocInfo::relocType rt ) { v8_only();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(cb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);  has_delay_slot(); }

    85 inline void Assembler::cb( Condition c, bool a, Label& L ) { cb(c, a, target(L)); }

    86 

    87 inline void Assembler::br( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep();   emit_data( op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);  has_delay_slot(); }

    88 inline void Assembler::br( Condition c, bool a, Label& L ) { br(c, a, target(L)); }

    89 

    90 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt);  has_delay_slot(); }

    91 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) { bp(c, a, cc, p, target(L)); }

    92 

    93 inline void Assembler::call( address d,  relocInfo::relocType rt ) { emit_data( op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt);  has_delay_slot(); assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); }

    94 inline void Assembler::call( Label& L,   relocInfo::relocType rt ) { call( target(L), rt); }

    95 

    96 inline void Assembler::flush( Register s1, Register s2) { emit_long( op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2)); }

    97 inline void Assembler::flush( Register s1, int simm13a) { emit_data( op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

    98 

    99 inline void Assembler::jmpl( Register s1, Register s2, Register d                          ) { emit_long( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2));  has_delay_slot(); }

   100 inline void Assembler::jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec);  has_delay_slot(); }

   101 

   102 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d) {

   103   if (s2.is_register()) ldf(w, s1, s2.as_register(), d);

   104   else                  ldf(w, s1, s2.as_constant(), d);

   105 }

   106 

   107 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2) ); }

   108 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); }

   109 

   110 inline void Assembler::ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset) { relocate(a.rspec(offset)); ldf( w, a.base(), a.disp() + offset, d); }

   111 

   112 inline void Assembler::ldfsr(  Register s1, Register s2) { v9_dep();   emit_long( op(ldst_op) |             op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }

   113 inline void Assembler::ldfsr(  Register s1, int simm13a) { v9_dep();   emit_data( op(ldst_op) |             op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   114 inline void Assembler::ldxfsr( Register s1, Register s2) { v9_only();  emit_long( op(ldst_op) | rd(G1)    | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }

   115 inline void Assembler::ldxfsr( Register s1, int simm13a) { v9_only();  emit_data( op(ldst_op) | rd(G1)    | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   116 

   117 inline void Assembler::ldc(   Register s1, Register s2, int crd) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(ldc_op3  ) | rs1(s1) | rs2(s2) ); }

   118 inline void Assembler::ldc(   Register s1, int simm13a, int crd) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(ldc_op3  ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   119 inline void Assembler::lddc(  Register s1, Register s2, int crd) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | rs2(s2) ); }

   120 inline void Assembler::lddc(  Register s1, int simm13a, int crd) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   121 inline void Assembler::ldcsr( Register s1, Register s2, int crd) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | rs2(s2) ); }

   122 inline void Assembler::ldcsr( Register s1, int simm13a, int crd) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   123 

   124 inline void Assembler::ldsb(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | rs2(s2) ); }

   125 inline void Assembler::ldsb(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   126 

   127 inline void Assembler::ldsh(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | rs2(s2) ); }

   128 inline void Assembler::ldsh(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   129 inline void Assembler::ldsw(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | rs2(s2) ); }

   130 inline void Assembler::ldsw(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   131 inline void Assembler::ldub(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | rs2(s2) ); }

   132 inline void Assembler::ldub(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   133 inline void Assembler::lduh(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | rs2(s2) ); }

   134 inline void Assembler::lduh(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   135 inline void Assembler::lduw(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | rs2(s2) ); }

   136 inline void Assembler::lduw(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   137 

   138 inline void Assembler::ldx(   Register s1, Register s2, Register d) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | rs2(s2) ); }

   139 inline void Assembler::ldx(   Register s1, int simm13a, Register d) { v9_only();  emit_data( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   140 inline void Assembler::ldd(   Register s1, Register s2, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | rs2(s2) ); }

   141 inline void Assembler::ldd(   Register s1, int simm13a, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   142 

   143 #ifdef _LP64

   144 // Make all 32 bit loads signed so 64 bit registers maintain proper sign

   145 inline void Assembler::ld(  Register s1, Register s2, Register d)      { ldsw( s1, s2, d); }

   146 inline void Assembler::ld(  Register s1, int simm13a, Register d)      { ldsw( s1, simm13a, d); }

   147 #else

   148 inline void Assembler::ld(  Register s1, Register s2, Register d)      { lduw( s1, s2, d); }

   149 inline void Assembler::ld(  Register s1, int simm13a, Register d)      { lduw( s1, simm13a, d); }

   150 #endif

   151 

   152 #ifdef ASSERT

   153   // ByteSize is only a class when ASSERT is defined, otherwise it's an int.

   154 # ifdef _LP64

   155 inline void Assembler::ld(  Register s1, ByteSize simm13a, Register d) { ldsw( s1, in_bytes(simm13a), d); }

   156 # else

   157 inline void Assembler::ld(  Register s1, ByteSize simm13a, Register d) { lduw( s1, in_bytes(simm13a), d); }

   158 # endif

   159 #endif

   160 

   161 inline void Assembler::ld(  const Address& a, Register d, int offset) {

   162   if (a.has_index()) { assert(offset == 0, ""); ld(  a.base(), a.index(),         d); }

   163   else               {                          ld(  a.base(), a.disp() + offset, d); }

   164 }

   165 inline void Assembler::ldsb(const Address& a, Register d, int offset) {

   166   if (a.has_index()) { assert(offset == 0, ""); ldsb(a.base(), a.index(),         d); }

   167   else               {                          ldsb(a.base(), a.disp() + offset, d); }

   168 }

   169 inline void Assembler::ldsh(const Address& a, Register d, int offset) {

   170   if (a.has_index()) { assert(offset == 0, ""); ldsh(a.base(), a.index(),         d); }

   171   else               {                          ldsh(a.base(), a.disp() + offset, d); }

   172 }

   173 inline void Assembler::ldsw(const Address& a, Register d, int offset) {

   174   if (a.has_index()) { assert(offset == 0, ""); ldsw(a.base(), a.index(),         d); }

   175   else               {                          ldsw(a.base(), a.disp() + offset, d); }

   176 }

   177 inline void Assembler::ldub(const Address& a, Register d, int offset) {

   178   if (a.has_index()) { assert(offset == 0, ""); ldub(a.base(), a.index(),         d); }

   179   else               {                          ldub(a.base(), a.disp() + offset, d); }

   180 }

   181 inline void Assembler::lduh(const Address& a, Register d, int offset) {

   182   if (a.has_index()) { assert(offset == 0, ""); lduh(a.base(), a.index(),         d); }

   183   else               {                          lduh(a.base(), a.disp() + offset, d); }

   184 }

   185 inline void Assembler::lduw(const Address& a, Register d, int offset) {

   186   if (a.has_index()) { assert(offset == 0, ""); lduw(a.base(), a.index(),         d); }

   187   else               {                          lduw(a.base(), a.disp() + offset, d); }

   188 }

   189 inline void Assembler::ldd( const Address& a, Register d, int offset) {

   190   if (a.has_index()) { assert(offset == 0, ""); ldd( a.base(), a.index(),         d); }

   191   else               {                          ldd( a.base(), a.disp() + offset, d); }

   192 }

   193 inline void Assembler::ldx( const Address& a, Register d, int offset) {

   194   if (a.has_index()) { assert(offset == 0, ""); ldx( a.base(), a.index(),         d); }

   195   else               {                          ldx( a.base(), a.disp() + offset, d); }

   196 }

   197 

   198 inline void Assembler::ldub(Register s1, RegisterOrConstant s2, Register d) { ldub(Address(s1, s2), d); }

   199 inline void Assembler::ldsb(Register s1, RegisterOrConstant s2, Register d) { ldsb(Address(s1, s2), d); }

   200 inline void Assembler::lduh(Register s1, RegisterOrConstant s2, Register d) { lduh(Address(s1, s2), d); }

   201 inline void Assembler::ldsh(Register s1, RegisterOrConstant s2, Register d) { ldsh(Address(s1, s2), d); }

   202 inline void Assembler::lduw(Register s1, RegisterOrConstant s2, Register d) { lduw(Address(s1, s2), d); }

   203 inline void Assembler::ldsw(Register s1, RegisterOrConstant s2, Register d) { ldsw(Address(s1, s2), d); }

   204 inline void Assembler::ldx( Register s1, RegisterOrConstant s2, Register d) { ldx( Address(s1, s2), d); }

   205 inline void Assembler::ld(  Register s1, RegisterOrConstant s2, Register d) { ld(  Address(s1, s2), d); }

   206 inline void Assembler::ldd( Register s1, RegisterOrConstant s2, Register d) { ldd( Address(s1, s2), d); }

   207 

   208 // form effective addresses this way:

   209 inline void Assembler::add(Register s1, RegisterOrConstant s2, Register d, int offset) {

   210   if (s2.is_register())  add(s1, s2.as_register(),          d);

   211   else                 { add(s1, s2.as_constant() + offset, d); offset = 0; }

   212   if (offset != 0)       add(d,  offset,                    d);

   213 }

   214 

   215 inline void Assembler::andn(Register s1, RegisterOrConstant s2, Register d) {

   216   if (s2.is_register())  andn(s1, s2.as_register(), d);

   217   else                   andn(s1, s2.as_constant(), d);

   218 }

   219 

   220 inline void Assembler::ldstub(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | rs2(s2) ); }

   221 inline void Assembler::ldstub(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   222 

   223 

   224 inline void Assembler::prefetch(Register s1, Register s2, PrefetchFcn f) { v9_only();  emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }

   225 inline void Assembler::prefetch(Register s1, int simm13a, PrefetchFcn f) { v9_only();  emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   226 

   227 inline void Assembler::prefetch(const Address& a, PrefetchFcn f, int offset) { v9_only(); relocate(a.rspec(offset)); prefetch(a.base(), a.disp() + offset, f); }

   228 

   229 

   230 inline void Assembler::rett( Register s1, Register s2                         ) { emit_long( op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2));  has_delay_slot(); }

   231 inline void Assembler::rett( Register s1, int simm13a, relocInfo::relocType rt) { emit_data( op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt);  has_delay_slot(); }

   232 

   233 inline void Assembler::sethi( int imm22a, Register d, RelocationHolder const& rspec ) { emit_data( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(imm22a), rspec); }

   234 

   235   // pp 222

   236 

   237 inline void Assembler::stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2) {

   238   if (s2.is_register()) stf(w, d, s1, s2.as_register());

   239   else                  stf(w, d, s1, s2.as_constant());

   240 }

   241 

   242 inline void Assembler::stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | rs2(s2) ); }

   243 inline void Assembler::stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   244 

   245 inline void Assembler::stf(    FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset) { relocate(a.rspec(offset)); stf(w, d, a.base(), a.disp() + offset); }

   246 

   247 inline void Assembler::stfsr(  Register s1, Register s2) { v9_dep();   emit_long( op(ldst_op) |             op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }

   248 inline void Assembler::stfsr(  Register s1, int simm13a) { v9_dep();   emit_data( op(ldst_op) |             op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   249 inline void Assembler::stxfsr( Register s1, Register s2) { v9_only();  emit_long( op(ldst_op) | rd(G1)    | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }

   250 inline void Assembler::stxfsr( Register s1, int simm13a) { v9_only();  emit_data( op(ldst_op) | rd(G1)    | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   251 

   252   // p 226

   253 

   254 inline void Assembler::stb(  Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | rs2(s2) ); }

   255 inline void Assembler::stb(  Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   256 inline void Assembler::sth(  Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | rs2(s2) ); }

   257 inline void Assembler::sth(  Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   258 inline void Assembler::stw(  Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | rs2(s2) ); }

   259 inline void Assembler::stw(  Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   260 

   261 

   262 inline void Assembler::stx(  Register d, Register s1, Register s2) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | rs2(s2) ); }

   263 inline void Assembler::stx(  Register d, Register s1, int simm13a) { v9_only();  emit_data( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   264 inline void Assembler::std(  Register d, Register s1, Register s2) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | rs2(s2) ); }

   265 inline void Assembler::std(  Register d, Register s1, int simm13a) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   266 

   267 inline void Assembler::st( Register d, Register s1, Register s2)      { stw(d, s1, s2); }

   268 inline void Assembler::st( Register d, Register s1, int simm13a)      { stw(d, s1, simm13a); }

   269 

   270 #ifdef ASSERT

   271 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.

   272 inline void Assembler::st( Register d, Register s1, ByteSize simm13a) { stw(d, s1, in_bytes(simm13a)); }

   273 #endif

   274 

   275 inline void Assembler::stb(Register d, const Address& a, int offset) {

   276   if (a.has_index()) { assert(offset == 0, ""); stb(d, a.base(), a.index()        ); }

   277   else               {                          stb(d, a.base(), a.disp() + offset); }

   278 }

   279 inline void Assembler::sth(Register d, const Address& a, int offset) {

   280   if (a.has_index()) { assert(offset == 0, ""); sth(d, a.base(), a.index()        ); }

   281   else               {                          sth(d, a.base(), a.disp() + offset); }

   282 }

   283 inline void Assembler::stw(Register d, const Address& a, int offset) {

   284   if (a.has_index()) { assert(offset == 0, ""); stw(d, a.base(), a.index()        ); }

   285   else               {                          stw(d, a.base(), a.disp() + offset); }

   286 }

   287 inline void Assembler::st( Register d, const Address& a, int offset) {

   288   if (a.has_index()) { assert(offset == 0, ""); st( d, a.base(), a.index()        ); }

   289   else               {                          st( d, a.base(), a.disp() + offset); }

   290 }

   291 inline void Assembler::std(Register d, const Address& a, int offset) {

   292   if (a.has_index()) { assert(offset == 0, ""); std(d, a.base(), a.index()        ); }

   293   else               {                          std(d, a.base(), a.disp() + offset); }

   294 }

   295 inline void Assembler::stx(Register d, const Address& a, int offset) {

   296   if (a.has_index()) { assert(offset == 0, ""); stx(d, a.base(), a.index()        ); }

   297   else               {                          stx(d, a.base(), a.disp() + offset); }

   298 }

   299 

   300 inline void Assembler::stb(Register d, Register s1, RegisterOrConstant s2) { stb(d, Address(s1, s2)); }

   301 inline void Assembler::sth(Register d, Register s1, RegisterOrConstant s2) { sth(d, Address(s1, s2)); }

   302 inline void Assembler::stw(Register d, Register s1, RegisterOrConstant s2) { stw(d, Address(s1, s2)); }

   303 inline void Assembler::stx(Register d, Register s1, RegisterOrConstant s2) { stx(d, Address(s1, s2)); }

   304 inline void Assembler::std(Register d, Register s1, RegisterOrConstant s2) { std(d, Address(s1, s2)); }

   305 inline void Assembler::st( Register d, Register s1, RegisterOrConstant s2) { st( d, Address(s1, s2)); }

   306 

   307 // v8 p 99

   308 

   309 inline void Assembler::stc(    int crd, Register s1, Register s2) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | rs2(s2) ); }

   310 inline void Assembler::stc(    int crd, Register s1, int simm13a) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   311 inline void Assembler::stdc(   int crd, Register s1, Register s2) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | rs2(s2) ); }

   312 inline void Assembler::stdc(   int crd, Register s1, int simm13a) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   313 inline void Assembler::stcsr(  int crd, Register s1, Register s2) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | rs2(s2) ); }

   314 inline void Assembler::stcsr(  int crd, Register s1, int simm13a) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   315 inline void Assembler::stdcq(  int crd, Register s1, Register s2) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | rs2(s2) ); }

   316 inline void Assembler::stdcq(  int crd, Register s1, int simm13a) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   317 

   318 

   319 // pp 231

   320 

   321 inline void Assembler::swap(    Register s1, Register s2, Register d) { v9_dep();  emit_long( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | rs2(s2) ); }

   322 inline void Assembler::swap(    Register s1, int simm13a, Register d) { v9_dep();  emit_data( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   323 

   324 inline void Assembler::swap(    Address& a, Register d, int offset ) { relocate(a.rspec(offset)); swap(  a.base(), a.disp() + offset, d ); }

   325 

   326 

   327 // Use the right loads/stores for the platform

   328 inline void MacroAssembler::ld_ptr( Register s1, Register s2, Register d ) {

   329 #ifdef _LP64

   330   Assembler::ldx(s1, s2, d);

   331 #else

   332   Assembler::ld( s1, s2, d);

   333 #endif

   334 }

   335 

   336 inline void MacroAssembler::ld_ptr( Register s1, int simm13a, Register d ) {

   337 #ifdef _LP64

   338   Assembler::ldx(s1, simm13a, d);

   339 #else

   340   Assembler::ld( s1, simm13a, d);

   341 #endif

   342 }

   343 

   344 #ifdef ASSERT

   345 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.

   346 inline void MacroAssembler::ld_ptr( Register s1, ByteSize simm13a, Register d ) {

   347   ld_ptr(s1, in_bytes(simm13a), d);

   348 }

   349 #endif

   350 

   351 inline void MacroAssembler::ld_ptr( Register s1, RegisterOrConstant s2, Register d ) {

   352 #ifdef _LP64

   353   Assembler::ldx(s1, s2, d);

   354 #else

   355   Assembler::ld( s1, s2, d);

   356 #endif

   357 }

   358 

   359 inline void MacroAssembler::ld_ptr(const Address& a, Register d, int offset) {

   360 #ifdef _LP64

   361   Assembler::ldx(a, d, offset);

   362 #else

   363   Assembler::ld( a, d, offset);

   364 #endif

   365 }

   366 

   367 inline void MacroAssembler::st_ptr( Register d, Register s1, Register s2 ) {

   368 #ifdef _LP64

   369   Assembler::stx(d, s1, s2);

   370 #else

   371   Assembler::st( d, s1, s2);

   372 #endif

   373 }

   374 

   375 inline void MacroAssembler::st_ptr( Register d, Register s1, int simm13a ) {

   376 #ifdef _LP64

   377   Assembler::stx(d, s1, simm13a);

   378 #else

   379   Assembler::st( d, s1, simm13a);

   380 #endif

   381 }

   382 

   383 #ifdef ASSERT

   384 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.

   385 inline void MacroAssembler::st_ptr( Register d, Register s1, ByteSize simm13a ) {

   386   st_ptr(d, s1, in_bytes(simm13a));

   387 }

   388 #endif

   389 

   390 inline void MacroAssembler::st_ptr( Register d, Register s1, RegisterOrConstant s2 ) {

   391 #ifdef _LP64

   392   Assembler::stx(d, s1, s2);

   393 #else

   394   Assembler::st( d, s1, s2);

   395 #endif

   396 }

   397 

   398 inline void MacroAssembler::st_ptr(Register d, const Address& a, int offset) {

   399 #ifdef _LP64

   400   Assembler::stx(d, a, offset);

   401 #else

   402   Assembler::st( d, a, offset);

   403 #endif

   404 }

   405 

   406 // Use the right loads/stores for the platform

   407 inline void MacroAssembler::ld_long( Register s1, Register s2, Register d ) {

   408 #ifdef _LP64

   409   Assembler::ldx(s1, s2, d);

   410 #else

   411   Assembler::ldd(s1, s2, d);

   412 #endif

   413 }

   414 

   415 inline void MacroAssembler::ld_long( Register s1, int simm13a, Register d ) {

   416 #ifdef _LP64

   417   Assembler::ldx(s1, simm13a, d);

   418 #else

   419   Assembler::ldd(s1, simm13a, d);

   420 #endif

   421 }

   422 

   423 inline void MacroAssembler::ld_long( Register s1, RegisterOrConstant s2, Register d ) {

   424 #ifdef _LP64

   425   Assembler::ldx(s1, s2, d);

   426 #else

   427   Assembler::ldd(s1, s2, d);

   428 #endif

   429 }

   430 

   431 inline void MacroAssembler::ld_long(const Address& a, Register d, int offset) {

   432 #ifdef _LP64

   433   Assembler::ldx(a, d, offset);

   434 #else

   435   Assembler::ldd(a, d, offset);

   436 #endif

   437 }

   438 

   439 inline void MacroAssembler::st_long( Register d, Register s1, Register s2 ) {

   440 #ifdef _LP64

   441   Assembler::stx(d, s1, s2);

   442 #else

   443   Assembler::std(d, s1, s2);

   444 #endif

   445 }

   446 

   447 inline void MacroAssembler::st_long( Register d, Register s1, int simm13a ) {

   448 #ifdef _LP64

   449   Assembler::stx(d, s1, simm13a);

   450 #else

   451   Assembler::std(d, s1, simm13a);

   452 #endif

   453 }

   454 

   455 inline void MacroAssembler::st_long( Register d, Register s1, RegisterOrConstant s2 ) {

   456 #ifdef _LP64

   457   Assembler::stx(d, s1, s2);

   458 #else

   459   Assembler::std(d, s1, s2);

   460 #endif

   461 }

   462 

   463 inline void MacroAssembler::st_long( Register d, const Address& a, int offset ) {

   464 #ifdef _LP64

   465   Assembler::stx(d, a, offset);

   466 #else

   467   Assembler::std(d, a, offset);

   468 #endif

   469 }

   470 

   471 // Functions for isolating 64 bit shifts for LP64

   472 

   473 inline void MacroAssembler::sll_ptr( Register s1, Register s2, Register d ) {

   474 #ifdef _LP64

   475   Assembler::sllx(s1, s2, d);

   476 #else

   477   Assembler::sll( s1, s2, d);

   478 #endif

   479 }

   480 

   481 inline void MacroAssembler::sll_ptr( Register s1, int imm6a,   Register d ) {

   482 #ifdef _LP64

   483   Assembler::sllx(s1, imm6a, d);

   484 #else

   485   Assembler::sll( s1, imm6a, d);

   486 #endif

   487 }

   488 

   489 inline void MacroAssembler::srl_ptr( Register s1, Register s2, Register d ) {

   490 #ifdef _LP64

   491   Assembler::srlx(s1, s2, d);

   492 #else

   493   Assembler::srl( s1, s2, d);

   494 #endif

   495 }

   496 

   497 inline void MacroAssembler::srl_ptr( Register s1, int imm6a,   Register d ) {

   498 #ifdef _LP64

   499   Assembler::srlx(s1, imm6a, d);

   500 #else

   501   Assembler::srl( s1, imm6a, d);

   502 #endif

   503 }

   504 

   505 inline void MacroAssembler::sll_ptr( Register s1, RegisterOrConstant s2, Register d ) {

   506   if (s2.is_register())  sll_ptr(s1, s2.as_register(), d);

   507   else                   sll_ptr(s1, s2.as_constant(), d);

   508 }

   509 

   510 // Use the right branch for the platform

   511 

   512 inline void MacroAssembler::br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {

   513   if (VM_Version::v9_instructions_work())

   514     Assembler::bp(c, a, icc, p, d, rt);

   515   else

   516     Assembler::br(c, a, d, rt);

   517 }

   518 

   519 inline void MacroAssembler::br( Condition c, bool a, Predict p, Label& L ) {

   520   br(c, a, p, target(L));

   521 }

   522 

   523 

   524 // Branch that tests either xcc or icc depending on the

   525 // architecture compiled (LP64 or not)

   526 inline void MacroAssembler::brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {

   527 #ifdef _LP64

   528     Assembler::bp(c, a, xcc, p, d, rt);

   529 #else

   530     MacroAssembler::br(c, a, p, d, rt);

   531 #endif

   532 }

   533 

   534 inline void MacroAssembler::brx( Condition c, bool a, Predict p, Label& L ) {

   535   brx(c, a, p, target(L));

   536 }

   537 

   538 inline void MacroAssembler::ba( bool a, Label& L ) {

   539   br(always, a, pt, L);

   540 }

   541 

   542 // Warning: V9 only functions

   543 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {

   544   Assembler::bp(c, a, cc, p, d, rt);

   545 }

   546 

   547 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) {

   548   Assembler::bp(c, a, cc, p, L);

   549 }

   550 

   551 inline void MacroAssembler::fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {

   552   if (VM_Version::v9_instructions_work())

   553     fbp(c, a, fcc0, p, d, rt);

   554   else

   555     Assembler::fb(c, a, d, rt);

   556 }

   557 

   558 inline void MacroAssembler::fb( Condition c, bool a, Predict p, Label& L ) {

   559   fb(c, a, p, target(L));

   560 }

   561 

   562 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {

   563   Assembler::fbp(c, a, cc, p, d, rt);

   564 }

   565 

   566 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) {

   567   Assembler::fbp(c, a, cc, p, L);

   568 }

   569 

   570 inline void MacroAssembler::jmp( Register s1, Register s2 ) { jmpl( s1, s2, G0 ); }

   571 inline void MacroAssembler::jmp( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, G0, rspec); }

   572 

   573 // Call with a check to see if we need to deal with the added

   574 // expense of relocation and if we overflow the displacement

   575 // of the quick call instruction./

   576 // Check to see if we have to deal with relocations

   577 inline void MacroAssembler::call( address d, relocInfo::relocType rt ) {

   578 #ifdef _LP64

   579   intptr_t disp;

   580   // NULL is ok because it will be relocated later.

   581   // Must change NULL to a reachable address in order to

   582   // pass asserts here and in wdisp.

   583   if ( d == NULL )

   584     d = pc();

   585 

   586   // Is this address within range of the call instruction?

   587   // If not, use the expensive instruction sequence

   588   disp = (intptr_t)d - (intptr_t)pc();

   589   if ( disp != (intptr_t)(int32_t)disp ) {

   590     relocate(rt);

   591     AddressLiteral dest(d);

   592     jumpl_to(dest, O7, O7);

   593   }

   594   else {

   595     Assembler::call( d, rt );

   596   }

   597 #else

   598   Assembler::call( d, rt );

   599 #endif

   600 }

   601 

   602 inline void MacroAssembler::call( Label& L,   relocInfo::relocType rt ) {

   603   MacroAssembler::call( target(L), rt);

   604 }

   605 

   606 

   607 

   608 inline void MacroAssembler::callr( Register s1, Register s2 ) { jmpl( s1, s2, O7 ); }

   609 inline void MacroAssembler::callr( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, O7, rspec); }

   610 

   611 // prefetch instruction

   612 inline void MacroAssembler::iprefetch( address d, relocInfo::relocType rt ) {

   613   if (VM_Version::v9_instructions_work())

   614     Assembler::bp( never, true, xcc, pt, d, rt );

   615 }

   616 inline void MacroAssembler::iprefetch( Label& L) { iprefetch( target(L) ); }

   617 

   618 

   619 // clobbers o7 on V8!!

   620 // returns delta from gotten pc to addr after

   621 inline int MacroAssembler::get_pc( Register d ) {

   622   int x = offset();

   623   if (VM_Version::v9_instructions_work())

   624     rdpc(d);

   625   else {

   626     Label lbl;

   627     Assembler::call(lbl, relocInfo::none);  // No relocation as this is call to pc+0x8

   628     if (d == O7)  delayed()->nop();

   629     else          delayed()->mov(O7, d);

   630     bind(lbl);

   631   }

   632   return offset() - x;

   633 }

   634 

   635 

   636 // Note:  All MacroAssembler::set_foo functions are defined out-of-line.

   637 

   638 

   639 // Loads the current PC of the following instruction as an immediate value in

   640 // 2 instructions.  All PCs in the CodeCache are within 2 Gig of each other.

   641 inline intptr_t MacroAssembler::load_pc_address( Register reg, int bytes_to_skip ) {

   642   intptr_t thepc = (intptr_t)pc() + 2*BytesPerInstWord + bytes_to_skip;

   643 #ifdef _LP64

   644   Unimplemented();

   645 #else

   646   Assembler::sethi(  thepc & ~0x3ff, reg, internal_word_Relocation::spec((address)thepc));

   647   Assembler::add(reg,thepc &  0x3ff, reg, internal_word_Relocation::spec((address)thepc));

   648 #endif

   649   return thepc;

   650 }

   651 

   652 

   653 inline void MacroAssembler::load_contents(AddressLiteral& addrlit, Register d, int offset) {

   654   assert_not_delayed();

   655   sethi(addrlit, d);

   656   ld(d, addrlit.low10() + offset, d);

   657 }

   658 

   659 

   660 inline void MacroAssembler::load_ptr_contents(AddressLiteral& addrlit, Register d, int offset) {

   661   assert_not_delayed();

   662   sethi(addrlit, d);

   663   ld_ptr(d, addrlit.low10() + offset, d);

   664 }

   665 

   666 

   667 inline void MacroAssembler::store_contents(Register s, AddressLiteral& addrlit, Register temp, int offset) {

   668   assert_not_delayed();

   669   sethi(addrlit, temp);

   670   st(s, temp, addrlit.low10() + offset);

   671 }

   672 

   673 

   674 inline void MacroAssembler::store_ptr_contents(Register s, AddressLiteral& addrlit, Register temp, int offset) {

   675   assert_not_delayed();

   676   sethi(addrlit, temp);

   677   st_ptr(s, temp, addrlit.low10() + offset);

   678 }

   679 

   680 

   681 // This code sequence is relocatable to any address, even on LP64.

   682 inline void MacroAssembler::jumpl_to(AddressLiteral& addrlit, Register temp, Register d, int offset) {

   683   assert_not_delayed();

   684   // Force fixed length sethi because NativeJump and NativeFarCall don't handle

   685   // variable length instruction streams.

   686   patchable_sethi(addrlit, temp);

   687   jmpl(temp, addrlit.low10() + offset, d);

   688 }

   689 

   690 

   691 inline void MacroAssembler::jump_to(AddressLiteral& addrlit, Register temp, int offset) {

   692   jumpl_to(addrlit, temp, G0, offset);

   693 }

   694 

   695 

   696 inline void MacroAssembler::jump_indirect_to(Address& a, Register temp,

   697                                              int ld_offset, int jmp_offset) {

   698   assert_not_delayed();

   699   //sethi(al);                   // sethi is caller responsibility for this one

   700   ld_ptr(a, temp, ld_offset);

   701   jmp(temp, jmp_offset);

   702 }

   703 

   704 

   705 inline void MacroAssembler::set_oop(jobject obj, Register d) {

   706   set_oop(allocate_oop_address(obj), d);

   707 }

   708 

   709 

   710 inline void MacroAssembler::set_oop_constant(jobject obj, Register d) {

   711   set_oop(constant_oop_address(obj), d);

   712 }

   713 

   714 

   715 inline void MacroAssembler::set_oop(AddressLiteral& obj_addr, Register d) {

   716   assert(obj_addr.rspec().type() == relocInfo::oop_type, "must be an oop reloc");

   717   set(obj_addr, d);

   718 }

   719 

   720 

   721 inline void MacroAssembler::load_argument( Argument& a, Register  d ) {

   722   if (a.is_register())

   723     mov(a.as_register(), d);

   724   else

   725     ld (a.as_address(),  d);

   726 }

   727 

   728 inline void MacroAssembler::store_argument( Register s, Argument& a ) {

   729   if (a.is_register())

   730     mov(s, a.as_register());

   731   else

   732     st_ptr (s, a.as_address());         // ABI says everything is right justified.

   733 }

   734 

   735 inline void MacroAssembler::store_ptr_argument( Register s, Argument& a ) {

   736   if (a.is_register())

   737     mov(s, a.as_register());

   738   else

   739     st_ptr (s, a.as_address());

   740 }

   741 

   742 

   743 #ifdef _LP64

   744 inline void MacroAssembler::store_float_argument( FloatRegister s, Argument& a ) {

   745   if (a.is_float_register())

   746 // V9 ABI has F1, F3, F5 are used to pass instead of O0, O1, O2

   747     fmov(FloatRegisterImpl::S, s, a.as_float_register() );

   748   else

   749     // Floats are stored in the high half of the stack entry

   750     // The low half is undefined per the ABI.

   751     stf(FloatRegisterImpl::S, s, a.as_address(), sizeof(jfloat));

   752 }

   753 

   754 inline void MacroAssembler::store_double_argument( FloatRegister s, Argument& a ) {

   755   if (a.is_float_register())

   756 // V9 ABI has D0, D2, D4 are used to pass instead of O0, O1, O2

   757     fmov(FloatRegisterImpl::D, s, a.as_double_register() );

   758   else

   759     stf(FloatRegisterImpl::D, s, a.as_address());

   760 }

   761 

   762 inline void MacroAssembler::store_long_argument( Register s, Argument& a ) {

   763   if (a.is_register())

   764     mov(s, a.as_register());

   765   else

   766     stx(s, a.as_address());

   767 }

   768 #endif

   769 

   770 inline void MacroAssembler::clrb( Register s1, Register s2) {  stb( G0, s1, s2 ); }

   771 inline void MacroAssembler::clrh( Register s1, Register s2) {  sth( G0, s1, s2 ); }

   772 inline void MacroAssembler::clr(  Register s1, Register s2) {  stw( G0, s1, s2 ); }

   773 inline void MacroAssembler::clrx( Register s1, Register s2) {  stx( G0, s1, s2 ); }

   774 

   775 inline void MacroAssembler::clrb( Register s1, int simm13a) { stb( G0, s1, simm13a); }

   776 inline void MacroAssembler::clrh( Register s1, int simm13a) { sth( G0, s1, simm13a); }

   777 inline void MacroAssembler::clr(  Register s1, int simm13a) { stw( G0, s1, simm13a); }

   778 inline void MacroAssembler::clrx( Register s1, int simm13a) { stx( G0, s1, simm13a); }

   779 

   780 // returns if membar generates anything, obviously this code should mirror

   781 // membar below.

   782 inline bool MacroAssembler::membar_has_effect( Membar_mask_bits const7a ) {

   783   if( !os::is_MP() ) return false;  // Not needed on single CPU

   784   if( VM_Version::v9_instructions_work() ) {

   785     const Membar_mask_bits effective_mask =

   786         Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));

   787     return (effective_mask != 0);

   788   } else {

   789     return true;

   790   }

   791 }

   792 

   793 inline void MacroAssembler::membar( Membar_mask_bits const7a ) {

   794   // Uniprocessors do not need memory barriers

   795   if (!os::is_MP()) return;

   796   // Weakened for current Sparcs and TSO.  See the v9 manual, sections 8.4.3,

   797   // 8.4.4.3, a.31 and a.50.

   798   if( VM_Version::v9_instructions_work() ) {

   799     // Under TSO, setting bit 3, 2, or 0 is redundant, so the only value

   800     // of the mmask subfield of const7a that does anything that isn't done

   801     // implicitly is StoreLoad.

   802     const Membar_mask_bits effective_mask =

   803         Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));

   804     if ( effective_mask != 0 ) {

   805       Assembler::membar( effective_mask );

   806     }

   807   } else {

   808     // stbar is the closest there is on v8.  Equivalent to membar(StoreStore).  We

   809     // do not issue the stbar because to my knowledge all v8 machines implement TSO,

   810     // which guarantees that all stores behave as if an stbar were issued just after

   811     // each one of them.  On these machines, stbar ought to be a nop.  There doesn't

   812     // appear to be an equivalent of membar(StoreLoad) on v8: TSO doesn't require it,

   813     // it can't be specified by stbar, nor have I come up with a way to simulate it.

   814     //

   815     // Addendum.  Dave says that ldstub guarantees a write buffer flush to coherent

   816     // space.  Put one here to be on the safe side.

   817     Assembler::ldstub(SP, 0, G0);

   818   }

   819 }

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