Tue, 24 Jun 2008 10:43:29 -0700
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
Summary: Remove DecodeNNode::decode() and EncodePNode::encode() methods.
Reviewed-by: rasbold, never
1 /*
2 * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
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22 *
23 */
25 class Compile;
26 class Node;
27 class MachNode;
28 class MachTypeNode;
29 class MachOper;
31 //---------------------------Matcher-------------------------------------------
32 class Matcher : public PhaseTransform {
33 friend class VMStructs;
34 // Private arena of State objects
35 ResourceArea _states_arena;
37 VectorSet _visited; // Visit bits
39 // Used to control the Label pass
40 VectorSet _shared; // Shared Ideal Node
41 VectorSet _dontcare; // Nothing the matcher cares about
43 // Private methods which perform the actual matching and reduction
44 // Walks the label tree, generating machine nodes
45 MachNode *ReduceInst( State *s, int rule, Node *&mem);
46 void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach);
47 uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds);
48 void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach );
50 // If this node already matched using "rule", return the MachNode for it.
51 MachNode* find_shared_node(Node* n, uint rule);
53 // Convert a dense opcode number to an expanded rule number
54 const int *_reduceOp;
55 const int *_leftOp;
56 const int *_rightOp;
58 // Map dense opcode number to info on when rule is swallowed constant.
59 const bool *_swallowed;
61 // Map dense rule number to determine if this is an instruction chain rule
62 const uint _begin_inst_chain_rule;
63 const uint _end_inst_chain_rule;
65 // We want to clone constants and possible CmpI-variants.
66 // If we do not clone CmpI, then we can have many instances of
67 // condition codes alive at once. This is OK on some chips and
68 // bad on others. Hence the machine-dependent table lookup.
69 const char *_must_clone;
71 // Find shared Nodes, or Nodes that otherwise are Matcher roots
72 void find_shared( Node *n );
74 // Debug and profile information for nodes in old space:
75 GrowableArray<Node_Notes*>* _old_node_note_array;
77 // Node labeling iterator for instruction selection
78 Node *Label_Root( const Node *n, State *svec, Node *control, const Node *mem );
80 Node *transform( Node *dummy );
82 Node_List &_proj_list; // For Machine nodes killing many values
84 Node_Array _shared_nodes;
86 debug_only(Node_Array _old2new_map;) // Map roots of ideal-trees to machine-roots
88 // Accessors for the inherited field PhaseTransform::_nodes:
89 void grow_new_node_array(uint idx_limit) {
90 _nodes.map(idx_limit-1, NULL);
91 }
92 bool has_new_node(const Node* n) const {
93 return _nodes.at(n->_idx) != NULL;
94 }
95 Node* new_node(const Node* n) const {
96 assert(has_new_node(n), "set before get");
97 return _nodes.at(n->_idx);
98 }
99 void set_new_node(const Node* n, Node *nn) {
100 assert(!has_new_node(n), "set only once");
101 _nodes.map(n->_idx, nn);
102 }
104 #ifdef ASSERT
105 // Make sure only new nodes are reachable from this node
106 void verify_new_nodes_only(Node* root);
108 Node* _mem_node; // Ideal memory node consumed by mach node
109 #endif
111 public:
112 int LabelRootDepth;
113 static const int base2reg[]; // Map Types to machine register types
114 // Convert ideal machine register to a register mask for spill-loads
115 static const RegMask *idealreg2regmask[];
116 RegMask *idealreg2spillmask[_last_machine_leaf];
117 RegMask *idealreg2debugmask[_last_machine_leaf];
118 void init_spill_mask( Node *ret );
119 // Convert machine register number to register mask
120 static uint mreg2regmask_max;
121 static RegMask mreg2regmask[];
122 static RegMask STACK_ONLY_mask;
124 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; }
125 void set_shared( Node *n ) { _shared.set(n->_idx); }
126 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; }
127 void set_visited( Node *n ) { _visited.set(n->_idx); }
128 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; }
129 void set_dontcare( Node *n ) { _dontcare.set(n->_idx); }
131 // Mode bit to tell DFA and expand rules whether we are running after
132 // (or during) register selection. Usually, the matcher runs before,
133 // but it will also get called to generate post-allocation spill code.
134 // In this situation, it is a deadly error to attempt to allocate more
135 // temporary registers.
136 bool _allocation_started;
138 // Machine register names
139 static const char *regName[];
140 // Machine register encodings
141 static const unsigned char _regEncode[];
142 // Machine Node names
143 const char **_ruleName;
144 // Rules that are cheaper to rematerialize than to spill
145 static const uint _begin_rematerialize;
146 static const uint _end_rematerialize;
148 // An array of chars, from 0 to _last_Mach_Reg.
149 // No Save = 'N' (for register windows)
150 // Save on Entry = 'E'
151 // Save on Call = 'C'
152 // Always Save = 'A' (same as SOE + SOC)
153 const char *_register_save_policy;
154 const char *_c_reg_save_policy;
155 // Convert a machine register to a machine register type, so-as to
156 // properly match spill code.
157 const int *_register_save_type;
158 // Maps from machine register to boolean; true if machine register can
159 // be holding a call argument in some signature.
160 static bool can_be_java_arg( int reg );
161 // Maps from machine register to boolean; true if machine register holds
162 // a spillable argument.
163 static bool is_spillable_arg( int reg );
165 // List of IfFalse or IfTrue Nodes that indicate a taken null test.
166 // List is valid in the post-matching space.
167 Node_List _null_check_tests;
168 void collect_null_checks( Node *proj );
169 void validate_null_checks( );
171 Matcher( Node_List &proj_list );
173 // Select instructions for entire method
174 void match( );
175 // Helper for match
176 OptoReg::Name warp_incoming_stk_arg( VMReg reg );
178 // Transform, then walk. Does implicit DCE while walking.
179 // Name changed from "transform" to avoid it being virtual.
180 Node *xform( Node *old_space_node, int Nodes );
182 // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce.
183 MachNode *match_tree( const Node *n );
184 MachNode *match_sfpt( SafePointNode *sfpt );
185 // Helper for match_sfpt
186 OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call );
188 // Initialize first stack mask and related masks.
189 void init_first_stack_mask();
191 // If we should save-on-entry this register
192 bool is_save_on_entry( int reg );
194 // Fixup the save-on-entry registers
195 void Fixup_Save_On_Entry( );
197 // --- Frame handling ---
199 // Register number of the stack slot corresponding to the incoming SP.
200 // Per the Big Picture in the AD file, it is:
201 // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2.
202 OptoReg::Name _old_SP;
204 // Register number of the stack slot corresponding to the highest incoming
205 // argument on the stack. Per the Big Picture in the AD file, it is:
206 // _old_SP + out_preserve_stack_slots + incoming argument size.
207 OptoReg::Name _in_arg_limit;
209 // Register number of the stack slot corresponding to the new SP.
210 // Per the Big Picture in the AD file, it is:
211 // _in_arg_limit + pad0
212 OptoReg::Name _new_SP;
214 // Register number of the stack slot corresponding to the highest outgoing
215 // argument on the stack. Per the Big Picture in the AD file, it is:
216 // _new_SP + max outgoing arguments of all calls
217 OptoReg::Name _out_arg_limit;
219 OptoRegPair *_parm_regs; // Array of machine registers per argument
220 RegMask *_calling_convention_mask; // Array of RegMasks per argument
222 // Does matcher support this ideal node?
223 static const bool has_match_rule(int opcode);
224 static const bool _hasMatchRule[_last_opcode];
226 // Used to determine if we have fast l2f conversion
227 // USII has it, USIII doesn't
228 static const bool convL2FSupported(void);
230 // Vector width in bytes
231 static const uint vector_width_in_bytes(void);
233 // Vector ideal reg
234 static const uint vector_ideal_reg(void);
236 // Used to determine a "low complexity" 64-bit constant. (Zero is simple.)
237 // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI).
238 // Depends on the details of 64-bit constant generation on the CPU.
239 static const bool isSimpleConstant64(jlong con);
241 // These calls are all generated by the ADLC
243 // TRUE - grows up, FALSE - grows down (Intel)
244 virtual bool stack_direction() const;
246 // Java-Java calling convention
247 // (what you use when Java calls Java)
249 // Alignment of stack in bytes, standard Intel word alignment is 4.
250 // Sparc probably wants at least double-word (8).
251 static uint stack_alignment_in_bytes();
252 // Alignment of stack, measured in stack slots.
253 // The size of stack slots is defined by VMRegImpl::stack_slot_size.
254 static uint stack_alignment_in_slots() {
255 return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size);
256 }
258 // Array mapping arguments to registers. Argument 0 is usually the 'this'
259 // pointer. Registers can include stack-slots and regular registers.
260 static void calling_convention( BasicType *, VMRegPair *, uint len, bool is_outgoing );
262 // Convert a sig into a calling convention register layout
263 // and find interesting things about it.
264 static OptoReg::Name find_receiver( bool is_outgoing );
265 // Return address register. On Intel it is a stack-slot. On PowerPC
266 // it is the Link register. On Sparc it is r31?
267 virtual OptoReg::Name return_addr() const;
268 RegMask _return_addr_mask;
269 // Return value register. On Intel it is EAX. On Sparc i0/o0.
270 static OptoRegPair return_value(int ideal_reg, bool is_outgoing);
271 static OptoRegPair c_return_value(int ideal_reg, bool is_outgoing);
272 RegMask _return_value_mask;
273 // Inline Cache Register
274 static OptoReg::Name inline_cache_reg();
275 static const RegMask &inline_cache_reg_mask();
276 static int inline_cache_reg_encode();
278 // Register for DIVI projection of divmodI
279 static RegMask divI_proj_mask();
280 // Register for MODI projection of divmodI
281 static RegMask modI_proj_mask();
283 // Register for DIVL projection of divmodL
284 static RegMask divL_proj_mask();
285 // Register for MODL projection of divmodL
286 static RegMask modL_proj_mask();
288 // Java-Interpreter calling convention
289 // (what you use when calling between compiled-Java and Interpreted-Java
291 // Number of callee-save + always-save registers
292 // Ignores frame pointer and "special" registers
293 static int number_of_saved_registers();
295 // The Method-klass-holder may be passed in the inline_cache_reg
296 // and then expanded into the inline_cache_reg and a method_oop register
298 static OptoReg::Name interpreter_method_oop_reg();
299 static const RegMask &interpreter_method_oop_reg_mask();
300 static int interpreter_method_oop_reg_encode();
302 static OptoReg::Name compiler_method_oop_reg();
303 static const RegMask &compiler_method_oop_reg_mask();
304 static int compiler_method_oop_reg_encode();
306 // Interpreter's Frame Pointer Register
307 static OptoReg::Name interpreter_frame_pointer_reg();
308 static const RegMask &interpreter_frame_pointer_reg_mask();
310 // Java-Native calling convention
311 // (what you use when intercalling between Java and C++ code)
313 // Array mapping arguments to registers. Argument 0 is usually the 'this'
314 // pointer. Registers can include stack-slots and regular registers.
315 static void c_calling_convention( BasicType*, VMRegPair *, uint );
316 // Frame pointer. The frame pointer is kept at the base of the stack
317 // and so is probably the stack pointer for most machines. On Intel
318 // it is ESP. On the PowerPC it is R1. On Sparc it is SP.
319 OptoReg::Name c_frame_pointer() const;
320 static RegMask c_frame_ptr_mask;
322 // !!!!! Special stuff for building ScopeDescs
323 virtual int regnum_to_fpu_offset(int regnum);
325 // Is this branch offset small enough to be addressed by a short branch?
326 bool is_short_branch_offset(int offset);
328 // Optional scaling for the parameter to the ClearArray/CopyArray node.
329 static const bool init_array_count_is_in_bytes;
331 // Threshold small size (in bytes) for a ClearArray/CopyArray node.
332 // Anything this size or smaller may get converted to discrete scalar stores.
333 static const int init_array_short_size;
335 // Should the Matcher clone shifts on addressing modes, expecting them to
336 // be subsumed into complex addressing expressions or compute them into
337 // registers? True for Intel but false for most RISCs
338 static const bool clone_shift_expressions;
340 // Is it better to copy float constants, or load them directly from memory?
341 // Intel can load a float constant from a direct address, requiring no
342 // extra registers. Most RISCs will have to materialize an address into a
343 // register first, so they may as well materialize the constant immediately.
344 static const bool rematerialize_float_constants;
346 // If CPU can load and store mis-aligned doubles directly then no fixup is
347 // needed. Else we split the double into 2 integer pieces and move it
348 // piece-by-piece. Only happens when passing doubles into C code or when
349 // calling i2c adapters as the Java calling convention forces doubles to be
350 // aligned.
351 static const bool misaligned_doubles_ok;
353 // Perform a platform dependent implicit null fixup. This is needed
354 // on windows95 to take care of some unusual register constraints.
355 void pd_implicit_null_fixup(MachNode *load, uint idx);
357 // Advertise here if the CPU requires explicit rounding operations
358 // to implement the UseStrictFP mode.
359 static const bool strict_fp_requires_explicit_rounding;
361 // Do floats take an entire double register or just half?
362 static const bool float_in_double;
363 // Do ints take an entire long register or just half?
364 static const bool int_in_long;
366 // This routine is run whenever a graph fails to match.
367 // If it returns, the compiler should bailout to interpreter without error.
368 // In non-product mode, SoftMatchFailure is false to detect non-canonical
369 // graphs. Print a message and exit.
370 static void soft_match_failure() {
371 if( SoftMatchFailure ) return;
372 else { fatal("SoftMatchFailure is not allowed except in product"); }
373 }
375 // Used by the DFA in dfa_sparc.cpp. Check for a prior FastLock
376 // acting as an Acquire and thus we don't need an Acquire here. We
377 // retain the Node to act as a compiler ordering barrier.
378 static bool prior_fast_lock( const Node *acq );
380 // Used by the DFA in dfa_sparc.cpp. Check for a following
381 // FastUnLock acting as a Release and thus we don't need a Release
382 // here. We retain the Node to act as a compiler ordering barrier.
383 static bool post_fast_unlock( const Node *rel );
385 // Check for a following volatile memory barrier without an
386 // intervening load and thus we don't need a barrier here. We
387 // retain the Node to act as a compiler ordering barrier.
388 static bool post_store_load_barrier(const Node* mb);
391 #ifdef ASSERT
392 void dump_old2new_map(); // machine-independent to machine-dependent
393 #endif
394 };