src/cpu/sparc/vm/vmreg_sparc.inline.hpp

Tue, 24 Jul 2012 10:51:00 -0700

author
twisti
date
Tue, 24 Jul 2012 10:51:00 -0700
changeset 3969
1d7922586cf6
parent 2314
f95d63e2154a
child 6876
710a3c8b516e
permissions
-rw-r--r--

7023639: JSR 292 method handle invocation needs a fast path for compiled code
6984705: JSR 292 method handle creation should not go through JNI
Summary: remove assembly code for JDK 7 chained method handles
Reviewed-by: jrose, twisti, kvn, mhaupt
Contributed-by: John Rose <john.r.rose@oracle.com>, Christian Thalinger <christian.thalinger@oracle.com>, Michael Haupt <michael.haupt@oracle.com>

     1 /*
     2  * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     4  *
     5  * This code is free software; you can redistribute it and/or modify it
     6  * under the terms of the GNU General Public License version 2 only, as
     7  * published by the Free Software Foundation.
     8  *
     9  * This code is distributed in the hope that it will be useful, but WITHOUT
    10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    12  * version 2 for more details (a copy is included in the LICENSE file that
    13  * accompanied this code).
    14  *
    15  * You should have received a copy of the GNU General Public License version
    16  * 2 along with this work; if not, write to the Free Software Foundation,
    17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
    18  *
    19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
    20  * or visit www.oracle.com if you need additional information or have any
    21  * questions.
    22  *
    23  */
    25 #ifndef CPU_SPARC_VM_VMREG_SPARC_INLINE_HPP
    26 #define CPU_SPARC_VM_VMREG_SPARC_INLINE_HPP
    28 inline VMReg RegisterImpl::as_VMReg() {
    29   if( this==noreg ) return VMRegImpl::Bad();
    30   return VMRegImpl::as_VMReg(encoding() << 1 );
    31 }
    33 inline VMReg FloatRegisterImpl::as_VMReg() { return VMRegImpl::as_VMReg( ConcreteRegisterImpl::max_gpr + encoding() ); }
    36 inline bool VMRegImpl::is_Register() { return value() >= 0 && value() < ConcreteRegisterImpl::max_gpr; }
    37 inline bool VMRegImpl::is_FloatRegister() { return value() >= ConcreteRegisterImpl::max_gpr &&
    38                                                    value() < ConcreteRegisterImpl::max_fpr; }
    39 inline Register VMRegImpl::as_Register() {
    41   assert( is_Register() && is_even(value()), "even-aligned GPR name" );
    42   // Yuk
    43   return ::as_Register(value()>>1);
    44 }
    46 inline FloatRegister VMRegImpl::as_FloatRegister() {
    47   assert( is_FloatRegister(), "must be" );
    48   // Yuk
    49   return ::as_FloatRegister( value() - ConcreteRegisterImpl::max_gpr );
    50 }
    52 inline   bool VMRegImpl::is_concrete() {
    53   assert(is_reg(), "must be");
    54   int v = value();
    55   if ( v  <  ConcreteRegisterImpl::max_gpr ) {
    56     return is_even(v);
    57   }
    58   // F0..F31
    59   if ( v <= ConcreteRegisterImpl::max_gpr + 31) return true;
    60   if ( v <  ConcreteRegisterImpl::max_fpr) {
    61     return is_even(v);
    62   }
    63   assert(false, "what register?");
    64   return false;
    65 }
    67 #endif // CPU_SPARC_VM_VMREG_SPARC_INLINE_HPP

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