src/cpu/sparc/vm/c1_LinearScan_sparc.hpp

Tue, 24 Jul 2012 10:51:00 -0700

author
twisti
date
Tue, 24 Jul 2012 10:51:00 -0700
changeset 3969
1d7922586cf6
parent 2314
f95d63e2154a
child 4056
7edbe32b9802
permissions
-rw-r--r--

7023639: JSR 292 method handle invocation needs a fast path for compiled code
6984705: JSR 292 method handle creation should not go through JNI
Summary: remove assembly code for JDK 7 chained method handles
Reviewed-by: jrose, twisti, kvn, mhaupt
Contributed-by: John Rose <john.r.rose@oracle.com>, Christian Thalinger <christian.thalinger@oracle.com>, Michael Haupt <michael.haupt@oracle.com>

     1 /*
     2  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     4  *
     5  * This code is free software; you can redistribute it and/or modify it
     6  * under the terms of the GNU General Public License version 2 only, as
     7  * published by the Free Software Foundation.
     8  *
     9  * This code is distributed in the hope that it will be useful, but WITHOUT
    10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    12  * version 2 for more details (a copy is included in the LICENSE file that
    13  * accompanied this code).
    14  *
    15  * You should have received a copy of the GNU General Public License version
    16  * 2 along with this work; if not, write to the Free Software Foundation,
    17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
    18  *
    19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
    20  * or visit www.oracle.com if you need additional information or have any
    21  * questions.
    22  *
    23  */
    25 #ifndef CPU_SPARC_VM_C1_LINEARSCAN_SPARC_HPP
    26 #define CPU_SPARC_VM_C1_LINEARSCAN_SPARC_HPP
    28 inline bool LinearScan::is_processed_reg_num(int reg_num) {
    29   return reg_num < 26 || reg_num > 31;
    30 }
    32 inline int LinearScan::num_physical_regs(BasicType type) {
    33   // Sparc requires two cpu registers for long
    34   // and two cpu registers for double
    35 #ifdef _LP64
    36   if (type == T_DOUBLE) {
    37 #else
    38   if (type == T_DOUBLE || type == T_LONG) {
    39 #endif
    40     return 2;
    41   }
    42   return 1;
    43 }
    46 inline bool LinearScan::requires_adjacent_regs(BasicType type) {
    47 #ifdef _LP64
    48   return type == T_DOUBLE;
    49 #else
    50   return type == T_DOUBLE || type == T_LONG;
    51 #endif
    52 }
    54 inline bool LinearScan::is_caller_save(int assigned_reg) {
    55   return assigned_reg > pd_last_callee_saved_reg && assigned_reg <= pd_last_fpu_reg;
    56 }
    59 inline void LinearScan::pd_add_temps(LIR_Op* op) {
    60   // No special case behaviours yet
    61 }
    64 inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) {
    65   if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::callee_saved)) {
    66     assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only");
    67     _first_reg = pd_first_callee_saved_reg;
    68     _last_reg = pd_last_callee_saved_reg;
    69     return true;
    70   } else if (cur->type() == T_INT || cur->type() == T_LONG || cur->type() == T_OBJECT || cur->type() == T_ADDRESS) {
    71     _first_reg = pd_first_cpu_reg;
    72     _last_reg = pd_last_allocatable_cpu_reg;
    73     return true;
    74   }
    75   return false;
    76 }
    78 #endif // CPU_SPARC_VM_C1_LINEARSCAN_SPARC_HPP

mercurial