Tue, 16 Aug 2011 16:59:46 -0700
7079329: Adjust allocation prefetching for T4
Summary: on T4 2 BIS instructions should be issued to prefetch 64 bytes
Reviewed-by: iveresov, phh, twisti
1 /*
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #include "precompiled.hpp"
26 #include "assembler_sparc.inline.hpp"
27 #include "memory/resourceArea.hpp"
28 #include "runtime/java.hpp"
29 #include "runtime/stubCodeGenerator.hpp"
30 #include "vm_version_sparc.hpp"
31 #ifdef TARGET_OS_FAMILY_linux
32 # include "os_linux.inline.hpp"
33 #endif
34 #ifdef TARGET_OS_FAMILY_solaris
35 # include "os_solaris.inline.hpp"
36 #endif
38 int VM_Version::_features = VM_Version::unknown_m;
39 const char* VM_Version::_features_str = "";
41 void VM_Version::initialize() {
42 _features = determine_features();
43 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
44 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
45 PrefetchFieldsAhead = prefetch_fields_ahead();
47 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value");
48 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
49 if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0;
51 // Allocation prefetch settings
52 intx cache_line_size = prefetch_data_size();
53 if( cache_line_size > AllocatePrefetchStepSize )
54 AllocatePrefetchStepSize = cache_line_size;
56 assert(AllocatePrefetchLines > 0, "invalid value");
57 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
58 AllocatePrefetchLines = 3;
59 assert(AllocateInstancePrefetchLines > 0, "invalid value");
60 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
61 AllocateInstancePrefetchLines = 1;
63 AllocatePrefetchDistance = allocate_prefetch_distance();
64 AllocatePrefetchStyle = allocate_prefetch_style();
66 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 &&
67 (AllocatePrefetchDistance > 0), "invalid value");
68 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 ||
69 (AllocatePrefetchDistance <= 0)) {
70 AllocatePrefetchDistance = AllocatePrefetchStepSize;
71 }
73 if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
74 warning("BIS instructions are not available on this CPU");
75 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
76 }
78 UseSSE = 0; // Only on x86 and x64
80 _supports_cx8 = has_v9();
82 if (is_niagara()) {
83 // Indirect branch is the same cost as direct
84 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
85 FLAG_SET_DEFAULT(UseInlineCaches, false);
86 }
87 // Align loops on a single instruction boundary.
88 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
89 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
90 }
91 // When using CMS, we cannot use memset() in BOT updates because
92 // the sun4v/CMT version in libc_psr uses BIS which exposes
93 // "phantom zeros" to concurrent readers. See 6948537.
94 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && UseConcMarkSweepGC) {
95 FLAG_SET_DEFAULT(UseMemSetInBOT, false);
96 }
97 #ifdef _LP64
98 // 32-bit oops don't make sense for the 64-bit VM on sparc
99 // since the 32-bit VM has the same registers and smaller objects.
100 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
101 #endif // _LP64
102 #ifdef COMPILER2
103 // Indirect branch is the same cost as direct
104 if (FLAG_IS_DEFAULT(UseJumpTables)) {
105 FLAG_SET_DEFAULT(UseJumpTables, true);
106 }
107 // Single-issue, so entry and loop tops are
108 // aligned on a single instruction boundary
109 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
110 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
111 }
112 if (is_niagara_plus()) {
113 if (has_blk_init() && UseTLAB &&
114 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
115 // Use BIS instruction for TLAB allocation prefetch.
116 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
117 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
118 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
119 }
120 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
121 // Use smaller prefetch distance with BIS
122 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
123 }
124 }
125 if (is_T4()) {
126 // Double number of prefetched cache lines on T4
127 // since L2 cache line size is smaller (32 bytes).
128 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
129 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
130 }
131 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
132 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
133 }
134 }
135 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
136 // Use different prefetch distance without BIS
137 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
138 }
139 if (AllocatePrefetchInstr == 1) {
140 // Need a space at the end of TLAB for BIS since it
141 // will fault when accessing memory outside of heap.
143 // +1 for rounding up to next cache line, +1 to be safe
144 int lines = AllocatePrefetchLines + 2;
145 int step_size = AllocatePrefetchStepSize;
146 int distance = AllocatePrefetchDistance;
147 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
148 }
149 }
150 #endif
151 }
153 // Use hardware population count instruction if available.
154 if (has_hardware_popc()) {
155 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
156 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
157 }
158 } else if (UsePopCountInstruction) {
159 warning("POPC instruction is not available on this CPU");
160 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
161 }
163 // T4 and newer Sparc cpus have new compare and branch instruction.
164 if (has_cbcond()) {
165 if (FLAG_IS_DEFAULT(UseCBCond)) {
166 FLAG_SET_DEFAULT(UseCBCond, true);
167 }
168 } else if (UseCBCond) {
169 warning("CBCOND instruction is not available on this CPU");
170 FLAG_SET_DEFAULT(UseCBCond, false);
171 }
173 #ifdef COMPILER2
174 // T4 and newer Sparc cpus have fast RDPC.
175 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
176 // FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
177 }
179 // Currently not supported anywhere.
180 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
182 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
183 #endif
185 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
186 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
188 char buf[512];
189 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
190 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
191 (has_hardware_popc() ? ", popc" : ""),
192 (has_vis1() ? ", vis1" : ""),
193 (has_vis2() ? ", vis2" : ""),
194 (has_vis3() ? ", vis3" : ""),
195 (has_blk_init() ? ", blk_init" : ""),
196 (has_cbcond() ? ", cbcond" : ""),
197 (is_ultra3() ? ", ultra3" : ""),
198 (is_sun4v() ? ", sun4v" : ""),
199 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
200 (is_sparc64() ? ", sparc64" : ""),
201 (!has_hardware_mul32() ? ", no-mul32" : ""),
202 (!has_hardware_div32() ? ", no-div32" : ""),
203 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
205 // buf is started with ", " or is empty
206 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);
208 // UseVIS is set to the smallest of what hardware supports and what
209 // the command line requires. I.e., you cannot set UseVIS to 3 on
210 // older UltraSparc which do not support it.
211 if (UseVIS > 3) UseVIS=3;
212 if (UseVIS < 0) UseVIS=0;
213 if (!has_vis3()) // Drop to 2 if no VIS3 support
214 UseVIS = MIN2((intx)2,UseVIS);
215 if (!has_vis2()) // Drop to 1 if no VIS2 support
216 UseVIS = MIN2((intx)1,UseVIS);
217 if (!has_vis1()) // Drop to 0 if no VIS1 support
218 UseVIS = 0;
220 #ifndef PRODUCT
221 if (PrintMiscellaneous && Verbose) {
222 tty->print("Allocation");
223 if (AllocatePrefetchStyle <= 0) {
224 tty->print_cr(": no prefetching");
225 } else {
226 tty->print(" prefetching: ");
227 if (AllocatePrefetchInstr == 0) {
228 tty->print("PREFETCH");
229 } else if (AllocatePrefetchInstr == 1) {
230 tty->print("BIS");
231 }
232 if (AllocatePrefetchLines > 1) {
233 tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
234 } else {
235 tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize);
236 }
237 }
238 if (PrefetchCopyIntervalInBytes > 0) {
239 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
240 }
241 if (PrefetchScanIntervalInBytes > 0) {
242 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
243 }
244 if (PrefetchFieldsAhead > 0) {
245 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
246 }
247 }
248 #endif // PRODUCT
249 }
251 void VM_Version::print_features() {
252 tty->print_cr("Version:%s", cpu_features());
253 }
255 int VM_Version::determine_features() {
256 if (UseV8InstrsOnly) {
257 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");)
258 return generic_v8_m;
259 }
261 int features = platform_features(unknown_m); // platform_features() is os_arch specific
263 if (features == unknown_m) {
264 features = generic_v9_m;
265 warning("Cannot recognize SPARC version. Default to V9");
266 }
268 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
269 if (UseNiagaraInstrs) { // Force code generation for Niagara
270 if (is_T_family(features)) {
271 // Happy to accomodate...
272 } else {
273 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");)
274 features |= T_family_m;
275 }
276 } else {
277 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
278 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");)
279 features &= ~(T_family_m | T1_model_m);
280 } else {
281 // Happy to accomodate...
282 }
283 }
285 return features;
286 }
288 static int saved_features = 0;
290 void VM_Version::allow_all() {
291 saved_features = _features;
292 _features = all_features_m;
293 }
295 void VM_Version::revert() {
296 _features = saved_features;
297 }
299 unsigned int VM_Version::calc_parallel_worker_threads() {
300 unsigned int result;
301 if (is_niagara_plus()) {
302 result = nof_parallel_worker_threads(5, 16, 8);
303 } else {
304 result = nof_parallel_worker_threads(5, 8, 8);
305 }
306 return result;
307 }