Thu, 26 Sep 2013 10:25:02 -0400
7195622: CheckUnhandledOops has limited usefulness now
Summary: Enable CHECK_UNHANDLED_OOPS in fastdebug builds across all supported platforms.
Reviewed-by: coleenp, hseigel, dholmes, stefank, twisti, ihse, rdurbin
Contributed-by: lois.foltan@oracle.com
1 //
2 // Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
25 // AMD64 Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
89 #ifdef _WIN64
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
97 #else
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
105 #endif
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
132 // Floating Point Registers
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
169 // Class for all pointer registers (including RSP)
170 reg_class any_reg(RAX, RAX_H,
171 RDX, RDX_H,
172 RBP, RBP_H,
173 RDI, RDI_H,
174 RSI, RSI_H,
175 RCX, RCX_H,
176 RBX, RBX_H,
177 RSP, RSP_H,
178 R8, R8_H,
179 R9, R9_H,
180 R10, R10_H,
181 R11, R11_H,
182 R12, R12_H,
183 R13, R13_H,
184 R14, R14_H,
185 R15, R15_H);
187 // Class for all pointer registers except RSP
188 reg_class ptr_reg(RAX, RAX_H,
189 RDX, RDX_H,
190 RBP, RBP_H,
191 RDI, RDI_H,
192 RSI, RSI_H,
193 RCX, RCX_H,
194 RBX, RBX_H,
195 R8, R8_H,
196 R9, R9_H,
197 R10, R10_H,
198 R11, R11_H,
199 R13, R13_H,
200 R14, R14_H);
202 // Class for all pointer registers except RAX and RSP
203 reg_class ptr_no_rax_reg(RDX, RDX_H,
204 RBP, RBP_H,
205 RDI, RDI_H,
206 RSI, RSI_H,
207 RCX, RCX_H,
208 RBX, RBX_H,
209 R8, R8_H,
210 R9, R9_H,
211 R10, R10_H,
212 R11, R11_H,
213 R13, R13_H,
214 R14, R14_H);
216 reg_class ptr_no_rbp_reg(RDX, RDX_H,
217 RAX, RAX_H,
218 RDI, RDI_H,
219 RSI, RSI_H,
220 RCX, RCX_H,
221 RBX, RBX_H,
222 R8, R8_H,
223 R9, R9_H,
224 R10, R10_H,
225 R11, R11_H,
226 R13, R13_H,
227 R14, R14_H);
229 // Class for all pointer registers except RAX, RBX and RSP
230 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
231 RBP, RBP_H,
232 RDI, RDI_H,
233 RSI, RSI_H,
234 RCX, RCX_H,
235 R8, R8_H,
236 R9, R9_H,
237 R10, R10_H,
238 R11, R11_H,
239 R13, R13_H,
240 R14, R14_H);
242 // Singleton class for RAX pointer register
243 reg_class ptr_rax_reg(RAX, RAX_H);
245 // Singleton class for RBX pointer register
246 reg_class ptr_rbx_reg(RBX, RBX_H);
248 // Singleton class for RSI pointer register
249 reg_class ptr_rsi_reg(RSI, RSI_H);
251 // Singleton class for RDI pointer register
252 reg_class ptr_rdi_reg(RDI, RDI_H);
254 // Singleton class for RBP pointer register
255 reg_class ptr_rbp_reg(RBP, RBP_H);
257 // Singleton class for stack pointer
258 reg_class ptr_rsp_reg(RSP, RSP_H);
260 // Singleton class for TLS pointer
261 reg_class ptr_r15_reg(R15, R15_H);
263 // Class for all long registers (except RSP)
264 reg_class long_reg(RAX, RAX_H,
265 RDX, RDX_H,
266 RBP, RBP_H,
267 RDI, RDI_H,
268 RSI, RSI_H,
269 RCX, RCX_H,
270 RBX, RBX_H,
271 R8, R8_H,
272 R9, R9_H,
273 R10, R10_H,
274 R11, R11_H,
275 R13, R13_H,
276 R14, R14_H);
278 // Class for all long registers except RAX, RDX (and RSP)
279 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
280 RDI, RDI_H,
281 RSI, RSI_H,
282 RCX, RCX_H,
283 RBX, RBX_H,
284 R8, R8_H,
285 R9, R9_H,
286 R10, R10_H,
287 R11, R11_H,
288 R13, R13_H,
289 R14, R14_H);
291 // Class for all long registers except RCX (and RSP)
292 reg_class long_no_rcx_reg(RBP, RBP_H,
293 RDI, RDI_H,
294 RSI, RSI_H,
295 RAX, RAX_H,
296 RDX, RDX_H,
297 RBX, RBX_H,
298 R8, R8_H,
299 R9, R9_H,
300 R10, R10_H,
301 R11, R11_H,
302 R13, R13_H,
303 R14, R14_H);
305 // Class for all long registers except RAX (and RSP)
306 reg_class long_no_rax_reg(RBP, RBP_H,
307 RDX, RDX_H,
308 RDI, RDI_H,
309 RSI, RSI_H,
310 RCX, RCX_H,
311 RBX, RBX_H,
312 R8, R8_H,
313 R9, R9_H,
314 R10, R10_H,
315 R11, R11_H,
316 R13, R13_H,
317 R14, R14_H);
319 // Singleton class for RAX long register
320 reg_class long_rax_reg(RAX, RAX_H);
322 // Singleton class for RCX long register
323 reg_class long_rcx_reg(RCX, RCX_H);
325 // Singleton class for RDX long register
326 reg_class long_rdx_reg(RDX, RDX_H);
328 // Class for all int registers (except RSP)
329 reg_class int_reg(RAX,
330 RDX,
331 RBP,
332 RDI,
333 RSI,
334 RCX,
335 RBX,
336 R8,
337 R9,
338 R10,
339 R11,
340 R13,
341 R14);
343 // Class for all int registers except RCX (and RSP)
344 reg_class int_no_rcx_reg(RAX,
345 RDX,
346 RBP,
347 RDI,
348 RSI,
349 RBX,
350 R8,
351 R9,
352 R10,
353 R11,
354 R13,
355 R14);
357 // Class for all int registers except RAX, RDX (and RSP)
358 reg_class int_no_rax_rdx_reg(RBP,
359 RDI,
360 RSI,
361 RCX,
362 RBX,
363 R8,
364 R9,
365 R10,
366 R11,
367 R13,
368 R14);
370 // Singleton class for RAX int register
371 reg_class int_rax_reg(RAX);
373 // Singleton class for RBX int register
374 reg_class int_rbx_reg(RBX);
376 // Singleton class for RCX int register
377 reg_class int_rcx_reg(RCX);
379 // Singleton class for RCX int register
380 reg_class int_rdx_reg(RDX);
382 // Singleton class for RCX int register
383 reg_class int_rdi_reg(RDI);
385 // Singleton class for instruction pointer
386 // reg_class ip_reg(RIP);
388 %}
390 //----------SOURCE BLOCK-------------------------------------------------------
391 // This is a block of C++ code which provides values, functions, and
392 // definitions necessary in the rest of the architecture description
393 source %{
394 #define RELOC_IMM64 Assembler::imm_operand
395 #define RELOC_DISP32 Assembler::disp32_operand
397 #define __ _masm.
399 static int preserve_SP_size() {
400 return 3; // rex.w, op, rm(reg/reg)
401 }
402 static int clear_avx_size() {
403 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper
404 }
406 // !!!!! Special hack to get all types of calls to specify the byte offset
407 // from the start of the call to the point where the return address
408 // will point.
409 int MachCallStaticJavaNode::ret_addr_offset()
410 {
411 int offset = 5; // 5 bytes from start of call to where return address points
412 offset += clear_avx_size();
413 if (_method_handle_invoke)
414 offset += preserve_SP_size();
415 return offset;
416 }
418 int MachCallDynamicJavaNode::ret_addr_offset()
419 {
420 int offset = 15; // 15 bytes from start of call to where return address points
421 offset += clear_avx_size();
422 return offset;
423 }
425 int MachCallRuntimeNode::ret_addr_offset() {
426 int offset = 13; // movq r10,#addr; callq (r10)
427 offset += clear_avx_size();
428 return offset;
429 }
431 // Indicate if the safepoint node needs the polling page as an input,
432 // it does if the polling page is more than disp32 away.
433 bool SafePointNode::needs_polling_address_input()
434 {
435 return Assembler::is_polling_page_far();
436 }
438 //
439 // Compute padding required for nodes which need alignment
440 //
442 // The address of the call instruction needs to be 4-byte aligned to
443 // ensure that it does not span a cache line so that it can be patched.
444 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
445 {
446 current_offset += clear_avx_size(); // skip vzeroupper
447 current_offset += 1; // skip call opcode byte
448 return round_to(current_offset, alignment_required()) - current_offset;
449 }
451 // The address of the call instruction needs to be 4-byte aligned to
452 // ensure that it does not span a cache line so that it can be patched.
453 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
454 {
455 current_offset += preserve_SP_size(); // skip mov rbp, rsp
456 current_offset += clear_avx_size(); // skip vzeroupper
457 current_offset += 1; // skip call opcode byte
458 return round_to(current_offset, alignment_required()) - current_offset;
459 }
461 // The address of the call instruction needs to be 4-byte aligned to
462 // ensure that it does not span a cache line so that it can be patched.
463 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
464 {
465 current_offset += clear_avx_size(); // skip vzeroupper
466 current_offset += 11; // skip movq instruction + call opcode byte
467 return round_to(current_offset, alignment_required()) - current_offset;
468 }
470 // EMIT_RM()
471 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
472 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
473 cbuf.insts()->emit_int8(c);
474 }
476 // EMIT_CC()
477 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
478 unsigned char c = (unsigned char) (f1 | f2);
479 cbuf.insts()->emit_int8(c);
480 }
482 // EMIT_OPCODE()
483 void emit_opcode(CodeBuffer &cbuf, int code) {
484 cbuf.insts()->emit_int8((unsigned char) code);
485 }
487 // EMIT_OPCODE() w/ relocation information
488 void emit_opcode(CodeBuffer &cbuf,
489 int code, relocInfo::relocType reloc, int offset, int format)
490 {
491 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
492 emit_opcode(cbuf, code);
493 }
495 // EMIT_D8()
496 void emit_d8(CodeBuffer &cbuf, int d8) {
497 cbuf.insts()->emit_int8((unsigned char) d8);
498 }
500 // EMIT_D16()
501 void emit_d16(CodeBuffer &cbuf, int d16) {
502 cbuf.insts()->emit_int16(d16);
503 }
505 // EMIT_D32()
506 void emit_d32(CodeBuffer &cbuf, int d32) {
507 cbuf.insts()->emit_int32(d32);
508 }
510 // EMIT_D64()
511 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
512 cbuf.insts()->emit_int64(d64);
513 }
515 // emit 32 bit value and construct relocation entry from relocInfo::relocType
516 void emit_d32_reloc(CodeBuffer& cbuf,
517 int d32,
518 relocInfo::relocType reloc,
519 int format)
520 {
521 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
522 cbuf.relocate(cbuf.insts_mark(), reloc, format);
523 cbuf.insts()->emit_int32(d32);
524 }
526 // emit 32 bit value and construct relocation entry from RelocationHolder
527 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
528 #ifdef ASSERT
529 if (rspec.reloc()->type() == relocInfo::oop_type &&
530 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
531 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
532 assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
533 }
534 #endif
535 cbuf.relocate(cbuf.insts_mark(), rspec, format);
536 cbuf.insts()->emit_int32(d32);
537 }
539 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
540 address next_ip = cbuf.insts_end() + 4;
541 emit_d32_reloc(cbuf, (int) (addr - next_ip),
542 external_word_Relocation::spec(addr),
543 RELOC_DISP32);
544 }
547 // emit 64 bit value and construct relocation entry from relocInfo::relocType
548 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
549 cbuf.relocate(cbuf.insts_mark(), reloc, format);
550 cbuf.insts()->emit_int64(d64);
551 }
553 // emit 64 bit value and construct relocation entry from RelocationHolder
554 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
555 #ifdef ASSERT
556 if (rspec.reloc()->type() == relocInfo::oop_type &&
557 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
558 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
559 assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()),
560 "cannot embed scavengable oops in code");
561 }
562 #endif
563 cbuf.relocate(cbuf.insts_mark(), rspec, format);
564 cbuf.insts()->emit_int64(d64);
565 }
567 // Access stack slot for load or store
568 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
569 {
570 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
571 if (-0x80 <= disp && disp < 0x80) {
572 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
573 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
574 emit_d8(cbuf, disp); // Displacement // R/M byte
575 } else {
576 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
577 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
578 emit_d32(cbuf, disp); // Displacement // R/M byte
579 }
580 }
582 // rRegI ereg, memory mem) %{ // emit_reg_mem
583 void encode_RegMem(CodeBuffer &cbuf,
584 int reg,
585 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
586 {
587 assert(disp_reloc == relocInfo::none, "cannot have disp");
588 int regenc = reg & 7;
589 int baseenc = base & 7;
590 int indexenc = index & 7;
592 // There is no index & no scale, use form without SIB byte
593 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
594 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
595 if (disp == 0 && base != RBP_enc && base != R13_enc) {
596 emit_rm(cbuf, 0x0, regenc, baseenc); // *
597 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
598 // If 8-bit displacement, mode 0x1
599 emit_rm(cbuf, 0x1, regenc, baseenc); // *
600 emit_d8(cbuf, disp);
601 } else {
602 // If 32-bit displacement
603 if (base == -1) { // Special flag for absolute address
604 emit_rm(cbuf, 0x0, regenc, 0x5); // *
605 if (disp_reloc != relocInfo::none) {
606 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
607 } else {
608 emit_d32(cbuf, disp);
609 }
610 } else {
611 // Normal base + offset
612 emit_rm(cbuf, 0x2, regenc, baseenc); // *
613 if (disp_reloc != relocInfo::none) {
614 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
615 } else {
616 emit_d32(cbuf, disp);
617 }
618 }
619 }
620 } else {
621 // Else, encode with the SIB byte
622 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
623 if (disp == 0 && base != RBP_enc && base != R13_enc) {
624 // If no displacement
625 emit_rm(cbuf, 0x0, regenc, 0x4); // *
626 emit_rm(cbuf, scale, indexenc, baseenc);
627 } else {
628 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
629 // If 8-bit displacement, mode 0x1
630 emit_rm(cbuf, 0x1, regenc, 0x4); // *
631 emit_rm(cbuf, scale, indexenc, baseenc);
632 emit_d8(cbuf, disp);
633 } else {
634 // If 32-bit displacement
635 if (base == 0x04 ) {
636 emit_rm(cbuf, 0x2, regenc, 0x4);
637 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
638 } else {
639 emit_rm(cbuf, 0x2, regenc, 0x4);
640 emit_rm(cbuf, scale, indexenc, baseenc); // *
641 }
642 if (disp_reloc != relocInfo::none) {
643 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
644 } else {
645 emit_d32(cbuf, disp);
646 }
647 }
648 }
649 }
650 }
652 // This could be in MacroAssembler but it's fairly C2 specific
653 void emit_cmpfp_fixup(MacroAssembler& _masm) {
654 Label exit;
655 __ jccb(Assembler::noParity, exit);
656 __ pushf();
657 //
658 // comiss/ucomiss instructions set ZF,PF,CF flags and
659 // zero OF,AF,SF for NaN values.
660 // Fixup flags by zeroing ZF,PF so that compare of NaN
661 // values returns 'less than' result (CF is set).
662 // Leave the rest of flags unchanged.
663 //
664 // 7 6 5 4 3 2 1 0
665 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
666 // 0 0 1 0 1 0 1 1 (0x2B)
667 //
668 __ andq(Address(rsp, 0), 0xffffff2b);
669 __ popf();
670 __ bind(exit);
671 }
673 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
674 Label done;
675 __ movl(dst, -1);
676 __ jcc(Assembler::parity, done);
677 __ jcc(Assembler::below, done);
678 __ setb(Assembler::notEqual, dst);
679 __ movzbl(dst, dst);
680 __ bind(done);
681 }
684 //=============================================================================
685 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
687 int Compile::ConstantTable::calculate_table_base_offset() const {
688 return 0; // absolute addressing, no offset
689 }
691 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
692 // Empty encoding
693 }
695 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
696 return 0;
697 }
699 #ifndef PRODUCT
700 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
701 st->print("# MachConstantBaseNode (empty encoding)");
702 }
703 #endif
706 //=============================================================================
707 #ifndef PRODUCT
708 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
709 Compile* C = ra_->C;
711 int framesize = C->frame_slots() << LogBytesPerInt;
712 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
713 // Remove wordSize for return addr which is already pushed.
714 framesize -= wordSize;
716 if (C->need_stack_bang(framesize)) {
717 framesize -= wordSize;
718 st->print("# stack bang");
719 st->print("\n\t");
720 st->print("pushq rbp\t# Save rbp");
721 if (framesize) {
722 st->print("\n\t");
723 st->print("subq rsp, #%d\t# Create frame",framesize);
724 }
725 } else {
726 st->print("subq rsp, #%d\t# Create frame",framesize);
727 st->print("\n\t");
728 framesize -= wordSize;
729 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
730 }
732 if (VerifyStackAtCalls) {
733 st->print("\n\t");
734 framesize -= wordSize;
735 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
736 #ifdef ASSERT
737 st->print("\n\t");
738 st->print("# stack alignment check");
739 #endif
740 }
741 st->cr();
742 }
743 #endif
745 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
746 Compile* C = ra_->C;
747 MacroAssembler _masm(&cbuf);
749 int framesize = C->frame_slots() << LogBytesPerInt;
751 __ verified_entry(framesize, C->need_stack_bang(framesize), false);
753 C->set_frame_complete(cbuf.insts_size());
755 if (C->has_mach_constant_base_node()) {
756 // NOTE: We set the table base offset here because users might be
757 // emitted before MachConstantBaseNode.
758 Compile::ConstantTable& constant_table = C->constant_table();
759 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
760 }
761 }
763 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
764 {
765 return MachNode::size(ra_); // too many variables; just compute it
766 // the hard way
767 }
769 int MachPrologNode::reloc() const
770 {
771 return 0; // a large enough number
772 }
774 //=============================================================================
775 #ifndef PRODUCT
776 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
777 {
778 Compile* C = ra_->C;
779 if (C->max_vector_size() > 16) {
780 st->print("vzeroupper");
781 st->cr(); st->print("\t");
782 }
784 int framesize = C->frame_slots() << LogBytesPerInt;
785 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
786 // Remove word for return adr already pushed
787 // and RBP
788 framesize -= 2*wordSize;
790 if (framesize) {
791 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
792 st->print("\t");
793 }
795 st->print_cr("popq rbp");
796 if (do_polling() && C->is_method_compilation()) {
797 st->print("\t");
798 if (Assembler::is_polling_page_far()) {
799 st->print_cr("movq rscratch1, #polling_page_address\n\t"
800 "testl rax, [rscratch1]\t"
801 "# Safepoint: poll for GC");
802 } else {
803 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
804 "# Safepoint: poll for GC");
805 }
806 }
807 }
808 #endif
810 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
811 {
812 Compile* C = ra_->C;
813 if (C->max_vector_size() > 16) {
814 // Clear upper bits of YMM registers when current compiled code uses
815 // wide vectors to avoid AVX <-> SSE transition penalty during call.
816 MacroAssembler _masm(&cbuf);
817 __ vzeroupper();
818 }
820 int framesize = C->frame_slots() << LogBytesPerInt;
821 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
822 // Remove word for return adr already pushed
823 // and RBP
824 framesize -= 2*wordSize;
826 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
828 if (framesize) {
829 emit_opcode(cbuf, Assembler::REX_W);
830 if (framesize < 0x80) {
831 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
832 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
833 emit_d8(cbuf, framesize);
834 } else {
835 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
836 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
837 emit_d32(cbuf, framesize);
838 }
839 }
841 // popq rbp
842 emit_opcode(cbuf, 0x58 | RBP_enc);
844 if (do_polling() && C->is_method_compilation()) {
845 MacroAssembler _masm(&cbuf);
846 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
847 if (Assembler::is_polling_page_far()) {
848 __ lea(rscratch1, polling_page);
849 __ relocate(relocInfo::poll_return_type);
850 __ testl(rax, Address(rscratch1, 0));
851 } else {
852 __ testl(rax, polling_page);
853 }
854 }
855 }
857 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
858 {
859 return MachNode::size(ra_); // too many variables; just compute it
860 // the hard way
861 }
863 int MachEpilogNode::reloc() const
864 {
865 return 2; // a large enough number
866 }
868 const Pipeline* MachEpilogNode::pipeline() const
869 {
870 return MachNode::pipeline_class();
871 }
873 int MachEpilogNode::safepoint_offset() const
874 {
875 return 0;
876 }
878 //=============================================================================
880 enum RC {
881 rc_bad,
882 rc_int,
883 rc_float,
884 rc_stack
885 };
887 static enum RC rc_class(OptoReg::Name reg)
888 {
889 if( !OptoReg::is_valid(reg) ) return rc_bad;
891 if (OptoReg::is_stack(reg)) return rc_stack;
893 VMReg r = OptoReg::as_VMReg(reg);
895 if (r->is_Register()) return rc_int;
897 assert(r->is_XMMRegister(), "must be");
898 return rc_float;
899 }
901 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
902 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
903 int src_hi, int dst_hi, uint ireg, outputStream* st);
905 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
906 int stack_offset, int reg, uint ireg, outputStream* st);
908 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
909 int dst_offset, uint ireg, outputStream* st) {
910 if (cbuf) {
911 MacroAssembler _masm(cbuf);
912 switch (ireg) {
913 case Op_VecS:
914 __ movq(Address(rsp, -8), rax);
915 __ movl(rax, Address(rsp, src_offset));
916 __ movl(Address(rsp, dst_offset), rax);
917 __ movq(rax, Address(rsp, -8));
918 break;
919 case Op_VecD:
920 __ pushq(Address(rsp, src_offset));
921 __ popq (Address(rsp, dst_offset));
922 break;
923 case Op_VecX:
924 __ pushq(Address(rsp, src_offset));
925 __ popq (Address(rsp, dst_offset));
926 __ pushq(Address(rsp, src_offset+8));
927 __ popq (Address(rsp, dst_offset+8));
928 break;
929 case Op_VecY:
930 __ vmovdqu(Address(rsp, -32), xmm0);
931 __ vmovdqu(xmm0, Address(rsp, src_offset));
932 __ vmovdqu(Address(rsp, dst_offset), xmm0);
933 __ vmovdqu(xmm0, Address(rsp, -32));
934 break;
935 default:
936 ShouldNotReachHere();
937 }
938 #ifndef PRODUCT
939 } else {
940 switch (ireg) {
941 case Op_VecS:
942 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
943 "movl rax, [rsp + #%d]\n\t"
944 "movl [rsp + #%d], rax\n\t"
945 "movq rax, [rsp - #8]",
946 src_offset, dst_offset);
947 break;
948 case Op_VecD:
949 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
950 "popq [rsp + #%d]",
951 src_offset, dst_offset);
952 break;
953 case Op_VecX:
954 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
955 "popq [rsp + #%d]\n\t"
956 "pushq [rsp + #%d]\n\t"
957 "popq [rsp + #%d]",
958 src_offset, dst_offset, src_offset+8, dst_offset+8);
959 break;
960 case Op_VecY:
961 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
962 "vmovdqu xmm0, [rsp + #%d]\n\t"
963 "vmovdqu [rsp + #%d], xmm0\n\t"
964 "vmovdqu xmm0, [rsp - #32]",
965 src_offset, dst_offset);
966 break;
967 default:
968 ShouldNotReachHere();
969 }
970 #endif
971 }
972 }
974 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
975 PhaseRegAlloc* ra_,
976 bool do_size,
977 outputStream* st) const {
978 assert(cbuf != NULL || st != NULL, "sanity");
979 // Get registers to move
980 OptoReg::Name src_second = ra_->get_reg_second(in(1));
981 OptoReg::Name src_first = ra_->get_reg_first(in(1));
982 OptoReg::Name dst_second = ra_->get_reg_second(this);
983 OptoReg::Name dst_first = ra_->get_reg_first(this);
985 enum RC src_second_rc = rc_class(src_second);
986 enum RC src_first_rc = rc_class(src_first);
987 enum RC dst_second_rc = rc_class(dst_second);
988 enum RC dst_first_rc = rc_class(dst_first);
990 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
991 "must move at least 1 register" );
993 if (src_first == dst_first && src_second == dst_second) {
994 // Self copy, no move
995 return 0;
996 }
997 if (bottom_type()->isa_vect() != NULL) {
998 uint ireg = ideal_reg();
999 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1000 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1001 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1002 // mem -> mem
1003 int src_offset = ra_->reg2offset(src_first);
1004 int dst_offset = ra_->reg2offset(dst_first);
1005 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1006 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1007 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1008 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1009 int stack_offset = ra_->reg2offset(dst_first);
1010 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1011 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1012 int stack_offset = ra_->reg2offset(src_first);
1013 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1014 } else {
1015 ShouldNotReachHere();
1016 }
1017 return 0;
1018 }
1019 if (src_first_rc == rc_stack) {
1020 // mem ->
1021 if (dst_first_rc == rc_stack) {
1022 // mem -> mem
1023 assert(src_second != dst_first, "overlap");
1024 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1025 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1026 // 64-bit
1027 int src_offset = ra_->reg2offset(src_first);
1028 int dst_offset = ra_->reg2offset(dst_first);
1029 if (cbuf) {
1030 MacroAssembler _masm(cbuf);
1031 __ pushq(Address(rsp, src_offset));
1032 __ popq (Address(rsp, dst_offset));
1033 #ifndef PRODUCT
1034 } else {
1035 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1036 "popq [rsp + #%d]",
1037 src_offset, dst_offset);
1038 #endif
1039 }
1040 } else {
1041 // 32-bit
1042 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1043 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1044 // No pushl/popl, so:
1045 int src_offset = ra_->reg2offset(src_first);
1046 int dst_offset = ra_->reg2offset(dst_first);
1047 if (cbuf) {
1048 MacroAssembler _masm(cbuf);
1049 __ movq(Address(rsp, -8), rax);
1050 __ movl(rax, Address(rsp, src_offset));
1051 __ movl(Address(rsp, dst_offset), rax);
1052 __ movq(rax, Address(rsp, -8));
1053 #ifndef PRODUCT
1054 } else {
1055 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1056 "movl rax, [rsp + #%d]\n\t"
1057 "movl [rsp + #%d], rax\n\t"
1058 "movq rax, [rsp - #8]",
1059 src_offset, dst_offset);
1060 #endif
1061 }
1062 }
1063 return 0;
1064 } else if (dst_first_rc == rc_int) {
1065 // mem -> gpr
1066 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1067 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1068 // 64-bit
1069 int offset = ra_->reg2offset(src_first);
1070 if (cbuf) {
1071 MacroAssembler _masm(cbuf);
1072 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1073 #ifndef PRODUCT
1074 } else {
1075 st->print("movq %s, [rsp + #%d]\t# spill",
1076 Matcher::regName[dst_first],
1077 offset);
1078 #endif
1079 }
1080 } else {
1081 // 32-bit
1082 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1083 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1084 int offset = ra_->reg2offset(src_first);
1085 if (cbuf) {
1086 MacroAssembler _masm(cbuf);
1087 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1088 #ifndef PRODUCT
1089 } else {
1090 st->print("movl %s, [rsp + #%d]\t# spill",
1091 Matcher::regName[dst_first],
1092 offset);
1093 #endif
1094 }
1095 }
1096 return 0;
1097 } else if (dst_first_rc == rc_float) {
1098 // mem-> xmm
1099 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1100 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1101 // 64-bit
1102 int offset = ra_->reg2offset(src_first);
1103 if (cbuf) {
1104 MacroAssembler _masm(cbuf);
1105 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1106 #ifndef PRODUCT
1107 } else {
1108 st->print("%s %s, [rsp + #%d]\t# spill",
1109 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1110 Matcher::regName[dst_first],
1111 offset);
1112 #endif
1113 }
1114 } else {
1115 // 32-bit
1116 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1117 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1118 int offset = ra_->reg2offset(src_first);
1119 if (cbuf) {
1120 MacroAssembler _masm(cbuf);
1121 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1122 #ifndef PRODUCT
1123 } else {
1124 st->print("movss %s, [rsp + #%d]\t# spill",
1125 Matcher::regName[dst_first],
1126 offset);
1127 #endif
1128 }
1129 }
1130 return 0;
1131 }
1132 } else if (src_first_rc == rc_int) {
1133 // gpr ->
1134 if (dst_first_rc == rc_stack) {
1135 // gpr -> mem
1136 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1137 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1138 // 64-bit
1139 int offset = ra_->reg2offset(dst_first);
1140 if (cbuf) {
1141 MacroAssembler _masm(cbuf);
1142 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1143 #ifndef PRODUCT
1144 } else {
1145 st->print("movq [rsp + #%d], %s\t# spill",
1146 offset,
1147 Matcher::regName[src_first]);
1148 #endif
1149 }
1150 } else {
1151 // 32-bit
1152 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1153 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1154 int offset = ra_->reg2offset(dst_first);
1155 if (cbuf) {
1156 MacroAssembler _masm(cbuf);
1157 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1158 #ifndef PRODUCT
1159 } else {
1160 st->print("movl [rsp + #%d], %s\t# spill",
1161 offset,
1162 Matcher::regName[src_first]);
1163 #endif
1164 }
1165 }
1166 return 0;
1167 } else if (dst_first_rc == rc_int) {
1168 // gpr -> gpr
1169 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1170 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1171 // 64-bit
1172 if (cbuf) {
1173 MacroAssembler _masm(cbuf);
1174 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1175 as_Register(Matcher::_regEncode[src_first]));
1176 #ifndef PRODUCT
1177 } else {
1178 st->print("movq %s, %s\t# spill",
1179 Matcher::regName[dst_first],
1180 Matcher::regName[src_first]);
1181 #endif
1182 }
1183 return 0;
1184 } else {
1185 // 32-bit
1186 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1187 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1188 if (cbuf) {
1189 MacroAssembler _masm(cbuf);
1190 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1191 as_Register(Matcher::_regEncode[src_first]));
1192 #ifndef PRODUCT
1193 } else {
1194 st->print("movl %s, %s\t# spill",
1195 Matcher::regName[dst_first],
1196 Matcher::regName[src_first]);
1197 #endif
1198 }
1199 return 0;
1200 }
1201 } else if (dst_first_rc == rc_float) {
1202 // gpr -> xmm
1203 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1204 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1205 // 64-bit
1206 if (cbuf) {
1207 MacroAssembler _masm(cbuf);
1208 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1209 #ifndef PRODUCT
1210 } else {
1211 st->print("movdq %s, %s\t# spill",
1212 Matcher::regName[dst_first],
1213 Matcher::regName[src_first]);
1214 #endif
1215 }
1216 } else {
1217 // 32-bit
1218 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1219 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1220 if (cbuf) {
1221 MacroAssembler _masm(cbuf);
1222 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1223 #ifndef PRODUCT
1224 } else {
1225 st->print("movdl %s, %s\t# spill",
1226 Matcher::regName[dst_first],
1227 Matcher::regName[src_first]);
1228 #endif
1229 }
1230 }
1231 return 0;
1232 }
1233 } else if (src_first_rc == rc_float) {
1234 // xmm ->
1235 if (dst_first_rc == rc_stack) {
1236 // xmm -> mem
1237 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1238 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1239 // 64-bit
1240 int offset = ra_->reg2offset(dst_first);
1241 if (cbuf) {
1242 MacroAssembler _masm(cbuf);
1243 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1244 #ifndef PRODUCT
1245 } else {
1246 st->print("movsd [rsp + #%d], %s\t# spill",
1247 offset,
1248 Matcher::regName[src_first]);
1249 #endif
1250 }
1251 } else {
1252 // 32-bit
1253 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1254 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1255 int offset = ra_->reg2offset(dst_first);
1256 if (cbuf) {
1257 MacroAssembler _masm(cbuf);
1258 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1259 #ifndef PRODUCT
1260 } else {
1261 st->print("movss [rsp + #%d], %s\t# spill",
1262 offset,
1263 Matcher::regName[src_first]);
1264 #endif
1265 }
1266 }
1267 return 0;
1268 } else if (dst_first_rc == rc_int) {
1269 // xmm -> gpr
1270 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1271 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1272 // 64-bit
1273 if (cbuf) {
1274 MacroAssembler _masm(cbuf);
1275 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1276 #ifndef PRODUCT
1277 } else {
1278 st->print("movdq %s, %s\t# spill",
1279 Matcher::regName[dst_first],
1280 Matcher::regName[src_first]);
1281 #endif
1282 }
1283 } else {
1284 // 32-bit
1285 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1286 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1287 if (cbuf) {
1288 MacroAssembler _masm(cbuf);
1289 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1290 #ifndef PRODUCT
1291 } else {
1292 st->print("movdl %s, %s\t# spill",
1293 Matcher::regName[dst_first],
1294 Matcher::regName[src_first]);
1295 #endif
1296 }
1297 }
1298 return 0;
1299 } else if (dst_first_rc == rc_float) {
1300 // xmm -> xmm
1301 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1302 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1303 // 64-bit
1304 if (cbuf) {
1305 MacroAssembler _masm(cbuf);
1306 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1307 #ifndef PRODUCT
1308 } else {
1309 st->print("%s %s, %s\t# spill",
1310 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1311 Matcher::regName[dst_first],
1312 Matcher::regName[src_first]);
1313 #endif
1314 }
1315 } else {
1316 // 32-bit
1317 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1318 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1319 if (cbuf) {
1320 MacroAssembler _masm(cbuf);
1321 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1322 #ifndef PRODUCT
1323 } else {
1324 st->print("%s %s, %s\t# spill",
1325 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1326 Matcher::regName[dst_first],
1327 Matcher::regName[src_first]);
1328 #endif
1329 }
1330 }
1331 return 0;
1332 }
1333 }
1335 assert(0," foo ");
1336 Unimplemented();
1337 return 0;
1338 }
1340 #ifndef PRODUCT
1341 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1342 implementation(NULL, ra_, false, st);
1343 }
1344 #endif
1346 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1347 implementation(&cbuf, ra_, false, NULL);
1348 }
1350 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1351 return MachNode::size(ra_);
1352 }
1354 //=============================================================================
1355 #ifndef PRODUCT
1356 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1357 {
1358 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1359 int reg = ra_->get_reg_first(this);
1360 st->print("leaq %s, [rsp + #%d]\t# box lock",
1361 Matcher::regName[reg], offset);
1362 }
1363 #endif
1365 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1366 {
1367 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1368 int reg = ra_->get_encode(this);
1369 if (offset >= 0x80) {
1370 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1371 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1372 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1373 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1374 emit_d32(cbuf, offset);
1375 } else {
1376 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1377 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1378 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1379 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1380 emit_d8(cbuf, offset);
1381 }
1382 }
1384 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1385 {
1386 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1387 return (offset < 0x80) ? 5 : 8; // REX
1388 }
1390 //=============================================================================
1391 #ifndef PRODUCT
1392 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1393 {
1394 if (UseCompressedClassPointers) {
1395 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1396 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1397 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1398 } else {
1399 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1400 "# Inline cache check");
1401 }
1402 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1403 st->print_cr("\tnop\t# nops to align entry point");
1404 }
1405 #endif
1407 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1408 {
1409 MacroAssembler masm(&cbuf);
1410 uint insts_size = cbuf.insts_size();
1411 if (UseCompressedClassPointers) {
1412 masm.load_klass(rscratch1, j_rarg0);
1413 masm.cmpptr(rax, rscratch1);
1414 } else {
1415 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1416 }
1418 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1420 /* WARNING these NOPs are critical so that verified entry point is properly
1421 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1422 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1423 if (OptoBreakpoint) {
1424 // Leave space for int3
1425 nops_cnt -= 1;
1426 }
1427 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1428 if (nops_cnt > 0)
1429 masm.nop(nops_cnt);
1430 }
1432 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1433 {
1434 return MachNode::size(ra_); // too many variables; just compute it
1435 // the hard way
1436 }
1439 //=============================================================================
1440 uint size_exception_handler()
1441 {
1442 // NativeCall instruction size is the same as NativeJump.
1443 // Note that this value is also credited (in output.cpp) to
1444 // the size of the code section.
1445 return NativeJump::instruction_size;
1446 }
1448 // Emit exception handler code.
1449 int emit_exception_handler(CodeBuffer& cbuf)
1450 {
1452 // Note that the code buffer's insts_mark is always relative to insts.
1453 // That's why we must use the macroassembler to generate a handler.
1454 MacroAssembler _masm(&cbuf);
1455 address base =
1456 __ start_a_stub(size_exception_handler());
1457 if (base == NULL) return 0; // CodeBuffer::expand failed
1458 int offset = __ offset();
1459 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1460 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1461 __ end_a_stub();
1462 return offset;
1463 }
1465 uint size_deopt_handler()
1466 {
1467 // three 5 byte instructions
1468 return 15;
1469 }
1471 // Emit deopt handler code.
1472 int emit_deopt_handler(CodeBuffer& cbuf)
1473 {
1475 // Note that the code buffer's insts_mark is always relative to insts.
1476 // That's why we must use the macroassembler to generate a handler.
1477 MacroAssembler _masm(&cbuf);
1478 address base =
1479 __ start_a_stub(size_deopt_handler());
1480 if (base == NULL) return 0; // CodeBuffer::expand failed
1481 int offset = __ offset();
1482 address the_pc = (address) __ pc();
1483 Label next;
1484 // push a "the_pc" on the stack without destroying any registers
1485 // as they all may be live.
1487 // push address of "next"
1488 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
1489 __ bind(next);
1490 // adjust it so it matches "the_pc"
1491 __ subptr(Address(rsp, 0), __ offset() - offset);
1492 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1493 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1494 __ end_a_stub();
1495 return offset;
1496 }
1498 int Matcher::regnum_to_fpu_offset(int regnum)
1499 {
1500 return regnum - 32; // The FP registers are in the second chunk
1501 }
1503 // This is UltraSparc specific, true just means we have fast l2f conversion
1504 const bool Matcher::convL2FSupported(void) {
1505 return true;
1506 }
1508 // Is this branch offset short enough that a short branch can be used?
1509 //
1510 // NOTE: If the platform does not provide any short branch variants, then
1511 // this method should return false for offset 0.
1512 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1513 // The passed offset is relative to address of the branch.
1514 // On 86 a branch displacement is calculated relative to address
1515 // of a next instruction.
1516 offset -= br_size;
1518 // the short version of jmpConUCF2 contains multiple branches,
1519 // making the reach slightly less
1520 if (rule == jmpConUCF2_rule)
1521 return (-126 <= offset && offset <= 125);
1522 return (-128 <= offset && offset <= 127);
1523 }
1525 const bool Matcher::isSimpleConstant64(jlong value) {
1526 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1527 //return value == (int) value; // Cf. storeImmL and immL32.
1529 // Probably always true, even if a temp register is required.
1530 return true;
1531 }
1533 // The ecx parameter to rep stosq for the ClearArray node is in words.
1534 const bool Matcher::init_array_count_is_in_bytes = false;
1536 // Threshold size for cleararray.
1537 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1539 // No additional cost for CMOVL.
1540 const int Matcher::long_cmove_cost() { return 0; }
1542 // No CMOVF/CMOVD with SSE2
1543 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1545 // Should the Matcher clone shifts on addressing modes, expecting them
1546 // to be subsumed into complex addressing expressions or compute them
1547 // into registers? True for Intel but false for most RISCs
1548 const bool Matcher::clone_shift_expressions = true;
1550 // Do we need to mask the count passed to shift instructions or does
1551 // the cpu only look at the lower 5/6 bits anyway?
1552 const bool Matcher::need_masked_shift_count = false;
1554 bool Matcher::narrow_oop_use_complex_address() {
1555 assert(UseCompressedOops, "only for compressed oops code");
1556 return (LogMinObjAlignmentInBytes <= 3);
1557 }
1559 bool Matcher::narrow_klass_use_complex_address() {
1560 assert(UseCompressedClassPointers, "only for compressed klass code");
1561 return (LogKlassAlignmentInBytes <= 3);
1562 }
1564 // Is it better to copy float constants, or load them directly from
1565 // memory? Intel can load a float constant from a direct address,
1566 // requiring no extra registers. Most RISCs will have to materialize
1567 // an address into a register first, so they would do better to copy
1568 // the constant from stack.
1569 const bool Matcher::rematerialize_float_constants = true; // XXX
1571 // If CPU can load and store mis-aligned doubles directly then no
1572 // fixup is needed. Else we split the double into 2 integer pieces
1573 // and move it piece-by-piece. Only happens when passing doubles into
1574 // C code as the Java calling convention forces doubles to be aligned.
1575 const bool Matcher::misaligned_doubles_ok = true;
1577 // No-op on amd64
1578 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1580 // Advertise here if the CPU requires explicit rounding operations to
1581 // implement the UseStrictFP mode.
1582 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1584 // Are floats conerted to double when stored to stack during deoptimization?
1585 // On x64 it is stored without convertion so we can use normal access.
1586 bool Matcher::float_in_double() { return false; }
1588 // Do ints take an entire long register or just half?
1589 const bool Matcher::int_in_long = true;
1591 // Return whether or not this register is ever used as an argument.
1592 // This function is used on startup to build the trampoline stubs in
1593 // generateOptoStub. Registers not mentioned will be killed by the VM
1594 // call in the trampoline, and arguments in those registers not be
1595 // available to the callee.
1596 bool Matcher::can_be_java_arg(int reg)
1597 {
1598 return
1599 reg == RDI_num || reg == RDI_H_num ||
1600 reg == RSI_num || reg == RSI_H_num ||
1601 reg == RDX_num || reg == RDX_H_num ||
1602 reg == RCX_num || reg == RCX_H_num ||
1603 reg == R8_num || reg == R8_H_num ||
1604 reg == R9_num || reg == R9_H_num ||
1605 reg == R12_num || reg == R12_H_num ||
1606 reg == XMM0_num || reg == XMM0b_num ||
1607 reg == XMM1_num || reg == XMM1b_num ||
1608 reg == XMM2_num || reg == XMM2b_num ||
1609 reg == XMM3_num || reg == XMM3b_num ||
1610 reg == XMM4_num || reg == XMM4b_num ||
1611 reg == XMM5_num || reg == XMM5b_num ||
1612 reg == XMM6_num || reg == XMM6b_num ||
1613 reg == XMM7_num || reg == XMM7b_num;
1614 }
1616 bool Matcher::is_spillable_arg(int reg)
1617 {
1618 return can_be_java_arg(reg);
1619 }
1621 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1622 // In 64 bit mode a code which use multiply when
1623 // devisor is constant is faster than hardware
1624 // DIV instruction (it uses MulHiL).
1625 return false;
1626 }
1628 // Register for DIVI projection of divmodI
1629 RegMask Matcher::divI_proj_mask() {
1630 return INT_RAX_REG_mask();
1631 }
1633 // Register for MODI projection of divmodI
1634 RegMask Matcher::modI_proj_mask() {
1635 return INT_RDX_REG_mask();
1636 }
1638 // Register for DIVL projection of divmodL
1639 RegMask Matcher::divL_proj_mask() {
1640 return LONG_RAX_REG_mask();
1641 }
1643 // Register for MODL projection of divmodL
1644 RegMask Matcher::modL_proj_mask() {
1645 return LONG_RDX_REG_mask();
1646 }
1648 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1649 return PTR_RBP_REG_mask();
1650 }
1652 %}
1654 //----------ENCODING BLOCK-----------------------------------------------------
1655 // This block specifies the encoding classes used by the compiler to
1656 // output byte streams. Encoding classes are parameterized macros
1657 // used by Machine Instruction Nodes in order to generate the bit
1658 // encoding of the instruction. Operands specify their base encoding
1659 // interface with the interface keyword. There are currently
1660 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1661 // COND_INTER. REG_INTER causes an operand to generate a function
1662 // which returns its register number when queried. CONST_INTER causes
1663 // an operand to generate a function which returns the value of the
1664 // constant when queried. MEMORY_INTER causes an operand to generate
1665 // four functions which return the Base Register, the Index Register,
1666 // the Scale Value, and the Offset Value of the operand when queried.
1667 // COND_INTER causes an operand to generate six functions which return
1668 // the encoding code (ie - encoding bits for the instruction)
1669 // associated with each basic boolean condition for a conditional
1670 // instruction.
1671 //
1672 // Instructions specify two basic values for encoding. Again, a
1673 // function is available to check if the constant displacement is an
1674 // oop. They use the ins_encode keyword to specify their encoding
1675 // classes (which must be a sequence of enc_class names, and their
1676 // parameters, specified in the encoding block), and they use the
1677 // opcode keyword to specify, in order, their primary, secondary, and
1678 // tertiary opcode. Only the opcode sections which a particular
1679 // instruction needs for encoding need to be specified.
1680 encode %{
1681 // Build emit functions for each basic byte or larger field in the
1682 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1683 // from C++ code in the enc_class source block. Emit functions will
1684 // live in the main source block for now. In future, we can
1685 // generalize this by adding a syntax that specifies the sizes of
1686 // fields in an order, so that the adlc can build the emit functions
1687 // automagically
1689 // Emit primary opcode
1690 enc_class OpcP
1691 %{
1692 emit_opcode(cbuf, $primary);
1693 %}
1695 // Emit secondary opcode
1696 enc_class OpcS
1697 %{
1698 emit_opcode(cbuf, $secondary);
1699 %}
1701 // Emit tertiary opcode
1702 enc_class OpcT
1703 %{
1704 emit_opcode(cbuf, $tertiary);
1705 %}
1707 // Emit opcode directly
1708 enc_class Opcode(immI d8)
1709 %{
1710 emit_opcode(cbuf, $d8$$constant);
1711 %}
1713 // Emit size prefix
1714 enc_class SizePrefix
1715 %{
1716 emit_opcode(cbuf, 0x66);
1717 %}
1719 enc_class reg(rRegI reg)
1720 %{
1721 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1722 %}
1724 enc_class reg_reg(rRegI dst, rRegI src)
1725 %{
1726 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1727 %}
1729 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1730 %{
1731 emit_opcode(cbuf, $opcode$$constant);
1732 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1733 %}
1735 enc_class cdql_enc(no_rax_rdx_RegI div)
1736 %{
1737 // Full implementation of Java idiv and irem; checks for
1738 // special case as described in JVM spec., p.243 & p.271.
1739 //
1740 // normal case special case
1741 //
1742 // input : rax: dividend min_int
1743 // reg: divisor -1
1744 //
1745 // output: rax: quotient (= rax idiv reg) min_int
1746 // rdx: remainder (= rax irem reg) 0
1747 //
1748 // Code sequnce:
1749 //
1750 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1751 // 5: 75 07/08 jne e <normal>
1752 // 7: 33 d2 xor %edx,%edx
1753 // [div >= 8 -> offset + 1]
1754 // [REX_B]
1755 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1756 // c: 74 03/04 je 11 <done>
1757 // 000000000000000e <normal>:
1758 // e: 99 cltd
1759 // [div >= 8 -> offset + 1]
1760 // [REX_B]
1761 // f: f7 f9 idiv $div
1762 // 0000000000000011 <done>:
1764 // cmp $0x80000000,%eax
1765 emit_opcode(cbuf, 0x3d);
1766 emit_d8(cbuf, 0x00);
1767 emit_d8(cbuf, 0x00);
1768 emit_d8(cbuf, 0x00);
1769 emit_d8(cbuf, 0x80);
1771 // jne e <normal>
1772 emit_opcode(cbuf, 0x75);
1773 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1775 // xor %edx,%edx
1776 emit_opcode(cbuf, 0x33);
1777 emit_d8(cbuf, 0xD2);
1779 // cmp $0xffffffffffffffff,%ecx
1780 if ($div$$reg >= 8) {
1781 emit_opcode(cbuf, Assembler::REX_B);
1782 }
1783 emit_opcode(cbuf, 0x83);
1784 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1785 emit_d8(cbuf, 0xFF);
1787 // je 11 <done>
1788 emit_opcode(cbuf, 0x74);
1789 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1791 // <normal>
1792 // cltd
1793 emit_opcode(cbuf, 0x99);
1795 // idivl (note: must be emitted by the user of this rule)
1796 // <done>
1797 %}
1799 enc_class cdqq_enc(no_rax_rdx_RegL div)
1800 %{
1801 // Full implementation of Java ldiv and lrem; checks for
1802 // special case as described in JVM spec., p.243 & p.271.
1803 //
1804 // normal case special case
1805 //
1806 // input : rax: dividend min_long
1807 // reg: divisor -1
1808 //
1809 // output: rax: quotient (= rax idiv reg) min_long
1810 // rdx: remainder (= rax irem reg) 0
1811 //
1812 // Code sequnce:
1813 //
1814 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1815 // 7: 00 00 80
1816 // a: 48 39 d0 cmp %rdx,%rax
1817 // d: 75 08 jne 17 <normal>
1818 // f: 33 d2 xor %edx,%edx
1819 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1820 // 15: 74 05 je 1c <done>
1821 // 0000000000000017 <normal>:
1822 // 17: 48 99 cqto
1823 // 19: 48 f7 f9 idiv $div
1824 // 000000000000001c <done>:
1826 // mov $0x8000000000000000,%rdx
1827 emit_opcode(cbuf, Assembler::REX_W);
1828 emit_opcode(cbuf, 0xBA);
1829 emit_d8(cbuf, 0x00);
1830 emit_d8(cbuf, 0x00);
1831 emit_d8(cbuf, 0x00);
1832 emit_d8(cbuf, 0x00);
1833 emit_d8(cbuf, 0x00);
1834 emit_d8(cbuf, 0x00);
1835 emit_d8(cbuf, 0x00);
1836 emit_d8(cbuf, 0x80);
1838 // cmp %rdx,%rax
1839 emit_opcode(cbuf, Assembler::REX_W);
1840 emit_opcode(cbuf, 0x39);
1841 emit_d8(cbuf, 0xD0);
1843 // jne 17 <normal>
1844 emit_opcode(cbuf, 0x75);
1845 emit_d8(cbuf, 0x08);
1847 // xor %edx,%edx
1848 emit_opcode(cbuf, 0x33);
1849 emit_d8(cbuf, 0xD2);
1851 // cmp $0xffffffffffffffff,$div
1852 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1853 emit_opcode(cbuf, 0x83);
1854 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1855 emit_d8(cbuf, 0xFF);
1857 // je 1e <done>
1858 emit_opcode(cbuf, 0x74);
1859 emit_d8(cbuf, 0x05);
1861 // <normal>
1862 // cqto
1863 emit_opcode(cbuf, Assembler::REX_W);
1864 emit_opcode(cbuf, 0x99);
1866 // idivq (note: must be emitted by the user of this rule)
1867 // <done>
1868 %}
1870 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1871 enc_class OpcSE(immI imm)
1872 %{
1873 // Emit primary opcode and set sign-extend bit
1874 // Check for 8-bit immediate, and set sign extend bit in opcode
1875 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1876 emit_opcode(cbuf, $primary | 0x02);
1877 } else {
1878 // 32-bit immediate
1879 emit_opcode(cbuf, $primary);
1880 }
1881 %}
1883 enc_class OpcSErm(rRegI dst, immI imm)
1884 %{
1885 // OpcSEr/m
1886 int dstenc = $dst$$reg;
1887 if (dstenc >= 8) {
1888 emit_opcode(cbuf, Assembler::REX_B);
1889 dstenc -= 8;
1890 }
1891 // Emit primary opcode and set sign-extend bit
1892 // Check for 8-bit immediate, and set sign extend bit in opcode
1893 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1894 emit_opcode(cbuf, $primary | 0x02);
1895 } else {
1896 // 32-bit immediate
1897 emit_opcode(cbuf, $primary);
1898 }
1899 // Emit r/m byte with secondary opcode, after primary opcode.
1900 emit_rm(cbuf, 0x3, $secondary, dstenc);
1901 %}
1903 enc_class OpcSErm_wide(rRegL dst, immI imm)
1904 %{
1905 // OpcSEr/m
1906 int dstenc = $dst$$reg;
1907 if (dstenc < 8) {
1908 emit_opcode(cbuf, Assembler::REX_W);
1909 } else {
1910 emit_opcode(cbuf, Assembler::REX_WB);
1911 dstenc -= 8;
1912 }
1913 // Emit primary opcode and set sign-extend bit
1914 // Check for 8-bit immediate, and set sign extend bit in opcode
1915 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1916 emit_opcode(cbuf, $primary | 0x02);
1917 } else {
1918 // 32-bit immediate
1919 emit_opcode(cbuf, $primary);
1920 }
1921 // Emit r/m byte with secondary opcode, after primary opcode.
1922 emit_rm(cbuf, 0x3, $secondary, dstenc);
1923 %}
1925 enc_class Con8or32(immI imm)
1926 %{
1927 // Check for 8-bit immediate, and set sign extend bit in opcode
1928 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1929 $$$emit8$imm$$constant;
1930 } else {
1931 // 32-bit immediate
1932 $$$emit32$imm$$constant;
1933 }
1934 %}
1936 enc_class opc2_reg(rRegI dst)
1937 %{
1938 // BSWAP
1939 emit_cc(cbuf, $secondary, $dst$$reg);
1940 %}
1942 enc_class opc3_reg(rRegI dst)
1943 %{
1944 // BSWAP
1945 emit_cc(cbuf, $tertiary, $dst$$reg);
1946 %}
1948 enc_class reg_opc(rRegI div)
1949 %{
1950 // INC, DEC, IDIV, IMOD, JMP indirect, ...
1951 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
1952 %}
1954 enc_class enc_cmov(cmpOp cop)
1955 %{
1956 // CMOV
1957 $$$emit8$primary;
1958 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1959 %}
1961 enc_class enc_PartialSubtypeCheck()
1962 %{
1963 Register Rrdi = as_Register(RDI_enc); // result register
1964 Register Rrax = as_Register(RAX_enc); // super class
1965 Register Rrcx = as_Register(RCX_enc); // killed
1966 Register Rrsi = as_Register(RSI_enc); // sub class
1967 Label miss;
1968 const bool set_cond_codes = true;
1970 MacroAssembler _masm(&cbuf);
1971 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
1972 NULL, &miss,
1973 /*set_cond_codes:*/ true);
1974 if ($primary) {
1975 __ xorptr(Rrdi, Rrdi);
1976 }
1977 __ bind(miss);
1978 %}
1980 enc_class clear_avx %{
1981 debug_only(int off0 = cbuf.insts_size());
1982 if (ra_->C->max_vector_size() > 16) {
1983 // Clear upper bits of YMM registers when current compiled code uses
1984 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1985 MacroAssembler _masm(&cbuf);
1986 __ vzeroupper();
1987 }
1988 debug_only(int off1 = cbuf.insts_size());
1989 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
1990 %}
1992 enc_class Java_To_Runtime(method meth) %{
1993 // No relocation needed
1994 MacroAssembler _masm(&cbuf);
1995 __ mov64(r10, (int64_t) $meth$$method);
1996 __ call(r10);
1997 %}
1999 enc_class Java_To_Interpreter(method meth)
2000 %{
2001 // CALL Java_To_Interpreter
2002 // This is the instruction starting address for relocation info.
2003 cbuf.set_insts_mark();
2004 $$$emit8$primary;
2005 // CALL directly to the runtime
2006 emit_d32_reloc(cbuf,
2007 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2008 runtime_call_Relocation::spec(),
2009 RELOC_DISP32);
2010 %}
2012 enc_class Java_Static_Call(method meth)
2013 %{
2014 // JAVA STATIC CALL
2015 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2016 // determine who we intended to call.
2017 cbuf.set_insts_mark();
2018 $$$emit8$primary;
2020 if (!_method) {
2021 emit_d32_reloc(cbuf,
2022 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2023 runtime_call_Relocation::spec(),
2024 RELOC_DISP32);
2025 } else if (_optimized_virtual) {
2026 emit_d32_reloc(cbuf,
2027 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2028 opt_virtual_call_Relocation::spec(),
2029 RELOC_DISP32);
2030 } else {
2031 emit_d32_reloc(cbuf,
2032 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2033 static_call_Relocation::spec(),
2034 RELOC_DISP32);
2035 }
2036 if (_method) {
2037 // Emit stub for static call.
2038 CompiledStaticCall::emit_to_interp_stub(cbuf);
2039 }
2040 %}
2042 enc_class Java_Dynamic_Call(method meth) %{
2043 MacroAssembler _masm(&cbuf);
2044 __ ic_call((address)$meth$$method);
2045 %}
2047 enc_class Java_Compiled_Call(method meth)
2048 %{
2049 // JAVA COMPILED CALL
2050 int disp = in_bytes(Method:: from_compiled_offset());
2052 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2053 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2055 // callq *disp(%rax)
2056 cbuf.set_insts_mark();
2057 $$$emit8$primary;
2058 if (disp < 0x80) {
2059 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2060 emit_d8(cbuf, disp); // Displacement
2061 } else {
2062 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2063 emit_d32(cbuf, disp); // Displacement
2064 }
2065 %}
2067 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2068 %{
2069 // SAL, SAR, SHR
2070 int dstenc = $dst$$reg;
2071 if (dstenc >= 8) {
2072 emit_opcode(cbuf, Assembler::REX_B);
2073 dstenc -= 8;
2074 }
2075 $$$emit8$primary;
2076 emit_rm(cbuf, 0x3, $secondary, dstenc);
2077 $$$emit8$shift$$constant;
2078 %}
2080 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2081 %{
2082 // SAL, SAR, SHR
2083 int dstenc = $dst$$reg;
2084 if (dstenc < 8) {
2085 emit_opcode(cbuf, Assembler::REX_W);
2086 } else {
2087 emit_opcode(cbuf, Assembler::REX_WB);
2088 dstenc -= 8;
2089 }
2090 $$$emit8$primary;
2091 emit_rm(cbuf, 0x3, $secondary, dstenc);
2092 $$$emit8$shift$$constant;
2093 %}
2095 enc_class load_immI(rRegI dst, immI src)
2096 %{
2097 int dstenc = $dst$$reg;
2098 if (dstenc >= 8) {
2099 emit_opcode(cbuf, Assembler::REX_B);
2100 dstenc -= 8;
2101 }
2102 emit_opcode(cbuf, 0xB8 | dstenc);
2103 $$$emit32$src$$constant;
2104 %}
2106 enc_class load_immL(rRegL dst, immL src)
2107 %{
2108 int dstenc = $dst$$reg;
2109 if (dstenc < 8) {
2110 emit_opcode(cbuf, Assembler::REX_W);
2111 } else {
2112 emit_opcode(cbuf, Assembler::REX_WB);
2113 dstenc -= 8;
2114 }
2115 emit_opcode(cbuf, 0xB8 | dstenc);
2116 emit_d64(cbuf, $src$$constant);
2117 %}
2119 enc_class load_immUL32(rRegL dst, immUL32 src)
2120 %{
2121 // same as load_immI, but this time we care about zeroes in the high word
2122 int dstenc = $dst$$reg;
2123 if (dstenc >= 8) {
2124 emit_opcode(cbuf, Assembler::REX_B);
2125 dstenc -= 8;
2126 }
2127 emit_opcode(cbuf, 0xB8 | dstenc);
2128 $$$emit32$src$$constant;
2129 %}
2131 enc_class load_immL32(rRegL dst, immL32 src)
2132 %{
2133 int dstenc = $dst$$reg;
2134 if (dstenc < 8) {
2135 emit_opcode(cbuf, Assembler::REX_W);
2136 } else {
2137 emit_opcode(cbuf, Assembler::REX_WB);
2138 dstenc -= 8;
2139 }
2140 emit_opcode(cbuf, 0xC7);
2141 emit_rm(cbuf, 0x03, 0x00, dstenc);
2142 $$$emit32$src$$constant;
2143 %}
2145 enc_class load_immP31(rRegP dst, immP32 src)
2146 %{
2147 // same as load_immI, but this time we care about zeroes in the high word
2148 int dstenc = $dst$$reg;
2149 if (dstenc >= 8) {
2150 emit_opcode(cbuf, Assembler::REX_B);
2151 dstenc -= 8;
2152 }
2153 emit_opcode(cbuf, 0xB8 | dstenc);
2154 $$$emit32$src$$constant;
2155 %}
2157 enc_class load_immP(rRegP dst, immP src)
2158 %{
2159 int dstenc = $dst$$reg;
2160 if (dstenc < 8) {
2161 emit_opcode(cbuf, Assembler::REX_W);
2162 } else {
2163 emit_opcode(cbuf, Assembler::REX_WB);
2164 dstenc -= 8;
2165 }
2166 emit_opcode(cbuf, 0xB8 | dstenc);
2167 // This next line should be generated from ADLC
2168 if ($src->constant_reloc() != relocInfo::none) {
2169 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2170 } else {
2171 emit_d64(cbuf, $src$$constant);
2172 }
2173 %}
2175 enc_class Con32(immI src)
2176 %{
2177 // Output immediate
2178 $$$emit32$src$$constant;
2179 %}
2181 enc_class Con32F_as_bits(immF src)
2182 %{
2183 // Output Float immediate bits
2184 jfloat jf = $src$$constant;
2185 jint jf_as_bits = jint_cast(jf);
2186 emit_d32(cbuf, jf_as_bits);
2187 %}
2189 enc_class Con16(immI src)
2190 %{
2191 // Output immediate
2192 $$$emit16$src$$constant;
2193 %}
2195 // How is this different from Con32??? XXX
2196 enc_class Con_d32(immI src)
2197 %{
2198 emit_d32(cbuf,$src$$constant);
2199 %}
2201 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2202 // Output immediate memory reference
2203 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2204 emit_d32(cbuf, 0x00);
2205 %}
2207 enc_class lock_prefix()
2208 %{
2209 if (os::is_MP()) {
2210 emit_opcode(cbuf, 0xF0); // lock
2211 }
2212 %}
2214 enc_class REX_mem(memory mem)
2215 %{
2216 if ($mem$$base >= 8) {
2217 if ($mem$$index < 8) {
2218 emit_opcode(cbuf, Assembler::REX_B);
2219 } else {
2220 emit_opcode(cbuf, Assembler::REX_XB);
2221 }
2222 } else {
2223 if ($mem$$index >= 8) {
2224 emit_opcode(cbuf, Assembler::REX_X);
2225 }
2226 }
2227 %}
2229 enc_class REX_mem_wide(memory mem)
2230 %{
2231 if ($mem$$base >= 8) {
2232 if ($mem$$index < 8) {
2233 emit_opcode(cbuf, Assembler::REX_WB);
2234 } else {
2235 emit_opcode(cbuf, Assembler::REX_WXB);
2236 }
2237 } else {
2238 if ($mem$$index < 8) {
2239 emit_opcode(cbuf, Assembler::REX_W);
2240 } else {
2241 emit_opcode(cbuf, Assembler::REX_WX);
2242 }
2243 }
2244 %}
2246 // for byte regs
2247 enc_class REX_breg(rRegI reg)
2248 %{
2249 if ($reg$$reg >= 4) {
2250 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2251 }
2252 %}
2254 // for byte regs
2255 enc_class REX_reg_breg(rRegI dst, rRegI src)
2256 %{
2257 if ($dst$$reg < 8) {
2258 if ($src$$reg >= 4) {
2259 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2260 }
2261 } else {
2262 if ($src$$reg < 8) {
2263 emit_opcode(cbuf, Assembler::REX_R);
2264 } else {
2265 emit_opcode(cbuf, Assembler::REX_RB);
2266 }
2267 }
2268 %}
2270 // for byte regs
2271 enc_class REX_breg_mem(rRegI reg, memory mem)
2272 %{
2273 if ($reg$$reg < 8) {
2274 if ($mem$$base < 8) {
2275 if ($mem$$index >= 8) {
2276 emit_opcode(cbuf, Assembler::REX_X);
2277 } else if ($reg$$reg >= 4) {
2278 emit_opcode(cbuf, Assembler::REX);
2279 }
2280 } else {
2281 if ($mem$$index < 8) {
2282 emit_opcode(cbuf, Assembler::REX_B);
2283 } else {
2284 emit_opcode(cbuf, Assembler::REX_XB);
2285 }
2286 }
2287 } else {
2288 if ($mem$$base < 8) {
2289 if ($mem$$index < 8) {
2290 emit_opcode(cbuf, Assembler::REX_R);
2291 } else {
2292 emit_opcode(cbuf, Assembler::REX_RX);
2293 }
2294 } else {
2295 if ($mem$$index < 8) {
2296 emit_opcode(cbuf, Assembler::REX_RB);
2297 } else {
2298 emit_opcode(cbuf, Assembler::REX_RXB);
2299 }
2300 }
2301 }
2302 %}
2304 enc_class REX_reg(rRegI reg)
2305 %{
2306 if ($reg$$reg >= 8) {
2307 emit_opcode(cbuf, Assembler::REX_B);
2308 }
2309 %}
2311 enc_class REX_reg_wide(rRegI reg)
2312 %{
2313 if ($reg$$reg < 8) {
2314 emit_opcode(cbuf, Assembler::REX_W);
2315 } else {
2316 emit_opcode(cbuf, Assembler::REX_WB);
2317 }
2318 %}
2320 enc_class REX_reg_reg(rRegI dst, rRegI src)
2321 %{
2322 if ($dst$$reg < 8) {
2323 if ($src$$reg >= 8) {
2324 emit_opcode(cbuf, Assembler::REX_B);
2325 }
2326 } else {
2327 if ($src$$reg < 8) {
2328 emit_opcode(cbuf, Assembler::REX_R);
2329 } else {
2330 emit_opcode(cbuf, Assembler::REX_RB);
2331 }
2332 }
2333 %}
2335 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2336 %{
2337 if ($dst$$reg < 8) {
2338 if ($src$$reg < 8) {
2339 emit_opcode(cbuf, Assembler::REX_W);
2340 } else {
2341 emit_opcode(cbuf, Assembler::REX_WB);
2342 }
2343 } else {
2344 if ($src$$reg < 8) {
2345 emit_opcode(cbuf, Assembler::REX_WR);
2346 } else {
2347 emit_opcode(cbuf, Assembler::REX_WRB);
2348 }
2349 }
2350 %}
2352 enc_class REX_reg_mem(rRegI reg, memory mem)
2353 %{
2354 if ($reg$$reg < 8) {
2355 if ($mem$$base < 8) {
2356 if ($mem$$index >= 8) {
2357 emit_opcode(cbuf, Assembler::REX_X);
2358 }
2359 } else {
2360 if ($mem$$index < 8) {
2361 emit_opcode(cbuf, Assembler::REX_B);
2362 } else {
2363 emit_opcode(cbuf, Assembler::REX_XB);
2364 }
2365 }
2366 } else {
2367 if ($mem$$base < 8) {
2368 if ($mem$$index < 8) {
2369 emit_opcode(cbuf, Assembler::REX_R);
2370 } else {
2371 emit_opcode(cbuf, Assembler::REX_RX);
2372 }
2373 } else {
2374 if ($mem$$index < 8) {
2375 emit_opcode(cbuf, Assembler::REX_RB);
2376 } else {
2377 emit_opcode(cbuf, Assembler::REX_RXB);
2378 }
2379 }
2380 }
2381 %}
2383 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2384 %{
2385 if ($reg$$reg < 8) {
2386 if ($mem$$base < 8) {
2387 if ($mem$$index < 8) {
2388 emit_opcode(cbuf, Assembler::REX_W);
2389 } else {
2390 emit_opcode(cbuf, Assembler::REX_WX);
2391 }
2392 } else {
2393 if ($mem$$index < 8) {
2394 emit_opcode(cbuf, Assembler::REX_WB);
2395 } else {
2396 emit_opcode(cbuf, Assembler::REX_WXB);
2397 }
2398 }
2399 } else {
2400 if ($mem$$base < 8) {
2401 if ($mem$$index < 8) {
2402 emit_opcode(cbuf, Assembler::REX_WR);
2403 } else {
2404 emit_opcode(cbuf, Assembler::REX_WRX);
2405 }
2406 } else {
2407 if ($mem$$index < 8) {
2408 emit_opcode(cbuf, Assembler::REX_WRB);
2409 } else {
2410 emit_opcode(cbuf, Assembler::REX_WRXB);
2411 }
2412 }
2413 }
2414 %}
2416 enc_class reg_mem(rRegI ereg, memory mem)
2417 %{
2418 // High registers handle in encode_RegMem
2419 int reg = $ereg$$reg;
2420 int base = $mem$$base;
2421 int index = $mem$$index;
2422 int scale = $mem$$scale;
2423 int disp = $mem$$disp;
2424 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2426 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2427 %}
2429 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2430 %{
2431 int rm_byte_opcode = $rm_opcode$$constant;
2433 // High registers handle in encode_RegMem
2434 int base = $mem$$base;
2435 int index = $mem$$index;
2436 int scale = $mem$$scale;
2437 int displace = $mem$$disp;
2439 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2440 // working with static
2441 // globals
2442 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2443 disp_reloc);
2444 %}
2446 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2447 %{
2448 int reg_encoding = $dst$$reg;
2449 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2450 int index = 0x04; // 0x04 indicates no index
2451 int scale = 0x00; // 0x00 indicates no scale
2452 int displace = $src1$$constant; // 0x00 indicates no displacement
2453 relocInfo::relocType disp_reloc = relocInfo::none;
2454 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2455 disp_reloc);
2456 %}
2458 enc_class neg_reg(rRegI dst)
2459 %{
2460 int dstenc = $dst$$reg;
2461 if (dstenc >= 8) {
2462 emit_opcode(cbuf, Assembler::REX_B);
2463 dstenc -= 8;
2464 }
2465 // NEG $dst
2466 emit_opcode(cbuf, 0xF7);
2467 emit_rm(cbuf, 0x3, 0x03, dstenc);
2468 %}
2470 enc_class neg_reg_wide(rRegI dst)
2471 %{
2472 int dstenc = $dst$$reg;
2473 if (dstenc < 8) {
2474 emit_opcode(cbuf, Assembler::REX_W);
2475 } else {
2476 emit_opcode(cbuf, Assembler::REX_WB);
2477 dstenc -= 8;
2478 }
2479 // NEG $dst
2480 emit_opcode(cbuf, 0xF7);
2481 emit_rm(cbuf, 0x3, 0x03, dstenc);
2482 %}
2484 enc_class setLT_reg(rRegI dst)
2485 %{
2486 int dstenc = $dst$$reg;
2487 if (dstenc >= 8) {
2488 emit_opcode(cbuf, Assembler::REX_B);
2489 dstenc -= 8;
2490 } else if (dstenc >= 4) {
2491 emit_opcode(cbuf, Assembler::REX);
2492 }
2493 // SETLT $dst
2494 emit_opcode(cbuf, 0x0F);
2495 emit_opcode(cbuf, 0x9C);
2496 emit_rm(cbuf, 0x3, 0x0, dstenc);
2497 %}
2499 enc_class setNZ_reg(rRegI dst)
2500 %{
2501 int dstenc = $dst$$reg;
2502 if (dstenc >= 8) {
2503 emit_opcode(cbuf, Assembler::REX_B);
2504 dstenc -= 8;
2505 } else if (dstenc >= 4) {
2506 emit_opcode(cbuf, Assembler::REX);
2507 }
2508 // SETNZ $dst
2509 emit_opcode(cbuf, 0x0F);
2510 emit_opcode(cbuf, 0x95);
2511 emit_rm(cbuf, 0x3, 0x0, dstenc);
2512 %}
2515 // Compare the lonogs and set -1, 0, or 1 into dst
2516 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2517 %{
2518 int src1enc = $src1$$reg;
2519 int src2enc = $src2$$reg;
2520 int dstenc = $dst$$reg;
2522 // cmpq $src1, $src2
2523 if (src1enc < 8) {
2524 if (src2enc < 8) {
2525 emit_opcode(cbuf, Assembler::REX_W);
2526 } else {
2527 emit_opcode(cbuf, Assembler::REX_WB);
2528 }
2529 } else {
2530 if (src2enc < 8) {
2531 emit_opcode(cbuf, Assembler::REX_WR);
2532 } else {
2533 emit_opcode(cbuf, Assembler::REX_WRB);
2534 }
2535 }
2536 emit_opcode(cbuf, 0x3B);
2537 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2539 // movl $dst, -1
2540 if (dstenc >= 8) {
2541 emit_opcode(cbuf, Assembler::REX_B);
2542 }
2543 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2544 emit_d32(cbuf, -1);
2546 // jl,s done
2547 emit_opcode(cbuf, 0x7C);
2548 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2550 // setne $dst
2551 if (dstenc >= 4) {
2552 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2553 }
2554 emit_opcode(cbuf, 0x0F);
2555 emit_opcode(cbuf, 0x95);
2556 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2558 // movzbl $dst, $dst
2559 if (dstenc >= 4) {
2560 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2561 }
2562 emit_opcode(cbuf, 0x0F);
2563 emit_opcode(cbuf, 0xB6);
2564 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2565 %}
2567 enc_class Push_ResultXD(regD dst) %{
2568 MacroAssembler _masm(&cbuf);
2569 __ fstp_d(Address(rsp, 0));
2570 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2571 __ addptr(rsp, 8);
2572 %}
2574 enc_class Push_SrcXD(regD src) %{
2575 MacroAssembler _masm(&cbuf);
2576 __ subptr(rsp, 8);
2577 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2578 __ fld_d(Address(rsp, 0));
2579 %}
2582 // obj: object to lock
2583 // box: box address (header location) -- killed
2584 // tmp: rax -- killed
2585 // scr: rbx -- killed
2586 //
2587 // What follows is a direct transliteration of fast_lock() and fast_unlock()
2588 // from i486.ad. See that file for comments.
2589 // TODO: where possible switch from movq (r, 0) to movl(r,0) and
2590 // use the shorter encoding. (Movl clears the high-order 32-bits).
2593 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
2594 %{
2595 Register objReg = as_Register((int)$obj$$reg);
2596 Register boxReg = as_Register((int)$box$$reg);
2597 Register tmpReg = as_Register($tmp$$reg);
2598 Register scrReg = as_Register($scr$$reg);
2599 MacroAssembler masm(&cbuf);
2601 // Verify uniqueness of register assignments -- necessary but not sufficient
2602 assert (objReg != boxReg && objReg != tmpReg &&
2603 objReg != scrReg && tmpReg != scrReg, "invariant") ;
2605 if (_counters != NULL) {
2606 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
2607 }
2608 if (EmitSync & 1) {
2609 // Without cast to int32_t a movptr will destroy r10 which is typically obj
2610 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
2611 masm.cmpptr(rsp, (int32_t)NULL_WORD) ;
2612 } else
2613 if (EmitSync & 2) {
2614 Label DONE_LABEL;
2615 if (UseBiasedLocking) {
2616 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
2617 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
2618 }
2619 // QQQ was movl...
2620 masm.movptr(tmpReg, 0x1);
2621 masm.orptr(tmpReg, Address(objReg, 0));
2622 masm.movptr(Address(boxReg, 0), tmpReg);
2623 if (os::is_MP()) {
2624 masm.lock();
2625 }
2626 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
2627 masm.jcc(Assembler::equal, DONE_LABEL);
2629 // Recursive locking
2630 masm.subptr(tmpReg, rsp);
2631 masm.andptr(tmpReg, 7 - os::vm_page_size());
2632 masm.movptr(Address(boxReg, 0), tmpReg);
2634 masm.bind(DONE_LABEL);
2635 masm.nop(); // avoid branch to branch
2636 } else {
2637 Label DONE_LABEL, IsInflated, Egress;
2639 masm.movptr(tmpReg, Address(objReg, 0)) ;
2640 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
2641 masm.jcc (Assembler::notZero, IsInflated) ;
2643 // it's stack-locked, biased or neutral
2644 // TODO: optimize markword triage order to reduce the number of
2645 // conditional branches in the most common cases.
2646 // Beware -- there's a subtle invariant that fetch of the markword
2647 // at [FETCH], below, will never observe a biased encoding (*101b).
2648 // If this invariant is not held we'll suffer exclusion (safety) failure.
2650 if (UseBiasedLocking && !UseOptoBiasInlining) {
2651 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
2652 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
2653 }
2655 // was q will it destroy high?
2656 masm.orl (tmpReg, 1) ;
2657 masm.movptr(Address(boxReg, 0), tmpReg) ;
2658 if (os::is_MP()) { masm.lock(); }
2659 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
2660 if (_counters != NULL) {
2661 masm.cond_inc32(Assembler::equal,
2662 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
2663 }
2664 masm.jcc (Assembler::equal, DONE_LABEL);
2666 // Recursive locking
2667 masm.subptr(tmpReg, rsp);
2668 masm.andptr(tmpReg, 7 - os::vm_page_size());
2669 masm.movptr(Address(boxReg, 0), tmpReg);
2670 if (_counters != NULL) {
2671 masm.cond_inc32(Assembler::equal,
2672 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
2673 }
2674 masm.jmp (DONE_LABEL) ;
2676 masm.bind (IsInflated) ;
2677 // It's inflated
2679 // TODO: someday avoid the ST-before-CAS penalty by
2680 // relocating (deferring) the following ST.
2681 // We should also think about trying a CAS without having
2682 // fetched _owner. If the CAS is successful we may
2683 // avoid an RTO->RTS upgrade on the $line.
2684 // Without cast to int32_t a movptr will destroy r10 which is typically obj
2685 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
2687 masm.mov (boxReg, tmpReg) ;
2688 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
2689 masm.testptr(tmpReg, tmpReg) ;
2690 masm.jcc (Assembler::notZero, DONE_LABEL) ;
2692 // It's inflated and appears unlocked
2693 if (os::is_MP()) { masm.lock(); }
2694 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
2695 // Intentional fall-through into DONE_LABEL ...
2697 masm.bind (DONE_LABEL) ;
2698 masm.nop () ; // avoid jmp to jmp
2699 }
2700 %}
2702 // obj: object to unlock
2703 // box: box address (displaced header location), killed
2704 // RBX: killed tmp; cannot be obj nor box
2705 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
2706 %{
2708 Register objReg = as_Register($obj$$reg);
2709 Register boxReg = as_Register($box$$reg);
2710 Register tmpReg = as_Register($tmp$$reg);
2711 MacroAssembler masm(&cbuf);
2713 if (EmitSync & 4) {
2714 masm.cmpptr(rsp, 0) ;
2715 } else
2716 if (EmitSync & 8) {
2717 Label DONE_LABEL;
2718 if (UseBiasedLocking) {
2719 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2720 }
2722 // Check whether the displaced header is 0
2723 //(=> recursive unlock)
2724 masm.movptr(tmpReg, Address(boxReg, 0));
2725 masm.testptr(tmpReg, tmpReg);
2726 masm.jcc(Assembler::zero, DONE_LABEL);
2728 // If not recursive lock, reset the header to displaced header
2729 if (os::is_MP()) {
2730 masm.lock();
2731 }
2732 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2733 masm.bind(DONE_LABEL);
2734 masm.nop(); // avoid branch to branch
2735 } else {
2736 Label DONE_LABEL, Stacked, CheckSucc ;
2738 if (UseBiasedLocking && !UseOptoBiasInlining) {
2739 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2740 }
2742 masm.movptr(tmpReg, Address(objReg, 0)) ;
2743 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ;
2744 masm.jcc (Assembler::zero, DONE_LABEL) ;
2745 masm.testl (tmpReg, 0x02) ;
2746 masm.jcc (Assembler::zero, Stacked) ;
2748 // It's inflated
2749 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
2750 masm.xorptr(boxReg, r15_thread) ;
2751 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
2752 masm.jcc (Assembler::notZero, DONE_LABEL) ;
2753 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
2754 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
2755 masm.jcc (Assembler::notZero, CheckSucc) ;
2756 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
2757 masm.jmp (DONE_LABEL) ;
2759 if ((EmitSync & 65536) == 0) {
2760 Label LSuccess, LGoSlowPath ;
2761 masm.bind (CheckSucc) ;
2762 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
2763 masm.jcc (Assembler::zero, LGoSlowPath) ;
2765 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
2766 // the explicit ST;MEMBAR combination, but masm doesn't currently support
2767 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
2768 // are all faster when the write buffer is populated.
2769 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
2770 if (os::is_MP()) {
2771 masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
2772 }
2773 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
2774 masm.jcc (Assembler::notZero, LSuccess) ;
2776 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX
2777 if (os::is_MP()) { masm.lock(); }
2778 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2779 masm.jcc (Assembler::notEqual, LSuccess) ;
2780 // Intentional fall-through into slow-path
2782 masm.bind (LGoSlowPath) ;
2783 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
2784 masm.jmp (DONE_LABEL) ;
2786 masm.bind (LSuccess) ;
2787 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success
2788 masm.jmp (DONE_LABEL) ;
2789 }
2791 masm.bind (Stacked) ;
2792 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch
2793 if (os::is_MP()) { masm.lock(); }
2794 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2796 if (EmitSync & 65536) {
2797 masm.bind (CheckSucc) ;
2798 }
2799 masm.bind(DONE_LABEL);
2800 if (EmitSync & 32768) {
2801 masm.nop(); // avoid branch to branch
2802 }
2803 }
2804 %}
2807 enc_class enc_rethrow()
2808 %{
2809 cbuf.set_insts_mark();
2810 emit_opcode(cbuf, 0xE9); // jmp entry
2811 emit_d32_reloc(cbuf,
2812 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2813 runtime_call_Relocation::spec(),
2814 RELOC_DISP32);
2815 %}
2817 %}
2821 //----------FRAME--------------------------------------------------------------
2822 // Definition of frame structure and management information.
2823 //
2824 // S T A C K L A Y O U T Allocators stack-slot number
2825 // | (to get allocators register number
2826 // G Owned by | | v add OptoReg::stack0())
2827 // r CALLER | |
2828 // o | +--------+ pad to even-align allocators stack-slot
2829 // w V | pad0 | numbers; owned by CALLER
2830 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2831 // h ^ | in | 5
2832 // | | args | 4 Holes in incoming args owned by SELF
2833 // | | | | 3
2834 // | | +--------+
2835 // V | | old out| Empty on Intel, window on Sparc
2836 // | old |preserve| Must be even aligned.
2837 // | SP-+--------+----> Matcher::_old_SP, even aligned
2838 // | | in | 3 area for Intel ret address
2839 // Owned by |preserve| Empty on Sparc.
2840 // SELF +--------+
2841 // | | pad2 | 2 pad to align old SP
2842 // | +--------+ 1
2843 // | | locks | 0
2844 // | +--------+----> OptoReg::stack0(), even aligned
2845 // | | pad1 | 11 pad to align new SP
2846 // | +--------+
2847 // | | | 10
2848 // | | spills | 9 spills
2849 // V | | 8 (pad0 slot for callee)
2850 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2851 // ^ | out | 7
2852 // | | args | 6 Holes in outgoing args owned by CALLEE
2853 // Owned by +--------+
2854 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2855 // | new |preserve| Must be even-aligned.
2856 // | SP-+--------+----> Matcher::_new_SP, even aligned
2857 // | | |
2858 //
2859 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2860 // known from SELF's arguments and the Java calling convention.
2861 // Region 6-7 is determined per call site.
2862 // Note 2: If the calling convention leaves holes in the incoming argument
2863 // area, those holes are owned by SELF. Holes in the outgoing area
2864 // are owned by the CALLEE. Holes should not be nessecary in the
2865 // incoming area, as the Java calling convention is completely under
2866 // the control of the AD file. Doubles can be sorted and packed to
2867 // avoid holes. Holes in the outgoing arguments may be nessecary for
2868 // varargs C calling conventions.
2869 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2870 // even aligned with pad0 as needed.
2871 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2872 // region 6-11 is even aligned; it may be padded out more so that
2873 // the region from SP to FP meets the minimum stack alignment.
2874 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2875 // alignment. Region 11, pad1, may be dynamically extended so that
2876 // SP meets the minimum alignment.
2878 frame
2879 %{
2880 // What direction does stack grow in (assumed to be same for C & Java)
2881 stack_direction(TOWARDS_LOW);
2883 // These three registers define part of the calling convention
2884 // between compiled code and the interpreter.
2885 inline_cache_reg(RAX); // Inline Cache Register
2886 interpreter_method_oop_reg(RBX); // Method Oop Register when
2887 // calling interpreter
2889 // Optional: name the operand used by cisc-spilling to access
2890 // [stack_pointer + offset]
2891 cisc_spilling_operand_name(indOffset32);
2893 // Number of stack slots consumed by locking an object
2894 sync_stack_slots(2);
2896 // Compiled code's Frame Pointer
2897 frame_pointer(RSP);
2899 // Interpreter stores its frame pointer in a register which is
2900 // stored to the stack by I2CAdaptors.
2901 // I2CAdaptors convert from interpreted java to compiled java.
2902 interpreter_frame_pointer(RBP);
2904 // Stack alignment requirement
2905 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2907 // Number of stack slots between incoming argument block and the start of
2908 // a new frame. The PROLOG must add this many slots to the stack. The
2909 // EPILOG must remove this many slots. amd64 needs two slots for
2910 // return address.
2911 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2913 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2914 // for calls to C. Supports the var-args backing area for register parms.
2915 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2917 // The after-PROLOG location of the return address. Location of
2918 // return address specifies a type (REG or STACK) and a number
2919 // representing the register number (i.e. - use a register name) or
2920 // stack slot.
2921 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2922 // Otherwise, it is above the locks and verification slot and alignment word
2923 return_addr(STACK - 2 +
2924 round_to((Compile::current()->in_preserve_stack_slots() +
2925 Compile::current()->fixed_slots()),
2926 stack_alignment_in_slots()));
2928 // Body of function which returns an integer array locating
2929 // arguments either in registers or in stack slots. Passed an array
2930 // of ideal registers called "sig" and a "length" count. Stack-slot
2931 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2932 // arguments for a CALLEE. Incoming stack arguments are
2933 // automatically biased by the preserve_stack_slots field above.
2935 calling_convention
2936 %{
2937 // No difference between ingoing/outgoing just pass false
2938 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2939 %}
2941 c_calling_convention
2942 %{
2943 // This is obviously always outgoing
2944 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
2945 %}
2947 // Location of compiled Java return values. Same as C for now.
2948 return_value
2949 %{
2950 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2951 "only return normal values");
2953 static const int lo[Op_RegL + 1] = {
2954 0,
2955 0,
2956 RAX_num, // Op_RegN
2957 RAX_num, // Op_RegI
2958 RAX_num, // Op_RegP
2959 XMM0_num, // Op_RegF
2960 XMM0_num, // Op_RegD
2961 RAX_num // Op_RegL
2962 };
2963 static const int hi[Op_RegL + 1] = {
2964 0,
2965 0,
2966 OptoReg::Bad, // Op_RegN
2967 OptoReg::Bad, // Op_RegI
2968 RAX_H_num, // Op_RegP
2969 OptoReg::Bad, // Op_RegF
2970 XMM0b_num, // Op_RegD
2971 RAX_H_num // Op_RegL
2972 };
2973 // Excluded flags and vector registers.
2974 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type");
2975 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2976 %}
2977 %}
2979 //----------ATTRIBUTES---------------------------------------------------------
2980 //----------Operand Attributes-------------------------------------------------
2981 op_attrib op_cost(0); // Required cost attribute
2983 //----------Instruction Attributes---------------------------------------------
2984 ins_attrib ins_cost(100); // Required cost attribute
2985 ins_attrib ins_size(8); // Required size attribute (in bits)
2986 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2987 // a non-matching short branch variant
2988 // of some long branch?
2989 ins_attrib ins_alignment(1); // Required alignment attribute (must
2990 // be a power of 2) specifies the
2991 // alignment that some part of the
2992 // instruction (not necessarily the
2993 // start) requires. If > 1, a
2994 // compute_padding() function must be
2995 // provided for the instruction
2997 //----------OPERANDS-----------------------------------------------------------
2998 // Operand definitions must precede instruction definitions for correct parsing
2999 // in the ADLC because operands constitute user defined types which are used in
3000 // instruction definitions.
3002 //----------Simple Operands----------------------------------------------------
3003 // Immediate Operands
3004 // Integer Immediate
3005 operand immI()
3006 %{
3007 match(ConI);
3009 op_cost(10);
3010 format %{ %}
3011 interface(CONST_INTER);
3012 %}
3014 // Constant for test vs zero
3015 operand immI0()
3016 %{
3017 predicate(n->get_int() == 0);
3018 match(ConI);
3020 op_cost(0);
3021 format %{ %}
3022 interface(CONST_INTER);
3023 %}
3025 // Constant for increment
3026 operand immI1()
3027 %{
3028 predicate(n->get_int() == 1);
3029 match(ConI);
3031 op_cost(0);
3032 format %{ %}
3033 interface(CONST_INTER);
3034 %}
3036 // Constant for decrement
3037 operand immI_M1()
3038 %{
3039 predicate(n->get_int() == -1);
3040 match(ConI);
3042 op_cost(0);
3043 format %{ %}
3044 interface(CONST_INTER);
3045 %}
3047 // Valid scale values for addressing modes
3048 operand immI2()
3049 %{
3050 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3051 match(ConI);
3053 format %{ %}
3054 interface(CONST_INTER);
3055 %}
3057 operand immI8()
3058 %{
3059 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
3060 match(ConI);
3062 op_cost(5);
3063 format %{ %}
3064 interface(CONST_INTER);
3065 %}
3067 operand immI16()
3068 %{
3069 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3070 match(ConI);
3072 op_cost(10);
3073 format %{ %}
3074 interface(CONST_INTER);
3075 %}
3077 // Constant for long shifts
3078 operand immI_32()
3079 %{
3080 predicate( n->get_int() == 32 );
3081 match(ConI);
3083 op_cost(0);
3084 format %{ %}
3085 interface(CONST_INTER);
3086 %}
3088 // Constant for long shifts
3089 operand immI_64()
3090 %{
3091 predicate( n->get_int() == 64 );
3092 match(ConI);
3094 op_cost(0);
3095 format %{ %}
3096 interface(CONST_INTER);
3097 %}
3099 // Pointer Immediate
3100 operand immP()
3101 %{
3102 match(ConP);
3104 op_cost(10);
3105 format %{ %}
3106 interface(CONST_INTER);
3107 %}
3109 // NULL Pointer Immediate
3110 operand immP0()
3111 %{
3112 predicate(n->get_ptr() == 0);
3113 match(ConP);
3115 op_cost(5);
3116 format %{ %}
3117 interface(CONST_INTER);
3118 %}
3120 // Pointer Immediate
3121 operand immN() %{
3122 match(ConN);
3124 op_cost(10);
3125 format %{ %}
3126 interface(CONST_INTER);
3127 %}
3129 operand immNKlass() %{
3130 match(ConNKlass);
3132 op_cost(10);
3133 format %{ %}
3134 interface(CONST_INTER);
3135 %}
3137 // NULL Pointer Immediate
3138 operand immN0() %{
3139 predicate(n->get_narrowcon() == 0);
3140 match(ConN);
3142 op_cost(5);
3143 format %{ %}
3144 interface(CONST_INTER);
3145 %}
3147 operand immP31()
3148 %{
3149 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3150 && (n->get_ptr() >> 31) == 0);
3151 match(ConP);
3153 op_cost(5);
3154 format %{ %}
3155 interface(CONST_INTER);
3156 %}
3159 // Long Immediate
3160 operand immL()
3161 %{
3162 match(ConL);
3164 op_cost(20);
3165 format %{ %}
3166 interface(CONST_INTER);
3167 %}
3169 // Long Immediate 8-bit
3170 operand immL8()
3171 %{
3172 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3173 match(ConL);
3175 op_cost(5);
3176 format %{ %}
3177 interface(CONST_INTER);
3178 %}
3180 // Long Immediate 32-bit unsigned
3181 operand immUL32()
3182 %{
3183 predicate(n->get_long() == (unsigned int) (n->get_long()));
3184 match(ConL);
3186 op_cost(10);
3187 format %{ %}
3188 interface(CONST_INTER);
3189 %}
3191 // Long Immediate 32-bit signed
3192 operand immL32()
3193 %{
3194 predicate(n->get_long() == (int) (n->get_long()));
3195 match(ConL);
3197 op_cost(15);
3198 format %{ %}
3199 interface(CONST_INTER);
3200 %}
3202 // Long Immediate zero
3203 operand immL0()
3204 %{
3205 predicate(n->get_long() == 0L);
3206 match(ConL);
3208 op_cost(10);
3209 format %{ %}
3210 interface(CONST_INTER);
3211 %}
3213 // Constant for increment
3214 operand immL1()
3215 %{
3216 predicate(n->get_long() == 1);
3217 match(ConL);
3219 format %{ %}
3220 interface(CONST_INTER);
3221 %}
3223 // Constant for decrement
3224 operand immL_M1()
3225 %{
3226 predicate(n->get_long() == -1);
3227 match(ConL);
3229 format %{ %}
3230 interface(CONST_INTER);
3231 %}
3233 // Long Immediate: the value 10
3234 operand immL10()
3235 %{
3236 predicate(n->get_long() == 10);
3237 match(ConL);
3239 format %{ %}
3240 interface(CONST_INTER);
3241 %}
3243 // Long immediate from 0 to 127.
3244 // Used for a shorter form of long mul by 10.
3245 operand immL_127()
3246 %{
3247 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3248 match(ConL);
3250 op_cost(10);
3251 format %{ %}
3252 interface(CONST_INTER);
3253 %}
3255 // Long Immediate: low 32-bit mask
3256 operand immL_32bits()
3257 %{
3258 predicate(n->get_long() == 0xFFFFFFFFL);
3259 match(ConL);
3260 op_cost(20);
3262 format %{ %}
3263 interface(CONST_INTER);
3264 %}
3266 // Float Immediate zero
3267 operand immF0()
3268 %{
3269 predicate(jint_cast(n->getf()) == 0);
3270 match(ConF);
3272 op_cost(5);
3273 format %{ %}
3274 interface(CONST_INTER);
3275 %}
3277 // Float Immediate
3278 operand immF()
3279 %{
3280 match(ConF);
3282 op_cost(15);
3283 format %{ %}
3284 interface(CONST_INTER);
3285 %}
3287 // Double Immediate zero
3288 operand immD0()
3289 %{
3290 predicate(jlong_cast(n->getd()) == 0);
3291 match(ConD);
3293 op_cost(5);
3294 format %{ %}
3295 interface(CONST_INTER);
3296 %}
3298 // Double Immediate
3299 operand immD()
3300 %{
3301 match(ConD);
3303 op_cost(15);
3304 format %{ %}
3305 interface(CONST_INTER);
3306 %}
3308 // Immediates for special shifts (sign extend)
3310 // Constants for increment
3311 operand immI_16()
3312 %{
3313 predicate(n->get_int() == 16);
3314 match(ConI);
3316 format %{ %}
3317 interface(CONST_INTER);
3318 %}
3320 operand immI_24()
3321 %{
3322 predicate(n->get_int() == 24);
3323 match(ConI);
3325 format %{ %}
3326 interface(CONST_INTER);
3327 %}
3329 // Constant for byte-wide masking
3330 operand immI_255()
3331 %{
3332 predicate(n->get_int() == 255);
3333 match(ConI);
3335 format %{ %}
3336 interface(CONST_INTER);
3337 %}
3339 // Constant for short-wide masking
3340 operand immI_65535()
3341 %{
3342 predicate(n->get_int() == 65535);
3343 match(ConI);
3345 format %{ %}
3346 interface(CONST_INTER);
3347 %}
3349 // Constant for byte-wide masking
3350 operand immL_255()
3351 %{
3352 predicate(n->get_long() == 255);
3353 match(ConL);
3355 format %{ %}
3356 interface(CONST_INTER);
3357 %}
3359 // Constant for short-wide masking
3360 operand immL_65535()
3361 %{
3362 predicate(n->get_long() == 65535);
3363 match(ConL);
3365 format %{ %}
3366 interface(CONST_INTER);
3367 %}
3369 // Register Operands
3370 // Integer Register
3371 operand rRegI()
3372 %{
3373 constraint(ALLOC_IN_RC(int_reg));
3374 match(RegI);
3376 match(rax_RegI);
3377 match(rbx_RegI);
3378 match(rcx_RegI);
3379 match(rdx_RegI);
3380 match(rdi_RegI);
3382 format %{ %}
3383 interface(REG_INTER);
3384 %}
3386 // Special Registers
3387 operand rax_RegI()
3388 %{
3389 constraint(ALLOC_IN_RC(int_rax_reg));
3390 match(RegI);
3391 match(rRegI);
3393 format %{ "RAX" %}
3394 interface(REG_INTER);
3395 %}
3397 // Special Registers
3398 operand rbx_RegI()
3399 %{
3400 constraint(ALLOC_IN_RC(int_rbx_reg));
3401 match(RegI);
3402 match(rRegI);
3404 format %{ "RBX" %}
3405 interface(REG_INTER);
3406 %}
3408 operand rcx_RegI()
3409 %{
3410 constraint(ALLOC_IN_RC(int_rcx_reg));
3411 match(RegI);
3412 match(rRegI);
3414 format %{ "RCX" %}
3415 interface(REG_INTER);
3416 %}
3418 operand rdx_RegI()
3419 %{
3420 constraint(ALLOC_IN_RC(int_rdx_reg));
3421 match(RegI);
3422 match(rRegI);
3424 format %{ "RDX" %}
3425 interface(REG_INTER);
3426 %}
3428 operand rdi_RegI()
3429 %{
3430 constraint(ALLOC_IN_RC(int_rdi_reg));
3431 match(RegI);
3432 match(rRegI);
3434 format %{ "RDI" %}
3435 interface(REG_INTER);
3436 %}
3438 operand no_rcx_RegI()
3439 %{
3440 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3441 match(RegI);
3442 match(rax_RegI);
3443 match(rbx_RegI);
3444 match(rdx_RegI);
3445 match(rdi_RegI);
3447 format %{ %}
3448 interface(REG_INTER);
3449 %}
3451 operand no_rax_rdx_RegI()
3452 %{
3453 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3454 match(RegI);
3455 match(rbx_RegI);
3456 match(rcx_RegI);
3457 match(rdi_RegI);
3459 format %{ %}
3460 interface(REG_INTER);
3461 %}
3463 // Pointer Register
3464 operand any_RegP()
3465 %{
3466 constraint(ALLOC_IN_RC(any_reg));
3467 match(RegP);
3468 match(rax_RegP);
3469 match(rbx_RegP);
3470 match(rdi_RegP);
3471 match(rsi_RegP);
3472 match(rbp_RegP);
3473 match(r15_RegP);
3474 match(rRegP);
3476 format %{ %}
3477 interface(REG_INTER);
3478 %}
3480 operand rRegP()
3481 %{
3482 constraint(ALLOC_IN_RC(ptr_reg));
3483 match(RegP);
3484 match(rax_RegP);
3485 match(rbx_RegP);
3486 match(rdi_RegP);
3487 match(rsi_RegP);
3488 match(rbp_RegP);
3489 match(r15_RegP); // See Q&A below about r15_RegP.
3491 format %{ %}
3492 interface(REG_INTER);
3493 %}
3495 operand rRegN() %{
3496 constraint(ALLOC_IN_RC(int_reg));
3497 match(RegN);
3499 format %{ %}
3500 interface(REG_INTER);
3501 %}
3503 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3504 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3505 // It's fine for an instruction input which expects rRegP to match a r15_RegP.
3506 // The output of an instruction is controlled by the allocator, which respects
3507 // register class masks, not match rules. Unless an instruction mentions
3508 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3509 // by the allocator as an input.
3511 operand no_rax_RegP()
3512 %{
3513 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3514 match(RegP);
3515 match(rbx_RegP);
3516 match(rsi_RegP);
3517 match(rdi_RegP);
3519 format %{ %}
3520 interface(REG_INTER);
3521 %}
3523 operand no_rbp_RegP()
3524 %{
3525 constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
3526 match(RegP);
3527 match(rbx_RegP);
3528 match(rsi_RegP);
3529 match(rdi_RegP);
3531 format %{ %}
3532 interface(REG_INTER);
3533 %}
3535 operand no_rax_rbx_RegP()
3536 %{
3537 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3538 match(RegP);
3539 match(rsi_RegP);
3540 match(rdi_RegP);
3542 format %{ %}
3543 interface(REG_INTER);
3544 %}
3546 // Special Registers
3547 // Return a pointer value
3548 operand rax_RegP()
3549 %{
3550 constraint(ALLOC_IN_RC(ptr_rax_reg));
3551 match(RegP);
3552 match(rRegP);
3554 format %{ %}
3555 interface(REG_INTER);
3556 %}
3558 // Special Registers
3559 // Return a compressed pointer value
3560 operand rax_RegN()
3561 %{
3562 constraint(ALLOC_IN_RC(int_rax_reg));
3563 match(RegN);
3564 match(rRegN);
3566 format %{ %}
3567 interface(REG_INTER);
3568 %}
3570 // Used in AtomicAdd
3571 operand rbx_RegP()
3572 %{
3573 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3574 match(RegP);
3575 match(rRegP);
3577 format %{ %}
3578 interface(REG_INTER);
3579 %}
3581 operand rsi_RegP()
3582 %{
3583 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3584 match(RegP);
3585 match(rRegP);
3587 format %{ %}
3588 interface(REG_INTER);
3589 %}
3591 // Used in rep stosq
3592 operand rdi_RegP()
3593 %{
3594 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3595 match(RegP);
3596 match(rRegP);
3598 format %{ %}
3599 interface(REG_INTER);
3600 %}
3602 operand rbp_RegP()
3603 %{
3604 constraint(ALLOC_IN_RC(ptr_rbp_reg));
3605 match(RegP);
3606 match(rRegP);
3608 format %{ %}
3609 interface(REG_INTER);
3610 %}
3612 operand r15_RegP()
3613 %{
3614 constraint(ALLOC_IN_RC(ptr_r15_reg));
3615 match(RegP);
3616 match(rRegP);
3618 format %{ %}
3619 interface(REG_INTER);
3620 %}
3622 operand rRegL()
3623 %{
3624 constraint(ALLOC_IN_RC(long_reg));
3625 match(RegL);
3626 match(rax_RegL);
3627 match(rdx_RegL);
3629 format %{ %}
3630 interface(REG_INTER);
3631 %}
3633 // Special Registers
3634 operand no_rax_rdx_RegL()
3635 %{
3636 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3637 match(RegL);
3638 match(rRegL);
3640 format %{ %}
3641 interface(REG_INTER);
3642 %}
3644 operand no_rax_RegL()
3645 %{
3646 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3647 match(RegL);
3648 match(rRegL);
3649 match(rdx_RegL);
3651 format %{ %}
3652 interface(REG_INTER);
3653 %}
3655 operand no_rcx_RegL()
3656 %{
3657 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3658 match(RegL);
3659 match(rRegL);
3661 format %{ %}
3662 interface(REG_INTER);
3663 %}
3665 operand rax_RegL()
3666 %{
3667 constraint(ALLOC_IN_RC(long_rax_reg));
3668 match(RegL);
3669 match(rRegL);
3671 format %{ "RAX" %}
3672 interface(REG_INTER);
3673 %}
3675 operand rcx_RegL()
3676 %{
3677 constraint(ALLOC_IN_RC(long_rcx_reg));
3678 match(RegL);
3679 match(rRegL);
3681 format %{ %}
3682 interface(REG_INTER);
3683 %}
3685 operand rdx_RegL()
3686 %{
3687 constraint(ALLOC_IN_RC(long_rdx_reg));
3688 match(RegL);
3689 match(rRegL);
3691 format %{ %}
3692 interface(REG_INTER);
3693 %}
3695 // Flags register, used as output of compare instructions
3696 operand rFlagsReg()
3697 %{
3698 constraint(ALLOC_IN_RC(int_flags));
3699 match(RegFlags);
3701 format %{ "RFLAGS" %}
3702 interface(REG_INTER);
3703 %}
3705 // Flags register, used as output of FLOATING POINT compare instructions
3706 operand rFlagsRegU()
3707 %{
3708 constraint(ALLOC_IN_RC(int_flags));
3709 match(RegFlags);
3711 format %{ "RFLAGS_U" %}
3712 interface(REG_INTER);
3713 %}
3715 operand rFlagsRegUCF() %{
3716 constraint(ALLOC_IN_RC(int_flags));
3717 match(RegFlags);
3718 predicate(false);
3720 format %{ "RFLAGS_U_CF" %}
3721 interface(REG_INTER);
3722 %}
3724 // Float register operands
3725 operand regF()
3726 %{
3727 constraint(ALLOC_IN_RC(float_reg));
3728 match(RegF);
3730 format %{ %}
3731 interface(REG_INTER);
3732 %}
3734 // Double register operands
3735 operand regD()
3736 %{
3737 constraint(ALLOC_IN_RC(double_reg));
3738 match(RegD);
3740 format %{ %}
3741 interface(REG_INTER);
3742 %}
3744 //----------Memory Operands----------------------------------------------------
3745 // Direct Memory Operand
3746 // operand direct(immP addr)
3747 // %{
3748 // match(addr);
3750 // format %{ "[$addr]" %}
3751 // interface(MEMORY_INTER) %{
3752 // base(0xFFFFFFFF);
3753 // index(0x4);
3754 // scale(0x0);
3755 // disp($addr);
3756 // %}
3757 // %}
3759 // Indirect Memory Operand
3760 operand indirect(any_RegP reg)
3761 %{
3762 constraint(ALLOC_IN_RC(ptr_reg));
3763 match(reg);
3765 format %{ "[$reg]" %}
3766 interface(MEMORY_INTER) %{
3767 base($reg);
3768 index(0x4);
3769 scale(0x0);
3770 disp(0x0);
3771 %}
3772 %}
3774 // Indirect Memory Plus Short Offset Operand
3775 operand indOffset8(any_RegP reg, immL8 off)
3776 %{
3777 constraint(ALLOC_IN_RC(ptr_reg));
3778 match(AddP reg off);
3780 format %{ "[$reg + $off (8-bit)]" %}
3781 interface(MEMORY_INTER) %{
3782 base($reg);
3783 index(0x4);
3784 scale(0x0);
3785 disp($off);
3786 %}
3787 %}
3789 // Indirect Memory Plus Long Offset Operand
3790 operand indOffset32(any_RegP reg, immL32 off)
3791 %{
3792 constraint(ALLOC_IN_RC(ptr_reg));
3793 match(AddP reg off);
3795 format %{ "[$reg + $off (32-bit)]" %}
3796 interface(MEMORY_INTER) %{
3797 base($reg);
3798 index(0x4);
3799 scale(0x0);
3800 disp($off);
3801 %}
3802 %}
3804 // Indirect Memory Plus Index Register Plus Offset Operand
3805 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3806 %{
3807 constraint(ALLOC_IN_RC(ptr_reg));
3808 match(AddP (AddP reg lreg) off);
3810 op_cost(10);
3811 format %{"[$reg + $off + $lreg]" %}
3812 interface(MEMORY_INTER) %{
3813 base($reg);
3814 index($lreg);
3815 scale(0x0);
3816 disp($off);
3817 %}
3818 %}
3820 // Indirect Memory Plus Index Register Plus Offset Operand
3821 operand indIndex(any_RegP reg, rRegL lreg)
3822 %{
3823 constraint(ALLOC_IN_RC(ptr_reg));
3824 match(AddP reg lreg);
3826 op_cost(10);
3827 format %{"[$reg + $lreg]" %}
3828 interface(MEMORY_INTER) %{
3829 base($reg);
3830 index($lreg);
3831 scale(0x0);
3832 disp(0x0);
3833 %}
3834 %}
3836 // Indirect Memory Times Scale Plus Index Register
3837 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3838 %{
3839 constraint(ALLOC_IN_RC(ptr_reg));
3840 match(AddP reg (LShiftL lreg scale));
3842 op_cost(10);
3843 format %{"[$reg + $lreg << $scale]" %}
3844 interface(MEMORY_INTER) %{
3845 base($reg);
3846 index($lreg);
3847 scale($scale);
3848 disp(0x0);
3849 %}
3850 %}
3852 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3853 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3854 %{
3855 constraint(ALLOC_IN_RC(ptr_reg));
3856 match(AddP (AddP reg (LShiftL lreg scale)) off);
3858 op_cost(10);
3859 format %{"[$reg + $off + $lreg << $scale]" %}
3860 interface(MEMORY_INTER) %{
3861 base($reg);
3862 index($lreg);
3863 scale($scale);
3864 disp($off);
3865 %}
3866 %}
3868 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3869 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3870 %{
3871 constraint(ALLOC_IN_RC(ptr_reg));
3872 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3873 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3875 op_cost(10);
3876 format %{"[$reg + $off + $idx << $scale]" %}
3877 interface(MEMORY_INTER) %{
3878 base($reg);
3879 index($idx);
3880 scale($scale);
3881 disp($off);
3882 %}
3883 %}
3885 // Indirect Narrow Oop Plus Offset Operand
3886 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3887 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3888 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3889 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3890 constraint(ALLOC_IN_RC(ptr_reg));
3891 match(AddP (DecodeN reg) off);
3893 op_cost(10);
3894 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3895 interface(MEMORY_INTER) %{
3896 base(0xc); // R12
3897 index($reg);
3898 scale(0x3);
3899 disp($off);
3900 %}
3901 %}
3903 // Indirect Memory Operand
3904 operand indirectNarrow(rRegN reg)
3905 %{
3906 predicate(Universe::narrow_oop_shift() == 0);
3907 constraint(ALLOC_IN_RC(ptr_reg));
3908 match(DecodeN reg);
3910 format %{ "[$reg]" %}
3911 interface(MEMORY_INTER) %{
3912 base($reg);
3913 index(0x4);
3914 scale(0x0);
3915 disp(0x0);
3916 %}
3917 %}
3919 // Indirect Memory Plus Short Offset Operand
3920 operand indOffset8Narrow(rRegN reg, immL8 off)
3921 %{
3922 predicate(Universe::narrow_oop_shift() == 0);
3923 constraint(ALLOC_IN_RC(ptr_reg));
3924 match(AddP (DecodeN reg) off);
3926 format %{ "[$reg + $off (8-bit)]" %}
3927 interface(MEMORY_INTER) %{
3928 base($reg);
3929 index(0x4);
3930 scale(0x0);
3931 disp($off);
3932 %}
3933 %}
3935 // Indirect Memory Plus Long Offset Operand
3936 operand indOffset32Narrow(rRegN reg, immL32 off)
3937 %{
3938 predicate(Universe::narrow_oop_shift() == 0);
3939 constraint(ALLOC_IN_RC(ptr_reg));
3940 match(AddP (DecodeN reg) off);
3942 format %{ "[$reg + $off (32-bit)]" %}
3943 interface(MEMORY_INTER) %{
3944 base($reg);
3945 index(0x4);
3946 scale(0x0);
3947 disp($off);
3948 %}
3949 %}
3951 // Indirect Memory Plus Index Register Plus Offset Operand
3952 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3953 %{
3954 predicate(Universe::narrow_oop_shift() == 0);
3955 constraint(ALLOC_IN_RC(ptr_reg));
3956 match(AddP (AddP (DecodeN reg) lreg) off);
3958 op_cost(10);
3959 format %{"[$reg + $off + $lreg]" %}
3960 interface(MEMORY_INTER) %{
3961 base($reg);
3962 index($lreg);
3963 scale(0x0);
3964 disp($off);
3965 %}
3966 %}
3968 // Indirect Memory Plus Index Register Plus Offset Operand
3969 operand indIndexNarrow(rRegN reg, rRegL lreg)
3970 %{
3971 predicate(Universe::narrow_oop_shift() == 0);
3972 constraint(ALLOC_IN_RC(ptr_reg));
3973 match(AddP (DecodeN reg) lreg);
3975 op_cost(10);
3976 format %{"[$reg + $lreg]" %}
3977 interface(MEMORY_INTER) %{
3978 base($reg);
3979 index($lreg);
3980 scale(0x0);
3981 disp(0x0);
3982 %}
3983 %}
3985 // Indirect Memory Times Scale Plus Index Register
3986 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
3987 %{
3988 predicate(Universe::narrow_oop_shift() == 0);
3989 constraint(ALLOC_IN_RC(ptr_reg));
3990 match(AddP (DecodeN reg) (LShiftL lreg scale));
3992 op_cost(10);
3993 format %{"[$reg + $lreg << $scale]" %}
3994 interface(MEMORY_INTER) %{
3995 base($reg);
3996 index($lreg);
3997 scale($scale);
3998 disp(0x0);
3999 %}
4000 %}
4002 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4003 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4004 %{
4005 predicate(Universe::narrow_oop_shift() == 0);
4006 constraint(ALLOC_IN_RC(ptr_reg));
4007 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4009 op_cost(10);
4010 format %{"[$reg + $off + $lreg << $scale]" %}
4011 interface(MEMORY_INTER) %{
4012 base($reg);
4013 index($lreg);
4014 scale($scale);
4015 disp($off);
4016 %}
4017 %}
4019 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4020 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4021 %{
4022 constraint(ALLOC_IN_RC(ptr_reg));
4023 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4024 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4026 op_cost(10);
4027 format %{"[$reg + $off + $idx << $scale]" %}
4028 interface(MEMORY_INTER) %{
4029 base($reg);
4030 index($idx);
4031 scale($scale);
4032 disp($off);
4033 %}
4034 %}
4036 //----------Special Memory Operands--------------------------------------------
4037 // Stack Slot Operand - This operand is used for loading and storing temporary
4038 // values on the stack where a match requires a value to
4039 // flow through memory.
4040 operand stackSlotP(sRegP reg)
4041 %{
4042 constraint(ALLOC_IN_RC(stack_slots));
4043 // No match rule because this operand is only generated in matching
4045 format %{ "[$reg]" %}
4046 interface(MEMORY_INTER) %{
4047 base(0x4); // RSP
4048 index(0x4); // No Index
4049 scale(0x0); // No Scale
4050 disp($reg); // Stack Offset
4051 %}
4052 %}
4054 operand stackSlotI(sRegI reg)
4055 %{
4056 constraint(ALLOC_IN_RC(stack_slots));
4057 // No match rule because this operand is only generated in matching
4059 format %{ "[$reg]" %}
4060 interface(MEMORY_INTER) %{
4061 base(0x4); // RSP
4062 index(0x4); // No Index
4063 scale(0x0); // No Scale
4064 disp($reg); // Stack Offset
4065 %}
4066 %}
4068 operand stackSlotF(sRegF reg)
4069 %{
4070 constraint(ALLOC_IN_RC(stack_slots));
4071 // No match rule because this operand is only generated in matching
4073 format %{ "[$reg]" %}
4074 interface(MEMORY_INTER) %{
4075 base(0x4); // RSP
4076 index(0x4); // No Index
4077 scale(0x0); // No Scale
4078 disp($reg); // Stack Offset
4079 %}
4080 %}
4082 operand stackSlotD(sRegD reg)
4083 %{
4084 constraint(ALLOC_IN_RC(stack_slots));
4085 // No match rule because this operand is only generated in matching
4087 format %{ "[$reg]" %}
4088 interface(MEMORY_INTER) %{
4089 base(0x4); // RSP
4090 index(0x4); // No Index
4091 scale(0x0); // No Scale
4092 disp($reg); // Stack Offset
4093 %}
4094 %}
4095 operand stackSlotL(sRegL reg)
4096 %{
4097 constraint(ALLOC_IN_RC(stack_slots));
4098 // No match rule because this operand is only generated in matching
4100 format %{ "[$reg]" %}
4101 interface(MEMORY_INTER) %{
4102 base(0x4); // RSP
4103 index(0x4); // No Index
4104 scale(0x0); // No Scale
4105 disp($reg); // Stack Offset
4106 %}
4107 %}
4109 //----------Conditional Branch Operands----------------------------------------
4110 // Comparison Op - This is the operation of the comparison, and is limited to
4111 // the following set of codes:
4112 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4113 //
4114 // Other attributes of the comparison, such as unsignedness, are specified
4115 // by the comparison instruction that sets a condition code flags register.
4116 // That result is represented by a flags operand whose subtype is appropriate
4117 // to the unsignedness (etc.) of the comparison.
4118 //
4119 // Later, the instruction which matches both the Comparison Op (a Bool) and
4120 // the flags (produced by the Cmp) specifies the coding of the comparison op
4121 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4123 // Comparision Code
4124 operand cmpOp()
4125 %{
4126 match(Bool);
4128 format %{ "" %}
4129 interface(COND_INTER) %{
4130 equal(0x4, "e");
4131 not_equal(0x5, "ne");
4132 less(0xC, "l");
4133 greater_equal(0xD, "ge");
4134 less_equal(0xE, "le");
4135 greater(0xF, "g");
4136 %}
4137 %}
4139 // Comparison Code, unsigned compare. Used by FP also, with
4140 // C2 (unordered) turned into GT or LT already. The other bits
4141 // C0 and C3 are turned into Carry & Zero flags.
4142 operand cmpOpU()
4143 %{
4144 match(Bool);
4146 format %{ "" %}
4147 interface(COND_INTER) %{
4148 equal(0x4, "e");
4149 not_equal(0x5, "ne");
4150 less(0x2, "b");
4151 greater_equal(0x3, "nb");
4152 less_equal(0x6, "be");
4153 greater(0x7, "nbe");
4154 %}
4155 %}
4158 // Floating comparisons that don't require any fixup for the unordered case
4159 operand cmpOpUCF() %{
4160 match(Bool);
4161 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4162 n->as_Bool()->_test._test == BoolTest::ge ||
4163 n->as_Bool()->_test._test == BoolTest::le ||
4164 n->as_Bool()->_test._test == BoolTest::gt);
4165 format %{ "" %}
4166 interface(COND_INTER) %{
4167 equal(0x4, "e");
4168 not_equal(0x5, "ne");
4169 less(0x2, "b");
4170 greater_equal(0x3, "nb");
4171 less_equal(0x6, "be");
4172 greater(0x7, "nbe");
4173 %}
4174 %}
4177 // Floating comparisons that can be fixed up with extra conditional jumps
4178 operand cmpOpUCF2() %{
4179 match(Bool);
4180 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4181 n->as_Bool()->_test._test == BoolTest::eq);
4182 format %{ "" %}
4183 interface(COND_INTER) %{
4184 equal(0x4, "e");
4185 not_equal(0x5, "ne");
4186 less(0x2, "b");
4187 greater_equal(0x3, "nb");
4188 less_equal(0x6, "be");
4189 greater(0x7, "nbe");
4190 %}
4191 %}
4194 //----------OPERAND CLASSES----------------------------------------------------
4195 // Operand Classes are groups of operands that are used as to simplify
4196 // instruction definitions by not requiring the AD writer to specify separate
4197 // instructions for every form of operand when the instruction accepts
4198 // multiple operand types with the same basic encoding and format. The classic
4199 // case of this is memory operands.
4201 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4202 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
4203 indCompressedOopOffset,
4204 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4205 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4206 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow);
4208 //----------PIPELINE-----------------------------------------------------------
4209 // Rules which define the behavior of the target architectures pipeline.
4210 pipeline %{
4212 //----------ATTRIBUTES---------------------------------------------------------
4213 attributes %{
4214 variable_size_instructions; // Fixed size instructions
4215 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4216 instruction_unit_size = 1; // An instruction is 1 bytes long
4217 instruction_fetch_unit_size = 16; // The processor fetches one line
4218 instruction_fetch_units = 1; // of 16 bytes
4220 // List of nop instructions
4221 nops( MachNop );
4222 %}
4224 //----------RESOURCES----------------------------------------------------------
4225 // Resources are the functional units available to the machine
4227 // Generic P2/P3 pipeline
4228 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4229 // 3 instructions decoded per cycle.
4230 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4231 // 3 ALU op, only ALU0 handles mul instructions.
4232 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4233 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4234 BR, FPU,
4235 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4237 //----------PIPELINE DESCRIPTION-----------------------------------------------
4238 // Pipeline Description specifies the stages in the machine's pipeline
4240 // Generic P2/P3 pipeline
4241 pipe_desc(S0, S1, S2, S3, S4, S5);
4243 //----------PIPELINE CLASSES---------------------------------------------------
4244 // Pipeline Classes describe the stages in which input and output are
4245 // referenced by the hardware pipeline.
4247 // Naming convention: ialu or fpu
4248 // Then: _reg
4249 // Then: _reg if there is a 2nd register
4250 // Then: _long if it's a pair of instructions implementing a long
4251 // Then: _fat if it requires the big decoder
4252 // Or: _mem if it requires the big decoder and a memory unit.
4254 // Integer ALU reg operation
4255 pipe_class ialu_reg(rRegI dst)
4256 %{
4257 single_instruction;
4258 dst : S4(write);
4259 dst : S3(read);
4260 DECODE : S0; // any decoder
4261 ALU : S3; // any alu
4262 %}
4264 // Long ALU reg operation
4265 pipe_class ialu_reg_long(rRegL dst)
4266 %{
4267 instruction_count(2);
4268 dst : S4(write);
4269 dst : S3(read);
4270 DECODE : S0(2); // any 2 decoders
4271 ALU : S3(2); // both alus
4272 %}
4274 // Integer ALU reg operation using big decoder
4275 pipe_class ialu_reg_fat(rRegI dst)
4276 %{
4277 single_instruction;
4278 dst : S4(write);
4279 dst : S3(read);
4280 D0 : S0; // big decoder only
4281 ALU : S3; // any alu
4282 %}
4284 // Long ALU reg operation using big decoder
4285 pipe_class ialu_reg_long_fat(rRegL dst)
4286 %{
4287 instruction_count(2);
4288 dst : S4(write);
4289 dst : S3(read);
4290 D0 : S0(2); // big decoder only; twice
4291 ALU : S3(2); // any 2 alus
4292 %}
4294 // Integer ALU reg-reg operation
4295 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4296 %{
4297 single_instruction;
4298 dst : S4(write);
4299 src : S3(read);
4300 DECODE : S0; // any decoder
4301 ALU : S3; // any alu
4302 %}
4304 // Long ALU reg-reg operation
4305 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4306 %{
4307 instruction_count(2);
4308 dst : S4(write);
4309 src : S3(read);
4310 DECODE : S0(2); // any 2 decoders
4311 ALU : S3(2); // both alus
4312 %}
4314 // Integer ALU reg-reg operation
4315 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4316 %{
4317 single_instruction;
4318 dst : S4(write);
4319 src : S3(read);
4320 D0 : S0; // big decoder only
4321 ALU : S3; // any alu
4322 %}
4324 // Long ALU reg-reg operation
4325 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4326 %{
4327 instruction_count(2);
4328 dst : S4(write);
4329 src : S3(read);
4330 D0 : S0(2); // big decoder only; twice
4331 ALU : S3(2); // both alus
4332 %}
4334 // Integer ALU reg-mem operation
4335 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4336 %{
4337 single_instruction;
4338 dst : S5(write);
4339 mem : S3(read);
4340 D0 : S0; // big decoder only
4341 ALU : S4; // any alu
4342 MEM : S3; // any mem
4343 %}
4345 // Integer mem operation (prefetch)
4346 pipe_class ialu_mem(memory mem)
4347 %{
4348 single_instruction;
4349 mem : S3(read);
4350 D0 : S0; // big decoder only
4351 MEM : S3; // any mem
4352 %}
4354 // Integer Store to Memory
4355 pipe_class ialu_mem_reg(memory mem, rRegI src)
4356 %{
4357 single_instruction;
4358 mem : S3(read);
4359 src : S5(read);
4360 D0 : S0; // big decoder only
4361 ALU : S4; // any alu
4362 MEM : S3;
4363 %}
4365 // // Long Store to Memory
4366 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4367 // %{
4368 // instruction_count(2);
4369 // mem : S3(read);
4370 // src : S5(read);
4371 // D0 : S0(2); // big decoder only; twice
4372 // ALU : S4(2); // any 2 alus
4373 // MEM : S3(2); // Both mems
4374 // %}
4376 // Integer Store to Memory
4377 pipe_class ialu_mem_imm(memory mem)
4378 %{
4379 single_instruction;
4380 mem : S3(read);
4381 D0 : S0; // big decoder only
4382 ALU : S4; // any alu
4383 MEM : S3;
4384 %}
4386 // Integer ALU0 reg-reg operation
4387 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4388 %{
4389 single_instruction;
4390 dst : S4(write);
4391 src : S3(read);
4392 D0 : S0; // Big decoder only
4393 ALU0 : S3; // only alu0
4394 %}
4396 // Integer ALU0 reg-mem operation
4397 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4398 %{
4399 single_instruction;
4400 dst : S5(write);
4401 mem : S3(read);
4402 D0 : S0; // big decoder only
4403 ALU0 : S4; // ALU0 only
4404 MEM : S3; // any mem
4405 %}
4407 // Integer ALU reg-reg operation
4408 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4409 %{
4410 single_instruction;
4411 cr : S4(write);
4412 src1 : S3(read);
4413 src2 : S3(read);
4414 DECODE : S0; // any decoder
4415 ALU : S3; // any alu
4416 %}
4418 // Integer ALU reg-imm operation
4419 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4420 %{
4421 single_instruction;
4422 cr : S4(write);
4423 src1 : S3(read);
4424 DECODE : S0; // any decoder
4425 ALU : S3; // any alu
4426 %}
4428 // Integer ALU reg-mem operation
4429 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4430 %{
4431 single_instruction;
4432 cr : S4(write);
4433 src1 : S3(read);
4434 src2 : S3(read);
4435 D0 : S0; // big decoder only
4436 ALU : S4; // any alu
4437 MEM : S3;
4438 %}
4440 // Conditional move reg-reg
4441 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4442 %{
4443 instruction_count(4);
4444 y : S4(read);
4445 q : S3(read);
4446 p : S3(read);
4447 DECODE : S0(4); // any decoder
4448 %}
4450 // Conditional move reg-reg
4451 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4452 %{
4453 single_instruction;
4454 dst : S4(write);
4455 src : S3(read);
4456 cr : S3(read);
4457 DECODE : S0; // any decoder
4458 %}
4460 // Conditional move reg-mem
4461 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4462 %{
4463 single_instruction;
4464 dst : S4(write);
4465 src : S3(read);
4466 cr : S3(read);
4467 DECODE : S0; // any decoder
4468 MEM : S3;
4469 %}
4471 // Conditional move reg-reg long
4472 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4473 %{
4474 single_instruction;
4475 dst : S4(write);
4476 src : S3(read);
4477 cr : S3(read);
4478 DECODE : S0(2); // any 2 decoders
4479 %}
4481 // XXX
4482 // // Conditional move double reg-reg
4483 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4484 // %{
4485 // single_instruction;
4486 // dst : S4(write);
4487 // src : S3(read);
4488 // cr : S3(read);
4489 // DECODE : S0; // any decoder
4490 // %}
4492 // Float reg-reg operation
4493 pipe_class fpu_reg(regD dst)
4494 %{
4495 instruction_count(2);
4496 dst : S3(read);
4497 DECODE : S0(2); // any 2 decoders
4498 FPU : S3;
4499 %}
4501 // Float reg-reg operation
4502 pipe_class fpu_reg_reg(regD dst, regD src)
4503 %{
4504 instruction_count(2);
4505 dst : S4(write);
4506 src : S3(read);
4507 DECODE : S0(2); // any 2 decoders
4508 FPU : S3;
4509 %}
4511 // Float reg-reg operation
4512 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4513 %{
4514 instruction_count(3);
4515 dst : S4(write);
4516 src1 : S3(read);
4517 src2 : S3(read);
4518 DECODE : S0(3); // any 3 decoders
4519 FPU : S3(2);
4520 %}
4522 // Float reg-reg operation
4523 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4524 %{
4525 instruction_count(4);
4526 dst : S4(write);
4527 src1 : S3(read);
4528 src2 : S3(read);
4529 src3 : S3(read);
4530 DECODE : S0(4); // any 3 decoders
4531 FPU : S3(2);
4532 %}
4534 // Float reg-reg operation
4535 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4536 %{
4537 instruction_count(4);
4538 dst : S4(write);
4539 src1 : S3(read);
4540 src2 : S3(read);
4541 src3 : S3(read);
4542 DECODE : S1(3); // any 3 decoders
4543 D0 : S0; // Big decoder only
4544 FPU : S3(2);
4545 MEM : S3;
4546 %}
4548 // Float reg-mem operation
4549 pipe_class fpu_reg_mem(regD dst, memory mem)
4550 %{
4551 instruction_count(2);
4552 dst : S5(write);
4553 mem : S3(read);
4554 D0 : S0; // big decoder only
4555 DECODE : S1; // any decoder for FPU POP
4556 FPU : S4;
4557 MEM : S3; // any mem
4558 %}
4560 // Float reg-mem operation
4561 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4562 %{
4563 instruction_count(3);
4564 dst : S5(write);
4565 src1 : S3(read);
4566 mem : S3(read);
4567 D0 : S0; // big decoder only
4568 DECODE : S1(2); // any decoder for FPU POP
4569 FPU : S4;
4570 MEM : S3; // any mem
4571 %}
4573 // Float mem-reg operation
4574 pipe_class fpu_mem_reg(memory mem, regD src)
4575 %{
4576 instruction_count(2);
4577 src : S5(read);
4578 mem : S3(read);
4579 DECODE : S0; // any decoder for FPU PUSH
4580 D0 : S1; // big decoder only
4581 FPU : S4;
4582 MEM : S3; // any mem
4583 %}
4585 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4586 %{
4587 instruction_count(3);
4588 src1 : S3(read);
4589 src2 : S3(read);
4590 mem : S3(read);
4591 DECODE : S0(2); // any decoder for FPU PUSH
4592 D0 : S1; // big decoder only
4593 FPU : S4;
4594 MEM : S3; // any mem
4595 %}
4597 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4598 %{
4599 instruction_count(3);
4600 src1 : S3(read);
4601 src2 : S3(read);
4602 mem : S4(read);
4603 DECODE : S0; // any decoder for FPU PUSH
4604 D0 : S0(2); // big decoder only
4605 FPU : S4;
4606 MEM : S3(2); // any mem
4607 %}
4609 pipe_class fpu_mem_mem(memory dst, memory src1)
4610 %{
4611 instruction_count(2);
4612 src1 : S3(read);
4613 dst : S4(read);
4614 D0 : S0(2); // big decoder only
4615 MEM : S3(2); // any mem
4616 %}
4618 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4619 %{
4620 instruction_count(3);
4621 src1 : S3(read);
4622 src2 : S3(read);
4623 dst : S4(read);
4624 D0 : S0(3); // big decoder only
4625 FPU : S4;
4626 MEM : S3(3); // any mem
4627 %}
4629 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4630 %{
4631 instruction_count(3);
4632 src1 : S4(read);
4633 mem : S4(read);
4634 DECODE : S0; // any decoder for FPU PUSH
4635 D0 : S0(2); // big decoder only
4636 FPU : S4;
4637 MEM : S3(2); // any mem
4638 %}
4640 // Float load constant
4641 pipe_class fpu_reg_con(regD dst)
4642 %{
4643 instruction_count(2);
4644 dst : S5(write);
4645 D0 : S0; // big decoder only for the load
4646 DECODE : S1; // any decoder for FPU POP
4647 FPU : S4;
4648 MEM : S3; // any mem
4649 %}
4651 // Float load constant
4652 pipe_class fpu_reg_reg_con(regD dst, regD src)
4653 %{
4654 instruction_count(3);
4655 dst : S5(write);
4656 src : S3(read);
4657 D0 : S0; // big decoder only for the load
4658 DECODE : S1(2); // any decoder for FPU POP
4659 FPU : S4;
4660 MEM : S3; // any mem
4661 %}
4663 // UnConditional branch
4664 pipe_class pipe_jmp(label labl)
4665 %{
4666 single_instruction;
4667 BR : S3;
4668 %}
4670 // Conditional branch
4671 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4672 %{
4673 single_instruction;
4674 cr : S1(read);
4675 BR : S3;
4676 %}
4678 // Allocation idiom
4679 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4680 %{
4681 instruction_count(1); force_serialization;
4682 fixed_latency(6);
4683 heap_ptr : S3(read);
4684 DECODE : S0(3);
4685 D0 : S2;
4686 MEM : S3;
4687 ALU : S3(2);
4688 dst : S5(write);
4689 BR : S5;
4690 %}
4692 // Generic big/slow expanded idiom
4693 pipe_class pipe_slow()
4694 %{
4695 instruction_count(10); multiple_bundles; force_serialization;
4696 fixed_latency(100);
4697 D0 : S0(2);
4698 MEM : S3(2);
4699 %}
4701 // The real do-nothing guy
4702 pipe_class empty()
4703 %{
4704 instruction_count(0);
4705 %}
4707 // Define the class for the Nop node
4708 define
4709 %{
4710 MachNop = empty;
4711 %}
4713 %}
4715 //----------INSTRUCTIONS-------------------------------------------------------
4716 //
4717 // match -- States which machine-independent subtree may be replaced
4718 // by this instruction.
4719 // ins_cost -- The estimated cost of this instruction is used by instruction
4720 // selection to identify a minimum cost tree of machine
4721 // instructions that matches a tree of machine-independent
4722 // instructions.
4723 // format -- A string providing the disassembly for this instruction.
4724 // The value of an instruction's operand may be inserted
4725 // by referring to it with a '$' prefix.
4726 // opcode -- Three instruction opcodes may be provided. These are referred
4727 // to within an encode class as $primary, $secondary, and $tertiary
4728 // rrspectively. The primary opcode is commonly used to
4729 // indicate the type of machine instruction, while secondary
4730 // and tertiary are often used for prefix options or addressing
4731 // modes.
4732 // ins_encode -- A list of encode classes with parameters. The encode class
4733 // name must have been defined in an 'enc_class' specification
4734 // in the encode section of the architecture description.
4737 //----------Load/Store/Move Instructions---------------------------------------
4738 //----------Load Instructions--------------------------------------------------
4740 // Load Byte (8 bit signed)
4741 instruct loadB(rRegI dst, memory mem)
4742 %{
4743 match(Set dst (LoadB mem));
4745 ins_cost(125);
4746 format %{ "movsbl $dst, $mem\t# byte" %}
4748 ins_encode %{
4749 __ movsbl($dst$$Register, $mem$$Address);
4750 %}
4752 ins_pipe(ialu_reg_mem);
4753 %}
4755 // Load Byte (8 bit signed) into Long Register
4756 instruct loadB2L(rRegL dst, memory mem)
4757 %{
4758 match(Set dst (ConvI2L (LoadB mem)));
4760 ins_cost(125);
4761 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4763 ins_encode %{
4764 __ movsbq($dst$$Register, $mem$$Address);
4765 %}
4767 ins_pipe(ialu_reg_mem);
4768 %}
4770 // Load Unsigned Byte (8 bit UNsigned)
4771 instruct loadUB(rRegI dst, memory mem)
4772 %{
4773 match(Set dst (LoadUB mem));
4775 ins_cost(125);
4776 format %{ "movzbl $dst, $mem\t# ubyte" %}
4778 ins_encode %{
4779 __ movzbl($dst$$Register, $mem$$Address);
4780 %}
4782 ins_pipe(ialu_reg_mem);
4783 %}
4785 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4786 instruct loadUB2L(rRegL dst, memory mem)
4787 %{
4788 match(Set dst (ConvI2L (LoadUB mem)));
4790 ins_cost(125);
4791 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4793 ins_encode %{
4794 __ movzbq($dst$$Register, $mem$$Address);
4795 %}
4797 ins_pipe(ialu_reg_mem);
4798 %}
4800 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register
4801 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{
4802 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4803 effect(KILL cr);
4805 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t"
4806 "andl $dst, $mask" %}
4807 ins_encode %{
4808 Register Rdst = $dst$$Register;
4809 __ movzbq(Rdst, $mem$$Address);
4810 __ andl(Rdst, $mask$$constant);
4811 %}
4812 ins_pipe(ialu_reg_mem);
4813 %}
4815 // Load Short (16 bit signed)
4816 instruct loadS(rRegI dst, memory mem)
4817 %{
4818 match(Set dst (LoadS mem));
4820 ins_cost(125);
4821 format %{ "movswl $dst, $mem\t# short" %}
4823 ins_encode %{
4824 __ movswl($dst$$Register, $mem$$Address);
4825 %}
4827 ins_pipe(ialu_reg_mem);
4828 %}
4830 // Load Short (16 bit signed) to Byte (8 bit signed)
4831 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4832 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4834 ins_cost(125);
4835 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4836 ins_encode %{
4837 __ movsbl($dst$$Register, $mem$$Address);
4838 %}
4839 ins_pipe(ialu_reg_mem);
4840 %}
4842 // Load Short (16 bit signed) into Long Register
4843 instruct loadS2L(rRegL dst, memory mem)
4844 %{
4845 match(Set dst (ConvI2L (LoadS mem)));
4847 ins_cost(125);
4848 format %{ "movswq $dst, $mem\t# short -> long" %}
4850 ins_encode %{
4851 __ movswq($dst$$Register, $mem$$Address);
4852 %}
4854 ins_pipe(ialu_reg_mem);
4855 %}
4857 // Load Unsigned Short/Char (16 bit UNsigned)
4858 instruct loadUS(rRegI dst, memory mem)
4859 %{
4860 match(Set dst (LoadUS mem));
4862 ins_cost(125);
4863 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4865 ins_encode %{
4866 __ movzwl($dst$$Register, $mem$$Address);
4867 %}
4869 ins_pipe(ialu_reg_mem);
4870 %}
4872 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4873 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4874 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4876 ins_cost(125);
4877 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4878 ins_encode %{
4879 __ movsbl($dst$$Register, $mem$$Address);
4880 %}
4881 ins_pipe(ialu_reg_mem);
4882 %}
4884 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4885 instruct loadUS2L(rRegL dst, memory mem)
4886 %{
4887 match(Set dst (ConvI2L (LoadUS mem)));
4889 ins_cost(125);
4890 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4892 ins_encode %{
4893 __ movzwq($dst$$Register, $mem$$Address);
4894 %}
4896 ins_pipe(ialu_reg_mem);
4897 %}
4899 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4900 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4901 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4903 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4904 ins_encode %{
4905 __ movzbq($dst$$Register, $mem$$Address);
4906 %}
4907 ins_pipe(ialu_reg_mem);
4908 %}
4910 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register
4911 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{
4912 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4913 effect(KILL cr);
4915 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t"
4916 "andl $dst, $mask" %}
4917 ins_encode %{
4918 Register Rdst = $dst$$Register;
4919 __ movzwq(Rdst, $mem$$Address);
4920 __ andl(Rdst, $mask$$constant);
4921 %}
4922 ins_pipe(ialu_reg_mem);
4923 %}
4925 // Load Integer
4926 instruct loadI(rRegI dst, memory mem)
4927 %{
4928 match(Set dst (LoadI mem));
4930 ins_cost(125);
4931 format %{ "movl $dst, $mem\t# int" %}
4933 ins_encode %{
4934 __ movl($dst$$Register, $mem$$Address);
4935 %}
4937 ins_pipe(ialu_reg_mem);
4938 %}
4940 // Load Integer (32 bit signed) to Byte (8 bit signed)
4941 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4942 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4944 ins_cost(125);
4945 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4946 ins_encode %{
4947 __ movsbl($dst$$Register, $mem$$Address);
4948 %}
4949 ins_pipe(ialu_reg_mem);
4950 %}
4952 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4953 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4954 match(Set dst (AndI (LoadI mem) mask));
4956 ins_cost(125);
4957 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4958 ins_encode %{
4959 __ movzbl($dst$$Register, $mem$$Address);
4960 %}
4961 ins_pipe(ialu_reg_mem);
4962 %}
4964 // Load Integer (32 bit signed) to Short (16 bit signed)
4965 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4966 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4968 ins_cost(125);
4969 format %{ "movswl $dst, $mem\t# int -> short" %}
4970 ins_encode %{
4971 __ movswl($dst$$Register, $mem$$Address);
4972 %}
4973 ins_pipe(ialu_reg_mem);
4974 %}
4976 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
4977 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
4978 match(Set dst (AndI (LoadI mem) mask));
4980 ins_cost(125);
4981 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
4982 ins_encode %{
4983 __ movzwl($dst$$Register, $mem$$Address);
4984 %}
4985 ins_pipe(ialu_reg_mem);
4986 %}
4988 // Load Integer into Long Register
4989 instruct loadI2L(rRegL dst, memory mem)
4990 %{
4991 match(Set dst (ConvI2L (LoadI mem)));
4993 ins_cost(125);
4994 format %{ "movslq $dst, $mem\t# int -> long" %}
4996 ins_encode %{
4997 __ movslq($dst$$Register, $mem$$Address);
4998 %}
5000 ins_pipe(ialu_reg_mem);
5001 %}
5003 // Load Integer with mask 0xFF into Long Register
5004 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5005 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5007 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
5008 ins_encode %{
5009 __ movzbq($dst$$Register, $mem$$Address);
5010 %}
5011 ins_pipe(ialu_reg_mem);
5012 %}
5014 // Load Integer with mask 0xFFFF into Long Register
5015 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5016 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5018 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5019 ins_encode %{
5020 __ movzwq($dst$$Register, $mem$$Address);
5021 %}
5022 ins_pipe(ialu_reg_mem);
5023 %}
5025 // Load Integer with a 32-bit mask into Long Register
5026 instruct loadI2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5027 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5028 effect(KILL cr);
5030 format %{ "movl $dst, $mem\t# int & 32-bit mask -> long\n\t"
5031 "andl $dst, $mask" %}
5032 ins_encode %{
5033 Register Rdst = $dst$$Register;
5034 __ movl(Rdst, $mem$$Address);
5035 __ andl(Rdst, $mask$$constant);
5036 %}
5037 ins_pipe(ialu_reg_mem);
5038 %}
5040 // Load Unsigned Integer into Long Register
5041 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5042 %{
5043 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5045 ins_cost(125);
5046 format %{ "movl $dst, $mem\t# uint -> long" %}
5048 ins_encode %{
5049 __ movl($dst$$Register, $mem$$Address);
5050 %}
5052 ins_pipe(ialu_reg_mem);
5053 %}
5055 // Load Long
5056 instruct loadL(rRegL dst, memory mem)
5057 %{
5058 match(Set dst (LoadL mem));
5060 ins_cost(125);
5061 format %{ "movq $dst, $mem\t# long" %}
5063 ins_encode %{
5064 __ movq($dst$$Register, $mem$$Address);
5065 %}
5067 ins_pipe(ialu_reg_mem); // XXX
5068 %}
5070 // Load Range
5071 instruct loadRange(rRegI dst, memory mem)
5072 %{
5073 match(Set dst (LoadRange mem));
5075 ins_cost(125); // XXX
5076 format %{ "movl $dst, $mem\t# range" %}
5077 opcode(0x8B);
5078 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5079 ins_pipe(ialu_reg_mem);
5080 %}
5082 // Load Pointer
5083 instruct loadP(rRegP dst, memory mem)
5084 %{
5085 match(Set dst (LoadP mem));
5087 ins_cost(125); // XXX
5088 format %{ "movq $dst, $mem\t# ptr" %}
5089 opcode(0x8B);
5090 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5091 ins_pipe(ialu_reg_mem); // XXX
5092 %}
5094 // Load Compressed Pointer
5095 instruct loadN(rRegN dst, memory mem)
5096 %{
5097 match(Set dst (LoadN mem));
5099 ins_cost(125); // XXX
5100 format %{ "movl $dst, $mem\t# compressed ptr" %}
5101 ins_encode %{
5102 __ movl($dst$$Register, $mem$$Address);
5103 %}
5104 ins_pipe(ialu_reg_mem); // XXX
5105 %}
5108 // Load Klass Pointer
5109 instruct loadKlass(rRegP dst, memory mem)
5110 %{
5111 match(Set dst (LoadKlass mem));
5113 ins_cost(125); // XXX
5114 format %{ "movq $dst, $mem\t# class" %}
5115 opcode(0x8B);
5116 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5117 ins_pipe(ialu_reg_mem); // XXX
5118 %}
5120 // Load narrow Klass Pointer
5121 instruct loadNKlass(rRegN dst, memory mem)
5122 %{
5123 match(Set dst (LoadNKlass mem));
5125 ins_cost(125); // XXX
5126 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5127 ins_encode %{
5128 __ movl($dst$$Register, $mem$$Address);
5129 %}
5130 ins_pipe(ialu_reg_mem); // XXX
5131 %}
5133 // Load Float
5134 instruct loadF(regF dst, memory mem)
5135 %{
5136 match(Set dst (LoadF mem));
5138 ins_cost(145); // XXX
5139 format %{ "movss $dst, $mem\t# float" %}
5140 ins_encode %{
5141 __ movflt($dst$$XMMRegister, $mem$$Address);
5142 %}
5143 ins_pipe(pipe_slow); // XXX
5144 %}
5146 // Load Double
5147 instruct loadD_partial(regD dst, memory mem)
5148 %{
5149 predicate(!UseXmmLoadAndClearUpper);
5150 match(Set dst (LoadD mem));
5152 ins_cost(145); // XXX
5153 format %{ "movlpd $dst, $mem\t# double" %}
5154 ins_encode %{
5155 __ movdbl($dst$$XMMRegister, $mem$$Address);
5156 %}
5157 ins_pipe(pipe_slow); // XXX
5158 %}
5160 instruct loadD(regD dst, memory mem)
5161 %{
5162 predicate(UseXmmLoadAndClearUpper);
5163 match(Set dst (LoadD mem));
5165 ins_cost(145); // XXX
5166 format %{ "movsd $dst, $mem\t# double" %}
5167 ins_encode %{
5168 __ movdbl($dst$$XMMRegister, $mem$$Address);
5169 %}
5170 ins_pipe(pipe_slow); // XXX
5171 %}
5173 // Load Effective Address
5174 instruct leaP8(rRegP dst, indOffset8 mem)
5175 %{
5176 match(Set dst mem);
5178 ins_cost(110); // XXX
5179 format %{ "leaq $dst, $mem\t# ptr 8" %}
5180 opcode(0x8D);
5181 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5182 ins_pipe(ialu_reg_reg_fat);
5183 %}
5185 instruct leaP32(rRegP dst, indOffset32 mem)
5186 %{
5187 match(Set dst mem);
5189 ins_cost(110);
5190 format %{ "leaq $dst, $mem\t# ptr 32" %}
5191 opcode(0x8D);
5192 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5193 ins_pipe(ialu_reg_reg_fat);
5194 %}
5196 // instruct leaPIdx(rRegP dst, indIndex mem)
5197 // %{
5198 // match(Set dst mem);
5200 // ins_cost(110);
5201 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5202 // opcode(0x8D);
5203 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5204 // ins_pipe(ialu_reg_reg_fat);
5205 // %}
5207 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5208 %{
5209 match(Set dst mem);
5211 ins_cost(110);
5212 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5213 opcode(0x8D);
5214 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5215 ins_pipe(ialu_reg_reg_fat);
5216 %}
5218 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5219 %{
5220 match(Set dst mem);
5222 ins_cost(110);
5223 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5224 opcode(0x8D);
5225 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5226 ins_pipe(ialu_reg_reg_fat);
5227 %}
5229 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5230 %{
5231 match(Set dst mem);
5233 ins_cost(110);
5234 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5235 opcode(0x8D);
5236 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5237 ins_pipe(ialu_reg_reg_fat);
5238 %}
5240 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5241 %{
5242 match(Set dst mem);
5244 ins_cost(110);
5245 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5246 opcode(0x8D);
5247 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5248 ins_pipe(ialu_reg_reg_fat);
5249 %}
5251 // Load Effective Address which uses Narrow (32-bits) oop
5252 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5253 %{
5254 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5255 match(Set dst mem);
5257 ins_cost(110);
5258 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5259 opcode(0x8D);
5260 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5261 ins_pipe(ialu_reg_reg_fat);
5262 %}
5264 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5265 %{
5266 predicate(Universe::narrow_oop_shift() == 0);
5267 match(Set dst mem);
5269 ins_cost(110); // XXX
5270 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5271 opcode(0x8D);
5272 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5273 ins_pipe(ialu_reg_reg_fat);
5274 %}
5276 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5277 %{
5278 predicate(Universe::narrow_oop_shift() == 0);
5279 match(Set dst mem);
5281 ins_cost(110);
5282 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5283 opcode(0x8D);
5284 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5285 ins_pipe(ialu_reg_reg_fat);
5286 %}
5288 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5289 %{
5290 predicate(Universe::narrow_oop_shift() == 0);
5291 match(Set dst mem);
5293 ins_cost(110);
5294 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5295 opcode(0x8D);
5296 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5297 ins_pipe(ialu_reg_reg_fat);
5298 %}
5300 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5301 %{
5302 predicate(Universe::narrow_oop_shift() == 0);
5303 match(Set dst mem);
5305 ins_cost(110);
5306 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5307 opcode(0x8D);
5308 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5309 ins_pipe(ialu_reg_reg_fat);
5310 %}
5312 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5313 %{
5314 predicate(Universe::narrow_oop_shift() == 0);
5315 match(Set dst mem);
5317 ins_cost(110);
5318 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5319 opcode(0x8D);
5320 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5321 ins_pipe(ialu_reg_reg_fat);
5322 %}
5324 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5325 %{
5326 predicate(Universe::narrow_oop_shift() == 0);
5327 match(Set dst mem);
5329 ins_cost(110);
5330 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5331 opcode(0x8D);
5332 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5333 ins_pipe(ialu_reg_reg_fat);
5334 %}
5336 instruct loadConI(rRegI dst, immI src)
5337 %{
5338 match(Set dst src);
5340 format %{ "movl $dst, $src\t# int" %}
5341 ins_encode(load_immI(dst, src));
5342 ins_pipe(ialu_reg_fat); // XXX
5343 %}
5345 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5346 %{
5347 match(Set dst src);
5348 effect(KILL cr);
5350 ins_cost(50);
5351 format %{ "xorl $dst, $dst\t# int" %}
5352 opcode(0x33); /* + rd */
5353 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5354 ins_pipe(ialu_reg);
5355 %}
5357 instruct loadConL(rRegL dst, immL src)
5358 %{
5359 match(Set dst src);
5361 ins_cost(150);
5362 format %{ "movq $dst, $src\t# long" %}
5363 ins_encode(load_immL(dst, src));
5364 ins_pipe(ialu_reg);
5365 %}
5367 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5368 %{
5369 match(Set dst src);
5370 effect(KILL cr);
5372 ins_cost(50);
5373 format %{ "xorl $dst, $dst\t# long" %}
5374 opcode(0x33); /* + rd */
5375 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5376 ins_pipe(ialu_reg); // XXX
5377 %}
5379 instruct loadConUL32(rRegL dst, immUL32 src)
5380 %{
5381 match(Set dst src);
5383 ins_cost(60);
5384 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5385 ins_encode(load_immUL32(dst, src));
5386 ins_pipe(ialu_reg);
5387 %}
5389 instruct loadConL32(rRegL dst, immL32 src)
5390 %{
5391 match(Set dst src);
5393 ins_cost(70);
5394 format %{ "movq $dst, $src\t# long (32-bit)" %}
5395 ins_encode(load_immL32(dst, src));
5396 ins_pipe(ialu_reg);
5397 %}
5399 instruct loadConP(rRegP dst, immP con) %{
5400 match(Set dst con);
5402 format %{ "movq $dst, $con\t# ptr" %}
5403 ins_encode(load_immP(dst, con));
5404 ins_pipe(ialu_reg_fat); // XXX
5405 %}
5407 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5408 %{
5409 match(Set dst src);
5410 effect(KILL cr);
5412 ins_cost(50);
5413 format %{ "xorl $dst, $dst\t# ptr" %}
5414 opcode(0x33); /* + rd */
5415 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5416 ins_pipe(ialu_reg);
5417 %}
5419 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5420 %{
5421 match(Set dst src);
5422 effect(KILL cr);
5424 ins_cost(60);
5425 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5426 ins_encode(load_immP31(dst, src));
5427 ins_pipe(ialu_reg);
5428 %}
5430 instruct loadConF(regF dst, immF con) %{
5431 match(Set dst con);
5432 ins_cost(125);
5433 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5434 ins_encode %{
5435 __ movflt($dst$$XMMRegister, $constantaddress($con));
5436 %}
5437 ins_pipe(pipe_slow);
5438 %}
5440 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5441 match(Set dst src);
5442 effect(KILL cr);
5443 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5444 ins_encode %{
5445 __ xorq($dst$$Register, $dst$$Register);
5446 %}
5447 ins_pipe(ialu_reg);
5448 %}
5450 instruct loadConN(rRegN dst, immN src) %{
5451 match(Set dst src);
5453 ins_cost(125);
5454 format %{ "movl $dst, $src\t# compressed ptr" %}
5455 ins_encode %{
5456 address con = (address)$src$$constant;
5457 if (con == NULL) {
5458 ShouldNotReachHere();
5459 } else {
5460 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5461 }
5462 %}
5463 ins_pipe(ialu_reg_fat); // XXX
5464 %}
5466 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5467 match(Set dst src);
5469 ins_cost(125);
5470 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5471 ins_encode %{
5472 address con = (address)$src$$constant;
5473 if (con == NULL) {
5474 ShouldNotReachHere();
5475 } else {
5476 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5477 }
5478 %}
5479 ins_pipe(ialu_reg_fat); // XXX
5480 %}
5482 instruct loadConF0(regF dst, immF0 src)
5483 %{
5484 match(Set dst src);
5485 ins_cost(100);
5487 format %{ "xorps $dst, $dst\t# float 0.0" %}
5488 ins_encode %{
5489 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5490 %}
5491 ins_pipe(pipe_slow);
5492 %}
5494 // Use the same format since predicate() can not be used here.
5495 instruct loadConD(regD dst, immD con) %{
5496 match(Set dst con);
5497 ins_cost(125);
5498 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5499 ins_encode %{
5500 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5501 %}
5502 ins_pipe(pipe_slow);
5503 %}
5505 instruct loadConD0(regD dst, immD0 src)
5506 %{
5507 match(Set dst src);
5508 ins_cost(100);
5510 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5511 ins_encode %{
5512 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5513 %}
5514 ins_pipe(pipe_slow);
5515 %}
5517 instruct loadSSI(rRegI dst, stackSlotI src)
5518 %{
5519 match(Set dst src);
5521 ins_cost(125);
5522 format %{ "movl $dst, $src\t# int stk" %}
5523 opcode(0x8B);
5524 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5525 ins_pipe(ialu_reg_mem);
5526 %}
5528 instruct loadSSL(rRegL dst, stackSlotL src)
5529 %{
5530 match(Set dst src);
5532 ins_cost(125);
5533 format %{ "movq $dst, $src\t# long stk" %}
5534 opcode(0x8B);
5535 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5536 ins_pipe(ialu_reg_mem);
5537 %}
5539 instruct loadSSP(rRegP dst, stackSlotP src)
5540 %{
5541 match(Set dst src);
5543 ins_cost(125);
5544 format %{ "movq $dst, $src\t# ptr stk" %}
5545 opcode(0x8B);
5546 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5547 ins_pipe(ialu_reg_mem);
5548 %}
5550 instruct loadSSF(regF dst, stackSlotF src)
5551 %{
5552 match(Set dst src);
5554 ins_cost(125);
5555 format %{ "movss $dst, $src\t# float stk" %}
5556 ins_encode %{
5557 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5558 %}
5559 ins_pipe(pipe_slow); // XXX
5560 %}
5562 // Use the same format since predicate() can not be used here.
5563 instruct loadSSD(regD dst, stackSlotD src)
5564 %{
5565 match(Set dst src);
5567 ins_cost(125);
5568 format %{ "movsd $dst, $src\t# double stk" %}
5569 ins_encode %{
5570 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5571 %}
5572 ins_pipe(pipe_slow); // XXX
5573 %}
5575 // Prefetch instructions.
5576 // Must be safe to execute with invalid address (cannot fault).
5578 instruct prefetchr( memory mem ) %{
5579 predicate(ReadPrefetchInstr==3);
5580 match(PrefetchRead mem);
5581 ins_cost(125);
5583 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
5584 ins_encode %{
5585 __ prefetchr($mem$$Address);
5586 %}
5587 ins_pipe(ialu_mem);
5588 %}
5590 instruct prefetchrNTA( memory mem ) %{
5591 predicate(ReadPrefetchInstr==0);
5592 match(PrefetchRead mem);
5593 ins_cost(125);
5595 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
5596 ins_encode %{
5597 __ prefetchnta($mem$$Address);
5598 %}
5599 ins_pipe(ialu_mem);
5600 %}
5602 instruct prefetchrT0( memory mem ) %{
5603 predicate(ReadPrefetchInstr==1);
5604 match(PrefetchRead mem);
5605 ins_cost(125);
5607 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
5608 ins_encode %{
5609 __ prefetcht0($mem$$Address);
5610 %}
5611 ins_pipe(ialu_mem);
5612 %}
5614 instruct prefetchrT2( memory mem ) %{
5615 predicate(ReadPrefetchInstr==2);
5616 match(PrefetchRead mem);
5617 ins_cost(125);
5619 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
5620 ins_encode %{
5621 __ prefetcht2($mem$$Address);
5622 %}
5623 ins_pipe(ialu_mem);
5624 %}
5626 instruct prefetchwNTA( memory mem ) %{
5627 match(PrefetchWrite mem);
5628 ins_cost(125);
5630 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
5631 ins_encode %{
5632 __ prefetchnta($mem$$Address);
5633 %}
5634 ins_pipe(ialu_mem);
5635 %}
5637 // Prefetch instructions for allocation.
5639 instruct prefetchAlloc( memory mem ) %{
5640 predicate(AllocatePrefetchInstr==3);
5641 match(PrefetchAllocation mem);
5642 ins_cost(125);
5644 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5645 ins_encode %{
5646 __ prefetchw($mem$$Address);
5647 %}
5648 ins_pipe(ialu_mem);
5649 %}
5651 instruct prefetchAllocNTA( memory mem ) %{
5652 predicate(AllocatePrefetchInstr==0);
5653 match(PrefetchAllocation mem);
5654 ins_cost(125);
5656 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5657 ins_encode %{
5658 __ prefetchnta($mem$$Address);
5659 %}
5660 ins_pipe(ialu_mem);
5661 %}
5663 instruct prefetchAllocT0( memory mem ) %{
5664 predicate(AllocatePrefetchInstr==1);
5665 match(PrefetchAllocation mem);
5666 ins_cost(125);
5668 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5669 ins_encode %{
5670 __ prefetcht0($mem$$Address);
5671 %}
5672 ins_pipe(ialu_mem);
5673 %}
5675 instruct prefetchAllocT2( memory mem ) %{
5676 predicate(AllocatePrefetchInstr==2);
5677 match(PrefetchAllocation mem);
5678 ins_cost(125);
5680 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5681 ins_encode %{
5682 __ prefetcht2($mem$$Address);
5683 %}
5684 ins_pipe(ialu_mem);
5685 %}
5687 //----------Store Instructions-------------------------------------------------
5689 // Store Byte
5690 instruct storeB(memory mem, rRegI src)
5691 %{
5692 match(Set mem (StoreB mem src));
5694 ins_cost(125); // XXX
5695 format %{ "movb $mem, $src\t# byte" %}
5696 opcode(0x88);
5697 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5698 ins_pipe(ialu_mem_reg);
5699 %}
5701 // Store Char/Short
5702 instruct storeC(memory mem, rRegI src)
5703 %{
5704 match(Set mem (StoreC mem src));
5706 ins_cost(125); // XXX
5707 format %{ "movw $mem, $src\t# char/short" %}
5708 opcode(0x89);
5709 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5710 ins_pipe(ialu_mem_reg);
5711 %}
5713 // Store Integer
5714 instruct storeI(memory mem, rRegI src)
5715 %{
5716 match(Set mem (StoreI mem src));
5718 ins_cost(125); // XXX
5719 format %{ "movl $mem, $src\t# int" %}
5720 opcode(0x89);
5721 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5722 ins_pipe(ialu_mem_reg);
5723 %}
5725 // Store Long
5726 instruct storeL(memory mem, rRegL src)
5727 %{
5728 match(Set mem (StoreL mem src));
5730 ins_cost(125); // XXX
5731 format %{ "movq $mem, $src\t# long" %}
5732 opcode(0x89);
5733 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5734 ins_pipe(ialu_mem_reg); // XXX
5735 %}
5737 // Store Pointer
5738 instruct storeP(memory mem, any_RegP src)
5739 %{
5740 match(Set mem (StoreP mem src));
5742 ins_cost(125); // XXX
5743 format %{ "movq $mem, $src\t# ptr" %}
5744 opcode(0x89);
5745 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5746 ins_pipe(ialu_mem_reg);
5747 %}
5749 instruct storeImmP0(memory mem, immP0 zero)
5750 %{
5751 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5752 match(Set mem (StoreP mem zero));
5754 ins_cost(125); // XXX
5755 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5756 ins_encode %{
5757 __ movq($mem$$Address, r12);
5758 %}
5759 ins_pipe(ialu_mem_reg);
5760 %}
5762 // Store NULL Pointer, mark word, or other simple pointer constant.
5763 instruct storeImmP(memory mem, immP31 src)
5764 %{
5765 match(Set mem (StoreP mem src));
5767 ins_cost(150); // XXX
5768 format %{ "movq $mem, $src\t# ptr" %}
5769 opcode(0xC7); /* C7 /0 */
5770 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5771 ins_pipe(ialu_mem_imm);
5772 %}
5774 // Store Compressed Pointer
5775 instruct storeN(memory mem, rRegN src)
5776 %{
5777 match(Set mem (StoreN mem src));
5779 ins_cost(125); // XXX
5780 format %{ "movl $mem, $src\t# compressed ptr" %}
5781 ins_encode %{
5782 __ movl($mem$$Address, $src$$Register);
5783 %}
5784 ins_pipe(ialu_mem_reg);
5785 %}
5787 instruct storeNKlass(memory mem, rRegN src)
5788 %{
5789 match(Set mem (StoreNKlass mem src));
5791 ins_cost(125); // XXX
5792 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5793 ins_encode %{
5794 __ movl($mem$$Address, $src$$Register);
5795 %}
5796 ins_pipe(ialu_mem_reg);
5797 %}
5799 instruct storeImmN0(memory mem, immN0 zero)
5800 %{
5801 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
5802 match(Set mem (StoreN mem zero));
5804 ins_cost(125); // XXX
5805 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5806 ins_encode %{
5807 __ movl($mem$$Address, r12);
5808 %}
5809 ins_pipe(ialu_mem_reg);
5810 %}
5812 instruct storeImmN(memory mem, immN src)
5813 %{
5814 match(Set mem (StoreN mem src));
5816 ins_cost(150); // XXX
5817 format %{ "movl $mem, $src\t# compressed ptr" %}
5818 ins_encode %{
5819 address con = (address)$src$$constant;
5820 if (con == NULL) {
5821 __ movl($mem$$Address, (int32_t)0);
5822 } else {
5823 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5824 }
5825 %}
5826 ins_pipe(ialu_mem_imm);
5827 %}
5829 instruct storeImmNKlass(memory mem, immNKlass src)
5830 %{
5831 match(Set mem (StoreNKlass mem src));
5833 ins_cost(150); // XXX
5834 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5835 ins_encode %{
5836 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
5837 %}
5838 ins_pipe(ialu_mem_imm);
5839 %}
5841 // Store Integer Immediate
5842 instruct storeImmI0(memory mem, immI0 zero)
5843 %{
5844 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5845 match(Set mem (StoreI mem zero));
5847 ins_cost(125); // XXX
5848 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5849 ins_encode %{
5850 __ movl($mem$$Address, r12);
5851 %}
5852 ins_pipe(ialu_mem_reg);
5853 %}
5855 instruct storeImmI(memory mem, immI src)
5856 %{
5857 match(Set mem (StoreI mem src));
5859 ins_cost(150);
5860 format %{ "movl $mem, $src\t# int" %}
5861 opcode(0xC7); /* C7 /0 */
5862 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5863 ins_pipe(ialu_mem_imm);
5864 %}
5866 // Store Long Immediate
5867 instruct storeImmL0(memory mem, immL0 zero)
5868 %{
5869 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5870 match(Set mem (StoreL mem zero));
5872 ins_cost(125); // XXX
5873 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5874 ins_encode %{
5875 __ movq($mem$$Address, r12);
5876 %}
5877 ins_pipe(ialu_mem_reg);
5878 %}
5880 instruct storeImmL(memory mem, immL32 src)
5881 %{
5882 match(Set mem (StoreL mem src));
5884 ins_cost(150);
5885 format %{ "movq $mem, $src\t# long" %}
5886 opcode(0xC7); /* C7 /0 */
5887 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5888 ins_pipe(ialu_mem_imm);
5889 %}
5891 // Store Short/Char Immediate
5892 instruct storeImmC0(memory mem, immI0 zero)
5893 %{
5894 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5895 match(Set mem (StoreC mem zero));
5897 ins_cost(125); // XXX
5898 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5899 ins_encode %{
5900 __ movw($mem$$Address, r12);
5901 %}
5902 ins_pipe(ialu_mem_reg);
5903 %}
5905 instruct storeImmI16(memory mem, immI16 src)
5906 %{
5907 predicate(UseStoreImmI16);
5908 match(Set mem (StoreC mem src));
5910 ins_cost(150);
5911 format %{ "movw $mem, $src\t# short/char" %}
5912 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
5913 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
5914 ins_pipe(ialu_mem_imm);
5915 %}
5917 // Store Byte Immediate
5918 instruct storeImmB0(memory mem, immI0 zero)
5919 %{
5920 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5921 match(Set mem (StoreB mem zero));
5923 ins_cost(125); // XXX
5924 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5925 ins_encode %{
5926 __ movb($mem$$Address, r12);
5927 %}
5928 ins_pipe(ialu_mem_reg);
5929 %}
5931 instruct storeImmB(memory mem, immI8 src)
5932 %{
5933 match(Set mem (StoreB mem src));
5935 ins_cost(150); // XXX
5936 format %{ "movb $mem, $src\t# byte" %}
5937 opcode(0xC6); /* C6 /0 */
5938 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5939 ins_pipe(ialu_mem_imm);
5940 %}
5942 // Store CMS card-mark Immediate
5943 instruct storeImmCM0_reg(memory mem, immI0 zero)
5944 %{
5945 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5946 match(Set mem (StoreCM mem zero));
5948 ins_cost(125); // XXX
5949 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
5950 ins_encode %{
5951 __ movb($mem$$Address, r12);
5952 %}
5953 ins_pipe(ialu_mem_reg);
5954 %}
5956 instruct storeImmCM0(memory mem, immI0 src)
5957 %{
5958 match(Set mem (StoreCM mem src));
5960 ins_cost(150); // XXX
5961 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
5962 opcode(0xC6); /* C6 /0 */
5963 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5964 ins_pipe(ialu_mem_imm);
5965 %}
5967 // Store Float
5968 instruct storeF(memory mem, regF src)
5969 %{
5970 match(Set mem (StoreF mem src));
5972 ins_cost(95); // XXX
5973 format %{ "movss $mem, $src\t# float" %}
5974 ins_encode %{
5975 __ movflt($mem$$Address, $src$$XMMRegister);
5976 %}
5977 ins_pipe(pipe_slow); // XXX
5978 %}
5980 // Store immediate Float value (it is faster than store from XMM register)
5981 instruct storeF0(memory mem, immF0 zero)
5982 %{
5983 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5984 match(Set mem (StoreF mem zero));
5986 ins_cost(25); // XXX
5987 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
5988 ins_encode %{
5989 __ movl($mem$$Address, r12);
5990 %}
5991 ins_pipe(ialu_mem_reg);
5992 %}
5994 instruct storeF_imm(memory mem, immF src)
5995 %{
5996 match(Set mem (StoreF mem src));
5998 ins_cost(50);
5999 format %{ "movl $mem, $src\t# float" %}
6000 opcode(0xC7); /* C7 /0 */
6001 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6002 ins_pipe(ialu_mem_imm);
6003 %}
6005 // Store Double
6006 instruct storeD(memory mem, regD src)
6007 %{
6008 match(Set mem (StoreD mem src));
6010 ins_cost(95); // XXX
6011 format %{ "movsd $mem, $src\t# double" %}
6012 ins_encode %{
6013 __ movdbl($mem$$Address, $src$$XMMRegister);
6014 %}
6015 ins_pipe(pipe_slow); // XXX
6016 %}
6018 // Store immediate double 0.0 (it is faster than store from XMM register)
6019 instruct storeD0_imm(memory mem, immD0 src)
6020 %{
6021 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
6022 match(Set mem (StoreD mem src));
6024 ins_cost(50);
6025 format %{ "movq $mem, $src\t# double 0." %}
6026 opcode(0xC7); /* C7 /0 */
6027 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6028 ins_pipe(ialu_mem_imm);
6029 %}
6031 instruct storeD0(memory mem, immD0 zero)
6032 %{
6033 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6034 match(Set mem (StoreD mem zero));
6036 ins_cost(25); // XXX
6037 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
6038 ins_encode %{
6039 __ movq($mem$$Address, r12);
6040 %}
6041 ins_pipe(ialu_mem_reg);
6042 %}
6044 instruct storeSSI(stackSlotI dst, rRegI src)
6045 %{
6046 match(Set dst src);
6048 ins_cost(100);
6049 format %{ "movl $dst, $src\t# int stk" %}
6050 opcode(0x89);
6051 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6052 ins_pipe( ialu_mem_reg );
6053 %}
6055 instruct storeSSL(stackSlotL dst, rRegL src)
6056 %{
6057 match(Set dst src);
6059 ins_cost(100);
6060 format %{ "movq $dst, $src\t# long stk" %}
6061 opcode(0x89);
6062 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6063 ins_pipe(ialu_mem_reg);
6064 %}
6066 instruct storeSSP(stackSlotP dst, rRegP src)
6067 %{
6068 match(Set dst src);
6070 ins_cost(100);
6071 format %{ "movq $dst, $src\t# ptr stk" %}
6072 opcode(0x89);
6073 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6074 ins_pipe(ialu_mem_reg);
6075 %}
6077 instruct storeSSF(stackSlotF dst, regF src)
6078 %{
6079 match(Set dst src);
6081 ins_cost(95); // XXX
6082 format %{ "movss $dst, $src\t# float stk" %}
6083 ins_encode %{
6084 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6085 %}
6086 ins_pipe(pipe_slow); // XXX
6087 %}
6089 instruct storeSSD(stackSlotD dst, regD src)
6090 %{
6091 match(Set dst src);
6093 ins_cost(95); // XXX
6094 format %{ "movsd $dst, $src\t# double stk" %}
6095 ins_encode %{
6096 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6097 %}
6098 ins_pipe(pipe_slow); // XXX
6099 %}
6101 //----------BSWAP Instructions-------------------------------------------------
6102 instruct bytes_reverse_int(rRegI dst) %{
6103 match(Set dst (ReverseBytesI dst));
6105 format %{ "bswapl $dst" %}
6106 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6107 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6108 ins_pipe( ialu_reg );
6109 %}
6111 instruct bytes_reverse_long(rRegL dst) %{
6112 match(Set dst (ReverseBytesL dst));
6114 format %{ "bswapq $dst" %}
6115 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6116 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6117 ins_pipe( ialu_reg);
6118 %}
6120 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6121 match(Set dst (ReverseBytesUS dst));
6122 effect(KILL cr);
6124 format %{ "bswapl $dst\n\t"
6125 "shrl $dst,16\n\t" %}
6126 ins_encode %{
6127 __ bswapl($dst$$Register);
6128 __ shrl($dst$$Register, 16);
6129 %}
6130 ins_pipe( ialu_reg );
6131 %}
6133 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6134 match(Set dst (ReverseBytesS dst));
6135 effect(KILL cr);
6137 format %{ "bswapl $dst\n\t"
6138 "sar $dst,16\n\t" %}
6139 ins_encode %{
6140 __ bswapl($dst$$Register);
6141 __ sarl($dst$$Register, 16);
6142 %}
6143 ins_pipe( ialu_reg );
6144 %}
6146 //---------- Zeros Count Instructions ------------------------------------------
6148 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6149 predicate(UseCountLeadingZerosInstruction);
6150 match(Set dst (CountLeadingZerosI src));
6151 effect(KILL cr);
6153 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6154 ins_encode %{
6155 __ lzcntl($dst$$Register, $src$$Register);
6156 %}
6157 ins_pipe(ialu_reg);
6158 %}
6160 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6161 predicate(!UseCountLeadingZerosInstruction);
6162 match(Set dst (CountLeadingZerosI src));
6163 effect(KILL cr);
6165 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6166 "jnz skip\n\t"
6167 "movl $dst, -1\n"
6168 "skip:\n\t"
6169 "negl $dst\n\t"
6170 "addl $dst, 31" %}
6171 ins_encode %{
6172 Register Rdst = $dst$$Register;
6173 Register Rsrc = $src$$Register;
6174 Label skip;
6175 __ bsrl(Rdst, Rsrc);
6176 __ jccb(Assembler::notZero, skip);
6177 __ movl(Rdst, -1);
6178 __ bind(skip);
6179 __ negl(Rdst);
6180 __ addl(Rdst, BitsPerInt - 1);
6181 %}
6182 ins_pipe(ialu_reg);
6183 %}
6185 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6186 predicate(UseCountLeadingZerosInstruction);
6187 match(Set dst (CountLeadingZerosL src));
6188 effect(KILL cr);
6190 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6191 ins_encode %{
6192 __ lzcntq($dst$$Register, $src$$Register);
6193 %}
6194 ins_pipe(ialu_reg);
6195 %}
6197 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6198 predicate(!UseCountLeadingZerosInstruction);
6199 match(Set dst (CountLeadingZerosL src));
6200 effect(KILL cr);
6202 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6203 "jnz skip\n\t"
6204 "movl $dst, -1\n"
6205 "skip:\n\t"
6206 "negl $dst\n\t"
6207 "addl $dst, 63" %}
6208 ins_encode %{
6209 Register Rdst = $dst$$Register;
6210 Register Rsrc = $src$$Register;
6211 Label skip;
6212 __ bsrq(Rdst, Rsrc);
6213 __ jccb(Assembler::notZero, skip);
6214 __ movl(Rdst, -1);
6215 __ bind(skip);
6216 __ negl(Rdst);
6217 __ addl(Rdst, BitsPerLong - 1);
6218 %}
6219 ins_pipe(ialu_reg);
6220 %}
6222 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6223 match(Set dst (CountTrailingZerosI src));
6224 effect(KILL cr);
6226 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6227 "jnz done\n\t"
6228 "movl $dst, 32\n"
6229 "done:" %}
6230 ins_encode %{
6231 Register Rdst = $dst$$Register;
6232 Label done;
6233 __ bsfl(Rdst, $src$$Register);
6234 __ jccb(Assembler::notZero, done);
6235 __ movl(Rdst, BitsPerInt);
6236 __ bind(done);
6237 %}
6238 ins_pipe(ialu_reg);
6239 %}
6241 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6242 match(Set dst (CountTrailingZerosL src));
6243 effect(KILL cr);
6245 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6246 "jnz done\n\t"
6247 "movl $dst, 64\n"
6248 "done:" %}
6249 ins_encode %{
6250 Register Rdst = $dst$$Register;
6251 Label done;
6252 __ bsfq(Rdst, $src$$Register);
6253 __ jccb(Assembler::notZero, done);
6254 __ movl(Rdst, BitsPerLong);
6255 __ bind(done);
6256 %}
6257 ins_pipe(ialu_reg);
6258 %}
6261 //---------- Population Count Instructions -------------------------------------
6263 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6264 predicate(UsePopCountInstruction);
6265 match(Set dst (PopCountI src));
6266 effect(KILL cr);
6268 format %{ "popcnt $dst, $src" %}
6269 ins_encode %{
6270 __ popcntl($dst$$Register, $src$$Register);
6271 %}
6272 ins_pipe(ialu_reg);
6273 %}
6275 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6276 predicate(UsePopCountInstruction);
6277 match(Set dst (PopCountI (LoadI mem)));
6278 effect(KILL cr);
6280 format %{ "popcnt $dst, $mem" %}
6281 ins_encode %{
6282 __ popcntl($dst$$Register, $mem$$Address);
6283 %}
6284 ins_pipe(ialu_reg);
6285 %}
6287 // Note: Long.bitCount(long) returns an int.
6288 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6289 predicate(UsePopCountInstruction);
6290 match(Set dst (PopCountL src));
6291 effect(KILL cr);
6293 format %{ "popcnt $dst, $src" %}
6294 ins_encode %{
6295 __ popcntq($dst$$Register, $src$$Register);
6296 %}
6297 ins_pipe(ialu_reg);
6298 %}
6300 // Note: Long.bitCount(long) returns an int.
6301 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6302 predicate(UsePopCountInstruction);
6303 match(Set dst (PopCountL (LoadL mem)));
6304 effect(KILL cr);
6306 format %{ "popcnt $dst, $mem" %}
6307 ins_encode %{
6308 __ popcntq($dst$$Register, $mem$$Address);
6309 %}
6310 ins_pipe(ialu_reg);
6311 %}
6314 //----------MemBar Instructions-----------------------------------------------
6315 // Memory barrier flavors
6317 instruct membar_acquire()
6318 %{
6319 match(MemBarAcquire);
6320 ins_cost(0);
6322 size(0);
6323 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6324 ins_encode();
6325 ins_pipe(empty);
6326 %}
6328 instruct membar_acquire_lock()
6329 %{
6330 match(MemBarAcquireLock);
6331 ins_cost(0);
6333 size(0);
6334 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6335 ins_encode();
6336 ins_pipe(empty);
6337 %}
6339 instruct membar_release()
6340 %{
6341 match(MemBarRelease);
6342 ins_cost(0);
6344 size(0);
6345 format %{ "MEMBAR-release ! (empty encoding)" %}
6346 ins_encode();
6347 ins_pipe(empty);
6348 %}
6350 instruct membar_release_lock()
6351 %{
6352 match(MemBarReleaseLock);
6353 ins_cost(0);
6355 size(0);
6356 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6357 ins_encode();
6358 ins_pipe(empty);
6359 %}
6361 instruct membar_volatile(rFlagsReg cr) %{
6362 match(MemBarVolatile);
6363 effect(KILL cr);
6364 ins_cost(400);
6366 format %{
6367 $$template
6368 if (os::is_MP()) {
6369 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6370 } else {
6371 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6372 }
6373 %}
6374 ins_encode %{
6375 __ membar(Assembler::StoreLoad);
6376 %}
6377 ins_pipe(pipe_slow);
6378 %}
6380 instruct unnecessary_membar_volatile()
6381 %{
6382 match(MemBarVolatile);
6383 predicate(Matcher::post_store_load_barrier(n));
6384 ins_cost(0);
6386 size(0);
6387 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6388 ins_encode();
6389 ins_pipe(empty);
6390 %}
6392 instruct membar_storestore() %{
6393 match(MemBarStoreStore);
6394 ins_cost(0);
6396 size(0);
6397 format %{ "MEMBAR-storestore (empty encoding)" %}
6398 ins_encode( );
6399 ins_pipe(empty);
6400 %}
6402 //----------Move Instructions--------------------------------------------------
6404 instruct castX2P(rRegP dst, rRegL src)
6405 %{
6406 match(Set dst (CastX2P src));
6408 format %{ "movq $dst, $src\t# long->ptr" %}
6409 ins_encode %{
6410 if ($dst$$reg != $src$$reg) {
6411 __ movptr($dst$$Register, $src$$Register);
6412 }
6413 %}
6414 ins_pipe(ialu_reg_reg); // XXX
6415 %}
6417 instruct castP2X(rRegL dst, rRegP src)
6418 %{
6419 match(Set dst (CastP2X src));
6421 format %{ "movq $dst, $src\t# ptr -> long" %}
6422 ins_encode %{
6423 if ($dst$$reg != $src$$reg) {
6424 __ movptr($dst$$Register, $src$$Register);
6425 }
6426 %}
6427 ins_pipe(ialu_reg_reg); // XXX
6428 %}
6430 // Convert oop into int for vectors alignment masking
6431 instruct convP2I(rRegI dst, rRegP src)
6432 %{
6433 match(Set dst (ConvL2I (CastP2X src)));
6435 format %{ "movl $dst, $src\t# ptr -> int" %}
6436 ins_encode %{
6437 __ movl($dst$$Register, $src$$Register);
6438 %}
6439 ins_pipe(ialu_reg_reg); // XXX
6440 %}
6442 // Convert compressed oop into int for vectors alignment masking
6443 // in case of 32bit oops (heap < 4Gb).
6444 instruct convN2I(rRegI dst, rRegN src)
6445 %{
6446 predicate(Universe::narrow_oop_shift() == 0);
6447 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6449 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6450 ins_encode %{
6451 __ movl($dst$$Register, $src$$Register);
6452 %}
6453 ins_pipe(ialu_reg_reg); // XXX
6454 %}
6456 // Convert oop pointer into compressed form
6457 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6458 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6459 match(Set dst (EncodeP src));
6460 effect(KILL cr);
6461 format %{ "encode_heap_oop $dst,$src" %}
6462 ins_encode %{
6463 Register s = $src$$Register;
6464 Register d = $dst$$Register;
6465 if (s != d) {
6466 __ movq(d, s);
6467 }
6468 __ encode_heap_oop(d);
6469 %}
6470 ins_pipe(ialu_reg_long);
6471 %}
6473 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6474 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6475 match(Set dst (EncodeP src));
6476 effect(KILL cr);
6477 format %{ "encode_heap_oop_not_null $dst,$src" %}
6478 ins_encode %{
6479 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6480 %}
6481 ins_pipe(ialu_reg_long);
6482 %}
6484 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6485 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6486 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6487 match(Set dst (DecodeN src));
6488 effect(KILL cr);
6489 format %{ "decode_heap_oop $dst,$src" %}
6490 ins_encode %{
6491 Register s = $src$$Register;
6492 Register d = $dst$$Register;
6493 if (s != d) {
6494 __ movq(d, s);
6495 }
6496 __ decode_heap_oop(d);
6497 %}
6498 ins_pipe(ialu_reg_long);
6499 %}
6501 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6502 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6503 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6504 match(Set dst (DecodeN src));
6505 effect(KILL cr);
6506 format %{ "decode_heap_oop_not_null $dst,$src" %}
6507 ins_encode %{
6508 Register s = $src$$Register;
6509 Register d = $dst$$Register;
6510 if (s != d) {
6511 __ decode_heap_oop_not_null(d, s);
6512 } else {
6513 __ decode_heap_oop_not_null(d);
6514 }
6515 %}
6516 ins_pipe(ialu_reg_long);
6517 %}
6519 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6520 match(Set dst (EncodePKlass src));
6521 effect(KILL cr);
6522 format %{ "encode_klass_not_null $dst,$src" %}
6523 ins_encode %{
6524 __ encode_klass_not_null($dst$$Register, $src$$Register);
6525 %}
6526 ins_pipe(ialu_reg_long);
6527 %}
6529 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6530 match(Set dst (DecodeNKlass src));
6531 effect(KILL cr);
6532 format %{ "decode_klass_not_null $dst,$src" %}
6533 ins_encode %{
6534 Register s = $src$$Register;
6535 Register d = $dst$$Register;
6536 if (s != d) {
6537 __ decode_klass_not_null(d, s);
6538 } else {
6539 __ decode_klass_not_null(d);
6540 }
6541 %}
6542 ins_pipe(ialu_reg_long);
6543 %}
6546 //----------Conditional Move---------------------------------------------------
6547 // Jump
6548 // dummy instruction for generating temp registers
6549 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6550 match(Jump (LShiftL switch_val shift));
6551 ins_cost(350);
6552 predicate(false);
6553 effect(TEMP dest);
6555 format %{ "leaq $dest, [$constantaddress]\n\t"
6556 "jmp [$dest + $switch_val << $shift]\n\t" %}
6557 ins_encode %{
6558 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6559 // to do that and the compiler is using that register as one it can allocate.
6560 // So we build it all by hand.
6561 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6562 // ArrayAddress dispatch(table, index);
6563 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6564 __ lea($dest$$Register, $constantaddress);
6565 __ jmp(dispatch);
6566 %}
6567 ins_pipe(pipe_jmp);
6568 %}
6570 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6571 match(Jump (AddL (LShiftL switch_val shift) offset));
6572 ins_cost(350);
6573 effect(TEMP dest);
6575 format %{ "leaq $dest, [$constantaddress]\n\t"
6576 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6577 ins_encode %{
6578 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6579 // to do that and the compiler is using that register as one it can allocate.
6580 // So we build it all by hand.
6581 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6582 // ArrayAddress dispatch(table, index);
6583 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6584 __ lea($dest$$Register, $constantaddress);
6585 __ jmp(dispatch);
6586 %}
6587 ins_pipe(pipe_jmp);
6588 %}
6590 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6591 match(Jump switch_val);
6592 ins_cost(350);
6593 effect(TEMP dest);
6595 format %{ "leaq $dest, [$constantaddress]\n\t"
6596 "jmp [$dest + $switch_val]\n\t" %}
6597 ins_encode %{
6598 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6599 // to do that and the compiler is using that register as one it can allocate.
6600 // So we build it all by hand.
6601 // Address index(noreg, switch_reg, Address::times_1);
6602 // ArrayAddress dispatch(table, index);
6603 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6604 __ lea($dest$$Register, $constantaddress);
6605 __ jmp(dispatch);
6606 %}
6607 ins_pipe(pipe_jmp);
6608 %}
6610 // Conditional move
6611 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6612 %{
6613 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6615 ins_cost(200); // XXX
6616 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6617 opcode(0x0F, 0x40);
6618 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6619 ins_pipe(pipe_cmov_reg);
6620 %}
6622 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6623 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6625 ins_cost(200); // XXX
6626 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6627 opcode(0x0F, 0x40);
6628 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6629 ins_pipe(pipe_cmov_reg);
6630 %}
6632 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6633 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6634 ins_cost(200);
6635 expand %{
6636 cmovI_regU(cop, cr, dst, src);
6637 %}
6638 %}
6640 // Conditional move
6641 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6642 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6644 ins_cost(250); // XXX
6645 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6646 opcode(0x0F, 0x40);
6647 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6648 ins_pipe(pipe_cmov_mem);
6649 %}
6651 // Conditional move
6652 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6653 %{
6654 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6656 ins_cost(250); // XXX
6657 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6658 opcode(0x0F, 0x40);
6659 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6660 ins_pipe(pipe_cmov_mem);
6661 %}
6663 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6664 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6665 ins_cost(250);
6666 expand %{
6667 cmovI_memU(cop, cr, dst, src);
6668 %}
6669 %}
6671 // Conditional move
6672 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6673 %{
6674 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6676 ins_cost(200); // XXX
6677 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6678 opcode(0x0F, 0x40);
6679 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6680 ins_pipe(pipe_cmov_reg);
6681 %}
6683 // Conditional move
6684 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6685 %{
6686 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6688 ins_cost(200); // XXX
6689 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6690 opcode(0x0F, 0x40);
6691 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6692 ins_pipe(pipe_cmov_reg);
6693 %}
6695 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6696 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6697 ins_cost(200);
6698 expand %{
6699 cmovN_regU(cop, cr, dst, src);
6700 %}
6701 %}
6703 // Conditional move
6704 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6705 %{
6706 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6708 ins_cost(200); // XXX
6709 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6710 opcode(0x0F, 0x40);
6711 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6712 ins_pipe(pipe_cmov_reg); // XXX
6713 %}
6715 // Conditional move
6716 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6717 %{
6718 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6720 ins_cost(200); // XXX
6721 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6722 opcode(0x0F, 0x40);
6723 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6724 ins_pipe(pipe_cmov_reg); // XXX
6725 %}
6727 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6728 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6729 ins_cost(200);
6730 expand %{
6731 cmovP_regU(cop, cr, dst, src);
6732 %}
6733 %}
6735 // DISABLED: Requires the ADLC to emit a bottom_type call that
6736 // correctly meets the two pointer arguments; one is an incoming
6737 // register but the other is a memory operand. ALSO appears to
6738 // be buggy with implicit null checks.
6739 //
6740 //// Conditional move
6741 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
6742 //%{
6743 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6744 // ins_cost(250);
6745 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6746 // opcode(0x0F,0x40);
6747 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6748 // ins_pipe( pipe_cmov_mem );
6749 //%}
6750 //
6751 //// Conditional move
6752 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
6753 //%{
6754 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6755 // ins_cost(250);
6756 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6757 // opcode(0x0F,0x40);
6758 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6759 // ins_pipe( pipe_cmov_mem );
6760 //%}
6762 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6763 %{
6764 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6766 ins_cost(200); // XXX
6767 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6768 opcode(0x0F, 0x40);
6769 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6770 ins_pipe(pipe_cmov_reg); // XXX
6771 %}
6773 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6774 %{
6775 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6777 ins_cost(200); // XXX
6778 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6779 opcode(0x0F, 0x40);
6780 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6781 ins_pipe(pipe_cmov_mem); // XXX
6782 %}
6784 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6785 %{
6786 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6788 ins_cost(200); // XXX
6789 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6790 opcode(0x0F, 0x40);
6791 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6792 ins_pipe(pipe_cmov_reg); // XXX
6793 %}
6795 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6796 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6797 ins_cost(200);
6798 expand %{
6799 cmovL_regU(cop, cr, dst, src);
6800 %}
6801 %}
6803 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6804 %{
6805 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6807 ins_cost(200); // XXX
6808 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6809 opcode(0x0F, 0x40);
6810 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6811 ins_pipe(pipe_cmov_mem); // XXX
6812 %}
6814 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6815 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6816 ins_cost(200);
6817 expand %{
6818 cmovL_memU(cop, cr, dst, src);
6819 %}
6820 %}
6822 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6823 %{
6824 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6826 ins_cost(200); // XXX
6827 format %{ "jn$cop skip\t# signed cmove float\n\t"
6828 "movss $dst, $src\n"
6829 "skip:" %}
6830 ins_encode %{
6831 Label Lskip;
6832 // Invert sense of branch from sense of CMOV
6833 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6834 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6835 __ bind(Lskip);
6836 %}
6837 ins_pipe(pipe_slow);
6838 %}
6840 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
6841 // %{
6842 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
6844 // ins_cost(200); // XXX
6845 // format %{ "jn$cop skip\t# signed cmove float\n\t"
6846 // "movss $dst, $src\n"
6847 // "skip:" %}
6848 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
6849 // ins_pipe(pipe_slow);
6850 // %}
6852 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6853 %{
6854 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6856 ins_cost(200); // XXX
6857 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6858 "movss $dst, $src\n"
6859 "skip:" %}
6860 ins_encode %{
6861 Label Lskip;
6862 // Invert sense of branch from sense of CMOV
6863 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6864 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6865 __ bind(Lskip);
6866 %}
6867 ins_pipe(pipe_slow);
6868 %}
6870 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6871 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6872 ins_cost(200);
6873 expand %{
6874 cmovF_regU(cop, cr, dst, src);
6875 %}
6876 %}
6878 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6879 %{
6880 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6882 ins_cost(200); // XXX
6883 format %{ "jn$cop skip\t# signed cmove double\n\t"
6884 "movsd $dst, $src\n"
6885 "skip:" %}
6886 ins_encode %{
6887 Label Lskip;
6888 // Invert sense of branch from sense of CMOV
6889 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6890 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6891 __ bind(Lskip);
6892 %}
6893 ins_pipe(pipe_slow);
6894 %}
6896 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6897 %{
6898 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6900 ins_cost(200); // XXX
6901 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6902 "movsd $dst, $src\n"
6903 "skip:" %}
6904 ins_encode %{
6905 Label Lskip;
6906 // Invert sense of branch from sense of CMOV
6907 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6908 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6909 __ bind(Lskip);
6910 %}
6911 ins_pipe(pipe_slow);
6912 %}
6914 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6915 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6916 ins_cost(200);
6917 expand %{
6918 cmovD_regU(cop, cr, dst, src);
6919 %}
6920 %}
6922 //----------Arithmetic Instructions--------------------------------------------
6923 //----------Addition Instructions----------------------------------------------
6925 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6926 %{
6927 match(Set dst (AddI dst src));
6928 effect(KILL cr);
6930 format %{ "addl $dst, $src\t# int" %}
6931 opcode(0x03);
6932 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
6933 ins_pipe(ialu_reg_reg);
6934 %}
6936 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6937 %{
6938 match(Set dst (AddI dst src));
6939 effect(KILL cr);
6941 format %{ "addl $dst, $src\t# int" %}
6942 opcode(0x81, 0x00); /* /0 id */
6943 ins_encode(OpcSErm(dst, src), Con8or32(src));
6944 ins_pipe( ialu_reg );
6945 %}
6947 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
6948 %{
6949 match(Set dst (AddI dst (LoadI src)));
6950 effect(KILL cr);
6952 ins_cost(125); // XXX
6953 format %{ "addl $dst, $src\t# int" %}
6954 opcode(0x03);
6955 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6956 ins_pipe(ialu_reg_mem);
6957 %}
6959 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
6960 %{
6961 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6962 effect(KILL cr);
6964 ins_cost(150); // XXX
6965 format %{ "addl $dst, $src\t# int" %}
6966 opcode(0x01); /* Opcode 01 /r */
6967 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6968 ins_pipe(ialu_mem_reg);
6969 %}
6971 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
6972 %{
6973 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6974 effect(KILL cr);
6976 ins_cost(125); // XXX
6977 format %{ "addl $dst, $src\t# int" %}
6978 opcode(0x81); /* Opcode 81 /0 id */
6979 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
6980 ins_pipe(ialu_mem_imm);
6981 %}
6983 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
6984 %{
6985 predicate(UseIncDec);
6986 match(Set dst (AddI dst src));
6987 effect(KILL cr);
6989 format %{ "incl $dst\t# int" %}
6990 opcode(0xFF, 0x00); // FF /0
6991 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6992 ins_pipe(ialu_reg);
6993 %}
6995 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
6996 %{
6997 predicate(UseIncDec);
6998 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6999 effect(KILL cr);
7001 ins_cost(125); // XXX
7002 format %{ "incl $dst\t# int" %}
7003 opcode(0xFF); /* Opcode FF /0 */
7004 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7005 ins_pipe(ialu_mem_imm);
7006 %}
7008 // XXX why does that use AddI
7009 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7010 %{
7011 predicate(UseIncDec);
7012 match(Set dst (AddI dst src));
7013 effect(KILL cr);
7015 format %{ "decl $dst\t# int" %}
7016 opcode(0xFF, 0x01); // FF /1
7017 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7018 ins_pipe(ialu_reg);
7019 %}
7021 // XXX why does that use AddI
7022 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7023 %{
7024 predicate(UseIncDec);
7025 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7026 effect(KILL cr);
7028 ins_cost(125); // XXX
7029 format %{ "decl $dst\t# int" %}
7030 opcode(0xFF); /* Opcode FF /1 */
7031 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7032 ins_pipe(ialu_mem_imm);
7033 %}
7035 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7036 %{
7037 match(Set dst (AddI src0 src1));
7039 ins_cost(110);
7040 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7041 opcode(0x8D); /* 0x8D /r */
7042 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7043 ins_pipe(ialu_reg_reg);
7044 %}
7046 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7047 %{
7048 match(Set dst (AddL dst src));
7049 effect(KILL cr);
7051 format %{ "addq $dst, $src\t# long" %}
7052 opcode(0x03);
7053 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7054 ins_pipe(ialu_reg_reg);
7055 %}
7057 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7058 %{
7059 match(Set dst (AddL dst src));
7060 effect(KILL cr);
7062 format %{ "addq $dst, $src\t# long" %}
7063 opcode(0x81, 0x00); /* /0 id */
7064 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7065 ins_pipe( ialu_reg );
7066 %}
7068 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7069 %{
7070 match(Set dst (AddL dst (LoadL src)));
7071 effect(KILL cr);
7073 ins_cost(125); // XXX
7074 format %{ "addq $dst, $src\t# long" %}
7075 opcode(0x03);
7076 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7077 ins_pipe(ialu_reg_mem);
7078 %}
7080 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7081 %{
7082 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7083 effect(KILL cr);
7085 ins_cost(150); // XXX
7086 format %{ "addq $dst, $src\t# long" %}
7087 opcode(0x01); /* Opcode 01 /r */
7088 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7089 ins_pipe(ialu_mem_reg);
7090 %}
7092 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7093 %{
7094 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7095 effect(KILL cr);
7097 ins_cost(125); // XXX
7098 format %{ "addq $dst, $src\t# long" %}
7099 opcode(0x81); /* Opcode 81 /0 id */
7100 ins_encode(REX_mem_wide(dst),
7101 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7102 ins_pipe(ialu_mem_imm);
7103 %}
7105 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7106 %{
7107 predicate(UseIncDec);
7108 match(Set dst (AddL dst src));
7109 effect(KILL cr);
7111 format %{ "incq $dst\t# long" %}
7112 opcode(0xFF, 0x00); // FF /0
7113 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7114 ins_pipe(ialu_reg);
7115 %}
7117 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7118 %{
7119 predicate(UseIncDec);
7120 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7121 effect(KILL cr);
7123 ins_cost(125); // XXX
7124 format %{ "incq $dst\t# long" %}
7125 opcode(0xFF); /* Opcode FF /0 */
7126 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7127 ins_pipe(ialu_mem_imm);
7128 %}
7130 // XXX why does that use AddL
7131 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7132 %{
7133 predicate(UseIncDec);
7134 match(Set dst (AddL dst src));
7135 effect(KILL cr);
7137 format %{ "decq $dst\t# long" %}
7138 opcode(0xFF, 0x01); // FF /1
7139 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7140 ins_pipe(ialu_reg);
7141 %}
7143 // XXX why does that use AddL
7144 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7145 %{
7146 predicate(UseIncDec);
7147 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7148 effect(KILL cr);
7150 ins_cost(125); // XXX
7151 format %{ "decq $dst\t# long" %}
7152 opcode(0xFF); /* Opcode FF /1 */
7153 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7154 ins_pipe(ialu_mem_imm);
7155 %}
7157 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7158 %{
7159 match(Set dst (AddL src0 src1));
7161 ins_cost(110);
7162 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7163 opcode(0x8D); /* 0x8D /r */
7164 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7165 ins_pipe(ialu_reg_reg);
7166 %}
7168 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7169 %{
7170 match(Set dst (AddP dst src));
7171 effect(KILL cr);
7173 format %{ "addq $dst, $src\t# ptr" %}
7174 opcode(0x03);
7175 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7176 ins_pipe(ialu_reg_reg);
7177 %}
7179 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7180 %{
7181 match(Set dst (AddP dst src));
7182 effect(KILL cr);
7184 format %{ "addq $dst, $src\t# ptr" %}
7185 opcode(0x81, 0x00); /* /0 id */
7186 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7187 ins_pipe( ialu_reg );
7188 %}
7190 // XXX addP mem ops ????
7192 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7193 %{
7194 match(Set dst (AddP src0 src1));
7196 ins_cost(110);
7197 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7198 opcode(0x8D); /* 0x8D /r */
7199 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7200 ins_pipe(ialu_reg_reg);
7201 %}
7203 instruct checkCastPP(rRegP dst)
7204 %{
7205 match(Set dst (CheckCastPP dst));
7207 size(0);
7208 format %{ "# checkcastPP of $dst" %}
7209 ins_encode(/* empty encoding */);
7210 ins_pipe(empty);
7211 %}
7213 instruct castPP(rRegP dst)
7214 %{
7215 match(Set dst (CastPP dst));
7217 size(0);
7218 format %{ "# castPP of $dst" %}
7219 ins_encode(/* empty encoding */);
7220 ins_pipe(empty);
7221 %}
7223 instruct castII(rRegI dst)
7224 %{
7225 match(Set dst (CastII dst));
7227 size(0);
7228 format %{ "# castII of $dst" %}
7229 ins_encode(/* empty encoding */);
7230 ins_cost(0);
7231 ins_pipe(empty);
7232 %}
7234 // LoadP-locked same as a regular LoadP when used with compare-swap
7235 instruct loadPLocked(rRegP dst, memory mem)
7236 %{
7237 match(Set dst (LoadPLocked mem));
7239 ins_cost(125); // XXX
7240 format %{ "movq $dst, $mem\t# ptr locked" %}
7241 opcode(0x8B);
7242 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7243 ins_pipe(ialu_reg_mem); // XXX
7244 %}
7246 // Conditional-store of the updated heap-top.
7247 // Used during allocation of the shared heap.
7248 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7250 instruct storePConditional(memory heap_top_ptr,
7251 rax_RegP oldval, rRegP newval,
7252 rFlagsReg cr)
7253 %{
7254 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7256 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7257 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7258 opcode(0x0F, 0xB1);
7259 ins_encode(lock_prefix,
7260 REX_reg_mem_wide(newval, heap_top_ptr),
7261 OpcP, OpcS,
7262 reg_mem(newval, heap_top_ptr));
7263 ins_pipe(pipe_cmpxchg);
7264 %}
7266 // Conditional-store of an int value.
7267 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7268 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7269 %{
7270 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7271 effect(KILL oldval);
7273 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7274 opcode(0x0F, 0xB1);
7275 ins_encode(lock_prefix,
7276 REX_reg_mem(newval, mem),
7277 OpcP, OpcS,
7278 reg_mem(newval, mem));
7279 ins_pipe(pipe_cmpxchg);
7280 %}
7282 // Conditional-store of a long value.
7283 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7284 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7285 %{
7286 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7287 effect(KILL oldval);
7289 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7290 opcode(0x0F, 0xB1);
7291 ins_encode(lock_prefix,
7292 REX_reg_mem_wide(newval, mem),
7293 OpcP, OpcS,
7294 reg_mem(newval, mem));
7295 ins_pipe(pipe_cmpxchg);
7296 %}
7299 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7300 instruct compareAndSwapP(rRegI res,
7301 memory mem_ptr,
7302 rax_RegP oldval, rRegP newval,
7303 rFlagsReg cr)
7304 %{
7305 predicate(VM_Version::supports_cx8());
7306 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7307 effect(KILL cr, KILL oldval);
7309 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7310 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7311 "sete $res\n\t"
7312 "movzbl $res, $res" %}
7313 opcode(0x0F, 0xB1);
7314 ins_encode(lock_prefix,
7315 REX_reg_mem_wide(newval, mem_ptr),
7316 OpcP, OpcS,
7317 reg_mem(newval, mem_ptr),
7318 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7319 REX_reg_breg(res, res), // movzbl
7320 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7321 ins_pipe( pipe_cmpxchg );
7322 %}
7324 instruct compareAndSwapL(rRegI res,
7325 memory mem_ptr,
7326 rax_RegL oldval, rRegL newval,
7327 rFlagsReg cr)
7328 %{
7329 predicate(VM_Version::supports_cx8());
7330 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7331 effect(KILL cr, KILL oldval);
7333 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7334 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7335 "sete $res\n\t"
7336 "movzbl $res, $res" %}
7337 opcode(0x0F, 0xB1);
7338 ins_encode(lock_prefix,
7339 REX_reg_mem_wide(newval, mem_ptr),
7340 OpcP, OpcS,
7341 reg_mem(newval, mem_ptr),
7342 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7343 REX_reg_breg(res, res), // movzbl
7344 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7345 ins_pipe( pipe_cmpxchg );
7346 %}
7348 instruct compareAndSwapI(rRegI res,
7349 memory mem_ptr,
7350 rax_RegI oldval, rRegI newval,
7351 rFlagsReg cr)
7352 %{
7353 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7354 effect(KILL cr, KILL oldval);
7356 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7357 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7358 "sete $res\n\t"
7359 "movzbl $res, $res" %}
7360 opcode(0x0F, 0xB1);
7361 ins_encode(lock_prefix,
7362 REX_reg_mem(newval, mem_ptr),
7363 OpcP, OpcS,
7364 reg_mem(newval, mem_ptr),
7365 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7366 REX_reg_breg(res, res), // movzbl
7367 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7368 ins_pipe( pipe_cmpxchg );
7369 %}
7372 instruct compareAndSwapN(rRegI res,
7373 memory mem_ptr,
7374 rax_RegN oldval, rRegN newval,
7375 rFlagsReg cr) %{
7376 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7377 effect(KILL cr, KILL oldval);
7379 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7380 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7381 "sete $res\n\t"
7382 "movzbl $res, $res" %}
7383 opcode(0x0F, 0xB1);
7384 ins_encode(lock_prefix,
7385 REX_reg_mem(newval, mem_ptr),
7386 OpcP, OpcS,
7387 reg_mem(newval, mem_ptr),
7388 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7389 REX_reg_breg(res, res), // movzbl
7390 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7391 ins_pipe( pipe_cmpxchg );
7392 %}
7394 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7395 predicate(n->as_LoadStore()->result_not_used());
7396 match(Set dummy (GetAndAddI mem add));
7397 effect(KILL cr);
7398 format %{ "ADDL [$mem],$add" %}
7399 ins_encode %{
7400 if (os::is_MP()) { __ lock(); }
7401 __ addl($mem$$Address, $add$$constant);
7402 %}
7403 ins_pipe( pipe_cmpxchg );
7404 %}
7406 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7407 match(Set newval (GetAndAddI mem newval));
7408 effect(KILL cr);
7409 format %{ "XADDL [$mem],$newval" %}
7410 ins_encode %{
7411 if (os::is_MP()) { __ lock(); }
7412 __ xaddl($mem$$Address, $newval$$Register);
7413 %}
7414 ins_pipe( pipe_cmpxchg );
7415 %}
7417 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7418 predicate(n->as_LoadStore()->result_not_used());
7419 match(Set dummy (GetAndAddL mem add));
7420 effect(KILL cr);
7421 format %{ "ADDQ [$mem],$add" %}
7422 ins_encode %{
7423 if (os::is_MP()) { __ lock(); }
7424 __ addq($mem$$Address, $add$$constant);
7425 %}
7426 ins_pipe( pipe_cmpxchg );
7427 %}
7429 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
7430 match(Set newval (GetAndAddL mem newval));
7431 effect(KILL cr);
7432 format %{ "XADDQ [$mem],$newval" %}
7433 ins_encode %{
7434 if (os::is_MP()) { __ lock(); }
7435 __ xaddq($mem$$Address, $newval$$Register);
7436 %}
7437 ins_pipe( pipe_cmpxchg );
7438 %}
7440 instruct xchgI( memory mem, rRegI newval) %{
7441 match(Set newval (GetAndSetI mem newval));
7442 format %{ "XCHGL $newval,[$mem]" %}
7443 ins_encode %{
7444 __ xchgl($newval$$Register, $mem$$Address);
7445 %}
7446 ins_pipe( pipe_cmpxchg );
7447 %}
7449 instruct xchgL( memory mem, rRegL newval) %{
7450 match(Set newval (GetAndSetL mem newval));
7451 format %{ "XCHGL $newval,[$mem]" %}
7452 ins_encode %{
7453 __ xchgq($newval$$Register, $mem$$Address);
7454 %}
7455 ins_pipe( pipe_cmpxchg );
7456 %}
7458 instruct xchgP( memory mem, rRegP newval) %{
7459 match(Set newval (GetAndSetP mem newval));
7460 format %{ "XCHGQ $newval,[$mem]" %}
7461 ins_encode %{
7462 __ xchgq($newval$$Register, $mem$$Address);
7463 %}
7464 ins_pipe( pipe_cmpxchg );
7465 %}
7467 instruct xchgN( memory mem, rRegN newval) %{
7468 match(Set newval (GetAndSetN mem newval));
7469 format %{ "XCHGL $newval,$mem]" %}
7470 ins_encode %{
7471 __ xchgl($newval$$Register, $mem$$Address);
7472 %}
7473 ins_pipe( pipe_cmpxchg );
7474 %}
7476 //----------Subtraction Instructions-------------------------------------------
7478 // Integer Subtraction Instructions
7479 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7480 %{
7481 match(Set dst (SubI dst src));
7482 effect(KILL cr);
7484 format %{ "subl $dst, $src\t# int" %}
7485 opcode(0x2B);
7486 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7487 ins_pipe(ialu_reg_reg);
7488 %}
7490 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7491 %{
7492 match(Set dst (SubI dst src));
7493 effect(KILL cr);
7495 format %{ "subl $dst, $src\t# int" %}
7496 opcode(0x81, 0x05); /* Opcode 81 /5 */
7497 ins_encode(OpcSErm(dst, src), Con8or32(src));
7498 ins_pipe(ialu_reg);
7499 %}
7501 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7502 %{
7503 match(Set dst (SubI dst (LoadI src)));
7504 effect(KILL cr);
7506 ins_cost(125);
7507 format %{ "subl $dst, $src\t# int" %}
7508 opcode(0x2B);
7509 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7510 ins_pipe(ialu_reg_mem);
7511 %}
7513 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7514 %{
7515 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7516 effect(KILL cr);
7518 ins_cost(150);
7519 format %{ "subl $dst, $src\t# int" %}
7520 opcode(0x29); /* Opcode 29 /r */
7521 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7522 ins_pipe(ialu_mem_reg);
7523 %}
7525 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7526 %{
7527 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7528 effect(KILL cr);
7530 ins_cost(125); // XXX
7531 format %{ "subl $dst, $src\t# int" %}
7532 opcode(0x81); /* Opcode 81 /5 id */
7533 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7534 ins_pipe(ialu_mem_imm);
7535 %}
7537 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7538 %{
7539 match(Set dst (SubL dst src));
7540 effect(KILL cr);
7542 format %{ "subq $dst, $src\t# long" %}
7543 opcode(0x2B);
7544 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7545 ins_pipe(ialu_reg_reg);
7546 %}
7548 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7549 %{
7550 match(Set dst (SubL dst src));
7551 effect(KILL cr);
7553 format %{ "subq $dst, $src\t# long" %}
7554 opcode(0x81, 0x05); /* Opcode 81 /5 */
7555 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7556 ins_pipe(ialu_reg);
7557 %}
7559 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7560 %{
7561 match(Set dst (SubL dst (LoadL src)));
7562 effect(KILL cr);
7564 ins_cost(125);
7565 format %{ "subq $dst, $src\t# long" %}
7566 opcode(0x2B);
7567 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7568 ins_pipe(ialu_reg_mem);
7569 %}
7571 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7572 %{
7573 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7574 effect(KILL cr);
7576 ins_cost(150);
7577 format %{ "subq $dst, $src\t# long" %}
7578 opcode(0x29); /* Opcode 29 /r */
7579 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7580 ins_pipe(ialu_mem_reg);
7581 %}
7583 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7584 %{
7585 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7586 effect(KILL cr);
7588 ins_cost(125); // XXX
7589 format %{ "subq $dst, $src\t# long" %}
7590 opcode(0x81); /* Opcode 81 /5 id */
7591 ins_encode(REX_mem_wide(dst),
7592 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7593 ins_pipe(ialu_mem_imm);
7594 %}
7596 // Subtract from a pointer
7597 // XXX hmpf???
7598 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
7599 %{
7600 match(Set dst (AddP dst (SubI zero src)));
7601 effect(KILL cr);
7603 format %{ "subq $dst, $src\t# ptr - int" %}
7604 opcode(0x2B);
7605 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7606 ins_pipe(ialu_reg_reg);
7607 %}
7609 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
7610 %{
7611 match(Set dst (SubI zero dst));
7612 effect(KILL cr);
7614 format %{ "negl $dst\t# int" %}
7615 opcode(0xF7, 0x03); // Opcode F7 /3
7616 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7617 ins_pipe(ialu_reg);
7618 %}
7620 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
7621 %{
7622 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7623 effect(KILL cr);
7625 format %{ "negl $dst\t# int" %}
7626 opcode(0xF7, 0x03); // Opcode F7 /3
7627 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7628 ins_pipe(ialu_reg);
7629 %}
7631 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7632 %{
7633 match(Set dst (SubL zero dst));
7634 effect(KILL cr);
7636 format %{ "negq $dst\t# long" %}
7637 opcode(0xF7, 0x03); // Opcode F7 /3
7638 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7639 ins_pipe(ialu_reg);
7640 %}
7642 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7643 %{
7644 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7645 effect(KILL cr);
7647 format %{ "negq $dst\t# long" %}
7648 opcode(0xF7, 0x03); // Opcode F7 /3
7649 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7650 ins_pipe(ialu_reg);
7651 %}
7654 //----------Multiplication/Division Instructions-------------------------------
7655 // Integer Multiplication Instructions
7656 // Multiply Register
7658 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7659 %{
7660 match(Set dst (MulI dst src));
7661 effect(KILL cr);
7663 ins_cost(300);
7664 format %{ "imull $dst, $src\t# int" %}
7665 opcode(0x0F, 0xAF);
7666 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7667 ins_pipe(ialu_reg_reg_alu0);
7668 %}
7670 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7671 %{
7672 match(Set dst (MulI src imm));
7673 effect(KILL cr);
7675 ins_cost(300);
7676 format %{ "imull $dst, $src, $imm\t# int" %}
7677 opcode(0x69); /* 69 /r id */
7678 ins_encode(REX_reg_reg(dst, src),
7679 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7680 ins_pipe(ialu_reg_reg_alu0);
7681 %}
7683 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
7684 %{
7685 match(Set dst (MulI dst (LoadI src)));
7686 effect(KILL cr);
7688 ins_cost(350);
7689 format %{ "imull $dst, $src\t# int" %}
7690 opcode(0x0F, 0xAF);
7691 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
7692 ins_pipe(ialu_reg_mem_alu0);
7693 %}
7695 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
7696 %{
7697 match(Set dst (MulI (LoadI src) imm));
7698 effect(KILL cr);
7700 ins_cost(300);
7701 format %{ "imull $dst, $src, $imm\t# int" %}
7702 opcode(0x69); /* 69 /r id */
7703 ins_encode(REX_reg_mem(dst, src),
7704 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7705 ins_pipe(ialu_reg_mem_alu0);
7706 %}
7708 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7709 %{
7710 match(Set dst (MulL dst src));
7711 effect(KILL cr);
7713 ins_cost(300);
7714 format %{ "imulq $dst, $src\t# long" %}
7715 opcode(0x0F, 0xAF);
7716 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
7717 ins_pipe(ialu_reg_reg_alu0);
7718 %}
7720 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7721 %{
7722 match(Set dst (MulL src imm));
7723 effect(KILL cr);
7725 ins_cost(300);
7726 format %{ "imulq $dst, $src, $imm\t# long" %}
7727 opcode(0x69); /* 69 /r id */
7728 ins_encode(REX_reg_reg_wide(dst, src),
7729 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7730 ins_pipe(ialu_reg_reg_alu0);
7731 %}
7733 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
7734 %{
7735 match(Set dst (MulL dst (LoadL src)));
7736 effect(KILL cr);
7738 ins_cost(350);
7739 format %{ "imulq $dst, $src\t# long" %}
7740 opcode(0x0F, 0xAF);
7741 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
7742 ins_pipe(ialu_reg_mem_alu0);
7743 %}
7745 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
7746 %{
7747 match(Set dst (MulL (LoadL src) imm));
7748 effect(KILL cr);
7750 ins_cost(300);
7751 format %{ "imulq $dst, $src, $imm\t# long" %}
7752 opcode(0x69); /* 69 /r id */
7753 ins_encode(REX_reg_mem_wide(dst, src),
7754 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7755 ins_pipe(ialu_reg_mem_alu0);
7756 %}
7758 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7759 %{
7760 match(Set dst (MulHiL src rax));
7761 effect(USE_KILL rax, KILL cr);
7763 ins_cost(300);
7764 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7765 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7766 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7767 ins_pipe(ialu_reg_reg_alu0);
7768 %}
7770 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7771 rFlagsReg cr)
7772 %{
7773 match(Set rax (DivI rax div));
7774 effect(KILL rdx, KILL cr);
7776 ins_cost(30*100+10*100); // XXX
7777 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7778 "jne,s normal\n\t"
7779 "xorl rdx, rdx\n\t"
7780 "cmpl $div, -1\n\t"
7781 "je,s done\n"
7782 "normal: cdql\n\t"
7783 "idivl $div\n"
7784 "done:" %}
7785 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7786 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7787 ins_pipe(ialu_reg_reg_alu0);
7788 %}
7790 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7791 rFlagsReg cr)
7792 %{
7793 match(Set rax (DivL rax div));
7794 effect(KILL rdx, KILL cr);
7796 ins_cost(30*100+10*100); // XXX
7797 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7798 "cmpq rax, rdx\n\t"
7799 "jne,s normal\n\t"
7800 "xorl rdx, rdx\n\t"
7801 "cmpq $div, -1\n\t"
7802 "je,s done\n"
7803 "normal: cdqq\n\t"
7804 "idivq $div\n"
7805 "done:" %}
7806 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7807 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7808 ins_pipe(ialu_reg_reg_alu0);
7809 %}
7811 // Integer DIVMOD with Register, both quotient and mod results
7812 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7813 rFlagsReg cr)
7814 %{
7815 match(DivModI rax div);
7816 effect(KILL cr);
7818 ins_cost(30*100+10*100); // XXX
7819 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7820 "jne,s normal\n\t"
7821 "xorl rdx, rdx\n\t"
7822 "cmpl $div, -1\n\t"
7823 "je,s done\n"
7824 "normal: cdql\n\t"
7825 "idivl $div\n"
7826 "done:" %}
7827 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7828 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7829 ins_pipe(pipe_slow);
7830 %}
7832 // Long DIVMOD with Register, both quotient and mod results
7833 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7834 rFlagsReg cr)
7835 %{
7836 match(DivModL rax div);
7837 effect(KILL cr);
7839 ins_cost(30*100+10*100); // XXX
7840 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7841 "cmpq rax, rdx\n\t"
7842 "jne,s normal\n\t"
7843 "xorl rdx, rdx\n\t"
7844 "cmpq $div, -1\n\t"
7845 "je,s done\n"
7846 "normal: cdqq\n\t"
7847 "idivq $div\n"
7848 "done:" %}
7849 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7850 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7851 ins_pipe(pipe_slow);
7852 %}
7854 //----------- DivL-By-Constant-Expansions--------------------------------------
7855 // DivI cases are handled by the compiler
7857 // Magic constant, reciprocal of 10
7858 instruct loadConL_0x6666666666666667(rRegL dst)
7859 %{
7860 effect(DEF dst);
7862 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
7863 ins_encode(load_immL(dst, 0x6666666666666667));
7864 ins_pipe(ialu_reg);
7865 %}
7867 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7868 %{
7869 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
7871 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
7872 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7873 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7874 ins_pipe(ialu_reg_reg_alu0);
7875 %}
7877 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
7878 %{
7879 effect(USE_DEF dst, KILL cr);
7881 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
7882 opcode(0xC1, 0x7); /* C1 /7 ib */
7883 ins_encode(reg_opc_imm_wide(dst, 0x3F));
7884 ins_pipe(ialu_reg);
7885 %}
7887 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
7888 %{
7889 effect(USE_DEF dst, KILL cr);
7891 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
7892 opcode(0xC1, 0x7); /* C1 /7 ib */
7893 ins_encode(reg_opc_imm_wide(dst, 0x2));
7894 ins_pipe(ialu_reg);
7895 %}
7897 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
7898 %{
7899 match(Set dst (DivL src div));
7901 ins_cost((5+8)*100);
7902 expand %{
7903 rax_RegL rax; // Killed temp
7904 rFlagsReg cr; // Killed
7905 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
7906 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
7907 sarL_rReg_63(src, cr); // sarq src, 63
7908 sarL_rReg_2(dst, cr); // sarq rdx, 2
7909 subL_rReg(dst, src, cr); // subl rdx, src
7910 %}
7911 %}
7913 //-----------------------------------------------------------------------------
7915 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
7916 rFlagsReg cr)
7917 %{
7918 match(Set rdx (ModI rax div));
7919 effect(KILL rax, KILL cr);
7921 ins_cost(300); // XXX
7922 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
7923 "jne,s normal\n\t"
7924 "xorl rdx, rdx\n\t"
7925 "cmpl $div, -1\n\t"
7926 "je,s done\n"
7927 "normal: cdql\n\t"
7928 "idivl $div\n"
7929 "done:" %}
7930 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7931 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7932 ins_pipe(ialu_reg_reg_alu0);
7933 %}
7935 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
7936 rFlagsReg cr)
7937 %{
7938 match(Set rdx (ModL rax div));
7939 effect(KILL rax, KILL cr);
7941 ins_cost(300); // XXX
7942 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
7943 "cmpq rax, rdx\n\t"
7944 "jne,s normal\n\t"
7945 "xorl rdx, rdx\n\t"
7946 "cmpq $div, -1\n\t"
7947 "je,s done\n"
7948 "normal: cdqq\n\t"
7949 "idivq $div\n"
7950 "done:" %}
7951 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7952 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7953 ins_pipe(ialu_reg_reg_alu0);
7954 %}
7956 // Integer Shift Instructions
7957 // Shift Left by one
7958 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
7959 %{
7960 match(Set dst (LShiftI dst shift));
7961 effect(KILL cr);
7963 format %{ "sall $dst, $shift" %}
7964 opcode(0xD1, 0x4); /* D1 /4 */
7965 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7966 ins_pipe(ialu_reg);
7967 %}
7969 // Shift Left by one
7970 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7971 %{
7972 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7973 effect(KILL cr);
7975 format %{ "sall $dst, $shift\t" %}
7976 opcode(0xD1, 0x4); /* D1 /4 */
7977 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7978 ins_pipe(ialu_mem_imm);
7979 %}
7981 // Shift Left by 8-bit immediate
7982 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
7983 %{
7984 match(Set dst (LShiftI dst shift));
7985 effect(KILL cr);
7987 format %{ "sall $dst, $shift" %}
7988 opcode(0xC1, 0x4); /* C1 /4 ib */
7989 ins_encode(reg_opc_imm(dst, shift));
7990 ins_pipe(ialu_reg);
7991 %}
7993 // Shift Left by 8-bit immediate
7994 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
7995 %{
7996 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7997 effect(KILL cr);
7999 format %{ "sall $dst, $shift" %}
8000 opcode(0xC1, 0x4); /* C1 /4 ib */
8001 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8002 ins_pipe(ialu_mem_imm);
8003 %}
8005 // Shift Left by variable
8006 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8007 %{
8008 match(Set dst (LShiftI dst shift));
8009 effect(KILL cr);
8011 format %{ "sall $dst, $shift" %}
8012 opcode(0xD3, 0x4); /* D3 /4 */
8013 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8014 ins_pipe(ialu_reg_reg);
8015 %}
8017 // Shift Left by variable
8018 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8019 %{
8020 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8021 effect(KILL cr);
8023 format %{ "sall $dst, $shift" %}
8024 opcode(0xD3, 0x4); /* D3 /4 */
8025 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8026 ins_pipe(ialu_mem_reg);
8027 %}
8029 // Arithmetic shift right by one
8030 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8031 %{
8032 match(Set dst (RShiftI dst shift));
8033 effect(KILL cr);
8035 format %{ "sarl $dst, $shift" %}
8036 opcode(0xD1, 0x7); /* D1 /7 */
8037 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8038 ins_pipe(ialu_reg);
8039 %}
8041 // Arithmetic shift right by one
8042 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8043 %{
8044 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8045 effect(KILL cr);
8047 format %{ "sarl $dst, $shift" %}
8048 opcode(0xD1, 0x7); /* D1 /7 */
8049 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8050 ins_pipe(ialu_mem_imm);
8051 %}
8053 // Arithmetic Shift Right by 8-bit immediate
8054 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8055 %{
8056 match(Set dst (RShiftI dst shift));
8057 effect(KILL cr);
8059 format %{ "sarl $dst, $shift" %}
8060 opcode(0xC1, 0x7); /* C1 /7 ib */
8061 ins_encode(reg_opc_imm(dst, shift));
8062 ins_pipe(ialu_mem_imm);
8063 %}
8065 // Arithmetic Shift Right by 8-bit immediate
8066 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8067 %{
8068 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8069 effect(KILL cr);
8071 format %{ "sarl $dst, $shift" %}
8072 opcode(0xC1, 0x7); /* C1 /7 ib */
8073 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8074 ins_pipe(ialu_mem_imm);
8075 %}
8077 // Arithmetic Shift Right by variable
8078 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8079 %{
8080 match(Set dst (RShiftI dst shift));
8081 effect(KILL cr);
8083 format %{ "sarl $dst, $shift" %}
8084 opcode(0xD3, 0x7); /* D3 /7 */
8085 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8086 ins_pipe(ialu_reg_reg);
8087 %}
8089 // Arithmetic Shift Right by variable
8090 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8091 %{
8092 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8093 effect(KILL cr);
8095 format %{ "sarl $dst, $shift" %}
8096 opcode(0xD3, 0x7); /* D3 /7 */
8097 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8098 ins_pipe(ialu_mem_reg);
8099 %}
8101 // Logical shift right by one
8102 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8103 %{
8104 match(Set dst (URShiftI dst shift));
8105 effect(KILL cr);
8107 format %{ "shrl $dst, $shift" %}
8108 opcode(0xD1, 0x5); /* D1 /5 */
8109 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8110 ins_pipe(ialu_reg);
8111 %}
8113 // Logical shift right by one
8114 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8115 %{
8116 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8117 effect(KILL cr);
8119 format %{ "shrl $dst, $shift" %}
8120 opcode(0xD1, 0x5); /* D1 /5 */
8121 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8122 ins_pipe(ialu_mem_imm);
8123 %}
8125 // Logical Shift Right by 8-bit immediate
8126 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8127 %{
8128 match(Set dst (URShiftI dst shift));
8129 effect(KILL cr);
8131 format %{ "shrl $dst, $shift" %}
8132 opcode(0xC1, 0x5); /* C1 /5 ib */
8133 ins_encode(reg_opc_imm(dst, shift));
8134 ins_pipe(ialu_reg);
8135 %}
8137 // Logical Shift Right by 8-bit immediate
8138 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8139 %{
8140 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8141 effect(KILL cr);
8143 format %{ "shrl $dst, $shift" %}
8144 opcode(0xC1, 0x5); /* C1 /5 ib */
8145 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8146 ins_pipe(ialu_mem_imm);
8147 %}
8149 // Logical Shift Right by variable
8150 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8151 %{
8152 match(Set dst (URShiftI dst shift));
8153 effect(KILL cr);
8155 format %{ "shrl $dst, $shift" %}
8156 opcode(0xD3, 0x5); /* D3 /5 */
8157 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8158 ins_pipe(ialu_reg_reg);
8159 %}
8161 // Logical Shift Right by variable
8162 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8163 %{
8164 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8165 effect(KILL cr);
8167 format %{ "shrl $dst, $shift" %}
8168 opcode(0xD3, 0x5); /* D3 /5 */
8169 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8170 ins_pipe(ialu_mem_reg);
8171 %}
8173 // Long Shift Instructions
8174 // Shift Left by one
8175 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8176 %{
8177 match(Set dst (LShiftL dst shift));
8178 effect(KILL cr);
8180 format %{ "salq $dst, $shift" %}
8181 opcode(0xD1, 0x4); /* D1 /4 */
8182 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8183 ins_pipe(ialu_reg);
8184 %}
8186 // Shift Left by one
8187 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8188 %{
8189 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8190 effect(KILL cr);
8192 format %{ "salq $dst, $shift" %}
8193 opcode(0xD1, 0x4); /* D1 /4 */
8194 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8195 ins_pipe(ialu_mem_imm);
8196 %}
8198 // Shift Left by 8-bit immediate
8199 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8200 %{
8201 match(Set dst (LShiftL dst shift));
8202 effect(KILL cr);
8204 format %{ "salq $dst, $shift" %}
8205 opcode(0xC1, 0x4); /* C1 /4 ib */
8206 ins_encode(reg_opc_imm_wide(dst, shift));
8207 ins_pipe(ialu_reg);
8208 %}
8210 // Shift Left by 8-bit immediate
8211 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8212 %{
8213 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8214 effect(KILL cr);
8216 format %{ "salq $dst, $shift" %}
8217 opcode(0xC1, 0x4); /* C1 /4 ib */
8218 ins_encode(REX_mem_wide(dst), OpcP,
8219 RM_opc_mem(secondary, dst), Con8or32(shift));
8220 ins_pipe(ialu_mem_imm);
8221 %}
8223 // Shift Left by variable
8224 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8225 %{
8226 match(Set dst (LShiftL dst shift));
8227 effect(KILL cr);
8229 format %{ "salq $dst, $shift" %}
8230 opcode(0xD3, 0x4); /* D3 /4 */
8231 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8232 ins_pipe(ialu_reg_reg);
8233 %}
8235 // Shift Left by variable
8236 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8237 %{
8238 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8239 effect(KILL cr);
8241 format %{ "salq $dst, $shift" %}
8242 opcode(0xD3, 0x4); /* D3 /4 */
8243 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8244 ins_pipe(ialu_mem_reg);
8245 %}
8247 // Arithmetic shift right by one
8248 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8249 %{
8250 match(Set dst (RShiftL dst shift));
8251 effect(KILL cr);
8253 format %{ "sarq $dst, $shift" %}
8254 opcode(0xD1, 0x7); /* D1 /7 */
8255 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8256 ins_pipe(ialu_reg);
8257 %}
8259 // Arithmetic shift right by one
8260 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8261 %{
8262 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8263 effect(KILL cr);
8265 format %{ "sarq $dst, $shift" %}
8266 opcode(0xD1, 0x7); /* D1 /7 */
8267 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8268 ins_pipe(ialu_mem_imm);
8269 %}
8271 // Arithmetic Shift Right by 8-bit immediate
8272 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8273 %{
8274 match(Set dst (RShiftL dst shift));
8275 effect(KILL cr);
8277 format %{ "sarq $dst, $shift" %}
8278 opcode(0xC1, 0x7); /* C1 /7 ib */
8279 ins_encode(reg_opc_imm_wide(dst, shift));
8280 ins_pipe(ialu_mem_imm);
8281 %}
8283 // Arithmetic Shift Right by 8-bit immediate
8284 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8285 %{
8286 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8287 effect(KILL cr);
8289 format %{ "sarq $dst, $shift" %}
8290 opcode(0xC1, 0x7); /* C1 /7 ib */
8291 ins_encode(REX_mem_wide(dst), OpcP,
8292 RM_opc_mem(secondary, dst), Con8or32(shift));
8293 ins_pipe(ialu_mem_imm);
8294 %}
8296 // Arithmetic Shift Right by variable
8297 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8298 %{
8299 match(Set dst (RShiftL dst shift));
8300 effect(KILL cr);
8302 format %{ "sarq $dst, $shift" %}
8303 opcode(0xD3, 0x7); /* D3 /7 */
8304 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8305 ins_pipe(ialu_reg_reg);
8306 %}
8308 // Arithmetic Shift Right by variable
8309 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8310 %{
8311 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8312 effect(KILL cr);
8314 format %{ "sarq $dst, $shift" %}
8315 opcode(0xD3, 0x7); /* D3 /7 */
8316 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8317 ins_pipe(ialu_mem_reg);
8318 %}
8320 // Logical shift right by one
8321 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8322 %{
8323 match(Set dst (URShiftL dst shift));
8324 effect(KILL cr);
8326 format %{ "shrq $dst, $shift" %}
8327 opcode(0xD1, 0x5); /* D1 /5 */
8328 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8329 ins_pipe(ialu_reg);
8330 %}
8332 // Logical shift right by one
8333 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8334 %{
8335 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8336 effect(KILL cr);
8338 format %{ "shrq $dst, $shift" %}
8339 opcode(0xD1, 0x5); /* D1 /5 */
8340 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8341 ins_pipe(ialu_mem_imm);
8342 %}
8344 // Logical Shift Right by 8-bit immediate
8345 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8346 %{
8347 match(Set dst (URShiftL dst shift));
8348 effect(KILL cr);
8350 format %{ "shrq $dst, $shift" %}
8351 opcode(0xC1, 0x5); /* C1 /5 ib */
8352 ins_encode(reg_opc_imm_wide(dst, shift));
8353 ins_pipe(ialu_reg);
8354 %}
8357 // Logical Shift Right by 8-bit immediate
8358 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8359 %{
8360 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8361 effect(KILL cr);
8363 format %{ "shrq $dst, $shift" %}
8364 opcode(0xC1, 0x5); /* C1 /5 ib */
8365 ins_encode(REX_mem_wide(dst), OpcP,
8366 RM_opc_mem(secondary, dst), Con8or32(shift));
8367 ins_pipe(ialu_mem_imm);
8368 %}
8370 // Logical Shift Right by variable
8371 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8372 %{
8373 match(Set dst (URShiftL dst shift));
8374 effect(KILL cr);
8376 format %{ "shrq $dst, $shift" %}
8377 opcode(0xD3, 0x5); /* D3 /5 */
8378 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8379 ins_pipe(ialu_reg_reg);
8380 %}
8382 // Logical Shift Right by variable
8383 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8384 %{
8385 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8386 effect(KILL cr);
8388 format %{ "shrq $dst, $shift" %}
8389 opcode(0xD3, 0x5); /* D3 /5 */
8390 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8391 ins_pipe(ialu_mem_reg);
8392 %}
8394 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8395 // This idiom is used by the compiler for the i2b bytecode.
8396 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8397 %{
8398 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8400 format %{ "movsbl $dst, $src\t# i2b" %}
8401 opcode(0x0F, 0xBE);
8402 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8403 ins_pipe(ialu_reg_reg);
8404 %}
8406 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8407 // This idiom is used by the compiler the i2s bytecode.
8408 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8409 %{
8410 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8412 format %{ "movswl $dst, $src\t# i2s" %}
8413 opcode(0x0F, 0xBF);
8414 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8415 ins_pipe(ialu_reg_reg);
8416 %}
8418 // ROL/ROR instructions
8420 // ROL expand
8421 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8422 effect(KILL cr, USE_DEF dst);
8424 format %{ "roll $dst" %}
8425 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8426 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8427 ins_pipe(ialu_reg);
8428 %}
8430 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8431 effect(USE_DEF dst, USE shift, KILL cr);
8433 format %{ "roll $dst, $shift" %}
8434 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8435 ins_encode( reg_opc_imm(dst, shift) );
8436 ins_pipe(ialu_reg);
8437 %}
8439 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8440 %{
8441 effect(USE_DEF dst, USE shift, KILL cr);
8443 format %{ "roll $dst, $shift" %}
8444 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8445 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8446 ins_pipe(ialu_reg_reg);
8447 %}
8448 // end of ROL expand
8450 // Rotate Left by one
8451 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8452 %{
8453 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8455 expand %{
8456 rolI_rReg_imm1(dst, cr);
8457 %}
8458 %}
8460 // Rotate Left by 8-bit immediate
8461 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8462 %{
8463 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8464 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8466 expand %{
8467 rolI_rReg_imm8(dst, lshift, cr);
8468 %}
8469 %}
8471 // Rotate Left by variable
8472 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8473 %{
8474 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8476 expand %{
8477 rolI_rReg_CL(dst, shift, cr);
8478 %}
8479 %}
8481 // Rotate Left by variable
8482 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8483 %{
8484 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8486 expand %{
8487 rolI_rReg_CL(dst, shift, cr);
8488 %}
8489 %}
8491 // ROR expand
8492 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8493 %{
8494 effect(USE_DEF dst, KILL cr);
8496 format %{ "rorl $dst" %}
8497 opcode(0xD1, 0x1); /* D1 /1 */
8498 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8499 ins_pipe(ialu_reg);
8500 %}
8502 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8503 %{
8504 effect(USE_DEF dst, USE shift, KILL cr);
8506 format %{ "rorl $dst, $shift" %}
8507 opcode(0xC1, 0x1); /* C1 /1 ib */
8508 ins_encode(reg_opc_imm(dst, shift));
8509 ins_pipe(ialu_reg);
8510 %}
8512 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8513 %{
8514 effect(USE_DEF dst, USE shift, KILL cr);
8516 format %{ "rorl $dst, $shift" %}
8517 opcode(0xD3, 0x1); /* D3 /1 */
8518 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8519 ins_pipe(ialu_reg_reg);
8520 %}
8521 // end of ROR expand
8523 // Rotate Right by one
8524 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8525 %{
8526 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8528 expand %{
8529 rorI_rReg_imm1(dst, cr);
8530 %}
8531 %}
8533 // Rotate Right by 8-bit immediate
8534 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8535 %{
8536 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8537 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8539 expand %{
8540 rorI_rReg_imm8(dst, rshift, cr);
8541 %}
8542 %}
8544 // Rotate Right by variable
8545 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8546 %{
8547 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8549 expand %{
8550 rorI_rReg_CL(dst, shift, cr);
8551 %}
8552 %}
8554 // Rotate Right by variable
8555 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8556 %{
8557 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8559 expand %{
8560 rorI_rReg_CL(dst, shift, cr);
8561 %}
8562 %}
8564 // for long rotate
8565 // ROL expand
8566 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
8567 effect(USE_DEF dst, KILL cr);
8569 format %{ "rolq $dst" %}
8570 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8571 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8572 ins_pipe(ialu_reg);
8573 %}
8575 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
8576 effect(USE_DEF dst, USE shift, KILL cr);
8578 format %{ "rolq $dst, $shift" %}
8579 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8580 ins_encode( reg_opc_imm_wide(dst, shift) );
8581 ins_pipe(ialu_reg);
8582 %}
8584 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8585 %{
8586 effect(USE_DEF dst, USE shift, KILL cr);
8588 format %{ "rolq $dst, $shift" %}
8589 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8590 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8591 ins_pipe(ialu_reg_reg);
8592 %}
8593 // end of ROL expand
8595 // Rotate Left by one
8596 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8597 %{
8598 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8600 expand %{
8601 rolL_rReg_imm1(dst, cr);
8602 %}
8603 %}
8605 // Rotate Left by 8-bit immediate
8606 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8607 %{
8608 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8609 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8611 expand %{
8612 rolL_rReg_imm8(dst, lshift, cr);
8613 %}
8614 %}
8616 // Rotate Left by variable
8617 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8618 %{
8619 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
8621 expand %{
8622 rolL_rReg_CL(dst, shift, cr);
8623 %}
8624 %}
8626 // Rotate Left by variable
8627 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8628 %{
8629 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
8631 expand %{
8632 rolL_rReg_CL(dst, shift, cr);
8633 %}
8634 %}
8636 // ROR expand
8637 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
8638 %{
8639 effect(USE_DEF dst, KILL cr);
8641 format %{ "rorq $dst" %}
8642 opcode(0xD1, 0x1); /* D1 /1 */
8643 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8644 ins_pipe(ialu_reg);
8645 %}
8647 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
8648 %{
8649 effect(USE_DEF dst, USE shift, KILL cr);
8651 format %{ "rorq $dst, $shift" %}
8652 opcode(0xC1, 0x1); /* C1 /1 ib */
8653 ins_encode(reg_opc_imm_wide(dst, shift));
8654 ins_pipe(ialu_reg);
8655 %}
8657 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8658 %{
8659 effect(USE_DEF dst, USE shift, KILL cr);
8661 format %{ "rorq $dst, $shift" %}
8662 opcode(0xD3, 0x1); /* D3 /1 */
8663 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8664 ins_pipe(ialu_reg_reg);
8665 %}
8666 // end of ROR expand
8668 // Rotate Right by one
8669 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8670 %{
8671 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8673 expand %{
8674 rorL_rReg_imm1(dst, cr);
8675 %}
8676 %}
8678 // Rotate Right by 8-bit immediate
8679 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8680 %{
8681 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8682 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8684 expand %{
8685 rorL_rReg_imm8(dst, rshift, cr);
8686 %}
8687 %}
8689 // Rotate Right by variable
8690 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8691 %{
8692 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
8694 expand %{
8695 rorL_rReg_CL(dst, shift, cr);
8696 %}
8697 %}
8699 // Rotate Right by variable
8700 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8701 %{
8702 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
8704 expand %{
8705 rorL_rReg_CL(dst, shift, cr);
8706 %}
8707 %}
8709 // Logical Instructions
8711 // Integer Logical Instructions
8713 // And Instructions
8714 // And Register with Register
8715 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8716 %{
8717 match(Set dst (AndI dst src));
8718 effect(KILL cr);
8720 format %{ "andl $dst, $src\t# int" %}
8721 opcode(0x23);
8722 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8723 ins_pipe(ialu_reg_reg);
8724 %}
8726 // And Register with Immediate 255
8727 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
8728 %{
8729 match(Set dst (AndI dst src));
8731 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
8732 opcode(0x0F, 0xB6);
8733 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8734 ins_pipe(ialu_reg);
8735 %}
8737 // And Register with Immediate 255 and promote to long
8738 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
8739 %{
8740 match(Set dst (ConvI2L (AndI src mask)));
8742 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
8743 opcode(0x0F, 0xB6);
8744 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8745 ins_pipe(ialu_reg);
8746 %}
8748 // And Register with Immediate 65535
8749 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
8750 %{
8751 match(Set dst (AndI dst src));
8753 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
8754 opcode(0x0F, 0xB7);
8755 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8756 ins_pipe(ialu_reg);
8757 %}
8759 // And Register with Immediate 65535 and promote to long
8760 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
8761 %{
8762 match(Set dst (ConvI2L (AndI src mask)));
8764 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
8765 opcode(0x0F, 0xB7);
8766 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8767 ins_pipe(ialu_reg);
8768 %}
8770 // And Register with Immediate
8771 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8772 %{
8773 match(Set dst (AndI dst src));
8774 effect(KILL cr);
8776 format %{ "andl $dst, $src\t# int" %}
8777 opcode(0x81, 0x04); /* Opcode 81 /4 */
8778 ins_encode(OpcSErm(dst, src), Con8or32(src));
8779 ins_pipe(ialu_reg);
8780 %}
8782 // And Register with Memory
8783 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8784 %{
8785 match(Set dst (AndI dst (LoadI src)));
8786 effect(KILL cr);
8788 ins_cost(125);
8789 format %{ "andl $dst, $src\t# int" %}
8790 opcode(0x23);
8791 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8792 ins_pipe(ialu_reg_mem);
8793 %}
8795 // And Memory with Register
8796 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8797 %{
8798 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8799 effect(KILL cr);
8801 ins_cost(150);
8802 format %{ "andl $dst, $src\t# int" %}
8803 opcode(0x21); /* Opcode 21 /r */
8804 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8805 ins_pipe(ialu_mem_reg);
8806 %}
8808 // And Memory with Immediate
8809 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
8810 %{
8811 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8812 effect(KILL cr);
8814 ins_cost(125);
8815 format %{ "andl $dst, $src\t# int" %}
8816 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8817 ins_encode(REX_mem(dst), OpcSE(src),
8818 RM_opc_mem(secondary, dst), Con8or32(src));
8819 ins_pipe(ialu_mem_imm);
8820 %}
8822 // Or Instructions
8823 // Or Register with Register
8824 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8825 %{
8826 match(Set dst (OrI dst src));
8827 effect(KILL cr);
8829 format %{ "orl $dst, $src\t# int" %}
8830 opcode(0x0B);
8831 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8832 ins_pipe(ialu_reg_reg);
8833 %}
8835 // Or Register with Immediate
8836 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8837 %{
8838 match(Set dst (OrI dst src));
8839 effect(KILL cr);
8841 format %{ "orl $dst, $src\t# int" %}
8842 opcode(0x81, 0x01); /* Opcode 81 /1 id */
8843 ins_encode(OpcSErm(dst, src), Con8or32(src));
8844 ins_pipe(ialu_reg);
8845 %}
8847 // Or Register with Memory
8848 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8849 %{
8850 match(Set dst (OrI dst (LoadI src)));
8851 effect(KILL cr);
8853 ins_cost(125);
8854 format %{ "orl $dst, $src\t# int" %}
8855 opcode(0x0B);
8856 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8857 ins_pipe(ialu_reg_mem);
8858 %}
8860 // Or Memory with Register
8861 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8862 %{
8863 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8864 effect(KILL cr);
8866 ins_cost(150);
8867 format %{ "orl $dst, $src\t# int" %}
8868 opcode(0x09); /* Opcode 09 /r */
8869 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8870 ins_pipe(ialu_mem_reg);
8871 %}
8873 // Or Memory with Immediate
8874 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
8875 %{
8876 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8877 effect(KILL cr);
8879 ins_cost(125);
8880 format %{ "orl $dst, $src\t# int" %}
8881 opcode(0x81, 0x1); /* Opcode 81 /1 id */
8882 ins_encode(REX_mem(dst), OpcSE(src),
8883 RM_opc_mem(secondary, dst), Con8or32(src));
8884 ins_pipe(ialu_mem_imm);
8885 %}
8887 // Xor Instructions
8888 // Xor Register with Register
8889 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8890 %{
8891 match(Set dst (XorI dst src));
8892 effect(KILL cr);
8894 format %{ "xorl $dst, $src\t# int" %}
8895 opcode(0x33);
8896 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8897 ins_pipe(ialu_reg_reg);
8898 %}
8900 // Xor Register with Immediate -1
8901 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
8902 match(Set dst (XorI dst imm));
8904 format %{ "not $dst" %}
8905 ins_encode %{
8906 __ notl($dst$$Register);
8907 %}
8908 ins_pipe(ialu_reg);
8909 %}
8911 // Xor Register with Immediate
8912 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8913 %{
8914 match(Set dst (XorI dst src));
8915 effect(KILL cr);
8917 format %{ "xorl $dst, $src\t# int" %}
8918 opcode(0x81, 0x06); /* Opcode 81 /6 id */
8919 ins_encode(OpcSErm(dst, src), Con8or32(src));
8920 ins_pipe(ialu_reg);
8921 %}
8923 // Xor Register with Memory
8924 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8925 %{
8926 match(Set dst (XorI dst (LoadI src)));
8927 effect(KILL cr);
8929 ins_cost(125);
8930 format %{ "xorl $dst, $src\t# int" %}
8931 opcode(0x33);
8932 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8933 ins_pipe(ialu_reg_mem);
8934 %}
8936 // Xor Memory with Register
8937 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8938 %{
8939 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8940 effect(KILL cr);
8942 ins_cost(150);
8943 format %{ "xorl $dst, $src\t# int" %}
8944 opcode(0x31); /* Opcode 31 /r */
8945 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8946 ins_pipe(ialu_mem_reg);
8947 %}
8949 // Xor Memory with Immediate
8950 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
8951 %{
8952 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8953 effect(KILL cr);
8955 ins_cost(125);
8956 format %{ "xorl $dst, $src\t# int" %}
8957 opcode(0x81, 0x6); /* Opcode 81 /6 id */
8958 ins_encode(REX_mem(dst), OpcSE(src),
8959 RM_opc_mem(secondary, dst), Con8or32(src));
8960 ins_pipe(ialu_mem_imm);
8961 %}
8964 // Long Logical Instructions
8966 // And Instructions
8967 // And Register with Register
8968 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8969 %{
8970 match(Set dst (AndL dst src));
8971 effect(KILL cr);
8973 format %{ "andq $dst, $src\t# long" %}
8974 opcode(0x23);
8975 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8976 ins_pipe(ialu_reg_reg);
8977 %}
8979 // And Register with Immediate 255
8980 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
8981 %{
8982 match(Set dst (AndL dst src));
8984 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
8985 opcode(0x0F, 0xB6);
8986 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8987 ins_pipe(ialu_reg);
8988 %}
8990 // And Register with Immediate 65535
8991 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
8992 %{
8993 match(Set dst (AndL dst src));
8995 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
8996 opcode(0x0F, 0xB7);
8997 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8998 ins_pipe(ialu_reg);
8999 %}
9001 // And Register with Immediate
9002 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9003 %{
9004 match(Set dst (AndL dst src));
9005 effect(KILL cr);
9007 format %{ "andq $dst, $src\t# long" %}
9008 opcode(0x81, 0x04); /* Opcode 81 /4 */
9009 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9010 ins_pipe(ialu_reg);
9011 %}
9013 // And Register with Memory
9014 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9015 %{
9016 match(Set dst (AndL dst (LoadL src)));
9017 effect(KILL cr);
9019 ins_cost(125);
9020 format %{ "andq $dst, $src\t# long" %}
9021 opcode(0x23);
9022 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9023 ins_pipe(ialu_reg_mem);
9024 %}
9026 // And Memory with Register
9027 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9028 %{
9029 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9030 effect(KILL cr);
9032 ins_cost(150);
9033 format %{ "andq $dst, $src\t# long" %}
9034 opcode(0x21); /* Opcode 21 /r */
9035 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9036 ins_pipe(ialu_mem_reg);
9037 %}
9039 // And Memory with Immediate
9040 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9041 %{
9042 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9043 effect(KILL cr);
9045 ins_cost(125);
9046 format %{ "andq $dst, $src\t# long" %}
9047 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9048 ins_encode(REX_mem_wide(dst), OpcSE(src),
9049 RM_opc_mem(secondary, dst), Con8or32(src));
9050 ins_pipe(ialu_mem_imm);
9051 %}
9053 // Or Instructions
9054 // Or Register with Register
9055 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9056 %{
9057 match(Set dst (OrL dst src));
9058 effect(KILL cr);
9060 format %{ "orq $dst, $src\t# long" %}
9061 opcode(0x0B);
9062 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9063 ins_pipe(ialu_reg_reg);
9064 %}
9066 // Use any_RegP to match R15 (TLS register) without spilling.
9067 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9068 match(Set dst (OrL dst (CastP2X src)));
9069 effect(KILL cr);
9071 format %{ "orq $dst, $src\t# long" %}
9072 opcode(0x0B);
9073 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9074 ins_pipe(ialu_reg_reg);
9075 %}
9078 // Or Register with Immediate
9079 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9080 %{
9081 match(Set dst (OrL dst src));
9082 effect(KILL cr);
9084 format %{ "orq $dst, $src\t# long" %}
9085 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9086 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9087 ins_pipe(ialu_reg);
9088 %}
9090 // Or Register with Memory
9091 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9092 %{
9093 match(Set dst (OrL dst (LoadL src)));
9094 effect(KILL cr);
9096 ins_cost(125);
9097 format %{ "orq $dst, $src\t# long" %}
9098 opcode(0x0B);
9099 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9100 ins_pipe(ialu_reg_mem);
9101 %}
9103 // Or Memory with Register
9104 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9105 %{
9106 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9107 effect(KILL cr);
9109 ins_cost(150);
9110 format %{ "orq $dst, $src\t# long" %}
9111 opcode(0x09); /* Opcode 09 /r */
9112 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9113 ins_pipe(ialu_mem_reg);
9114 %}
9116 // Or Memory with Immediate
9117 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9118 %{
9119 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9120 effect(KILL cr);
9122 ins_cost(125);
9123 format %{ "orq $dst, $src\t# long" %}
9124 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9125 ins_encode(REX_mem_wide(dst), OpcSE(src),
9126 RM_opc_mem(secondary, dst), Con8or32(src));
9127 ins_pipe(ialu_mem_imm);
9128 %}
9130 // Xor Instructions
9131 // Xor Register with Register
9132 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9133 %{
9134 match(Set dst (XorL dst src));
9135 effect(KILL cr);
9137 format %{ "xorq $dst, $src\t# long" %}
9138 opcode(0x33);
9139 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9140 ins_pipe(ialu_reg_reg);
9141 %}
9143 // Xor Register with Immediate -1
9144 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9145 match(Set dst (XorL dst imm));
9147 format %{ "notq $dst" %}
9148 ins_encode %{
9149 __ notq($dst$$Register);
9150 %}
9151 ins_pipe(ialu_reg);
9152 %}
9154 // Xor Register with Immediate
9155 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9156 %{
9157 match(Set dst (XorL dst src));
9158 effect(KILL cr);
9160 format %{ "xorq $dst, $src\t# long" %}
9161 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9162 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9163 ins_pipe(ialu_reg);
9164 %}
9166 // Xor Register with Memory
9167 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9168 %{
9169 match(Set dst (XorL dst (LoadL src)));
9170 effect(KILL cr);
9172 ins_cost(125);
9173 format %{ "xorq $dst, $src\t# long" %}
9174 opcode(0x33);
9175 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9176 ins_pipe(ialu_reg_mem);
9177 %}
9179 // Xor Memory with Register
9180 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9181 %{
9182 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9183 effect(KILL cr);
9185 ins_cost(150);
9186 format %{ "xorq $dst, $src\t# long" %}
9187 opcode(0x31); /* Opcode 31 /r */
9188 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9189 ins_pipe(ialu_mem_reg);
9190 %}
9192 // Xor Memory with Immediate
9193 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9194 %{
9195 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9196 effect(KILL cr);
9198 ins_cost(125);
9199 format %{ "xorq $dst, $src\t# long" %}
9200 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9201 ins_encode(REX_mem_wide(dst), OpcSE(src),
9202 RM_opc_mem(secondary, dst), Con8or32(src));
9203 ins_pipe(ialu_mem_imm);
9204 %}
9206 // Convert Int to Boolean
9207 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9208 %{
9209 match(Set dst (Conv2B src));
9210 effect(KILL cr);
9212 format %{ "testl $src, $src\t# ci2b\n\t"
9213 "setnz $dst\n\t"
9214 "movzbl $dst, $dst" %}
9215 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9216 setNZ_reg(dst),
9217 REX_reg_breg(dst, dst), // movzbl
9218 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9219 ins_pipe(pipe_slow); // XXX
9220 %}
9222 // Convert Pointer to Boolean
9223 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9224 %{
9225 match(Set dst (Conv2B src));
9226 effect(KILL cr);
9228 format %{ "testq $src, $src\t# cp2b\n\t"
9229 "setnz $dst\n\t"
9230 "movzbl $dst, $dst" %}
9231 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9232 setNZ_reg(dst),
9233 REX_reg_breg(dst, dst), // movzbl
9234 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9235 ins_pipe(pipe_slow); // XXX
9236 %}
9238 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9239 %{
9240 match(Set dst (CmpLTMask p q));
9241 effect(KILL cr);
9243 ins_cost(400);
9244 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9245 "setlt $dst\n\t"
9246 "movzbl $dst, $dst\n\t"
9247 "negl $dst" %}
9248 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9249 setLT_reg(dst),
9250 REX_reg_breg(dst, dst), // movzbl
9251 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9252 neg_reg(dst));
9253 ins_pipe(pipe_slow);
9254 %}
9256 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9257 %{
9258 match(Set dst (CmpLTMask dst zero));
9259 effect(KILL cr);
9261 ins_cost(100);
9262 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9263 ins_encode %{
9264 __ sarl($dst$$Register, 31);
9265 %}
9266 ins_pipe(ialu_reg);
9267 %}
9269 /* Better to save a register than avoid a branch */
9270 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9271 %{
9272 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9273 effect(KILL cr);
9274 ins_cost(300);
9275 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
9276 "jge done\n\t"
9277 "addl $p,$y\n"
9278 "done: " %}
9279 ins_encode %{
9280 Register Rp = $p$$Register;
9281 Register Rq = $q$$Register;
9282 Register Ry = $y$$Register;
9283 Label done;
9284 __ subl(Rp, Rq);
9285 __ jccb(Assembler::greaterEqual, done);
9286 __ addl(Rp, Ry);
9287 __ bind(done);
9288 %}
9289 ins_pipe(pipe_cmplt);
9290 %}
9292 /* Better to save a register than avoid a branch */
9293 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9294 %{
9295 match(Set y (AndI (CmpLTMask p q) y));
9296 effect(KILL cr);
9298 ins_cost(300);
9300 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
9301 "jlt done\n\t"
9302 "xorl $y, $y\n"
9303 "done: " %}
9304 ins_encode %{
9305 Register Rp = $p$$Register;
9306 Register Rq = $q$$Register;
9307 Register Ry = $y$$Register;
9308 Label done;
9309 __ cmpl(Rp, Rq);
9310 __ jccb(Assembler::less, done);
9311 __ xorl(Ry, Ry);
9312 __ bind(done);
9313 %}
9314 ins_pipe(pipe_cmplt);
9315 %}
9318 //---------- FP Instructions------------------------------------------------
9320 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9321 %{
9322 match(Set cr (CmpF src1 src2));
9324 ins_cost(145);
9325 format %{ "ucomiss $src1, $src2\n\t"
9326 "jnp,s exit\n\t"
9327 "pushfq\t# saw NaN, set CF\n\t"
9328 "andq [rsp], #0xffffff2b\n\t"
9329 "popfq\n"
9330 "exit:" %}
9331 ins_encode %{
9332 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9333 emit_cmpfp_fixup(_masm);
9334 %}
9335 ins_pipe(pipe_slow);
9336 %}
9338 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
9339 match(Set cr (CmpF src1 src2));
9341 ins_cost(100);
9342 format %{ "ucomiss $src1, $src2" %}
9343 ins_encode %{
9344 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9345 %}
9346 ins_pipe(pipe_slow);
9347 %}
9349 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
9350 %{
9351 match(Set cr (CmpF src1 (LoadF src2)));
9353 ins_cost(145);
9354 format %{ "ucomiss $src1, $src2\n\t"
9355 "jnp,s exit\n\t"
9356 "pushfq\t# saw NaN, set CF\n\t"
9357 "andq [rsp], #0xffffff2b\n\t"
9358 "popfq\n"
9359 "exit:" %}
9360 ins_encode %{
9361 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9362 emit_cmpfp_fixup(_masm);
9363 %}
9364 ins_pipe(pipe_slow);
9365 %}
9367 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
9368 match(Set cr (CmpF src1 (LoadF src2)));
9370 ins_cost(100);
9371 format %{ "ucomiss $src1, $src2" %}
9372 ins_encode %{
9373 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9374 %}
9375 ins_pipe(pipe_slow);
9376 %}
9378 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
9379 match(Set cr (CmpF src con));
9381 ins_cost(145);
9382 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9383 "jnp,s exit\n\t"
9384 "pushfq\t# saw NaN, set CF\n\t"
9385 "andq [rsp], #0xffffff2b\n\t"
9386 "popfq\n"
9387 "exit:" %}
9388 ins_encode %{
9389 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9390 emit_cmpfp_fixup(_masm);
9391 %}
9392 ins_pipe(pipe_slow);
9393 %}
9395 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
9396 match(Set cr (CmpF src con));
9397 ins_cost(100);
9398 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
9399 ins_encode %{
9400 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9401 %}
9402 ins_pipe(pipe_slow);
9403 %}
9405 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9406 %{
9407 match(Set cr (CmpD src1 src2));
9409 ins_cost(145);
9410 format %{ "ucomisd $src1, $src2\n\t"
9411 "jnp,s exit\n\t"
9412 "pushfq\t# saw NaN, set CF\n\t"
9413 "andq [rsp], #0xffffff2b\n\t"
9414 "popfq\n"
9415 "exit:" %}
9416 ins_encode %{
9417 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9418 emit_cmpfp_fixup(_masm);
9419 %}
9420 ins_pipe(pipe_slow);
9421 %}
9423 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
9424 match(Set cr (CmpD src1 src2));
9426 ins_cost(100);
9427 format %{ "ucomisd $src1, $src2 test" %}
9428 ins_encode %{
9429 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9430 %}
9431 ins_pipe(pipe_slow);
9432 %}
9434 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
9435 %{
9436 match(Set cr (CmpD src1 (LoadD src2)));
9438 ins_cost(145);
9439 format %{ "ucomisd $src1, $src2\n\t"
9440 "jnp,s exit\n\t"
9441 "pushfq\t# saw NaN, set CF\n\t"
9442 "andq [rsp], #0xffffff2b\n\t"
9443 "popfq\n"
9444 "exit:" %}
9445 ins_encode %{
9446 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9447 emit_cmpfp_fixup(_masm);
9448 %}
9449 ins_pipe(pipe_slow);
9450 %}
9452 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
9453 match(Set cr (CmpD src1 (LoadD src2)));
9455 ins_cost(100);
9456 format %{ "ucomisd $src1, $src2" %}
9457 ins_encode %{
9458 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9459 %}
9460 ins_pipe(pipe_slow);
9461 %}
9463 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
9464 match(Set cr (CmpD src con));
9466 ins_cost(145);
9467 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9468 "jnp,s exit\n\t"
9469 "pushfq\t# saw NaN, set CF\n\t"
9470 "andq [rsp], #0xffffff2b\n\t"
9471 "popfq\n"
9472 "exit:" %}
9473 ins_encode %{
9474 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9475 emit_cmpfp_fixup(_masm);
9476 %}
9477 ins_pipe(pipe_slow);
9478 %}
9480 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
9481 match(Set cr (CmpD src con));
9482 ins_cost(100);
9483 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
9484 ins_encode %{
9485 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9486 %}
9487 ins_pipe(pipe_slow);
9488 %}
9490 // Compare into -1,0,1
9491 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9492 %{
9493 match(Set dst (CmpF3 src1 src2));
9494 effect(KILL cr);
9496 ins_cost(275);
9497 format %{ "ucomiss $src1, $src2\n\t"
9498 "movl $dst, #-1\n\t"
9499 "jp,s done\n\t"
9500 "jb,s done\n\t"
9501 "setne $dst\n\t"
9502 "movzbl $dst, $dst\n"
9503 "done:" %}
9504 ins_encode %{
9505 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9506 emit_cmpfp3(_masm, $dst$$Register);
9507 %}
9508 ins_pipe(pipe_slow);
9509 %}
9511 // Compare into -1,0,1
9512 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
9513 %{
9514 match(Set dst (CmpF3 src1 (LoadF src2)));
9515 effect(KILL cr);
9517 ins_cost(275);
9518 format %{ "ucomiss $src1, $src2\n\t"
9519 "movl $dst, #-1\n\t"
9520 "jp,s done\n\t"
9521 "jb,s done\n\t"
9522 "setne $dst\n\t"
9523 "movzbl $dst, $dst\n"
9524 "done:" %}
9525 ins_encode %{
9526 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9527 emit_cmpfp3(_masm, $dst$$Register);
9528 %}
9529 ins_pipe(pipe_slow);
9530 %}
9532 // Compare into -1,0,1
9533 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
9534 match(Set dst (CmpF3 src con));
9535 effect(KILL cr);
9537 ins_cost(275);
9538 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9539 "movl $dst, #-1\n\t"
9540 "jp,s done\n\t"
9541 "jb,s done\n\t"
9542 "setne $dst\n\t"
9543 "movzbl $dst, $dst\n"
9544 "done:" %}
9545 ins_encode %{
9546 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9547 emit_cmpfp3(_masm, $dst$$Register);
9548 %}
9549 ins_pipe(pipe_slow);
9550 %}
9552 // Compare into -1,0,1
9553 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
9554 %{
9555 match(Set dst (CmpD3 src1 src2));
9556 effect(KILL cr);
9558 ins_cost(275);
9559 format %{ "ucomisd $src1, $src2\n\t"
9560 "movl $dst, #-1\n\t"
9561 "jp,s done\n\t"
9562 "jb,s done\n\t"
9563 "setne $dst\n\t"
9564 "movzbl $dst, $dst\n"
9565 "done:" %}
9566 ins_encode %{
9567 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9568 emit_cmpfp3(_masm, $dst$$Register);
9569 %}
9570 ins_pipe(pipe_slow);
9571 %}
9573 // Compare into -1,0,1
9574 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
9575 %{
9576 match(Set dst (CmpD3 src1 (LoadD src2)));
9577 effect(KILL cr);
9579 ins_cost(275);
9580 format %{ "ucomisd $src1, $src2\n\t"
9581 "movl $dst, #-1\n\t"
9582 "jp,s done\n\t"
9583 "jb,s done\n\t"
9584 "setne $dst\n\t"
9585 "movzbl $dst, $dst\n"
9586 "done:" %}
9587 ins_encode %{
9588 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9589 emit_cmpfp3(_masm, $dst$$Register);
9590 %}
9591 ins_pipe(pipe_slow);
9592 %}
9594 // Compare into -1,0,1
9595 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
9596 match(Set dst (CmpD3 src con));
9597 effect(KILL cr);
9599 ins_cost(275);
9600 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9601 "movl $dst, #-1\n\t"
9602 "jp,s done\n\t"
9603 "jb,s done\n\t"
9604 "setne $dst\n\t"
9605 "movzbl $dst, $dst\n"
9606 "done:" %}
9607 ins_encode %{
9608 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9609 emit_cmpfp3(_masm, $dst$$Register);
9610 %}
9611 ins_pipe(pipe_slow);
9612 %}
9614 // -----------Trig and Trancendental Instructions------------------------------
9615 instruct cosD_reg(regD dst) %{
9616 match(Set dst (CosD dst));
9618 format %{ "dcos $dst\n\t" %}
9619 opcode(0xD9, 0xFF);
9620 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9621 ins_pipe( pipe_slow );
9622 %}
9624 instruct sinD_reg(regD dst) %{
9625 match(Set dst (SinD dst));
9627 format %{ "dsin $dst\n\t" %}
9628 opcode(0xD9, 0xFE);
9629 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9630 ins_pipe( pipe_slow );
9631 %}
9633 instruct tanD_reg(regD dst) %{
9634 match(Set dst (TanD dst));
9636 format %{ "dtan $dst\n\t" %}
9637 ins_encode( Push_SrcXD(dst),
9638 Opcode(0xD9), Opcode(0xF2), //fptan
9639 Opcode(0xDD), Opcode(0xD8), //fstp st
9640 Push_ResultXD(dst) );
9641 ins_pipe( pipe_slow );
9642 %}
9644 instruct log10D_reg(regD dst) %{
9645 // The source and result Double operands in XMM registers
9646 match(Set dst (Log10D dst));
9647 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9648 // fyl2x ; compute log_10(2) * log_2(x)
9649 format %{ "fldlg2\t\t\t#Log10\n\t"
9650 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
9651 %}
9652 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
9653 Push_SrcXD(dst),
9654 Opcode(0xD9), Opcode(0xF1), // fyl2x
9655 Push_ResultXD(dst));
9657 ins_pipe( pipe_slow );
9658 %}
9660 instruct logD_reg(regD dst) %{
9661 // The source and result Double operands in XMM registers
9662 match(Set dst (LogD dst));
9663 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9664 // fyl2x ; compute log_e(2) * log_2(x)
9665 format %{ "fldln2\t\t\t#Log_e\n\t"
9666 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
9667 %}
9668 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9669 Push_SrcXD(dst),
9670 Opcode(0xD9), Opcode(0xF1), // fyl2x
9671 Push_ResultXD(dst));
9672 ins_pipe( pipe_slow );
9673 %}
9675 instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9676 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9677 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9678 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9679 ins_encode %{
9680 __ subptr(rsp, 8);
9681 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9682 __ fld_d(Address(rsp, 0));
9683 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9684 __ fld_d(Address(rsp, 0));
9685 __ fast_pow();
9686 __ fstp_d(Address(rsp, 0));
9687 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9688 __ addptr(rsp, 8);
9689 %}
9690 ins_pipe( pipe_slow );
9691 %}
9693 instruct expD_reg(regD dst, regD src, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9694 match(Set dst (ExpD src));
9695 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9696 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
9697 ins_encode %{
9698 __ subptr(rsp, 8);
9699 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9700 __ fld_d(Address(rsp, 0));
9701 __ fast_exp();
9702 __ fstp_d(Address(rsp, 0));
9703 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9704 __ addptr(rsp, 8);
9705 %}
9706 ins_pipe( pipe_slow );
9707 %}
9709 //----------Arithmetic Conversion Instructions---------------------------------
9711 instruct roundFloat_nop(regF dst)
9712 %{
9713 match(Set dst (RoundFloat dst));
9715 ins_cost(0);
9716 ins_encode();
9717 ins_pipe(empty);
9718 %}
9720 instruct roundDouble_nop(regD dst)
9721 %{
9722 match(Set dst (RoundDouble dst));
9724 ins_cost(0);
9725 ins_encode();
9726 ins_pipe(empty);
9727 %}
9729 instruct convF2D_reg_reg(regD dst, regF src)
9730 %{
9731 match(Set dst (ConvF2D src));
9733 format %{ "cvtss2sd $dst, $src" %}
9734 ins_encode %{
9735 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
9736 %}
9737 ins_pipe(pipe_slow); // XXX
9738 %}
9740 instruct convF2D_reg_mem(regD dst, memory src)
9741 %{
9742 match(Set dst (ConvF2D (LoadF src)));
9744 format %{ "cvtss2sd $dst, $src" %}
9745 ins_encode %{
9746 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
9747 %}
9748 ins_pipe(pipe_slow); // XXX
9749 %}
9751 instruct convD2F_reg_reg(regF dst, regD src)
9752 %{
9753 match(Set dst (ConvD2F src));
9755 format %{ "cvtsd2ss $dst, $src" %}
9756 ins_encode %{
9757 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
9758 %}
9759 ins_pipe(pipe_slow); // XXX
9760 %}
9762 instruct convD2F_reg_mem(regF dst, memory src)
9763 %{
9764 match(Set dst (ConvD2F (LoadD src)));
9766 format %{ "cvtsd2ss $dst, $src" %}
9767 ins_encode %{
9768 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
9769 %}
9770 ins_pipe(pipe_slow); // XXX
9771 %}
9773 // XXX do mem variants
9774 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
9775 %{
9776 match(Set dst (ConvF2I src));
9777 effect(KILL cr);
9779 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
9780 "cmpl $dst, #0x80000000\n\t"
9781 "jne,s done\n\t"
9782 "subq rsp, #8\n\t"
9783 "movss [rsp], $src\n\t"
9784 "call f2i_fixup\n\t"
9785 "popq $dst\n"
9786 "done: "%}
9787 ins_encode %{
9788 Label done;
9789 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
9790 __ cmpl($dst$$Register, 0x80000000);
9791 __ jccb(Assembler::notEqual, done);
9792 __ subptr(rsp, 8);
9793 __ movflt(Address(rsp, 0), $src$$XMMRegister);
9794 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
9795 __ pop($dst$$Register);
9796 __ bind(done);
9797 %}
9798 ins_pipe(pipe_slow);
9799 %}
9801 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
9802 %{
9803 match(Set dst (ConvF2L src));
9804 effect(KILL cr);
9806 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
9807 "cmpq $dst, [0x8000000000000000]\n\t"
9808 "jne,s done\n\t"
9809 "subq rsp, #8\n\t"
9810 "movss [rsp], $src\n\t"
9811 "call f2l_fixup\n\t"
9812 "popq $dst\n"
9813 "done: "%}
9814 ins_encode %{
9815 Label done;
9816 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
9817 __ cmp64($dst$$Register,
9818 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9819 __ jccb(Assembler::notEqual, done);
9820 __ subptr(rsp, 8);
9821 __ movflt(Address(rsp, 0), $src$$XMMRegister);
9822 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
9823 __ pop($dst$$Register);
9824 __ bind(done);
9825 %}
9826 ins_pipe(pipe_slow);
9827 %}
9829 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
9830 %{
9831 match(Set dst (ConvD2I src));
9832 effect(KILL cr);
9834 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
9835 "cmpl $dst, #0x80000000\n\t"
9836 "jne,s done\n\t"
9837 "subq rsp, #8\n\t"
9838 "movsd [rsp], $src\n\t"
9839 "call d2i_fixup\n\t"
9840 "popq $dst\n"
9841 "done: "%}
9842 ins_encode %{
9843 Label done;
9844 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
9845 __ cmpl($dst$$Register, 0x80000000);
9846 __ jccb(Assembler::notEqual, done);
9847 __ subptr(rsp, 8);
9848 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9849 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
9850 __ pop($dst$$Register);
9851 __ bind(done);
9852 %}
9853 ins_pipe(pipe_slow);
9854 %}
9856 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
9857 %{
9858 match(Set dst (ConvD2L src));
9859 effect(KILL cr);
9861 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
9862 "cmpq $dst, [0x8000000000000000]\n\t"
9863 "jne,s done\n\t"
9864 "subq rsp, #8\n\t"
9865 "movsd [rsp], $src\n\t"
9866 "call d2l_fixup\n\t"
9867 "popq $dst\n"
9868 "done: "%}
9869 ins_encode %{
9870 Label done;
9871 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
9872 __ cmp64($dst$$Register,
9873 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9874 __ jccb(Assembler::notEqual, done);
9875 __ subptr(rsp, 8);
9876 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9877 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
9878 __ pop($dst$$Register);
9879 __ bind(done);
9880 %}
9881 ins_pipe(pipe_slow);
9882 %}
9884 instruct convI2F_reg_reg(regF dst, rRegI src)
9885 %{
9886 predicate(!UseXmmI2F);
9887 match(Set dst (ConvI2F src));
9889 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
9890 ins_encode %{
9891 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
9892 %}
9893 ins_pipe(pipe_slow); // XXX
9894 %}
9896 instruct convI2F_reg_mem(regF dst, memory src)
9897 %{
9898 match(Set dst (ConvI2F (LoadI src)));
9900 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
9901 ins_encode %{
9902 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
9903 %}
9904 ins_pipe(pipe_slow); // XXX
9905 %}
9907 instruct convI2D_reg_reg(regD dst, rRegI src)
9908 %{
9909 predicate(!UseXmmI2D);
9910 match(Set dst (ConvI2D src));
9912 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
9913 ins_encode %{
9914 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
9915 %}
9916 ins_pipe(pipe_slow); // XXX
9917 %}
9919 instruct convI2D_reg_mem(regD dst, memory src)
9920 %{
9921 match(Set dst (ConvI2D (LoadI src)));
9923 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
9924 ins_encode %{
9925 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
9926 %}
9927 ins_pipe(pipe_slow); // XXX
9928 %}
9930 instruct convXI2F_reg(regF dst, rRegI src)
9931 %{
9932 predicate(UseXmmI2F);
9933 match(Set dst (ConvI2F src));
9935 format %{ "movdl $dst, $src\n\t"
9936 "cvtdq2psl $dst, $dst\t# i2f" %}
9937 ins_encode %{
9938 __ movdl($dst$$XMMRegister, $src$$Register);
9939 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
9940 %}
9941 ins_pipe(pipe_slow); // XXX
9942 %}
9944 instruct convXI2D_reg(regD dst, rRegI src)
9945 %{
9946 predicate(UseXmmI2D);
9947 match(Set dst (ConvI2D src));
9949 format %{ "movdl $dst, $src\n\t"
9950 "cvtdq2pdl $dst, $dst\t# i2d" %}
9951 ins_encode %{
9952 __ movdl($dst$$XMMRegister, $src$$Register);
9953 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
9954 %}
9955 ins_pipe(pipe_slow); // XXX
9956 %}
9958 instruct convL2F_reg_reg(regF dst, rRegL src)
9959 %{
9960 match(Set dst (ConvL2F src));
9962 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
9963 ins_encode %{
9964 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
9965 %}
9966 ins_pipe(pipe_slow); // XXX
9967 %}
9969 instruct convL2F_reg_mem(regF dst, memory src)
9970 %{
9971 match(Set dst (ConvL2F (LoadL src)));
9973 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
9974 ins_encode %{
9975 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
9976 %}
9977 ins_pipe(pipe_slow); // XXX
9978 %}
9980 instruct convL2D_reg_reg(regD dst, rRegL src)
9981 %{
9982 match(Set dst (ConvL2D src));
9984 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
9985 ins_encode %{
9986 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
9987 %}
9988 ins_pipe(pipe_slow); // XXX
9989 %}
9991 instruct convL2D_reg_mem(regD dst, memory src)
9992 %{
9993 match(Set dst (ConvL2D (LoadL src)));
9995 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
9996 ins_encode %{
9997 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
9998 %}
9999 ins_pipe(pipe_slow); // XXX
10000 %}
10002 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10003 %{
10004 match(Set dst (ConvI2L src));
10006 ins_cost(125);
10007 format %{ "movslq $dst, $src\t# i2l" %}
10008 ins_encode %{
10009 __ movslq($dst$$Register, $src$$Register);
10010 %}
10011 ins_pipe(ialu_reg_reg);
10012 %}
10014 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10015 // %{
10016 // match(Set dst (ConvI2L src));
10017 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10018 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10019 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10020 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10021 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10022 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10024 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10025 // ins_encode(enc_copy(dst, src));
10026 // // opcode(0x63); // needs REX.W
10027 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10028 // ins_pipe(ialu_reg_reg);
10029 // %}
10031 // Zero-extend convert int to long
10032 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10033 %{
10034 match(Set dst (AndL (ConvI2L src) mask));
10036 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10037 ins_encode %{
10038 if ($dst$$reg != $src$$reg) {
10039 __ movl($dst$$Register, $src$$Register);
10040 }
10041 %}
10042 ins_pipe(ialu_reg_reg);
10043 %}
10045 // Zero-extend convert int to long
10046 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10047 %{
10048 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10050 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10051 ins_encode %{
10052 __ movl($dst$$Register, $src$$Address);
10053 %}
10054 ins_pipe(ialu_reg_mem);
10055 %}
10057 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10058 %{
10059 match(Set dst (AndL src mask));
10061 format %{ "movl $dst, $src\t# zero-extend long" %}
10062 ins_encode %{
10063 __ movl($dst$$Register, $src$$Register);
10064 %}
10065 ins_pipe(ialu_reg_reg);
10066 %}
10068 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10069 %{
10070 match(Set dst (ConvL2I src));
10072 format %{ "movl $dst, $src\t# l2i" %}
10073 ins_encode %{
10074 __ movl($dst$$Register, $src$$Register);
10075 %}
10076 ins_pipe(ialu_reg_reg);
10077 %}
10080 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10081 match(Set dst (MoveF2I src));
10082 effect(DEF dst, USE src);
10084 ins_cost(125);
10085 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10086 ins_encode %{
10087 __ movl($dst$$Register, Address(rsp, $src$$disp));
10088 %}
10089 ins_pipe(ialu_reg_mem);
10090 %}
10092 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10093 match(Set dst (MoveI2F src));
10094 effect(DEF dst, USE src);
10096 ins_cost(125);
10097 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10098 ins_encode %{
10099 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10100 %}
10101 ins_pipe(pipe_slow);
10102 %}
10104 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10105 match(Set dst (MoveD2L src));
10106 effect(DEF dst, USE src);
10108 ins_cost(125);
10109 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10110 ins_encode %{
10111 __ movq($dst$$Register, Address(rsp, $src$$disp));
10112 %}
10113 ins_pipe(ialu_reg_mem);
10114 %}
10116 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10117 predicate(!UseXmmLoadAndClearUpper);
10118 match(Set dst (MoveL2D src));
10119 effect(DEF dst, USE src);
10121 ins_cost(125);
10122 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10123 ins_encode %{
10124 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10125 %}
10126 ins_pipe(pipe_slow);
10127 %}
10129 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10130 predicate(UseXmmLoadAndClearUpper);
10131 match(Set dst (MoveL2D src));
10132 effect(DEF dst, USE src);
10134 ins_cost(125);
10135 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10136 ins_encode %{
10137 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10138 %}
10139 ins_pipe(pipe_slow);
10140 %}
10143 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10144 match(Set dst (MoveF2I src));
10145 effect(DEF dst, USE src);
10147 ins_cost(95); // XXX
10148 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10149 ins_encode %{
10150 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10151 %}
10152 ins_pipe(pipe_slow);
10153 %}
10155 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10156 match(Set dst (MoveI2F src));
10157 effect(DEF dst, USE src);
10159 ins_cost(100);
10160 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10161 ins_encode %{
10162 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10163 %}
10164 ins_pipe( ialu_mem_reg );
10165 %}
10167 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10168 match(Set dst (MoveD2L src));
10169 effect(DEF dst, USE src);
10171 ins_cost(95); // XXX
10172 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10173 ins_encode %{
10174 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10175 %}
10176 ins_pipe(pipe_slow);
10177 %}
10179 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10180 match(Set dst (MoveL2D src));
10181 effect(DEF dst, USE src);
10183 ins_cost(100);
10184 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10185 ins_encode %{
10186 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10187 %}
10188 ins_pipe(ialu_mem_reg);
10189 %}
10191 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10192 match(Set dst (MoveF2I src));
10193 effect(DEF dst, USE src);
10194 ins_cost(85);
10195 format %{ "movd $dst,$src\t# MoveF2I" %}
10196 ins_encode %{
10197 __ movdl($dst$$Register, $src$$XMMRegister);
10198 %}
10199 ins_pipe( pipe_slow );
10200 %}
10202 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10203 match(Set dst (MoveD2L src));
10204 effect(DEF dst, USE src);
10205 ins_cost(85);
10206 format %{ "movd $dst,$src\t# MoveD2L" %}
10207 ins_encode %{
10208 __ movdq($dst$$Register, $src$$XMMRegister);
10209 %}
10210 ins_pipe( pipe_slow );
10211 %}
10213 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10214 match(Set dst (MoveI2F src));
10215 effect(DEF dst, USE src);
10216 ins_cost(100);
10217 format %{ "movd $dst,$src\t# MoveI2F" %}
10218 ins_encode %{
10219 __ movdl($dst$$XMMRegister, $src$$Register);
10220 %}
10221 ins_pipe( pipe_slow );
10222 %}
10224 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10225 match(Set dst (MoveL2D src));
10226 effect(DEF dst, USE src);
10227 ins_cost(100);
10228 format %{ "movd $dst,$src\t# MoveL2D" %}
10229 ins_encode %{
10230 __ movdq($dst$$XMMRegister, $src$$Register);
10231 %}
10232 ins_pipe( pipe_slow );
10233 %}
10236 // =======================================================================
10237 // fast clearing of an array
10238 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10239 rFlagsReg cr)
10240 %{
10241 predicate(!UseFastStosb);
10242 match(Set dummy (ClearArray cnt base));
10243 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10245 format %{ "xorq rax, rax\t# ClearArray:\n\t"
10246 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
10247 ins_encode %{
10248 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
10249 %}
10250 ins_pipe(pipe_slow);
10251 %}
10253 instruct rep_fast_stosb(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10254 rFlagsReg cr)
10255 %{
10256 predicate(UseFastStosb);
10257 match(Set dummy (ClearArray cnt base));
10258 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10259 format %{ "xorq rax, rax\t# ClearArray:\n\t"
10260 "shlq rcx,3\t# Convert doublewords to bytes\n\t"
10261 "rep stosb\t# Store rax to *rdi++ while rcx--" %}
10262 ins_encode %{
10263 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
10264 %}
10265 ins_pipe( pipe_slow );
10266 %}
10268 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10269 rax_RegI result, regD tmp1, rFlagsReg cr)
10270 %{
10271 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10272 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10274 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10275 ins_encode %{
10276 __ string_compare($str1$$Register, $str2$$Register,
10277 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10278 $tmp1$$XMMRegister);
10279 %}
10280 ins_pipe( pipe_slow );
10281 %}
10283 // fast search of substring with known size.
10284 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10285 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10286 %{
10287 predicate(UseSSE42Intrinsics);
10288 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10289 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10291 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10292 ins_encode %{
10293 int icnt2 = (int)$int_cnt2$$constant;
10294 if (icnt2 >= 8) {
10295 // IndexOf for constant substrings with size >= 8 elements
10296 // which don't need to be loaded through stack.
10297 __ string_indexofC8($str1$$Register, $str2$$Register,
10298 $cnt1$$Register, $cnt2$$Register,
10299 icnt2, $result$$Register,
10300 $vec$$XMMRegister, $tmp$$Register);
10301 } else {
10302 // Small strings are loaded through stack if they cross page boundary.
10303 __ string_indexof($str1$$Register, $str2$$Register,
10304 $cnt1$$Register, $cnt2$$Register,
10305 icnt2, $result$$Register,
10306 $vec$$XMMRegister, $tmp$$Register);
10307 }
10308 %}
10309 ins_pipe( pipe_slow );
10310 %}
10312 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10313 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10314 %{
10315 predicate(UseSSE42Intrinsics);
10316 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10317 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10319 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10320 ins_encode %{
10321 __ string_indexof($str1$$Register, $str2$$Register,
10322 $cnt1$$Register, $cnt2$$Register,
10323 (-1), $result$$Register,
10324 $vec$$XMMRegister, $tmp$$Register);
10325 %}
10326 ins_pipe( pipe_slow );
10327 %}
10329 // fast string equals
10330 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
10331 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10332 %{
10333 match(Set result (StrEquals (Binary str1 str2) cnt));
10334 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
10336 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10337 ins_encode %{
10338 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
10339 $cnt$$Register, $result$$Register, $tmp3$$Register,
10340 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10341 %}
10342 ins_pipe( pipe_slow );
10343 %}
10345 // fast array equals
10346 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10347 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10348 %{
10349 match(Set result (AryEq ary1 ary2));
10350 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10351 //ins_cost(300);
10353 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10354 ins_encode %{
10355 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
10356 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10357 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10358 %}
10359 ins_pipe( pipe_slow );
10360 %}
10362 // encode char[] to byte[] in ISO_8859_1
10363 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10364 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10365 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10366 match(Set result (EncodeISOArray src (Binary dst len)));
10367 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10369 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
10370 ins_encode %{
10371 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10372 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10373 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10374 %}
10375 ins_pipe( pipe_slow );
10376 %}
10379 //----------Control Flow Instructions------------------------------------------
10380 // Signed compare Instructions
10382 // XXX more variants!!
10383 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10384 %{
10385 match(Set cr (CmpI op1 op2));
10386 effect(DEF cr, USE op1, USE op2);
10388 format %{ "cmpl $op1, $op2" %}
10389 opcode(0x3B); /* Opcode 3B /r */
10390 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10391 ins_pipe(ialu_cr_reg_reg);
10392 %}
10394 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10395 %{
10396 match(Set cr (CmpI op1 op2));
10398 format %{ "cmpl $op1, $op2" %}
10399 opcode(0x81, 0x07); /* Opcode 81 /7 */
10400 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10401 ins_pipe(ialu_cr_reg_imm);
10402 %}
10404 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
10405 %{
10406 match(Set cr (CmpI op1 (LoadI op2)));
10408 ins_cost(500); // XXX
10409 format %{ "cmpl $op1, $op2" %}
10410 opcode(0x3B); /* Opcode 3B /r */
10411 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10412 ins_pipe(ialu_cr_reg_mem);
10413 %}
10415 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
10416 %{
10417 match(Set cr (CmpI src zero));
10419 format %{ "testl $src, $src" %}
10420 opcode(0x85);
10421 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10422 ins_pipe(ialu_cr_reg_imm);
10423 %}
10425 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
10426 %{
10427 match(Set cr (CmpI (AndI src con) zero));
10429 format %{ "testl $src, $con" %}
10430 opcode(0xF7, 0x00);
10431 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
10432 ins_pipe(ialu_cr_reg_imm);
10433 %}
10435 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
10436 %{
10437 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
10439 format %{ "testl $src, $mem" %}
10440 opcode(0x85);
10441 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
10442 ins_pipe(ialu_cr_reg_mem);
10443 %}
10445 // Unsigned compare Instructions; really, same as signed except they
10446 // produce an rFlagsRegU instead of rFlagsReg.
10447 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
10448 %{
10449 match(Set cr (CmpU op1 op2));
10451 format %{ "cmpl $op1, $op2\t# unsigned" %}
10452 opcode(0x3B); /* Opcode 3B /r */
10453 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10454 ins_pipe(ialu_cr_reg_reg);
10455 %}
10457 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
10458 %{
10459 match(Set cr (CmpU op1 op2));
10461 format %{ "cmpl $op1, $op2\t# unsigned" %}
10462 opcode(0x81,0x07); /* Opcode 81 /7 */
10463 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10464 ins_pipe(ialu_cr_reg_imm);
10465 %}
10467 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
10468 %{
10469 match(Set cr (CmpU op1 (LoadI op2)));
10471 ins_cost(500); // XXX
10472 format %{ "cmpl $op1, $op2\t# unsigned" %}
10473 opcode(0x3B); /* Opcode 3B /r */
10474 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10475 ins_pipe(ialu_cr_reg_mem);
10476 %}
10478 // // // Cisc-spilled version of cmpU_rReg
10479 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
10480 // //%{
10481 // // match(Set cr (CmpU (LoadI op1) op2));
10482 // //
10483 // // format %{ "CMPu $op1,$op2" %}
10484 // // ins_cost(500);
10485 // // opcode(0x39); /* Opcode 39 /r */
10486 // // ins_encode( OpcP, reg_mem( op1, op2) );
10487 // //%}
10489 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
10490 %{
10491 match(Set cr (CmpU src zero));
10493 format %{ "testl $src, $src\t# unsigned" %}
10494 opcode(0x85);
10495 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10496 ins_pipe(ialu_cr_reg_imm);
10497 %}
10499 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
10500 %{
10501 match(Set cr (CmpP op1 op2));
10503 format %{ "cmpq $op1, $op2\t# ptr" %}
10504 opcode(0x3B); /* Opcode 3B /r */
10505 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10506 ins_pipe(ialu_cr_reg_reg);
10507 %}
10509 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
10510 %{
10511 match(Set cr (CmpP op1 (LoadP op2)));
10513 ins_cost(500); // XXX
10514 format %{ "cmpq $op1, $op2\t# ptr" %}
10515 opcode(0x3B); /* Opcode 3B /r */
10516 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10517 ins_pipe(ialu_cr_reg_mem);
10518 %}
10520 // // // Cisc-spilled version of cmpP_rReg
10521 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
10522 // //%{
10523 // // match(Set cr (CmpP (LoadP op1) op2));
10524 // //
10525 // // format %{ "CMPu $op1,$op2" %}
10526 // // ins_cost(500);
10527 // // opcode(0x39); /* Opcode 39 /r */
10528 // // ins_encode( OpcP, reg_mem( op1, op2) );
10529 // //%}
10531 // XXX this is generalized by compP_rReg_mem???
10532 // Compare raw pointer (used in out-of-heap check).
10533 // Only works because non-oop pointers must be raw pointers
10534 // and raw pointers have no anti-dependencies.
10535 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
10536 %{
10537 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
10538 match(Set cr (CmpP op1 (LoadP op2)));
10540 format %{ "cmpq $op1, $op2\t# raw ptr" %}
10541 opcode(0x3B); /* Opcode 3B /r */
10542 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10543 ins_pipe(ialu_cr_reg_mem);
10544 %}
10546 // This will generate a signed flags result. This should be OK since
10547 // any compare to a zero should be eq/neq.
10548 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
10549 %{
10550 match(Set cr (CmpP src zero));
10552 format %{ "testq $src, $src\t# ptr" %}
10553 opcode(0x85);
10554 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
10555 ins_pipe(ialu_cr_reg_imm);
10556 %}
10558 // This will generate a signed flags result. This should be OK since
10559 // any compare to a zero should be eq/neq.
10560 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
10561 %{
10562 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
10563 match(Set cr (CmpP (LoadP op) zero));
10565 ins_cost(500); // XXX
10566 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
10567 opcode(0xF7); /* Opcode F7 /0 */
10568 ins_encode(REX_mem_wide(op),
10569 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
10570 ins_pipe(ialu_cr_reg_imm);
10571 %}
10573 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
10574 %{
10575 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
10576 match(Set cr (CmpP (LoadP mem) zero));
10578 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
10579 ins_encode %{
10580 __ cmpq(r12, $mem$$Address);
10581 %}
10582 ins_pipe(ialu_cr_reg_mem);
10583 %}
10585 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
10586 %{
10587 match(Set cr (CmpN op1 op2));
10589 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10590 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
10591 ins_pipe(ialu_cr_reg_reg);
10592 %}
10594 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
10595 %{
10596 match(Set cr (CmpN src (LoadN mem)));
10598 format %{ "cmpl $src, $mem\t# compressed ptr" %}
10599 ins_encode %{
10600 __ cmpl($src$$Register, $mem$$Address);
10601 %}
10602 ins_pipe(ialu_cr_reg_mem);
10603 %}
10605 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
10606 match(Set cr (CmpN op1 op2));
10608 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10609 ins_encode %{
10610 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
10611 %}
10612 ins_pipe(ialu_cr_reg_imm);
10613 %}
10615 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
10616 %{
10617 match(Set cr (CmpN src (LoadN mem)));
10619 format %{ "cmpl $mem, $src\t# compressed ptr" %}
10620 ins_encode %{
10621 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
10622 %}
10623 ins_pipe(ialu_cr_reg_mem);
10624 %}
10626 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
10627 match(Set cr (CmpN op1 op2));
10629 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
10630 ins_encode %{
10631 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
10632 %}
10633 ins_pipe(ialu_cr_reg_imm);
10634 %}
10636 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
10637 %{
10638 match(Set cr (CmpN src (LoadNKlass mem)));
10640 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
10641 ins_encode %{
10642 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
10643 %}
10644 ins_pipe(ialu_cr_reg_mem);
10645 %}
10647 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
10648 match(Set cr (CmpN src zero));
10650 format %{ "testl $src, $src\t# compressed ptr" %}
10651 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
10652 ins_pipe(ialu_cr_reg_imm);
10653 %}
10655 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
10656 %{
10657 predicate(Universe::narrow_oop_base() != NULL);
10658 match(Set cr (CmpN (LoadN mem) zero));
10660 ins_cost(500); // XXX
10661 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
10662 ins_encode %{
10663 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
10664 %}
10665 ins_pipe(ialu_cr_reg_mem);
10666 %}
10668 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
10669 %{
10670 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
10671 match(Set cr (CmpN (LoadN mem) zero));
10673 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
10674 ins_encode %{
10675 __ cmpl(r12, $mem$$Address);
10676 %}
10677 ins_pipe(ialu_cr_reg_mem);
10678 %}
10680 // Yanked all unsigned pointer compare operations.
10681 // Pointer compares are done with CmpP which is already unsigned.
10683 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
10684 %{
10685 match(Set cr (CmpL op1 op2));
10687 format %{ "cmpq $op1, $op2" %}
10688 opcode(0x3B); /* Opcode 3B /r */
10689 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10690 ins_pipe(ialu_cr_reg_reg);
10691 %}
10693 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
10694 %{
10695 match(Set cr (CmpL op1 op2));
10697 format %{ "cmpq $op1, $op2" %}
10698 opcode(0x81, 0x07); /* Opcode 81 /7 */
10699 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
10700 ins_pipe(ialu_cr_reg_imm);
10701 %}
10703 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
10704 %{
10705 match(Set cr (CmpL op1 (LoadL op2)));
10707 format %{ "cmpq $op1, $op2" %}
10708 opcode(0x3B); /* Opcode 3B /r */
10709 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10710 ins_pipe(ialu_cr_reg_mem);
10711 %}
10713 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
10714 %{
10715 match(Set cr (CmpL src zero));
10717 format %{ "testq $src, $src" %}
10718 opcode(0x85);
10719 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
10720 ins_pipe(ialu_cr_reg_imm);
10721 %}
10723 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
10724 %{
10725 match(Set cr (CmpL (AndL src con) zero));
10727 format %{ "testq $src, $con\t# long" %}
10728 opcode(0xF7, 0x00);
10729 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
10730 ins_pipe(ialu_cr_reg_imm);
10731 %}
10733 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
10734 %{
10735 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
10737 format %{ "testq $src, $mem" %}
10738 opcode(0x85);
10739 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
10740 ins_pipe(ialu_cr_reg_mem);
10741 %}
10743 // Manifest a CmpL result in an integer register. Very painful.
10744 // This is the test to avoid.
10745 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
10746 %{
10747 match(Set dst (CmpL3 src1 src2));
10748 effect(KILL flags);
10750 ins_cost(275); // XXX
10751 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
10752 "movl $dst, -1\n\t"
10753 "jl,s done\n\t"
10754 "setne $dst\n\t"
10755 "movzbl $dst, $dst\n\t"
10756 "done:" %}
10757 ins_encode(cmpl3_flag(src1, src2, dst));
10758 ins_pipe(pipe_slow);
10759 %}
10761 //----------Max and Min--------------------------------------------------------
10762 // Min Instructions
10764 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
10765 %{
10766 effect(USE_DEF dst, USE src, USE cr);
10768 format %{ "cmovlgt $dst, $src\t# min" %}
10769 opcode(0x0F, 0x4F);
10770 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
10771 ins_pipe(pipe_cmov_reg);
10772 %}
10775 instruct minI_rReg(rRegI dst, rRegI src)
10776 %{
10777 match(Set dst (MinI dst src));
10779 ins_cost(200);
10780 expand %{
10781 rFlagsReg cr;
10782 compI_rReg(cr, dst, src);
10783 cmovI_reg_g(dst, src, cr);
10784 %}
10785 %}
10787 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
10788 %{
10789 effect(USE_DEF dst, USE src, USE cr);
10791 format %{ "cmovllt $dst, $src\t# max" %}
10792 opcode(0x0F, 0x4C);
10793 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
10794 ins_pipe(pipe_cmov_reg);
10795 %}
10798 instruct maxI_rReg(rRegI dst, rRegI src)
10799 %{
10800 match(Set dst (MaxI dst src));
10802 ins_cost(200);
10803 expand %{
10804 rFlagsReg cr;
10805 compI_rReg(cr, dst, src);
10806 cmovI_reg_l(dst, src, cr);
10807 %}
10808 %}
10810 // ============================================================================
10811 // Branch Instructions
10813 // Jump Direct - Label defines a relative address from JMP+1
10814 instruct jmpDir(label labl)
10815 %{
10816 match(Goto);
10817 effect(USE labl);
10819 ins_cost(300);
10820 format %{ "jmp $labl" %}
10821 size(5);
10822 ins_encode %{
10823 Label* L = $labl$$label;
10824 __ jmp(*L, false); // Always long jump
10825 %}
10826 ins_pipe(pipe_jmp);
10827 %}
10829 // Jump Direct Conditional - Label defines a relative address from Jcc+1
10830 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
10831 %{
10832 match(If cop cr);
10833 effect(USE labl);
10835 ins_cost(300);
10836 format %{ "j$cop $labl" %}
10837 size(6);
10838 ins_encode %{
10839 Label* L = $labl$$label;
10840 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10841 %}
10842 ins_pipe(pipe_jcc);
10843 %}
10845 // Jump Direct Conditional - Label defines a relative address from Jcc+1
10846 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
10847 %{
10848 match(CountedLoopEnd cop cr);
10849 effect(USE labl);
10851 ins_cost(300);
10852 format %{ "j$cop $labl\t# loop end" %}
10853 size(6);
10854 ins_encode %{
10855 Label* L = $labl$$label;
10856 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10857 %}
10858 ins_pipe(pipe_jcc);
10859 %}
10861 // Jump Direct Conditional - Label defines a relative address from Jcc+1
10862 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
10863 match(CountedLoopEnd cop cmp);
10864 effect(USE labl);
10866 ins_cost(300);
10867 format %{ "j$cop,u $labl\t# loop end" %}
10868 size(6);
10869 ins_encode %{
10870 Label* L = $labl$$label;
10871 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10872 %}
10873 ins_pipe(pipe_jcc);
10874 %}
10876 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
10877 match(CountedLoopEnd cop cmp);
10878 effect(USE labl);
10880 ins_cost(200);
10881 format %{ "j$cop,u $labl\t# loop end" %}
10882 size(6);
10883 ins_encode %{
10884 Label* L = $labl$$label;
10885 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10886 %}
10887 ins_pipe(pipe_jcc);
10888 %}
10890 // Jump Direct Conditional - using unsigned comparison
10891 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
10892 match(If cop cmp);
10893 effect(USE labl);
10895 ins_cost(300);
10896 format %{ "j$cop,u $labl" %}
10897 size(6);
10898 ins_encode %{
10899 Label* L = $labl$$label;
10900 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10901 %}
10902 ins_pipe(pipe_jcc);
10903 %}
10905 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
10906 match(If cop cmp);
10907 effect(USE labl);
10909 ins_cost(200);
10910 format %{ "j$cop,u $labl" %}
10911 size(6);
10912 ins_encode %{
10913 Label* L = $labl$$label;
10914 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10915 %}
10916 ins_pipe(pipe_jcc);
10917 %}
10919 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
10920 match(If cop cmp);
10921 effect(USE labl);
10923 ins_cost(200);
10924 format %{ $$template
10925 if ($cop$$cmpcode == Assembler::notEqual) {
10926 $$emit$$"jp,u $labl\n\t"
10927 $$emit$$"j$cop,u $labl"
10928 } else {
10929 $$emit$$"jp,u done\n\t"
10930 $$emit$$"j$cop,u $labl\n\t"
10931 $$emit$$"done:"
10932 }
10933 %}
10934 ins_encode %{
10935 Label* l = $labl$$label;
10936 if ($cop$$cmpcode == Assembler::notEqual) {
10937 __ jcc(Assembler::parity, *l, false);
10938 __ jcc(Assembler::notEqual, *l, false);
10939 } else if ($cop$$cmpcode == Assembler::equal) {
10940 Label done;
10941 __ jccb(Assembler::parity, done);
10942 __ jcc(Assembler::equal, *l, false);
10943 __ bind(done);
10944 } else {
10945 ShouldNotReachHere();
10946 }
10947 %}
10948 ins_pipe(pipe_jcc);
10949 %}
10951 // ============================================================================
10952 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
10953 // superklass array for an instance of the superklass. Set a hidden
10954 // internal cache on a hit (cache is checked with exposed code in
10955 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
10956 // encoding ALSO sets flags.
10958 instruct partialSubtypeCheck(rdi_RegP result,
10959 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
10960 rFlagsReg cr)
10961 %{
10962 match(Set result (PartialSubtypeCheck sub super));
10963 effect(KILL rcx, KILL cr);
10965 ins_cost(1100); // slightly larger than the next version
10966 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
10967 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
10968 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
10969 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
10970 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
10971 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
10972 "xorq $result, $result\t\t Hit: rdi zero\n\t"
10973 "miss:\t" %}
10975 opcode(0x1); // Force a XOR of RDI
10976 ins_encode(enc_PartialSubtypeCheck());
10977 ins_pipe(pipe_slow);
10978 %}
10980 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
10981 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
10982 immP0 zero,
10983 rdi_RegP result)
10984 %{
10985 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
10986 effect(KILL rcx, KILL result);
10988 ins_cost(1000);
10989 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
10990 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
10991 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
10992 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
10993 "jne,s miss\t\t# Missed: flags nz\n\t"
10994 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
10995 "miss:\t" %}
10997 opcode(0x0); // No need to XOR RDI
10998 ins_encode(enc_PartialSubtypeCheck());
10999 ins_pipe(pipe_slow);
11000 %}
11002 // ============================================================================
11003 // Branch Instructions -- short offset versions
11004 //
11005 // These instructions are used to replace jumps of a long offset (the default
11006 // match) with jumps of a shorter offset. These instructions are all tagged
11007 // with the ins_short_branch attribute, which causes the ADLC to suppress the
11008 // match rules in general matching. Instead, the ADLC generates a conversion
11009 // method in the MachNode which can be used to do in-place replacement of the
11010 // long variant with the shorter variant. The compiler will determine if a
11011 // branch can be taken by the is_short_branch_offset() predicate in the machine
11012 // specific code section of the file.
11014 // Jump Direct - Label defines a relative address from JMP+1
11015 instruct jmpDir_short(label labl) %{
11016 match(Goto);
11017 effect(USE labl);
11019 ins_cost(300);
11020 format %{ "jmp,s $labl" %}
11021 size(2);
11022 ins_encode %{
11023 Label* L = $labl$$label;
11024 __ jmpb(*L);
11025 %}
11026 ins_pipe(pipe_jmp);
11027 ins_short_branch(1);
11028 %}
11030 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11031 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
11032 match(If cop cr);
11033 effect(USE labl);
11035 ins_cost(300);
11036 format %{ "j$cop,s $labl" %}
11037 size(2);
11038 ins_encode %{
11039 Label* L = $labl$$label;
11040 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11041 %}
11042 ins_pipe(pipe_jcc);
11043 ins_short_branch(1);
11044 %}
11046 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11047 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
11048 match(CountedLoopEnd cop cr);
11049 effect(USE labl);
11051 ins_cost(300);
11052 format %{ "j$cop,s $labl\t# loop end" %}
11053 size(2);
11054 ins_encode %{
11055 Label* L = $labl$$label;
11056 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11057 %}
11058 ins_pipe(pipe_jcc);
11059 ins_short_branch(1);
11060 %}
11062 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11063 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11064 match(CountedLoopEnd cop cmp);
11065 effect(USE labl);
11067 ins_cost(300);
11068 format %{ "j$cop,us $labl\t# loop end" %}
11069 size(2);
11070 ins_encode %{
11071 Label* L = $labl$$label;
11072 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11073 %}
11074 ins_pipe(pipe_jcc);
11075 ins_short_branch(1);
11076 %}
11078 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11079 match(CountedLoopEnd cop cmp);
11080 effect(USE labl);
11082 ins_cost(300);
11083 format %{ "j$cop,us $labl\t# loop end" %}
11084 size(2);
11085 ins_encode %{
11086 Label* L = $labl$$label;
11087 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11088 %}
11089 ins_pipe(pipe_jcc);
11090 ins_short_branch(1);
11091 %}
11093 // Jump Direct Conditional - using unsigned comparison
11094 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11095 match(If cop cmp);
11096 effect(USE labl);
11098 ins_cost(300);
11099 format %{ "j$cop,us $labl" %}
11100 size(2);
11101 ins_encode %{
11102 Label* L = $labl$$label;
11103 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11104 %}
11105 ins_pipe(pipe_jcc);
11106 ins_short_branch(1);
11107 %}
11109 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11110 match(If cop cmp);
11111 effect(USE labl);
11113 ins_cost(300);
11114 format %{ "j$cop,us $labl" %}
11115 size(2);
11116 ins_encode %{
11117 Label* L = $labl$$label;
11118 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11119 %}
11120 ins_pipe(pipe_jcc);
11121 ins_short_branch(1);
11122 %}
11124 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11125 match(If cop cmp);
11126 effect(USE labl);
11128 ins_cost(300);
11129 format %{ $$template
11130 if ($cop$$cmpcode == Assembler::notEqual) {
11131 $$emit$$"jp,u,s $labl\n\t"
11132 $$emit$$"j$cop,u,s $labl"
11133 } else {
11134 $$emit$$"jp,u,s done\n\t"
11135 $$emit$$"j$cop,u,s $labl\n\t"
11136 $$emit$$"done:"
11137 }
11138 %}
11139 size(4);
11140 ins_encode %{
11141 Label* l = $labl$$label;
11142 if ($cop$$cmpcode == Assembler::notEqual) {
11143 __ jccb(Assembler::parity, *l);
11144 __ jccb(Assembler::notEqual, *l);
11145 } else if ($cop$$cmpcode == Assembler::equal) {
11146 Label done;
11147 __ jccb(Assembler::parity, done);
11148 __ jccb(Assembler::equal, *l);
11149 __ bind(done);
11150 } else {
11151 ShouldNotReachHere();
11152 }
11153 %}
11154 ins_pipe(pipe_jcc);
11155 ins_short_branch(1);
11156 %}
11158 // ============================================================================
11159 // inlined locking and unlocking
11161 instruct cmpFastLock(rFlagsReg cr,
11162 rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr)
11163 %{
11164 match(Set cr (FastLock object box));
11165 effect(TEMP tmp, TEMP scr, USE_KILL box);
11167 ins_cost(300);
11168 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
11169 ins_encode(Fast_Lock(object, box, tmp, scr));
11170 ins_pipe(pipe_slow);
11171 %}
11173 instruct cmpFastUnlock(rFlagsReg cr,
11174 rRegP object, rax_RegP box, rRegP tmp)
11175 %{
11176 match(Set cr (FastUnlock object box));
11177 effect(TEMP tmp, USE_KILL box);
11179 ins_cost(300);
11180 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
11181 ins_encode(Fast_Unlock(object, box, tmp));
11182 ins_pipe(pipe_slow);
11183 %}
11186 // ============================================================================
11187 // Safepoint Instructions
11188 instruct safePoint_poll(rFlagsReg cr)
11189 %{
11190 predicate(!Assembler::is_polling_page_far());
11191 match(SafePoint);
11192 effect(KILL cr);
11194 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
11195 "# Safepoint: poll for GC" %}
11196 ins_cost(125);
11197 ins_encode %{
11198 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
11199 __ testl(rax, addr);
11200 %}
11201 ins_pipe(ialu_reg_mem);
11202 %}
11204 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
11205 %{
11206 predicate(Assembler::is_polling_page_far());
11207 match(SafePoint poll);
11208 effect(KILL cr, USE poll);
11210 format %{ "testl rax, [$poll]\t"
11211 "# Safepoint: poll for GC" %}
11212 ins_cost(125);
11213 ins_encode %{
11214 __ relocate(relocInfo::poll_type);
11215 __ testl(rax, Address($poll$$Register, 0));
11216 %}
11217 ins_pipe(ialu_reg_mem);
11218 %}
11220 // ============================================================================
11221 // Procedure Call/Return Instructions
11222 // Call Java Static Instruction
11223 // Note: If this code changes, the corresponding ret_addr_offset() and
11224 // compute_padding() functions will have to be adjusted.
11225 instruct CallStaticJavaDirect(method meth) %{
11226 match(CallStaticJava);
11227 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke());
11228 effect(USE meth);
11230 ins_cost(300);
11231 format %{ "call,static " %}
11232 opcode(0xE8); /* E8 cd */
11233 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
11234 ins_pipe(pipe_slow);
11235 ins_alignment(4);
11236 %}
11238 // Call Java Static Instruction (method handle version)
11239 // Note: If this code changes, the corresponding ret_addr_offset() and
11240 // compute_padding() functions will have to be adjusted.
11241 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{
11242 match(CallStaticJava);
11243 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke());
11244 effect(USE meth);
11245 // RBP is saved by all callees (for interpreter stack correction).
11246 // We use it here for a similar purpose, in {preserve,restore}_SP.
11248 ins_cost(300);
11249 format %{ "call,static/MethodHandle " %}
11250 opcode(0xE8); /* E8 cd */
11251 ins_encode(clear_avx, preserve_SP,
11252 Java_Static_Call(meth),
11253 restore_SP,
11254 call_epilog);
11255 ins_pipe(pipe_slow);
11256 ins_alignment(4);
11257 %}
11259 // Call Java Dynamic Instruction
11260 // Note: If this code changes, the corresponding ret_addr_offset() and
11261 // compute_padding() functions will have to be adjusted.
11262 instruct CallDynamicJavaDirect(method meth)
11263 %{
11264 match(CallDynamicJava);
11265 effect(USE meth);
11267 ins_cost(300);
11268 format %{ "movq rax, #Universe::non_oop_word()\n\t"
11269 "call,dynamic " %}
11270 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
11271 ins_pipe(pipe_slow);
11272 ins_alignment(4);
11273 %}
11275 // Call Runtime Instruction
11276 instruct CallRuntimeDirect(method meth)
11277 %{
11278 match(CallRuntime);
11279 effect(USE meth);
11281 ins_cost(300);
11282 format %{ "call,runtime " %}
11283 ins_encode(clear_avx, Java_To_Runtime(meth));
11284 ins_pipe(pipe_slow);
11285 %}
11287 // Call runtime without safepoint
11288 instruct CallLeafDirect(method meth)
11289 %{
11290 match(CallLeaf);
11291 effect(USE meth);
11293 ins_cost(300);
11294 format %{ "call_leaf,runtime " %}
11295 ins_encode(clear_avx, Java_To_Runtime(meth));
11296 ins_pipe(pipe_slow);
11297 %}
11299 // Call runtime without safepoint
11300 instruct CallLeafNoFPDirect(method meth)
11301 %{
11302 match(CallLeafNoFP);
11303 effect(USE meth);
11305 ins_cost(300);
11306 format %{ "call_leaf_nofp,runtime " %}
11307 ins_encode(Java_To_Runtime(meth));
11308 ins_pipe(pipe_slow);
11309 %}
11311 // Return Instruction
11312 // Remove the return address & jump to it.
11313 // Notice: We always emit a nop after a ret to make sure there is room
11314 // for safepoint patching
11315 instruct Ret()
11316 %{
11317 match(Return);
11319 format %{ "ret" %}
11320 opcode(0xC3);
11321 ins_encode(OpcP);
11322 ins_pipe(pipe_jmp);
11323 %}
11325 // Tail Call; Jump from runtime stub to Java code.
11326 // Also known as an 'interprocedural jump'.
11327 // Target of jump will eventually return to caller.
11328 // TailJump below removes the return address.
11329 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
11330 %{
11331 match(TailCall jump_target method_oop);
11333 ins_cost(300);
11334 format %{ "jmp $jump_target\t# rbx holds method oop" %}
11335 opcode(0xFF, 0x4); /* Opcode FF /4 */
11336 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
11337 ins_pipe(pipe_jmp);
11338 %}
11340 // Tail Jump; remove the return address; jump to target.
11341 // TailCall above leaves the return address around.
11342 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
11343 %{
11344 match(TailJump jump_target ex_oop);
11346 ins_cost(300);
11347 format %{ "popq rdx\t# pop return address\n\t"
11348 "jmp $jump_target" %}
11349 opcode(0xFF, 0x4); /* Opcode FF /4 */
11350 ins_encode(Opcode(0x5a), // popq rdx
11351 REX_reg(jump_target), OpcP, reg_opc(jump_target));
11352 ins_pipe(pipe_jmp);
11353 %}
11355 // Create exception oop: created by stack-crawling runtime code.
11356 // Created exception is now available to this handler, and is setup
11357 // just prior to jumping to this handler. No code emitted.
11358 instruct CreateException(rax_RegP ex_oop)
11359 %{
11360 match(Set ex_oop (CreateEx));
11362 size(0);
11363 // use the following format syntax
11364 format %{ "# exception oop is in rax; no code emitted" %}
11365 ins_encode();
11366 ins_pipe(empty);
11367 %}
11369 // Rethrow exception:
11370 // The exception oop will come in the first argument position.
11371 // Then JUMP (not call) to the rethrow stub code.
11372 instruct RethrowException()
11373 %{
11374 match(Rethrow);
11376 // use the following format syntax
11377 format %{ "jmp rethrow_stub" %}
11378 ins_encode(enc_rethrow);
11379 ins_pipe(pipe_jmp);
11380 %}
11383 // ============================================================================
11384 // This name is KNOWN by the ADLC and cannot be changed.
11385 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11386 // for this guy.
11387 instruct tlsLoadP(r15_RegP dst) %{
11388 match(Set dst (ThreadLocal));
11389 effect(DEF dst);
11391 size(0);
11392 format %{ "# TLS is in R15" %}
11393 ins_encode( /*empty encoding*/ );
11394 ins_pipe(ialu_reg_reg);
11395 %}
11398 //----------PEEPHOLE RULES-----------------------------------------------------
11399 // These must follow all instruction definitions as they use the names
11400 // defined in the instructions definitions.
11401 //
11402 // peepmatch ( root_instr_name [preceding_instruction]* );
11403 //
11404 // peepconstraint %{
11405 // (instruction_number.operand_name relational_op instruction_number.operand_name
11406 // [, ...] );
11407 // // instruction numbers are zero-based using left to right order in peepmatch
11408 //
11409 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11410 // // provide an instruction_number.operand_name for each operand that appears
11411 // // in the replacement instruction's match rule
11412 //
11413 // ---------VM FLAGS---------------------------------------------------------
11414 //
11415 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11416 //
11417 // Each peephole rule is given an identifying number starting with zero and
11418 // increasing by one in the order seen by the parser. An individual peephole
11419 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11420 // on the command-line.
11421 //
11422 // ---------CURRENT LIMITATIONS----------------------------------------------
11423 //
11424 // Only match adjacent instructions in same basic block
11425 // Only equality constraints
11426 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11427 // Only one replacement instruction
11428 //
11429 // ---------EXAMPLE----------------------------------------------------------
11430 //
11431 // // pertinent parts of existing instructions in architecture description
11432 // instruct movI(rRegI dst, rRegI src)
11433 // %{
11434 // match(Set dst (CopyI src));
11435 // %}
11436 //
11437 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
11438 // %{
11439 // match(Set dst (AddI dst src));
11440 // effect(KILL cr);
11441 // %}
11442 //
11443 // // Change (inc mov) to lea
11444 // peephole %{
11445 // // increment preceeded by register-register move
11446 // peepmatch ( incI_rReg movI );
11447 // // require that the destination register of the increment
11448 // // match the destination register of the move
11449 // peepconstraint ( 0.dst == 1.dst );
11450 // // construct a replacement instruction that sets
11451 // // the destination to ( move's source register + one )
11452 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
11453 // %}
11454 //
11456 // Implementation no longer uses movX instructions since
11457 // machine-independent system no longer uses CopyX nodes.
11458 //
11459 // peephole
11460 // %{
11461 // peepmatch (incI_rReg movI);
11462 // peepconstraint (0.dst == 1.dst);
11463 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11464 // %}
11466 // peephole
11467 // %{
11468 // peepmatch (decI_rReg movI);
11469 // peepconstraint (0.dst == 1.dst);
11470 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11471 // %}
11473 // peephole
11474 // %{
11475 // peepmatch (addI_rReg_imm movI);
11476 // peepconstraint (0.dst == 1.dst);
11477 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11478 // %}
11480 // peephole
11481 // %{
11482 // peepmatch (incL_rReg movL);
11483 // peepconstraint (0.dst == 1.dst);
11484 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11485 // %}
11487 // peephole
11488 // %{
11489 // peepmatch (decL_rReg movL);
11490 // peepconstraint (0.dst == 1.dst);
11491 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11492 // %}
11494 // peephole
11495 // %{
11496 // peepmatch (addL_rReg_imm movL);
11497 // peepconstraint (0.dst == 1.dst);
11498 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11499 // %}
11501 // peephole
11502 // %{
11503 // peepmatch (addP_rReg_imm movP);
11504 // peepconstraint (0.dst == 1.dst);
11505 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
11506 // %}
11508 // // Change load of spilled value to only a spill
11509 // instruct storeI(memory mem, rRegI src)
11510 // %{
11511 // match(Set mem (StoreI mem src));
11512 // %}
11513 //
11514 // instruct loadI(rRegI dst, memory mem)
11515 // %{
11516 // match(Set dst (LoadI mem));
11517 // %}
11518 //
11520 peephole
11521 %{
11522 peepmatch (loadI storeI);
11523 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11524 peepreplace (storeI(1.mem 1.mem 1.src));
11525 %}
11527 peephole
11528 %{
11529 peepmatch (loadL storeL);
11530 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11531 peepreplace (storeL(1.mem 1.mem 1.src));
11532 %}
11534 //----------SMARTSPILL RULES---------------------------------------------------
11535 // These must follow all instruction definitions as they use the names
11536 // defined in the instructions definitions.