Thu, 10 Apr 2014 23:15:13 -0700
8038297: Avoid placing CTI immediately following cbcond instruction on T4
Summary: Insert a nop between cbcond and CTI
Reviewed-by: kvn, twisti
1 /*
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
28 #include "asm/register.hpp"
30 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
31 // level; i.e., what you write
32 // is what you get. The Assembler is generating code into a CodeBuffer.
34 class Assembler : public AbstractAssembler {
35 friend class AbstractAssembler;
36 friend class AddressLiteral;
38 // code patchers need various routines like inv_wdisp()
39 friend class NativeInstruction;
40 friend class NativeGeneralJump;
41 friend class Relocation;
42 friend class Label;
44 public:
45 // op carries format info; see page 62 & 267
47 enum ops {
48 call_op = 1, // fmt 1
49 branch_op = 0, // also sethi (fmt2)
50 arith_op = 2, // fmt 3, arith & misc
51 ldst_op = 3 // fmt 3, load/store
52 };
54 enum op2s {
55 bpr_op2 = 3,
56 fb_op2 = 6,
57 fbp_op2 = 5,
58 br_op2 = 2,
59 bp_op2 = 1,
60 sethi_op2 = 4
61 };
63 enum op3s {
64 // selected op3s
65 add_op3 = 0x00,
66 and_op3 = 0x01,
67 or_op3 = 0x02,
68 xor_op3 = 0x03,
69 sub_op3 = 0x04,
70 andn_op3 = 0x05,
71 orn_op3 = 0x06,
72 xnor_op3 = 0x07,
73 addc_op3 = 0x08,
74 mulx_op3 = 0x09,
75 umul_op3 = 0x0a,
76 smul_op3 = 0x0b,
77 subc_op3 = 0x0c,
78 udivx_op3 = 0x0d,
79 udiv_op3 = 0x0e,
80 sdiv_op3 = 0x0f,
82 addcc_op3 = 0x10,
83 andcc_op3 = 0x11,
84 orcc_op3 = 0x12,
85 xorcc_op3 = 0x13,
86 subcc_op3 = 0x14,
87 andncc_op3 = 0x15,
88 orncc_op3 = 0x16,
89 xnorcc_op3 = 0x17,
90 addccc_op3 = 0x18,
91 aes4_op3 = 0x19,
92 umulcc_op3 = 0x1a,
93 smulcc_op3 = 0x1b,
94 subccc_op3 = 0x1c,
95 udivcc_op3 = 0x1e,
96 sdivcc_op3 = 0x1f,
98 taddcc_op3 = 0x20,
99 tsubcc_op3 = 0x21,
100 taddcctv_op3 = 0x22,
101 tsubcctv_op3 = 0x23,
102 mulscc_op3 = 0x24,
103 sll_op3 = 0x25,
104 sllx_op3 = 0x25,
105 srl_op3 = 0x26,
106 srlx_op3 = 0x26,
107 sra_op3 = 0x27,
108 srax_op3 = 0x27,
109 rdreg_op3 = 0x28,
110 membar_op3 = 0x28,
112 flushw_op3 = 0x2b,
113 movcc_op3 = 0x2c,
114 sdivx_op3 = 0x2d,
115 popc_op3 = 0x2e,
116 movr_op3 = 0x2f,
118 sir_op3 = 0x30,
119 wrreg_op3 = 0x30,
120 saved_op3 = 0x31,
122 fpop1_op3 = 0x34,
123 fpop2_op3 = 0x35,
124 impdep1_op3 = 0x36,
125 aes3_op3 = 0x36,
126 flog3_op3 = 0x36,
127 impdep2_op3 = 0x37,
128 jmpl_op3 = 0x38,
129 rett_op3 = 0x39,
130 trap_op3 = 0x3a,
131 flush_op3 = 0x3b,
132 save_op3 = 0x3c,
133 restore_op3 = 0x3d,
134 done_op3 = 0x3e,
135 retry_op3 = 0x3e,
137 lduw_op3 = 0x00,
138 ldub_op3 = 0x01,
139 lduh_op3 = 0x02,
140 ldd_op3 = 0x03,
141 stw_op3 = 0x04,
142 stb_op3 = 0x05,
143 sth_op3 = 0x06,
144 std_op3 = 0x07,
145 ldsw_op3 = 0x08,
146 ldsb_op3 = 0x09,
147 ldsh_op3 = 0x0a,
148 ldx_op3 = 0x0b,
150 stx_op3 = 0x0e,
151 swap_op3 = 0x0f,
153 stwa_op3 = 0x14,
154 stxa_op3 = 0x1e,
156 ldf_op3 = 0x20,
157 ldfsr_op3 = 0x21,
158 ldqf_op3 = 0x22,
159 lddf_op3 = 0x23,
160 stf_op3 = 0x24,
161 stfsr_op3 = 0x25,
162 stqf_op3 = 0x26,
163 stdf_op3 = 0x27,
165 prefetch_op3 = 0x2d,
167 casa_op3 = 0x3c,
168 casxa_op3 = 0x3e,
170 mftoi_op3 = 0x36,
172 alt_bit_op3 = 0x10,
173 cc_bit_op3 = 0x10
174 };
176 enum opfs {
177 // selected opfs
178 fmovs_opf = 0x01,
179 fmovd_opf = 0x02,
181 fnegs_opf = 0x05,
182 fnegd_opf = 0x06,
184 fadds_opf = 0x41,
185 faddd_opf = 0x42,
186 fsubs_opf = 0x45,
187 fsubd_opf = 0x46,
189 fmuls_opf = 0x49,
190 fmuld_opf = 0x4a,
191 fdivs_opf = 0x4d,
192 fdivd_opf = 0x4e,
194 fcmps_opf = 0x51,
195 fcmpd_opf = 0x52,
197 fstox_opf = 0x81,
198 fdtox_opf = 0x82,
199 fxtos_opf = 0x84,
200 fxtod_opf = 0x88,
201 fitos_opf = 0xc4,
202 fdtos_opf = 0xc6,
203 fitod_opf = 0xc8,
204 fstod_opf = 0xc9,
205 fstoi_opf = 0xd1,
206 fdtoi_opf = 0xd2,
208 mdtox_opf = 0x110,
209 mstouw_opf = 0x111,
210 mstosw_opf = 0x113,
211 mxtod_opf = 0x118,
212 mwtos_opf = 0x119,
214 aes_kexpand0_opf = 0x130,
215 aes_kexpand2_opf = 0x131
216 };
218 enum op5s {
219 aes_eround01_op5 = 0x00,
220 aes_eround23_op5 = 0x01,
221 aes_dround01_op5 = 0x02,
222 aes_dround23_op5 = 0x03,
223 aes_eround01_l_op5 = 0x04,
224 aes_eround23_l_op5 = 0x05,
225 aes_dround01_l_op5 = 0x06,
226 aes_dround23_l_op5 = 0x07,
227 aes_kexpand1_op5 = 0x08
228 };
230 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
232 enum Condition {
233 // for FBfcc & FBPfcc instruction
234 f_never = 0,
235 f_notEqual = 1,
236 f_notZero = 1,
237 f_lessOrGreater = 2,
238 f_unorderedOrLess = 3,
239 f_less = 4,
240 f_unorderedOrGreater = 5,
241 f_greater = 6,
242 f_unordered = 7,
243 f_always = 8,
244 f_equal = 9,
245 f_zero = 9,
246 f_unorderedOrEqual = 10,
247 f_greaterOrEqual = 11,
248 f_unorderedOrGreaterOrEqual = 12,
249 f_lessOrEqual = 13,
250 f_unorderedOrLessOrEqual = 14,
251 f_ordered = 15,
253 // V8 coproc, pp 123 v8 manual
255 cp_always = 8,
256 cp_never = 0,
257 cp_3 = 7,
258 cp_2 = 6,
259 cp_2or3 = 5,
260 cp_1 = 4,
261 cp_1or3 = 3,
262 cp_1or2 = 2,
263 cp_1or2or3 = 1,
264 cp_0 = 9,
265 cp_0or3 = 10,
266 cp_0or2 = 11,
267 cp_0or2or3 = 12,
268 cp_0or1 = 13,
269 cp_0or1or3 = 14,
270 cp_0or1or2 = 15,
273 // for integers
275 never = 0,
276 equal = 1,
277 zero = 1,
278 lessEqual = 2,
279 less = 3,
280 lessEqualUnsigned = 4,
281 lessUnsigned = 5,
282 carrySet = 5,
283 negative = 6,
284 overflowSet = 7,
285 always = 8,
286 notEqual = 9,
287 notZero = 9,
288 greater = 10,
289 greaterEqual = 11,
290 greaterUnsigned = 12,
291 greaterEqualUnsigned = 13,
292 carryClear = 13,
293 positive = 14,
294 overflowClear = 15
295 };
297 enum CC {
298 icc = 0, xcc = 2,
299 // ptr_cc is the correct condition code for a pointer or intptr_t:
300 ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
301 fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3
302 };
304 enum PrefetchFcn {
305 severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
306 };
308 public:
309 // Helper functions for groups of instructions
311 enum Predict { pt = 1, pn = 0 }; // pt = predict taken
313 enum Membar_mask_bits { // page 184, v9
314 StoreStore = 1 << 3,
315 LoadStore = 1 << 2,
316 StoreLoad = 1 << 1,
317 LoadLoad = 1 << 0,
319 Sync = 1 << 6,
320 MemIssue = 1 << 5,
321 Lookaside = 1 << 4
322 };
324 static bool is_in_wdisp_range(address a, address b, int nbits) {
325 intptr_t d = intptr_t(b) - intptr_t(a);
326 return is_simm(d, nbits + 2);
327 }
329 address target_distance(Label& L) {
330 // Assembler::target(L) should be called only when
331 // a branch instruction is emitted since non-bound
332 // labels record current pc() as a branch address.
333 if (L.is_bound()) return target(L);
334 // Return current address for non-bound labels.
335 return pc();
336 }
338 // test if label is in simm16 range in words (wdisp16).
339 bool is_in_wdisp16_range(Label& L) {
340 return is_in_wdisp_range(target_distance(L), pc(), 16);
341 }
342 // test if the distance between two addresses fits in simm30 range in words
343 static bool is_in_wdisp30_range(address a, address b) {
344 return is_in_wdisp_range(a, b, 30);
345 }
347 enum ASIs { // page 72, v9
348 ASI_PRIMARY = 0x80,
349 ASI_PRIMARY_NOFAULT = 0x82,
350 ASI_PRIMARY_LITTLE = 0x88,
351 // Block initializing store
352 ASI_ST_BLKINIT_PRIMARY = 0xE2,
353 // Most-Recently-Used (MRU) BIS variant
354 ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2
355 // add more from book as needed
356 };
358 protected:
359 // helpers
361 // x is supposed to fit in a field "nbits" wide
362 // and be sign-extended. Check the range.
364 static void assert_signed_range(intptr_t x, int nbits) {
365 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < ( 1 << nbits-1)),
366 err_msg("value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits));
367 }
369 static void assert_signed_word_disp_range(intptr_t x, int nbits) {
370 assert( (x & 3) == 0, "not word aligned");
371 assert_signed_range(x, nbits + 2);
372 }
374 static void assert_unsigned_const(int x, int nbits) {
375 assert( juint(x) < juint(1 << nbits), "unsigned constant out of range");
376 }
378 // fields: note bits numbered from LSB = 0,
379 // fields known by inclusive bit range
381 static int fmask(juint hi_bit, juint lo_bit) {
382 assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");
383 return (1 << ( hi_bit-lo_bit + 1 )) - 1;
384 }
386 // inverse of u_field
388 static int inv_u_field(int x, int hi_bit, int lo_bit) {
389 juint r = juint(x) >> lo_bit;
390 r &= fmask( hi_bit, lo_bit);
391 return int(r);
392 }
395 // signed version: extract from field and sign-extend
397 static int inv_s_field(int x, int hi_bit, int lo_bit) {
398 int sign_shift = 31 - hi_bit;
399 return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
400 }
402 // given a field that ranges from hi_bit to lo_bit (inclusive,
403 // LSB = 0), and an unsigned value for the field,
404 // shift it into the field
406 #ifdef ASSERT
407 static int u_field(int x, int hi_bit, int lo_bit) {
408 assert( ( x & ~fmask(hi_bit, lo_bit)) == 0,
409 "value out of range");
410 int r = x << lo_bit;
411 assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
412 return r;
413 }
414 #else
415 // make sure this is inlined as it will reduce code size significantly
416 #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))
417 #endif
419 static int inv_op( int x ) { return inv_u_field(x, 31, 30); }
420 static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
421 static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
422 static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
424 static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
426 static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); }
427 static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
428 static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); }
430 static int op( int x) { return u_field(x, 31, 30); }
431 static int rd( Register r) { return u_field(r->encoding(), 29, 25); }
432 static int fcn( int x) { return u_field(x, 29, 25); }
433 static int op3( int x) { return u_field(x, 24, 19); }
434 static int rs1( Register r) { return u_field(r->encoding(), 18, 14); }
435 static int rs2( Register r) { return u_field(r->encoding(), 4, 0); }
436 static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); }
437 static int cond( int x) { return u_field(x, 28, 25); }
438 static int cond_mov( int x) { return u_field(x, 17, 14); }
439 static int rcond( RCondition x) { return u_field(x, 12, 10); }
440 static int op2( int x) { return u_field(x, 24, 22); }
441 static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); }
442 static int branchcc( CC fcca) { return u_field(fcca, 21, 20); }
443 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); }
444 static int imm_asi( int x) { return u_field(x, 12, 5); }
445 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
446 static int opf_low6( int w) { return u_field(w, 10, 5); }
447 static int opf_low5( int w) { return u_field(w, 9, 5); }
448 static int op5( int x) { return u_field(x, 8, 5); }
449 static int trapcc( CC cc) { return u_field(cc, 12, 11); }
450 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
451 static int opf( int x) { return u_field(x, 13, 5); }
453 static bool is_cbcond( int x ) {
454 return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
455 inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
456 }
457 static bool is_cxb( int x ) {
458 assert(is_cbcond(x), "wrong instruction");
459 return (x & (1<<21)) != 0;
460 }
461 static int cond_cbcond( int x) { return u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); }
462 static int inv_cond_cbcond(int x) {
463 assert(is_cbcond(x), "wrong instruction");
464 return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3);
465 }
467 static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
468 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
470 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
471 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
472 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
473 static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); };
475 // some float instructions use this encoding on the op3 field
476 static int alt_op3(int op, FloatRegisterImpl::Width w) {
477 int r;
478 switch(w) {
479 case FloatRegisterImpl::S: r = op + 0; break;
480 case FloatRegisterImpl::D: r = op + 3; break;
481 case FloatRegisterImpl::Q: r = op + 2; break;
482 default: ShouldNotReachHere(); break;
483 }
484 return op3(r);
485 }
488 // compute inverse of simm
489 static int inv_simm(int x, int nbits) {
490 return (int)(x << (32 - nbits)) >> (32 - nbits);
491 }
493 static int inv_simm13( int x ) { return inv_simm(x, 13); }
495 // signed immediate, in low bits, nbits long
496 static int simm(int x, int nbits) {
497 assert_signed_range(x, nbits);
498 return x & (( 1 << nbits ) - 1);
499 }
501 // compute inverse of wdisp16
502 static intptr_t inv_wdisp16(int x, intptr_t pos) {
503 int lo = x & (( 1 << 14 ) - 1);
504 int hi = (x >> 20) & 3;
505 if (hi >= 2) hi |= ~1;
506 return (((hi << 14) | lo) << 2) + pos;
507 }
509 // word offset, 14 bits at LSend, 2 bits at B21, B20
510 static int wdisp16(intptr_t x, intptr_t off) {
511 intptr_t xx = x - off;
512 assert_signed_word_disp_range(xx, 16);
513 int r = (xx >> 2) & ((1 << 14) - 1)
514 | ( ( (xx>>(2+14)) & 3 ) << 20 );
515 assert( inv_wdisp16(r, off) == x, "inverse is not inverse");
516 return r;
517 }
519 // compute inverse of wdisp10
520 static intptr_t inv_wdisp10(int x, intptr_t pos) {
521 assert(is_cbcond(x), "wrong instruction");
522 int lo = inv_u_field(x, 12, 5);
523 int hi = (x >> 19) & 3;
524 if (hi >= 2) hi |= ~1;
525 return (((hi << 8) | lo) << 2) + pos;
526 }
528 // word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19]
529 static int wdisp10(intptr_t x, intptr_t off) {
530 assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction");
531 intptr_t xx = x - off;
532 assert_signed_word_disp_range(xx, 10);
533 int r = ( ( (xx >> 2 ) & ((1 << 8) - 1) ) << 5 )
534 | ( ( (xx >> (2+8)) & 3 ) << 19 );
535 // Have to fake cbcond instruction to pass assert in inv_wdisp10()
536 assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse");
537 return r;
538 }
540 // word displacement in low-order nbits bits
542 static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
543 int pre_sign_extend = x & (( 1 << nbits ) - 1);
544 int r = pre_sign_extend >= ( 1 << (nbits-1) )
545 ? pre_sign_extend | ~(( 1 << nbits ) - 1)
546 : pre_sign_extend;
547 return (r << 2) + pos;
548 }
550 static int wdisp( intptr_t x, intptr_t off, int nbits ) {
551 intptr_t xx = x - off;
552 assert_signed_word_disp_range(xx, nbits);
553 int r = (xx >> 2) & (( 1 << nbits ) - 1);
554 assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse");
555 return r;
556 }
559 // Extract the top 32 bits in a 64 bit word
560 static int32_t hi32( int64_t x ) {
561 int32_t r = int32_t( (uint64_t)x >> 32 );
562 return r;
563 }
565 // given a sethi instruction, extract the constant, left-justified
566 static int inv_hi22( int x ) {
567 return x << 10;
568 }
570 // create an imm22 field, given a 32-bit left-justified constant
571 static int hi22( int x ) {
572 int r = int( juint(x) >> 10 );
573 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
574 return r;
575 }
577 // create a low10 __value__ (not a field) for a given a 32-bit constant
578 static int low10( int x ) {
579 return x & ((1 << 10) - 1);
580 }
582 // AES crypto instructions supported only on certain processors
583 static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
585 // instruction only in VIS1
586 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
588 // instruction only in VIS3
589 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
591 // instruction only in v9
592 static void v9_only() { } // do nothing
594 // instruction deprecated in v9
595 static void v9_dep() { } // do nothing for now
597 // v8 has no CC field
598 static void v8_no_cc(CC cc) { if (cc) v9_only(); }
600 protected:
601 // Simple delay-slot scheme:
602 // In order to check the programmer, the assembler keeps track of deley slots.
603 // It forbids CTIs in delay slots (conservative, but should be OK).
604 // Also, when putting an instruction into a delay slot, you must say
605 // asm->delayed()->add(...), in order to check that you don't omit
606 // delay-slot instructions.
607 // To implement this, we use a simple FSA
609 #ifdef ASSERT
610 #define CHECK_DELAY
611 #endif
612 #ifdef CHECK_DELAY
613 enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
614 #endif
616 public:
617 // Tells assembler next instruction must NOT be in delay slot.
618 // Use at start of multinstruction macros.
619 void assert_not_delayed() {
620 // This is a separate overloading to avoid creation of string constants
621 // in non-asserted code--with some compilers this pollutes the object code.
622 #ifdef CHECK_DELAY
623 assert_not_delayed("next instruction should not be a delay slot");
624 #endif
625 }
626 void assert_not_delayed(const char* msg) {
627 #ifdef CHECK_DELAY
628 assert(delay_state == no_delay, msg);
629 #endif
630 }
632 protected:
633 // Insert a nop if the previous is cbcond
634 void insert_nop_after_cbcond() {
635 if (UseCBCond && cbcond_before()) {
636 nop();
637 }
638 }
639 // Delay slot helpers
640 // cti is called when emitting control-transfer instruction,
641 // BEFORE doing the emitting.
642 // Only effective when assertion-checking is enabled.
643 void cti() {
644 // A cbcond instruction immediately followed by a CTI
645 // instruction introduces pipeline stalls, we need to avoid that.
646 no_cbcond_before();
647 #ifdef CHECK_DELAY
648 assert_not_delayed("cti should not be in delay slot");
649 #endif
650 }
652 // called when emitting cti with a delay slot, AFTER emitting
653 void has_delay_slot() {
654 #ifdef CHECK_DELAY
655 assert_not_delayed("just checking");
656 delay_state = at_delay_slot;
657 #endif
658 }
660 // cbcond instruction should not be generated one after an other
661 bool cbcond_before() {
662 if (offset() == 0) return false; // it is first instruction
663 int x = *(int*)(intptr_t(pc()) - 4); // previous instruction
664 return is_cbcond(x);
665 }
667 void no_cbcond_before() {
668 assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond");
669 }
670 public:
672 bool use_cbcond(Label& L) {
673 if (!UseCBCond || cbcond_before()) return false;
674 intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
675 assert( (x & 3) == 0, "not word aligned");
676 return is_simm12(x);
677 }
679 // Tells assembler you know that next instruction is delayed
680 Assembler* delayed() {
681 #ifdef CHECK_DELAY
682 assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
683 delay_state = filling_delay_slot;
684 #endif
685 return this;
686 }
688 void flush() {
689 #ifdef CHECK_DELAY
690 assert ( delay_state == no_delay, "ending code with a delay slot");
691 #endif
692 AbstractAssembler::flush();
693 }
695 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32
696 inline void emit_data(int x) { emit_int32(x); }
697 inline void emit_data(int, RelocationHolder const&);
698 inline void emit_data(int, relocInfo::relocType rtype);
699 // helper for above fcns
700 inline void check_delay();
703 public:
704 // instructions, refer to page numbers in the SPARC Architecture Manual, V9
706 // pp 135 (addc was addx in v8)
708 inline void add(Register s1, Register s2, Register d );
709 inline void add(Register s1, int simm13a, Register d );
711 void addcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
712 void addcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
713 void addc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); }
714 void addc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
715 void addccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
716 void addccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
719 // 4-operand AES instructions
721 void aes_eround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
722 void aes_eround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
723 void aes_dround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
724 void aes_dround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
725 void aes_eround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
726 void aes_eround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
727 void aes_dround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
728 void aes_dround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
729 void aes_kexpand1( FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | u_field(imm5a, 13, 9) | op5(aes_kexpand1_op5) | fs2(s2, FloatRegisterImpl::D) ); }
732 // 3-operand AES instructions
734 void aes_kexpand0( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand0_opf) | fs2(s2, FloatRegisterImpl::D) ); }
735 void aes_kexpand2( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand2_opf) | fs2(s2, FloatRegisterImpl::D) ); }
737 // pp 136
739 inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
740 inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L);
742 // compare and branch
743 inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L);
744 inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L);
746 protected: // use MacroAssembler::br instead
748 // pp 138
750 inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
751 inline void fb( Condition c, bool a, Label& L );
753 // pp 141
755 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
756 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
758 // pp 144
760 inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
761 inline void br( Condition c, bool a, Label& L );
763 // pp 146
765 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
766 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
768 // pp 149
770 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
771 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
773 public:
775 // pp 150
777 // These instructions compare the contents of s2 with the contents of
778 // memory at address in s1. If the values are equal, the contents of memory
779 // at address s1 is swapped with the data in d. If the values are not equal,
780 // the the contents of memory at s1 is loaded into d, without the swap.
782 void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
783 void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
785 // pp 152
787 void udiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); }
788 void udiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
789 void sdiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); }
790 void sdiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
791 void udivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
792 void udivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
793 void sdivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
794 void sdivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
796 // pp 155
798 void done() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(0) | op3(done_op3) ); }
799 void retry() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(1) | op3(retry_op3) ); }
801 // pp 156
803 void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); }
804 void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); }
806 // pp 157
808 void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
809 void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
811 // pp 159
813 void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
814 void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
816 // pp 160
818 void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
820 // pp 161
822 void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); }
823 void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); }
825 // pp 162
827 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
829 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
831 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }
833 // pp 163
835 void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); }
836 void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
837 void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); }
839 // FXORs/FXORd instructions
841 void fxor( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(flog3_op3) | fs1(s1, w) | opf(0x6E - w) | fs2(s2, w)); }
843 // pp 164
845 void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
847 // pp 165
849 inline void flush( Register s1, Register s2 );
850 inline void flush( Register s1, int simm13a);
852 // pp 167
854 void flushw() { v9_only(); emit_int32( op(arith_op) | op3(flushw_op3) ); }
856 // pp 168
858 void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_int32( op(branch_op) | u_field(const22a, 21, 0) ); }
859 // v8 unimp == illtrap(0)
861 // pp 169
863 void impdep1( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); }
864 void impdep2( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); }
866 // pp 170
868 void jmpl( Register s1, Register s2, Register d );
869 void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
871 // 171
873 inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
874 inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
877 inline void ldfsr( Register s1, Register s2 );
878 inline void ldfsr( Register s1, int simm13a);
879 inline void ldxfsr( Register s1, Register s2 );
880 inline void ldxfsr( Register s1, int simm13a);
882 // 173
884 void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
885 void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
887 // pp 175, lduw is ld on v8
889 inline void ldsb( Register s1, Register s2, Register d );
890 inline void ldsb( Register s1, int simm13a, Register d);
891 inline void ldsh( Register s1, Register s2, Register d );
892 inline void ldsh( Register s1, int simm13a, Register d);
893 inline void ldsw( Register s1, Register s2, Register d );
894 inline void ldsw( Register s1, int simm13a, Register d);
895 inline void ldub( Register s1, Register s2, Register d );
896 inline void ldub( Register s1, int simm13a, Register d);
897 inline void lduh( Register s1, Register s2, Register d );
898 inline void lduh( Register s1, int simm13a, Register d);
899 inline void lduw( Register s1, Register s2, Register d );
900 inline void lduw( Register s1, int simm13a, Register d);
901 inline void ldx( Register s1, Register s2, Register d );
902 inline void ldx( Register s1, int simm13a, Register d);
903 inline void ldd( Register s1, Register s2, Register d );
904 inline void ldd( Register s1, int simm13a, Register d);
906 // pp 177
908 void ldsba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
909 void ldsba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
910 void ldsha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
911 void ldsha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
912 void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
913 void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
914 void lduba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
915 void lduba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
916 void lduha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
917 void lduha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
918 void lduwa( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
919 void lduwa( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
920 void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
921 void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
923 // pp 181
925 void and3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
926 void and3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
927 void andcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
928 void andcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
929 void andn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
930 void andn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
931 void andncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
932 void andncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
933 void or3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
934 void or3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
935 void orcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
936 void orcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
937 void orn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
938 void orn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
939 void orncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
940 void orncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
941 void xor3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
942 void xor3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
943 void xorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
944 void xorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
945 void xnor( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); }
946 void xnor( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
947 void xnorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
948 void xnorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
950 // pp 183
952 void membar( Membar_mask_bits const7a ) { v9_only(); emit_int32( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); }
954 // pp 185
956 void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); }
958 // pp 189
960 void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); }
962 // pp 191
964 void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); }
965 void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); }
967 // pp 195
969 void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); }
970 void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); }
972 // pp 196
974 void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); }
975 void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
976 void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
977 void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
978 void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
979 void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
981 // pp 197
983 void umul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); }
984 void umul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
985 void smul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); }
986 void smul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
987 void umulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
988 void umulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
989 void smulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
990 void smulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
992 // pp 201
994 void nop() { emit_int32( op(branch_op) | op2(sethi_op2) ); }
997 // pp 202
999 void popc( Register s, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
1000 void popc( int simm13a, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
1002 // pp 203
1004 void prefetch( Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
1005 void prefetch( Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
1007 void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1008 void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1010 // pp 208
1012 // not implementing read privileged register
1014 inline void rdy( Register d) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); }
1015 inline void rdccr( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); }
1016 inline void rdasi( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); }
1017 inline void rdtick( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon!
1018 inline void rdpc( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); }
1019 inline void rdfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); }
1021 // pp 213
1023 inline void rett( Register s1, Register s2);
1024 inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
1026 // pp 214
1028 void save( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); }
1029 void save( Register s1, int simm13a, Register d ) {
1030 // make sure frame is at least large enough for the register save area
1031 assert(-simm13a >= 16 * wordSize, "frame too small");
1032 emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) );
1033 }
1035 void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); }
1036 void restore( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1038 // pp 216
1040 void saved() { v9_only(); emit_int32( op(arith_op) | fcn(0) | op3(saved_op3)); }
1041 void restored() { v9_only(); emit_int32( op(arith_op) | fcn(1) | op3(saved_op3)); }
1043 // pp 217
1045 inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
1046 // pp 218
1048 void sll( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1049 void sll( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1050 void srl( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1051 void srl( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1052 void sra( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1053 void sra( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1055 void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1056 void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1057 void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1058 void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1059 void srax( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1060 void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1062 // pp 220
1064 void sir( int simm13a ) { emit_int32( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); }
1066 // pp 221
1068 void stbar() { emit_int32( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); }
1070 // pp 222
1072 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
1073 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
1075 inline void stfsr( Register s1, Register s2 );
1076 inline void stfsr( Register s1, int simm13a);
1077 inline void stxfsr( Register s1, Register s2 );
1078 inline void stxfsr( Register s1, int simm13a);
1080 // pp 224
1082 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1083 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1085 // p 226
1087 inline void stb( Register d, Register s1, Register s2 );
1088 inline void stb( Register d, Register s1, int simm13a);
1089 inline void sth( Register d, Register s1, Register s2 );
1090 inline void sth( Register d, Register s1, int simm13a);
1091 inline void stw( Register d, Register s1, Register s2 );
1092 inline void stw( Register d, Register s1, int simm13a);
1093 inline void stx( Register d, Register s1, Register s2 );
1094 inline void stx( Register d, Register s1, int simm13a);
1095 inline void std( Register d, Register s1, Register s2 );
1096 inline void std( Register d, Register s1, int simm13a);
1098 // pp 177
1100 void stba( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1101 void stba( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1102 void stha( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1103 void stha( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1104 void stwa( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1105 void stwa( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1106 void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1107 void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1108 void stda( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1109 void stda( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1111 // pp 230
1113 void sub( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); }
1114 void sub( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1116 void subcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
1117 void subcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1118 void subc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); }
1119 void subc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1120 void subccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1121 void subccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1123 // pp 231
1125 inline void swap( Register s1, Register s2, Register d );
1126 inline void swap( Register s1, int simm13a, Register d);
1128 // pp 232
1130 void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1131 void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1133 // pp 234, note op in book is wrong, see pp 268
1135 void taddcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); }
1136 void taddcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1138 // pp 235
1140 void tsubcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); }
1141 void tsubcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1143 // pp 237
1145 void trap( Condition c, CC cc, Register s1, Register s2 ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
1146 void trap( Condition c, CC cc, Register s1, int trapa ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
1147 // simple uncond. trap
1148 void trap( int trapa ) { trap( always, icc, G0, trapa ); }
1150 // pp 239 omit write priv register for now
1152 inline void wry( Register d) { v9_dep(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
1153 inline void wrccr(Register s) { v9_only(); emit_int32( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
1154 inline void wrccr(Register s, int simm13a) { v9_only(); emit_int32( op(arith_op) |
1155 rs1(s) |
1156 op3(wrreg_op3) |
1157 u_field(2, 29, 25) |
1158 immed(true) |
1159 simm(simm13a, 13)); }
1160 inline void wrasi(Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
1161 // wrasi(d, imm) stores (d xor imm) to asi
1162 inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) |
1163 u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); }
1164 inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1167 // VIS3 instructions
1169 void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
1170 void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
1171 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
1173 void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
1174 void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
1176 // Creation
1177 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1178 #ifdef CHECK_DELAY
1179 delay_state = no_delay;
1180 #endif
1181 }
1182 };
1184 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP