Mercurial > jdk8-mips64-public > hotspot / file revision
src/cpu/mips/vm/nativeInst_mips.cpp@17884ee5d053
src/cpu/mips/vm/nativeInst_mips.cpp
Wed, 04 Dec 2019 18:01:06 +0800
- author
- jiefu
- date
- Wed, 04 Dec 2019 18:01:06 +0800
- changeset 9761
- 17884ee5d053
- parent 9645
- ac996ba07f9d
- child 9932
- 86ea9a02a717
- permissions
- -rw-r--r--
#10637: java/util/stream/test/org/openjdk/tests/java/util/stream/SliceOpTest.java fails with -XX:ReservedCodeCacheSize=256m
Reviewed-by: aoqi
1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.hpp"
28 #include "memory/resourceArea.hpp"
29 #include "nativeInst_mips.hpp"
30 #include "oops/oop.inline.hpp"
31 #include "runtime/handles.hpp"
32 #include "runtime/sharedRuntime.hpp"
33 #include "runtime/stubRoutines.hpp"
34 #include "utilities/ostream.hpp"
35 #ifdef COMPILER1
36 #include "c1/c1_Runtime1.hpp"
37 #endif
39 #include <sys/mman.h>
41 void NativeInstruction::wrote(int offset) {
42 ICache::invalidate_word(addr_at(offset));
43 }
45 void NativeInstruction::set_long_at(int offset, long i) {
46 address addr = addr_at(offset);
47 *(long*)addr = i;
48 #ifdef _LP64
49 ICache::invalidate_range(addr, 8);
50 #else
51 ICache::invalidate_word(addr);
52 #endif
53 }
55 static int illegal_instruction_bits = 0;
57 int NativeInstruction::illegal_instruction() {
58 if (illegal_instruction_bits == 0) {
59 ResourceMark rm;
60 char buf[40];
61 CodeBuffer cbuf((address)&buf[0], 20);
62 MacroAssembler* a = new MacroAssembler(&cbuf);
63 address ia = a->pc();
64 a->brk(11);
65 int bits = *(int*)ia;
66 illegal_instruction_bits = bits;
67 }
68 return illegal_instruction_bits;
69 }
71 bool NativeInstruction::is_int_branch() {
72 switch(Assembler::opcode(insn_word())) {
73 case Assembler::beq_op:
74 case Assembler::beql_op:
75 case Assembler::bgtz_op:
76 case Assembler::bgtzl_op:
77 case Assembler::blez_op:
78 case Assembler::blezl_op:
79 case Assembler::bne_op:
80 case Assembler::bnel_op:
81 return true;
82 case Assembler::regimm_op:
83 switch(Assembler::rt(insn_word())) {
84 case Assembler::bgez_op:
85 case Assembler::bgezal_op:
86 case Assembler::bgezall_op:
87 case Assembler::bgezl_op:
88 case Assembler::bltz_op:
89 case Assembler::bltzal_op:
90 case Assembler::bltzall_op:
91 case Assembler::bltzl_op:
92 return true;
93 }
94 }
96 return false;
97 }
99 bool NativeInstruction::is_float_branch() {
100 if (!is_op(Assembler::cop1_op) ||
101 !is_rs((Register)Assembler::bc1f_op)) return false;
103 switch(Assembler::rt(insn_word())) {
104 case Assembler::bcf_op:
105 case Assembler::bcfl_op:
106 case Assembler::bct_op:
107 case Assembler::bctl_op:
108 return true;
109 }
111 return false;
112 }
115 void NativeCall::verify() {
116 // make sure code pattern is actually a call instruction
117 #ifndef _LP64
118 if ( !is_op(Assembler::lui_op) ||
119 !is_op(int_at(4), Assembler::addiu_op) ||
120 !is_special_op(int_at(8), Assembler::jalr_op) ) {
121 fatal("not a call");
122 }
123 #else
125 // nop
126 // nop
127 // nop
128 // nop
129 // jal targe
130 // nop
131 if ( is_nop() &&
132 nativeInstruction_at(addr_at(4))->is_nop() &&
133 nativeInstruction_at(addr_at(8))->is_nop() &&
134 nativeInstruction_at(addr_at(12))->is_nop() &&
135 is_op(int_at(16), Assembler::jal_op) &&
136 nativeInstruction_at(addr_at(20))->is_nop() ) {
137 return;
138 }
140 // jal targe
141 // nop
142 if ( is_op(int_at(0), Assembler::jal_op) &&
143 nativeInstruction_at(addr_at(4))->is_nop() ) {
144 return;
145 }
147 // li64
148 if ( is_op(Assembler::lui_op) &&
149 is_op(int_at(4), Assembler::ori_op) &&
150 is_special_op(int_at(8), Assembler::dsll_op) &&
151 is_op(int_at(12), Assembler::ori_op) &&
152 is_special_op(int_at(16), Assembler::dsll_op) &&
153 is_op(int_at(20), Assembler::ori_op) &&
154 is_special_op(int_at(24), Assembler::jalr_op) ) {
155 return;
156 }
158 //lui dst, imm16
159 //ori dst, dst, imm16
160 //dsll dst, dst, 16
161 //ori dst, dst, imm16
162 if ( is_op(Assembler::lui_op) &&
163 is_op (int_at(4), Assembler::ori_op) &&
164 is_special_op(int_at(8), Assembler::dsll_op) &&
165 is_op (int_at(12), Assembler::ori_op) &&
166 is_special_op(int_at(16), Assembler::jalr_op) ) {
167 return;
168 }
170 //ori dst, R0, imm16
171 //dsll dst, dst, 16
172 //ori dst, dst, imm16
173 //nop
174 if ( is_op(Assembler::ori_op) &&
175 is_special_op(int_at(4), Assembler::dsll_op) &&
176 is_op (int_at(8), Assembler::ori_op) &&
177 nativeInstruction_at(addr_at(12))->is_nop() &&
178 is_special_op(int_at(16), Assembler::jalr_op) ) {
179 return;
180 }
182 //ori dst, R0, imm16
183 //dsll dst, dst, 16
184 //nop
185 //nop
186 if ( is_op(Assembler::ori_op) &&
187 is_special_op(int_at(4), Assembler::dsll_op) &&
188 nativeInstruction_at(addr_at(8))->is_nop() &&
189 nativeInstruction_at(addr_at(12))->is_nop() &&
190 is_special_op(int_at(16), Assembler::jalr_op) ) {
191 return;
192 }
194 //daddiu dst, R0, imm16
195 //nop
196 //nop
197 //nop
198 if ( is_op(Assembler::daddiu_op) &&
199 nativeInstruction_at(addr_at(4))->is_nop() &&
200 nativeInstruction_at(addr_at(8))->is_nop() &&
201 nativeInstruction_at(addr_at(12))->is_nop() &&
202 is_special_op(int_at(16), Assembler::jalr_op) ) {
203 return;
204 }
206 // FIXME: why add jr_op here?
207 //daddiu dst, R0, imm16
208 //nop
209 //nop
210 //nop
211 if ( is_op(Assembler::daddiu_op) &&
212 nativeInstruction_at(addr_at(4))->is_nop() &&
213 nativeInstruction_at(addr_at(8))->is_nop() &&
214 nativeInstruction_at(addr_at(12))->is_nop() &&
215 is_special_op(int_at(16), Assembler::jr_op) ) {
216 return;
217 }
219 //lui dst, imm16
220 //ori dst, dst, imm16
221 //nop
222 //nop
223 if ( is_op(Assembler::lui_op) &&
224 is_op (int_at(4), Assembler::ori_op) &&
225 nativeInstruction_at(addr_at(8))->is_nop() &&
226 nativeInstruction_at(addr_at(12))->is_nop() &&
227 is_special_op(int_at(16), Assembler::jalr_op) ) {
228 return;
229 }
231 //lui dst, imm16
232 //nop
233 //nop
234 //nop
235 if ( is_op(Assembler::lui_op) &&
236 nativeInstruction_at(addr_at(4))->is_nop() &&
237 nativeInstruction_at(addr_at(8))->is_nop() &&
238 nativeInstruction_at(addr_at(12))->is_nop() &&
239 is_special_op(int_at(16), Assembler::jalr_op) ) {
240 return;
241 }
243 //daddiu dst, R0, imm16
244 //nop
245 if ( is_op(Assembler::daddiu_op) &&
246 nativeInstruction_at(addr_at(4))->is_nop() &&
247 is_special_op(int_at(8), Assembler::jalr_op) ) {
248 return;
249 }
251 //lui dst, imm16
252 //ori dst, dst, imm16
253 if ( is_op(Assembler::lui_op) &&
254 is_op (int_at(4), Assembler::ori_op) &&
255 is_special_op(int_at(8), Assembler::jalr_op) ) {
256 return;
257 }
259 //lui dst, imm16
260 //nop
261 if ( is_op(Assembler::lui_op) &&
262 nativeInstruction_at(addr_at(4))->is_nop() &&
263 is_special_op(int_at(8), Assembler::jalr_op) ) {
264 return;
265 }
267 fatal("not a call");
268 #endif
269 }
271 address NativeCall::destination() const {
272 #ifndef _LP64
273 return (address)Assembler::merge(int_at(4)&0xffff, long_at(0)&0xffff);
274 #else
275 // jal target
276 // nop
277 if ( is_op(int_at(0), Assembler::jal_op) &&
278 nativeInstruction_at(addr_at(4))->is_nop()) {
279 int instr_index = int_at(0) & 0x3ffffff;
280 intptr_t target_high = ((intptr_t)addr_at(4)) & 0xfffffffff0000000;
281 intptr_t target = target_high | (instr_index << 2);
282 return (address)target;
283 }
285 // nop
286 // nop
287 // nop
288 // nop
289 // jal target
290 // nop
291 if ( nativeInstruction_at(addr_at(0))->is_nop() &&
292 nativeInstruction_at(addr_at(4))->is_nop() &&
293 nativeInstruction_at(addr_at(8))->is_nop() &&
294 nativeInstruction_at(addr_at(12))->is_nop() &&
295 is_op(int_at(16), Assembler::jal_op) &&
296 nativeInstruction_at(addr_at(20))->is_nop()) {
297 int instr_index = int_at(16) & 0x3ffffff;
298 intptr_t target_high = ((intptr_t)addr_at(20)) & 0xfffffffff0000000;
299 intptr_t target = target_high | (instr_index << 2);
300 return (address)target;
301 }
303 // li64
304 if ( is_op(Assembler::lui_op) &&
305 is_op(int_at(4), Assembler::ori_op) &&
306 is_special_op(int_at(8), Assembler::dsll_op) &&
307 is_op(int_at(12), Assembler::ori_op) &&
308 is_special_op(int_at(16), Assembler::dsll_op) &&
309 is_op(int_at(20), Assembler::ori_op) ) {
311 return (address)Assembler::merge( (intptr_t)(int_at(20) & 0xffff),
312 (intptr_t)(int_at(12) & 0xffff),
313 (intptr_t)(int_at(4) & 0xffff),
314 (intptr_t)(int_at(0) & 0xffff));
315 }
317 //lui dst, imm16
318 //ori dst, dst, imm16
319 //dsll dst, dst, 16
320 //ori dst, dst, imm16
321 if ( is_op(Assembler::lui_op) &&
322 is_op (int_at(4), Assembler::ori_op) &&
323 is_special_op(int_at(8), Assembler::dsll_op) &&
324 is_op (int_at(12), Assembler::ori_op) ) {
326 return (address)Assembler::merge( (intptr_t)(int_at(12) & 0xffff),
327 (intptr_t)(int_at(4) & 0xffff),
328 (intptr_t)(int_at(0) & 0xffff),
329 (intptr_t)0);
330 }
332 //ori dst, R0, imm16
333 //dsll dst, dst, 16
334 //ori dst, dst, imm16
335 //nop
336 if ( is_op(Assembler::ori_op) &&
337 is_special_op(int_at(4), Assembler::dsll_op) &&
338 is_op (int_at(8), Assembler::ori_op) &&
339 nativeInstruction_at(addr_at(12))->is_nop()) {
341 return (address)Assembler::merge( (intptr_t)(int_at(8) & 0xffff),
342 (intptr_t)(int_at(0) & 0xffff),
343 (intptr_t)0,
344 (intptr_t)0);
345 }
347 //ori dst, R0, imm16
348 //dsll dst, dst, 16
349 //nop
350 //nop
351 if ( is_op(Assembler::ori_op) &&
352 is_special_op(int_at(4), Assembler::dsll_op) &&
353 nativeInstruction_at(addr_at(8))->is_nop() &&
354 nativeInstruction_at(addr_at(12))->is_nop()) {
356 return (address)Assembler::merge( (intptr_t)(0),
357 (intptr_t)(int_at(0) & 0xffff),
358 (intptr_t)0,
359 (intptr_t)0);
360 }
362 //daddiu dst, R0, imm16
363 //nop
364 //nop <-- optional
365 //nop <-- optional
366 if ( is_op(Assembler::daddiu_op) &&
367 nativeInstruction_at(addr_at(4))->is_nop() ) {
369 int sign = int_at(0) & 0x8000;
370 if (sign == 0) {
371 return (address)Assembler::merge( (intptr_t)(int_at(0) & 0xffff),
372 (intptr_t)0,
373 (intptr_t)0,
374 (intptr_t)0);
375 } else {
376 return (address)Assembler::merge( (intptr_t)(int_at(0) & 0xffff),
377 (intptr_t)(0xffff),
378 (intptr_t)(0xffff),
379 (intptr_t)(0xffff));
380 }
381 }
383 //lui dst, imm16
384 //ori dst, dst, imm16
385 //nop <-- optional
386 //nop <-- optional
387 if ( is_op(Assembler::lui_op) &&
388 is_op (int_at(4), Assembler::ori_op) ) {
390 int sign = int_at(0) & 0x8000;
391 if (sign == 0) {
392 return (address)Assembler::merge( (intptr_t)(int_at(4) & 0xffff),
393 (intptr_t)(int_at(0) & 0xffff),
394 (intptr_t)0,
395 (intptr_t)0);
396 } else {
397 return (address)Assembler::merge( (intptr_t)(int_at(4) & 0xffff),
398 (intptr_t)(int_at(0) & 0xffff),
399 (intptr_t)(0xffff),
400 (intptr_t)(0xffff));
401 }
402 }
404 //lui dst, imm16
405 //nop
406 //nop <-- optional
407 //nop <-- optional
408 if ( is_op(Assembler::lui_op) &&
409 nativeInstruction_at(addr_at(4))->is_nop() ) {
411 int sign = int_at(0) & 0x8000;
412 if (sign == 0) {
413 return (address)Assembler::merge( (intptr_t)0,
414 (intptr_t)(int_at(0) & 0xffff),
415 (intptr_t)0,
416 (intptr_t)0);
417 } else {
418 return (address)Assembler::merge( (intptr_t)0,
419 (intptr_t)(int_at(0) & 0xffff),
420 (intptr_t)(0xffff),
421 (intptr_t)(0xffff));
422 }
423 }
425 fatal("not a call");
426 #endif
427 }
429 // manual implementation of GSSQ
430 //
431 // 00000001200009c0 <atomic_store128>:
432 // 1200009c0: 0085202d daddu a0, a0, a1
433 // 1200009c4: e8860027 gssq a2, a3, 0(a0)
434 // 1200009c8: 03e00008 jr ra
435 // 1200009cc: 00000000 nop
436 //
437 typedef void (* atomic_store128_ptr)(long *addr, int offset, long low64, long hi64);
439 static int *buf;
441 static atomic_store128_ptr get_atomic_store128_func() {
442 assert(UseLEXT1, "UseLEXT1 must be true");
443 static atomic_store128_ptr p = NULL;
444 if (p != NULL)
445 return p;
447 buf = (int *)mmap(NULL, 1024, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS,
448 -1, 0);
449 buf[0] = 0x0085202d;
450 buf[1] = (0x3a << 26) | (4 << 21) | (6 << 16) | 0x27; /* gssq $a2, $a3, 0($a0) */
451 buf[2] = 0x03e00008;
452 buf[3] = 0;
454 asm("sync");
455 p = (atomic_store128_ptr)buf;
456 return p;
457 }
459 void NativeCall::patch_on_jal_only(address dst) {
460 #ifdef _LP64
461 long dest = ((long)dst - (((long)addr_at(4)) & 0xfffffffff0000000))>>2;
462 #else
463 long dest = ((long)dst - (((long)addr_at(4)) & 0xf0000000))>>2;
464 #endif
465 if ((dest >= 0) && (dest < (1<<26))) {
466 jint jal_inst = (Assembler::jal_op << 26) | dest;
467 set_int_at(0, jal_inst);
468 ICache::invalidate_range(addr_at(0), 4);
469 } else {
470 ShouldNotReachHere();
471 }
472 }
474 void NativeCall::patch_on_jal_gs(address dst) {
475 #ifdef _LP64
476 long dest = ((long)dst - (((long)addr_at(20)) & 0xfffffffff0000000))>>2;
477 #else
478 long dest = ((long)dst - (((long)addr_at(20)) & 0xf0000000))>>2;
479 #endif
480 if ((dest >= 0) && (dest < (1<<26))) {
481 jint jal_inst = (Assembler::jal_op << 26) | dest;
482 set_int_at(16, jal_inst);
483 ICache::invalidate_range(addr_at(16), 4);
484 } else {
485 ShouldNotReachHere();
486 }
487 }
489 void NativeCall::patch_on_jal(address dst) {
490 patch_on_jal_gs(dst);
491 }
493 void NativeCall::patch_on_jalr_gs(address dst) {
494 patch_set48_gs(dst);
495 }
497 void NativeCall::patch_on_jalr(address dst) {
498 patch_set48(dst);
499 }
501 void NativeCall::patch_set48_gs(address dest) {
502 jlong value = (jlong) dest;
503 int rt_reg = (int_at(0) & (0x1f << 16));
505 if (rt_reg == 0) rt_reg = 25 << 16; // r25 is T9
507 int rs_reg = rt_reg << 5;
508 int rd_reg = rt_reg >> 5;
510 int hi = (int)(value >> 32);
511 int lo = (int)(value & ~0);
512 int count = 0;
513 int insts[4] = {0, 0, 0, 0};
515 if (value == lo) { // 32-bit integer
516 if (Assembler::is_simm16(value)) {
517 insts[count] = (Assembler::daddiu_op << 26) | rt_reg | Assembler::split_low(value);
518 count += 1;
519 } else {
520 insts[count] = (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 16);
521 count += 1;
522 if (Assembler::split_low(value)) {
523 insts[count] = (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value);
524 count += 1;
525 }
526 }
527 } else if (hi == 0) { // hardware zero-extends to upper 32
528 insts[count] = (Assembler::ori_op << 26) | rt_reg | Assembler::split_low(julong(value) >> 16);
529 count += 1;
530 insts[count] = (Assembler::dsll_op) | rt_reg | rd_reg | (16 << 6);
531 count += 1;
532 if (Assembler::split_low(value)) {
533 insts[count] = (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value);
534 count += 1;
535 }
536 } else if ((value> 0) && Assembler::is_simm16(value >> 32)) {
537 insts[count] = (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 32);
538 count += 1;
539 insts[count] = (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value >> 16);
540 count += 1;
541 insts[count] = (Assembler::dsll_op) | rt_reg | rd_reg | (16 << 6);
542 count += 1;
543 insts[count] = (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value);
544 count += 1;
545 } else {
546 tty->print_cr("dest = 0x%x", value);
547 guarantee(false, "Not supported yet !");
548 }
550 while (count < 4) {
551 insts[count] = 0;
552 count++;
553 }
555 guarantee(((long)addr_at(0) % (BytesPerWord * 2)) == 0, "must be aligned");
556 atomic_store128_ptr func = get_atomic_store128_func();
557 (*func)((long *)addr_at(0), 0, *(long *)&insts[0], *(long *)&insts[2]);
559 ICache::invalidate_range(addr_at(0), 16);
560 }
562 void NativeCall::patch_set32_gs(address dest) {
563 jlong value = (jlong) dest;
564 int rt_reg = (int_at(0) & (0x1f << 16));
566 if (rt_reg == 0) rt_reg = 25 << 16; // r25 is T9
568 int rs_reg = rt_reg << 5;
569 int rd_reg = rt_reg >> 5;
571 int hi = (int)(value >> 32);
572 int lo = (int)(value & ~0);
574 int count = 0;
576 int insts[2] = {0, 0};
578 if (value == lo) { // 32-bit integer
579 if (Assembler::is_simm16(value)) {
580 //daddiu(d, R0, value);
581 //set_int_at(count << 2, (Assembler::daddiu_op << 26) | rt_reg | Assembler::split_low(value));
582 insts[count] = (Assembler::daddiu_op << 26) | rt_reg | Assembler::split_low(value);
583 count += 1;
584 } else {
585 //lui(d, split_low(value >> 16));
586 //set_int_at(count << 2, (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 16));
587 insts[count] = (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 16);
588 count += 1;
589 if (Assembler::split_low(value)) {
590 //ori(d, d, split_low(value));
591 //set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value));
592 insts[count] = (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value);
593 count += 1;
594 }
595 }
596 } else {
597 tty->print_cr("dest = 0x%x", value);
598 guarantee(false, "Not supported yet !");
599 }
601 while (count < 2) {
602 //nop();
603 //set_int_at(count << 2, 0);
604 insts[count] = 0;
605 count++;
606 }
608 long inst = insts[1];
609 inst = inst << 32;
610 inst = inst + insts[0];
612 set_long_at(0, inst);
613 }
615 void NativeCall::patch_set48(address dest) {
616 jlong value = (jlong) dest;
617 int rt_reg = (int_at(0) & (0x1f << 16));
619 if (rt_reg == 0) rt_reg = 25 << 16; // r25 is T9
621 int rs_reg = rt_reg << 5;
622 int rd_reg = rt_reg >> 5;
624 int hi = (int)(value >> 32);
625 int lo = (int)(value & ~0);
627 int count = 0;
629 if (value == lo) { // 32-bit integer
630 if (Assembler::is_simm16(value)) {
631 //daddiu(d, R0, value);
632 set_int_at(count << 2, (Assembler::daddiu_op << 26) | rt_reg | Assembler::split_low(value));
633 count += 1;
634 } else {
635 //lui(d, split_low(value >> 16));
636 set_int_at(count << 2, (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 16));
637 count += 1;
638 if (Assembler::split_low(value)) {
639 //ori(d, d, split_low(value));
640 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value));
641 count += 1;
642 }
643 }
644 } else if (hi == 0) { // hardware zero-extends to upper 32
645 //ori(d, R0, julong(value) >> 16);
646 set_int_at(count << 2, (Assembler::ori_op << 26) | rt_reg | Assembler::split_low(julong(value) >> 16));
647 count += 1;
648 //dsll(d, d, 16);
649 set_int_at(count << 2, (Assembler::dsll_op) | rt_reg | rd_reg | (16 << 6));
650 count += 1;
651 if (Assembler::split_low(value)) {
652 //ori(d, d, split_low(value));
653 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value));
654 count += 1;
655 }
656 } else if ((value> 0) && Assembler::is_simm16(value >> 32)) {
657 //lui(d, value >> 32);
658 set_int_at(count << 2, (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 32));
659 count += 1;
660 //ori(d, d, split_low(value >> 16));
661 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value >> 16));
662 count += 1;
663 //dsll(d, d, 16);
664 set_int_at(count << 2, (Assembler::dsll_op) | rt_reg | rd_reg | (16 << 6));
665 count += 1;
666 //ori(d, d, split_low(value));
667 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value));
668 count += 1;
669 } else {
670 tty->print_cr("dest = 0x%x", value);
671 guarantee(false, "Not supported yet !");
672 }
674 while (count < 4) {
675 //nop();
676 set_int_at(count << 2, 0);
677 count++;
678 }
680 ICache::invalidate_range(addr_at(0), 16);
681 }
683 void NativeCall::patch_set32(address dest) {
684 patch_set32_gs(dest);
685 }
687 void NativeCall::set_destination(address dest) {
688 #ifndef _LP64
689 OrderAccess::fence();
690 set_int_at(0, (int_at(0) & 0xffff0000) | (Assembler::split_high((intptr_t)dest) & 0xffff));
691 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low((intptr_t)dest) & 0xffff));
692 ICache::invalidate_range(addr_at(0), 8);
693 #else
694 OrderAccess::fence();
696 // li64
697 if (is_special_op(int_at(16), Assembler::dsll_op)) {
698 int first_word = int_at(0);
699 set_int_at(0, 0x1000ffff); /* .1: b .1 */
700 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low((intptr_t)dest >> 32) & 0xffff));
701 set_int_at(12, (int_at(12) & 0xffff0000) | (Assembler::split_low((intptr_t)dest >> 16) & 0xffff));
702 set_int_at(20, (int_at(20) & 0xffff0000) | (Assembler::split_low((intptr_t)dest) & 0xffff));
703 set_int_at(0, (first_word & 0xffff0000) | (Assembler::split_low((intptr_t)dest >> 48) & 0xffff));
704 ICache::invalidate_range(addr_at(0), 24);
705 } else if (is_op(int_at(16), Assembler::jal_op)) {
706 if (UseLEXT1) {
707 patch_on_jal_gs(dest);
708 } else {
709 patch_on_jal(dest);
710 }
711 } else if (is_op(int_at(0), Assembler::jal_op)) {
712 patch_on_jal_only(dest);
713 } else if (is_special_op(int_at(16), Assembler::jalr_op)) {
714 if (UseLEXT1) {
715 patch_on_jalr_gs(dest);
716 } else {
717 patch_on_jalr(dest);
718 }
719 } else if (is_special_op(int_at(8), Assembler::jalr_op)) {
720 guarantee(!os::is_MP() || (((long)addr_at(0) % 8) == 0), "destination must be aligned by 8");
721 if (UseLEXT1) {
722 patch_set32_gs(dest);
723 } else {
724 patch_set32(dest);
725 }
726 ICache::invalidate_range(addr_at(0), 8);
727 } else {
728 fatal("not a call");
729 }
730 #endif
731 }
733 void NativeCall::print() {
734 tty->print_cr(PTR_FORMAT ": call " PTR_FORMAT,
735 instruction_address(), destination());
736 }
738 // Inserts a native call instruction at a given pc
739 void NativeCall::insert(address code_pos, address entry) {
740 NativeCall *call = nativeCall_at(code_pos);
741 CodeBuffer cb(call->addr_at(0), instruction_size);
742 MacroAssembler masm(&cb);
743 #define __ masm.
744 #ifndef _LP64
745 __ lui(T9, Assembler::split_high((int)entry));
746 __ addiu(T9, T9, Assembler::split_low((int)entry));
747 #else
748 __ li48(T9, (long)entry);
749 #endif
750 __ jalr ();
751 __ delayed()->nop();
752 #undef __
754 ICache::invalidate_range(call->addr_at(0), instruction_size);
755 }
757 // MT-safe patching of a call instruction.
758 // First patches first word of instruction to two jmp's that jmps to them
759 // selfs (spinlock). Then patches the last byte, and then atomicly replaces
760 // the jmp's with the first 4 byte of the new instruction.
761 void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) {
762 Unimplemented();
763 }
765 //-------------------------------------------------------------------
767 void NativeMovConstReg::verify() {
768 #ifndef _LP64
769 if ( !is_op(Assembler::lui_op) ||
770 !is_op(int_at(4), Assembler::addiu_op) )
771 fatal("not a mov reg, imm32")
772 #else
773 // li64
774 if ( is_op(Assembler::lui_op) &&
775 is_op(int_at(4), Assembler::ori_op) &&
776 is_special_op(int_at(8), Assembler::dsll_op) &&
777 is_op(int_at(12), Assembler::ori_op) &&
778 is_special_op(int_at(16), Assembler::dsll_op) &&
779 is_op(int_at(20), Assembler::ori_op) ) {
780 return;
781 }
783 //lui dst, imm16
784 //ori dst, dst, imm16
785 //dsll dst, dst, 16
786 //ori dst, dst, imm16
787 if ( is_op(Assembler::lui_op) &&
788 is_op (int_at(4), Assembler::ori_op) &&
789 is_special_op(int_at(8), Assembler::dsll_op) &&
790 is_op (int_at(12), Assembler::ori_op) ) {
791 return;
792 }
794 //ori dst, R0, imm16
795 //dsll dst, dst, 16
796 //ori dst, dst, imm16
797 //nop
798 if ( is_op(Assembler::ori_op) &&
799 is_special_op(int_at(4), Assembler::dsll_op) &&
800 is_op (int_at(8), Assembler::ori_op) &&
801 nativeInstruction_at(addr_at(12))->is_nop()) {
802 return;
803 }
805 //ori dst, R0, imm16
806 //dsll dst, dst, 16
807 //nop
808 //nop
809 if ( is_op(Assembler::ori_op) &&
810 is_special_op(int_at(4), Assembler::dsll_op) &&
811 nativeInstruction_at(addr_at(8))->is_nop() &&
812 nativeInstruction_at(addr_at(12))->is_nop()) {
813 return;
814 }
816 //daddiu dst, R0, imm16
817 //nop
818 //nop
819 //nop
820 if ( is_op(Assembler::daddiu_op) &&
821 nativeInstruction_at(addr_at(4))->is_nop() &&
822 nativeInstruction_at(addr_at(8))->is_nop() &&
823 nativeInstruction_at(addr_at(12))->is_nop() ) {
824 return;
825 }
827 //lui dst, imm16
828 //ori dst, dst, imm16
829 //nop
830 //nop
831 if ( is_op(Assembler::lui_op) &&
832 is_op (int_at(4), Assembler::ori_op) &&
833 nativeInstruction_at(addr_at(8))->is_nop() &&
834 nativeInstruction_at(addr_at(12))->is_nop() ) {
835 return;
836 }
838 //lui dst, imm16
839 //nop
840 //nop
841 //nop
842 if ( is_op(Assembler::lui_op) &&
843 nativeInstruction_at(addr_at(4))->is_nop() &&
844 nativeInstruction_at(addr_at(8))->is_nop() &&
845 nativeInstruction_at(addr_at(12))->is_nop() ) {
846 return;
847 }
849 fatal("not a mov reg, imm64/imm48");
850 #endif
851 }
853 void NativeMovConstReg::print() {
854 tty->print_cr(PTR_FORMAT ": mov reg, " INTPTR_FORMAT,
855 instruction_address(), data());
856 }
858 intptr_t NativeMovConstReg::data() const {
859 #ifndef _LP64
860 return Assembler::merge(int_at(4)&0xffff, long_at(0)&0xffff);
861 #else
862 // li64
863 if ( is_op(Assembler::lui_op) &&
864 is_op(int_at(4), Assembler::ori_op) &&
865 is_special_op(int_at(8), Assembler::dsll_op) &&
866 is_op(int_at(12), Assembler::ori_op) &&
867 is_special_op(int_at(16), Assembler::dsll_op) &&
868 is_op(int_at(20), Assembler::ori_op) ) {
870 return Assembler::merge( (intptr_t)(int_at(20) & 0xffff),
871 (intptr_t)(int_at(12) & 0xffff),
872 (intptr_t)(int_at(4) & 0xffff),
873 (intptr_t)(int_at(0) & 0xffff));
874 }
876 //lui dst, imm16
877 //ori dst, dst, imm16
878 //dsll dst, dst, 16
879 //ori dst, dst, imm16
880 if ( is_op(Assembler::lui_op) &&
881 is_op (int_at(4), Assembler::ori_op) &&
882 is_special_op(int_at(8), Assembler::dsll_op) &&
883 is_op (int_at(12), Assembler::ori_op) ) {
885 return Assembler::merge( (intptr_t)(int_at(12) & 0xffff),
886 (intptr_t)(int_at(4) & 0xffff),
887 (intptr_t)(int_at(0) & 0xffff),
888 (intptr_t)0);
889 }
891 //ori dst, R0, imm16
892 //dsll dst, dst, 16
893 //ori dst, dst, imm16
894 //nop
895 if ( is_op(Assembler::ori_op) &&
896 is_special_op(int_at(4), Assembler::dsll_op) &&
897 is_op (int_at(8), Assembler::ori_op) &&
898 nativeInstruction_at(addr_at(12))->is_nop()) {
900 return Assembler::merge( (intptr_t)(int_at(8) & 0xffff),
901 (intptr_t)(int_at(0) & 0xffff),
902 (intptr_t)0,
903 (intptr_t)0);
904 }
906 //ori dst, R0, imm16
907 //dsll dst, dst, 16
908 //nop
909 //nop
910 if ( is_op(Assembler::ori_op) &&
911 is_special_op(int_at(4), Assembler::dsll_op) &&
912 nativeInstruction_at(addr_at(8))->is_nop() &&
913 nativeInstruction_at(addr_at(12))->is_nop()) {
915 return Assembler::merge( (intptr_t)(0),
916 (intptr_t)(int_at(0) & 0xffff),
917 (intptr_t)0,
918 (intptr_t)0);
919 }
921 //daddiu dst, R0, imm16
922 //nop
923 //nop
924 //nop
925 if ( is_op(Assembler::daddiu_op) &&
926 nativeInstruction_at(addr_at(4))->is_nop() &&
927 nativeInstruction_at(addr_at(8))->is_nop() &&
928 nativeInstruction_at(addr_at(12))->is_nop() ) {
930 int sign = int_at(0) & 0x8000;
931 if (sign == 0) {
932 return Assembler::merge( (intptr_t)(int_at(0) & 0xffff),
933 (intptr_t)0,
934 (intptr_t)0,
935 (intptr_t)0);
936 } else {
937 return Assembler::merge( (intptr_t)(int_at(0) & 0xffff),
938 (intptr_t)(0xffff),
939 (intptr_t)(0xffff),
940 (intptr_t)(0xffff));
941 }
942 }
944 //lui dst, imm16
945 //ori dst, dst, imm16
946 //nop
947 //nop
948 if ( is_op(Assembler::lui_op) &&
949 is_op (int_at(4), Assembler::ori_op) &&
950 nativeInstruction_at(addr_at(8))->is_nop() &&
951 nativeInstruction_at(addr_at(12))->is_nop() ) {
953 int sign = int_at(0) & 0x8000;
954 if (sign == 0) {
955 return Assembler::merge( (intptr_t)(int_at(4) & 0xffff),
956 (intptr_t)(int_at(0) & 0xffff),
957 (intptr_t)0,
958 (intptr_t)0);
959 } else {
960 return Assembler::merge( (intptr_t)(int_at(4) & 0xffff),
961 (intptr_t)(int_at(0) & 0xffff),
962 (intptr_t)(0xffff),
963 (intptr_t)(0xffff));
964 }
965 }
967 //lui dst, imm16
968 //nop
969 //nop
970 //nop
971 if ( is_op(Assembler::lui_op) &&
972 nativeInstruction_at(addr_at(4))->is_nop() &&
973 nativeInstruction_at(addr_at(8))->is_nop() &&
974 nativeInstruction_at(addr_at(12))->is_nop() ) {
976 int sign = int_at(0) & 0x8000;
977 if (sign == 0) {
978 return Assembler::merge( (intptr_t)0,
979 (intptr_t)(int_at(0) & 0xffff),
980 (intptr_t)0,
981 (intptr_t)0);
982 } else {
983 return Assembler::merge( (intptr_t)0,
984 (intptr_t)(int_at(0) & 0xffff),
985 (intptr_t)(0xffff),
986 (intptr_t)(0xffff));
987 }
988 }
990 fatal("not a mov reg, imm64/imm48");
992 #endif
993 }
995 void NativeMovConstReg::patch_set48(intptr_t x) {
996 jlong value = (jlong) x;
997 int rt_reg = (int_at(0) & (0x1f << 16));
998 int rs_reg = rt_reg << 5;
999 int rd_reg = rt_reg >> 5;
1001 int hi = (int)(value >> 32);
1002 int lo = (int)(value & ~0);
1004 int count = 0;
1006 if (value == lo) { // 32-bit integer
1007 if (Assembler::is_simm16(value)) {
1008 //daddiu(d, R0, value);
1009 set_int_at(count << 2, (Assembler::daddiu_op << 26) | rt_reg | Assembler::split_low(value));
1010 count += 1;
1011 } else {
1012 //lui(d, split_low(value >> 16));
1013 set_int_at(count << 2, (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 16));
1014 count += 1;
1015 if (Assembler::split_low(value)) {
1016 //ori(d, d, split_low(value));
1017 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value));
1018 count += 1;
1019 }
1020 }
1021 } else if (hi == 0) { // hardware zero-extends to upper 32
1022 set_int_at(count << 2, (Assembler::ori_op << 26) | rt_reg | Assembler::split_low(julong(value) >> 16));
1023 count += 1;
1024 set_int_at(count << 2, (Assembler::dsll_op) | rt_reg | rd_reg | (16 << 6));
1025 count += 1;
1026 if (Assembler::split_low(value)) {
1027 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value));
1028 count += 1;
1029 }
1030 } else if ((value> 0) && Assembler::is_simm16(value >> 32)) {
1031 set_int_at(count << 2, (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 32));
1032 count += 1;
1033 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value >> 16));
1034 count += 1;
1035 set_int_at(count << 2, (Assembler::dsll_op) | rt_reg | rd_reg | (16 << 6));
1036 count += 1;
1037 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value));
1038 count += 1;
1039 } else {
1040 tty->print_cr("value = 0x%x", value);
1041 guarantee(false, "Not supported yet !");
1042 }
1044 while (count < 4) {
1045 set_int_at(count << 2, 0);
1046 count++;
1047 }
1048 }
1050 void NativeMovConstReg::set_data(intptr_t x) {
1051 #ifndef _LP64
1052 set_int_at(0, (int_at(0) & 0xffff0000) | (Assembler::split_high(x) & 0xffff));
1053 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low(x) & 0xffff));
1054 ICache::invalidate_range(addr_at(0), 8);
1055 #else
1056 // li64 or li48
1057 if ((!nativeInstruction_at(addr_at(12))->is_nop()) && is_special_op(int_at(16), Assembler::dsll_op) && is_op(long_at(20), Assembler::ori_op)) {
1058 set_int_at(0, (int_at(0) & 0xffff0000) | (Assembler::split_low((intptr_t)x >> 48) & 0xffff));
1059 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low((intptr_t)x >> 32) & 0xffff));
1060 set_int_at(12, (int_at(12) & 0xffff0000) | (Assembler::split_low((intptr_t)x >> 16) & 0xffff));
1061 set_int_at(20, (int_at(20) & 0xffff0000) | (Assembler::split_low((intptr_t)x) & 0xffff));
1062 } else {
1063 patch_set48(x);
1064 }
1066 ICache::invalidate_range(addr_at(0), 24);
1067 #endif
1068 }
1070 //-------------------------------------------------------------------
1072 int NativeMovRegMem::offset() const{
1073 if (is_immediate())
1074 return (short)(int_at(instruction_offset)&0xffff);
1075 else
1076 return Assembler::merge(int_at(hiword_offset)&0xffff, long_at(instruction_offset)&0xffff);
1077 }
1079 void NativeMovRegMem::set_offset(int x) {
1080 if (is_immediate()) {
1081 assert(Assembler::is_simm16(x), "just check");
1082 set_int_at(0, (int_at(0)&0xffff0000) | (x&0xffff) );
1083 if (is_64ldst()) {
1084 assert(Assembler::is_simm16(x+4), "just check");
1085 set_int_at(4, (int_at(4)&0xffff0000) | ((x+4)&0xffff) );
1086 }
1087 } else {
1088 set_int_at(0, (int_at(0) & 0xffff0000) | (Assembler::split_high(x) & 0xffff));
1089 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low(x) & 0xffff));
1090 }
1091 ICache::invalidate_range(addr_at(0), 8);
1092 }
1094 void NativeMovRegMem::verify() {
1095 int offset = 0;
1097 if ( Assembler::opcode(int_at(0)) == Assembler::lui_op ) {
1099 if ( Assembler::opcode(int_at(4)) != Assembler::ori_op ) {
1100 fatal ("not a mov [reg+offs], reg instruction");
1101 }
1103 offset += 12;
1104 }
1106 switch(Assembler::opcode(int_at(offset))) {
1107 case Assembler::lb_op:
1108 case Assembler::lbu_op:
1109 case Assembler::lh_op:
1110 case Assembler::lhu_op:
1111 case Assembler::lw_op:
1112 case Assembler::lwu_op:
1113 LP64_ONLY(case Assembler::ld_op:)
1114 case Assembler::lwc1_op:
1115 LP64_ONLY(case Assembler::ldc1_op:)
1116 case Assembler::sb_op:
1117 case Assembler::sh_op:
1118 case Assembler::sw_op:
1119 LP64_ONLY(case Assembler::sd_op:)
1120 case Assembler::swc1_op:
1121 LP64_ONLY(case Assembler::sdc1_op:)
1122 break;
1123 default:
1124 fatal ("not a mov [reg+offs], reg instruction");
1125 }
1126 }
1129 void NativeMovRegMem::print() {
1130 tty->print_cr("0x%x: mov reg, [reg + %x]", instruction_address(), offset());
1131 }
1133 bool NativeInstruction::is_sigill_zombie_not_entrant() {
1134 return uint_at(0) == NativeIllegalInstruction::instruction_code;
1135 }
1137 void NativeIllegalInstruction::insert(address code_pos) {
1138 *(juint*)code_pos = instruction_code;
1139 ICache::invalidate_range(code_pos, instruction_size);
1140 }
1142 void NativeGeneralJump::verify() {
1143 assert(((NativeInstruction *)this)->is_jump() ||
1144 ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction");
1145 }
1147 void NativeGeneralJump::patch_set48_gs(address dest) {
1148 jlong value = (jlong) dest;
1149 int rt_reg = (int_at(0) & (0x1f << 16));
1151 if (rt_reg == 0) rt_reg = 25 << 16; // r25 is T9
1153 int rs_reg = rt_reg << 5;
1154 int rd_reg = rt_reg >> 5;
1156 int hi = (int)(value >> 32);
1157 int lo = (int)(value & ~0);
1159 int count = 0;
1161 int insts[4] = {0, 0, 0, 0};
1163 if (value == lo) { // 32-bit integer
1164 if (Assembler::is_simm16(value)) {
1165 insts[count] = (Assembler::daddiu_op << 26) | rt_reg | Assembler::split_low(value);
1166 count += 1;
1167 } else {
1168 insts[count] = (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 16);
1169 count += 1;
1170 if (Assembler::split_low(value)) {
1171 insts[count] = (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value);
1172 count += 1;
1173 }
1174 }
1175 } else if (hi == 0) { // hardware zero-extends to upper 32
1176 insts[count] = (Assembler::ori_op << 26) | rt_reg | Assembler::split_low(julong(value) >> 16);
1177 count += 1;
1178 insts[count] = (Assembler::dsll_op) | rt_reg | rd_reg | (16 << 6);
1179 count += 1;
1180 if (Assembler::split_low(value)) {
1181 insts[count] = (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value);
1182 count += 1;
1183 }
1184 } else if ((value> 0) && Assembler::is_simm16(value >> 32)) {
1185 insts[count] = (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 32);
1186 count += 1;
1187 insts[count] = (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value >> 16);
1188 count += 1;
1189 insts[count] = (Assembler::dsll_op) | rt_reg | rd_reg | (16 << 6);
1190 count += 1;
1191 insts[count] = (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value);
1192 count += 1;
1193 } else {
1194 tty->print_cr("dest = 0x%x", value);
1195 guarantee(false, "Not supported yet !");
1196 }
1198 while (count < 4) {
1199 insts[count] = 0;
1200 count++;
1201 }
1203 guarantee(((long)addr_at(0) % (BytesPerWord * 2)) == 0, "must be aligned");
1204 atomic_store128_ptr func = get_atomic_store128_func();
1205 (*func)((long *)addr_at(0), 0, *(long *)&insts[0], *(long *)&insts[2]);
1207 ICache::invalidate_range(addr_at(0), 16);
1208 }
1210 void NativeGeneralJump::patch_set48(address dest) {
1211 jlong value = (jlong) dest;
1212 int rt_reg = (int_at(0) & (0x1f << 16));
1213 int rs_reg = rt_reg << 5;
1214 int rd_reg = rt_reg >> 5;
1216 int hi = (int)(value >> 32);
1217 int lo = (int)(value & ~0);
1219 int count = 0;
1221 if (value == lo) { // 32-bit integer
1222 if (Assembler::is_simm16(value)) {
1223 set_int_at(count << 2, (Assembler::daddiu_op << 26) | rt_reg | Assembler::split_low(value));
1224 count += 1;
1225 } else {
1226 set_int_at(count << 2, (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 16));
1227 count += 1;
1228 if (Assembler::split_low(value)) {
1229 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value));
1230 count += 1;
1231 }
1232 }
1233 } else if (hi == 0) { // hardware zero-extends to upper 32
1234 set_int_at(count << 2, (Assembler::ori_op << 26) | rt_reg | Assembler::split_low(julong(value) >> 16));
1235 count += 1;
1236 set_int_at(count << 2, (Assembler::dsll_op) | rt_reg | rd_reg | (16 << 6));
1237 count += 1;
1238 if (Assembler::split_low(value)) {
1239 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value));
1240 count += 1;
1241 }
1242 } else if ((value> 0) && Assembler::is_simm16(value >> 32)) {
1243 set_int_at(count << 2, (Assembler::lui_op << 26) | rt_reg | Assembler::split_low(value >> 32));
1244 count += 1;
1245 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value >> 16));
1246 count += 1;
1247 set_int_at(count << 2, (Assembler::dsll_op) | rt_reg | rd_reg | (16 << 6));
1248 count += 1;
1249 set_int_at(count << 2, (Assembler::ori_op << 26) | rs_reg | rt_reg | Assembler::split_low(value));
1250 count += 1;
1251 } else {
1252 tty->print_cr("dest = 0x%x", value);
1253 guarantee(false, "Not supported yet !");
1254 }
1256 while (count < 4) {
1257 set_int_at(count << 2, 0);
1258 count++;
1259 }
1261 ICache::invalidate_range(addr_at(0), 16);
1262 }
1264 void NativeGeneralJump::patch_on_j_only(address dst) {
1265 #ifdef _LP64
1266 long dest = ((long)dst - (((long)addr_at(4)) & 0xfffffffff0000000))>>2;
1267 #else
1268 long dest = ((long)dst - (((long)addr_at(4)) & 0xf0000000))>>2;
1269 #endif
1270 if ((dest >= 0) && (dest < (1<<26))) {
1271 jint j_inst = (Assembler::j_op << 26) | dest;
1272 set_int_at(0, j_inst);
1273 ICache::invalidate_range(addr_at(0), 4);
1274 } else {
1275 ShouldNotReachHere();
1276 }
1277 }
1280 void NativeGeneralJump::patch_on_j_gs(address dst) {
1281 #ifdef _LP64
1282 long dest = ((long)dst - (((long)addr_at(20)) & 0xfffffffff0000000))>>2;
1283 #else
1284 long dest = ((long)dst - (((long)addr_at(20)) & 0xf0000000))>>2;
1285 #endif
1286 if ((dest >= 0) && (dest < (1<<26))) {
1287 jint j_inst = (Assembler::j_op << 26) | dest;
1288 set_int_at(16, j_inst);
1289 ICache::invalidate_range(addr_at(16), 4);
1290 } else {
1291 ShouldNotReachHere();
1292 }
1293 }
1295 void NativeGeneralJump::patch_on_j(address dst) {
1296 patch_on_j_gs(dst);
1297 }
1299 void NativeGeneralJump::patch_on_jr_gs(address dst) {
1300 patch_set48_gs(dst);
1301 ICache::invalidate_range(addr_at(0), 16);
1302 }
1304 void NativeGeneralJump::patch_on_jr(address dst) {
1305 patch_set48(dst);
1306 ICache::invalidate_range(addr_at(0), 16);
1307 }
1310 void NativeGeneralJump::set_jump_destination(address dest) {
1311 OrderAccess::fence();
1313 if (is_short()) {
1314 assert(Assembler::is_simm16(dest-addr_at(4)), "change this code");
1315 set_int_at(0, (int_at(0) & 0xffff0000) | (dest - addr_at(4)) & 0xffff );
1316 ICache::invalidate_range(addr_at(0), 4);
1317 #ifdef _LP64
1318 } else if (is_b_far()) {
1319 int offset = dest - addr_at(12);
1320 set_int_at(12, (int_at(12) & 0xffff0000) | (offset >> 16));
1321 set_int_at(16, (int_at(16) & 0xffff0000) | (offset & 0xffff));
1322 #endif
1323 } else {
1324 #ifndef _LP64
1325 set_int_at(0, (int_at(0) & 0xffff0000) | (Assembler::split_high((intptr_t)dest) & 0xffff));
1326 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low((intptr_t)dest) & 0xffff));
1327 ICache::invalidate_range(addr_at(0), 8);
1328 #else
1329 if (is_op(int_at(16), Assembler::j_op)) {
1330 if (UseLEXT1) {
1331 patch_on_j_gs(dest);
1332 } else {
1333 patch_on_j(dest);
1334 }
1335 } else if (is_op(int_at(0), Assembler::j_op)) {
1336 patch_on_j_only(dest);
1337 } else if (is_special_op(int_at(16), Assembler::jr_op)) {
1338 if (UseLEXT1) {
1339 //guarantee(!os::is_MP() || (((long)addr_at(0) % 16) == 0), "destination must be aligned for GSSD");
1340 //patch_on_jr_gs(dest);
1341 patch_on_jr(dest);
1342 } else {
1343 patch_on_jr(dest);
1344 }
1345 } else {
1346 fatal("not a jump");
1347 }
1348 #endif
1349 }
1350 }
1352 void NativeGeneralJump::insert_unconditional(address code_pos, address entry) {
1353 CodeBuffer cb(code_pos, instruction_size);
1354 MacroAssembler masm(&cb);
1355 #define __ masm.
1356 #ifdef _LP64
1357 if (Assembler::is_simm16((entry - code_pos - 4) / 4)) {
1358 __ b(entry);
1359 __ delayed()->nop();
1360 } else {
1361 // Attention: We have to use a relative jump here since PC reloc-operation isn't allowed here.
1362 int offset = entry - code_pos;
1364 Label L;
1365 __ bgezal(R0, L);
1366 __ delayed()->lui(T9, (offset - 8) >> 16);
1367 __ bind(L);
1368 __ ori(T9, T9, (offset - 8) & 0xffff);
1369 __ daddu(T9, T9, RA);
1370 __ jr(T9);
1371 __ delayed()->nop();
1372 }
1374 #else
1375 __ b(entry);
1376 __ delayed()->nop();
1377 #endif
1378 #undef __
1380 ICache::invalidate_range(code_pos, instruction_size);
1381 }
1383 #ifdef _LP64
1384 bool NativeGeneralJump::is_b_far() {
1385 //
1386 // 0x000000556809f198: dadd at, ra, zero
1387 // 0x000000556809f19c: [4110001]bgezal zero, 0x000000556809f1a4
1388 //
1389 // 0x000000556809f1a0: nop
1390 // 0x000000556809f1a4: lui t9, 0xfffffffd
1391 // 0x000000556809f1a8: ori t9, t9, 0x14dc
1392 // 0x000000556809f1ac: daddu t9, t9, ra
1393 // 0x000000556809f1b0: dadd ra, at, zero
1394 // 0x000000556809f1b4: jr t9
1395 // 0x000000556809f1b8: nop
1396 // ;; ImplicitNullCheckStub slow case
1397 // 0x000000556809f1bc: lui t9, 0x55
1398 //
1399 return is_op(int_at(12), Assembler::lui_op);
1400 }
1401 #endif
1403 address NativeGeneralJump::jump_destination() {
1404 if ( is_short() ) {
1405 return addr_at(4) + Assembler::imm_off(int_at(instruction_offset)) * 4;
1406 }
1407 #ifndef _LP64
1408 return (address)Assembler::merge(int_at(4)&0xffff, long_at(instruction_offset)&0xffff);
1409 #else
1410 // Assembler::merge() is not correct in MIPS_64!
1411 //
1412 // Example:
1413 // hi16 = 0xfffd,
1414 // lo16 = f7a4,
1415 //
1416 // offset=0xfffdf7a4 (Right)
1417 // Assembler::merge = 0xfffcf7a4 (Wrong)
1418 //
1419 if ( is_b_far() ) {
1420 int hi16 = int_at(12)&0xffff;
1421 int low16 = int_at(16)&0xffff;
1422 address target = addr_at(12) + (hi16 << 16) + low16;
1423 return target;
1424 }
1426 // nop
1427 // nop
1428 // nop
1429 // nop
1430 // j target
1431 // nop
1432 if ( nativeInstruction_at(addr_at(0))->is_nop() &&
1433 nativeInstruction_at(addr_at(4))->is_nop() &&
1434 nativeInstruction_at(addr_at(8))->is_nop() &&
1435 nativeInstruction_at(addr_at(12))->is_nop() &&
1436 is_op(int_at(16), Assembler::j_op) &&
1437 nativeInstruction_at(addr_at(20))->is_nop()) {
1438 int instr_index = int_at(16) & 0x3ffffff;
1439 intptr_t target_high = ((intptr_t)addr_at(20)) & 0xfffffffff0000000;
1440 intptr_t target = target_high | (instr_index << 2);
1441 return (address)target;
1442 }
1444 // j target
1445 // nop
1446 if ( is_op(int_at(0), Assembler::j_op) &&
1447 nativeInstruction_at(addr_at(4))->is_nop()) {
1448 int instr_index = int_at(0) & 0x3ffffff;
1449 intptr_t target_high = ((intptr_t)addr_at(4)) & 0xfffffffff0000000;
1450 intptr_t target = target_high | (instr_index << 2);
1451 return (address)target;
1452 }
1454 // li64
1455 if ( is_op(Assembler::lui_op) &&
1456 is_op(int_at(4), Assembler::ori_op) &&
1457 is_special_op(int_at(8), Assembler::dsll_op) &&
1458 is_op(int_at(12), Assembler::ori_op) &&
1459 is_special_op(int_at(16), Assembler::dsll_op) &&
1460 is_op(int_at(20), Assembler::ori_op) ) {
1462 return (address)Assembler::merge( (intptr_t)(int_at(20) & 0xffff),
1463 (intptr_t)(int_at(12) & 0xffff),
1464 (intptr_t)(int_at(4) & 0xffff),
1465 (intptr_t)(int_at(0) & 0xffff));
1466 }
1468 //lui dst, imm16
1469 //ori dst, dst, imm16
1470 //dsll dst, dst, 16
1471 //ori dst, dst, imm16
1472 if ( is_op(Assembler::lui_op) &&
1473 is_op (int_at(4), Assembler::ori_op) &&
1474 is_special_op(int_at(8), Assembler::dsll_op) &&
1475 is_op (int_at(12), Assembler::ori_op) ) {
1477 return (address)Assembler::merge( (intptr_t)(int_at(12) & 0xffff),
1478 (intptr_t)(int_at(4) & 0xffff),
1479 (intptr_t)(int_at(0) & 0xffff),
1480 (intptr_t)0);
1481 }
1483 //ori dst, R0, imm16
1484 //dsll dst, dst, 16
1485 //ori dst, dst, imm16
1486 //nop
1487 if ( is_op(Assembler::ori_op) &&
1488 is_special_op(int_at(4), Assembler::dsll_op) &&
1489 is_op (int_at(8), Assembler::ori_op) &&
1490 nativeInstruction_at(addr_at(12))->is_nop()) {
1492 return (address)Assembler::merge( (intptr_t)(int_at(8) & 0xffff),
1493 (intptr_t)(int_at(0) & 0xffff),
1494 (intptr_t)0,
1495 (intptr_t)0);
1496 }
1498 //ori dst, R0, imm16
1499 //dsll dst, dst, 16
1500 //nop
1501 //nop
1502 if ( is_op(Assembler::ori_op) &&
1503 is_special_op(int_at(4), Assembler::dsll_op) &&
1504 nativeInstruction_at(addr_at(8))->is_nop() &&
1505 nativeInstruction_at(addr_at(12))->is_nop()) {
1507 return (address)Assembler::merge( (intptr_t)(0),
1508 (intptr_t)(int_at(0) & 0xffff),
1509 (intptr_t)0,
1510 (intptr_t)0);
1511 }
1513 //daddiu dst, R0, imm16
1514 //nop
1515 //nop
1516 //nop
1517 if ( is_op(Assembler::daddiu_op) &&
1518 nativeInstruction_at(addr_at(4))->is_nop() &&
1519 nativeInstruction_at(addr_at(8))->is_nop() &&
1520 nativeInstruction_at(addr_at(12))->is_nop() ) {
1522 int sign = int_at(0) & 0x8000;
1523 if (sign == 0) {
1524 return (address)Assembler::merge( (intptr_t)(int_at(0) & 0xffff),
1525 (intptr_t)0,
1526 (intptr_t)0,
1527 (intptr_t)0);
1528 } else {
1529 return (address)Assembler::merge( (intptr_t)(int_at(0) & 0xffff),
1530 (intptr_t)(0xffff),
1531 (intptr_t)(0xffff),
1532 (intptr_t)(0xffff));
1533 }
1534 }
1536 //lui dst, imm16
1537 //ori dst, dst, imm16
1538 //nop
1539 //nop
1540 if ( is_op(Assembler::lui_op) &&
1541 is_op (int_at(4), Assembler::ori_op) &&
1542 nativeInstruction_at(addr_at(8))->is_nop() &&
1543 nativeInstruction_at(addr_at(12))->is_nop() ) {
1545 int sign = int_at(0) & 0x8000;
1546 if (sign == 0) {
1547 return (address)Assembler::merge( (intptr_t)(int_at(4) & 0xffff),
1548 (intptr_t)(int_at(0) & 0xffff),
1549 (intptr_t)0,
1550 (intptr_t)0);
1551 } else {
1552 return (address)Assembler::merge( (intptr_t)(int_at(4) & 0xffff),
1553 (intptr_t)(int_at(0) & 0xffff),
1554 (intptr_t)(0xffff),
1555 (intptr_t)(0xffff));
1556 }
1557 }
1559 //lui dst, imm16
1560 //nop
1561 //nop
1562 //nop
1563 if ( is_op(Assembler::lui_op) &&
1564 nativeInstruction_at(addr_at(4))->is_nop() &&
1565 nativeInstruction_at(addr_at(8))->is_nop() &&
1566 nativeInstruction_at(addr_at(12))->is_nop() ) {
1568 int sign = int_at(0) & 0x8000;
1569 if (sign == 0) {
1570 return (address)Assembler::merge( (intptr_t)0,
1571 (intptr_t)(int_at(0) & 0xffff),
1572 (intptr_t)0,
1573 (intptr_t)0);
1574 } else {
1575 return (address)Assembler::merge( (intptr_t)0,
1576 (intptr_t)(int_at(0) & 0xffff),
1577 (intptr_t)(0xffff),
1578 (intptr_t)(0xffff));
1579 }
1580 }
1582 #if defined(COMPILER1) || defined(TIERED)
1583 // 0x92eea8: bal 0x92eeb0
1584 // 0x92eeac: lui t9,0x3
1585 // 0x92eeb0: ori t9,t9,0x8f44
1586 // 0x92eeb4: daddu t9,t9,ra
1587 // 0x92eeb8: jr t9
1588 // 0x92eebc: nop
1589 if ( is_op(int_at(4), Assembler::lui_op) &&
1590 is_op (int_at(8), Assembler::ori_op) &&
1591 is_special_op(int_at(16), Assembler::jr_op) ) {
1592 address target = addr_at(4) + Assembler::imm_off(int_at(instruction_offset)) * 4;
1594 int sign = int_at(0) & 0x8000;
1595 if (sign == 0) {
1596 return target + Assembler::merge( (intptr_t)(int_at(4) & 0xffff),
1597 (intptr_t)(int_at(0) & 0xffff),
1598 (intptr_t)0,
1599 (intptr_t)0);
1600 } else {
1601 return target + Assembler::merge( (intptr_t)(int_at(4) & 0xffff),
1602 (intptr_t)(int_at(0) & 0xffff),
1603 (intptr_t)(0xffff),
1604 (intptr_t)(0xffff));
1605 }
1606 }
1607 #endif
1609 fatal("not a jump");
1610 #endif
1611 }
1613 // MT-safe patching of a long jump instruction.
1614 // First patches first word of instruction to two jmp's that jmps to them
1615 // selfs (spinlock). Then patches the last byte, and then atomicly replaces
1616 // the jmp's with the first 4 byte of the new instruction.
1617 void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) {
1618 NativeGeneralJump* h_jump = nativeGeneralJump_at (instr_addr);
1619 assert(NativeGeneralJump::instruction_size == NativeCall::instruction_size,
1620 "note::Runtime1::patch_code uses NativeCall::instruction_size");
1622 // ensure 100% atomicity
1623 guarantee(!os::is_MP() || (((long)instr_addr % BytesPerWord) == 0), "destination must be aligned for SD");
1625 int *p = (int *)instr_addr;
1626 int jr_word = p[4];
1628 p[4] = 0x1000fffb; /* .1: --; --; --; --; b .1; nop */
1629 memcpy(instr_addr, code_buffer, NativeCall::instruction_size - 8);
1630 *(long *)(instr_addr + 16) = *(long *)(code_buffer + 16);
1631 }
1633 // Must ensure atomicity
1634 void NativeGeneralJump::patch_verified_entry(address entry, address verified_entry, address dest) {
1635 // ensure 100% atomicity.
1636 // The destination is fixed and can be cached in JavaThread.
1637 //
1638 // Destination must be aligned for GSSQ.
1639 bool is_aligned = !os::is_MP() || (((long)verified_entry % (BytesPerWord * 2)) == 0);
1641 if (UseLEXT1 && is_aligned) {
1642 int code_buffer[4];
1644 CodeBuffer cb((address)code_buffer, instruction_size);
1645 MacroAssembler masm(&cb);
1646 #define __ masm.
1647 __ ld(T9, TREG, in_bytes(JavaThread::handle_wrong_method_stub_offset()));
1648 __ jr(T9);
1649 __ delayed()->nop();
1650 __ nop();
1652 atomic_store128_ptr func = get_atomic_store128_func();
1653 (*func)((long *)verified_entry, 0, *(long *)&code_buffer[0], *(long *)&code_buffer[2]);
1654 } else {
1655 // We use an illegal instruction for marking a method as
1656 // not_entrant or zombie
1657 NativeIllegalInstruction::insert(verified_entry);
1658 }
1660 ICache::invalidate_range(verified_entry, instruction_size);
1661 }
1663 bool NativeInstruction::is_jump()
1664 {
1665 #ifndef _LP64
1666 return ((int_at(0) & NativeGeneralJump::b_mask) == NativeGeneralJump::beq_opcode) ||
1667 (is_op(int_at(0), Assembler::lui_op) &&
1668 is_op(int_at(4), Assembler::addiu_op) &&
1669 is_special_op(int_at(8), Assembler::jr_op));
1670 #else
1671 if ((int_at(0) & NativeGeneralJump::b_mask) == NativeGeneralJump::beq_opcode)
1672 return true;
1673 if (is_op(int_at(4), Assembler::lui_op)) // simplified b_far
1674 return true;
1675 if (is_op(int_at(12), Assembler::lui_op)) // original b_far
1676 return true;
1678 // nop
1679 // nop
1680 // nop
1681 // nop
1682 // j target
1683 // nop
1684 if ( is_nop() &&
1685 nativeInstruction_at(addr_at(4))->is_nop() &&
1686 nativeInstruction_at(addr_at(8))->is_nop() &&
1687 nativeInstruction_at(addr_at(12))->is_nop() &&
1688 nativeInstruction_at(addr_at(16))->is_op(Assembler::j_op) &&
1689 nativeInstruction_at(addr_at(20))->is_nop() ) {
1690 return true;
1691 }
1693 if ( nativeInstruction_at(addr_at(0))->is_op(Assembler::j_op) &&
1694 nativeInstruction_at(addr_at(4))->is_nop() ) {
1695 return true;
1696 }
1698 // lui rd, imm(63...48);
1699 // ori rd, rd, imm(47...32);
1700 // dsll rd, rd, 16;
1701 // ori rd, rd, imm(31...16);
1702 // dsll rd, rd, 16;
1703 // ori rd, rd, imm(15...0);
1704 // jr rd
1705 // nop
1706 if (is_op(int_at(0), Assembler::lui_op) &&
1707 is_op(int_at(4), Assembler::ori_op) &&
1708 is_special_op(int_at(8), Assembler::dsll_op) &&
1709 is_op(int_at(12), Assembler::ori_op) &&
1710 is_special_op(int_at(16), Assembler::dsll_op) &&
1711 is_op(int_at(20), Assembler::ori_op) &&
1712 is_special_op(int_at(24), Assembler::jr_op)) {
1713 return true;
1714 }
1716 //lui dst, imm16
1717 //ori dst, dst, imm16
1718 //dsll dst, dst, 16
1719 //ori dst, dst, imm16
1720 if (is_op(int_at(0), Assembler::lui_op) &&
1721 is_op(int_at(4), Assembler::ori_op) &&
1722 is_special_op(int_at(8), Assembler::dsll_op) &&
1723 is_op(int_at(12), Assembler::ori_op) &&
1724 is_special_op(int_at(16), Assembler::jr_op)) {
1725 return true;
1726 }
1728 //ori dst, R0, imm16
1729 //dsll dst, dst, 16
1730 //ori dst, dst, imm16
1731 //nop
1732 if ( is_op(Assembler::ori_op) &&
1733 is_special_op(int_at(4), Assembler::dsll_op) &&
1734 is_op (int_at(8), Assembler::ori_op) &&
1735 nativeInstruction_at(addr_at(12))->is_nop() &&
1736 is_special_op(int_at(16), Assembler::jr_op)) {
1737 return true;
1738 }
1740 //ori dst, R0, imm16
1741 //dsll dst, dst, 16
1742 //nop
1743 //nop
1744 if ( is_op(Assembler::ori_op) &&
1745 is_special_op(int_at(4), Assembler::dsll_op) &&
1746 nativeInstruction_at(addr_at(8))->is_nop() &&
1747 nativeInstruction_at(addr_at(12))->is_nop() &&
1748 is_special_op(int_at(16), Assembler::jr_op)) {
1749 return true;
1750 }
1752 //daddiu dst, R0, imm16
1753 //nop
1754 //nop
1755 //nop
1756 if ( is_op(Assembler::daddiu_op) &&
1757 nativeInstruction_at(addr_at(4))->is_nop() &&
1758 nativeInstruction_at(addr_at(8))->is_nop() &&
1759 nativeInstruction_at(addr_at(12))->is_nop() &&
1760 is_special_op(int_at(16), Assembler::jr_op)) {
1761 return true;
1762 }
1764 //lui dst, imm16
1765 //ori dst, dst, imm16
1766 //nop
1767 //nop
1768 if ( is_op(Assembler::lui_op) &&
1769 is_op (int_at(4), Assembler::ori_op) &&
1770 nativeInstruction_at(addr_at(8))->is_nop() &&
1771 nativeInstruction_at(addr_at(12))->is_nop() &&
1772 is_special_op(int_at(16), Assembler::jr_op)) {
1773 return true;
1774 }
1776 //lui dst, imm16
1777 //nop
1778 //nop
1779 //nop
1780 if ( is_op(Assembler::lui_op) &&
1781 nativeInstruction_at(addr_at(4))->is_nop() &&
1782 nativeInstruction_at(addr_at(8))->is_nop() &&
1783 nativeInstruction_at(addr_at(12))->is_nop() &&
1784 is_special_op(int_at(16), Assembler::jr_op)) {
1785 return true;
1786 }
1788 return false;
1789 #endif
1790 }
1792 bool NativeInstruction::is_dtrace_trap() {
1793 //return (*(int32_t*)this & 0xff) == 0xcc;
1794 Unimplemented();
1795 return false;
1796 }
1798 bool NativeInstruction::is_safepoint_poll() {
1799 #ifdef _LP64
1800 //
1801 // 390 li T2, 0x0000000000400000 #@loadConP
1802 // 394 sw [SP + #12], V1 # spill 9
1803 // 398 Safepoint @ [T2] : poll for GC @ safePoint_poll # spec.benchmarks.compress.Decompressor::decompress @ bci:224 L[0]=A6 L[1]=_ L[2]=sp + #28 L[3]=_ L[4]=V1
1804 //
1805 // 0x000000ffe5815130: lui t2, 0x40
1806 // 0x000000ffe5815134: sw v1, 0xc(sp) ; OopMap{a6=Oop off=920}
1807 // ;*goto
1808 // ; - spec.benchmarks.compress.Decompressor::decompress@224 (line 584)
1809 //
1810 // 0x000000ffe5815138: lw at, 0x0(t2) ;*goto <--- PC
1811 // ; - spec.benchmarks.compress.Decompressor::decompress@224 (line 584)
1812 //
1814 // Since there may be some spill instructions between the safePoint_poll and loadConP,
1815 // we check the safepoint instruction like the this.
1816 return is_op(Assembler::lw_op) && is_rt(AT);
1817 #else
1818 return is_op(int_at(-4), Assembler::lui_op) &&
1819 is_op(Assembler::lw_op) &&
1820 is_rt(AT);
1821 #endif
1822 }
