Tue, 02 Sep 2014 12:48:45 -0700
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
Summary: Add new C2 intrinsic for BigInteger::multiplyToLen() on x86 in 64-bit VM.
Reviewed-by: roland
1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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23 */
25 #ifndef SHARE_VM_OPTO_REGMASK_HPP
26 #define SHARE_VM_OPTO_REGMASK_HPP
28 #include "code/vmreg.hpp"
29 #include "libadt/port.hpp"
30 #include "opto/optoreg.hpp"
31 #ifdef TARGET_ARCH_MODEL_x86_32
32 # include "adfiles/adGlobals_x86_32.hpp"
33 #endif
34 #ifdef TARGET_ARCH_MODEL_x86_64
35 # include "adfiles/adGlobals_x86_64.hpp"
36 #endif
37 #ifdef TARGET_ARCH_MODEL_sparc
38 # include "adfiles/adGlobals_sparc.hpp"
39 #endif
40 #ifdef TARGET_ARCH_MODEL_zero
41 # include "adfiles/adGlobals_zero.hpp"
42 #endif
43 #ifdef TARGET_ARCH_MODEL_arm
44 # include "adfiles/adGlobals_arm.hpp"
45 #endif
46 #ifdef TARGET_ARCH_MODEL_ppc_32
47 # include "adfiles/adGlobals_ppc_32.hpp"
48 #endif
49 #ifdef TARGET_ARCH_MODEL_ppc_64
50 # include "adfiles/adGlobals_ppc_64.hpp"
51 #endif
53 // Some fun naming (textual) substitutions:
54 //
55 // RegMask::get_low_elem() ==> RegMask::find_first_elem()
56 // RegMask::Special ==> RegMask::Empty
57 // RegMask::_flags ==> RegMask::is_AllStack()
58 // RegMask::operator<<=() ==> RegMask::Insert()
59 // RegMask::operator>>=() ==> RegMask::Remove()
60 // RegMask::Union() ==> RegMask::OR
61 // RegMask::Inter() ==> RegMask::AND
62 //
63 // OptoRegister::RegName ==> OptoReg::Name
64 //
65 // OptoReg::stack0() ==> _last_Mach_Reg or ZERO in core version
66 //
67 // numregs in chaitin ==> proper degree in chaitin
69 //-------------Non-zero bit search methods used by RegMask---------------------
70 // Find lowest 1, or return 32 if empty
71 int find_lowest_bit( uint32 mask );
72 // Find highest 1, or return 32 if empty
73 int find_hihghest_bit( uint32 mask );
75 //------------------------------RegMask----------------------------------------
76 // The ADL file describes how to print the machine-specific registers, as well
77 // as any notion of register classes. We provide a register mask, which is
78 // just a collection of Register numbers.
80 // The ADLC defines 2 macros, RM_SIZE and FORALL_BODY.
81 // RM_SIZE is the size of a register mask in words.
82 // FORALL_BODY replicates a BODY macro once per word in the register mask.
83 // The usage is somewhat clumsy and limited to the regmask.[h,c]pp files.
84 // However, it means the ADLC can redefine the unroll macro and all loops
85 // over register masks will be unrolled by the correct amount.
87 class RegMask VALUE_OBJ_CLASS_SPEC {
88 union {
89 double _dummy_force_double_alignment[RM_SIZE>>1];
90 // Array of Register Mask bits. This array is large enough to cover
91 // all the machine registers and all parameters that need to be passed
92 // on the stack (stack registers) up to some interesting limit. Methods
93 // that need more parameters will NOT be compiled. On Intel, the limit
94 // is something like 90+ parameters.
95 int _A[RM_SIZE];
96 };
98 enum {
99 _WordBits = BitsPerInt,
100 _LogWordBits = LogBitsPerInt,
101 _RM_SIZE = RM_SIZE // local constant, imported, then hidden by #undef
102 };
104 public:
105 enum { CHUNK_SIZE = RM_SIZE*_WordBits };
107 // SlotsPerLong is 2, since slots are 32 bits and longs are 64 bits.
108 // Also, consider the maximum alignment size for a normally allocated
109 // value. Since we allocate register pairs but not register quads (at
110 // present), this alignment is SlotsPerLong (== 2). A normally
111 // aligned allocated register is either a single register, or a pair
112 // of adjacent registers, the lower-numbered being even.
113 // See also is_aligned_Pairs() below, and the padding added before
114 // Matcher::_new_SP to keep allocated pairs aligned properly.
115 // If we ever go to quad-word allocations, SlotsPerQuad will become
116 // the controlling alignment constraint. Note that this alignment
117 // requirement is internal to the allocator, and independent of any
118 // particular platform.
119 enum { SlotsPerLong = 2,
120 SlotsPerVecS = 1,
121 SlotsPerVecD = 2,
122 SlotsPerVecX = 4,
123 SlotsPerVecY = 8 };
125 // A constructor only used by the ADLC output. All mask fields are filled
126 // in directly. Calls to this look something like RM(1,2,3,4);
127 RegMask(
128 # define BODY(I) int a##I,
129 FORALL_BODY
130 # undef BODY
131 int dummy = 0 ) {
132 # define BODY(I) _A[I] = a##I;
133 FORALL_BODY
134 # undef BODY
135 }
137 // Handy copying constructor
138 RegMask( RegMask *rm ) {
139 # define BODY(I) _A[I] = rm->_A[I];
140 FORALL_BODY
141 # undef BODY
142 }
144 // Construct an empty mask
145 RegMask( ) { Clear(); }
147 // Construct a mask with a single bit
148 RegMask( OptoReg::Name reg ) { Clear(); Insert(reg); }
150 // Check for register being in mask
151 int Member( OptoReg::Name reg ) const {
152 assert( reg < CHUNK_SIZE, "" );
153 return _A[reg>>_LogWordBits] & (1<<(reg&(_WordBits-1)));
154 }
156 // The last bit in the register mask indicates that the mask should repeat
157 // indefinitely with ONE bits. Returns TRUE if mask is infinite or
158 // unbounded in size. Returns FALSE if mask is finite size.
159 int is_AllStack() const { return _A[RM_SIZE-1] >> (_WordBits-1); }
161 // Work around an -xO3 optimization problme in WS6U1. The old way:
162 // void set_AllStack() { _A[RM_SIZE-1] |= (1<<(_WordBits-1)); }
163 // will cause _A[RM_SIZE-1] to be clobbered, not updated when set_AllStack()
164 // follows an Insert() loop, like the one found in init_spill_mask(). Using
165 // Insert() instead works because the index into _A in computed instead of
166 // constant. See bug 4665841.
167 void set_AllStack() { Insert(OptoReg::Name(CHUNK_SIZE-1)); }
169 // Test for being a not-empty mask.
170 int is_NotEmpty( ) const {
171 int tmp = 0;
172 # define BODY(I) tmp |= _A[I];
173 FORALL_BODY
174 # undef BODY
175 return tmp;
176 }
178 // Find lowest-numbered register from mask, or BAD if mask is empty.
179 OptoReg::Name find_first_elem() const {
180 int base, bits;
181 # define BODY(I) if( (bits = _A[I]) != 0 ) base = I<<_LogWordBits; else
182 FORALL_BODY
183 # undef BODY
184 { base = OptoReg::Bad; bits = 1<<0; }
185 return OptoReg::Name(base + find_lowest_bit(bits));
186 }
187 // Get highest-numbered register from mask, or BAD if mask is empty.
188 OptoReg::Name find_last_elem() const {
189 int base, bits;
190 # define BODY(I) if( (bits = _A[RM_SIZE-1-I]) != 0 ) base = (RM_SIZE-1-I)<<_LogWordBits; else
191 FORALL_BODY
192 # undef BODY
193 { base = OptoReg::Bad; bits = 1<<0; }
194 return OptoReg::Name(base + find_hihghest_bit(bits));
195 }
197 // Find the lowest-numbered register pair in the mask. Return the
198 // HIGHEST register number in the pair, or BAD if no pairs.
199 // Assert that the mask contains only bit pairs.
200 OptoReg::Name find_first_pair() const;
202 // Clear out partial bits; leave only aligned adjacent bit pairs.
203 void clear_to_pairs();
204 // Smear out partial bits; leave only aligned adjacent bit pairs.
205 void smear_to_pairs();
206 // Verify that the mask contains only aligned adjacent bit pairs
207 void verify_pairs() const { assert( is_aligned_pairs(), "mask is not aligned, adjacent pairs" ); }
208 // Test that the mask contains only aligned adjacent bit pairs
209 bool is_aligned_pairs() const;
211 // mask is a pair of misaligned registers
212 bool is_misaligned_pair() const { return Size()==2 && !is_aligned_pairs(); }
213 // Test for single register
214 int is_bound1() const;
215 // Test for a single adjacent pair
216 int is_bound_pair() const;
217 // Test for a single adjacent set of ideal register's size.
218 int is_bound(uint ireg) const {
219 if (is_vector(ireg)) {
220 if (is_bound_set(num_registers(ireg)))
221 return true;
222 } else if (is_bound1() || is_bound_pair()) {
223 return true;
224 }
225 return false;
226 }
228 // Find the lowest-numbered register set in the mask. Return the
229 // HIGHEST register number in the set, or BAD if no sets.
230 // Assert that the mask contains only bit sets.
231 OptoReg::Name find_first_set(const int size) const;
233 // Clear out partial bits; leave only aligned adjacent bit sets of size.
234 void clear_to_sets(const int size);
235 // Smear out partial bits to aligned adjacent bit sets.
236 void smear_to_sets(const int size);
237 // Verify that the mask contains only aligned adjacent bit sets
238 void verify_sets(int size) const { assert(is_aligned_sets(size), "mask is not aligned, adjacent sets"); }
239 // Test that the mask contains only aligned adjacent bit sets
240 bool is_aligned_sets(const int size) const;
242 // mask is a set of misaligned registers
243 bool is_misaligned_set(int size) const { return (int)Size()==size && !is_aligned_sets(size);}
245 // Test for a single adjacent set
246 int is_bound_set(const int size) const;
248 static bool is_vector(uint ireg);
249 static int num_registers(uint ireg);
251 // Fast overlap test. Non-zero if any registers in common.
252 int overlap( const RegMask &rm ) const {
253 return
254 # define BODY(I) (_A[I] & rm._A[I]) |
255 FORALL_BODY
256 # undef BODY
257 0 ;
258 }
260 // Special test for register pressure based splitting
261 // UP means register only, Register plus stack, or stack only is DOWN
262 bool is_UP() const;
264 // Clear a register mask
265 void Clear( ) {
266 # define BODY(I) _A[I] = 0;
267 FORALL_BODY
268 # undef BODY
269 }
271 // Fill a register mask with 1's
272 void Set_All( ) {
273 # define BODY(I) _A[I] = -1;
274 FORALL_BODY
275 # undef BODY
276 }
278 // Insert register into mask
279 void Insert( OptoReg::Name reg ) {
280 assert( reg < CHUNK_SIZE, "" );
281 _A[reg>>_LogWordBits] |= (1<<(reg&(_WordBits-1)));
282 }
284 // Remove register from mask
285 void Remove( OptoReg::Name reg ) {
286 assert( reg < CHUNK_SIZE, "" );
287 _A[reg>>_LogWordBits] &= ~(1<<(reg&(_WordBits-1)));
288 }
290 // OR 'rm' into 'this'
291 void OR( const RegMask &rm ) {
292 # define BODY(I) this->_A[I] |= rm._A[I];
293 FORALL_BODY
294 # undef BODY
295 }
297 // AND 'rm' into 'this'
298 void AND( const RegMask &rm ) {
299 # define BODY(I) this->_A[I] &= rm._A[I];
300 FORALL_BODY
301 # undef BODY
302 }
304 // Subtract 'rm' from 'this'
305 void SUBTRACT( const RegMask &rm ) {
306 # define BODY(I) _A[I] &= ~rm._A[I];
307 FORALL_BODY
308 # undef BODY
309 }
311 // Compute size of register mask: number of bits
312 uint Size() const;
314 #ifndef PRODUCT
315 void print() const { dump(); }
316 void dump(outputStream *st = tty) const; // Print a mask
317 #endif
319 static const RegMask Empty; // Common empty mask
321 static bool can_represent(OptoReg::Name reg) {
322 // NOTE: -1 in computation reflects the usage of the last
323 // bit of the regmask as an infinite stack flag and
324 // -7 is to keep mask aligned for largest value (VecY).
325 return (int)reg < (int)(CHUNK_SIZE-1);
326 }
327 static bool can_represent_arg(OptoReg::Name reg) {
328 // NOTE: -SlotsPerVecY in computation reflects the need
329 // to keep mask aligned for largest value (VecY).
330 return (int)reg < (int)(CHUNK_SIZE-SlotsPerVecY);
331 }
332 };
334 // Do not use this constant directly in client code!
335 #undef RM_SIZE
337 #endif // SHARE_VM_OPTO_REGMASK_HPP