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src/cpu/x86/vm/assembler_x86.hpp@166d744df0de
src/cpu/x86/vm/assembler_x86.hpp
Tue, 02 Sep 2014 12:48:45 -0700
- author
- kvn
- date
- Tue, 02 Sep 2014 12:48:45 -0700
- changeset 7152
- 166d744df0de
- parent 7025
- b1bc1af04c6e
- child 7535
- 7ae4e26cb1e0
- child 7854
- e8260b6328fb
- permissions
- -rw-r--r--
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
Summary: Add new C2 intrinsic for BigInteger::multiplyToLen() on x86 in 64-bit VM.
Reviewed-by: roland
1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
28 #include "asm/register.hpp"
30 class BiasedLockingCounters;
32 // Contains all the definitions needed for x86 assembly code generation.
34 // Calling convention
35 class Argument VALUE_OBJ_CLASS_SPEC {
36 public:
37 enum {
38 #ifdef _LP64
39 #ifdef _WIN64
40 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
41 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
42 #else
43 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
44 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
45 #endif // _WIN64
46 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
47 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
48 #else
49 n_register_parameters = 0 // 0 registers used to pass arguments
50 #endif // _LP64
51 };
52 };
55 #ifdef _LP64
56 // Symbolically name the register arguments used by the c calling convention.
57 // Windows is different from linux/solaris. So much for standards...
59 #ifdef _WIN64
61 REGISTER_DECLARATION(Register, c_rarg0, rcx);
62 REGISTER_DECLARATION(Register, c_rarg1, rdx);
63 REGISTER_DECLARATION(Register, c_rarg2, r8);
64 REGISTER_DECLARATION(Register, c_rarg3, r9);
66 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
67 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
68 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
69 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
71 #else
73 REGISTER_DECLARATION(Register, c_rarg0, rdi);
74 REGISTER_DECLARATION(Register, c_rarg1, rsi);
75 REGISTER_DECLARATION(Register, c_rarg2, rdx);
76 REGISTER_DECLARATION(Register, c_rarg3, rcx);
77 REGISTER_DECLARATION(Register, c_rarg4, r8);
78 REGISTER_DECLARATION(Register, c_rarg5, r9);
80 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
81 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
82 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
83 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
84 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
85 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
86 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
87 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
89 #endif // _WIN64
91 // Symbolically name the register arguments used by the Java calling convention.
92 // We have control over the convention for java so we can do what we please.
93 // What pleases us is to offset the java calling convention so that when
94 // we call a suitable jni method the arguments are lined up and we don't
95 // have to do little shuffling. A suitable jni method is non-static and a
96 // small number of arguments (two fewer args on windows)
97 //
98 // |-------------------------------------------------------|
99 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
100 // |-------------------------------------------------------|
101 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
102 // | rdi rsi rdx rcx r8 r9 | solaris/linux
103 // |-------------------------------------------------------|
104 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
105 // |-------------------------------------------------------|
107 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
108 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
109 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
110 // Windows runs out of register args here
111 #ifdef _WIN64
112 REGISTER_DECLARATION(Register, j_rarg3, rdi);
113 REGISTER_DECLARATION(Register, j_rarg4, rsi);
114 #else
115 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
116 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
117 #endif /* _WIN64 */
118 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
120 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
121 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
122 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
123 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
124 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
125 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
126 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
127 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
129 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
130 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
132 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
133 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
135 #else
136 // rscratch1 will apear in 32bit code that is dead but of course must compile
137 // Using noreg ensures if the dead code is incorrectly live and executed it
138 // will cause an assertion failure
139 #define rscratch1 noreg
140 #define rscratch2 noreg
142 #endif // _LP64
144 // JSR 292 fixed register usages:
145 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp);
147 // Address is an abstraction used to represent a memory location
148 // using any of the amd64 addressing modes with one object.
149 //
150 // Note: A register location is represented via a Register, not
151 // via an address for efficiency & simplicity reasons.
153 class ArrayAddress;
155 class Address VALUE_OBJ_CLASS_SPEC {
156 public:
157 enum ScaleFactor {
158 no_scale = -1,
159 times_1 = 0,
160 times_2 = 1,
161 times_4 = 2,
162 times_8 = 3,
163 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
164 };
165 static ScaleFactor times(int size) {
166 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
167 if (size == 8) return times_8;
168 if (size == 4) return times_4;
169 if (size == 2) return times_2;
170 return times_1;
171 }
172 static int scale_size(ScaleFactor scale) {
173 assert(scale != no_scale, "");
174 assert(((1 << (int)times_1) == 1 &&
175 (1 << (int)times_2) == 2 &&
176 (1 << (int)times_4) == 4 &&
177 (1 << (int)times_8) == 8), "");
178 return (1 << (int)scale);
179 }
181 private:
182 Register _base;
183 Register _index;
184 ScaleFactor _scale;
185 int _disp;
186 RelocationHolder _rspec;
188 // Easily misused constructors make them private
189 // %%% can we make these go away?
190 NOT_LP64(Address(address loc, RelocationHolder spec);)
191 Address(int disp, address loc, relocInfo::relocType rtype);
192 Address(int disp, address loc, RelocationHolder spec);
194 public:
196 int disp() { return _disp; }
197 // creation
198 Address()
199 : _base(noreg),
200 _index(noreg),
201 _scale(no_scale),
202 _disp(0) {
203 }
205 // No default displacement otherwise Register can be implicitly
206 // converted to 0(Register) which is quite a different animal.
208 Address(Register base, int disp)
209 : _base(base),
210 _index(noreg),
211 _scale(no_scale),
212 _disp(disp) {
213 }
215 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
216 : _base (base),
217 _index(index),
218 _scale(scale),
219 _disp (disp) {
220 assert(!index->is_valid() == (scale == Address::no_scale),
221 "inconsistent address");
222 }
224 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
225 : _base (base),
226 _index(index.register_or_noreg()),
227 _scale(scale),
228 _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
229 if (!index.is_register()) scale = Address::no_scale;
230 assert(!_index->is_valid() == (scale == Address::no_scale),
231 "inconsistent address");
232 }
234 Address plus_disp(int disp) const {
235 Address a = (*this);
236 a._disp += disp;
237 return a;
238 }
239 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
240 Address a = (*this);
241 a._disp += disp.constant_or_zero() * scale_size(scale);
242 if (disp.is_register()) {
243 assert(!a.index()->is_valid(), "competing indexes");
244 a._index = disp.as_register();
245 a._scale = scale;
246 }
247 return a;
248 }
249 bool is_same_address(Address a) const {
250 // disregard _rspec
251 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
252 }
254 // The following two overloads are used in connection with the
255 // ByteSize type (see sizes.hpp). They simplify the use of
256 // ByteSize'd arguments in assembly code. Note that their equivalent
257 // for the optimized build are the member functions with int disp
258 // argument since ByteSize is mapped to an int type in that case.
259 //
260 // Note: DO NOT introduce similar overloaded functions for WordSize
261 // arguments as in the optimized mode, both ByteSize and WordSize
262 // are mapped to the same type and thus the compiler cannot make a
263 // distinction anymore (=> compiler errors).
265 #ifdef ASSERT
266 Address(Register base, ByteSize disp)
267 : _base(base),
268 _index(noreg),
269 _scale(no_scale),
270 _disp(in_bytes(disp)) {
271 }
273 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
274 : _base(base),
275 _index(index),
276 _scale(scale),
277 _disp(in_bytes(disp)) {
278 assert(!index->is_valid() == (scale == Address::no_scale),
279 "inconsistent address");
280 }
282 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
283 : _base (base),
284 _index(index.register_or_noreg()),
285 _scale(scale),
286 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
287 if (!index.is_register()) scale = Address::no_scale;
288 assert(!_index->is_valid() == (scale == Address::no_scale),
289 "inconsistent address");
290 }
292 #endif // ASSERT
294 // accessors
295 bool uses(Register reg) const { return _base == reg || _index == reg; }
296 Register base() const { return _base; }
297 Register index() const { return _index; }
298 ScaleFactor scale() const { return _scale; }
299 int disp() const { return _disp; }
301 // Convert the raw encoding form into the form expected by the constructor for
302 // Address. An index of 4 (rsp) corresponds to having no index, so convert
303 // that to noreg for the Address constructor.
304 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
306 static Address make_array(ArrayAddress);
308 private:
309 bool base_needs_rex() const {
310 return _base != noreg && _base->encoding() >= 8;
311 }
313 bool index_needs_rex() const {
314 return _index != noreg &&_index->encoding() >= 8;
315 }
317 relocInfo::relocType reloc() const { return _rspec.type(); }
319 friend class Assembler;
320 friend class MacroAssembler;
321 friend class LIR_Assembler; // base/index/scale/disp
322 };
324 //
325 // AddressLiteral has been split out from Address because operands of this type
326 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
327 // the few instructions that need to deal with address literals are unique and the
328 // MacroAssembler does not have to implement every instruction in the Assembler
329 // in order to search for address literals that may need special handling depending
330 // on the instruction and the platform. As small step on the way to merging i486/amd64
331 // directories.
332 //
333 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
334 friend class ArrayAddress;
335 RelocationHolder _rspec;
336 // Typically we use AddressLiterals we want to use their rval
337 // However in some situations we want the lval (effect address) of the item.
338 // We provide a special factory for making those lvals.
339 bool _is_lval;
341 // If the target is far we'll need to load the ea of this to
342 // a register to reach it. Otherwise if near we can do rip
343 // relative addressing.
345 address _target;
347 protected:
348 // creation
349 AddressLiteral()
350 : _is_lval(false),
351 _target(NULL)
352 {}
354 public:
357 AddressLiteral(address target, relocInfo::relocType rtype);
359 AddressLiteral(address target, RelocationHolder const& rspec)
360 : _rspec(rspec),
361 _is_lval(false),
362 _target(target)
363 {}
365 AddressLiteral addr() {
366 AddressLiteral ret = *this;
367 ret._is_lval = true;
368 return ret;
369 }
372 private:
374 address target() { return _target; }
375 bool is_lval() { return _is_lval; }
377 relocInfo::relocType reloc() const { return _rspec.type(); }
378 const RelocationHolder& rspec() const { return _rspec; }
380 friend class Assembler;
381 friend class MacroAssembler;
382 friend class Address;
383 friend class LIR_Assembler;
384 };
386 // Convience classes
387 class RuntimeAddress: public AddressLiteral {
389 public:
391 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
393 };
395 class ExternalAddress: public AddressLiteral {
396 private:
397 static relocInfo::relocType reloc_for_target(address target) {
398 // Sometimes ExternalAddress is used for values which aren't
399 // exactly addresses, like the card table base.
400 // external_word_type can't be used for values in the first page
401 // so just skip the reloc in that case.
402 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
403 }
405 public:
407 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
409 };
411 class InternalAddress: public AddressLiteral {
413 public:
415 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
417 };
419 // x86 can do array addressing as a single operation since disp can be an absolute
420 // address amd64 can't. We create a class that expresses the concept but does extra
421 // magic on amd64 to get the final result
423 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
424 private:
426 AddressLiteral _base;
427 Address _index;
429 public:
431 ArrayAddress() {};
432 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
433 AddressLiteral base() { return _base; }
434 Address index() { return _index; }
436 };
438 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
440 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
441 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
442 // is what you get. The Assembler is generating code into a CodeBuffer.
444 class Assembler : public AbstractAssembler {
445 friend class AbstractAssembler; // for the non-virtual hack
446 friend class LIR_Assembler; // as_Address()
447 friend class StubGenerator;
449 public:
450 enum Condition { // The x86 condition codes used for conditional jumps/moves.
451 zero = 0x4,
452 notZero = 0x5,
453 equal = 0x4,
454 notEqual = 0x5,
455 less = 0xc,
456 lessEqual = 0xe,
457 greater = 0xf,
458 greaterEqual = 0xd,
459 below = 0x2,
460 belowEqual = 0x6,
461 above = 0x7,
462 aboveEqual = 0x3,
463 overflow = 0x0,
464 noOverflow = 0x1,
465 carrySet = 0x2,
466 carryClear = 0x3,
467 negative = 0x8,
468 positive = 0x9,
469 parity = 0xa,
470 noParity = 0xb
471 };
473 enum Prefix {
474 // segment overrides
475 CS_segment = 0x2e,
476 SS_segment = 0x36,
477 DS_segment = 0x3e,
478 ES_segment = 0x26,
479 FS_segment = 0x64,
480 GS_segment = 0x65,
482 REX = 0x40,
484 REX_B = 0x41,
485 REX_X = 0x42,
486 REX_XB = 0x43,
487 REX_R = 0x44,
488 REX_RB = 0x45,
489 REX_RX = 0x46,
490 REX_RXB = 0x47,
492 REX_W = 0x48,
494 REX_WB = 0x49,
495 REX_WX = 0x4A,
496 REX_WXB = 0x4B,
497 REX_WR = 0x4C,
498 REX_WRB = 0x4D,
499 REX_WRX = 0x4E,
500 REX_WRXB = 0x4F,
502 VEX_3bytes = 0xC4,
503 VEX_2bytes = 0xC5
504 };
506 enum VexPrefix {
507 VEX_B = 0x20,
508 VEX_X = 0x40,
509 VEX_R = 0x80,
510 VEX_W = 0x80
511 };
513 enum VexSimdPrefix {
514 VEX_SIMD_NONE = 0x0,
515 VEX_SIMD_66 = 0x1,
516 VEX_SIMD_F3 = 0x2,
517 VEX_SIMD_F2 = 0x3
518 };
520 enum VexOpcode {
521 VEX_OPCODE_NONE = 0x0,
522 VEX_OPCODE_0F = 0x1,
523 VEX_OPCODE_0F_38 = 0x2,
524 VEX_OPCODE_0F_3A = 0x3
525 };
527 enum WhichOperand {
528 // input to locate_operand, and format code for relocations
529 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
530 disp32_operand = 1, // embedded 32-bit displacement or address
531 call32_operand = 2, // embedded 32-bit self-relative displacement
532 #ifndef _LP64
533 _WhichOperand_limit = 3
534 #else
535 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
536 _WhichOperand_limit = 4
537 #endif
538 };
542 // NOTE: The general philopsophy of the declarations here is that 64bit versions
543 // of instructions are freely declared without the need for wrapping them an ifdef.
544 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
545 // In the .cpp file the implementations are wrapped so that they are dropped out
546 // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
547 // to the size it was prior to merging up the 32bit and 64bit assemblers.
548 //
549 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
550 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
552 private:
555 // 64bit prefixes
556 int prefix_and_encode(int reg_enc, bool byteinst = false);
557 int prefixq_and_encode(int reg_enc);
559 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
560 int prefixq_and_encode(int dst_enc, int src_enc);
562 void prefix(Register reg);
563 void prefix(Address adr);
564 void prefixq(Address adr);
566 void prefix(Address adr, Register reg, bool byteinst = false);
567 void prefix(Address adr, XMMRegister reg);
568 void prefixq(Address adr, Register reg);
569 void prefixq(Address adr, XMMRegister reg);
571 void prefetch_prefix(Address src);
573 void rex_prefix(Address adr, XMMRegister xreg,
574 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
575 int rex_prefix_and_encode(int dst_enc, int src_enc,
576 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
578 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w,
579 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
580 bool vector256);
582 void vex_prefix(Address adr, int nds_enc, int xreg_enc,
583 VexSimdPrefix pre, VexOpcode opc,
584 bool vex_w, bool vector256);
586 void vex_prefix(XMMRegister dst, XMMRegister nds, Address src,
587 VexSimdPrefix pre, bool vector256 = false) {
588 int dst_enc = dst->encoding();
589 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
590 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector256);
591 }
593 void vex_prefix_0F38(Register dst, Register nds, Address src) {
594 bool vex_w = false;
595 bool vector256 = false;
596 vex_prefix(src, nds->encoding(), dst->encoding(),
597 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256);
598 }
600 void vex_prefix_0F38_q(Register dst, Register nds, Address src) {
601 bool vex_w = true;
602 bool vector256 = false;
603 vex_prefix(src, nds->encoding(), dst->encoding(),
604 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256);
605 }
606 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
607 VexSimdPrefix pre, VexOpcode opc,
608 bool vex_w, bool vector256);
610 int vex_prefix_0F38_and_encode(Register dst, Register nds, Register src) {
611 bool vex_w = false;
612 bool vector256 = false;
613 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
614 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256);
615 }
616 int vex_prefix_0F38_and_encode_q(Register dst, Register nds, Register src) {
617 bool vex_w = true;
618 bool vector256 = false;
619 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
620 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256);
621 }
622 int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
623 VexSimdPrefix pre, bool vector256 = false,
624 VexOpcode opc = VEX_OPCODE_0F) {
625 int src_enc = src->encoding();
626 int dst_enc = dst->encoding();
627 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
628 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector256);
629 }
631 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr,
632 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
633 bool rex_w = false, bool vector256 = false);
635 void simd_prefix(XMMRegister dst, Address src,
636 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
637 simd_prefix(dst, xnoreg, src, pre, opc);
638 }
640 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) {
641 simd_prefix(src, dst, pre);
642 }
643 void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src,
644 VexSimdPrefix pre) {
645 bool rex_w = true;
646 simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w);
647 }
649 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
650 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
651 bool rex_w = false, bool vector256 = false);
653 // Move/convert 32-bit integer value.
654 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src,
655 VexSimdPrefix pre) {
656 // It is OK to cast from Register to XMMRegister to pass argument here
657 // since only encoding is used in simd_prefix_and_encode() and number of
658 // Gen and Xmm registers are the same.
659 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre);
660 }
661 int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) {
662 return simd_prefix_and_encode(dst, xnoreg, src, pre);
663 }
664 int simd_prefix_and_encode(Register dst, XMMRegister src,
665 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
666 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc);
667 }
669 // Move/convert 64-bit integer value.
670 int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src,
671 VexSimdPrefix pre) {
672 bool rex_w = true;
673 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w);
674 }
675 int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) {
676 return simd_prefix_and_encode_q(dst, xnoreg, src, pre);
677 }
678 int simd_prefix_and_encode_q(Register dst, XMMRegister src,
679 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
680 bool rex_w = true;
681 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc, rex_w);
682 }
684 // Helper functions for groups of instructions
685 void emit_arith_b(int op1, int op2, Register dst, int imm8);
687 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
688 // Force generation of a 4 byte immediate value even if it fits into 8bit
689 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
690 void emit_arith(int op1, int op2, Register dst, Register src);
692 void emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre);
693 void emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre);
694 void emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre);
695 void emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre);
696 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
697 Address src, VexSimdPrefix pre, bool vector256);
698 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
699 XMMRegister src, VexSimdPrefix pre, bool vector256);
701 void emit_operand(Register reg,
702 Register base, Register index, Address::ScaleFactor scale,
703 int disp,
704 RelocationHolder const& rspec,
705 int rip_relative_correction = 0);
707 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
709 // operands that only take the original 32bit registers
710 void emit_operand32(Register reg, Address adr);
712 void emit_operand(XMMRegister reg,
713 Register base, Register index, Address::ScaleFactor scale,
714 int disp,
715 RelocationHolder const& rspec);
717 void emit_operand(XMMRegister reg, Address adr);
719 void emit_operand(MMXRegister reg, Address adr);
721 // workaround gcc (3.2.1-7) bug
722 void emit_operand(Address adr, MMXRegister reg);
725 // Immediate-to-memory forms
726 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
728 void emit_farith(int b1, int b2, int i);
731 protected:
732 #ifdef ASSERT
733 void check_relocation(RelocationHolder const& rspec, int format);
734 #endif
736 void emit_data(jint data, relocInfo::relocType rtype, int format);
737 void emit_data(jint data, RelocationHolder const& rspec, int format);
738 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
739 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
741 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
743 // These are all easily abused and hence protected
745 // 32BIT ONLY SECTION
746 #ifndef _LP64
747 // Make these disappear in 64bit mode since they would never be correct
748 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
749 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
751 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
752 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
754 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
755 #else
756 // 64BIT ONLY SECTION
757 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
759 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
760 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
762 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
763 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
764 #endif // _LP64
766 // These are unique in that we are ensured by the caller that the 32bit
767 // relative in these instructions will always be able to reach the potentially
768 // 64bit address described by entry. Since they can take a 64bit address they
769 // don't have the 32 suffix like the other instructions in this class.
771 void call_literal(address entry, RelocationHolder const& rspec);
772 void jmp_literal(address entry, RelocationHolder const& rspec);
774 // Avoid using directly section
775 // Instructions in this section are actually usable by anyone without danger
776 // of failure but have performance issues that are addressed my enhanced
777 // instructions which will do the proper thing base on the particular cpu.
778 // We protect them because we don't trust you...
780 // Don't use next inc() and dec() methods directly. INC & DEC instructions
781 // could cause a partial flag stall since they don't set CF flag.
782 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
783 // which call inc() & dec() or add() & sub() in accordance with
784 // the product flag UseIncDec value.
786 void decl(Register dst);
787 void decl(Address dst);
788 void decq(Register dst);
789 void decq(Address dst);
791 void incl(Register dst);
792 void incl(Address dst);
793 void incq(Register dst);
794 void incq(Address dst);
796 // New cpus require use of movsd and movss to avoid partial register stall
797 // when loading from memory. But for old Opteron use movlpd instead of movsd.
798 // The selection is done in MacroAssembler::movdbl() and movflt().
800 // Move Scalar Single-Precision Floating-Point Values
801 void movss(XMMRegister dst, Address src);
802 void movss(XMMRegister dst, XMMRegister src);
803 void movss(Address dst, XMMRegister src);
805 // Move Scalar Double-Precision Floating-Point Values
806 void movsd(XMMRegister dst, Address src);
807 void movsd(XMMRegister dst, XMMRegister src);
808 void movsd(Address dst, XMMRegister src);
809 void movlpd(XMMRegister dst, Address src);
811 // New cpus require use of movaps and movapd to avoid partial register stall
812 // when moving between registers.
813 void movaps(XMMRegister dst, XMMRegister src);
814 void movapd(XMMRegister dst, XMMRegister src);
816 // End avoid using directly
819 // Instruction prefixes
820 void prefix(Prefix p);
822 public:
824 // Creation
825 Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
827 // Decoding
828 static address locate_operand(address inst, WhichOperand which);
829 static address locate_next_instruction(address inst);
831 // Utilities
832 static bool is_polling_page_far() NOT_LP64({ return false;});
834 // Generic instructions
835 // Does 32bit or 64bit as needed for the platform. In some sense these
836 // belong in macro assembler but there is no need for both varieties to exist
838 void lea(Register dst, Address src);
840 void mov(Register dst, Register src);
842 void pusha();
843 void popa();
845 void pushf();
846 void popf();
848 void push(int32_t imm32);
850 void push(Register src);
852 void pop(Register dst);
854 // These are dummies to prevent surprise implicit conversions to Register
855 void push(void* v);
856 void pop(void* v);
858 // These do register sized moves/scans
859 void rep_mov();
860 void rep_stos();
861 void rep_stosb();
862 void repne_scan();
863 #ifdef _LP64
864 void repne_scanl();
865 #endif
867 // Vanilla instructions in lexical order
869 void adcl(Address dst, int32_t imm32);
870 void adcl(Address dst, Register src);
871 void adcl(Register dst, int32_t imm32);
872 void adcl(Register dst, Address src);
873 void adcl(Register dst, Register src);
875 void adcq(Register dst, int32_t imm32);
876 void adcq(Register dst, Address src);
877 void adcq(Register dst, Register src);
879 void addl(Address dst, int32_t imm32);
880 void addl(Address dst, Register src);
881 void addl(Register dst, int32_t imm32);
882 void addl(Register dst, Address src);
883 void addl(Register dst, Register src);
885 void addq(Address dst, int32_t imm32);
886 void addq(Address dst, Register src);
887 void addq(Register dst, int32_t imm32);
888 void addq(Register dst, Address src);
889 void addq(Register dst, Register src);
891 #ifdef _LP64
892 //Add Unsigned Integers with Carry Flag
893 void adcxq(Register dst, Register src);
895 //Add Unsigned Integers with Overflow Flag
896 void adoxq(Register dst, Register src);
897 #endif
899 void addr_nop_4();
900 void addr_nop_5();
901 void addr_nop_7();
902 void addr_nop_8();
904 // Add Scalar Double-Precision Floating-Point Values
905 void addsd(XMMRegister dst, Address src);
906 void addsd(XMMRegister dst, XMMRegister src);
908 // Add Scalar Single-Precision Floating-Point Values
909 void addss(XMMRegister dst, Address src);
910 void addss(XMMRegister dst, XMMRegister src);
912 // AES instructions
913 void aesdec(XMMRegister dst, Address src);
914 void aesdec(XMMRegister dst, XMMRegister src);
915 void aesdeclast(XMMRegister dst, Address src);
916 void aesdeclast(XMMRegister dst, XMMRegister src);
917 void aesenc(XMMRegister dst, Address src);
918 void aesenc(XMMRegister dst, XMMRegister src);
919 void aesenclast(XMMRegister dst, Address src);
920 void aesenclast(XMMRegister dst, XMMRegister src);
923 void andl(Address dst, int32_t imm32);
924 void andl(Register dst, int32_t imm32);
925 void andl(Register dst, Address src);
926 void andl(Register dst, Register src);
928 void andq(Address dst, int32_t imm32);
929 void andq(Register dst, int32_t imm32);
930 void andq(Register dst, Address src);
931 void andq(Register dst, Register src);
933 // BMI instructions
934 void andnl(Register dst, Register src1, Register src2);
935 void andnl(Register dst, Register src1, Address src2);
936 void andnq(Register dst, Register src1, Register src2);
937 void andnq(Register dst, Register src1, Address src2);
939 void blsil(Register dst, Register src);
940 void blsil(Register dst, Address src);
941 void blsiq(Register dst, Register src);
942 void blsiq(Register dst, Address src);
944 void blsmskl(Register dst, Register src);
945 void blsmskl(Register dst, Address src);
946 void blsmskq(Register dst, Register src);
947 void blsmskq(Register dst, Address src);
949 void blsrl(Register dst, Register src);
950 void blsrl(Register dst, Address src);
951 void blsrq(Register dst, Register src);
952 void blsrq(Register dst, Address src);
954 void bsfl(Register dst, Register src);
955 void bsrl(Register dst, Register src);
957 #ifdef _LP64
958 void bsfq(Register dst, Register src);
959 void bsrq(Register dst, Register src);
960 #endif
962 void bswapl(Register reg);
964 void bswapq(Register reg);
966 void call(Label& L, relocInfo::relocType rtype);
967 void call(Register reg); // push pc; pc <- reg
968 void call(Address adr); // push pc; pc <- adr
970 void cdql();
972 void cdqq();
974 void cld();
976 void clflush(Address adr);
978 void cmovl(Condition cc, Register dst, Register src);
979 void cmovl(Condition cc, Register dst, Address src);
981 void cmovq(Condition cc, Register dst, Register src);
982 void cmovq(Condition cc, Register dst, Address src);
985 void cmpb(Address dst, int imm8);
987 void cmpl(Address dst, int32_t imm32);
989 void cmpl(Register dst, int32_t imm32);
990 void cmpl(Register dst, Register src);
991 void cmpl(Register dst, Address src);
993 void cmpq(Address dst, int32_t imm32);
994 void cmpq(Address dst, Register src);
996 void cmpq(Register dst, int32_t imm32);
997 void cmpq(Register dst, Register src);
998 void cmpq(Register dst, Address src);
1000 // these are dummies used to catch attempting to convert NULL to Register
1001 void cmpl(Register dst, void* junk); // dummy
1002 void cmpq(Register dst, void* junk); // dummy
1004 void cmpw(Address dst, int imm16);
1006 void cmpxchg8 (Address adr);
1008 void cmpxchgl(Register reg, Address adr);
1010 void cmpxchgq(Register reg, Address adr);
1012 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1013 void comisd(XMMRegister dst, Address src);
1014 void comisd(XMMRegister dst, XMMRegister src);
1016 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1017 void comiss(XMMRegister dst, Address src);
1018 void comiss(XMMRegister dst, XMMRegister src);
1020 // Identify processor type and features
1021 void cpuid();
1023 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
1024 void cvtsd2ss(XMMRegister dst, XMMRegister src);
1025 void cvtsd2ss(XMMRegister dst, Address src);
1027 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
1028 void cvtsi2sdl(XMMRegister dst, Register src);
1029 void cvtsi2sdl(XMMRegister dst, Address src);
1030 void cvtsi2sdq(XMMRegister dst, Register src);
1031 void cvtsi2sdq(XMMRegister dst, Address src);
1033 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
1034 void cvtsi2ssl(XMMRegister dst, Register src);
1035 void cvtsi2ssl(XMMRegister dst, Address src);
1036 void cvtsi2ssq(XMMRegister dst, Register src);
1037 void cvtsi2ssq(XMMRegister dst, Address src);
1039 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
1040 void cvtdq2pd(XMMRegister dst, XMMRegister src);
1042 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
1043 void cvtdq2ps(XMMRegister dst, XMMRegister src);
1045 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
1046 void cvtss2sd(XMMRegister dst, XMMRegister src);
1047 void cvtss2sd(XMMRegister dst, Address src);
1049 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
1050 void cvttsd2sil(Register dst, Address src);
1051 void cvttsd2sil(Register dst, XMMRegister src);
1052 void cvttsd2siq(Register dst, XMMRegister src);
1054 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1055 void cvttss2sil(Register dst, XMMRegister src);
1056 void cvttss2siq(Register dst, XMMRegister src);
1058 // Divide Scalar Double-Precision Floating-Point Values
1059 void divsd(XMMRegister dst, Address src);
1060 void divsd(XMMRegister dst, XMMRegister src);
1062 // Divide Scalar Single-Precision Floating-Point Values
1063 void divss(XMMRegister dst, Address src);
1064 void divss(XMMRegister dst, XMMRegister src);
1066 void emms();
1068 void fabs();
1070 void fadd(int i);
1072 void fadd_d(Address src);
1073 void fadd_s(Address src);
1075 // "Alternate" versions of x87 instructions place result down in FPU
1076 // stack instead of on TOS
1078 void fadda(int i); // "alternate" fadd
1079 void faddp(int i = 1);
1081 void fchs();
1083 void fcom(int i);
1085 void fcomp(int i = 1);
1086 void fcomp_d(Address src);
1087 void fcomp_s(Address src);
1089 void fcompp();
1091 void fcos();
1093 void fdecstp();
1095 void fdiv(int i);
1096 void fdiv_d(Address src);
1097 void fdivr_s(Address src);
1098 void fdiva(int i); // "alternate" fdiv
1099 void fdivp(int i = 1);
1101 void fdivr(int i);
1102 void fdivr_d(Address src);
1103 void fdiv_s(Address src);
1105 void fdivra(int i); // "alternate" reversed fdiv
1107 void fdivrp(int i = 1);
1109 void ffree(int i = 0);
1111 void fild_d(Address adr);
1112 void fild_s(Address adr);
1114 void fincstp();
1116 void finit();
1118 void fist_s (Address adr);
1119 void fistp_d(Address adr);
1120 void fistp_s(Address adr);
1122 void fld1();
1124 void fld_d(Address adr);
1125 void fld_s(Address adr);
1126 void fld_s(int index);
1127 void fld_x(Address adr); // extended-precision (80-bit) format
1129 void fldcw(Address src);
1131 void fldenv(Address src);
1133 void fldlg2();
1135 void fldln2();
1137 void fldz();
1139 void flog();
1140 void flog10();
1142 void fmul(int i);
1144 void fmul_d(Address src);
1145 void fmul_s(Address src);
1147 void fmula(int i); // "alternate" fmul
1149 void fmulp(int i = 1);
1151 void fnsave(Address dst);
1153 void fnstcw(Address src);
1155 void fnstsw_ax();
1157 void fprem();
1158 void fprem1();
1160 void frstor(Address src);
1162 void fsin();
1164 void fsqrt();
1166 void fst_d(Address adr);
1167 void fst_s(Address adr);
1169 void fstp_d(Address adr);
1170 void fstp_d(int index);
1171 void fstp_s(Address adr);
1172 void fstp_x(Address adr); // extended-precision (80-bit) format
1174 void fsub(int i);
1175 void fsub_d(Address src);
1176 void fsub_s(Address src);
1178 void fsuba(int i); // "alternate" fsub
1180 void fsubp(int i = 1);
1182 void fsubr(int i);
1183 void fsubr_d(Address src);
1184 void fsubr_s(Address src);
1186 void fsubra(int i); // "alternate" reversed fsub
1188 void fsubrp(int i = 1);
1190 void ftan();
1192 void ftst();
1194 void fucomi(int i = 1);
1195 void fucomip(int i = 1);
1197 void fwait();
1199 void fxch(int i = 1);
1201 void fxrstor(Address src);
1203 void fxsave(Address dst);
1205 void fyl2x();
1206 void frndint();
1207 void f2xm1();
1208 void fldl2e();
1210 void hlt();
1212 void idivl(Register src);
1213 void divl(Register src); // Unsigned division
1215 #ifdef _LP64
1216 void idivq(Register src);
1217 #endif
1219 void imull(Register dst, Register src);
1220 void imull(Register dst, Register src, int value);
1221 void imull(Register dst, Address src);
1223 #ifdef _LP64
1224 void imulq(Register dst, Register src);
1225 void imulq(Register dst, Register src, int value);
1226 void imulq(Register dst, Address src);
1227 #endif
1229 // jcc is the generic conditional branch generator to run-
1230 // time routines, jcc is used for branches to labels. jcc
1231 // takes a branch opcode (cc) and a label (L) and generates
1232 // either a backward branch or a forward branch and links it
1233 // to the label fixup chain. Usage:
1234 //
1235 // Label L; // unbound label
1236 // jcc(cc, L); // forward branch to unbound label
1237 // bind(L); // bind label to the current pc
1238 // jcc(cc, L); // backward branch to bound label
1239 // bind(L); // illegal: a label may be bound only once
1240 //
1241 // Note: The same Label can be used for forward and backward branches
1242 // but it may be bound only once.
1244 void jcc(Condition cc, Label& L, bool maybe_short = true);
1246 // Conditional jump to a 8-bit offset to L.
1247 // WARNING: be very careful using this for forward jumps. If the label is
1248 // not bound within an 8-bit offset of this instruction, a run-time error
1249 // will occur.
1250 void jccb(Condition cc, Label& L);
1252 void jmp(Address entry); // pc <- entry
1254 // Label operations & relative jumps (PPUM Appendix D)
1255 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L
1257 void jmp(Register entry); // pc <- entry
1259 // Unconditional 8-bit offset jump to L.
1260 // WARNING: be very careful using this for forward jumps. If the label is
1261 // not bound within an 8-bit offset of this instruction, a run-time error
1262 // will occur.
1263 void jmpb(Label& L);
1265 void ldmxcsr( Address src );
1267 void leal(Register dst, Address src);
1269 void leaq(Register dst, Address src);
1271 void lfence();
1273 void lock();
1275 void lzcntl(Register dst, Register src);
1277 #ifdef _LP64
1278 void lzcntq(Register dst, Register src);
1279 #endif
1281 enum Membar_mask_bits {
1282 StoreStore = 1 << 3,
1283 LoadStore = 1 << 2,
1284 StoreLoad = 1 << 1,
1285 LoadLoad = 1 << 0
1286 };
1288 // Serializes memory and blows flags
1289 void membar(Membar_mask_bits order_constraint) {
1290 if (os::is_MP()) {
1291 // We only have to handle StoreLoad
1292 if (order_constraint & StoreLoad) {
1293 // All usable chips support "locked" instructions which suffice
1294 // as barriers, and are much faster than the alternative of
1295 // using cpuid instruction. We use here a locked add [esp],0.
1296 // This is conveniently otherwise a no-op except for blowing
1297 // flags.
1298 // Any change to this code may need to revisit other places in
1299 // the code where this idiom is used, in particular the
1300 // orderAccess code.
1301 lock();
1302 addl(Address(rsp, 0), 0);// Assert the lock# signal here
1303 }
1304 }
1305 }
1307 void mfence();
1309 // Moves
1311 void mov64(Register dst, int64_t imm64);
1313 void movb(Address dst, Register src);
1314 void movb(Address dst, int imm8);
1315 void movb(Register dst, Address src);
1317 void movdl(XMMRegister dst, Register src);
1318 void movdl(Register dst, XMMRegister src);
1319 void movdl(XMMRegister dst, Address src);
1320 void movdl(Address dst, XMMRegister src);
1322 // Move Double Quadword
1323 void movdq(XMMRegister dst, Register src);
1324 void movdq(Register dst, XMMRegister src);
1326 // Move Aligned Double Quadword
1327 void movdqa(XMMRegister dst, XMMRegister src);
1328 void movdqa(XMMRegister dst, Address src);
1330 // Move Unaligned Double Quadword
1331 void movdqu(Address dst, XMMRegister src);
1332 void movdqu(XMMRegister dst, Address src);
1333 void movdqu(XMMRegister dst, XMMRegister src);
1335 // Move Unaligned 256bit Vector
1336 void vmovdqu(Address dst, XMMRegister src);
1337 void vmovdqu(XMMRegister dst, Address src);
1338 void vmovdqu(XMMRegister dst, XMMRegister src);
1340 // Move lower 64bit to high 64bit in 128bit register
1341 void movlhps(XMMRegister dst, XMMRegister src);
1343 void movl(Register dst, int32_t imm32);
1344 void movl(Address dst, int32_t imm32);
1345 void movl(Register dst, Register src);
1346 void movl(Register dst, Address src);
1347 void movl(Address dst, Register src);
1349 // These dummies prevent using movl from converting a zero (like NULL) into Register
1350 // by giving the compiler two choices it can't resolve
1352 void movl(Address dst, void* junk);
1353 void movl(Register dst, void* junk);
1355 #ifdef _LP64
1356 void movq(Register dst, Register src);
1357 void movq(Register dst, Address src);
1358 void movq(Address dst, Register src);
1359 #endif
1361 void movq(Address dst, MMXRegister src );
1362 void movq(MMXRegister dst, Address src );
1364 #ifdef _LP64
1365 // These dummies prevent using movq from converting a zero (like NULL) into Register
1366 // by giving the compiler two choices it can't resolve
1368 void movq(Address dst, void* dummy);
1369 void movq(Register dst, void* dummy);
1370 #endif
1372 // Move Quadword
1373 void movq(Address dst, XMMRegister src);
1374 void movq(XMMRegister dst, Address src);
1376 void movsbl(Register dst, Address src);
1377 void movsbl(Register dst, Register src);
1379 #ifdef _LP64
1380 void movsbq(Register dst, Address src);
1381 void movsbq(Register dst, Register src);
1383 // Move signed 32bit immediate to 64bit extending sign
1384 void movslq(Address dst, int32_t imm64);
1385 void movslq(Register dst, int32_t imm64);
1387 void movslq(Register dst, Address src);
1388 void movslq(Register dst, Register src);
1389 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1390 #endif
1392 void movswl(Register dst, Address src);
1393 void movswl(Register dst, Register src);
1395 #ifdef _LP64
1396 void movswq(Register dst, Address src);
1397 void movswq(Register dst, Register src);
1398 #endif
1400 void movw(Address dst, int imm16);
1401 void movw(Register dst, Address src);
1402 void movw(Address dst, Register src);
1404 void movzbl(Register dst, Address src);
1405 void movzbl(Register dst, Register src);
1407 #ifdef _LP64
1408 void movzbq(Register dst, Address src);
1409 void movzbq(Register dst, Register src);
1410 #endif
1412 void movzwl(Register dst, Address src);
1413 void movzwl(Register dst, Register src);
1415 #ifdef _LP64
1416 void movzwq(Register dst, Address src);
1417 void movzwq(Register dst, Register src);
1418 #endif
1420 // Unsigned multiply with RAX destination register
1421 void mull(Address src);
1422 void mull(Register src);
1424 #ifdef _LP64
1425 void mulq(Address src);
1426 void mulq(Register src);
1427 void mulxq(Register dst1, Register dst2, Register src);
1428 #endif
1430 // Multiply Scalar Double-Precision Floating-Point Values
1431 void mulsd(XMMRegister dst, Address src);
1432 void mulsd(XMMRegister dst, XMMRegister src);
1434 // Multiply Scalar Single-Precision Floating-Point Values
1435 void mulss(XMMRegister dst, Address src);
1436 void mulss(XMMRegister dst, XMMRegister src);
1438 void negl(Register dst);
1440 #ifdef _LP64
1441 void negq(Register dst);
1442 #endif
1444 void nop(int i = 1);
1446 void notl(Register dst);
1448 #ifdef _LP64
1449 void notq(Register dst);
1450 #endif
1452 void orl(Address dst, int32_t imm32);
1453 void orl(Register dst, int32_t imm32);
1454 void orl(Register dst, Address src);
1455 void orl(Register dst, Register src);
1457 void orq(Address dst, int32_t imm32);
1458 void orq(Register dst, int32_t imm32);
1459 void orq(Register dst, Address src);
1460 void orq(Register dst, Register src);
1462 // Pack with unsigned saturation
1463 void packuswb(XMMRegister dst, XMMRegister src);
1464 void packuswb(XMMRegister dst, Address src);
1465 void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1467 // Pemutation of 64bit words
1468 void vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256);
1470 void pause();
1472 // SSE4.2 string instructions
1473 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1474 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1476 // SSE 4.1 extract
1477 void pextrd(Register dst, XMMRegister src, int imm8);
1478 void pextrq(Register dst, XMMRegister src, int imm8);
1480 // SSE 4.1 insert
1481 void pinsrd(XMMRegister dst, Register src, int imm8);
1482 void pinsrq(XMMRegister dst, Register src, int imm8);
1484 // SSE4.1 packed move
1485 void pmovzxbw(XMMRegister dst, XMMRegister src);
1486 void pmovzxbw(XMMRegister dst, Address src);
1488 #ifndef _LP64 // no 32bit push/pop on amd64
1489 void popl(Address dst);
1490 #endif
1492 #ifdef _LP64
1493 void popq(Address dst);
1494 #endif
1496 void popcntl(Register dst, Address src);
1497 void popcntl(Register dst, Register src);
1499 #ifdef _LP64
1500 void popcntq(Register dst, Address src);
1501 void popcntq(Register dst, Register src);
1502 #endif
1504 // Prefetches (SSE, SSE2, 3DNOW only)
1506 void prefetchnta(Address src);
1507 void prefetchr(Address src);
1508 void prefetcht0(Address src);
1509 void prefetcht1(Address src);
1510 void prefetcht2(Address src);
1511 void prefetchw(Address src);
1513 // Shuffle Bytes
1514 void pshufb(XMMRegister dst, XMMRegister src);
1515 void pshufb(XMMRegister dst, Address src);
1517 // Shuffle Packed Doublewords
1518 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1519 void pshufd(XMMRegister dst, Address src, int mode);
1521 // Shuffle Packed Low Words
1522 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1523 void pshuflw(XMMRegister dst, Address src, int mode);
1525 // Shift Right by bytes Logical DoubleQuadword Immediate
1526 void psrldq(XMMRegister dst, int shift);
1528 // Logical Compare 128bit
1529 void ptest(XMMRegister dst, XMMRegister src);
1530 void ptest(XMMRegister dst, Address src);
1531 // Logical Compare 256bit
1532 void vptest(XMMRegister dst, XMMRegister src);
1533 void vptest(XMMRegister dst, Address src);
1535 // Interleave Low Bytes
1536 void punpcklbw(XMMRegister dst, XMMRegister src);
1537 void punpcklbw(XMMRegister dst, Address src);
1539 // Interleave Low Doublewords
1540 void punpckldq(XMMRegister dst, XMMRegister src);
1541 void punpckldq(XMMRegister dst, Address src);
1543 // Interleave Low Quadwords
1544 void punpcklqdq(XMMRegister dst, XMMRegister src);
1546 #ifndef _LP64 // no 32bit push/pop on amd64
1547 void pushl(Address src);
1548 #endif
1550 void pushq(Address src);
1552 void rcll(Register dst, int imm8);
1554 void rclq(Register dst, int imm8);
1556 void rdtsc();
1558 void ret(int imm16);
1560 #ifdef _LP64
1561 void rorq(Register dst, int imm8);
1562 void rorxq(Register dst, Register src, int imm8);
1563 #endif
1565 void sahf();
1567 void sarl(Register dst, int imm8);
1568 void sarl(Register dst);
1570 void sarq(Register dst, int imm8);
1571 void sarq(Register dst);
1573 void sbbl(Address dst, int32_t imm32);
1574 void sbbl(Register dst, int32_t imm32);
1575 void sbbl(Register dst, Address src);
1576 void sbbl(Register dst, Register src);
1578 void sbbq(Address dst, int32_t imm32);
1579 void sbbq(Register dst, int32_t imm32);
1580 void sbbq(Register dst, Address src);
1581 void sbbq(Register dst, Register src);
1583 void setb(Condition cc, Register dst);
1585 void shldl(Register dst, Register src);
1587 void shll(Register dst, int imm8);
1588 void shll(Register dst);
1590 void shlq(Register dst, int imm8);
1591 void shlq(Register dst);
1593 void shrdl(Register dst, Register src);
1595 void shrl(Register dst, int imm8);
1596 void shrl(Register dst);
1598 void shrq(Register dst, int imm8);
1599 void shrq(Register dst);
1601 void smovl(); // QQQ generic?
1603 // Compute Square Root of Scalar Double-Precision Floating-Point Value
1604 void sqrtsd(XMMRegister dst, Address src);
1605 void sqrtsd(XMMRegister dst, XMMRegister src);
1607 // Compute Square Root of Scalar Single-Precision Floating-Point Value
1608 void sqrtss(XMMRegister dst, Address src);
1609 void sqrtss(XMMRegister dst, XMMRegister src);
1611 void std();
1613 void stmxcsr( Address dst );
1615 void subl(Address dst, int32_t imm32);
1616 void subl(Address dst, Register src);
1617 void subl(Register dst, int32_t imm32);
1618 void subl(Register dst, Address src);
1619 void subl(Register dst, Register src);
1621 void subq(Address dst, int32_t imm32);
1622 void subq(Address dst, Register src);
1623 void subq(Register dst, int32_t imm32);
1624 void subq(Register dst, Address src);
1625 void subq(Register dst, Register src);
1627 // Force generation of a 4 byte immediate value even if it fits into 8bit
1628 void subl_imm32(Register dst, int32_t imm32);
1629 void subq_imm32(Register dst, int32_t imm32);
1631 // Subtract Scalar Double-Precision Floating-Point Values
1632 void subsd(XMMRegister dst, Address src);
1633 void subsd(XMMRegister dst, XMMRegister src);
1635 // Subtract Scalar Single-Precision Floating-Point Values
1636 void subss(XMMRegister dst, Address src);
1637 void subss(XMMRegister dst, XMMRegister src);
1639 void testb(Register dst, int imm8);
1641 void testl(Register dst, int32_t imm32);
1642 void testl(Register dst, Register src);
1643 void testl(Register dst, Address src);
1645 void testq(Register dst, int32_t imm32);
1646 void testq(Register dst, Register src);
1648 // BMI - count trailing zeros
1649 void tzcntl(Register dst, Register src);
1650 void tzcntq(Register dst, Register src);
1652 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1653 void ucomisd(XMMRegister dst, Address src);
1654 void ucomisd(XMMRegister dst, XMMRegister src);
1656 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1657 void ucomiss(XMMRegister dst, Address src);
1658 void ucomiss(XMMRegister dst, XMMRegister src);
1660 void xabort(int8_t imm8);
1662 void xaddl(Address dst, Register src);
1664 void xaddq(Address dst, Register src);
1666 void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
1668 void xchgl(Register reg, Address adr);
1669 void xchgl(Register dst, Register src);
1671 void xchgq(Register reg, Address adr);
1672 void xchgq(Register dst, Register src);
1674 void xend();
1676 // Get Value of Extended Control Register
1677 void xgetbv();
1679 void xorl(Register dst, int32_t imm32);
1680 void xorl(Register dst, Address src);
1681 void xorl(Register dst, Register src);
1683 void xorq(Register dst, Address src);
1684 void xorq(Register dst, Register src);
1686 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1688 // AVX 3-operands scalar instructions (encoded with VEX prefix)
1690 void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1691 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1692 void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1693 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1694 void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1695 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1696 void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1697 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1698 void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1699 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1700 void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1701 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1702 void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1703 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1704 void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1705 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1708 //====================VECTOR ARITHMETIC=====================================
1710 // Add Packed Floating-Point Values
1711 void addpd(XMMRegister dst, XMMRegister src);
1712 void addps(XMMRegister dst, XMMRegister src);
1713 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1714 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1715 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1716 void vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1718 // Subtract Packed Floating-Point Values
1719 void subpd(XMMRegister dst, XMMRegister src);
1720 void subps(XMMRegister dst, XMMRegister src);
1721 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1722 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1723 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1724 void vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1726 // Multiply Packed Floating-Point Values
1727 void mulpd(XMMRegister dst, XMMRegister src);
1728 void mulps(XMMRegister dst, XMMRegister src);
1729 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1730 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1731 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1732 void vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1734 // Divide Packed Floating-Point Values
1735 void divpd(XMMRegister dst, XMMRegister src);
1736 void divps(XMMRegister dst, XMMRegister src);
1737 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1738 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1739 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1740 void vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1742 // Bitwise Logical AND of Packed Floating-Point Values
1743 void andpd(XMMRegister dst, XMMRegister src);
1744 void andps(XMMRegister dst, XMMRegister src);
1745 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1746 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1747 void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1748 void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1750 // Bitwise Logical XOR of Packed Floating-Point Values
1751 void xorpd(XMMRegister dst, XMMRegister src);
1752 void xorps(XMMRegister dst, XMMRegister src);
1753 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1754 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1755 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1756 void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1758 // Add packed integers
1759 void paddb(XMMRegister dst, XMMRegister src);
1760 void paddw(XMMRegister dst, XMMRegister src);
1761 void paddd(XMMRegister dst, XMMRegister src);
1762 void paddq(XMMRegister dst, XMMRegister src);
1763 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1764 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1765 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1766 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1767 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1768 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1769 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1770 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1772 // Sub packed integers
1773 void psubb(XMMRegister dst, XMMRegister src);
1774 void psubw(XMMRegister dst, XMMRegister src);
1775 void psubd(XMMRegister dst, XMMRegister src);
1776 void psubq(XMMRegister dst, XMMRegister src);
1777 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1778 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1779 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1780 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1781 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1782 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1783 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1784 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1786 // Multiply packed integers (only shorts and ints)
1787 void pmullw(XMMRegister dst, XMMRegister src);
1788 void pmulld(XMMRegister dst, XMMRegister src);
1789 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1790 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1791 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1792 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1794 // Shift left packed integers
1795 void psllw(XMMRegister dst, int shift);
1796 void pslld(XMMRegister dst, int shift);
1797 void psllq(XMMRegister dst, int shift);
1798 void psllw(XMMRegister dst, XMMRegister shift);
1799 void pslld(XMMRegister dst, XMMRegister shift);
1800 void psllq(XMMRegister dst, XMMRegister shift);
1801 void vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1802 void vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1803 void vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1804 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1805 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1806 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1808 // Logical shift right packed integers
1809 void psrlw(XMMRegister dst, int shift);
1810 void psrld(XMMRegister dst, int shift);
1811 void psrlq(XMMRegister dst, int shift);
1812 void psrlw(XMMRegister dst, XMMRegister shift);
1813 void psrld(XMMRegister dst, XMMRegister shift);
1814 void psrlq(XMMRegister dst, XMMRegister shift);
1815 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1816 void vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1817 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1818 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1819 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1820 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1822 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
1823 void psraw(XMMRegister dst, int shift);
1824 void psrad(XMMRegister dst, int shift);
1825 void psraw(XMMRegister dst, XMMRegister shift);
1826 void psrad(XMMRegister dst, XMMRegister shift);
1827 void vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1828 void vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1829 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1830 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1832 // And packed integers
1833 void pand(XMMRegister dst, XMMRegister src);
1834 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1835 void vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1837 // Or packed integers
1838 void por(XMMRegister dst, XMMRegister src);
1839 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1840 void vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1842 // Xor packed integers
1843 void pxor(XMMRegister dst, XMMRegister src);
1844 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1845 void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1847 // Copy low 128bit into high 128bit of YMM registers.
1848 void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
1849 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
1851 // Load/store high 128bit of YMM registers which does not destroy other half.
1852 void vinsertf128h(XMMRegister dst, Address src);
1853 void vinserti128h(XMMRegister dst, Address src);
1854 void vextractf128h(Address dst, XMMRegister src);
1855 void vextracti128h(Address dst, XMMRegister src);
1857 // duplicate 4-bytes integer data from src into 8 locations in dest
1858 void vpbroadcastd(XMMRegister dst, XMMRegister src);
1860 // Carry-Less Multiplication Quadword
1861 void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
1862 void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
1864 // AVX instruction which is used to clear upper 128 bits of YMM registers and
1865 // to avoid transaction penalty between AVX and SSE states. There is no
1866 // penalty if legacy SSE instructions are encoded using VEX prefix because
1867 // they always clear upper 128 bits. It should be used before calling
1868 // runtime code and native libraries.
1869 void vzeroupper();
1871 protected:
1872 // Next instructions require address alignment 16 bytes SSE mode.
1873 // They should be called only from corresponding MacroAssembler instructions.
1874 void andpd(XMMRegister dst, Address src);
1875 void andps(XMMRegister dst, Address src);
1876 void xorpd(XMMRegister dst, Address src);
1877 void xorps(XMMRegister dst, Address src);
1879 };
1881 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP
