Mon, 23 Oct 2017 17:07:19 +0800
[G1] Initial porting of MacroAssembler::g1_write_barrier_{pre/post}
1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2017, Loongson Technology. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #include "precompiled.hpp"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "asm/macroAssembler.inline.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "gc_interface/collectedHeap.inline.hpp"
32 #include "interpreter/interpreter.hpp"
33 #include "memory/cardTableModRefBS.hpp"
34 #include "memory/resourceArea.hpp"
35 #include "memory/universe.hpp"
36 #include "prims/methodHandles.hpp"
37 #include "runtime/biasedLocking.hpp"
38 #include "runtime/interfaceSupport.hpp"
39 #include "runtime/objectMonitor.hpp"
40 #include "runtime/os.hpp"
41 #include "runtime/sharedRuntime.hpp"
42 #include "runtime/stubRoutines.hpp"
43 #include "utilities/macros.hpp"
44 #if INCLUDE_ALL_GCS
45 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
46 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
47 #include "gc_implementation/g1/heapRegion.hpp"
48 #endif // INCLUDE_ALL_GCS
50 // Implementation of MacroAssembler
52 intptr_t MacroAssembler::i[32] = {0};
53 float MacroAssembler::f[32] = {0.0};
55 void MacroAssembler::print(outputStream *s) {
56 unsigned int k;
57 for(k=0; k<sizeof(i)/sizeof(i[0]); k++) {
58 s->print_cr("i%d = 0x%.16lx", k, i[k]);
59 }
60 s->cr();
62 for(k=0; k<sizeof(f)/sizeof(f[0]); k++) {
63 s->print_cr("f%d = %f", k, f[k]);
64 }
65 s->cr();
66 }
68 int MacroAssembler::i_offset(unsigned int k) { return (intptr_t)&((MacroAssembler*)0)->i[k]; }
69 int MacroAssembler::f_offset(unsigned int k) { return (intptr_t)&((MacroAssembler*)0)->f[k]; }
71 void MacroAssembler::save_registers(MacroAssembler *masm) {
72 #define __ masm->
73 for(int k=0; k<32; k++) {
74 __ sw (as_Register(k), A0, i_offset(k));
75 }
77 for(int k=0; k<32; k++) {
78 __ swc1 (as_FloatRegister(k), A0, f_offset(k));
79 }
80 #undef __
81 }
83 void MacroAssembler::restore_registers(MacroAssembler *masm) {
84 #define __ masm->
85 for(int k=0; k<32; k++) {
86 __ lw (as_Register(k), A0, i_offset(k));
87 }
89 for(int k=0; k<32; k++) {
90 __ lwc1 (as_FloatRegister(k), A0, f_offset(k));
91 }
92 #undef __
93 }
96 void MacroAssembler::pd_patch_instruction(address branch, address target) {
97 jint& stub_inst = *(jint*) branch;
99 /* *
100 move(AT, RA); // dadd
101 emit_long(insn_ORRI(regimm_op, 0, bgezal_op, 1));
102 nop();
103 lui(T9, 0); // to be patched
104 ori(T9, 0);
105 daddu(T9, T9, RA);
106 move(RA, AT);
107 jr(T9);
108 */
109 if(special(stub_inst) == dadd_op) {
110 jint *pc = (jint *)branch;
112 assert(opcode(pc[3]) == lui_op
113 && opcode(pc[4]) == ori_op
114 && special(pc[5]) == daddu_op, "Not a branch label patch");
115 if(!(opcode(pc[3]) == lui_op
116 && opcode(pc[4]) == ori_op
117 && special(pc[5]) == daddu_op)) { tty->print_cr("Not a branch label patch"); }
119 int offset = target - branch;
120 if (!is_simm16(offset))
121 {
122 pc[3] = (pc[3] & 0xffff0000) | high16(offset - 12);
123 pc[4] = (pc[4] & 0xffff0000) | low16(offset - 12);
124 }
125 else
126 {
127 /* revert to "beq + nop" */
128 CodeBuffer cb(branch, 4 * 10);
129 MacroAssembler masm(&cb);
130 #define __ masm.
131 __ b(target);
132 __ nop();
133 __ nop();
134 __ nop();
135 __ nop();
136 __ nop();
137 __ nop();
138 __ nop();
139 }
140 return;
141 }
143 #ifndef PRODUCT
144 if (!is_simm16((target - branch - 4) >> 2))
145 {
146 tty->print_cr("Illegal patching: target=0x%lx", target);
147 int *p = (int *)branch;
148 for (int i = -10; i < 10; i++)
149 {
150 tty->print("0x%lx, ", p[i]);
151 }
152 tty->print_cr("");
153 }
154 #endif
156 stub_inst = patched_branch(target - branch, stub_inst, 0);
157 }
159 static inline address first_cache_address() {
160 return CodeCache::low_bound() + sizeof(HeapBlock::Header);
161 }
163 static inline address last_cache_address() {
164 return CodeCache::high_bound() - Assembler::InstructionSize;
165 }
167 int MacroAssembler::call_size(address target, bool far, bool patchable) {
168 if (patchable) return 6 << Assembler::LogInstructionSize;
169 if (!far) return 2 << Assembler::LogInstructionSize; // jal + nop
170 return (insts_for_set64((jlong)target) + 2) << Assembler::LogInstructionSize;
171 }
173 // Can we reach target using jal/j from anywhere
174 // in the code cache (because code can be relocated)?
175 bool MacroAssembler::reachable_from_cache(address target) {
176 address cl = first_cache_address();
177 address ch = last_cache_address();
179 return fit_in_jal(target, cl) && fit_in_jal(target, ch);
180 }
182 void MacroAssembler::general_jump(address target) {
183 if (reachable_from_cache(target)) {
184 j(target);
185 nop();
186 } else {
187 set64(T9, (long)target);
188 jr(T9);
189 nop();
190 }
191 }
193 int MacroAssembler::insts_for_general_jump(address target) {
194 if (reachable_from_cache(target)) {
195 //j(target);
196 //nop();
197 return 2;
198 } else {
199 //set64(T9, (long)target);
200 //jr(T9);
201 //nop();
202 return insts_for_set64((jlong)target) + 2;
203 }
204 }
206 void MacroAssembler::patchable_jump(address target) {
207 if (reachable_from_cache(target)) {
208 nop();
209 nop();
210 nop();
211 nop();
212 j(target);
213 nop();
214 } else {
215 patchable_set48(T9, (long)target);
216 jr(T9);
217 nop();
218 }
219 }
221 int MacroAssembler::insts_for_patchable_jump(address target) {
222 return 6;
223 }
225 void MacroAssembler::general_call(address target) {
226 if (reachable_from_cache(target)) {
227 jal(target);
228 nop();
229 } else {
230 set64(T9, (long)target);
231 jalr(T9);
232 nop();
233 }
234 }
236 int MacroAssembler::insts_for_general_call(address target) {
237 if (reachable_from_cache(target)) {
238 //jal(target);
239 //nop();
240 return 2;
241 } else {
242 //set64(T9, (long)target);
243 //jalr(T9);
244 //nop();
245 return insts_for_set64((jlong)target) + 2;
246 }
247 }
249 void MacroAssembler::patchable_call(address target) {
250 if (reachable_from_cache(target)) {
251 nop();
252 nop();
253 nop();
254 nop();
255 jal(target);
256 nop();
257 } else {
258 patchable_set48(T9, (long)target);
259 jalr(T9);
260 nop();
261 }
262 }
264 int MacroAssembler::insts_for_patchable_call(address target) {
265 return 6;
266 }
268 void MacroAssembler::beq_far(Register rs, Register rt, address entry)
269 {
270 u_char * cur_pc = pc();
272 /* Jin: Near/Far jump */
273 if(is_simm16((entry - pc() - 4) / 4))
274 {
275 Assembler::beq(rs, rt, offset(entry));
276 }
277 else
278 {
279 Label not_jump;
280 bne(rs, rt, not_jump);
281 delayed()->nop();
283 b_far(entry);
284 delayed()->nop();
286 bind(not_jump);
287 has_delay_slot();
288 }
289 }
291 void MacroAssembler::beq_far(Register rs, Register rt, Label& L)
292 {
293 if (L.is_bound()) {
294 beq_far(rs, rt, target(L));
295 } else {
296 u_char * cur_pc = pc();
297 Label not_jump;
298 bne(rs, rt, not_jump);
299 delayed()->nop();
301 b_far(L);
302 delayed()->nop();
304 bind(not_jump);
305 has_delay_slot();
306 }
307 }
309 void MacroAssembler::bne_far(Register rs, Register rt, address entry)
310 {
311 u_char * cur_pc = pc();
313 /* Jin: Near/Far jump */
314 if(is_simm16((entry - pc() - 4) / 4))
315 {
316 Assembler::bne(rs, rt, offset(entry));
317 }
318 else
319 {
320 Label not_jump;
321 beq(rs, rt, not_jump);
322 delayed()->nop();
324 b_far(entry);
325 delayed()->nop();
327 bind(not_jump);
328 has_delay_slot();
329 }
330 }
332 void MacroAssembler::bne_far(Register rs, Register rt, Label& L)
333 {
334 if (L.is_bound()) {
335 bne_far(rs, rt, target(L));
336 } else {
337 u_char * cur_pc = pc();
338 Label not_jump;
339 beq(rs, rt, not_jump);
340 delayed()->nop();
342 b_far(L);
343 delayed()->nop();
345 bind(not_jump);
346 has_delay_slot();
347 }
348 }
350 void MacroAssembler::b_far(Label& L)
351 {
352 if (L.is_bound()) {
353 b_far(target(L));
354 } else {
355 volatile address dest = target(L);
356 /*
357 MacroAssembler::pd_patch_instruction branch=55651ed514, target=55651ef6d8
358 0x00000055651ed514: dadd at, ra, zero
359 0x00000055651ed518: [4110001]bgezal zero, 0x00000055651ed520
361 0x00000055651ed51c: sll zero, zero, 0
362 0x00000055651ed520: lui t9, 0x0
363 0x00000055651ed524: ori t9, t9, 0x21b8
364 0x00000055651ed528: daddu t9, t9, ra
365 0x00000055651ed52c: dadd ra, at, zero
366 0x00000055651ed530: jr t9
367 0x00000055651ed534: sll zero, zero, 0
368 */
369 move(AT, RA);
370 emit_long(insn_ORRI(regimm_op, 0, bgezal_op, 1));
371 nop();
372 lui(T9, 0); // to be patched
373 ori(T9, T9, 0);
374 daddu(T9, T9, RA);
375 move(RA, AT);
376 jr(T9);
377 }
378 }
380 void MacroAssembler::b_far(address entry)
381 {
382 u_char * cur_pc = pc();
384 /* Jin: Near/Far jump */
385 if(is_simm16((entry - pc() - 4) / 4))
386 {
387 b(offset(entry));
388 }
389 else
390 {
391 /* address must be bounded */
392 move(AT, RA);
393 emit_long(insn_ORRI(regimm_op, 0, bgezal_op, 1));
394 nop();
395 li32(T9, entry - pc());
396 daddu(T9, T9, RA);
397 move(RA, AT);
398 jr(T9);
399 }
400 }
402 void MacroAssembler::ld_ptr(Register rt, Register offset, Register base) {
403 addu_long(AT, base, offset);
404 ld_ptr(rt, 0, AT);
405 }
407 void MacroAssembler::st_ptr(Register rt, Register offset, Register base) {
408 addu_long(AT, base, offset);
409 st_ptr(rt, 0, AT);
410 }
412 void MacroAssembler::ld_long(Register rt, Register offset, Register base) {
413 addu_long(AT, base, offset);
414 ld_long(rt, 0, AT);
415 }
417 void MacroAssembler::st_long(Register rt, Register offset, Register base) {
418 addu_long(AT, base, offset);
419 st_long(rt, 0, AT);
420 }
422 Address MacroAssembler::as_Address(AddressLiteral adr) {
423 return Address(adr.target(), adr.rspec());
424 }
426 Address MacroAssembler::as_Address(ArrayAddress adr) {
427 return Address::make_array(adr);
428 }
430 // tmp_reg1 and tmp_reg2 should be saved outside of atomic_inc32 (caller saved).
431 void MacroAssembler::atomic_inc32(address counter_addr, int inc, Register tmp_reg1, Register tmp_reg2) {
432 Label again;
434 li(tmp_reg1, counter_addr);
435 bind(again);
436 if(!Use3A2000) sync();
437 ll(tmp_reg2, tmp_reg1, 0);
438 addi(tmp_reg2, tmp_reg2, inc);
439 sc(tmp_reg2, tmp_reg1, 0);
440 beq(tmp_reg2, R0, again);
441 delayed()->nop();
442 }
444 int MacroAssembler::biased_locking_enter(Register lock_reg,
445 Register obj_reg,
446 Register swap_reg,
447 Register tmp_reg,
448 bool swap_reg_contains_mark,
449 Label& done,
450 Label* slow_case,
451 BiasedLockingCounters* counters) {
452 assert(UseBiasedLocking, "why call this otherwise?");
453 bool need_tmp_reg = false;
454 if (tmp_reg == noreg) {
455 need_tmp_reg = true;
456 tmp_reg = T9;
457 }
458 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, AT);
459 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
460 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
461 Address saved_mark_addr(lock_reg, 0);
463 // Biased locking
464 // See whether the lock is currently biased toward our thread and
465 // whether the epoch is still valid
466 // Note that the runtime guarantees sufficient alignment of JavaThread
467 // pointers to allow age to be placed into low bits
468 // First check to see whether biasing is even enabled for this object
469 Label cas_label;
470 int null_check_offset = -1;
471 if (!swap_reg_contains_mark) {
472 null_check_offset = offset();
473 ld_ptr(swap_reg, mark_addr);
474 }
476 if (need_tmp_reg) {
477 push(tmp_reg);
478 }
479 move(tmp_reg, swap_reg);
480 andi(tmp_reg, tmp_reg, markOopDesc::biased_lock_mask_in_place);
481 #ifdef _LP64
482 daddi(AT, R0, markOopDesc::biased_lock_pattern);
483 dsub(AT, AT, tmp_reg);
484 #else
485 addi(AT, R0, markOopDesc::biased_lock_pattern);
486 sub(AT, AT, tmp_reg);
487 #endif
488 if (need_tmp_reg) {
489 pop(tmp_reg);
490 }
492 bne(AT, R0, cas_label);
493 delayed()->nop();
496 // The bias pattern is present in the object's header. Need to check
497 // whether the bias owner and the epoch are both still current.
498 // Note that because there is no current thread register on MIPS we
499 // need to store off the mark word we read out of the object to
500 // avoid reloading it and needing to recheck invariants below. This
501 // store is unfortunate but it makes the overall code shorter and
502 // simpler.
503 st_ptr(swap_reg, saved_mark_addr);
504 if (need_tmp_reg) {
505 push(tmp_reg);
506 }
507 if (swap_reg_contains_mark) {
508 null_check_offset = offset();
509 }
510 load_prototype_header(tmp_reg, obj_reg);
511 xorr(tmp_reg, tmp_reg, swap_reg);
512 get_thread(swap_reg);
513 xorr(swap_reg, swap_reg, tmp_reg);
515 move(AT, ~((int) markOopDesc::age_mask_in_place));
516 andr(swap_reg, swap_reg, AT);
518 if (PrintBiasedLockingStatistics) {
519 Label L;
520 bne(swap_reg, R0, L);
521 delayed()->nop();
522 push(tmp_reg);
523 push(A0);
524 atomic_inc32((address)BiasedLocking::biased_lock_entry_count_addr(), 1, A0, tmp_reg);
525 pop(A0);
526 pop(tmp_reg);
527 bind(L);
528 }
529 if (need_tmp_reg) {
530 pop(tmp_reg);
531 }
532 beq(swap_reg, R0, done);
533 delayed()->nop();
534 Label try_revoke_bias;
535 Label try_rebias;
537 // At this point we know that the header has the bias pattern and
538 // that we are not the bias owner in the current epoch. We need to
539 // figure out more details about the state of the header in order to
540 // know what operations can be legally performed on the object's
541 // header.
543 // If the low three bits in the xor result aren't clear, that means
544 // the prototype header is no longer biased and we have to revoke
545 // the bias on this object.
547 move(AT, markOopDesc::biased_lock_mask_in_place);
548 andr(AT, swap_reg, AT);
549 bne(AT, R0, try_revoke_bias);
550 delayed()->nop();
551 // Biasing is still enabled for this data type. See whether the
552 // epoch of the current bias is still valid, meaning that the epoch
553 // bits of the mark word are equal to the epoch bits of the
554 // prototype header. (Note that the prototype header's epoch bits
555 // only change at a safepoint.) If not, attempt to rebias the object
556 // toward the current thread. Note that we must be absolutely sure
557 // that the current epoch is invalid in order to do this because
558 // otherwise the manipulations it performs on the mark word are
559 // illegal.
561 move(AT, markOopDesc::epoch_mask_in_place);
562 andr(AT,swap_reg, AT);
563 bne(AT, R0, try_rebias);
564 delayed()->nop();
565 // The epoch of the current bias is still valid but we know nothing
566 // about the owner; it might be set or it might be clear. Try to
567 // acquire the bias of the object using an atomic operation. If this
568 // fails we will go in to the runtime to revoke the object's bias.
569 // Note that we first construct the presumed unbiased header so we
570 // don't accidentally blow away another thread's valid bias.
572 ld_ptr(swap_reg, saved_mark_addr);
574 move(AT, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
575 andr(swap_reg, swap_reg, AT);
577 if (need_tmp_reg) {
578 push(tmp_reg);
579 }
580 get_thread(tmp_reg);
581 orr(tmp_reg, tmp_reg, swap_reg);
582 //if (os::is_MP()) {
583 // sync();
584 //}
585 cmpxchg(tmp_reg, Address(obj_reg, 0), swap_reg);
586 if (need_tmp_reg) {
587 pop(tmp_reg);
588 }
589 // If the biasing toward our thread failed, this means that
590 // another thread succeeded in biasing it toward itself and we
591 // need to revoke that bias. The revocation will occur in the
592 // interpreter runtime in the slow case.
593 if (PrintBiasedLockingStatistics) {
594 Label L;
595 bne(AT, R0, L);
596 delayed()->nop();
597 push(tmp_reg);
598 push(A0);
599 atomic_inc32((address)BiasedLocking::anonymously_biased_lock_entry_count_addr(), 1, A0, tmp_reg);
600 pop(A0);
601 pop(tmp_reg);
602 bind(L);
603 }
604 if (slow_case != NULL) {
605 beq_far(AT, R0, *slow_case);
606 delayed()->nop();
607 }
608 b(done);
609 delayed()->nop();
611 bind(try_rebias);
612 // At this point we know the epoch has expired, meaning that the
613 // current "bias owner", if any, is actually invalid. Under these
614 // circumstances _only_, we are allowed to use the current header's
615 // value as the comparison value when doing the cas to acquire the
616 // bias in the current epoch. In other words, we allow transfer of
617 // the bias from one thread to another directly in this situation.
618 //
619 // FIXME: due to a lack of registers we currently blow away the age
620 // bits in this situation. Should attempt to preserve them.
621 if (need_tmp_reg) {
622 push(tmp_reg);
623 }
624 load_prototype_header(tmp_reg, obj_reg);
625 get_thread(swap_reg);
626 orr(tmp_reg, tmp_reg, swap_reg);
627 ld_ptr(swap_reg, saved_mark_addr);
629 //if (os::is_MP()) {
630 // sync();
631 //}
632 cmpxchg(tmp_reg, Address(obj_reg, 0), swap_reg);
633 if (need_tmp_reg) {
634 pop(tmp_reg);
635 }
636 // If the biasing toward our thread failed, then another thread
637 // succeeded in biasing it toward itself and we need to revoke that
638 // bias. The revocation will occur in the runtime in the slow case.
639 if (PrintBiasedLockingStatistics) {
640 Label L;
641 bne(AT, R0, L);
642 delayed()->nop();
643 push(AT);
644 push(tmp_reg);
645 atomic_inc32((address)BiasedLocking::rebiased_lock_entry_count_addr(), 1, AT, tmp_reg);
646 pop(tmp_reg);
647 pop(AT);
648 bind(L);
649 }
650 if (slow_case != NULL) {
651 beq_far(AT, R0, *slow_case);
652 delayed()->nop();
653 }
655 b(done);
656 delayed()->nop();
657 bind(try_revoke_bias);
658 // The prototype mark in the klass doesn't have the bias bit set any
659 // more, indicating that objects of this data type are not supposed
660 // to be biased any more. We are going to try to reset the mark of
661 // this object to the prototype value and fall through to the
662 // CAS-based locking scheme. Note that if our CAS fails, it means
663 // that another thread raced us for the privilege of revoking the
664 // bias of this particular object, so it's okay to continue in the
665 // normal locking code.
666 //
667 // FIXME: due to a lack of registers we currently blow away the age
668 // bits in this situation. Should attempt to preserve them.
669 ld_ptr(swap_reg, saved_mark_addr);
671 if (need_tmp_reg) {
672 push(tmp_reg);
673 }
674 load_prototype_header(tmp_reg, obj_reg);
675 //if (os::is_MP()) {
676 // lock();
677 //}
678 cmpxchg(tmp_reg, Address(obj_reg, 0), swap_reg);
679 if (need_tmp_reg) {
680 pop(tmp_reg);
681 }
682 // Fall through to the normal CAS-based lock, because no matter what
683 // the result of the above CAS, some thread must have succeeded in
684 // removing the bias bit from the object's header.
685 if (PrintBiasedLockingStatistics) {
686 Label L;
687 bne(AT, R0, L);
688 delayed()->nop();
689 push(AT);
690 push(tmp_reg);
691 atomic_inc32((address)BiasedLocking::revoked_lock_entry_count_addr(), 1, AT, tmp_reg);
692 pop(tmp_reg);
693 pop(AT);
694 bind(L);
695 }
697 bind(cas_label);
698 return null_check_offset;
699 }
701 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
702 assert(UseBiasedLocking, "why call this otherwise?");
704 // Check for biased locking unlock case, which is a no-op
705 // Note: we do not have to check the thread ID for two reasons.
706 // First, the interpreter checks for IllegalMonitorStateException at
707 // a higher level. Second, if the bias was revoked while we held the
708 // lock, the object could not be rebiased toward another thread, so
709 // the bias bit would be clear.
710 #ifdef _LP64
711 ld(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
712 andi(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place);
713 daddi(AT, R0, markOopDesc::biased_lock_pattern);
714 #else
715 lw(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
716 andi(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place);
717 addi(AT, R0, markOopDesc::biased_lock_pattern);
718 #endif
720 beq(AT, temp_reg, done);
721 delayed()->nop();
722 }
724 // NOTE: we dont increment the SP after call like the x86 version, maybe this is a problem, FIXME.
725 // the stack pointer adjustment is needed. see InterpreterMacroAssembler::super_call_VM_leaf
726 // this method will handle the stack problem, you need not to preserve the stack space for the argument now
727 void MacroAssembler::call_VM_leaf_base(address entry_point,
728 int number_of_arguments) {
729 //call(RuntimeAddress(entry_point));
730 //increment(rsp, number_of_arguments * wordSize);
731 Label L, E;
733 assert(number_of_arguments <= 4, "just check");
735 andi(AT, SP, 0xf);
736 beq(AT, R0, L);
737 delayed()->nop();
738 daddi(SP, SP, -8);
739 call(entry_point, relocInfo::runtime_call_type);
740 delayed()->nop();
741 daddi(SP, SP, 8);
742 b(E);
743 delayed()->nop();
745 bind(L);
746 call(entry_point, relocInfo::runtime_call_type);
747 delayed()->nop();
748 bind(E);
749 }
752 void MacroAssembler::jmp(address entry) {
753 patchable_set48(T9, (long)entry);
754 jr(T9);
755 }
757 void MacroAssembler::jmp(address entry, relocInfo::relocType rtype) {
758 switch (rtype) {
759 case relocInfo::runtime_call_type:
760 case relocInfo::none:
761 jmp(entry);
762 break;
763 default:
764 {
765 InstructionMark im(this);
766 relocate(rtype);
767 patchable_set48(T9, (long)entry);
768 jr(T9);
769 }
770 break;
771 }
772 }
774 void MacroAssembler::call(address entry) {
775 // c/c++ code assume T9 is entry point, so we just always move entry to t9
776 // maybe there is some more graceful method to handle this. FIXME
777 // For more info, see class NativeCall.
778 #ifndef _LP64
779 move(T9, (int)entry);
780 #else
781 patchable_set48(T9, (long)entry);
782 #endif
783 jalr(T9);
784 }
786 void MacroAssembler::call(address entry, relocInfo::relocType rtype) {
787 switch (rtype) {
788 case relocInfo::runtime_call_type:
789 case relocInfo::none:
790 call(entry);
791 break;
792 default:
793 {
794 InstructionMark im(this);
795 relocate(rtype);
796 call(entry);
797 }
798 break;
799 }
800 }
802 void MacroAssembler::call(address entry, RelocationHolder& rh)
803 {
804 switch (rh.type()) {
805 case relocInfo::runtime_call_type:
806 case relocInfo::none:
807 call(entry);
808 break;
809 default:
810 {
811 InstructionMark im(this);
812 relocate(rh);
813 call(entry);
814 }
815 break;
816 }
817 }
819 void MacroAssembler::ic_call(address entry) {
820 RelocationHolder rh = virtual_call_Relocation::spec(pc());
821 patchable_set48(IC_Klass, (long)Universe::non_oop_word());
822 assert(entry != NULL, "call most probably wrong");
823 InstructionMark im(this);
824 relocate(rh);
825 patchable_call(entry);
826 }
828 void MacroAssembler::c2bool(Register r) {
829 Label L;
830 Assembler::beq(r, R0, L);
831 delayed()->nop();
832 move(r, 1);
833 bind(L);
834 }
836 #ifndef PRODUCT
837 extern "C" void findpc(intptr_t x);
838 #endif
840 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
841 // In order to get locks to work, we need to fake a in_VM state
842 JavaThread* thread = JavaThread::current();
843 JavaThreadState saved_state = thread->thread_state();
844 thread->set_thread_state(_thread_in_vm);
845 if (ShowMessageBoxOnError) {
846 JavaThread* thread = JavaThread::current();
847 JavaThreadState saved_state = thread->thread_state();
848 thread->set_thread_state(_thread_in_vm);
849 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
850 ttyLocker ttyl;
851 BytecodeCounter::print();
852 }
853 // To see where a verify_oop failed, get $ebx+40/X for this frame.
854 // This is the value of eip which points to where verify_oop will return.
855 if (os::message_box(msg, "Execution stopped, print registers?")) {
856 ttyLocker ttyl;
857 tty->print_cr("eip = 0x%08x", eip);
858 #ifndef PRODUCT
859 tty->cr();
860 findpc(eip);
861 tty->cr();
862 #endif
863 tty->print_cr("rax, = 0x%08x", rax);
864 tty->print_cr("rbx, = 0x%08x", rbx);
865 tty->print_cr("rcx = 0x%08x", rcx);
866 tty->print_cr("rdx = 0x%08x", rdx);
867 tty->print_cr("rdi = 0x%08x", rdi);
868 tty->print_cr("rsi = 0x%08x", rsi);
869 tty->print_cr("rbp, = 0x%08x", rbp);
870 tty->print_cr("rsp = 0x%08x", rsp);
871 BREAKPOINT;
872 }
873 } else {
874 ttyLocker ttyl;
875 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
876 assert(false, "DEBUG MESSAGE");
877 }
878 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
879 }
881 void MacroAssembler::debug(char* msg/*, RegistersForDebugging* regs*/) {
882 if ( ShowMessageBoxOnError ) {
883 JavaThreadState saved_state = JavaThread::current()->thread_state();
884 JavaThread::current()->set_thread_state(_thread_in_vm);
885 {
886 // In order to get locks work, we need to fake a in_VM state
887 ttyLocker ttyl;
888 ::tty->print_cr("EXECUTION STOPPED: %s\n", msg);
889 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
890 BytecodeCounter::print();
891 }
893 // if (os::message_box(msg, "Execution stopped, print registers?"))
894 // regs->print(::tty);
895 }
896 ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state);
897 }
898 else
899 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
900 }
903 void MacroAssembler::stop(const char* msg) {
904 li(A0, (long)msg);
905 #ifndef _LP64
906 //reserver space for argument. added by yjl 7/10/2005
907 addiu(SP, SP, - 1 * wordSize);
908 #endif
909 call(CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
910 delayed()->nop();
911 #ifndef _LP64
912 //restore space for argument
913 addiu(SP, SP, 1 * wordSize);
914 #endif
915 brk(17);
916 }
918 void MacroAssembler::warn(const char* msg) {
919 #ifdef _LP64
920 pushad();
921 li(A0, (long)msg);
922 push(S2);
923 move(AT, -(StackAlignmentInBytes));
924 move(S2, SP); // use S2 as a sender SP holder
925 andr(SP, SP, AT); // align stack as required by ABI
926 call(CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
927 delayed()->nop();
928 move(SP, S2); // use S2 as a sender SP holder
929 pop(S2);
930 popad();
931 #else
932 pushad();
933 addi(SP, SP, -4);
934 sw(A0, SP, -1 * wordSize);
935 li(A0, (long)msg);
936 addi(SP, SP, -1 * wordSize);
937 call(CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
938 delayed()->nop();
939 addi(SP, SP, 1 * wordSize);
940 lw(A0, SP, -1 * wordSize);
941 addi(SP, SP, 4);
942 popad();
943 #endif
944 }
946 void MacroAssembler::print_reg(Register reg) {
947 /*
948 char *s = getenv("PRINT_REG");
949 if (s == NULL)
950 return;
951 if (strcmp(s, "1") != 0)
952 return;
953 */
954 void * cur_pc = pc();
955 pushad();
956 NOT_LP64(push(FP);)
958 li(A0, (long)reg->name());
959 if (reg == SP)
960 addiu(A1, SP, wordSize * 23); //23 registers saved in pushad()
961 else if (reg == A0)
962 ld(A1, SP, wordSize * 19); //A0 has been modified by li(A0, (long)reg->name()). Ugly Code!
963 else
964 move(A1, reg);
965 li(A2, (long)cur_pc);
966 push(S2);
967 move(AT, -(StackAlignmentInBytes));
968 move(S2, SP); // use S2 as a sender SP holder
969 andr(SP, SP, AT); // align stack as required by ABI
970 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_reg_with_pc),relocInfo::runtime_call_type);
971 delayed()->nop();
972 move(SP, S2); // use S2 as a sender SP holder
973 pop(S2);
974 NOT_LP64(pop(FP);)
975 popad();
977 /*
978 pushad();
979 #ifdef _LP64
980 if (reg == SP)
981 addiu(A0, SP, wordSize * 23); //23 registers saved in pushad()
982 else
983 move(A0, reg);
984 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_long),relocInfo::runtime_call_type);
985 delayed()->nop();
986 #else
987 push(FP);
988 move(A0, reg);
989 dsrl32(A1, reg, 0);
990 //call(CAST_FROM_FN_PTR(address, SharedRuntime::print_int),relocInfo::runtime_call_type);
991 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_long),relocInfo::runtime_call_type);
992 delayed()->nop();
993 pop(FP);
994 #endif
995 popad();
996 pushad();
997 NOT_LP64(push(FP);)
998 char b[50];
999 sprintf((char *)b, " pc: %p\n",cur_pc);
1000 li(A0, (long)(char *)b);
1001 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_str),relocInfo::runtime_call_type);
1002 delayed()->nop();
1003 NOT_LP64(pop(FP);)
1004 popad();
1005 */
1006 }
1008 void MacroAssembler::print_reg(FloatRegister reg) {
1009 void * cur_pc = pc();
1010 pushad();
1011 NOT_LP64(push(FP);)
1012 li(A0, (long)reg->name());
1013 push(S2);
1014 move(AT, -(StackAlignmentInBytes));
1015 move(S2, SP); // use S2 as a sender SP holder
1016 andr(SP, SP, AT); // align stack as required by ABI
1017 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_str),relocInfo::runtime_call_type);
1018 delayed()->nop();
1019 move(SP, S2); // use S2 as a sender SP holder
1020 pop(S2);
1021 NOT_LP64(pop(FP);)
1022 popad();
1024 pushad();
1025 NOT_LP64(push(FP);)
1026 #if 1
1027 move(FP, SP);
1028 move(AT, -(StackAlignmentInBytes));
1029 andr(SP , SP , AT);
1030 mov_d(F12, reg);
1031 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_double),relocInfo::runtime_call_type);
1032 delayed()->nop();
1033 move(SP, FP);
1034 #else
1035 mov_s(F12, reg);
1036 //call(CAST_FROM_FN_PTR(address, SharedRuntime::print_float),relocInfo::runtime_call_type);
1037 //delayed()->nop();
1038 #endif
1039 NOT_LP64(pop(FP);)
1040 popad();
1042 #if 0
1043 pushad();
1044 NOT_LP64(push(FP);)
1045 char* b = new char[50];
1046 sprintf(b, " pc: %p\n", cur_pc);
1047 li(A0, (long)b);
1048 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_str),relocInfo::runtime_call_type);
1049 delayed()->nop();
1050 NOT_LP64(pop(FP);)
1051 popad();
1052 #endif
1053 }
1055 void MacroAssembler::increment(Register reg, int imm) {
1056 if (!imm) return;
1057 if (is_simm16(imm)) {
1058 #ifdef _LP64
1059 daddiu(reg, reg, imm);
1060 #else
1061 addiu(reg, reg, imm);
1062 #endif
1063 } else {
1064 move(AT, imm);
1065 #ifdef _LP64
1066 daddu(reg, reg, AT);
1067 #else
1068 addu(reg, reg, AT);
1069 #endif
1070 }
1071 }
1073 void MacroAssembler::decrement(Register reg, int imm) {
1074 increment(reg, -imm);
1075 }
1078 void MacroAssembler::call_VM(Register oop_result,
1079 address entry_point,
1080 bool check_exceptions) {
1081 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1082 }
1084 void MacroAssembler::call_VM(Register oop_result,
1085 address entry_point,
1086 Register arg_1,
1087 bool check_exceptions) {
1088 if (arg_1!=A1) move(A1, arg_1);
1089 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1090 }
1092 void MacroAssembler::call_VM(Register oop_result,
1093 address entry_point,
1094 Register arg_1,
1095 Register arg_2,
1096 bool check_exceptions) {
1097 if (arg_1!=A1) move(A1, arg_1);
1098 if (arg_2!=A2) move(A2, arg_2);
1099 assert(arg_2 != A1, "smashed argument");
1100 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1101 }
1103 void MacroAssembler::call_VM(Register oop_result,
1104 address entry_point,
1105 Register arg_1,
1106 Register arg_2,
1107 Register arg_3,
1108 bool check_exceptions) {
1109 if (arg_1!=A1) move(A1, arg_1);
1110 if (arg_2!=A2) move(A2, arg_2); assert(arg_2 != A1, "smashed argument");
1111 if (arg_3!=A3) move(A3, arg_3); assert(arg_3 != A1 && arg_3 != A2, "smashed argument");
1112 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1113 }
1115 void MacroAssembler::call_VM(Register oop_result,
1116 Register last_java_sp,
1117 address entry_point,
1118 int number_of_arguments,
1119 bool check_exceptions) {
1120 call_VM_base(oop_result, NOREG, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1121 }
1123 void MacroAssembler::call_VM(Register oop_result,
1124 Register last_java_sp,
1125 address entry_point,
1126 Register arg_1,
1127 bool check_exceptions) {
1128 if (arg_1 != A1) move(A1, arg_1);
1129 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1130 }
1132 void MacroAssembler::call_VM(Register oop_result,
1133 Register last_java_sp,
1134 address entry_point,
1135 Register arg_1,
1136 Register arg_2,
1137 bool check_exceptions) {
1138 if (arg_1 != A1) move(A1, arg_1);
1139 if (arg_2 != A2) move(A2, arg_2); assert(arg_2 != A1, "smashed argument");
1140 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1141 }
1143 void MacroAssembler::call_VM(Register oop_result,
1144 Register last_java_sp,
1145 address entry_point,
1146 Register arg_1,
1147 Register arg_2,
1148 Register arg_3,
1149 bool check_exceptions) {
1150 if (arg_1 != A1) move(A1, arg_1);
1151 if (arg_2 != A2) move(A2, arg_2); assert(arg_2 != A1, "smashed argument");
1152 if (arg_3 != A3) move(A3, arg_3); assert(arg_3 != A1 && arg_3 != A2, "smashed argument");
1153 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1154 }
1156 void MacroAssembler::call_VM_base(Register oop_result,
1157 Register java_thread,
1158 Register last_java_sp,
1159 address entry_point,
1160 int number_of_arguments,
1161 bool check_exceptions) {
1163 address before_call_pc;
1164 // determine java_thread register
1165 if (!java_thread->is_valid()) {
1166 #ifndef OPT_THREAD
1167 java_thread = T2;
1168 get_thread(java_thread);
1169 #else
1170 java_thread = TREG;
1171 #endif
1172 }
1173 // determine last_java_sp register
1174 if (!last_java_sp->is_valid()) {
1175 last_java_sp = SP;
1176 }
1177 // debugging support
1178 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1179 assert(number_of_arguments <= 4 , "cannot have negative number of arguments");
1180 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1181 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1183 assert(last_java_sp != FP, "this code doesn't work for last_java_sp == fp, which currently can't portably work anyway since C2 doesn't save ebp");
1185 // set last Java frame before call
1186 before_call_pc = (address)pc();
1187 set_last_Java_frame(java_thread, last_java_sp, FP, before_call_pc);
1189 // do the call
1190 move(A0, java_thread);
1191 call(entry_point, relocInfo::runtime_call_type);
1192 delayed()->nop();
1194 // restore the thread (cannot use the pushed argument since arguments
1195 // may be overwritten by C code generated by an optimizing compiler);
1196 // however can use the register value directly if it is callee saved.
1197 #ifndef OPT_THREAD
1198 get_thread(java_thread);
1199 #else
1200 #ifdef ASSERT
1201 {
1202 Label L;
1203 get_thread(AT);
1204 beq(java_thread, AT, L);
1205 delayed()->nop();
1206 stop("MacroAssembler::call_VM_base: edi not callee saved?");
1207 bind(L);
1208 }
1209 #endif
1210 #endif
1212 // discard thread and arguments
1213 ld_ptr(SP, java_thread, in_bytes(JavaThread::last_Java_sp_offset()));
1214 // reset last Java frame
1215 reset_last_Java_frame(java_thread, false, true);
1217 check_and_handle_popframe(java_thread);
1218 check_and_handle_earlyret(java_thread);
1219 if (check_exceptions) {
1220 // check for pending exceptions (java_thread is set upon return)
1221 Label L;
1222 #ifdef _LP64
1223 ld(AT, java_thread, in_bytes(Thread::pending_exception_offset()));
1224 #else
1225 lw(AT, java_thread, in_bytes(Thread::pending_exception_offset()));
1226 #endif
1227 beq(AT, R0, L);
1228 delayed()->nop();
1229 li(AT, before_call_pc);
1230 push(AT);
1231 jmp(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type);
1232 delayed()->nop();
1233 bind(L);
1234 }
1236 // get oop result if there is one and reset the value in the thread
1237 if (oop_result->is_valid()) {
1238 #ifdef _LP64
1239 ld(oop_result, java_thread, in_bytes(JavaThread::vm_result_offset()));
1240 sd(R0, java_thread, in_bytes(JavaThread::vm_result_offset()));
1241 #else
1242 lw(oop_result, java_thread, in_bytes(JavaThread::vm_result_offset()));
1243 sw(R0, java_thread, in_bytes(JavaThread::vm_result_offset()));
1244 #endif
1245 verify_oop(oop_result);
1246 }
1247 }
1249 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1251 move(V0, SP);
1252 //we also reserve space for java_thread here
1253 #ifndef _LP64
1254 daddi(SP, SP, (1 + number_of_arguments) * (- wordSize));
1255 #endif
1256 move(AT, -(StackAlignmentInBytes));
1257 andr(SP, SP, AT);
1258 call_VM_base(oop_result, NOREG, V0, entry_point, number_of_arguments, check_exceptions);
1260 }
1262 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1263 call_VM_leaf_base(entry_point, number_of_arguments);
1264 }
1266 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1267 if (arg_0 != A0) move(A0, arg_0);
1268 call_VM_leaf(entry_point, 1);
1269 }
1271 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1272 if (arg_0 != A0) move(A0, arg_0);
1273 if (arg_1 != A1) move(A1, arg_1); assert(arg_1 != A0, "smashed argument");
1274 call_VM_leaf(entry_point, 2);
1275 }
1277 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1278 if (arg_0 != A0) move(A0, arg_0);
1279 if (arg_1 != A1) move(A1, arg_1); assert(arg_1 != A0, "smashed argument");
1280 if (arg_2 != A2) move(A2, arg_2); assert(arg_2 != A0 && arg_2 != A1, "smashed argument");
1281 call_VM_leaf(entry_point, 3);
1282 }
1283 void MacroAssembler::super_call_VM_leaf(address entry_point) {
1284 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1285 }
1288 void MacroAssembler::super_call_VM_leaf(address entry_point,
1289 Register arg_1) {
1290 if (arg_1 != A0) move(A0, arg_1);
1291 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1292 }
1295 void MacroAssembler::super_call_VM_leaf(address entry_point,
1296 Register arg_1,
1297 Register arg_2) {
1298 if (arg_1 != A0) move(A0, arg_1);
1299 if (arg_2 != A1) move(A1, arg_2); assert(arg_2 != A0, "smashed argument");
1300 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1301 }
1302 void MacroAssembler::super_call_VM_leaf(address entry_point,
1303 Register arg_1,
1304 Register arg_2,
1305 Register arg_3) {
1306 if (arg_1 != A0) move(A0, arg_1);
1307 if (arg_2 != A1) move(A1, arg_2); assert(arg_2 != A0, "smashed argument");
1308 if (arg_3 != A2) move(A2, arg_3); assert(arg_3 != A0 && arg_3 != A1, "smashed argument");
1309 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1310 }
1312 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1313 }
1315 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1316 }
1318 void MacroAssembler::null_check(Register reg, int offset) {
1319 if (needs_explicit_null_check(offset)) {
1320 // provoke OS NULL exception if reg = NULL by
1321 // accessing M[reg] w/o changing any (non-CC) registers
1322 // NOTE: cmpl is plenty here to provoke a segv
1323 lw(AT, reg, 0);
1324 // Note: should probably use testl(rax, Address(reg, 0));
1325 // may be shorter code (however, this version of
1326 // testl needs to be implemented first)
1327 } else {
1328 // nothing to do, (later) access of M[reg + offset]
1329 // will provoke OS NULL exception if reg = NULL
1330 }
1331 }
1333 void MacroAssembler::enter() {
1334 push2(RA, FP);
1335 move(FP, SP);
1336 }
1338 void MacroAssembler::leave() {
1339 #ifndef _LP64
1340 //move(SP, FP);
1341 //pop2(FP, RA);
1342 addi(SP, FP, 2 * wordSize);
1343 lw(RA, SP, - 1 * wordSize);
1344 lw(FP, SP, - 2 * wordSize);
1345 #else
1346 daddi(SP, FP, 2 * wordSize);
1347 ld(RA, SP, - 1 * wordSize);
1348 ld(FP, SP, - 2 * wordSize);
1349 #endif
1350 }
1351 /*
1352 void MacroAssembler::os_breakpoint() {
1353 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
1354 // (e.g., MSVC can't call ps() otherwise)
1355 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
1356 }
1357 */
1358 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
1359 // determine java_thread register
1360 if (!java_thread->is_valid()) {
1361 #ifndef OPT_THREAD
1362 java_thread = T1;
1363 get_thread(java_thread);
1364 #else
1365 java_thread = TREG;
1366 #endif
1367 }
1368 // we must set sp to zero to clear frame
1369 st_ptr(R0, java_thread, in_bytes(JavaThread::last_Java_sp_offset()));
1370 // must clear fp, so that compiled frames are not confused; it is possible
1371 // that we need it only for debugging
1372 if(clear_fp)
1373 st_ptr(R0, java_thread, in_bytes(JavaThread::last_Java_fp_offset()));
1375 if (clear_pc)
1376 st_ptr(R0, java_thread, in_bytes(JavaThread::last_Java_pc_offset()));
1377 }
1379 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
1380 bool clear_pc) {
1381 Register thread = TREG;
1382 #ifndef OPT_THREAD
1383 get_thread(thread);
1384 #endif
1385 // we must set sp to zero to clear frame
1386 sd(R0, Address(thread, JavaThread::last_Java_sp_offset()));
1387 // must clear fp, so that compiled frames are not confused; it is
1388 // possible that we need it only for debugging
1389 if (clear_fp) {
1390 sd(R0, Address(thread, JavaThread::last_Java_fp_offset()));
1391 }
1393 if (clear_pc) {
1394 sd(R0, Address(thread, JavaThread::last_Java_pc_offset()));
1395 }
1396 }
1398 // Write serialization page so VM thread can do a pseudo remote membar.
1399 // We use the current thread pointer to calculate a thread specific
1400 // offset to write to within the page. This minimizes bus traffic
1401 // due to cache line collision.
1402 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
1403 move(tmp, thread);
1404 srl(tmp, tmp,os::get_serialize_page_shift_count());
1405 move(AT, (os::vm_page_size() - sizeof(int)));
1406 andr(tmp, tmp,AT);
1407 sw(tmp,Address(tmp, (intptr_t)os::get_memory_serialize_page()));
1408 }
1410 // Calls to C land
1411 //
1412 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
1413 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
1414 // has to be reset to 0. This is required to allow proper stack traversal.
1415 void MacroAssembler::set_last_Java_frame(Register java_thread,
1416 Register last_java_sp,
1417 Register last_java_fp,
1418 address last_java_pc) {
1419 // determine java_thread register
1420 if (!java_thread->is_valid()) {
1421 #ifndef OPT_THREAD
1422 java_thread = T2;
1423 get_thread(java_thread);
1424 #else
1425 java_thread = TREG;
1426 #endif
1427 }
1428 // determine last_java_sp register
1429 if (!last_java_sp->is_valid()) {
1430 last_java_sp = SP;
1431 }
1433 // last_java_fp is optional
1435 if (last_java_fp->is_valid()) {
1436 st_ptr(last_java_fp, java_thread, in_bytes(JavaThread::last_Java_fp_offset()));
1437 }
1439 // last_java_pc is optional
1441 if (last_java_pc != NULL) {
1442 relocate(relocInfo::internal_pc_type);
1443 patchable_set48(AT, (long)last_java_pc);
1444 st_ptr(AT, java_thread, in_bytes(JavaThread::last_Java_pc_offset()));
1445 }
1446 st_ptr(last_java_sp, java_thread, in_bytes(JavaThread::last_Java_sp_offset()));
1447 }
1449 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
1450 Register last_java_fp,
1451 address last_java_pc) {
1452 // determine last_java_sp register
1453 if (!last_java_sp->is_valid()) {
1454 last_java_sp = SP;
1455 }
1457 Register thread = TREG;
1458 #ifndef OPT_THREAD
1459 get_thread(thread);
1460 #endif
1461 // last_java_fp is optional
1462 if (last_java_fp->is_valid()) {
1463 sd(last_java_fp, Address(thread, JavaThread::last_Java_fp_offset()));
1464 }
1466 // last_java_pc is optional
1467 if (last_java_pc != NULL) {
1468 Address java_pc(thread,
1469 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
1470 li(AT, (intptr_t)(last_java_pc));
1471 sd(AT, java_pc);
1472 }
1474 sd(last_java_sp, Address(thread, JavaThread::last_Java_sp_offset()));
1475 }
1478 //////////////////////////////////////////////////////////////////////////////////
1479 #if INCLUDE_ALL_GCS
1481 void MacroAssembler::g1_write_barrier_pre(Register obj,
1482 Register pre_val,
1483 Register thread,
1484 Register tmp,
1485 bool tosca_live,
1486 bool expand_call) {
1488 // If expand_call is true then we expand the call_VM_leaf macro
1489 // directly to skip generating the check by
1490 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
1492 #ifdef _LP64
1493 assert(thread == TREG, "must be");
1494 #endif // _LP64
1496 Label done;
1497 Label runtime;
1499 assert(pre_val != noreg, "check this code");
1501 if (obj != noreg) {
1502 assert_different_registers(obj, pre_val, tmp);
1503 assert(pre_val != V0, "check this code");
1504 }
1506 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
1507 PtrQueue::byte_offset_of_active()));
1508 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
1509 PtrQueue::byte_offset_of_index()));
1510 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
1511 PtrQueue::byte_offset_of_buf()));
1514 // Is marking active?
1515 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
1516 //cmpl(in_progress, 0);
1517 lw(AT, in_progress);
1518 } else {
1519 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
1520 //cmpb(in_progress, 0);
1521 lb(AT, in_progress);
1522 }
1523 //jcc(Assembler::equal, done);
1524 beq(AT, R0, done);
1525 nop();
1527 // Do we need to load the previous value?
1528 if (obj != noreg) {
1529 load_heap_oop(pre_val, Address(obj, 0));
1530 }
1532 // Is the previous value null?
1533 //cmpptr(pre_val, (int32_t) NULL_WORD);
1534 //jcc(Assembler::equal, done);
1535 beq(pre_val, R0, done);
1536 nop();
1538 // Can we store original value in the thread's buffer?
1539 // Is index == 0?
1540 // (The index field is typed as size_t.)
1542 //movptr(tmp, index); // tmp := *index_adr
1543 ld(tmp, index);
1544 //cmpptr(tmp, 0); // tmp == 0?
1545 //jcc(Assembler::equal, runtime); // If yes, goto runtime
1546 beq(tmp, R0, runtime);
1547 nop();
1549 //subptr(tmp, wordSize); // tmp := tmp - wordSize
1550 //movptr(index, tmp); // *index_adr := tmp
1551 //addptr(tmp, buffer); // tmp := tmp + *buffer_adr
1552 daddiu(tmp, tmp, -1 * wordSize);
1553 sd(tmp, index);
1554 ld(AT, buffer);
1555 daddu(tmp, tmp, AT);
1557 // Record the previous value
1558 //movptr(Address(tmp, 0), pre_val);
1559 //jmp(done);
1560 sd(pre_val, tmp, 0);
1561 beq(R0, R0, done);
1562 nop();
1564 bind(runtime);
1565 // save the live input values
1566 //if(tosca_live) push(rax);
1567 if(tosca_live) push(V0);
1569 //if (obj != noreg && obj != rax)
1570 if (obj != noreg && obj != V0)
1571 push(obj);
1573 //if (pre_val != rax)
1574 if (pre_val != V0)
1575 push(pre_val);
1577 // Calling the runtime using the regular call_VM_leaf mechanism generates
1578 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
1579 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
1580 //
1581 // If we care generating the pre-barrier without a frame (e.g. in the
1582 // intrinsified Reference.get() routine) then ebp might be pointing to
1583 // the caller frame and so this check will most likely fail at runtime.
1584 //
1585 // Expanding the call directly bypasses the generation of the check.
1586 // So when we do not have have a full interpreter frame on the stack
1587 // expand_call should be passed true.
1589 NOT_LP64( push(thread); )
1591 if (expand_call) {
1592 //LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
1593 LP64_ONLY( assert(pre_val != A1, "smashed arg"); )
1594 //pass_arg1(this, thread);
1595 if (thread != A1) move(A1, thread);
1596 //pass_arg0(this, pre_val);
1597 if (pre_val != A0) move(A0, pre_val);
1598 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
1599 } else {
1600 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
1601 }
1603 NOT_LP64( pop(thread); )
1605 // save the live input values
1606 //if (pre_val != rax)
1607 if (pre_val != V0)
1608 pop(pre_val);
1610 //if (obj != noreg && obj != rax)
1611 if (obj != noreg && obj != V0)
1612 pop(obj);
1614 //if(tosca_live) pop(rax);
1615 if(tosca_live) pop(V0);
1617 bind(done);
1618 }
1620 void MacroAssembler::g1_write_barrier_post(Register store_addr,
1621 Register new_val,
1622 Register thread,
1623 Register tmp,
1624 Register tmp2) {
1625 assert(tmp == AT, "must be");
1626 assert(tmp2 == AT, "must be");
1627 #ifdef _LP64
1628 assert(thread == TREG, "must be");
1629 #endif // _LP64
1631 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
1632 PtrQueue::byte_offset_of_index()));
1633 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
1634 PtrQueue::byte_offset_of_buf()));
1636 BarrierSet* bs = Universe::heap()->barrier_set();
1637 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
1638 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
1640 Label done;
1641 Label runtime;
1643 // Does store cross heap regions?
1645 //movptr(tmp, store_addr);
1646 //xorptr(tmp, new_val);
1647 //shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
1648 //jcc(Assembler::equal, done);
1649 xorr(AT, store_addr, new_val);
1650 dsrl(AT, AT, HeapRegion::LogOfHRGrainBytes);
1651 beq(AT, R0, done);
1652 nop();
1655 // crosses regions, storing NULL?
1657 //cmpptr(new_val, (int32_t) NULL_WORD);
1658 //jcc(Assembler::equal, done);
1659 beq(new_val, R0, done);
1660 nop();
1662 // storing region crossing non-NULL, is card already dirty?
1664 const Register card_addr = tmp;
1665 const Register cardtable = tmp2;
1667 //movptr(card_addr, store_addr);
1668 //shrptr(card_addr, CardTableModRefBS::card_shift);
1669 move(card_addr, store_addr);
1670 dsrl(card_addr, card_addr, CardTableModRefBS::card_shift);
1671 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
1672 // a valid address and therefore is not properly handled by the relocation code.
1673 //movptr(cardtable, (intptr_t)ct->byte_map_base);
1674 //addptr(card_addr, cardtable);
1675 set64(cardtable, (intptr_t)ct->byte_map_base);
1676 daddu(card_addr, card_addr, cardtable);
1678 //cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
1679 //jcc(Assembler::equal, done);
1680 lb(AT, card_addr, 0);
1681 daddiu(AT, AT, -1 * (int)G1SATBCardTableModRefBS::g1_young_card_val());
1682 beq(AT, R0, done);
1683 nop();
1685 //membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
1686 //cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
1687 //jcc(Assembler::equal, done);
1688 sync();
1689 lb(AT, card_addr, 0);
1690 daddiu(AT, AT, -1 * (int)(int)CardTableModRefBS::dirty_card_val());
1691 beq(AT, R0, done);
1692 nop();
1695 // storing a region crossing, non-NULL oop, card is clean.
1696 // dirty card and log.
1698 //movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
1699 move(AT, (int)CardTableModRefBS::dirty_card_val());
1700 sb(AT, card_addr, 0);
1702 //cmpl(queue_index, 0);
1703 //jcc(Assembler::equal, runtime);
1704 //subl(queue_index, wordSize);
1705 //movptr(tmp2, buffer);
1706 lw(AT, queue_index);
1707 beq(AT, R0, runtime);
1708 nop();
1709 daddiu(AT, AT, -1 * wordSize);
1710 sw(AT, queue_index);
1711 ld(tmp2, buffer);
1712 #ifdef _LP64
1713 //movslq(rscratch1, queue_index);
1714 //addq(tmp2, rscratch1);
1715 //movq(Address(tmp2, 0), card_addr);
1716 ld(AT, queue_index);
1717 daddu(tmp2, tmp2, AT);
1718 sd(card_addr, tmp2, 0);
1719 #else
1720 //addl(tmp2, queue_index);
1721 //movl(Address(tmp2, 0), card_addr);
1722 lw(AT, queue_index);
1723 addu32(tmp2, tmp2, AT);
1724 sw(card_addr, tmp2, 0);
1725 #endif
1726 //jmp(done);
1727 beq(R0, R0, done);
1728 nop();
1730 bind(runtime);
1731 // save the live input values
1732 push(store_addr);
1733 push(new_val);
1734 #ifdef _LP64
1735 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, TREG);
1736 #else
1737 push(thread);
1738 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
1739 pop(thread);
1740 #endif
1741 pop(new_val);
1742 pop(store_addr);
1744 bind(done);
1745 }
1747 #endif // INCLUDE_ALL_GCS
1748 //////////////////////////////////////////////////////////////////////////////////
1751 void MacroAssembler::store_check(Register obj) {
1752 // Does a store check for the oop in register obj. The content of
1753 // register obj is destroyed afterwards.
1754 store_check_part_1(obj);
1755 store_check_part_2(obj);
1756 }
1758 void MacroAssembler::store_check(Register obj, Address dst) {
1759 store_check(obj);
1760 }
1763 // split the store check operation so that other instructions can be scheduled inbetween
1764 void MacroAssembler::store_check_part_1(Register obj) {
1765 BarrierSet* bs = Universe::heap()->barrier_set();
1766 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
1767 #ifdef _LP64
1768 dsrl(obj, obj, CardTableModRefBS::card_shift);
1769 #else
1770 shr(obj, CardTableModRefBS::card_shift);
1771 #endif
1772 }
1774 void MacroAssembler::store_check_part_2(Register obj) {
1775 BarrierSet* bs = Universe::heap()->barrier_set();
1776 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
1777 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
1778 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
1780 li(AT, (long)ct->byte_map_base);
1781 #ifdef _LP64
1782 dadd(AT, AT, obj);
1783 #else
1784 add(AT, AT, obj);
1785 #endif
1786 sb(R0, AT, 0);
1787 sync();
1788 }
1790 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
1791 void MacroAssembler::tlab_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes,
1792 Register t1, Register t2, Label& slow_case) {
1793 assert_different_registers(obj, var_size_in_bytes, t1, t2, AT);
1795 Register end = t2;
1796 #ifndef OPT_THREAD
1797 Register thread = t1;
1798 get_thread(thread);
1799 #else
1800 Register thread = TREG;
1801 #endif
1802 verify_tlab(t1, t2);//blows t1&t2
1804 ld_ptr(obj, thread, in_bytes(JavaThread::tlab_top_offset()));
1806 if (var_size_in_bytes == NOREG) {
1807 // i dont think we need move con_size_in_bytes to a register first.
1808 // by yjl 8/17/2005
1809 assert(is_simm16(con_size_in_bytes), "fixme by moving imm to a register first");
1810 addi(end, obj, con_size_in_bytes);
1811 } else {
1812 add(end, obj, var_size_in_bytes);
1813 }
1815 ld_ptr(AT, thread, in_bytes(JavaThread::tlab_end_offset()));
1816 sltu(AT, AT, end);
1817 bne_far(AT, R0, slow_case);
1818 delayed()->nop();
1821 // update the tlab top pointer
1822 st_ptr(end, thread, in_bytes(JavaThread::tlab_top_offset()));
1824 // recover var_size_in_bytes if necessary
1825 /*if (var_size_in_bytes == end) {
1826 sub(var_size_in_bytes, end, obj);
1827 }*/
1829 verify_tlab(t1, t2);
1830 }
1832 // Defines obj, preserves var_size_in_bytes
1833 void MacroAssembler::eden_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes,
1834 Register t1, Register t2, Label& slow_case) {
1835 assert_different_registers(obj, var_size_in_bytes, t1, AT);
1836 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { //by yyq
1837 // No allocation in the shared eden.
1838 b_far(slow_case);
1839 delayed()->nop();
1840 } else {
1842 #ifndef _LP64
1843 Address heap_top(t1, Assembler::split_low((intptr_t)Universe::heap()->top_addr()));
1844 lui(t1, split_high((intptr_t)Universe::heap()->top_addr()));
1845 #else
1846 Address heap_top(t1);
1847 li(t1, (long)Universe::heap()->top_addr());
1848 #endif
1849 ld_ptr(obj, heap_top);
1851 Register end = t2;
1852 Label retry;
1854 bind(retry);
1855 if (var_size_in_bytes == NOREG) {
1856 // i dont think we need move con_size_in_bytes to a register first.
1857 assert(is_simm16(con_size_in_bytes), "fixme by moving imm to a register first");
1858 addi(end, obj, con_size_in_bytes);
1859 } else {
1860 add(end, obj, var_size_in_bytes);
1861 }
1862 // if end < obj then we wrapped around => object too long => slow case
1863 sltu(AT, end, obj);
1864 bne_far(AT, R0, slow_case);
1865 delayed()->nop();
1867 li(AT, (long)Universe::heap()->end_addr());
1868 sltu(AT, AT, end);
1869 bne_far(AT, R0, slow_case);
1870 delayed()->nop();
1871 // Compare obj with the top addr, and if still equal, store the new top addr in
1872 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
1873 // it otherwise. Use lock prefix for atomicity on MPs.
1874 //if (os::is_MP()) {
1875 // sync();
1876 //}
1878 // if someone beat us on the allocation, try again, otherwise continue
1879 cmpxchg(end, heap_top, obj);
1880 beq_far(AT, R0, retry); //by yyq
1881 delayed()->nop();
1883 }
1884 }
1886 // C2 doesn't invoke this one.
1887 void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) {
1888 Register top = T0;
1889 Register t1 = T1;
1890 /* Jin: tlab_refill() is called in
1892 [c1_Runtime1_mips.cpp] Runtime1::generate_code_for(new_type_array_id);
1894 In generate_code_for(), T2 has been assigned as a register(length), which is used
1895 after calling tlab_refill();
1896 Therefore, tlab_refill() should not use T2.
1898 Source:
1900 Exception in thread "main" java.lang.ArrayIndexOutOfBoundsException
1901 at java.lang.System.arraycopy(Native Method)
1902 at java.util.Arrays.copyOf(Arrays.java:2799) <-- alloc_array
1903 at sun.misc.Resource.getBytes(Resource.java:117)
1904 at java.net.URLClassLoader.defineClass(URLClassLoader.java:273)
1905 at java.net.URLClassLoader.findClass(URLClassLoader.java:205)
1906 at java.lang.ClassLoader.loadClass(ClassLoader.java:321)
1907 */
1908 Register t2 = T9;
1909 Register t3 = T3;
1910 Register thread_reg = T8;
1911 Label do_refill, discard_tlab;
1912 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { //by yyq
1913 // No allocation in the shared eden.
1914 b(slow_case);
1915 delayed()->nop();
1916 }
1918 get_thread(thread_reg);
1920 ld_ptr(top, thread_reg, in_bytes(JavaThread::tlab_top_offset()));
1921 ld_ptr(t1, thread_reg, in_bytes(JavaThread::tlab_end_offset()));
1923 // calculate amount of free space
1924 sub(t1, t1, top);
1925 shr(t1, LogHeapWordSize);
1927 // Retain tlab and allocate object in shared space if
1928 // the amount free in the tlab is too large to discard.
1929 ld_ptr(t2, thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()));
1930 slt(AT, t2, t1);
1931 beq(AT, R0, discard_tlab);
1932 delayed()->nop();
1934 // Retain
1936 #ifndef _LP64
1937 move(AT, ThreadLocalAllocBuffer::refill_waste_limit_increment());
1938 #else
1939 li(AT, ThreadLocalAllocBuffer::refill_waste_limit_increment());
1940 #endif
1941 add(t2, t2, AT);
1942 st_ptr(t2, thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()));
1944 if (TLABStats) {
1945 // increment number of slow_allocations
1946 lw(AT, thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset()));
1947 addiu(AT, AT, 1);
1948 sw(AT, thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset()));
1949 }
1950 b(try_eden);
1951 delayed()->nop();
1953 bind(discard_tlab);
1954 if (TLABStats) {
1955 // increment number of refills
1956 lw(AT, thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset()));
1957 addi(AT, AT, 1);
1958 sw(AT, thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset()));
1959 // accumulate wastage -- t1 is amount free in tlab
1960 lw(AT, thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset()));
1961 add(AT, AT, t1);
1962 sw(AT, thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset()));
1963 }
1965 // if tlab is currently allocated (top or end != null) then
1966 // fill [top, end + alignment_reserve) with array object
1967 beq(top, R0, do_refill);
1968 delayed()->nop();
1970 // set up the mark word
1971 li(AT, (long)markOopDesc::prototype()->copy_set_hash(0x2));
1972 st_ptr(AT, top, oopDesc::mark_offset_in_bytes());
1974 // set the length to the remaining space
1975 addi(t1, t1, - typeArrayOopDesc::header_size(T_INT));
1976 addi(t1, t1, ThreadLocalAllocBuffer::alignment_reserve());
1977 shl(t1, log2_intptr(HeapWordSize/sizeof(jint)));
1978 sw(t1, top, arrayOopDesc::length_offset_in_bytes());
1980 // set klass to intArrayKlass
1981 #ifndef _LP64
1982 lui(AT, split_high((intptr_t)Universe::intArrayKlassObj_addr()));
1983 lw(t1, AT, split_low((intptr_t)Universe::intArrayKlassObj_addr()));
1984 #else
1985 li(AT, (intptr_t)Universe::intArrayKlassObj_addr());
1986 ld_ptr(t1, AT, 0);
1987 #endif
1988 //st_ptr(t1, top, oopDesc::klass_offset_in_bytes());
1989 store_klass(top, t1);
1991 // refill the tlab with an eden allocation
1992 bind(do_refill);
1993 ld_ptr(t1, thread_reg, in_bytes(JavaThread::tlab_size_offset()));
1994 shl(t1, LogHeapWordSize);
1995 // add object_size ??
1996 eden_allocate(top, t1, 0, t2, t3, slow_case);
1998 // Check that t1 was preserved in eden_allocate.
1999 #ifdef ASSERT
2000 if (UseTLAB) {
2001 Label ok;
2002 assert_different_registers(thread_reg, t1);
2003 ld_ptr(AT, thread_reg, in_bytes(JavaThread::tlab_size_offset()));
2004 shl(AT, LogHeapWordSize);
2005 beq(AT, t1, ok);
2006 delayed()->nop();
2007 stop("assert(t1 != tlab size)");
2008 should_not_reach_here();
2010 bind(ok);
2011 }
2012 #endif
2013 st_ptr(top, thread_reg, in_bytes(JavaThread::tlab_start_offset()));
2014 st_ptr(top, thread_reg, in_bytes(JavaThread::tlab_top_offset()));
2015 add(top, top, t1);
2016 addi(top, top, - ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
2017 st_ptr(top, thread_reg, in_bytes(JavaThread::tlab_end_offset()));
2018 verify_tlab(t1, t2);
2019 b(retry);
2020 delayed()->nop();
2021 }
2023 static const double pi_4 = 0.7853981633974483;
2025 // the x86 version is to clumsy, i dont think we need that fuss. maybe i'm wrong, FIXME
2026 // must get argument(a double) in F12/F13
2027 //void MacroAssembler::trigfunc(char trig, bool preserve_cpu_regs, int num_fpu_regs_in_use) {
2028 //We need to preseve the register which maybe modified during the Call @Jerome
2029 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
2030 //save all modified register here
2031 // if (preserve_cpu_regs) {
2032 // }
2033 //FIXME, in the disassembly of tirgfunc, only used V0,V1,T9, SP,RA,so we ony save V0,V1,T9
2034 pushad();
2035 //we should preserve the stack space before we call
2036 addi(SP, SP, -wordSize * 2);
2037 switch (trig){
2038 case 's' :
2039 call( CAST_FROM_FN_PTR(address, SharedRuntime::dsin), relocInfo::runtime_call_type );
2040 delayed()->nop();
2041 break;
2042 case 'c':
2043 call( CAST_FROM_FN_PTR(address, SharedRuntime::dcos), relocInfo::runtime_call_type );
2044 delayed()->nop();
2045 break;
2046 case 't':
2047 call( CAST_FROM_FN_PTR(address, SharedRuntime::dtan), relocInfo::runtime_call_type );
2048 delayed()->nop();
2049 break;
2050 default:assert (false, "bad intrinsic");
2051 break;
2053 }
2055 addi(SP, SP, wordSize * 2);
2056 popad();
2057 // if (preserve_cpu_regs) {
2058 // }
2059 }
2061 #ifdef _LP64
2062 void MacroAssembler::li(Register rd, long imm) {
2063 if (imm <= max_jint && imm >= min_jint) {
2064 li32(rd, (int)imm);
2065 } else if (julong(imm) <= 0xFFFFFFFF) {
2066 assert_not_delayed();
2067 // lui sign-extends, so we can't use that.
2068 ori(rd, R0, julong(imm) >> 16);
2069 dsll(rd, rd, 16);
2070 ori(rd, rd, split_low(imm));
2071 //aoqi_test
2072 //} else if ((imm > 0) && ((imm >> 48) == 0)) {
2073 } else if ((imm > 0) && is_simm16(imm >> 32)) {
2074 /* A 48-bit address */
2075 li48(rd, imm);
2076 } else {
2077 li64(rd, imm);
2078 }
2079 }
2080 #else
2081 void MacroAssembler::li(Register rd, long imm) {
2082 li32(rd, (int)imm);
2083 }
2084 #endif
2086 void MacroAssembler::li32(Register reg, int imm) {
2087 if (is_simm16(imm)) {
2088 /* Jin: for imm < 0, we should use addi instead of addiu.
2089 *
2090 * java.lang.StringCoding$StringDecoder.decode(jobject, jint, jint)
2091 *
2092 * 78 move [int:-1|I] [a0|I]
2093 * : daddi a0, zero, 0xffffffff (correct)
2094 * : daddiu a0, zero, 0xffffffff (incorrect)
2095 */
2096 if (imm >= 0)
2097 addiu(reg, R0, imm);
2098 else
2099 addi(reg, R0, imm);
2100 } else {
2101 lui(reg, split_low(imm >> 16));
2102 if (split_low(imm))
2103 ori(reg, reg, split_low(imm));
2104 }
2105 }
2107 #ifdef _LP64
2108 void MacroAssembler::set64(Register d, jlong value) {
2109 assert_not_delayed();
2111 int hi = (int)(value >> 32);
2112 int lo = (int)(value & ~0);
2114 if (value == lo) { // 32-bit integer
2115 if (is_simm16(value)) {
2116 daddiu(d, R0, value);
2117 } else {
2118 lui(d, split_low(value >> 16));
2119 if (split_low(value)) {
2120 ori(d, d, split_low(value));
2121 }
2122 }
2123 } else if (hi == 0) { // hardware zero-extends to upper 32
2124 ori(d, R0, julong(value) >> 16);
2125 dsll(d, d, 16);
2126 if (split_low(value)) {
2127 ori(d, d, split_low(value));
2128 }
2129 } else if ((value> 0) && is_simm16(value >> 32)) { // li48
2130 // 4 insts
2131 li48(d, value);
2132 } else { // li64
2133 // 6 insts
2134 li64(d, value);
2135 }
2136 }
2139 int MacroAssembler::insts_for_set64(jlong value) {
2140 int hi = (int)(value >> 32);
2141 int lo = (int)(value & ~0);
2143 int count = 0;
2145 if (value == lo) { // 32-bit integer
2146 if (is_simm16(value)) {
2147 //daddiu(d, R0, value);
2148 count++;
2149 } else {
2150 //lui(d, split_low(value >> 16));
2151 count++;
2152 if (split_low(value)) {
2153 //ori(d, d, split_low(value));
2154 count++;
2155 }
2156 }
2157 } else if (hi == 0) { // hardware zero-extends to upper 32
2158 //ori(d, R0, julong(value) >> 16);
2159 //dsll(d, d, 16);
2160 count += 2;
2161 if (split_low(value)) {
2162 //ori(d, d, split_low(value));
2163 count++;
2164 }
2165 } else if ((value> 0) && is_simm16(value >> 32)) { // li48
2166 // 4 insts
2167 //li48(d, value);
2168 count += 4;
2169 } else { // li64
2170 // 6 insts
2171 //li64(d, value);
2172 count += 6;
2173 }
2175 return count;
2176 }
2178 void MacroAssembler::patchable_set48(Register d, jlong value) {
2179 assert_not_delayed();
2181 int hi = (int)(value >> 32);
2182 int lo = (int)(value & ~0);
2184 int count = 0;
2186 if (value == lo) { // 32-bit integer
2187 if (is_simm16(value)) {
2188 daddiu(d, R0, value);
2189 count += 1;
2190 } else {
2191 lui(d, split_low(value >> 16));
2192 count += 1;
2193 if (split_low(value)) {
2194 ori(d, d, split_low(value));
2195 count += 1;
2196 }
2197 }
2198 } else if (hi == 0) { // hardware zero-extends to upper 32
2199 ori(d, R0, julong(value) >> 16);
2200 dsll(d, d, 16);
2201 count += 2;
2202 if (split_low(value)) {
2203 ori(d, d, split_low(value));
2204 count += 1;
2205 }
2206 } else if ((value> 0) && is_simm16(value >> 32)) { // li48
2207 // 4 insts
2208 li48(d, value);
2209 count += 4;
2210 } else { // li64
2211 tty->print_cr("value = 0x%x", value);
2212 guarantee(false, "Not supported yet !");
2213 }
2215 for (count; count < 4; count++) {
2216 nop();
2217 }
2218 }
2220 void MacroAssembler::patchable_set32(Register d, jlong value) {
2221 assert_not_delayed();
2223 int hi = (int)(value >> 32);
2224 int lo = (int)(value & ~0);
2226 int count = 0;
2228 if (value == lo) { // 32-bit integer
2229 if (is_simm16(value)) {
2230 daddiu(d, R0, value);
2231 count += 1;
2232 } else {
2233 lui(d, split_low(value >> 16));
2234 count += 1;
2235 if (split_low(value)) {
2236 ori(d, d, split_low(value));
2237 count += 1;
2238 }
2239 }
2240 } else if (hi == 0) { // hardware zero-extends to upper 32
2241 ori(d, R0, julong(value) >> 16);
2242 dsll(d, d, 16);
2243 count += 2;
2244 if (split_low(value)) {
2245 ori(d, d, split_low(value));
2246 count += 1;
2247 }
2248 } else {
2249 tty->print_cr("value = 0x%x", value);
2250 guarantee(false, "Not supported yet !");
2251 }
2253 for (count; count < 3; count++) {
2254 nop();
2255 }
2256 }
2258 void MacroAssembler::patchable_call32(Register d, jlong value) {
2259 assert_not_delayed();
2261 int hi = (int)(value >> 32);
2262 int lo = (int)(value & ~0);
2264 int count = 0;
2266 if (value == lo) { // 32-bit integer
2267 if (is_simm16(value)) {
2268 daddiu(d, R0, value);
2269 count += 1;
2270 } else {
2271 lui(d, split_low(value >> 16));
2272 count += 1;
2273 if (split_low(value)) {
2274 ori(d, d, split_low(value));
2275 count += 1;
2276 }
2277 }
2278 } else {
2279 tty->print_cr("value = 0x%x", value);
2280 guarantee(false, "Not supported yet !");
2281 }
2283 for (count; count < 2; count++) {
2284 nop();
2285 }
2286 }
2288 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
2289 assert(UseCompressedClassPointers, "should only be used for compressed header");
2290 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
2292 int klass_index = oop_recorder()->find_index(k);
2293 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
2294 long narrowKlass = (long)Klass::encode_klass(k);
2296 relocate(rspec, Assembler::narrow_oop_operand);
2297 patchable_set48(dst, narrowKlass);
2298 }
2301 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
2302 assert(UseCompressedOops, "should only be used for compressed header");
2303 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
2305 int oop_index = oop_recorder()->find_index(obj);
2306 RelocationHolder rspec = oop_Relocation::spec(oop_index);
2308 relocate(rspec, Assembler::narrow_oop_operand);
2309 patchable_set48(dst, oop_index);
2310 }
2312 void MacroAssembler::li64(Register rd, long imm) {
2313 assert_not_delayed();
2314 lui(rd, imm >> 48);
2315 ori(rd, rd, split_low(imm >> 32));
2316 dsll(rd, rd, 16);
2317 ori(rd, rd, split_low(imm >> 16));
2318 dsll(rd, rd, 16);
2319 ori(rd, rd, split_low(imm));
2320 }
2322 void MacroAssembler::li48(Register rd, long imm) {
2323 assert_not_delayed();
2324 assert(is_simm16(imm >> 32), "Not a 48-bit address");
2325 lui(rd, imm >> 32);
2326 ori(rd, rd, split_low(imm >> 16));
2327 dsll(rd, rd, 16);
2328 ori(rd, rd, split_low(imm));
2329 }
2330 #endif
2331 // NOTE: i dont push eax as i486.
2332 // the x86 save eax for it use eax as the jump register
2333 void MacroAssembler::verify_oop(Register reg, const char* s) {
2334 /*
2335 if (!VerifyOops) return;
2337 // Pass register number to verify_oop_subroutine
2338 char* b = new char[strlen(s) + 50];
2339 sprintf(b, "verify_oop: %s: %s", reg->name(), s);
2340 push(rax); // save rax,
2341 push(reg); // pass register argument
2342 ExternalAddress buffer((address) b);
2343 // avoid using pushptr, as it modifies scratch registers
2344 // and our contract is not to modify anything
2345 movptr(rax, buffer.addr());
2346 push(rax);
2347 // call indirectly to solve generation ordering problem
2348 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2349 call(rax);
2350 */
2351 if (!VerifyOops) return;
2352 const char * b = NULL;
2353 stringStream ss;
2354 ss.print("verify_oop: %s: %s", reg->name(), s);
2355 b = code_string(ss.as_string());
2356 #ifdef _LP64
2357 pushad();
2358 move(A1, reg);
2359 li(A0, (long)b);
2360 li(AT, (long)StubRoutines::verify_oop_subroutine_entry_address());
2361 ld(T9, AT, 0);
2362 jalr(T9);
2363 delayed()->nop();
2364 popad();
2365 #else
2366 // Pass register number to verify_oop_subroutine
2367 sw(T0, SP, - wordSize);
2368 sw(T1, SP, - 2*wordSize);
2369 sw(RA, SP, - 3*wordSize);
2370 sw(A0, SP ,- 4*wordSize);
2371 sw(A1, SP ,- 5*wordSize);
2372 sw(AT, SP ,- 6*wordSize);
2373 sw(T9, SP ,- 7*wordSize);
2374 addiu(SP, SP, - 7 * wordSize);
2375 move(A1, reg);
2376 li(A0, (long)b);
2377 // call indirectly to solve generation ordering problem
2378 li(AT, (long)StubRoutines::verify_oop_subroutine_entry_address());
2379 lw(T9, AT, 0);
2380 jalr(T9);
2381 delayed()->nop();
2382 lw(T0, SP, 6* wordSize);
2383 lw(T1, SP, 5* wordSize);
2384 lw(RA, SP, 4* wordSize);
2385 lw(A0, SP, 3* wordSize);
2386 lw(A1, SP, 2* wordSize);
2387 lw(AT, SP, 1* wordSize);
2388 lw(T9, SP, 0* wordSize);
2389 addiu(SP, SP, 7 * wordSize);
2390 #endif
2391 }
2394 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
2395 if (!VerifyOops) {
2396 nop();
2397 return;
2398 }
2399 // Pass register number to verify_oop_subroutine
2400 const char * b = NULL;
2401 stringStream ss;
2402 ss.print("verify_oop_addr: %s", s);
2403 b = code_string(ss.as_string());
2405 st_ptr(T0, SP, - wordSize);
2406 st_ptr(T1, SP, - 2*wordSize);
2407 st_ptr(RA, SP, - 3*wordSize);
2408 st_ptr(A0, SP, - 4*wordSize);
2409 st_ptr(A1, SP, - 5*wordSize);
2410 st_ptr(AT, SP, - 6*wordSize);
2411 st_ptr(T9, SP, - 7*wordSize);
2412 ld_ptr(A1, addr); // addr may use SP, so load from it before change SP
2413 addiu(SP, SP, - 7 * wordSize);
2415 li(A0, (long)b);
2416 // call indirectly to solve generation ordering problem
2417 li(AT, (long)StubRoutines::verify_oop_subroutine_entry_address());
2418 ld_ptr(T9, AT, 0);
2419 jalr(T9);
2420 delayed()->nop();
2421 ld_ptr(T0, SP, 6* wordSize);
2422 ld_ptr(T1, SP, 5* wordSize);
2423 ld_ptr(RA, SP, 4* wordSize);
2424 ld_ptr(A0, SP, 3* wordSize);
2425 ld_ptr(A1, SP, 2* wordSize);
2426 ld_ptr(AT, SP, 1* wordSize);
2427 ld_ptr(T9, SP, 0* wordSize);
2428 addiu(SP, SP, 7 * wordSize);
2429 }
2431 // used registers : T0, T1
2432 void MacroAssembler::verify_oop_subroutine() {
2433 // RA: ra
2434 // A0: char* error message
2435 // A1: oop object to verify
2437 Label exit, error;
2438 // increment counter
2439 li(T0, (long)StubRoutines::verify_oop_count_addr());
2440 lw(AT, T0, 0);
2441 #ifdef _LP64
2442 daddi(AT, AT, 1);
2443 #else
2444 addi(AT, AT, 1);
2445 #endif
2446 sw(AT, T0, 0);
2448 // make sure object is 'reasonable'
2449 beq(A1, R0, exit); // if obj is NULL it is ok
2450 delayed()->nop();
2452 // Check if the oop is in the right area of memory
2453 //const int oop_mask = Universe::verify_oop_mask();
2454 //const int oop_bits = Universe::verify_oop_bits();
2455 const uintptr_t oop_mask = Universe::verify_oop_mask();
2456 const uintptr_t oop_bits = Universe::verify_oop_bits();
2457 li(AT, oop_mask);
2458 andr(T0, A1, AT);
2459 li(AT, oop_bits);
2460 bne(T0, AT, error);
2461 delayed()->nop();
2463 // make sure klass is 'reasonable'
2464 //add for compressedoops
2465 reinit_heapbase();
2466 //add for compressedoops
2467 load_klass(T0, A1);
2468 beq(T0, R0, error); // if klass is NULL it is broken
2469 delayed()->nop();
2470 #if 0
2471 //FIXME:wuhui.
2472 // Check if the klass is in the right area of memory
2473 //const int klass_mask = Universe::verify_klass_mask();
2474 //const int klass_bits = Universe::verify_klass_bits();
2475 const uintptr_t klass_mask = Universe::verify_klass_mask();
2476 const uintptr_t klass_bits = Universe::verify_klass_bits();
2478 li(AT, klass_mask);
2479 andr(T1, T0, AT);
2480 li(AT, klass_bits);
2481 bne(T1, AT, error);
2482 delayed()->nop();
2483 // make sure klass' klass is 'reasonable'
2484 //add for compressedoops
2485 load_klass(T0, T0);
2486 beq(T0, R0, error); // if klass' klass is NULL it is broken
2487 delayed()->nop();
2489 li(AT, klass_mask);
2490 andr(T1, T0, AT);
2491 li(AT, klass_bits);
2492 bne(T1, AT, error);
2493 delayed()->nop(); // if klass not in right area of memory it is broken too.
2494 #endif
2495 // return if everything seems ok
2496 bind(exit);
2498 jr(RA);
2499 delayed()->nop();
2501 // handle errors
2502 bind(error);
2503 pushad();
2504 #ifndef _LP64
2505 addi(SP, SP, (-1) * wordSize);
2506 #endif
2507 call(CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
2508 delayed()->nop();
2509 #ifndef _LP64
2510 addiu(SP, SP, 1 * wordSize);
2511 #endif
2512 popad();
2513 jr(RA);
2514 delayed()->nop();
2515 }
2517 void MacroAssembler::verify_tlab(Register t1, Register t2) {
2518 #ifdef ASSERT
2519 assert_different_registers(t1, t2, AT);
2520 if (UseTLAB && VerifyOops) {
2521 Label next, ok;
2523 get_thread(t1);
2525 ld_ptr(t2, t1, in_bytes(JavaThread::tlab_top_offset()));
2526 ld_ptr(AT, t1, in_bytes(JavaThread::tlab_start_offset()));
2527 sltu(AT, t2, AT);
2528 beq(AT, R0, next);
2529 delayed()->nop();
2531 stop("assert(top >= start)");
2533 bind(next);
2534 ld_ptr(AT, t1, in_bytes(JavaThread::tlab_end_offset()));
2535 sltu(AT, AT, t2);
2536 beq(AT, R0, ok);
2537 delayed()->nop();
2539 stop("assert(top <= end)");
2541 bind(ok);
2543 }
2544 #endif
2545 }
2546 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
2547 Register tmp,
2548 int offset) {
2549 intptr_t value = *delayed_value_addr;
2550 if (value != 0)
2551 return RegisterOrConstant(value + offset);
2552 AddressLiteral a(delayed_value_addr);
2553 // load indirectly to solve generation ordering problem
2554 //movptr(tmp, ExternalAddress((address) delayed_value_addr));
2555 //ld(tmp, a);
2556 if (offset != 0)
2557 daddi(tmp,tmp, offset);
2559 return RegisterOrConstant(tmp);
2560 }
2562 void MacroAssembler::hswap(Register reg) {
2563 //short
2564 //andi(reg, reg, 0xffff);
2565 srl(AT, reg, 8);
2566 sll(reg, reg, 24);
2567 sra(reg, reg, 16);
2568 orr(reg, reg, AT);
2569 }
2571 void MacroAssembler::huswap(Register reg) {
2572 #ifdef _LP64
2573 dsrl(AT, reg, 8);
2574 dsll(reg, reg, 24);
2575 dsrl(reg, reg, 16);
2576 orr(reg, reg, AT);
2577 andi(reg, reg, 0xffff);
2578 #else
2579 //andi(reg, reg, 0xffff);
2580 srl(AT, reg, 8);
2581 sll(reg, reg, 24);
2582 srl(reg, reg, 16);
2583 orr(reg, reg, AT);
2584 #endif
2585 }
2587 // something funny to do this will only one more register AT
2588 // 32 bits
2589 void MacroAssembler::swap(Register reg) {
2590 srl(AT, reg, 8);
2591 sll(reg, reg, 24);
2592 orr(reg, reg, AT);
2593 //reg : 4 1 2 3
2594 srl(AT, AT, 16);
2595 xorr(AT, AT, reg);
2596 andi(AT, AT, 0xff);
2597 //AT : 0 0 0 1^3);
2598 xorr(reg, reg, AT);
2599 //reg : 4 1 2 1
2600 sll(AT, AT, 16);
2601 xorr(reg, reg, AT);
2602 //reg : 4 3 2 1
2603 }
2605 #ifdef _LP64
2607 /* do 32-bit CAS using MIPS64 lld/scd
2609 Jin: cas_int should only compare 32-bits of the memory value.
2610 However, lld/scd will do 64-bit operation, which violates the intention of cas_int.
2611 To simulate a 32-bit atomic operation, the value loaded with LLD should be split into
2612 tow halves, and only the low-32 bits is compared. If equals, the low-32 bits of newval,
2613 plus the high-32 bits or memory value, are stored togethor with SCD.
2615 Example:
2617 double d = 3.1415926;
2618 System.err.println("hello" + d);
2620 sun.misc.FloatingDecimal$1.<init>()
2621 |
2622 `- java.util.concurrent.atomic.AtomicInteger::compareAndSet()
2624 38 cas_int [a7a7|J] [a0|I] [a6|I]
2625 // a0: 0xffffffffe8ea9f63 pc: 0x55647f3354
2626 // a6: 0x4ab325aa
2628 again:
2629 0x00000055647f3c5c: lld at, 0x0(a7) ; 64-bit load, "0xe8ea9f63"
2631 0x00000055647f3c60: sll t9, at, 0 ; t9: low-32 bits (sign extended)
2632 0x00000055647f3c64: dsrl32 t8, at, 0 ; t8: high-32 bits
2633 0x00000055647f3c68: dsll32 t8, t8, 0
2634 0x00000055647f3c6c: bne t9, a0, 0x00000055647f3c9c ; goto nequal
2635 0x00000055647f3c70: sll zero, zero, 0
2637 0x00000055647f3c74: ori v1, zero, 0xffffffff ; v1: low-32 bits of newval (sign unextended)
2638 0x00000055647f3c78: dsll v1, v1, 16 ; v1 = a6 & 0xFFFFFFFF;
2639 0x00000055647f3c7c: ori v1, v1, 0xffffffff
2640 0x00000055647f3c80: and v1, a6, v1
2641 0x00000055647f3c84: or at, t8, v1
2642 0x00000055647f3c88: scd at, 0x0(a7)
2643 0x00000055647f3c8c: beq at, zero, 0x00000055647f3c5c ; goto again
2644 0x00000055647f3c90: sll zero, zero, 0
2645 0x00000055647f3c94: beq zero, zero, 0x00000055647f45ac ; goto done
2646 0x00000055647f3c98: sll zero, zero, 0
2647 nequal:
2648 0x00000055647f45a4: dadd a0, t9, zero
2649 0x00000055647f45a8: dadd at, zero, zero
2650 done:
2651 */
2653 void MacroAssembler::cmpxchg32(Register x_reg, Address dest, Register c_reg) {
2654 /* 2012/11/11 Jin: MIPS64 can use ll/sc for 32-bit atomic memory access */
2655 Label done, again, nequal;
2657 bind(again);
2659 if(!Use3A2000) sync();
2660 ll(AT, dest);
2661 bne(AT, c_reg, nequal);
2662 delayed()->nop();
2664 move(AT, x_reg);
2665 sc(AT, dest);
2666 beq(AT, R0, again);
2667 delayed()->nop();
2668 b(done);
2669 delayed()->nop();
2671 // not xchged
2672 bind(nequal);
2673 sync();
2674 move(c_reg, AT);
2675 move(AT, R0);
2677 bind(done);
2678 }
2679 #endif // cmpxchg32
2681 void MacroAssembler::cmpxchg(Register x_reg, Address dest, Register c_reg) {
2682 Label done, again, nequal;
2684 bind(again);
2685 #ifdef _LP64
2686 if(!Use3A2000) sync();
2687 lld(AT, dest);
2688 #else
2689 if(!Use3A2000) sync();
2690 ll(AT, dest);
2691 #endif
2692 bne(AT, c_reg, nequal);
2693 delayed()->nop();
2695 move(AT, x_reg);
2696 #ifdef _LP64
2697 scd(AT, dest);
2698 #else
2699 sc(AT, dest);
2700 #endif
2701 beq(AT, R0, again);
2702 delayed()->nop();
2703 b(done);
2704 delayed()->nop();
2706 // not xchged
2707 bind(nequal);
2708 sync();
2709 move(c_reg, AT);
2710 move(AT, R0);
2712 bind(done);
2713 }
2715 void MacroAssembler::cmpxchg8(Register x_regLo, Register x_regHi, Address dest, Register c_regLo, Register c_regHi) {
2716 Label done, again, nequal;
2718 Register x_reg = x_regLo;
2719 dsll32(x_regHi, x_regHi, 0);
2720 dsll32(x_regLo, x_regLo, 0);
2721 dsrl32(x_regLo, x_regLo, 0);
2722 orr(x_reg, x_regLo, x_regHi);
2724 Register c_reg = c_regLo;
2725 dsll32(c_regHi, c_regHi, 0);
2726 dsll32(c_regLo, c_regLo, 0);
2727 dsrl32(c_regLo, c_regLo, 0);
2728 orr(c_reg, c_regLo, c_regHi);
2730 bind(again);
2732 if(!Use3A2000) sync();
2733 lld(AT, dest);
2734 bne(AT, c_reg, nequal);
2735 delayed()->nop();
2737 //move(AT, x_reg);
2738 dadd(AT, x_reg, R0);
2739 scd(AT, dest);
2740 beq(AT, R0, again);
2741 delayed()->nop();
2742 b(done);
2743 delayed()->nop();
2745 // not xchged
2746 bind(nequal);
2747 sync();
2748 //move(c_reg, AT);
2749 //move(AT, R0);
2750 dadd(c_reg, AT, R0);
2751 dadd(AT, R0, R0);
2752 bind(done);
2753 }
2755 // be sure the three register is different
2756 void MacroAssembler::rem_s(FloatRegister fd, FloatRegister fs, FloatRegister ft, FloatRegister tmp) {
2757 assert_different_registers(tmp, fs, ft);
2758 div_s(tmp, fs, ft);
2759 trunc_l_s(tmp, tmp);
2760 cvt_s_l(tmp, tmp);
2761 mul_s(tmp, tmp, ft);
2762 sub_s(fd, fs, tmp);
2763 }
2765 // be sure the three register is different
2766 void MacroAssembler::rem_d(FloatRegister fd, FloatRegister fs, FloatRegister ft, FloatRegister tmp) {
2767 assert_different_registers(tmp, fs, ft);
2768 div_d(tmp, fs, ft);
2769 trunc_l_d(tmp, tmp);
2770 cvt_d_l(tmp, tmp);
2771 mul_d(tmp, tmp, ft);
2772 sub_d(fd, fs, tmp);
2773 }
2775 // Fast_Lock and Fast_Unlock used by C2
2777 // Because the transitions from emitted code to the runtime
2778 // monitorenter/exit helper stubs are so slow it's critical that
2779 // we inline both the stack-locking fast-path and the inflated fast path.
2780 //
2781 // See also: cmpFastLock and cmpFastUnlock.
2782 //
2783 // What follows is a specialized inline transliteration of the code
2784 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2785 // another option would be to emit TrySlowEnter and TrySlowExit methods
2786 // at startup-time. These methods would accept arguments as
2787 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2788 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2789 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2790 // In practice, however, the # of lock sites is bounded and is usually small.
2791 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2792 // if the processor uses simple bimodal branch predictors keyed by EIP
2793 // Since the helper routines would be called from multiple synchronization
2794 // sites.
2795 //
2796 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2797 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2798 // to those specialized methods. That'd give us a mostly platform-independent
2799 // implementation that the JITs could optimize and inline at their pleasure.
2800 // Done correctly, the only time we'd need to cross to native could would be
2801 // to park() or unpark() threads. We'd also need a few more unsafe operators
2802 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2803 // (b) explicit barriers or fence operations.
2804 //
2805 // TODO:
2806 //
2807 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2808 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2809 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2810 // the lock operators would typically be faster than reifying Self.
2811 //
2812 // * Ideally I'd define the primitives as:
2813 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2814 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2815 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
2816 // Instead, we're stuck with a rather awkward and brittle register assignments below.
2817 // Furthermore the register assignments are overconstrained, possibly resulting in
2818 // sub-optimal code near the synchronization site.
2819 //
2820 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
2821 // Alternately, use a better sp-proximity test.
2822 //
2823 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
2824 // Either one is sufficient to uniquely identify a thread.
2825 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
2826 //
2827 // * Intrinsify notify() and notifyAll() for the common cases where the
2828 // object is locked by the calling thread but the waitlist is empty.
2829 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
2830 //
2831 // * use jccb and jmpb instead of jcc and jmp to improve code density.
2832 // But beware of excessive branch density on AMD Opterons.
2833 //
2834 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
2835 // or failure of the fast-path. If the fast-path fails then we pass
2836 // control to the slow-path, typically in C. In Fast_Lock and
2837 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
2838 // will emit a conditional branch immediately after the node.
2839 // So we have branches to branches and lots of ICC.ZF games.
2840 // Instead, it might be better to have C2 pass a "FailureLabel"
2841 // into Fast_Lock and Fast_Unlock. In the case of success, control
2842 // will drop through the node. ICC.ZF is undefined at exit.
2843 // In the case of failure, the node will branch directly to the
2844 // FailureLabel
2847 // obj: object to lock
2848 // box: on-stack box address (displaced header location) - KILLED
2849 // rax,: tmp -- KILLED
2850 // scr: tmp -- KILLED
2851 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg, Register scrReg) {
2853 // Ensure the register assignents are disjoint
2854 guarantee (objReg != boxReg, "") ;
2855 guarantee (objReg != tmpReg, "") ;
2856 guarantee (objReg != scrReg, "") ;
2857 guarantee (boxReg != tmpReg, "") ;
2858 guarantee (boxReg != scrReg, "") ;
2861 block_comment("FastLock");
2862 /*
2863 move(AT, 0x0);
2864 return;
2865 */
2866 if (PrintBiasedLockingStatistics) {
2867 push(tmpReg);
2868 atomic_inc32((address)BiasedLocking::total_entry_count_addr(), 1, AT, tmpReg);
2869 pop(tmpReg);
2870 }
2872 if (EmitSync & 1) {
2873 move(AT, 0x0);
2874 return;
2875 } else
2876 if (EmitSync & 2) {
2877 Label DONE_LABEL ;
2878 if (UseBiasedLocking) {
2879 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
2880 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL);
2881 }
2883 ld(tmpReg, Address(objReg, 0)) ; // fetch markword
2884 ori(tmpReg, tmpReg, 0x1);
2885 sd(tmpReg, Address(boxReg, 0)); // Anticipate successful CAS
2887 cmpxchg(boxReg, Address(objReg, 0), tmpReg); // Updates tmpReg
2888 bne(AT, R0, DONE_LABEL);
2889 delayed()->nop();
2891 // Recursive locking
2892 dsubu(tmpReg, tmpReg, SP);
2893 li(AT, (7 - os::vm_page_size() ));
2894 andr(tmpReg, tmpReg, AT);
2895 sd(tmpReg, Address(boxReg, 0));
2896 bind(DONE_LABEL) ;
2897 } else {
2898 // Possible cases that we'll encounter in fast_lock
2899 // ------------------------------------------------
2900 // * Inflated
2901 // -- unlocked
2902 // -- Locked
2903 // = by self
2904 // = by other
2905 // * biased
2906 // -- by Self
2907 // -- by other
2908 // * neutral
2909 // * stack-locked
2910 // -- by self
2911 // = sp-proximity test hits
2912 // = sp-proximity test generates false-negative
2913 // -- by other
2914 //
2916 Label IsInflated, DONE_LABEL, PopDone ;
2918 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
2919 // order to reduce the number of conditional branches in the most common cases.
2920 // Beware -- there's a subtle invariant that fetch of the markword
2921 // at [FETCH], below, will never observe a biased encoding (*101b).
2922 // If this invariant is not held we risk exclusion (safety) failure.
2923 if (UseBiasedLocking && !UseOptoBiasInlining) {
2924 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL);
2925 }
2927 ld(tmpReg, Address(objReg, 0)) ; //Fetch the markword of the object.
2928 andi(AT, tmpReg, markOopDesc::monitor_value);
2929 bne(AT, R0, IsInflated); // inflated vs stack-locked|neutral|bias
2930 delayed()->nop();
2932 // Attempt stack-locking ...
2933 ori (tmpReg, tmpReg, markOopDesc::unlocked_value);
2934 sd(tmpReg, Address(boxReg, 0)); // Anticipate successful CAS
2935 //if (os::is_MP()) {
2936 // sync();
2937 //}
2939 cmpxchg(boxReg, Address(objReg, 0), tmpReg); // Updates tmpReg
2940 //AT == 1: unlocked
2942 if (PrintBiasedLockingStatistics) {
2943 Label L;
2944 beq(AT, R0, L);
2945 delayed()->nop();
2946 push(T0);
2947 push(T1);
2948 atomic_inc32((address)BiasedLocking::fast_path_entry_count_addr(), 1, T0, T1);
2949 pop(T1);
2950 pop(T0);
2951 bind(L);
2952 }
2953 bne(AT, R0, DONE_LABEL);
2954 delayed()->nop();
2956 // Recursive locking
2957 // The object is stack-locked: markword contains stack pointer to BasicLock.
2958 // Locked by current thread if difference with current SP is less than one page.
2959 dsubu(tmpReg, tmpReg, SP);
2960 li(AT, 7 - os::vm_page_size() );
2961 andr(tmpReg, tmpReg, AT);
2962 sd(tmpReg, Address(boxReg, 0));
2963 if (PrintBiasedLockingStatistics) {
2964 Label L;
2965 // tmpReg == 0 => BiasedLocking::_fast_path_entry_count++
2966 bne(tmpReg, R0, L);
2967 delayed()->nop();
2968 push(T0);
2969 push(T1);
2970 atomic_inc32((address)BiasedLocking::fast_path_entry_count_addr(), 1, T0, T1);
2971 pop(T1);
2972 pop(T0);
2973 bind(L);
2974 }
2975 sltiu(AT, tmpReg, 1); /* AT = (tmpReg == 0) ? 1 : 0 */
2977 b(DONE_LABEL) ;
2978 delayed()->nop();
2980 bind(IsInflated) ;
2981 // The object's monitor m is unlocked iff m->owner == NULL,
2982 // otherwise m->owner may contain a thread or a stack address.
2984 // TODO: someday avoid the ST-before-CAS penalty by
2985 // relocating (deferring) the following ST.
2986 // We should also think about trying a CAS without having
2987 // fetched _owner. If the CAS is successful we may
2988 // avoid an RTO->RTS upgrade on the $line.
2989 // Without cast to int32_t a movptr will destroy r10 which is typically obj
2990 li(AT, (int32_t)intptr_t(markOopDesc::unused_mark()));
2991 sd(AT, Address(boxReg, 0));
2993 move(boxReg, tmpReg) ;
2994 ld(tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
2995 // if (m->owner != 0) => AT = 0, goto slow path.
2996 move(AT, R0);
2997 bne(tmpReg, R0, DONE_LABEL);
2998 delayed()->nop();
3000 #ifndef OPT_THREAD
3001 get_thread (TREG) ;
3002 #endif
3003 // It's inflated and appears unlocked
3004 //if (os::is_MP()) {
3005 // sync();
3006 //}
3007 cmpxchg(TREG, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), tmpReg) ;
3008 // Intentional fall-through into DONE_LABEL ...
3011 // DONE_LABEL is a hot target - we'd really like to place it at the
3012 // start of cache line by padding with NOPs.
3013 // See the AMD and Intel software optimization manuals for the
3014 // most efficient "long" NOP encodings.
3015 // Unfortunately none of our alignment mechanisms suffice.
3016 bind(DONE_LABEL);
3018 // At DONE_LABEL the AT is set as follows ...
3019 // Fast_Unlock uses the same protocol.
3020 // AT == 1 -> Success
3021 // AT == 0 -> Failure - force control through the slow-path
3023 // Avoid branch-to-branch on AMD processors
3024 // This appears to be superstition.
3025 if (EmitSync & 32) nop() ;
3027 }
3028 }
3030 // obj: object to unlock
3031 // box: box address (displaced header location), killed. Must be EAX.
3032 // rbx,: killed tmp; cannot be obj nor box.
3033 //
3034 // Some commentary on balanced locking:
3035 //
3036 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3037 // Methods that don't have provably balanced locking are forced to run in the
3038 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3039 // The interpreter provides two properties:
3040 // I1: At return-time the interpreter automatically and quietly unlocks any
3041 // objects acquired the current activation (frame). Recall that the
3042 // interpreter maintains an on-stack list of locks currently held by
3043 // a frame.
3044 // I2: If a method attempts to unlock an object that is not held by the
3045 // the frame the interpreter throws IMSX.
3046 //
3047 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3048 // B() doesn't have provably balanced locking so it runs in the interpreter.
3049 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3050 // is still locked by A().
3051 //
3052 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3053 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3054 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3055 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3057 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg) {
3059 guarantee (objReg != boxReg, "") ;
3060 guarantee (objReg != tmpReg, "") ;
3061 guarantee (boxReg != tmpReg, "") ;
3065 block_comment("FastUnlock");
3068 if (EmitSync & 4) {
3069 // Disable - inhibit all inlining. Force control through the slow-path
3070 move(AT, 0x0);
3071 return;
3072 } else
3073 if (EmitSync & 8) {
3074 Label DONE_LABEL ;
3075 if (UseBiasedLocking) {
3076 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3077 }
3078 // classic stack-locking code ...
3079 ld(tmpReg, Address(boxReg, 0)) ;
3080 beq(tmpReg, R0, DONE_LABEL) ;
3081 move(AT, 0x1); // delay slot
3083 cmpxchg(tmpReg, Address(objReg, 0), boxReg); // Uses EAX which is box
3084 bind(DONE_LABEL);
3085 } else {
3086 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3088 // Critically, the biased locking test must have precedence over
3089 // and appear before the (box->dhw == 0) recursive stack-lock test.
3090 if (UseBiasedLocking && !UseOptoBiasInlining) {
3091 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3092 }
3094 ld(AT, Address(boxReg, 0)) ; // Examine the displaced header
3095 beq(AT, R0, DONE_LABEL) ; // 0 indicates recursive stack-lock
3096 delayed()->daddiu(AT, R0, 0x1);
3098 ld(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3099 andi(AT, tmpReg, markOopDesc::monitor_value) ; // Inflated?
3100 beq(AT, R0, Stacked) ; // Inflated?
3101 delayed()->nop();
3103 bind(Inflated) ;
3104 // It's inflated.
3105 // Despite our balanced locking property we still check that m->_owner == Self
3106 // as java routines or native JNI code called by this thread might
3107 // have released the lock.
3108 // Refer to the comments in synchronizer.cpp for how we might encode extra
3109 // state in _succ so we can avoid fetching EntryList|cxq.
3110 //
3111 // I'd like to add more cases in fast_lock() and fast_unlock() --
3112 // such as recursive enter and exit -- but we have to be wary of
3113 // I$ bloat, T$ effects and BP$ effects.
3114 //
3115 // If there's no contention try a 1-0 exit. That is, exit without
3116 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3117 // we detect and recover from the race that the 1-0 exit admits.
3118 //
3119 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3120 // before it STs null into _owner, releasing the lock. Updates
3121 // to data protected by the critical section must be visible before
3122 // we drop the lock (and thus before any other thread could acquire
3123 // the lock and observe the fields protected by the lock).
3124 // IA32's memory-model is SPO, so STs are ordered with respect to
3125 // each other and there's no need for an explicit barrier (fence).
3126 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3127 #ifndef OPT_THREAD
3128 get_thread (TREG) ;
3129 #endif
3131 // It's inflated
3132 ld(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3133 xorr(boxReg, boxReg, TREG);
3135 ld(AT, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3136 orr(boxReg, boxReg, AT);
3138 move(AT, R0);
3139 bne(boxReg, R0, DONE_LABEL);
3140 delayed()->nop();
3142 ld(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3143 ld(AT, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3144 orr(boxReg, boxReg, AT);
3146 move(AT, R0);
3147 bne(boxReg, R0, DONE_LABEL);
3148 delayed()->nop();
3150 sync();
3151 sd(R0, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3152 move(AT, 0x1);
3153 b(DONE_LABEL);
3154 delayed()->nop();
3156 bind (Stacked);
3157 ld(tmpReg, Address(boxReg, 0)) ;
3158 //if (os::is_MP()) { sync(); }
3159 cmpxchg(tmpReg, Address(objReg, 0), boxReg);
3161 if (EmitSync & 65536) {
3162 bind (CheckSucc);
3163 }
3165 bind(DONE_LABEL);
3167 // Avoid branch to branch on AMD processors
3168 if (EmitSync & 32768) { nop() ; }
3169 }
3170 }
3172 void MacroAssembler::align(int modulus) {
3173 while (offset() % modulus != 0) nop();
3174 }
3177 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
3178 //Unimplemented();
3179 }
3181 #ifdef _LP64
3182 Register caller_saved_registers[] = {AT, V0, V1, A0, A1, A2, A3, A4, A5, A6, A7, T0, T1, T2, T3, T8, T9, GP, RA, FP};
3184 /* FIXME: Jin: In MIPS64, F0~23 are all caller-saved registers */
3185 FloatRegister caller_saved_fpu_registers[] = {F0, F12, F13};
3186 #else
3187 Register caller_saved_registers[] = {AT, V0, V1, A0, A1, A2, A3, T4, T5, T6, T7, T0, T1, T2, T3, T8, T9, GP, RA, FP};
3189 Register caller_saved_fpu_registers[] = {};
3190 #endif
3192 //We preserve all caller-saved register
3193 void MacroAssembler::pushad(){
3194 int i;
3196 /* Fixed-point registers */
3197 int len = sizeof(caller_saved_registers) / sizeof(caller_saved_registers[0]);
3198 daddi(SP, SP, -1 * len * wordSize);
3199 for (i = 0; i < len; i++)
3200 {
3201 #ifdef _LP64
3202 sd(caller_saved_registers[i], SP, (len - i - 1) * wordSize);
3203 #else
3204 sw(caller_saved_registers[i], SP, (len - i - 1) * wordSize);
3205 #endif
3206 }
3208 /* Floating-point registers */
3209 len = sizeof(caller_saved_fpu_registers) / sizeof(caller_saved_fpu_registers[0]);
3210 daddi(SP, SP, -1 * len * wordSize);
3211 for (i = 0; i < len; i++)
3212 {
3213 #ifdef _LP64
3214 sdc1(caller_saved_fpu_registers[i], SP, (len - i - 1) * wordSize);
3215 #else
3216 swc1(caller_saved_fpu_registers[i], SP, (len - i - 1) * wordSize);
3217 #endif
3218 }
3219 };
3221 void MacroAssembler::popad(){
3222 int i;
3224 /* Floating-point registers */
3225 int len = sizeof(caller_saved_fpu_registers) / sizeof(caller_saved_fpu_registers[0]);
3226 for (i = 0; i < len; i++)
3227 {
3228 #ifdef _LP64
3229 ldc1(caller_saved_fpu_registers[i], SP, (len - i - 1) * wordSize);
3230 #else
3231 lwc1(caller_saved_fpu_registers[i], SP, (len - i - 1) * wordSize);
3232 #endif
3233 }
3234 daddi(SP, SP, len * wordSize);
3236 /* Fixed-point registers */
3237 len = sizeof(caller_saved_registers) / sizeof(caller_saved_registers[0]);
3238 for (i = 0; i < len; i++)
3239 {
3240 #ifdef _LP64
3241 ld(caller_saved_registers[i], SP, (len - i - 1) * wordSize);
3242 #else
3243 lw(caller_saved_registers[i], SP, (len - i - 1) * wordSize);
3244 #endif
3245 }
3246 daddi(SP, SP, len * wordSize);
3247 };
3249 void MacroAssembler::push2(Register reg1, Register reg2) {
3250 #ifdef _LP64
3251 daddi(SP, SP, -16);
3252 sd(reg2, SP, 0);
3253 sd(reg1, SP, 8);
3254 #else
3255 addi(SP, SP, -8);
3256 sw(reg2, SP, 0);
3257 sw(reg1, SP, 4);
3258 #endif
3259 }
3261 void MacroAssembler::pop2(Register reg1, Register reg2) {
3262 #ifdef _LP64
3263 ld(reg1, SP, 0);
3264 ld(reg2, SP, 8);
3265 daddi(SP, SP, 16);
3266 #else
3267 lw(reg1, SP, 0);
3268 lw(reg2, SP, 4);
3269 addi(SP, SP, 8);
3270 #endif
3271 }
3273 //for UseCompressedOops Option
3274 void MacroAssembler::load_klass(Register dst, Register src) {
3275 #ifdef _LP64
3276 if(UseCompressedClassPointers){
3277 lwu(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3278 decode_klass_not_null(dst);
3279 } else
3280 #endif
3281 ld(dst, src, oopDesc::klass_offset_in_bytes());
3282 }
3284 void MacroAssembler::store_klass(Register dst, Register src) {
3285 #ifdef _LP64
3286 if(UseCompressedClassPointers){
3287 encode_klass_not_null(src);
3288 sw(src, dst, oopDesc::klass_offset_in_bytes());
3289 } else {
3290 #endif
3291 sd(src, dst, oopDesc::klass_offset_in_bytes());
3292 }
3293 }
3295 void MacroAssembler::load_prototype_header(Register dst, Register src) {
3296 load_klass(dst, src);
3297 ld(dst, Address(dst, Klass::prototype_header_offset()));
3298 }
3300 #ifdef _LP64
3301 void MacroAssembler::store_klass_gap(Register dst, Register src) {
3302 if (UseCompressedClassPointers) {
3303 sw(src, dst, oopDesc::klass_gap_offset_in_bytes());
3304 }
3305 }
3307 void MacroAssembler::load_heap_oop(Register dst, Address src) {
3308 if(UseCompressedOops){
3309 lwu(dst, src);
3310 decode_heap_oop(dst);
3311 } else{
3312 ld(dst, src);
3313 }
3314 }
3316 void MacroAssembler::store_heap_oop(Address dst, Register src){
3317 if(UseCompressedOops){
3318 assert(!dst.uses(src), "not enough registers");
3319 encode_heap_oop(src);
3320 sw(src, dst);
3321 } else{
3322 sd(src, dst);
3323 }
3324 }
3326 #ifdef ASSERT
3327 void MacroAssembler::verify_heapbase(const char* msg) {
3328 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
3329 assert (Universe::heap() != NULL, "java heap should be initialized");
3330 }
3331 #endif
3334 // Algorithm must match oop.inline.hpp encode_heap_oop.
3335 void MacroAssembler::encode_heap_oop(Register r) {
3336 #ifdef ASSERT
3337 verify_heapbase("MacroAssembler::encode_heap_oop:heap base corrupted?");
3338 #endif
3339 verify_oop(r, "broken oop in encode_heap_oop");
3340 if (Universe::narrow_oop_base() == NULL) {
3341 if (Universe::narrow_oop_shift() != 0) {
3342 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3343 shr(r, LogMinObjAlignmentInBytes);
3344 }
3345 return;
3346 }
3348 movz(r, S5_heapbase, r);
3349 dsub(r, r, S5_heapbase);
3350 if (Universe::narrow_oop_shift() != 0) {
3351 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3352 shr(r, LogMinObjAlignmentInBytes);
3353 }
3354 }
3356 void MacroAssembler::encode_heap_oop(Register dst, Register src) {
3357 #ifdef ASSERT
3358 verify_heapbase("MacroAssembler::encode_heap_oop:heap base corrupted?");
3359 #endif
3360 verify_oop(src, "broken oop in encode_heap_oop");
3361 if (Universe::narrow_oop_base() == NULL) {
3362 if (Universe::narrow_oop_shift() != 0) {
3363 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3364 dsrl(dst, src, LogMinObjAlignmentInBytes);
3365 } else {
3366 if (dst != src) move(dst, src);
3367 }
3368 } else {
3369 if (dst == src) {
3370 movz(dst, S5_heapbase, dst);
3371 dsub(dst, dst, S5_heapbase);
3372 if (Universe::narrow_oop_shift() != 0) {
3373 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3374 shr(dst, LogMinObjAlignmentInBytes);
3375 }
3376 } else {
3377 dsub(dst, src, S5_heapbase);
3378 if (Universe::narrow_oop_shift() != 0) {
3379 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3380 shr(dst, LogMinObjAlignmentInBytes);
3381 }
3382 movz(dst, R0, src);
3383 }
3384 }
3385 }
3387 void MacroAssembler::encode_heap_oop_not_null(Register r) {
3388 assert (UseCompressedOops, "should be compressed");
3389 #ifdef ASSERT
3390 if (CheckCompressedOops) {
3391 Label ok;
3392 bne(r, R0, ok);
3393 delayed()->nop();
3394 stop("null oop passed to encode_heap_oop_not_null");
3395 bind(ok);
3396 }
3397 #endif
3398 verify_oop(r, "broken oop in encode_heap_oop_not_null");
3399 if (Universe::narrow_oop_base() != NULL) {
3400 dsub(r, r, S5_heapbase);
3401 }
3402 if (Universe::narrow_oop_shift() != 0) {
3403 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3404 shr(r, LogMinObjAlignmentInBytes);
3405 }
3407 }
3409 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
3410 assert (UseCompressedOops, "should be compressed");
3411 #ifdef ASSERT
3412 if (CheckCompressedOops) {
3413 Label ok;
3414 bne(src, R0, ok);
3415 delayed()->nop();
3416 stop("null oop passed to encode_heap_oop_not_null2");
3417 bind(ok);
3418 }
3419 #endif
3420 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
3422 if (Universe::narrow_oop_base() != NULL) {
3423 dsub(dst, src, S5_heapbase);
3424 if (Universe::narrow_oop_shift() != 0) {
3425 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3426 shr(dst, LogMinObjAlignmentInBytes);
3427 }
3428 } else {
3429 if (Universe::narrow_oop_shift() != 0) {
3430 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3431 dsrl(dst, src, LogMinObjAlignmentInBytes);
3432 } else {
3433 if (dst != src) move(dst, src);
3434 }
3435 }
3436 }
3438 void MacroAssembler::decode_heap_oop(Register r) {
3439 #ifdef ASSERT
3440 verify_heapbase("MacroAssembler::decode_heap_oop corrupted?");
3441 #endif
3442 if (Universe::narrow_oop_base() == NULL) {
3443 if (Universe::narrow_oop_shift() != 0) {
3444 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3445 shl(r, LogMinObjAlignmentInBytes);
3446 }
3447 } else {
3448 move(AT, r);
3449 if (Universe::narrow_oop_shift() != 0) {
3450 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3451 shl(r, LogMinObjAlignmentInBytes);
3452 }
3453 dadd(r, r, S5_heapbase);
3454 movz(r, R0, AT);
3455 }
3456 verify_oop(r, "broken oop in decode_heap_oop");
3457 }
3459 void MacroAssembler::decode_heap_oop(Register dst, Register src) {
3460 #ifdef ASSERT
3461 verify_heapbase("MacroAssembler::decode_heap_oop corrupted?");
3462 #endif
3463 if (Universe::narrow_oop_base() == NULL) {
3464 if (Universe::narrow_oop_shift() != 0) {
3465 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3466 if (dst != src) nop(); // DON'T DELETE THIS GUY.
3467 dsll(dst, src, LogMinObjAlignmentInBytes);
3468 } else {
3469 if (dst != src) move(dst, src);
3470 }
3471 } else {
3472 if (dst == src) {
3473 move(AT, dst);
3474 if (Universe::narrow_oop_shift() != 0) {
3475 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3476 shl(dst, LogMinObjAlignmentInBytes);
3477 }
3478 dadd(dst, dst, S5_heapbase);
3479 movz(dst, R0, AT);
3480 } else {
3481 if (Universe::narrow_oop_shift() != 0) {
3482 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3483 dsll(dst, src, LogMinObjAlignmentInBytes);
3484 daddu(dst, dst, S5_heapbase);
3485 } else {
3486 daddu(dst, src, S5_heapbase);
3487 }
3488 movz(dst, R0, src);
3489 }
3490 }
3491 verify_oop(dst, "broken oop in decode_heap_oop");
3492 }
3494 void MacroAssembler::decode_heap_oop_not_null(Register r) {
3495 // Note: it will change flags
3496 assert (UseCompressedOops, "should only be used for compressed headers");
3497 assert (Universe::heap() != NULL, "java heap should be initialized");
3498 // Cannot assert, unverified entry point counts instructions (see .ad file)
3499 // vtableStubs also counts instructions in pd_code_size_limit.
3500 // Also do not verify_oop as this is called by verify_oop.
3501 if (Universe::narrow_oop_shift() != 0) {
3502 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3503 shl(r, LogMinObjAlignmentInBytes);
3504 if (Universe::narrow_oop_base() != NULL) {
3505 daddu(r, r, S5_heapbase);
3506 }
3507 } else {
3508 assert (Universe::narrow_oop_base() == NULL, "sanity");
3509 }
3510 }
3512 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
3513 assert (UseCompressedOops, "should only be used for compressed headers");
3514 assert (Universe::heap() != NULL, "java heap should be initialized");
3516 // Cannot assert, unverified entry point counts instructions (see .ad file)
3517 // vtableStubs also counts instructions in pd_code_size_limit.
3518 // Also do not verify_oop as this is called by verify_oop.
3519 //lea(dst, Address(S5_heapbase, src, Address::times_8, 0));
3520 if (Universe::narrow_oop_shift() != 0) {
3521 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3522 if (LogMinObjAlignmentInBytes == Address::times_8) {
3523 dsll(dst, src, LogMinObjAlignmentInBytes);
3524 daddu(dst, dst, S5_heapbase);
3525 } else {
3526 dsll(dst, src, LogMinObjAlignmentInBytes);
3527 if (Universe::narrow_oop_base() != NULL) {
3528 daddu(dst, dst, S5_heapbase);
3529 }
3530 }
3531 } else {
3532 assert (Universe::narrow_oop_base() == NULL, "sanity");
3533 if (dst != src) {
3534 move(dst, src);
3535 }
3536 }
3537 }
3539 void MacroAssembler::encode_klass_not_null(Register r) {
3540 if (Universe::narrow_klass_base() != NULL) {
3541 assert(r != AT, "Encoding a klass in AT");
3542 set64(AT, (int64_t)Universe::narrow_klass_base());
3543 dsub(r, r, AT);
3544 }
3545 if (Universe::narrow_klass_shift() != 0) {
3546 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3547 shr(r, LogKlassAlignmentInBytes);
3548 }
3549 // Not neccessary for MIPS at all.
3550 //if (Universe::narrow_klass_base() != NULL) {
3551 // reinit_heapbase();
3552 //}
3553 }
3555 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
3556 if (dst == src) {
3557 encode_klass_not_null(src);
3558 } else {
3559 if (Universe::narrow_klass_base() != NULL) {
3560 set64(dst, (int64_t)Universe::narrow_klass_base());
3561 dsub(dst, src, dst);
3562 if (Universe::narrow_klass_shift() != 0) {
3563 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3564 shr(dst, LogKlassAlignmentInBytes);
3565 }
3566 } else {
3567 if (Universe::narrow_klass_shift() != 0) {
3568 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3569 dsrl(dst, src, LogKlassAlignmentInBytes);
3570 } else {
3571 move(dst, src);
3572 }
3573 }
3574 }
3575 }
3577 // Function instr_size_for_decode_klass_not_null() counts the instructions
3578 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
3579 // when (Universe::heap() != NULL). Hence, if the instructions they
3580 // generate change, then this method needs to be updated.
3581 int MacroAssembler::instr_size_for_decode_klass_not_null() {
3582 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
3583 if (Universe::narrow_klass_base() != NULL) {
3584 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
3585 return (Universe::narrow_klass_shift() == 0 ? 4 * 9 : 4 * 10);
3586 } else {
3587 // longest load decode klass function, mov64, leaq
3588 return (Universe::narrow_klass_shift() == 0 ? 4 * 0 : 4 * 1);
3589 }
3590 }
3592 void MacroAssembler::decode_klass_not_null(Register r) {
3593 assert (UseCompressedClassPointers, "should only be used for compressed headers");
3594 assert(r != AT, "Decoding a klass in AT");
3595 // Cannot assert, unverified entry point counts instructions (see .ad file)
3596 // vtableStubs also counts instructions in pd_code_size_limit.
3597 // Also do not verify_oop as this is called by verify_oop.
3598 if (Universe::narrow_klass_shift() != 0) {
3599 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3600 shl(r, LogKlassAlignmentInBytes);
3601 }
3602 if (Universe::narrow_klass_base() != NULL) {
3603 set64(AT, (int64_t)Universe::narrow_klass_base());
3604 daddu(r, r, AT);
3605 //Not neccessary for MIPS at all.
3606 //reinit_heapbase();
3607 }
3608 }
3610 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
3611 assert (UseCompressedClassPointers, "should only be used for compressed headers");
3613 if (dst == src) {
3614 decode_klass_not_null(dst);
3615 } else {
3616 // Cannot assert, unverified entry point counts instructions (see .ad file)
3617 // vtableStubs also counts instructions in pd_code_size_limit.
3618 // Also do not verify_oop as this is called by verify_oop.
3619 set64(dst, (int64_t)Universe::narrow_klass_base());
3620 if (Universe::narrow_klass_shift() != 0) {
3621 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3622 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
3623 dsll(AT, src, Address::times_8);
3624 daddu(dst, dst, AT);
3625 } else {
3626 daddu(dst, src, dst);
3627 }
3628 }
3629 }
3631 void MacroAssembler::incrementl(Register reg, int value) {
3632 if (value == min_jint) {
3633 move(AT, value);
3634 LP64_ONLY(addu32(reg, reg, AT)) NOT_LP64(addu(reg, reg, AT));
3635 return;
3636 }
3637 if (value < 0) { decrementl(reg, -value); return; }
3638 if (value == 0) { ; return; }
3640 if(Assembler::is_simm16(value)) {
3641 NOT_LP64(addiu(reg, reg, value));
3642 LP64_ONLY(move(AT, value); addu32(reg, reg, AT));
3643 } else {
3644 move(AT, value);
3645 LP64_ONLY(addu32(reg, reg, AT)) NOT_LP64(addu(reg, reg, AT));
3646 }
3647 }
3649 void MacroAssembler::decrementl(Register reg, int value) {
3650 if (value == min_jint) {
3651 move(AT, value);
3652 LP64_ONLY(subu32(reg, reg, AT)) NOT_LP64(subu(reg, reg, AT));
3653 return;
3654 }
3655 if (value < 0) { incrementl(reg, -value); return; }
3656 if (value == 0) { ; return; }
3658 if(Assembler::is_simm16(value)) {
3659 NOT_LP64(addiu(reg, reg, -value));
3660 LP64_ONLY(move(AT, value); subu32(reg, reg, AT));
3661 } else {
3662 move(AT, value);
3663 LP64_ONLY(subu32(reg, reg, AT)) NOT_LP64(subu(reg, reg, AT));
3664 }
3665 }
3667 void MacroAssembler::reinit_heapbase() {
3668 if (UseCompressedOops || UseCompressedClassPointers) {
3669 if (Universe::heap() != NULL) {
3670 if (Universe::narrow_oop_base() == NULL) {
3671 move(S5_heapbase, R0);
3672 } else {
3673 set64(S5_heapbase, (int64_t)Universe::narrow_ptrs_base());
3674 }
3675 } else {
3676 set64(S5_heapbase, (intptr_t)Universe::narrow_ptrs_base_addr());
3677 ld(S5_heapbase, S5_heapbase, 0);
3678 }
3679 }
3680 }
3681 #endif // _LP64
3683 void MacroAssembler::check_klass_subtype(Register sub_klass,
3684 Register super_klass,
3685 Register temp_reg,
3686 Label& L_success) {
3687 //implement ind gen_subtype_check
3688 Label L_failure;
3689 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
3690 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
3691 bind(L_failure);
3692 }
3694 SkipIfEqual::SkipIfEqual(
3695 MacroAssembler* masm, const bool* flag_addr, bool value) {
3696 _masm = masm;
3697 _masm->li(AT, (address)flag_addr);
3698 _masm->lb(AT,AT,0);
3699 _masm->addi(AT,AT,-value);
3700 _masm->beq(AT,R0,_label);
3701 _masm->delayed()->nop();
3702 }
3703 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
3704 Register super_klass,
3705 Register temp_reg,
3706 Label* L_success,
3707 Label* L_failure,
3708 Label* L_slow_path,
3709 RegisterOrConstant super_check_offset) {
3710 assert_different_registers(sub_klass, super_klass, temp_reg);
3711 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
3712 if (super_check_offset.is_register()) {
3713 assert_different_registers(sub_klass, super_klass,
3714 super_check_offset.as_register());
3715 } else if (must_load_sco) {
3716 assert(temp_reg != noreg, "supply either a temp or a register offset");
3717 }
3719 Label L_fallthrough;
3720 int label_nulls = 0;
3721 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
3722 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
3723 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
3724 assert(label_nulls <= 1, "at most one NULL in the batch");
3726 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
3727 int sco_offset = in_bytes(Klass::super_check_offset_offset());
3728 // If the pointers are equal, we are done (e.g., String[] elements).
3729 // This self-check enables sharing of secondary supertype arrays among
3730 // non-primary types such as array-of-interface. Otherwise, each such
3731 // type would need its own customized SSA.
3732 // We move this check to the front of the fast path because many
3733 // type checks are in fact trivially successful in this manner,
3734 // so we get a nicely predicted branch right at the start of the check.
3735 //cmpptr(sub_klass, super_klass);
3736 //local_jcc(Assembler::equal, *L_success);
3737 beq(sub_klass, super_klass, *L_success);
3738 delayed()->nop();
3739 // Check the supertype display:
3740 if (must_load_sco) {
3741 // Positive movl does right thing on LP64.
3742 lwu(temp_reg, super_klass, sco_offset);
3743 super_check_offset = RegisterOrConstant(temp_reg);
3744 }
3745 dsll(AT, super_check_offset.register_or_noreg(), Address::times_1);
3746 daddu(AT, sub_klass, AT);
3747 ld(AT, AT, super_check_offset.constant_or_zero()*Address::times_1);
3749 // This check has worked decisively for primary supers.
3750 // Secondary supers are sought in the super_cache ('super_cache_addr').
3751 // (Secondary supers are interfaces and very deeply nested subtypes.)
3752 // This works in the same check above because of a tricky aliasing
3753 // between the super_cache and the primary super display elements.
3754 // (The 'super_check_addr' can address either, as the case requires.)
3755 // Note that the cache is updated below if it does not help us find
3756 // what we need immediately.
3757 // So if it was a primary super, we can just fail immediately.
3758 // Otherwise, it's the slow path for us (no success at this point).
3760 if (super_check_offset.is_register()) {
3761 beq(super_klass, AT, *L_success);
3762 delayed()->nop();
3763 addi(AT, super_check_offset.as_register(), -sc_offset);
3764 if (L_failure == &L_fallthrough) {
3765 beq(AT, R0, *L_slow_path);
3766 delayed()->nop();
3767 } else {
3768 bne(AT, R0, *L_failure);
3769 delayed()->nop();
3770 b(*L_slow_path);
3771 delayed()->nop();
3772 }
3773 } else if (super_check_offset.as_constant() == sc_offset) {
3774 // Need a slow path; fast failure is impossible.
3775 if (L_slow_path == &L_fallthrough) {
3776 beq(super_klass, AT, *L_success);
3777 delayed()->nop();
3778 } else {
3779 bne(super_klass, AT, *L_slow_path);
3780 delayed()->nop();
3781 b(*L_success);
3782 delayed()->nop();
3783 }
3784 } else {
3785 // No slow path; it's a fast decision.
3786 if (L_failure == &L_fallthrough) {
3787 beq(super_klass, AT, *L_success);
3788 delayed()->nop();
3789 } else {
3790 bne(super_klass, AT, *L_failure);
3791 delayed()->nop();
3792 b(*L_success);
3793 delayed()->nop();
3794 }
3795 }
3797 bind(L_fallthrough);
3799 }
3802 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
3803 Register super_klass,
3804 Register temp_reg,
3805 Register temp2_reg,
3806 Label* L_success,
3807 Label* L_failure,
3808 bool set_cond_codes) {
3809 assert_different_registers(sub_klass, super_klass, temp_reg);
3810 if (temp2_reg != noreg)
3811 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
3812 else
3813 temp2_reg = T9;
3814 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
3816 Label L_fallthrough;
3817 int label_nulls = 0;
3818 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
3819 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
3820 assert(label_nulls <= 1, "at most one NULL in the batch");
3822 // a couple of useful fields in sub_klass:
3823 int ss_offset = in_bytes(Klass::secondary_supers_offset());
3824 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
3825 Address secondary_supers_addr(sub_klass, ss_offset);
3826 Address super_cache_addr( sub_klass, sc_offset);
3828 // Do a linear scan of the secondary super-klass chain.
3829 // This code is rarely used, so simplicity is a virtue here.
3830 // The repne_scan instruction uses fixed registers, which we must spill.
3831 // Don't worry too much about pre-existing connections with the input regs.
3833 #if 0
3834 assert(sub_klass != T9, "killed reg"); // killed by mov(rax, super)
3835 assert(sub_klass != T1, "killed reg"); // killed by lea(rcx, &pst_counter)
3836 #endif
3838 // Get super_klass value into rax (even if it was in rdi or rcx).
3839 #ifndef PRODUCT
3840 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
3841 ExternalAddress pst_counter_addr((address) pst_counter);
3842 NOT_LP64( incrementl(pst_counter_addr) );
3843 //LP64_ONLY( lea(rcx, pst_counter_addr) );
3844 //LP64_ONLY( incrementl(Address(rcx, 0)) );
3845 #endif //PRODUCT
3847 // We will consult the secondary-super array.
3848 ld(temp_reg, secondary_supers_addr);
3849 // Load the array length. (Positive movl does right thing on LP64.)
3850 lw(temp2_reg, Address(temp_reg, Array<Klass*>::length_offset_in_bytes()));
3851 // Skip to start of data.
3852 daddiu(temp_reg, temp_reg, Array<Klass*>::base_offset_in_bytes());
3854 // Scan RCX words at [RDI] for an occurrence of RAX.
3855 // Set NZ/Z based on last compare.
3856 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
3857 // not change flags (only scas instruction which is repeated sets flags).
3858 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
3860 /* 2013/4/3 Jin: OpenJDK8 never compresses klass pointers in secondary-super array. */
3861 Label Loop, subtype;
3862 bind(Loop);
3863 beq(temp2_reg, R0, *L_failure);
3864 delayed()->nop();
3865 ld(AT, temp_reg, 0);
3866 beq(AT, super_klass, subtype);
3867 delayed()->daddi(temp_reg, temp_reg, 1 * wordSize);
3868 b(Loop);
3869 delayed()->daddi(temp2_reg, temp2_reg, -1);
3871 bind(subtype);
3872 sd(super_klass, super_cache_addr);
3873 if (L_success != &L_fallthrough) {
3874 b(*L_success);
3875 delayed()->nop();
3876 }
3878 // Success. Cache the super we found and proceed in triumph.
3879 #undef IS_A_TEMP
3881 bind(L_fallthrough);
3882 }
3883 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
3884 ld(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
3885 sd(R0, Address(java_thread, JavaThread::vm_result_offset()));
3886 verify_oop(oop_result, "broken oop in call_VM_base");
3887 }
3889 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
3890 ld(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
3891 sd(R0, Address(java_thread, JavaThread::vm_result_2_offset()));
3892 }
3894 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
3895 int extra_slot_offset) {
3896 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
3897 int stackElementSize = Interpreter::stackElementSize;
3898 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
3899 #ifdef ASSERT
3900 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
3901 assert(offset1 - offset == stackElementSize, "correct arithmetic");
3902 #endif
3903 Register scale_reg = NOREG;
3904 Address::ScaleFactor scale_factor = Address::no_scale;
3905 if (arg_slot.is_constant()) {
3906 offset += arg_slot.as_constant() * stackElementSize;
3907 } else {
3908 scale_reg = arg_slot.as_register();
3909 scale_factor = Address::times_8;
3910 }
3911 // 2014/07/31 Fu: We don't push RA on stack in prepare_invoke.
3912 // offset += wordSize; // return PC is on stack
3913 if(scale_reg==NOREG) return Address(SP, offset);
3914 else {
3915 dsll(scale_reg, scale_reg, scale_factor);
3916 daddu(scale_reg, SP, scale_reg);
3917 return Address(scale_reg, offset);
3918 }
3919 }
3921 SkipIfEqual::~SkipIfEqual() {
3922 _masm->bind(_label);
3923 }
3925 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3926 switch (size_in_bytes) {
3927 #ifndef _LP64
3928 case 8:
3929 assert(dst2 != noreg, "second dest register required");
3930 lw(dst, src);
3931 lw(dst2, src.plus_disp(BytesPerInt));
3932 break;
3933 #else
3934 case 8: ld(dst, src); break;
3935 #endif
3936 case 4: lw(dst, src); break;
3937 case 2: is_signed ? lh(dst, src) : lhu(dst, src); break;
3938 case 1: is_signed ? lb( dst, src) : lbu( dst, src); break;
3939 default: ShouldNotReachHere();
3940 }
3941 }
3943 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3944 switch (size_in_bytes) {
3945 #ifndef _LP64
3946 case 8:
3947 assert(src2 != noreg, "second source register required");
3948 sw(src, dst);
3949 sw(src2, dst.plus_disp(BytesPerInt));
3950 break;
3951 #else
3952 case 8: sd(src, dst); break;
3953 #endif
3954 case 4: sw(src, dst); break;
3955 case 2: sh(src, dst); break;
3956 case 1: sb(src, dst); break;
3957 default: ShouldNotReachHere();
3958 }
3959 }
3961 // Look up the method for a megamorphic invokeinterface call.
3962 // The target method is determined by <intf_klass, itable_index>.
3963 // The receiver klass is in recv_klass.
3964 // On success, the result will be in method_result, and execution falls through.
3965 // On failure, execution transfers to the given label.
3966 void MacroAssembler::lookup_interface_method(Register recv_klass,
3967 Register intf_klass,
3968 RegisterOrConstant itable_index,
3969 Register method_result,
3970 Register scan_temp,
3971 Label& L_no_such_interface) {
3972 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
3973 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3974 "caller must use same register for non-constant itable index as for method");
3976 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3977 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
3978 int itentry_off = itableMethodEntry::method_offset_in_bytes();
3979 int scan_step = itableOffsetEntry::size() * wordSize;
3980 int vte_size = vtableEntry::size() * wordSize;
3981 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3982 assert(vte_size == wordSize, "else adjust times_vte_scale");
3984 lw(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize));
3986 // %%% Could store the aligned, prescaled offset in the klassoop.
3987 dsll(scan_temp, scan_temp, times_vte_scale);
3988 daddu(scan_temp, recv_klass, scan_temp);
3989 daddiu(scan_temp, scan_temp, vtable_base);
3990 if (HeapWordsPerLong > 1) {
3991 // Round up to align_object_offset boundary
3992 // see code for InstanceKlass::start_of_itable!
3993 round_to(scan_temp, BytesPerLong);
3994 }
3996 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3997 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3998 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
3999 if (itable_index.is_constant()) {
4000 set64(AT, (int)itable_index.is_constant());
4001 dsll(AT, AT, (int)Address::times_ptr);
4002 } else {
4003 dsll(AT, itable_index.as_register(), (int)Address::times_ptr);
4004 }
4005 daddu(AT, AT, recv_klass);
4006 daddiu(recv_klass, AT, itentry_off);
4008 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
4009 // if (scan->interface() == intf) {
4010 // result = (klass + scan->offset() + itable_index);
4011 // }
4012 // }
4013 Label search, found_method;
4015 for (int peel = 1; peel >= 0; peel--) {
4016 ld(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4018 if (peel) {
4019 beq(intf_klass, method_result, found_method);
4020 nop();
4021 } else {
4022 bne(intf_klass, method_result, search);
4023 nop();
4024 // (invert the test to fall through to found_method...)
4025 }
4027 if (!peel) break;
4029 bind(search);
4031 // Check that the previous entry is non-null. A null entry means that
4032 // the receiver class doesn't implement the interface, and wasn't the
4033 // same as when the caller was compiled.
4034 beq(method_result, R0, L_no_such_interface);
4035 nop();
4036 daddiu(scan_temp, scan_temp, scan_step);
4037 }
4039 bind(found_method);
4041 // Got a hit.
4042 lw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4043 //ld(method_result, Address(recv_klass, scan_temp, Address::times_1));
4044 if(UseLoongsonISA) {
4045 gsldx(method_result, recv_klass, scan_temp, 0);
4046 } else {
4047 daddu(AT, recv_klass, scan_temp);
4048 ld(method_result, AT);
4049 }
4050 }
4053 // virtual method calling
4054 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4055 RegisterOrConstant vtable_index,
4056 Register method_result) {
4057 Register tmp = GP;
4058 push(tmp);
4060 if (vtable_index.is_constant()) {
4061 assert_different_registers(recv_klass, method_result, tmp);
4062 } else {
4063 assert_different_registers(recv_klass, method_result, vtable_index.as_register(), tmp);
4064 }
4065 const int base = InstanceKlass::vtable_start_offset() * wordSize;
4066 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4067 /*
4068 Address vtable_entry_addr(recv_klass,
4069 vtable_index, Address::times_ptr,
4070 base + vtableEntry::method_offset_in_bytes());
4071 */
4072 if (vtable_index.is_constant()) {
4073 set64(AT, vtable_index.as_constant());
4074 dsll(AT, AT, (int)Address::times_ptr);
4075 } else {
4076 dsll(AT, vtable_index.as_register(), (int)Address::times_ptr);
4077 }
4078 set64(tmp, base + vtableEntry::method_offset_in_bytes());
4079 daddu(tmp, tmp, AT);
4080 daddu(tmp, tmp, recv_klass);
4081 ld(method_result, tmp, 0);
4083 pop(tmp);
4084 }