Wed, 14 Dec 2011 14:54:38 -0800
7116452: Add support for AVX instructions
Summary: Added support for AVX extension to the x86 instruction set.
Reviewed-by: never
1 //
2 // Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
25 // X86 Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundary (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source_hpp %{
239 // Must be visible to the DFA in dfa_x86_32.cpp
240 extern bool is_operand_hi32_zero(Node* n);
241 %}
243 source %{
244 #define RELOC_IMM32 Assembler::imm_operand
245 #define RELOC_DISP32 Assembler::disp32_operand
247 #define __ _masm.
249 // How to find the high register of a Long pair, given the low register
250 #define HIGH_FROM_LOW(x) ((x)+2)
252 // These masks are used to provide 128-bit aligned bitmasks to the XMM
253 // instructions, to allow sign-masking or sign-bit flipping. They allow
254 // fast versions of NegF/NegD and AbsF/AbsD.
256 // Note: 'double' and 'long long' have 32-bits alignment on x86.
257 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
258 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
259 // of 128-bits operands for SSE instructions.
260 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
261 // Store the value to a 128-bits operand.
262 operand[0] = lo;
263 operand[1] = hi;
264 return operand;
265 }
267 // Buffer for 128-bits masks used by SSE instructions.
268 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
270 // Static initialization during VM startup.
271 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
272 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
273 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
274 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
276 // Offset hacking within calls.
277 static int pre_call_FPU_size() {
278 if (Compile::current()->in_24_bit_fp_mode())
279 return 6; // fldcw
280 return 0;
281 }
283 static int preserve_SP_size() {
284 return 2; // op, rm(reg/reg)
285 }
287 // !!!!! Special hack to get all type of calls to specify the byte offset
288 // from the start of the call to the point where the return address
289 // will point.
290 int MachCallStaticJavaNode::ret_addr_offset() {
291 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points
292 if (_method_handle_invoke)
293 offset += preserve_SP_size();
294 return offset;
295 }
297 int MachCallDynamicJavaNode::ret_addr_offset() {
298 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points
299 }
301 static int sizeof_FFree_Float_Stack_All = -1;
303 int MachCallRuntimeNode::ret_addr_offset() {
304 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
305 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size();
306 }
308 // Indicate if the safepoint node needs the polling page as an input.
309 // Since x86 does have absolute addressing, it doesn't.
310 bool SafePointNode::needs_polling_address_input() {
311 return false;
312 }
314 //
315 // Compute padding required for nodes which need alignment
316 //
318 // The address of the call instruction needs to be 4-byte aligned to
319 // ensure that it does not span a cache line so that it can be patched.
320 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
321 current_offset += pre_call_FPU_size(); // skip fldcw, if any
322 current_offset += 1; // skip call opcode byte
323 return round_to(current_offset, alignment_required()) - current_offset;
324 }
326 // The address of the call instruction needs to be 4-byte aligned to
327 // ensure that it does not span a cache line so that it can be patched.
328 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
329 current_offset += pre_call_FPU_size(); // skip fldcw, if any
330 current_offset += preserve_SP_size(); // skip mov rbp, rsp
331 current_offset += 1; // skip call opcode byte
332 return round_to(current_offset, alignment_required()) - current_offset;
333 }
335 // The address of the call instruction needs to be 4-byte aligned to
336 // ensure that it does not span a cache line so that it can be patched.
337 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
338 current_offset += pre_call_FPU_size(); // skip fldcw, if any
339 current_offset += 5; // skip MOV instruction
340 current_offset += 1; // skip call opcode byte
341 return round_to(current_offset, alignment_required()) - current_offset;
342 }
344 #ifndef PRODUCT
345 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
346 st->print("INT3");
347 }
348 #endif
350 // EMIT_RM()
351 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
352 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
353 cbuf.insts()->emit_int8(c);
354 }
356 // EMIT_CC()
357 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
358 unsigned char c = (unsigned char)( f1 | f2 );
359 cbuf.insts()->emit_int8(c);
360 }
362 // EMIT_OPCODE()
363 void emit_opcode(CodeBuffer &cbuf, int code) {
364 cbuf.insts()->emit_int8((unsigned char) code);
365 }
367 // EMIT_OPCODE() w/ relocation information
368 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
369 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
370 emit_opcode(cbuf, code);
371 }
373 // EMIT_D8()
374 void emit_d8(CodeBuffer &cbuf, int d8) {
375 cbuf.insts()->emit_int8((unsigned char) d8);
376 }
378 // EMIT_D16()
379 void emit_d16(CodeBuffer &cbuf, int d16) {
380 cbuf.insts()->emit_int16(d16);
381 }
383 // EMIT_D32()
384 void emit_d32(CodeBuffer &cbuf, int d32) {
385 cbuf.insts()->emit_int32(d32);
386 }
388 // emit 32 bit value and construct relocation entry from relocInfo::relocType
389 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
390 int format) {
391 cbuf.relocate(cbuf.insts_mark(), reloc, format);
392 cbuf.insts()->emit_int32(d32);
393 }
395 // emit 32 bit value and construct relocation entry from RelocationHolder
396 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
397 int format) {
398 #ifdef ASSERT
399 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
400 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
401 }
402 #endif
403 cbuf.relocate(cbuf.insts_mark(), rspec, format);
404 cbuf.insts()->emit_int32(d32);
405 }
407 // Access stack slot for load or store
408 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
409 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
410 if( -128 <= disp && disp <= 127 ) {
411 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
412 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
413 emit_d8 (cbuf, disp); // Displacement // R/M byte
414 } else {
415 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
416 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
417 emit_d32(cbuf, disp); // Displacement // R/M byte
418 }
419 }
421 // eRegI ereg, memory mem) %{ // emit_reg_mem
422 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
423 // There is no index & no scale, use form without SIB byte
424 if ((index == 0x4) &&
425 (scale == 0) && (base != ESP_enc)) {
426 // If no displacement, mode is 0x0; unless base is [EBP]
427 if ( (displace == 0) && (base != EBP_enc) ) {
428 emit_rm(cbuf, 0x0, reg_encoding, base);
429 }
430 else { // If 8-bit displacement, mode 0x1
431 if ((displace >= -128) && (displace <= 127)
432 && !(displace_is_oop) ) {
433 emit_rm(cbuf, 0x1, reg_encoding, base);
434 emit_d8(cbuf, displace);
435 }
436 else { // If 32-bit displacement
437 if (base == -1) { // Special flag for absolute address
438 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
439 // (manual lies; no SIB needed here)
440 if ( displace_is_oop ) {
441 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
442 } else {
443 emit_d32 (cbuf, displace);
444 }
445 }
446 else { // Normal base + offset
447 emit_rm(cbuf, 0x2, reg_encoding, base);
448 if ( displace_is_oop ) {
449 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
450 } else {
451 emit_d32 (cbuf, displace);
452 }
453 }
454 }
455 }
456 }
457 else { // Else, encode with the SIB byte
458 // If no displacement, mode is 0x0; unless base is [EBP]
459 if (displace == 0 && (base != EBP_enc)) { // If no displacement
460 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
461 emit_rm(cbuf, scale, index, base);
462 }
463 else { // If 8-bit displacement, mode 0x1
464 if ((displace >= -128) && (displace <= 127)
465 && !(displace_is_oop) ) {
466 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
467 emit_rm(cbuf, scale, index, base);
468 emit_d8(cbuf, displace);
469 }
470 else { // If 32-bit displacement
471 if (base == 0x04 ) {
472 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
473 emit_rm(cbuf, scale, index, 0x04);
474 } else {
475 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
476 emit_rm(cbuf, scale, index, base);
477 }
478 if ( displace_is_oop ) {
479 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
480 } else {
481 emit_d32 (cbuf, displace);
482 }
483 }
484 }
485 }
486 }
489 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
490 if( dst_encoding == src_encoding ) {
491 // reg-reg copy, use an empty encoding
492 } else {
493 emit_opcode( cbuf, 0x8B );
494 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
495 }
496 }
498 void emit_cmpfp_fixup(MacroAssembler& _masm) {
499 Label exit;
500 __ jccb(Assembler::noParity, exit);
501 __ pushf();
502 //
503 // comiss/ucomiss instructions set ZF,PF,CF flags and
504 // zero OF,AF,SF for NaN values.
505 // Fixup flags by zeroing ZF,PF so that compare of NaN
506 // values returns 'less than' result (CF is set).
507 // Leave the rest of flags unchanged.
508 //
509 // 7 6 5 4 3 2 1 0
510 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
511 // 0 0 1 0 1 0 1 1 (0x2B)
512 //
513 __ andl(Address(rsp, 0), 0xffffff2b);
514 __ popf();
515 __ bind(exit);
516 }
518 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
519 Label done;
520 __ movl(dst, -1);
521 __ jcc(Assembler::parity, done);
522 __ jcc(Assembler::below, done);
523 __ setb(Assembler::notEqual, dst);
524 __ movzbl(dst, dst);
525 __ bind(done);
526 }
529 //=============================================================================
530 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
532 int Compile::ConstantTable::calculate_table_base_offset() const {
533 return 0; // absolute addressing, no offset
534 }
536 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
537 // Empty encoding
538 }
540 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
541 return 0;
542 }
544 #ifndef PRODUCT
545 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
546 st->print("# MachConstantBaseNode (empty encoding)");
547 }
548 #endif
551 //=============================================================================
552 #ifndef PRODUCT
553 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
554 Compile* C = ra_->C;
555 if( C->in_24_bit_fp_mode() ) {
556 st->print("FLDCW 24 bit fpu control word");
557 st->print_cr(""); st->print("\t");
558 }
560 int framesize = C->frame_slots() << LogBytesPerInt;
561 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
562 // Remove two words for return addr and rbp,
563 framesize -= 2*wordSize;
565 // Calls to C2R adapters often do not accept exceptional returns.
566 // We require that their callers must bang for them. But be careful, because
567 // some VM calls (such as call site linkage) can use several kilobytes of
568 // stack. But the stack safety zone should account for that.
569 // See bugs 4446381, 4468289, 4497237.
570 if (C->need_stack_bang(framesize)) {
571 st->print_cr("# stack bang"); st->print("\t");
572 }
573 st->print_cr("PUSHL EBP"); st->print("\t");
575 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
576 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check");
577 st->print_cr(""); st->print("\t");
578 framesize -= wordSize;
579 }
581 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
582 if (framesize) {
583 st->print("SUB ESP,%d\t# Create frame",framesize);
584 }
585 } else {
586 st->print("SUB ESP,%d\t# Create frame",framesize);
587 }
588 }
589 #endif
592 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
593 Compile* C = ra_->C;
595 if (UseSSE >= 2 && VerifyFPU) {
596 MacroAssembler masm(&cbuf);
597 masm.verify_FPU(0, "FPU stack must be clean on entry");
598 }
600 // WARNING: Initial instruction MUST be 5 bytes or longer so that
601 // NativeJump::patch_verified_entry will be able to patch out the entry
602 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
603 // depth is ok at 5 bytes, the frame allocation can be either 3 or
604 // 6 bytes. So if we don't do the fldcw or the push then we must
605 // use the 6 byte frame allocation even if we have no frame. :-(
606 // If method sets FPU control word do it now
607 if( C->in_24_bit_fp_mode() ) {
608 MacroAssembler masm(&cbuf);
609 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
610 }
612 int framesize = C->frame_slots() << LogBytesPerInt;
613 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
614 // Remove two words for return addr and rbp,
615 framesize -= 2*wordSize;
617 // Calls to C2R adapters often do not accept exceptional returns.
618 // We require that their callers must bang for them. But be careful, because
619 // some VM calls (such as call site linkage) can use several kilobytes of
620 // stack. But the stack safety zone should account for that.
621 // See bugs 4446381, 4468289, 4497237.
622 if (C->need_stack_bang(framesize)) {
623 MacroAssembler masm(&cbuf);
624 masm.generate_stack_overflow_check(framesize);
625 }
627 // We always push rbp, so that on return to interpreter rbp, will be
628 // restored correctly and we can correct the stack.
629 emit_opcode(cbuf, 0x50 | EBP_enc);
631 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
632 emit_opcode(cbuf, 0x68); // push 0xbadb100d
633 emit_d32(cbuf, 0xbadb100d);
634 framesize -= wordSize;
635 }
637 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
638 if (framesize) {
639 emit_opcode(cbuf, 0x83); // sub SP,#framesize
640 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
641 emit_d8(cbuf, framesize);
642 }
643 } else {
644 emit_opcode(cbuf, 0x81); // sub SP,#framesize
645 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
646 emit_d32(cbuf, framesize);
647 }
648 C->set_frame_complete(cbuf.insts_size());
650 #ifdef ASSERT
651 if (VerifyStackAtCalls) {
652 Label L;
653 MacroAssembler masm(&cbuf);
654 masm.push(rax);
655 masm.mov(rax, rsp);
656 masm.andptr(rax, StackAlignmentInBytes-1);
657 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
658 masm.pop(rax);
659 masm.jcc(Assembler::equal, L);
660 masm.stop("Stack is not properly aligned!");
661 masm.bind(L);
662 }
663 #endif
665 if (C->has_mach_constant_base_node()) {
666 // NOTE: We set the table base offset here because users might be
667 // emitted before MachConstantBaseNode.
668 Compile::ConstantTable& constant_table = C->constant_table();
669 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
670 }
671 }
673 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
674 return MachNode::size(ra_); // too many variables; just compute it the hard way
675 }
677 int MachPrologNode::reloc() const {
678 return 0; // a large enough number
679 }
681 //=============================================================================
682 #ifndef PRODUCT
683 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
684 Compile *C = ra_->C;
685 int framesize = C->frame_slots() << LogBytesPerInt;
686 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
687 // Remove two words for return addr and rbp,
688 framesize -= 2*wordSize;
690 if( C->in_24_bit_fp_mode() ) {
691 st->print("FLDCW standard control word");
692 st->cr(); st->print("\t");
693 }
694 if( framesize ) {
695 st->print("ADD ESP,%d\t# Destroy frame",framesize);
696 st->cr(); st->print("\t");
697 }
698 st->print_cr("POPL EBP"); st->print("\t");
699 if( do_polling() && C->is_method_compilation() ) {
700 st->print("TEST PollPage,EAX\t! Poll Safepoint");
701 st->cr(); st->print("\t");
702 }
703 }
704 #endif
706 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
707 Compile *C = ra_->C;
709 // If method set FPU control word, restore to standard control word
710 if( C->in_24_bit_fp_mode() ) {
711 MacroAssembler masm(&cbuf);
712 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
713 }
715 int framesize = C->frame_slots() << LogBytesPerInt;
716 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
717 // Remove two words for return addr and rbp,
718 framesize -= 2*wordSize;
720 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
722 if( framesize >= 128 ) {
723 emit_opcode(cbuf, 0x81); // add SP, #framesize
724 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
725 emit_d32(cbuf, framesize);
726 }
727 else if( framesize ) {
728 emit_opcode(cbuf, 0x83); // add SP, #framesize
729 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
730 emit_d8(cbuf, framesize);
731 }
733 emit_opcode(cbuf, 0x58 | EBP_enc);
735 if( do_polling() && C->is_method_compilation() ) {
736 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
737 emit_opcode(cbuf,0x85);
738 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
739 emit_d32(cbuf, (intptr_t)os::get_polling_page());
740 }
741 }
743 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
744 Compile *C = ra_->C;
745 // If method set FPU control word, restore to standard control word
746 int size = C->in_24_bit_fp_mode() ? 6 : 0;
747 if( do_polling() && C->is_method_compilation() ) size += 6;
749 int framesize = C->frame_slots() << LogBytesPerInt;
750 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
751 // Remove two words for return addr and rbp,
752 framesize -= 2*wordSize;
754 size++; // popl rbp,
756 if( framesize >= 128 ) {
757 size += 6;
758 } else {
759 size += framesize ? 3 : 0;
760 }
761 return size;
762 }
764 int MachEpilogNode::reloc() const {
765 return 0; // a large enough number
766 }
768 const Pipeline * MachEpilogNode::pipeline() const {
769 return MachNode::pipeline_class();
770 }
772 int MachEpilogNode::safepoint_offset() const { return 0; }
774 //=============================================================================
776 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
777 static enum RC rc_class( OptoReg::Name reg ) {
779 if( !OptoReg::is_valid(reg) ) return rc_bad;
780 if (OptoReg::is_stack(reg)) return rc_stack;
782 VMReg r = OptoReg::as_VMReg(reg);
783 if (r->is_Register()) return rc_int;
784 if (r->is_FloatRegister()) {
785 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
786 return rc_float;
787 }
788 assert(r->is_XMMRegister(), "must be");
789 return rc_xmm;
790 }
792 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
793 int opcode, const char *op_str, int size, outputStream* st ) {
794 if( cbuf ) {
795 emit_opcode (*cbuf, opcode );
796 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
797 #ifndef PRODUCT
798 } else if( !do_size ) {
799 if( size != 0 ) st->print("\n\t");
800 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
801 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
802 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
803 } else { // FLD, FST, PUSH, POP
804 st->print("%s [ESP + #%d]",op_str,offset);
805 }
806 #endif
807 }
808 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
809 return size+3+offset_size;
810 }
812 // Helper for XMM registers. Extra opcode bits, limited syntax.
813 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
814 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
815 if (cbuf) {
816 MacroAssembler _masm(cbuf);
817 if (reg_lo+1 == reg_hi) { // double move?
818 if (is_load) {
819 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
820 } else {
821 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
822 }
823 } else {
824 if (is_load) {
825 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
826 } else {
827 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
828 }
829 }
830 #ifndef PRODUCT
831 } else if (!do_size) {
832 if (size != 0) st->print("\n\t");
833 if (reg_lo+1 == reg_hi) { // double move?
834 if (is_load) st->print("%s %s,[ESP + #%d]",
835 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
836 Matcher::regName[reg_lo], offset);
837 else st->print("MOVSD [ESP + #%d],%s",
838 offset, Matcher::regName[reg_lo]);
839 } else {
840 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
841 Matcher::regName[reg_lo], offset);
842 else st->print("MOVSS [ESP + #%d],%s",
843 offset, Matcher::regName[reg_lo]);
844 }
845 #endif
846 }
847 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
848 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes.
849 return size+5+offset_size;
850 }
853 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
854 int src_hi, int dst_hi, int size, outputStream* st ) {
855 if (cbuf) {
856 MacroAssembler _masm(cbuf);
857 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
858 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
859 as_XMMRegister(Matcher::_regEncode[src_lo]));
860 } else {
861 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
862 as_XMMRegister(Matcher::_regEncode[src_lo]));
863 }
864 #ifndef PRODUCT
865 } else if (!do_size) {
866 if (size != 0) st->print("\n\t");
867 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
868 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
869 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
870 } else {
871 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
872 }
873 } else {
874 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
875 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
876 } else {
877 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
878 }
879 }
880 #endif
881 }
882 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes.
883 // Only MOVAPS SSE prefix uses 1 byte.
884 int sz = 4;
885 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
886 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
887 return size + sz;
888 }
890 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
891 int src_hi, int dst_hi, int size, outputStream* st ) {
892 // 32-bit
893 if (cbuf) {
894 MacroAssembler _masm(cbuf);
895 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
896 as_Register(Matcher::_regEncode[src_lo]));
897 #ifndef PRODUCT
898 } else if (!do_size) {
899 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
900 #endif
901 }
902 return 4;
903 }
906 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
907 int src_hi, int dst_hi, int size, outputStream* st ) {
908 // 32-bit
909 if (cbuf) {
910 MacroAssembler _masm(cbuf);
911 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
912 as_XMMRegister(Matcher::_regEncode[src_lo]));
913 #ifndef PRODUCT
914 } else if (!do_size) {
915 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
916 #endif
917 }
918 return 4;
919 }
921 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
922 if( cbuf ) {
923 emit_opcode(*cbuf, 0x8B );
924 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
925 #ifndef PRODUCT
926 } else if( !do_size ) {
927 if( size != 0 ) st->print("\n\t");
928 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
929 #endif
930 }
931 return size+2;
932 }
934 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
935 int offset, int size, outputStream* st ) {
936 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
937 if( cbuf ) {
938 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
939 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
940 #ifndef PRODUCT
941 } else if( !do_size ) {
942 if( size != 0 ) st->print("\n\t");
943 st->print("FLD %s",Matcher::regName[src_lo]);
944 #endif
945 }
946 size += 2;
947 }
949 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
950 const char *op_str;
951 int op;
952 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
953 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
954 op = 0xDD;
955 } else { // 32-bit store
956 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
957 op = 0xD9;
958 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
959 }
961 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
962 }
964 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
965 // Get registers to move
966 OptoReg::Name src_second = ra_->get_reg_second(in(1));
967 OptoReg::Name src_first = ra_->get_reg_first(in(1));
968 OptoReg::Name dst_second = ra_->get_reg_second(this );
969 OptoReg::Name dst_first = ra_->get_reg_first(this );
971 enum RC src_second_rc = rc_class(src_second);
972 enum RC src_first_rc = rc_class(src_first);
973 enum RC dst_second_rc = rc_class(dst_second);
974 enum RC dst_first_rc = rc_class(dst_first);
976 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
978 // Generate spill code!
979 int size = 0;
981 if( src_first == dst_first && src_second == dst_second )
982 return size; // Self copy, no move
984 // --------------------------------------
985 // Check for mem-mem move. push/pop to move.
986 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
987 if( src_second == dst_first ) { // overlapping stack copy ranges
988 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
989 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
990 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
991 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
992 }
993 // move low bits
994 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
995 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
996 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
997 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
998 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
999 }
1000 return size;
1001 }
1003 // --------------------------------------
1004 // Check for integer reg-reg copy
1005 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1006 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1008 // Check for integer store
1009 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1010 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1012 // Check for integer load
1013 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1014 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1016 // Check for integer reg-xmm reg copy
1017 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1018 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1019 "no 64 bit integer-float reg moves" );
1020 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1021 }
1022 // --------------------------------------
1023 // Check for float reg-reg copy
1024 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1025 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1026 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1027 if( cbuf ) {
1029 // Note the mucking with the register encode to compensate for the 0/1
1030 // indexing issue mentioned in a comment in the reg_def sections
1031 // for FPR registers many lines above here.
1033 if( src_first != FPR1L_num ) {
1034 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1035 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1036 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1037 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1038 } else {
1039 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1040 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1041 }
1042 #ifndef PRODUCT
1043 } else if( !do_size ) {
1044 if( size != 0 ) st->print("\n\t");
1045 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1046 else st->print( "FST %s", Matcher::regName[dst_first]);
1047 #endif
1048 }
1049 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1050 }
1052 // Check for float store
1053 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1054 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1055 }
1057 // Check for float load
1058 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1059 int offset = ra_->reg2offset(src_first);
1060 const char *op_str;
1061 int op;
1062 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1063 op_str = "FLD_D";
1064 op = 0xDD;
1065 } else { // 32-bit load
1066 op_str = "FLD_S";
1067 op = 0xD9;
1068 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1069 }
1070 if( cbuf ) {
1071 emit_opcode (*cbuf, op );
1072 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
1073 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1074 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1075 #ifndef PRODUCT
1076 } else if( !do_size ) {
1077 if( size != 0 ) st->print("\n\t");
1078 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1079 #endif
1080 }
1081 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1082 return size + 3+offset_size+2;
1083 }
1085 // Check for xmm reg-reg copy
1086 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1087 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1088 (src_first+1 == src_second && dst_first+1 == dst_second),
1089 "no non-adjacent float-moves" );
1090 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1091 }
1093 // Check for xmm reg-integer reg copy
1094 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1095 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1096 "no 64 bit float-integer reg moves" );
1097 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1098 }
1100 // Check for xmm store
1101 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1102 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1103 }
1105 // Check for float xmm load
1106 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1107 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1108 }
1110 // Copy from float reg to xmm reg
1111 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1112 // copy to the top of stack from floating point reg
1113 // and use LEA to preserve flags
1114 if( cbuf ) {
1115 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1116 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1117 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1118 emit_d8(*cbuf,0xF8);
1119 #ifndef PRODUCT
1120 } else if( !do_size ) {
1121 if( size != 0 ) st->print("\n\t");
1122 st->print("LEA ESP,[ESP-8]");
1123 #endif
1124 }
1125 size += 4;
1127 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1129 // Copy from the temp memory to the xmm reg.
1130 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1132 if( cbuf ) {
1133 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1134 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1135 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1136 emit_d8(*cbuf,0x08);
1137 #ifndef PRODUCT
1138 } else if( !do_size ) {
1139 if( size != 0 ) st->print("\n\t");
1140 st->print("LEA ESP,[ESP+8]");
1141 #endif
1142 }
1143 size += 4;
1144 return size;
1145 }
1147 assert( size > 0, "missed a case" );
1149 // --------------------------------------------------------------------
1150 // Check for second bits still needing moving.
1151 if( src_second == dst_second )
1152 return size; // Self copy; no move
1153 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1155 // Check for second word int-int move
1156 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1157 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1159 // Check for second word integer store
1160 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1161 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1163 // Check for second word integer load
1164 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1165 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1168 Unimplemented();
1169 }
1171 #ifndef PRODUCT
1172 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1173 implementation( NULL, ra_, false, st );
1174 }
1175 #endif
1177 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1178 implementation( &cbuf, ra_, false, NULL );
1179 }
1181 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1182 return implementation( NULL, ra_, true, NULL );
1183 }
1185 //=============================================================================
1186 #ifndef PRODUCT
1187 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1188 st->print("NOP \t# %d bytes pad for loops and calls", _count);
1189 }
1190 #endif
1192 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1193 MacroAssembler _masm(&cbuf);
1194 __ nop(_count);
1195 }
1197 uint MachNopNode::size(PhaseRegAlloc *) const {
1198 return _count;
1199 }
1202 //=============================================================================
1203 #ifndef PRODUCT
1204 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1205 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1206 int reg = ra_->get_reg_first(this);
1207 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1208 }
1209 #endif
1211 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1212 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1213 int reg = ra_->get_encode(this);
1214 if( offset >= 128 ) {
1215 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1216 emit_rm(cbuf, 0x2, reg, 0x04);
1217 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1218 emit_d32(cbuf, offset);
1219 }
1220 else {
1221 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1222 emit_rm(cbuf, 0x1, reg, 0x04);
1223 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1224 emit_d8(cbuf, offset);
1225 }
1226 }
1228 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1229 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1230 if( offset >= 128 ) {
1231 return 7;
1232 }
1233 else {
1234 return 4;
1235 }
1236 }
1238 //=============================================================================
1240 // emit call stub, compiled java to interpreter
1241 void emit_java_to_interp(CodeBuffer &cbuf ) {
1242 // Stub is fixed up when the corresponding call is converted from calling
1243 // compiled code to calling interpreted code.
1244 // mov rbx,0
1245 // jmp -1
1247 address mark = cbuf.insts_mark(); // get mark within main instrs section
1249 // Note that the code buffer's insts_mark is always relative to insts.
1250 // That's why we must use the macroassembler to generate a stub.
1251 MacroAssembler _masm(&cbuf);
1253 address base =
1254 __ start_a_stub(Compile::MAX_stubs_size);
1255 if (base == NULL) return; // CodeBuffer::expand failed
1256 // static stub relocation stores the instruction address of the call
1257 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1258 // static stub relocation also tags the methodOop in the code-stream.
1259 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1260 // This is recognized as unresolved by relocs/nativeInst/ic code
1261 __ jump(RuntimeAddress(__ pc()));
1263 __ end_a_stub();
1264 // Update current stubs pointer and restore insts_end.
1265 }
1266 // size of call stub, compiled java to interpretor
1267 uint size_java_to_interp() {
1268 return 10; // movl; jmp
1269 }
1270 // relocation entries for call stub, compiled java to interpretor
1271 uint reloc_java_to_interp() {
1272 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1273 }
1275 //=============================================================================
1276 #ifndef PRODUCT
1277 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1278 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1279 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1280 st->print_cr("\tNOP");
1281 st->print_cr("\tNOP");
1282 if( !OptoBreakpoint )
1283 st->print_cr("\tNOP");
1284 }
1285 #endif
1287 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1288 MacroAssembler masm(&cbuf);
1289 #ifdef ASSERT
1290 uint insts_size = cbuf.insts_size();
1291 #endif
1292 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1293 masm.jump_cc(Assembler::notEqual,
1294 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1295 /* WARNING these NOPs are critical so that verified entry point is properly
1296 aligned for patching by NativeJump::patch_verified_entry() */
1297 int nops_cnt = 2;
1298 if( !OptoBreakpoint ) // Leave space for int3
1299 nops_cnt += 1;
1300 masm.nop(nops_cnt);
1302 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1303 }
1305 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1306 return OptoBreakpoint ? 11 : 12;
1307 }
1310 //=============================================================================
1311 uint size_exception_handler() {
1312 // NativeCall instruction size is the same as NativeJump.
1313 // exception handler starts out as jump and can be patched to
1314 // a call be deoptimization. (4932387)
1315 // Note that this value is also credited (in output.cpp) to
1316 // the size of the code section.
1317 return NativeJump::instruction_size;
1318 }
1320 // Emit exception handler code. Stuff framesize into a register
1321 // and call a VM stub routine.
1322 int emit_exception_handler(CodeBuffer& cbuf) {
1324 // Note that the code buffer's insts_mark is always relative to insts.
1325 // That's why we must use the macroassembler to generate a handler.
1326 MacroAssembler _masm(&cbuf);
1327 address base =
1328 __ start_a_stub(size_exception_handler());
1329 if (base == NULL) return 0; // CodeBuffer::expand failed
1330 int offset = __ offset();
1331 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1332 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1333 __ end_a_stub();
1334 return offset;
1335 }
1337 uint size_deopt_handler() {
1338 // NativeCall instruction size is the same as NativeJump.
1339 // exception handler starts out as jump and can be patched to
1340 // a call be deoptimization. (4932387)
1341 // Note that this value is also credited (in output.cpp) to
1342 // the size of the code section.
1343 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1344 }
1346 // Emit deopt handler code.
1347 int emit_deopt_handler(CodeBuffer& cbuf) {
1349 // Note that the code buffer's insts_mark is always relative to insts.
1350 // That's why we must use the macroassembler to generate a handler.
1351 MacroAssembler _masm(&cbuf);
1352 address base =
1353 __ start_a_stub(size_exception_handler());
1354 if (base == NULL) return 0; // CodeBuffer::expand failed
1355 int offset = __ offset();
1356 InternalAddress here(__ pc());
1357 __ pushptr(here.addr());
1359 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1360 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1361 __ end_a_stub();
1362 return offset;
1363 }
1366 const bool Matcher::match_rule_supported(int opcode) {
1367 if (!has_match_rule(opcode))
1368 return false;
1370 return true; // Per default match rules are supported.
1371 }
1373 int Matcher::regnum_to_fpu_offset(int regnum) {
1374 return regnum - 32; // The FP registers are in the second chunk
1375 }
1377 // This is UltraSparc specific, true just means we have fast l2f conversion
1378 const bool Matcher::convL2FSupported(void) {
1379 return true;
1380 }
1382 // Vector width in bytes
1383 const uint Matcher::vector_width_in_bytes(void) {
1384 return UseSSE >= 2 ? 8 : 0;
1385 }
1387 // Vector ideal reg
1388 const uint Matcher::vector_ideal_reg(void) {
1389 return Op_RegD;
1390 }
1392 // Is this branch offset short enough that a short branch can be used?
1393 //
1394 // NOTE: If the platform does not provide any short branch variants, then
1395 // this method should return false for offset 0.
1396 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1397 // The passed offset is relative to address of the branch.
1398 // On 86 a branch displacement is calculated relative to address
1399 // of a next instruction.
1400 offset -= br_size;
1402 // the short version of jmpConUCF2 contains multiple branches,
1403 // making the reach slightly less
1404 if (rule == jmpConUCF2_rule)
1405 return (-126 <= offset && offset <= 125);
1406 return (-128 <= offset && offset <= 127);
1407 }
1409 const bool Matcher::isSimpleConstant64(jlong value) {
1410 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1411 return false;
1412 }
1414 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1415 const bool Matcher::init_array_count_is_in_bytes = false;
1417 // Threshold size for cleararray.
1418 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1420 // Needs 2 CMOV's for longs.
1421 const int Matcher::long_cmove_cost() { return 1; }
1423 // No CMOVF/CMOVD with SSE/SSE2
1424 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1426 // Should the Matcher clone shifts on addressing modes, expecting them to
1427 // be subsumed into complex addressing expressions or compute them into
1428 // registers? True for Intel but false for most RISCs
1429 const bool Matcher::clone_shift_expressions = true;
1431 // Do we need to mask the count passed to shift instructions or does
1432 // the cpu only look at the lower 5/6 bits anyway?
1433 const bool Matcher::need_masked_shift_count = false;
1435 bool Matcher::narrow_oop_use_complex_address() {
1436 ShouldNotCallThis();
1437 return true;
1438 }
1441 // Is it better to copy float constants, or load them directly from memory?
1442 // Intel can load a float constant from a direct address, requiring no
1443 // extra registers. Most RISCs will have to materialize an address into a
1444 // register first, so they would do better to copy the constant from stack.
1445 const bool Matcher::rematerialize_float_constants = true;
1447 // If CPU can load and store mis-aligned doubles directly then no fixup is
1448 // needed. Else we split the double into 2 integer pieces and move it
1449 // piece-by-piece. Only happens when passing doubles into C code as the
1450 // Java calling convention forces doubles to be aligned.
1451 const bool Matcher::misaligned_doubles_ok = true;
1454 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1455 // Get the memory operand from the node
1456 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1457 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1458 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1459 uint opcnt = 1; // First operand
1460 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1461 while( idx >= skipped+num_edges ) {
1462 skipped += num_edges;
1463 opcnt++; // Bump operand count
1464 assert( opcnt < numopnds, "Accessing non-existent operand" );
1465 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1466 }
1468 MachOper *memory = node->_opnds[opcnt];
1469 MachOper *new_memory = NULL;
1470 switch (memory->opcode()) {
1471 case DIRECT:
1472 case INDOFFSET32X:
1473 // No transformation necessary.
1474 return;
1475 case INDIRECT:
1476 new_memory = new (C) indirect_win95_safeOper( );
1477 break;
1478 case INDOFFSET8:
1479 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1480 break;
1481 case INDOFFSET32:
1482 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1483 break;
1484 case INDINDEXOFFSET:
1485 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1486 break;
1487 case INDINDEXSCALE:
1488 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1489 break;
1490 case INDINDEXSCALEOFFSET:
1491 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1492 break;
1493 case LOAD_LONG_INDIRECT:
1494 case LOAD_LONG_INDOFFSET32:
1495 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1496 return;
1497 default:
1498 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1499 return;
1500 }
1501 node->_opnds[opcnt] = new_memory;
1502 }
1504 // Advertise here if the CPU requires explicit rounding operations
1505 // to implement the UseStrictFP mode.
1506 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1508 // Are floats conerted to double when stored to stack during deoptimization?
1509 // On x32 it is stored with convertion only when FPU is used for floats.
1510 bool Matcher::float_in_double() { return (UseSSE == 0); }
1512 // Do ints take an entire long register or just half?
1513 const bool Matcher::int_in_long = false;
1515 // Return whether or not this register is ever used as an argument. This
1516 // function is used on startup to build the trampoline stubs in generateOptoStub.
1517 // Registers not mentioned will be killed by the VM call in the trampoline, and
1518 // arguments in those registers not be available to the callee.
1519 bool Matcher::can_be_java_arg( int reg ) {
1520 if( reg == ECX_num || reg == EDX_num ) return true;
1521 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1522 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1523 return false;
1524 }
1526 bool Matcher::is_spillable_arg( int reg ) {
1527 return can_be_java_arg(reg);
1528 }
1530 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1531 // Use hardware integer DIV instruction when
1532 // it is faster than a code which use multiply.
1533 // Only when constant divisor fits into 32 bit
1534 // (min_jint is excluded to get only correct
1535 // positive 32 bit values from negative).
1536 return VM_Version::has_fast_idiv() &&
1537 (divisor == (int)divisor && divisor != min_jint);
1538 }
1540 // Register for DIVI projection of divmodI
1541 RegMask Matcher::divI_proj_mask() {
1542 return EAX_REG_mask();
1543 }
1545 // Register for MODI projection of divmodI
1546 RegMask Matcher::modI_proj_mask() {
1547 return EDX_REG_mask();
1548 }
1550 // Register for DIVL projection of divmodL
1551 RegMask Matcher::divL_proj_mask() {
1552 ShouldNotReachHere();
1553 return RegMask();
1554 }
1556 // Register for MODL projection of divmodL
1557 RegMask Matcher::modL_proj_mask() {
1558 ShouldNotReachHere();
1559 return RegMask();
1560 }
1562 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1563 return EBP_REG_mask();
1564 }
1566 // Returns true if the high 32 bits of the value is known to be zero.
1567 bool is_operand_hi32_zero(Node* n) {
1568 int opc = n->Opcode();
1569 if (opc == Op_LoadUI2L) {
1570 return true;
1571 }
1572 if (opc == Op_AndL) {
1573 Node* o2 = n->in(2);
1574 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1575 return true;
1576 }
1577 }
1578 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1579 return true;
1580 }
1581 return false;
1582 }
1584 %}
1586 //----------ENCODING BLOCK-----------------------------------------------------
1587 // This block specifies the encoding classes used by the compiler to output
1588 // byte streams. Encoding classes generate functions which are called by
1589 // Machine Instruction Nodes in order to generate the bit encoding of the
1590 // instruction. Operands specify their base encoding interface with the
1591 // interface keyword. There are currently supported four interfaces,
1592 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1593 // operand to generate a function which returns its register number when
1594 // queried. CONST_INTER causes an operand to generate a function which
1595 // returns the value of the constant when queried. MEMORY_INTER causes an
1596 // operand to generate four functions which return the Base Register, the
1597 // Index Register, the Scale Value, and the Offset Value of the operand when
1598 // queried. COND_INTER causes an operand to generate six functions which
1599 // return the encoding code (ie - encoding bits for the instruction)
1600 // associated with each basic boolean condition for a conditional instruction.
1601 // Instructions specify two basic values for encoding. They use the
1602 // ins_encode keyword to specify their encoding class (which must be one of
1603 // the class names specified in the encoding block), and they use the
1604 // opcode keyword to specify, in order, their primary, secondary, and
1605 // tertiary opcode. Only the opcode sections which a particular instruction
1606 // needs for encoding need to be specified.
1607 encode %{
1608 // Build emit functions for each basic byte or larger field in the intel
1609 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1610 // code in the enc_class source block. Emit functions will live in the
1611 // main source block for now. In future, we can generalize this by
1612 // adding a syntax that specifies the sizes of fields in an order,
1613 // so that the adlc can build the emit functions automagically
1615 // Emit primary opcode
1616 enc_class OpcP %{
1617 emit_opcode(cbuf, $primary);
1618 %}
1620 // Emit secondary opcode
1621 enc_class OpcS %{
1622 emit_opcode(cbuf, $secondary);
1623 %}
1625 // Emit opcode directly
1626 enc_class Opcode(immI d8) %{
1627 emit_opcode(cbuf, $d8$$constant);
1628 %}
1630 enc_class SizePrefix %{
1631 emit_opcode(cbuf,0x66);
1632 %}
1634 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1635 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1636 %}
1638 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1639 emit_opcode(cbuf,$opcode$$constant);
1640 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1641 %}
1643 enc_class mov_r32_imm0( eRegI dst ) %{
1644 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1645 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1646 %}
1648 enc_class cdq_enc %{
1649 // Full implementation of Java idiv and irem; checks for
1650 // special case as described in JVM spec., p.243 & p.271.
1651 //
1652 // normal case special case
1653 //
1654 // input : rax,: dividend min_int
1655 // reg: divisor -1
1656 //
1657 // output: rax,: quotient (= rax, idiv reg) min_int
1658 // rdx: remainder (= rax, irem reg) 0
1659 //
1660 // Code sequnce:
1661 //
1662 // 81 F8 00 00 00 80 cmp rax,80000000h
1663 // 0F 85 0B 00 00 00 jne normal_case
1664 // 33 D2 xor rdx,edx
1665 // 83 F9 FF cmp rcx,0FFh
1666 // 0F 84 03 00 00 00 je done
1667 // normal_case:
1668 // 99 cdq
1669 // F7 F9 idiv rax,ecx
1670 // done:
1671 //
1672 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1673 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1674 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1675 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1676 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1677 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1678 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1679 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1680 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1681 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1682 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1683 // normal_case:
1684 emit_opcode(cbuf,0x99); // cdq
1685 // idiv (note: must be emitted by the user of this rule)
1686 // normal:
1687 %}
1689 // Dense encoding for older common ops
1690 enc_class Opc_plus(immI opcode, eRegI reg) %{
1691 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1692 %}
1695 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1696 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1697 // Check for 8-bit immediate, and set sign extend bit in opcode
1698 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1699 emit_opcode(cbuf, $primary | 0x02);
1700 }
1701 else { // If 32-bit immediate
1702 emit_opcode(cbuf, $primary);
1703 }
1704 %}
1706 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1707 // Emit primary opcode and set sign-extend bit
1708 // Check for 8-bit immediate, and set sign extend bit in opcode
1709 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1710 emit_opcode(cbuf, $primary | 0x02); }
1711 else { // If 32-bit immediate
1712 emit_opcode(cbuf, $primary);
1713 }
1714 // Emit r/m byte with secondary opcode, after primary opcode.
1715 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1716 %}
1718 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1719 // Check for 8-bit immediate, and set sign extend bit in opcode
1720 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1721 $$$emit8$imm$$constant;
1722 }
1723 else { // If 32-bit immediate
1724 // Output immediate
1725 $$$emit32$imm$$constant;
1726 }
1727 %}
1729 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1730 // Emit primary opcode and set sign-extend bit
1731 // Check for 8-bit immediate, and set sign extend bit in opcode
1732 int con = (int)$imm$$constant; // Throw away top bits
1733 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1734 // Emit r/m byte with secondary opcode, after primary opcode.
1735 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1736 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1737 else emit_d32(cbuf,con);
1738 %}
1740 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1741 // Emit primary opcode and set sign-extend bit
1742 // Check for 8-bit immediate, and set sign extend bit in opcode
1743 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1744 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1745 // Emit r/m byte with tertiary opcode, after primary opcode.
1746 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1747 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1748 else emit_d32(cbuf,con);
1749 %}
1751 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1752 emit_cc(cbuf, $secondary, $dst$$reg );
1753 %}
1755 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1756 int destlo = $dst$$reg;
1757 int desthi = HIGH_FROM_LOW(destlo);
1758 // bswap lo
1759 emit_opcode(cbuf, 0x0F);
1760 emit_cc(cbuf, 0xC8, destlo);
1761 // bswap hi
1762 emit_opcode(cbuf, 0x0F);
1763 emit_cc(cbuf, 0xC8, desthi);
1764 // xchg lo and hi
1765 emit_opcode(cbuf, 0x87);
1766 emit_rm(cbuf, 0x3, destlo, desthi);
1767 %}
1769 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1770 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1771 %}
1773 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1774 $$$emit8$primary;
1775 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1776 %}
1778 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV
1779 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1780 emit_d8(cbuf, op >> 8 );
1781 emit_d8(cbuf, op & 255);
1782 %}
1784 // emulate a CMOV with a conditional branch around a MOV
1785 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1786 // Invert sense of branch from sense of CMOV
1787 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1788 emit_d8( cbuf, $brOffs$$constant );
1789 %}
1791 enc_class enc_PartialSubtypeCheck( ) %{
1792 Register Redi = as_Register(EDI_enc); // result register
1793 Register Reax = as_Register(EAX_enc); // super class
1794 Register Recx = as_Register(ECX_enc); // killed
1795 Register Resi = as_Register(ESI_enc); // sub class
1796 Label miss;
1798 MacroAssembler _masm(&cbuf);
1799 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1800 NULL, &miss,
1801 /*set_cond_codes:*/ true);
1802 if ($primary) {
1803 __ xorptr(Redi, Redi);
1804 }
1805 __ bind(miss);
1806 %}
1808 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1809 MacroAssembler masm(&cbuf);
1810 int start = masm.offset();
1811 if (UseSSE >= 2) {
1812 if (VerifyFPU) {
1813 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1814 }
1815 } else {
1816 // External c_calling_convention expects the FPU stack to be 'clean'.
1817 // Compiled code leaves it dirty. Do cleanup now.
1818 masm.empty_FPU_stack();
1819 }
1820 if (sizeof_FFree_Float_Stack_All == -1) {
1821 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1822 } else {
1823 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1824 }
1825 %}
1827 enc_class Verify_FPU_For_Leaf %{
1828 if( VerifyFPU ) {
1829 MacroAssembler masm(&cbuf);
1830 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1831 }
1832 %}
1834 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1835 // This is the instruction starting address for relocation info.
1836 cbuf.set_insts_mark();
1837 $$$emit8$primary;
1838 // CALL directly to the runtime
1839 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1840 runtime_call_Relocation::spec(), RELOC_IMM32 );
1842 if (UseSSE >= 2) {
1843 MacroAssembler _masm(&cbuf);
1844 BasicType rt = tf()->return_type();
1846 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1847 // A C runtime call where the return value is unused. In SSE2+
1848 // mode the result needs to be removed from the FPU stack. It's
1849 // likely that this function call could be removed by the
1850 // optimizer if the C function is a pure function.
1851 __ ffree(0);
1852 } else if (rt == T_FLOAT) {
1853 __ lea(rsp, Address(rsp, -4));
1854 __ fstp_s(Address(rsp, 0));
1855 __ movflt(xmm0, Address(rsp, 0));
1856 __ lea(rsp, Address(rsp, 4));
1857 } else if (rt == T_DOUBLE) {
1858 __ lea(rsp, Address(rsp, -8));
1859 __ fstp_d(Address(rsp, 0));
1860 __ movdbl(xmm0, Address(rsp, 0));
1861 __ lea(rsp, Address(rsp, 8));
1862 }
1863 }
1864 %}
1867 enc_class pre_call_FPU %{
1868 // If method sets FPU control word restore it here
1869 debug_only(int off0 = cbuf.insts_size());
1870 if( Compile::current()->in_24_bit_fp_mode() ) {
1871 MacroAssembler masm(&cbuf);
1872 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1873 }
1874 debug_only(int off1 = cbuf.insts_size());
1875 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction");
1876 %}
1878 enc_class post_call_FPU %{
1879 // If method sets FPU control word do it here also
1880 if( Compile::current()->in_24_bit_fp_mode() ) {
1881 MacroAssembler masm(&cbuf);
1882 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1883 }
1884 %}
1886 enc_class preserve_SP %{
1887 debug_only(int off0 = cbuf.insts_size());
1888 MacroAssembler _masm(&cbuf);
1889 // RBP is preserved across all calls, even compiled calls.
1890 // Use it to preserve RSP in places where the callee might change the SP.
1891 __ movptr(rbp_mh_SP_save, rsp);
1892 debug_only(int off1 = cbuf.insts_size());
1893 assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
1894 %}
1896 enc_class restore_SP %{
1897 MacroAssembler _masm(&cbuf);
1898 __ movptr(rsp, rbp_mh_SP_save);
1899 %}
1901 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1902 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1903 // who we intended to call.
1904 cbuf.set_insts_mark();
1905 $$$emit8$primary;
1906 if ( !_method ) {
1907 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1908 runtime_call_Relocation::spec(), RELOC_IMM32 );
1909 } else if(_optimized_virtual) {
1910 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1911 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1912 } else {
1913 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1914 static_call_Relocation::spec(), RELOC_IMM32 );
1915 }
1916 if( _method ) { // Emit stub for static call
1917 emit_java_to_interp(cbuf);
1918 }
1919 %}
1921 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1922 // !!!!!
1923 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1924 // emit_call_dynamic_prologue( cbuf );
1925 cbuf.set_insts_mark();
1926 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1927 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1928 address virtual_call_oop_addr = cbuf.insts_mark();
1929 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1930 // who we intended to call.
1931 cbuf.set_insts_mark();
1932 $$$emit8$primary;
1933 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1934 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1935 %}
1937 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1938 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1939 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1941 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1942 cbuf.set_insts_mark();
1943 $$$emit8$primary;
1944 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1945 emit_d8(cbuf, disp); // Displacement
1947 %}
1949 // Following encoding is no longer used, but may be restored if calling
1950 // convention changes significantly.
1951 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1952 //
1953 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1954 // // int ic_reg = Matcher::inline_cache_reg();
1955 // // int ic_encode = Matcher::_regEncode[ic_reg];
1956 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1957 // // int imo_encode = Matcher::_regEncode[imo_reg];
1958 //
1959 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1960 // // // so we load it immediately before the call
1961 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1962 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1963 //
1964 // // xor rbp,ebp
1965 // emit_opcode(cbuf, 0x33);
1966 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1967 //
1968 // // CALL to interpreter.
1969 // cbuf.set_insts_mark();
1970 // $$$emit8$primary;
1971 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1972 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1973 // %}
1975 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1976 $$$emit8$primary;
1977 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1978 $$$emit8$shift$$constant;
1979 %}
1981 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1982 // Load immediate does not have a zero or sign extended version
1983 // for 8-bit immediates
1984 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1985 $$$emit32$src$$constant;
1986 %}
1988 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1989 // Load immediate does not have a zero or sign extended version
1990 // for 8-bit immediates
1991 emit_opcode(cbuf, $primary + $dst$$reg);
1992 $$$emit32$src$$constant;
1993 %}
1995 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1996 // Load immediate does not have a zero or sign extended version
1997 // for 8-bit immediates
1998 int dst_enc = $dst$$reg;
1999 int src_con = $src$$constant & 0x0FFFFFFFFL;
2000 if (src_con == 0) {
2001 // xor dst, dst
2002 emit_opcode(cbuf, 0x33);
2003 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
2004 } else {
2005 emit_opcode(cbuf, $primary + dst_enc);
2006 emit_d32(cbuf, src_con);
2007 }
2008 %}
2010 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
2011 // Load immediate does not have a zero or sign extended version
2012 // for 8-bit immediates
2013 int dst_enc = $dst$$reg + 2;
2014 int src_con = ((julong)($src$$constant)) >> 32;
2015 if (src_con == 0) {
2016 // xor dst, dst
2017 emit_opcode(cbuf, 0x33);
2018 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
2019 } else {
2020 emit_opcode(cbuf, $primary + dst_enc);
2021 emit_d32(cbuf, src_con);
2022 }
2023 %}
2026 // Encode a reg-reg copy. If it is useless, then empty encoding.
2027 enc_class enc_Copy( eRegI dst, eRegI src ) %{
2028 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2029 %}
2031 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
2032 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2033 %}
2035 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
2036 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2037 %}
2039 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2040 $$$emit8$primary;
2041 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2042 %}
2044 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2045 $$$emit8$secondary;
2046 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2047 %}
2049 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2050 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2051 %}
2053 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2054 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2055 %}
2057 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
2058 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2059 %}
2061 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2062 // Output immediate
2063 $$$emit32$src$$constant;
2064 %}
2066 enc_class Con32F_as_bits(immF src) %{ // storeF_imm
2067 // Output Float immediate bits
2068 jfloat jf = $src$$constant;
2069 int jf_as_bits = jint_cast( jf );
2070 emit_d32(cbuf, jf_as_bits);
2071 %}
2073 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm
2074 // Output Float immediate bits
2075 jfloat jf = $src$$constant;
2076 int jf_as_bits = jint_cast( jf );
2077 emit_d32(cbuf, jf_as_bits);
2078 %}
2080 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2081 // Output immediate
2082 $$$emit16$src$$constant;
2083 %}
2085 enc_class Con_d32(immI src) %{
2086 emit_d32(cbuf,$src$$constant);
2087 %}
2089 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2090 // Output immediate memory reference
2091 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2092 emit_d32(cbuf, 0x00);
2093 %}
2095 enc_class lock_prefix( ) %{
2096 if( os::is_MP() )
2097 emit_opcode(cbuf,0xF0); // [Lock]
2098 %}
2100 // Cmp-xchg long value.
2101 // Note: we need to swap rbx, and rcx before and after the
2102 // cmpxchg8 instruction because the instruction uses
2103 // rcx as the high order word of the new value to store but
2104 // our register encoding uses rbx,.
2105 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2107 // XCHG rbx,ecx
2108 emit_opcode(cbuf,0x87);
2109 emit_opcode(cbuf,0xD9);
2110 // [Lock]
2111 if( os::is_MP() )
2112 emit_opcode(cbuf,0xF0);
2113 // CMPXCHG8 [Eptr]
2114 emit_opcode(cbuf,0x0F);
2115 emit_opcode(cbuf,0xC7);
2116 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2117 // XCHG rbx,ecx
2118 emit_opcode(cbuf,0x87);
2119 emit_opcode(cbuf,0xD9);
2120 %}
2122 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2123 // [Lock]
2124 if( os::is_MP() )
2125 emit_opcode(cbuf,0xF0);
2127 // CMPXCHG [Eptr]
2128 emit_opcode(cbuf,0x0F);
2129 emit_opcode(cbuf,0xB1);
2130 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2131 %}
2133 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2134 int res_encoding = $res$$reg;
2136 // MOV res,0
2137 emit_opcode( cbuf, 0xB8 + res_encoding);
2138 emit_d32( cbuf, 0 );
2139 // JNE,s fail
2140 emit_opcode(cbuf,0x75);
2141 emit_d8(cbuf, 5 );
2142 // MOV res,1
2143 emit_opcode( cbuf, 0xB8 + res_encoding);
2144 emit_d32( cbuf, 1 );
2145 // fail:
2146 %}
2148 enc_class set_instruction_start( ) %{
2149 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2150 %}
2152 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2153 int reg_encoding = $ereg$$reg;
2154 int base = $mem$$base;
2155 int index = $mem$$index;
2156 int scale = $mem$$scale;
2157 int displace = $mem$$disp;
2158 bool disp_is_oop = $mem->disp_is_oop();
2159 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2160 %}
2162 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2163 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2164 int base = $mem$$base;
2165 int index = $mem$$index;
2166 int scale = $mem$$scale;
2167 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2168 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2169 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2170 %}
2172 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2173 int r1, r2;
2174 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2175 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2176 emit_opcode(cbuf,0x0F);
2177 emit_opcode(cbuf,$tertiary);
2178 emit_rm(cbuf, 0x3, r1, r2);
2179 emit_d8(cbuf,$cnt$$constant);
2180 emit_d8(cbuf,$primary);
2181 emit_rm(cbuf, 0x3, $secondary, r1);
2182 emit_d8(cbuf,$cnt$$constant);
2183 %}
2185 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2186 emit_opcode( cbuf, 0x8B ); // Move
2187 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2188 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2189 emit_d8(cbuf,$primary);
2190 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2191 emit_d8(cbuf,$cnt$$constant-32);
2192 }
2193 emit_d8(cbuf,$primary);
2194 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2195 emit_d8(cbuf,31);
2196 %}
2198 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2199 int r1, r2;
2200 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2201 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2203 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2204 emit_rm(cbuf, 0x3, r1, r2);
2205 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2206 emit_opcode(cbuf,$primary);
2207 emit_rm(cbuf, 0x3, $secondary, r1);
2208 emit_d8(cbuf,$cnt$$constant-32);
2209 }
2210 emit_opcode(cbuf,0x33); // XOR r2,r2
2211 emit_rm(cbuf, 0x3, r2, r2);
2212 %}
2214 // Clone of RegMem but accepts an extra parameter to access each
2215 // half of a double in memory; it never needs relocation info.
2216 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2217 emit_opcode(cbuf,$opcode$$constant);
2218 int reg_encoding = $rm_reg$$reg;
2219 int base = $mem$$base;
2220 int index = $mem$$index;
2221 int scale = $mem$$scale;
2222 int displace = $mem$$disp + $disp_for_half$$constant;
2223 bool disp_is_oop = false;
2224 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2225 %}
2227 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2228 //
2229 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2230 // and it never needs relocation information.
2231 // Frequently used to move data between FPU's Stack Top and memory.
2232 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2233 int rm_byte_opcode = $rm_opcode$$constant;
2234 int base = $mem$$base;
2235 int index = $mem$$index;
2236 int scale = $mem$$scale;
2237 int displace = $mem$$disp;
2238 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2239 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2240 %}
2242 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2243 int rm_byte_opcode = $rm_opcode$$constant;
2244 int base = $mem$$base;
2245 int index = $mem$$index;
2246 int scale = $mem$$scale;
2247 int displace = $mem$$disp;
2248 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2249 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2250 %}
2252 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2253 int reg_encoding = $dst$$reg;
2254 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2255 int index = 0x04; // 0x04 indicates no index
2256 int scale = 0x00; // 0x00 indicates no scale
2257 int displace = $src1$$constant; // 0x00 indicates no displacement
2258 bool disp_is_oop = false;
2259 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2260 %}
2262 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2263 // Compare dst,src
2264 emit_opcode(cbuf,0x3B);
2265 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2266 // jmp dst < src around move
2267 emit_opcode(cbuf,0x7C);
2268 emit_d8(cbuf,2);
2269 // move dst,src
2270 emit_opcode(cbuf,0x8B);
2271 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2272 %}
2274 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2275 // Compare dst,src
2276 emit_opcode(cbuf,0x3B);
2277 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2278 // jmp dst > src around move
2279 emit_opcode(cbuf,0x7F);
2280 emit_d8(cbuf,2);
2281 // move dst,src
2282 emit_opcode(cbuf,0x8B);
2283 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2284 %}
2286 enc_class enc_FP_store(memory mem, regD src) %{
2287 // If src is FPR1, we can just FST to store it.
2288 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2289 int reg_encoding = 0x2; // Just store
2290 int base = $mem$$base;
2291 int index = $mem$$index;
2292 int scale = $mem$$scale;
2293 int displace = $mem$$disp;
2294 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2295 if( $src$$reg != FPR1L_enc ) {
2296 reg_encoding = 0x3; // Store & pop
2297 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2298 emit_d8( cbuf, 0xC0-1+$src$$reg );
2299 }
2300 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2301 emit_opcode(cbuf,$primary);
2302 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2303 %}
2305 enc_class neg_reg(eRegI dst) %{
2306 // NEG $dst
2307 emit_opcode(cbuf,0xF7);
2308 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2309 %}
2311 enc_class setLT_reg(eCXRegI dst) %{
2312 // SETLT $dst
2313 emit_opcode(cbuf,0x0F);
2314 emit_opcode(cbuf,0x9C);
2315 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2316 %}
2318 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2319 int tmpReg = $tmp$$reg;
2321 // SUB $p,$q
2322 emit_opcode(cbuf,0x2B);
2323 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2324 // SBB $tmp,$tmp
2325 emit_opcode(cbuf,0x1B);
2326 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2327 // AND $tmp,$y
2328 emit_opcode(cbuf,0x23);
2329 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2330 // ADD $p,$tmp
2331 emit_opcode(cbuf,0x03);
2332 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2333 %}
2335 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2336 int tmpReg = $tmp$$reg;
2338 // SUB $p,$q
2339 emit_opcode(cbuf,0x2B);
2340 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2341 // SBB $tmp,$tmp
2342 emit_opcode(cbuf,0x1B);
2343 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2344 // AND $tmp,$y
2345 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2346 emit_opcode(cbuf,0x23);
2347 int reg_encoding = tmpReg;
2348 int base = $mem$$base;
2349 int index = $mem$$index;
2350 int scale = $mem$$scale;
2351 int displace = $mem$$disp;
2352 bool disp_is_oop = $mem->disp_is_oop();
2353 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2354 // ADD $p,$tmp
2355 emit_opcode(cbuf,0x03);
2356 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2357 %}
2359 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2360 // TEST shift,32
2361 emit_opcode(cbuf,0xF7);
2362 emit_rm(cbuf, 0x3, 0, ECX_enc);
2363 emit_d32(cbuf,0x20);
2364 // JEQ,s small
2365 emit_opcode(cbuf, 0x74);
2366 emit_d8(cbuf, 0x04);
2367 // MOV $dst.hi,$dst.lo
2368 emit_opcode( cbuf, 0x8B );
2369 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2370 // CLR $dst.lo
2371 emit_opcode(cbuf, 0x33);
2372 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2373 // small:
2374 // SHLD $dst.hi,$dst.lo,$shift
2375 emit_opcode(cbuf,0x0F);
2376 emit_opcode(cbuf,0xA5);
2377 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2378 // SHL $dst.lo,$shift"
2379 emit_opcode(cbuf,0xD3);
2380 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2381 %}
2383 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2384 // TEST shift,32
2385 emit_opcode(cbuf,0xF7);
2386 emit_rm(cbuf, 0x3, 0, ECX_enc);
2387 emit_d32(cbuf,0x20);
2388 // JEQ,s small
2389 emit_opcode(cbuf, 0x74);
2390 emit_d8(cbuf, 0x04);
2391 // MOV $dst.lo,$dst.hi
2392 emit_opcode( cbuf, 0x8B );
2393 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2394 // CLR $dst.hi
2395 emit_opcode(cbuf, 0x33);
2396 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2397 // small:
2398 // SHRD $dst.lo,$dst.hi,$shift
2399 emit_opcode(cbuf,0x0F);
2400 emit_opcode(cbuf,0xAD);
2401 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2402 // SHR $dst.hi,$shift"
2403 emit_opcode(cbuf,0xD3);
2404 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2405 %}
2407 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2408 // TEST shift,32
2409 emit_opcode(cbuf,0xF7);
2410 emit_rm(cbuf, 0x3, 0, ECX_enc);
2411 emit_d32(cbuf,0x20);
2412 // JEQ,s small
2413 emit_opcode(cbuf, 0x74);
2414 emit_d8(cbuf, 0x05);
2415 // MOV $dst.lo,$dst.hi
2416 emit_opcode( cbuf, 0x8B );
2417 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2418 // SAR $dst.hi,31
2419 emit_opcode(cbuf, 0xC1);
2420 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2421 emit_d8(cbuf, 0x1F );
2422 // small:
2423 // SHRD $dst.lo,$dst.hi,$shift
2424 emit_opcode(cbuf,0x0F);
2425 emit_opcode(cbuf,0xAD);
2426 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2427 // SAR $dst.hi,$shift"
2428 emit_opcode(cbuf,0xD3);
2429 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2430 %}
2433 // ----------------- Encodings for floating point unit -----------------
2434 // May leave result in FPU-TOS or FPU reg depending on opcodes
2435 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV
2436 $$$emit8$primary;
2437 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2438 %}
2440 // Pop argument in FPR0 with FSTP ST(0)
2441 enc_class PopFPU() %{
2442 emit_opcode( cbuf, 0xDD );
2443 emit_d8( cbuf, 0xD8 );
2444 %}
2446 // !!!!! equivalent to Pop_Reg_F
2447 enc_class Pop_Reg_D( regD dst ) %{
2448 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2449 emit_d8( cbuf, 0xD8+$dst$$reg );
2450 %}
2452 enc_class Push_Reg_D( regD dst ) %{
2453 emit_opcode( cbuf, 0xD9 );
2454 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2455 %}
2457 enc_class strictfp_bias1( regD dst ) %{
2458 emit_opcode( cbuf, 0xDB ); // FLD m80real
2459 emit_opcode( cbuf, 0x2D );
2460 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2461 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2462 emit_opcode( cbuf, 0xC8+$dst$$reg );
2463 %}
2465 enc_class strictfp_bias2( regD dst ) %{
2466 emit_opcode( cbuf, 0xDB ); // FLD m80real
2467 emit_opcode( cbuf, 0x2D );
2468 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2469 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2470 emit_opcode( cbuf, 0xC8+$dst$$reg );
2471 %}
2473 // Special case for moving an integer register to a stack slot.
2474 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2475 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2476 %}
2478 // Special case for moving a register to a stack slot.
2479 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2480 // Opcode already emitted
2481 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2482 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2483 emit_d32(cbuf, $dst$$disp); // Displacement
2484 %}
2486 // Push the integer in stackSlot 'src' onto FP-stack
2487 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2488 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2489 %}
2491 // Push the float in stackSlot 'src' onto FP-stack
2492 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src]
2493 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp );
2494 %}
2496 // Push the double in stackSlot 'src' onto FP-stack
2497 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src]
2498 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp );
2499 %}
2501 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2502 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2503 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2504 %}
2506 // Same as Pop_Mem_F except for opcode
2507 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2508 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2509 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2510 %}
2512 enc_class Pop_Reg_F( regF dst ) %{
2513 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2514 emit_d8( cbuf, 0xD8+$dst$$reg );
2515 %}
2517 enc_class Push_Reg_F( regF dst ) %{
2518 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2519 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2520 %}
2522 // Push FPU's float to a stack-slot, and pop FPU-stack
2523 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{
2524 int pop = 0x02;
2525 if ($src$$reg != FPR1L_enc) {
2526 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2527 emit_d8( cbuf, 0xC0-1+$src$$reg );
2528 pop = 0x03;
2529 }
2530 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2531 %}
2533 // Push FPU's double to a stack-slot, and pop FPU-stack
2534 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{
2535 int pop = 0x02;
2536 if ($src$$reg != FPR1L_enc) {
2537 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2538 emit_d8( cbuf, 0xC0-1+$src$$reg );
2539 pop = 0x03;
2540 }
2541 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2542 %}
2544 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2545 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{
2546 int pop = 0xD0 - 1; // -1 since we skip FLD
2547 if ($src$$reg != FPR1L_enc) {
2548 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2549 emit_d8( cbuf, 0xC0-1+$src$$reg );
2550 pop = 0xD8;
2551 }
2552 emit_opcode( cbuf, 0xDD );
2553 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2554 %}
2557 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{
2558 MacroAssembler masm(&cbuf);
2559 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg
2560 masm.fmul( $src2$$reg+0); // value at TOS
2561 masm.fadd( $src$$reg+0); // value at TOS
2562 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store
2563 %}
2566 enc_class Push_Reg_Mod_D( regD dst, regD src) %{
2567 // load dst in FPR0
2568 emit_opcode( cbuf, 0xD9 );
2569 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2570 if ($src$$reg != FPR1L_enc) {
2571 // fincstp
2572 emit_opcode (cbuf, 0xD9);
2573 emit_opcode (cbuf, 0xF7);
2574 // swap src with FPR1:
2575 // FXCH FPR1 with src
2576 emit_opcode(cbuf, 0xD9);
2577 emit_d8(cbuf, 0xC8-1+$src$$reg );
2578 // fdecstp
2579 emit_opcode (cbuf, 0xD9);
2580 emit_opcode (cbuf, 0xF6);
2581 }
2582 %}
2584 enc_class Push_ModD_encoding(regXD src0, regXD src1) %{
2585 MacroAssembler _masm(&cbuf);
2586 __ subptr(rsp, 8);
2587 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2588 __ fld_d(Address(rsp, 0));
2589 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2590 __ fld_d(Address(rsp, 0));
2591 %}
2593 enc_class Push_ModX_encoding(regX src0, regX src1) %{
2594 MacroAssembler _masm(&cbuf);
2595 __ subptr(rsp, 4);
2596 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2597 __ fld_s(Address(rsp, 0));
2598 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2599 __ fld_s(Address(rsp, 0));
2600 %}
2602 enc_class Push_ResultXD(regXD dst) %{
2603 MacroAssembler _masm(&cbuf);
2604 __ fstp_d(Address(rsp, 0));
2605 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2606 __ addptr(rsp, 8);
2607 %}
2609 enc_class Push_ResultX(regX dst, immI d8) %{
2610 MacroAssembler _masm(&cbuf);
2611 __ fstp_s(Address(rsp, 0));
2612 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2613 __ addptr(rsp, $d8$$constant);
2614 %}
2616 enc_class Push_SrcXD(regXD src) %{
2617 MacroAssembler _masm(&cbuf);
2618 __ subptr(rsp, 8);
2619 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2620 __ fld_d(Address(rsp, 0));
2621 %}
2623 enc_class push_stack_temp_qword() %{
2624 MacroAssembler _masm(&cbuf);
2625 __ subptr(rsp, 8);
2626 %}
2628 enc_class pop_stack_temp_qword() %{
2629 MacroAssembler _masm(&cbuf);
2630 __ addptr(rsp, 8);
2631 %}
2633 enc_class push_xmm_to_fpr1(regXD src) %{
2634 MacroAssembler _masm(&cbuf);
2635 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2636 __ fld_d(Address(rsp, 0));
2637 %}
2639 // Compute X^Y using Intel's fast hardware instructions, if possible.
2640 // Otherwise return a NaN.
2641 enc_class pow_exp_core_encoding %{
2642 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X))
2643 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q
2644 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q
2645 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q)
2646 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q)
2647 emit_opcode(cbuf,0x1C);
2648 emit_d8(cbuf,0x24);
2649 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1
2650 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1
2651 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q)
2652 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q)
2653 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false);
2654 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask
2655 emit_rm(cbuf, 0x3, 0x0, ECX_enc);
2656 emit_d32(cbuf,0xFFFFF800);
2657 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias
2658 emit_rm(cbuf, 0x3, 0x0, EAX_enc);
2659 emit_d32(cbuf,1023);
2660 emit_opcode(cbuf,0x8B); // mov rbx,eax
2661 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc);
2662 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position
2663 emit_rm(cbuf,0x3,0x4,EAX_enc);
2664 emit_d8(cbuf,20);
2665 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow
2666 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc);
2667 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX
2668 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc);
2669 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word
2670 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false);
2671 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q)
2672 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2673 emit_d32(cbuf,0);
2674 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q
2675 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false);
2676 %}
2678 // enc_class Pop_Reg_Mod_D( regD dst, regD src)
2679 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X()
2681 enc_class Push_Result_Mod_D( regD src) %{
2682 if ($src$$reg != FPR1L_enc) {
2683 // fincstp
2684 emit_opcode (cbuf, 0xD9);
2685 emit_opcode (cbuf, 0xF7);
2686 // FXCH FPR1 with src
2687 emit_opcode(cbuf, 0xD9);
2688 emit_d8(cbuf, 0xC8-1+$src$$reg );
2689 // fdecstp
2690 emit_opcode (cbuf, 0xD9);
2691 emit_opcode (cbuf, 0xF6);
2692 }
2693 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2694 // // FSTP FPR$dst$$reg
2695 // emit_opcode( cbuf, 0xDD );
2696 // emit_d8( cbuf, 0xD8+$dst$$reg );
2697 %}
2699 enc_class fnstsw_sahf_skip_parity() %{
2700 // fnstsw ax
2701 emit_opcode( cbuf, 0xDF );
2702 emit_opcode( cbuf, 0xE0 );
2703 // sahf
2704 emit_opcode( cbuf, 0x9E );
2705 // jnp ::skip
2706 emit_opcode( cbuf, 0x7B );
2707 emit_opcode( cbuf, 0x05 );
2708 %}
2710 enc_class emitModD() %{
2711 // fprem must be iterative
2712 // :: loop
2713 // fprem
2714 emit_opcode( cbuf, 0xD9 );
2715 emit_opcode( cbuf, 0xF8 );
2716 // wait
2717 emit_opcode( cbuf, 0x9b );
2718 // fnstsw ax
2719 emit_opcode( cbuf, 0xDF );
2720 emit_opcode( cbuf, 0xE0 );
2721 // sahf
2722 emit_opcode( cbuf, 0x9E );
2723 // jp ::loop
2724 emit_opcode( cbuf, 0x0F );
2725 emit_opcode( cbuf, 0x8A );
2726 emit_opcode( cbuf, 0xF4 );
2727 emit_opcode( cbuf, 0xFF );
2728 emit_opcode( cbuf, 0xFF );
2729 emit_opcode( cbuf, 0xFF );
2730 %}
2732 enc_class fpu_flags() %{
2733 // fnstsw_ax
2734 emit_opcode( cbuf, 0xDF);
2735 emit_opcode( cbuf, 0xE0);
2736 // test ax,0x0400
2737 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2738 emit_opcode( cbuf, 0xA9 );
2739 emit_d16 ( cbuf, 0x0400 );
2740 // // // This sequence works, but stalls for 12-16 cycles on PPro
2741 // // test rax,0x0400
2742 // emit_opcode( cbuf, 0xA9 );
2743 // emit_d32 ( cbuf, 0x00000400 );
2744 //
2745 // jz exit (no unordered comparison)
2746 emit_opcode( cbuf, 0x74 );
2747 emit_d8 ( cbuf, 0x02 );
2748 // mov ah,1 - treat as LT case (set carry flag)
2749 emit_opcode( cbuf, 0xB4 );
2750 emit_d8 ( cbuf, 0x01 );
2751 // sahf
2752 emit_opcode( cbuf, 0x9E);
2753 %}
2755 enc_class cmpF_P6_fixup() %{
2756 // Fixup the integer flags in case comparison involved a NaN
2757 //
2758 // JNP exit (no unordered comparison, P-flag is set by NaN)
2759 emit_opcode( cbuf, 0x7B );
2760 emit_d8 ( cbuf, 0x03 );
2761 // MOV AH,1 - treat as LT case (set carry flag)
2762 emit_opcode( cbuf, 0xB4 );
2763 emit_d8 ( cbuf, 0x01 );
2764 // SAHF
2765 emit_opcode( cbuf, 0x9E);
2766 // NOP // target for branch to avoid branch to branch
2767 emit_opcode( cbuf, 0x90);
2768 %}
2770 // fnstsw_ax();
2771 // sahf();
2772 // movl(dst, nan_result);
2773 // jcc(Assembler::parity, exit);
2774 // movl(dst, less_result);
2775 // jcc(Assembler::below, exit);
2776 // movl(dst, equal_result);
2777 // jcc(Assembler::equal, exit);
2778 // movl(dst, greater_result);
2780 // less_result = 1;
2781 // greater_result = -1;
2782 // equal_result = 0;
2783 // nan_result = -1;
2785 enc_class CmpF_Result(eRegI dst) %{
2786 // fnstsw_ax();
2787 emit_opcode( cbuf, 0xDF);
2788 emit_opcode( cbuf, 0xE0);
2789 // sahf
2790 emit_opcode( cbuf, 0x9E);
2791 // movl(dst, nan_result);
2792 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2793 emit_d32( cbuf, -1 );
2794 // jcc(Assembler::parity, exit);
2795 emit_opcode( cbuf, 0x7A );
2796 emit_d8 ( cbuf, 0x13 );
2797 // movl(dst, less_result);
2798 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2799 emit_d32( cbuf, -1 );
2800 // jcc(Assembler::below, exit);
2801 emit_opcode( cbuf, 0x72 );
2802 emit_d8 ( cbuf, 0x0C );
2803 // movl(dst, equal_result);
2804 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2805 emit_d32( cbuf, 0 );
2806 // jcc(Assembler::equal, exit);
2807 emit_opcode( cbuf, 0x74 );
2808 emit_d8 ( cbuf, 0x05 );
2809 // movl(dst, greater_result);
2810 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2811 emit_d32( cbuf, 1 );
2812 %}
2815 // Compare the longs and set flags
2816 // BROKEN! Do Not use as-is
2817 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2818 // CMP $src1.hi,$src2.hi
2819 emit_opcode( cbuf, 0x3B );
2820 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2821 // JNE,s done
2822 emit_opcode(cbuf,0x75);
2823 emit_d8(cbuf, 2 );
2824 // CMP $src1.lo,$src2.lo
2825 emit_opcode( cbuf, 0x3B );
2826 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2827 // done:
2828 %}
2830 enc_class convert_int_long( regL dst, eRegI src ) %{
2831 // mov $dst.lo,$src
2832 int dst_encoding = $dst$$reg;
2833 int src_encoding = $src$$reg;
2834 encode_Copy( cbuf, dst_encoding , src_encoding );
2835 // mov $dst.hi,$src
2836 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2837 // sar $dst.hi,31
2838 emit_opcode( cbuf, 0xC1 );
2839 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2840 emit_d8(cbuf, 0x1F );
2841 %}
2843 enc_class convert_long_double( eRegL src ) %{
2844 // push $src.hi
2845 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2846 // push $src.lo
2847 emit_opcode(cbuf, 0x50+$src$$reg );
2848 // fild 64-bits at [SP]
2849 emit_opcode(cbuf,0xdf);
2850 emit_d8(cbuf, 0x6C);
2851 emit_d8(cbuf, 0x24);
2852 emit_d8(cbuf, 0x00);
2853 // pop stack
2854 emit_opcode(cbuf, 0x83); // add SP, #8
2855 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2856 emit_d8(cbuf, 0x8);
2857 %}
2859 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2860 // IMUL EDX:EAX,$src1
2861 emit_opcode( cbuf, 0xF7 );
2862 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2863 // SAR EDX,$cnt-32
2864 int shift_count = ((int)$cnt$$constant) - 32;
2865 if (shift_count > 0) {
2866 emit_opcode(cbuf, 0xC1);
2867 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2868 emit_d8(cbuf, shift_count);
2869 }
2870 %}
2872 // this version doesn't have add sp, 8
2873 enc_class convert_long_double2( eRegL src ) %{
2874 // push $src.hi
2875 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2876 // push $src.lo
2877 emit_opcode(cbuf, 0x50+$src$$reg );
2878 // fild 64-bits at [SP]
2879 emit_opcode(cbuf,0xdf);
2880 emit_d8(cbuf, 0x6C);
2881 emit_d8(cbuf, 0x24);
2882 emit_d8(cbuf, 0x00);
2883 %}
2885 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2886 // Basic idea: long = (long)int * (long)int
2887 // IMUL EDX:EAX, src
2888 emit_opcode( cbuf, 0xF7 );
2889 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2890 %}
2892 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2893 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2894 // MUL EDX:EAX, src
2895 emit_opcode( cbuf, 0xF7 );
2896 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2897 %}
2899 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
2900 // Basic idea: lo(result) = lo(x_lo * y_lo)
2901 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2902 // MOV $tmp,$src.lo
2903 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2904 // IMUL $tmp,EDX
2905 emit_opcode( cbuf, 0x0F );
2906 emit_opcode( cbuf, 0xAF );
2907 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2908 // MOV EDX,$src.hi
2909 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2910 // IMUL EDX,EAX
2911 emit_opcode( cbuf, 0x0F );
2912 emit_opcode( cbuf, 0xAF );
2913 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2914 // ADD $tmp,EDX
2915 emit_opcode( cbuf, 0x03 );
2916 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2917 // MUL EDX:EAX,$src.lo
2918 emit_opcode( cbuf, 0xF7 );
2919 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2920 // ADD EDX,ESI
2921 emit_opcode( cbuf, 0x03 );
2922 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2923 %}
2925 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
2926 // Basic idea: lo(result) = lo(src * y_lo)
2927 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2928 // IMUL $tmp,EDX,$src
2929 emit_opcode( cbuf, 0x6B );
2930 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2931 emit_d8( cbuf, (int)$src$$constant );
2932 // MOV EDX,$src
2933 emit_opcode(cbuf, 0xB8 + EDX_enc);
2934 emit_d32( cbuf, (int)$src$$constant );
2935 // MUL EDX:EAX,EDX
2936 emit_opcode( cbuf, 0xF7 );
2937 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2938 // ADD EDX,ESI
2939 emit_opcode( cbuf, 0x03 );
2940 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2941 %}
2943 enc_class long_div( eRegL src1, eRegL src2 ) %{
2944 // PUSH src1.hi
2945 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2946 // PUSH src1.lo
2947 emit_opcode(cbuf, 0x50+$src1$$reg );
2948 // PUSH src2.hi
2949 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2950 // PUSH src2.lo
2951 emit_opcode(cbuf, 0x50+$src2$$reg );
2952 // CALL directly to the runtime
2953 cbuf.set_insts_mark();
2954 emit_opcode(cbuf,0xE8); // Call into runtime
2955 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2956 // Restore stack
2957 emit_opcode(cbuf, 0x83); // add SP, #framesize
2958 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2959 emit_d8(cbuf, 4*4);
2960 %}
2962 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2963 // PUSH src1.hi
2964 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2965 // PUSH src1.lo
2966 emit_opcode(cbuf, 0x50+$src1$$reg );
2967 // PUSH src2.hi
2968 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2969 // PUSH src2.lo
2970 emit_opcode(cbuf, 0x50+$src2$$reg );
2971 // CALL directly to the runtime
2972 cbuf.set_insts_mark();
2973 emit_opcode(cbuf,0xE8); // Call into runtime
2974 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2975 // Restore stack
2976 emit_opcode(cbuf, 0x83); // add SP, #framesize
2977 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2978 emit_d8(cbuf, 4*4);
2979 %}
2981 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
2982 // MOV $tmp,$src.lo
2983 emit_opcode(cbuf, 0x8B);
2984 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2985 // OR $tmp,$src.hi
2986 emit_opcode(cbuf, 0x0B);
2987 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2988 %}
2990 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2991 // CMP $src1.lo,$src2.lo
2992 emit_opcode( cbuf, 0x3B );
2993 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2994 // JNE,s skip
2995 emit_cc(cbuf, 0x70, 0x5);
2996 emit_d8(cbuf,2);
2997 // CMP $src1.hi,$src2.hi
2998 emit_opcode( cbuf, 0x3B );
2999 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
3000 %}
3002 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
3003 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
3004 emit_opcode( cbuf, 0x3B );
3005 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3006 // MOV $tmp,$src1.hi
3007 emit_opcode( cbuf, 0x8B );
3008 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
3009 // SBB $tmp,$src2.hi\t! Compute flags for long compare
3010 emit_opcode( cbuf, 0x1B );
3011 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
3012 %}
3014 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
3015 // XOR $tmp,$tmp
3016 emit_opcode(cbuf,0x33); // XOR
3017 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
3018 // CMP $tmp,$src.lo
3019 emit_opcode( cbuf, 0x3B );
3020 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
3021 // SBB $tmp,$src.hi
3022 emit_opcode( cbuf, 0x1B );
3023 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
3024 %}
3026 // Sniff, sniff... smells like Gnu Superoptimizer
3027 enc_class neg_long( eRegL dst ) %{
3028 emit_opcode(cbuf,0xF7); // NEG hi
3029 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3030 emit_opcode(cbuf,0xF7); // NEG lo
3031 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
3032 emit_opcode(cbuf,0x83); // SBB hi,0
3033 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3034 emit_d8 (cbuf,0 );
3035 %}
3038 // Because the transitions from emitted code to the runtime
3039 // monitorenter/exit helper stubs are so slow it's critical that
3040 // we inline both the stack-locking fast-path and the inflated fast path.
3041 //
3042 // See also: cmpFastLock and cmpFastUnlock.
3043 //
3044 // What follows is a specialized inline transliteration of the code
3045 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
3046 // another option would be to emit TrySlowEnter and TrySlowExit methods
3047 // at startup-time. These methods would accept arguments as
3048 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
3049 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
3050 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
3051 // In practice, however, the # of lock sites is bounded and is usually small.
3052 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
3053 // if the processor uses simple bimodal branch predictors keyed by EIP
3054 // Since the helper routines would be called from multiple synchronization
3055 // sites.
3056 //
3057 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
3058 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
3059 // to those specialized methods. That'd give us a mostly platform-independent
3060 // implementation that the JITs could optimize and inline at their pleasure.
3061 // Done correctly, the only time we'd need to cross to native could would be
3062 // to park() or unpark() threads. We'd also need a few more unsafe operators
3063 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
3064 // (b) explicit barriers or fence operations.
3065 //
3066 // TODO:
3067 //
3068 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
3069 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
3070 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
3071 // the lock operators would typically be faster than reifying Self.
3072 //
3073 // * Ideally I'd define the primitives as:
3074 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3075 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3076 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3077 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3078 // Furthermore the register assignments are overconstrained, possibly resulting in
3079 // sub-optimal code near the synchronization site.
3080 //
3081 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3082 // Alternately, use a better sp-proximity test.
3083 //
3084 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3085 // Either one is sufficient to uniquely identify a thread.
3086 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3087 //
3088 // * Intrinsify notify() and notifyAll() for the common cases where the
3089 // object is locked by the calling thread but the waitlist is empty.
3090 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3091 //
3092 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3093 // But beware of excessive branch density on AMD Opterons.
3094 //
3095 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3096 // or failure of the fast-path. If the fast-path fails then we pass
3097 // control to the slow-path, typically in C. In Fast_Lock and
3098 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3099 // will emit a conditional branch immediately after the node.
3100 // So we have branches to branches and lots of ICC.ZF games.
3101 // Instead, it might be better to have C2 pass a "FailureLabel"
3102 // into Fast_Lock and Fast_Unlock. In the case of success, control
3103 // will drop through the node. ICC.ZF is undefined at exit.
3104 // In the case of failure, the node will branch directly to the
3105 // FailureLabel
3108 // obj: object to lock
3109 // box: on-stack box address (displaced header location) - KILLED
3110 // rax,: tmp -- KILLED
3111 // scr: tmp -- KILLED
3112 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3114 Register objReg = as_Register($obj$$reg);
3115 Register boxReg = as_Register($box$$reg);
3116 Register tmpReg = as_Register($tmp$$reg);
3117 Register scrReg = as_Register($scr$$reg);
3119 // Ensure the register assignents are disjoint
3120 guarantee (objReg != boxReg, "") ;
3121 guarantee (objReg != tmpReg, "") ;
3122 guarantee (objReg != scrReg, "") ;
3123 guarantee (boxReg != tmpReg, "") ;
3124 guarantee (boxReg != scrReg, "") ;
3125 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3127 MacroAssembler masm(&cbuf);
3129 if (_counters != NULL) {
3130 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3131 }
3132 if (EmitSync & 1) {
3133 // set box->dhw = unused_mark (3)
3134 // Force all sync thru slow-path: slow_enter() and slow_exit()
3135 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3136 masm.cmpptr (rsp, (int32_t)0) ;
3137 } else
3138 if (EmitSync & 2) {
3139 Label DONE_LABEL ;
3140 if (UseBiasedLocking) {
3141 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3142 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3143 }
3145 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3146 masm.orptr (tmpReg, 0x1);
3147 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3148 if (os::is_MP()) { masm.lock(); }
3149 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3150 masm.jcc(Assembler::equal, DONE_LABEL);
3151 // Recursive locking
3152 masm.subptr(tmpReg, rsp);
3153 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3154 masm.movptr(Address(boxReg, 0), tmpReg);
3155 masm.bind(DONE_LABEL) ;
3156 } else {
3157 // Possible cases that we'll encounter in fast_lock
3158 // ------------------------------------------------
3159 // * Inflated
3160 // -- unlocked
3161 // -- Locked
3162 // = by self
3163 // = by other
3164 // * biased
3165 // -- by Self
3166 // -- by other
3167 // * neutral
3168 // * stack-locked
3169 // -- by self
3170 // = sp-proximity test hits
3171 // = sp-proximity test generates false-negative
3172 // -- by other
3173 //
3175 Label IsInflated, DONE_LABEL, PopDone ;
3177 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3178 // order to reduce the number of conditional branches in the most common cases.
3179 // Beware -- there's a subtle invariant that fetch of the markword
3180 // at [FETCH], below, will never observe a biased encoding (*101b).
3181 // If this invariant is not held we risk exclusion (safety) failure.
3182 if (UseBiasedLocking && !UseOptoBiasInlining) {
3183 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3184 }
3186 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3187 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3188 masm.jccb (Assembler::notZero, IsInflated) ;
3190 // Attempt stack-locking ...
3191 masm.orptr (tmpReg, 0x1);
3192 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3193 if (os::is_MP()) { masm.lock(); }
3194 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3195 if (_counters != NULL) {
3196 masm.cond_inc32(Assembler::equal,
3197 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3198 }
3199 masm.jccb (Assembler::equal, DONE_LABEL);
3201 // Recursive locking
3202 masm.subptr(tmpReg, rsp);
3203 masm.andptr(tmpReg, 0xFFFFF003 );
3204 masm.movptr(Address(boxReg, 0), tmpReg);
3205 if (_counters != NULL) {
3206 masm.cond_inc32(Assembler::equal,
3207 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3208 }
3209 masm.jmp (DONE_LABEL) ;
3211 masm.bind (IsInflated) ;
3213 // The object is inflated.
3214 //
3215 // TODO-FIXME: eliminate the ugly use of manifest constants:
3216 // Use markOopDesc::monitor_value instead of "2".
3217 // use markOop::unused_mark() instead of "3".
3218 // The tmpReg value is an objectMonitor reference ORed with
3219 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3220 // objectmonitor pointer by masking off the "2" bit or we can just
3221 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3222 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3223 //
3224 // I use the latter as it avoids AGI stalls.
3225 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3226 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3227 //
3228 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3230 // boxReg refers to the on-stack BasicLock in the current frame.
3231 // We'd like to write:
3232 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3233 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3234 // additional latency as we have another ST in the store buffer that must drain.
3236 if (EmitSync & 8192) {
3237 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3238 masm.get_thread (scrReg) ;
3239 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3240 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3241 if (os::is_MP()) { masm.lock(); }
3242 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3243 } else
3244 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3245 masm.movptr(scrReg, boxReg) ;
3246 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3248 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3249 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3250 // prefetchw [eax + Offset(_owner)-2]
3251 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3252 }
3254 if ((EmitSync & 64) == 0) {
3255 // Optimistic form: consider XORL tmpReg,tmpReg
3256 masm.movptr(tmpReg, NULL_WORD) ;
3257 } else {
3258 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3259 // Test-And-CAS instead of CAS
3260 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3261 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3262 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3263 }
3265 // Appears unlocked - try to swing _owner from null to non-null.
3266 // Ideally, I'd manifest "Self" with get_thread and then attempt
3267 // to CAS the register containing Self into m->Owner.
3268 // But we don't have enough registers, so instead we can either try to CAS
3269 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3270 // we later store "Self" into m->Owner. Transiently storing a stack address
3271 // (rsp or the address of the box) into m->owner is harmless.
3272 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3273 if (os::is_MP()) { masm.lock(); }
3274 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3275 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3276 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3277 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3278 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3279 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3281 // If the CAS fails we can either retry or pass control to the slow-path.
3282 // We use the latter tactic.
3283 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3284 // If the CAS was successful ...
3285 // Self has acquired the lock
3286 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3287 // Intentional fall-through into DONE_LABEL ...
3288 } else {
3289 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3290 masm.movptr(boxReg, tmpReg) ;
3292 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3293 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3294 // prefetchw [eax + Offset(_owner)-2]
3295 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3296 }
3298 if ((EmitSync & 64) == 0) {
3299 // Optimistic form
3300 masm.xorptr (tmpReg, tmpReg) ;
3301 } else {
3302 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3303 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3304 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3305 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3306 }
3308 // Appears unlocked - try to swing _owner from null to non-null.
3309 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3310 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3311 masm.get_thread (scrReg) ;
3312 if (os::is_MP()) { masm.lock(); }
3313 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3315 // If the CAS fails we can either retry or pass control to the slow-path.
3316 // We use the latter tactic.
3317 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3318 // If the CAS was successful ...
3319 // Self has acquired the lock
3320 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3321 // Intentional fall-through into DONE_LABEL ...
3322 }
3324 // DONE_LABEL is a hot target - we'd really like to place it at the
3325 // start of cache line by padding with NOPs.
3326 // See the AMD and Intel software optimization manuals for the
3327 // most efficient "long" NOP encodings.
3328 // Unfortunately none of our alignment mechanisms suffice.
3329 masm.bind(DONE_LABEL);
3331 // Avoid branch-to-branch on AMD processors
3332 // This appears to be superstition.
3333 if (EmitSync & 32) masm.nop() ;
3336 // At DONE_LABEL the icc ZFlag is set as follows ...
3337 // Fast_Unlock uses the same protocol.
3338 // ZFlag == 1 -> Success
3339 // ZFlag == 0 -> Failure - force control through the slow-path
3340 }
3341 %}
3343 // obj: object to unlock
3344 // box: box address (displaced header location), killed. Must be EAX.
3345 // rbx,: killed tmp; cannot be obj nor box.
3346 //
3347 // Some commentary on balanced locking:
3348 //
3349 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3350 // Methods that don't have provably balanced locking are forced to run in the
3351 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3352 // The interpreter provides two properties:
3353 // I1: At return-time the interpreter automatically and quietly unlocks any
3354 // objects acquired the current activation (frame). Recall that the
3355 // interpreter maintains an on-stack list of locks currently held by
3356 // a frame.
3357 // I2: If a method attempts to unlock an object that is not held by the
3358 // the frame the interpreter throws IMSX.
3359 //
3360 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3361 // B() doesn't have provably balanced locking so it runs in the interpreter.
3362 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3363 // is still locked by A().
3364 //
3365 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3366 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3367 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3368 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3370 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3372 Register objReg = as_Register($obj$$reg);
3373 Register boxReg = as_Register($box$$reg);
3374 Register tmpReg = as_Register($tmp$$reg);
3376 guarantee (objReg != boxReg, "") ;
3377 guarantee (objReg != tmpReg, "") ;
3378 guarantee (boxReg != tmpReg, "") ;
3379 guarantee (boxReg == as_Register(EAX_enc), "") ;
3380 MacroAssembler masm(&cbuf);
3382 if (EmitSync & 4) {
3383 // Disable - inhibit all inlining. Force control through the slow-path
3384 masm.cmpptr (rsp, 0) ;
3385 } else
3386 if (EmitSync & 8) {
3387 Label DONE_LABEL ;
3388 if (UseBiasedLocking) {
3389 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3390 }
3391 // classic stack-locking code ...
3392 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3393 masm.testptr(tmpReg, tmpReg) ;
3394 masm.jcc (Assembler::zero, DONE_LABEL) ;
3395 if (os::is_MP()) { masm.lock(); }
3396 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3397 masm.bind(DONE_LABEL);
3398 } else {
3399 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3401 // Critically, the biased locking test must have precedence over
3402 // and appear before the (box->dhw == 0) recursive stack-lock test.
3403 if (UseBiasedLocking && !UseOptoBiasInlining) {
3404 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3405 }
3407 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3408 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3409 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3411 masm.testptr(tmpReg, 0x02) ; // Inflated?
3412 masm.jccb (Assembler::zero, Stacked) ;
3414 masm.bind (Inflated) ;
3415 // It's inflated.
3416 // Despite our balanced locking property we still check that m->_owner == Self
3417 // as java routines or native JNI code called by this thread might
3418 // have released the lock.
3419 // Refer to the comments in synchronizer.cpp for how we might encode extra
3420 // state in _succ so we can avoid fetching EntryList|cxq.
3421 //
3422 // I'd like to add more cases in fast_lock() and fast_unlock() --
3423 // such as recursive enter and exit -- but we have to be wary of
3424 // I$ bloat, T$ effects and BP$ effects.
3425 //
3426 // If there's no contention try a 1-0 exit. That is, exit without
3427 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3428 // we detect and recover from the race that the 1-0 exit admits.
3429 //
3430 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3431 // before it STs null into _owner, releasing the lock. Updates
3432 // to data protected by the critical section must be visible before
3433 // we drop the lock (and thus before any other thread could acquire
3434 // the lock and observe the fields protected by the lock).
3435 // IA32's memory-model is SPO, so STs are ordered with respect to
3436 // each other and there's no need for an explicit barrier (fence).
3437 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3439 masm.get_thread (boxReg) ;
3440 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3441 // prefetchw [ebx + Offset(_owner)-2]
3442 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3443 }
3445 // Note that we could employ various encoding schemes to reduce
3446 // the number of loads below (currently 4) to just 2 or 3.
3447 // Refer to the comments in synchronizer.cpp.
3448 // In practice the chain of fetches doesn't seem to impact performance, however.
3449 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3450 // Attempt to reduce branch density - AMD's branch predictor.
3451 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3452 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3453 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3454 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3455 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3456 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3457 masm.jmpb (DONE_LABEL) ;
3458 } else {
3459 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3460 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3461 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3462 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3463 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3464 masm.jccb (Assembler::notZero, CheckSucc) ;
3465 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3466 masm.jmpb (DONE_LABEL) ;
3467 }
3469 // The Following code fragment (EmitSync & 65536) improves the performance of
3470 // contended applications and contended synchronization microbenchmarks.
3471 // Unfortunately the emission of the code - even though not executed - causes regressions
3472 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3473 // with an equal number of never-executed NOPs results in the same regression.
3474 // We leave it off by default.
3476 if ((EmitSync & 65536) != 0) {
3477 Label LSuccess, LGoSlowPath ;
3479 masm.bind (CheckSucc) ;
3481 // Optional pre-test ... it's safe to elide this
3482 if ((EmitSync & 16) == 0) {
3483 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3484 masm.jccb (Assembler::zero, LGoSlowPath) ;
3485 }
3487 // We have a classic Dekker-style idiom:
3488 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3489 // There are a number of ways to implement the barrier:
3490 // (1) lock:andl &m->_owner, 0
3491 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3492 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3493 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3494 // (2) If supported, an explicit MFENCE is appealing.
3495 // In older IA32 processors MFENCE is slower than lock:add or xchg
3496 // particularly if the write-buffer is full as might be the case if
3497 // if stores closely precede the fence or fence-equivalent instruction.
3498 // In more modern implementations MFENCE appears faster, however.
3499 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3500 // The $lines underlying the top-of-stack should be in M-state.
3501 // The locked add instruction is serializing, of course.
3502 // (4) Use xchg, which is serializing
3503 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3504 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3505 // The integer condition codes will tell us if succ was 0.
3506 // Since _succ and _owner should reside in the same $line and
3507 // we just stored into _owner, it's likely that the $line
3508 // remains in M-state for the lock:orl.
3509 //
3510 // We currently use (3), although it's likely that switching to (2)
3511 // is correct for the future.
3513 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3514 if (os::is_MP()) {
3515 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3516 masm.mfence();
3517 } else {
3518 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3519 }
3520 }
3521 // Ratify _succ remains non-null
3522 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3523 masm.jccb (Assembler::notZero, LSuccess) ;
3525 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3526 if (os::is_MP()) { masm.lock(); }
3527 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3528 masm.jccb (Assembler::notEqual, LSuccess) ;
3529 // Since we're low on registers we installed rsp as a placeholding in _owner.
3530 // Now install Self over rsp. This is safe as we're transitioning from
3531 // non-null to non=null
3532 masm.get_thread (boxReg) ;
3533 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3534 // Intentional fall-through into LGoSlowPath ...
3536 masm.bind (LGoSlowPath) ;
3537 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3538 masm.jmpb (DONE_LABEL) ;
3540 masm.bind (LSuccess) ;
3541 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3542 masm.jmpb (DONE_LABEL) ;
3543 }
3545 masm.bind (Stacked) ;
3546 // It's not inflated and it's not recursively stack-locked and it's not biased.
3547 // It must be stack-locked.
3548 // Try to reset the header to displaced header.
3549 // The "box" value on the stack is stable, so we can reload
3550 // and be assured we observe the same value as above.
3551 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3552 if (os::is_MP()) { masm.lock(); }
3553 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3554 // Intention fall-thru into DONE_LABEL
3557 // DONE_LABEL is a hot target - we'd really like to place it at the
3558 // start of cache line by padding with NOPs.
3559 // See the AMD and Intel software optimization manuals for the
3560 // most efficient "long" NOP encodings.
3561 // Unfortunately none of our alignment mechanisms suffice.
3562 if ((EmitSync & 65536) == 0) {
3563 masm.bind (CheckSucc) ;
3564 }
3565 masm.bind(DONE_LABEL);
3567 // Avoid branch to branch on AMD processors
3568 if (EmitSync & 32768) { masm.nop() ; }
3569 }
3570 %}
3573 enc_class enc_pop_rdx() %{
3574 emit_opcode(cbuf,0x5A);
3575 %}
3577 enc_class enc_rethrow() %{
3578 cbuf.set_insts_mark();
3579 emit_opcode(cbuf, 0xE9); // jmp entry
3580 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3581 runtime_call_Relocation::spec(), RELOC_IMM32 );
3582 %}
3585 // Convert a double to an int. Java semantics require we do complex
3586 // manglelations in the corner cases. So we set the rounding mode to
3587 // 'zero', store the darned double down as an int, and reset the
3588 // rounding mode to 'nearest'. The hardware throws an exception which
3589 // patches up the correct value directly to the stack.
3590 enc_class D2I_encoding( regD src ) %{
3591 // Flip to round-to-zero mode. We attempted to allow invalid-op
3592 // exceptions here, so that a NAN or other corner-case value will
3593 // thrown an exception (but normal values get converted at full speed).
3594 // However, I2C adapters and other float-stack manglers leave pending
3595 // invalid-op exceptions hanging. We would have to clear them before
3596 // enabling them and that is more expensive than just testing for the
3597 // invalid value Intel stores down in the corner cases.
3598 emit_opcode(cbuf,0xD9); // FLDCW trunc
3599 emit_opcode(cbuf,0x2D);
3600 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3601 // Allocate a word
3602 emit_opcode(cbuf,0x83); // SUB ESP,4
3603 emit_opcode(cbuf,0xEC);
3604 emit_d8(cbuf,0x04);
3605 // Encoding assumes a double has been pushed into FPR0.
3606 // Store down the double as an int, popping the FPU stack
3607 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3608 emit_opcode(cbuf,0x1C);
3609 emit_d8(cbuf,0x24);
3610 // Restore the rounding mode; mask the exception
3611 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3612 emit_opcode(cbuf,0x2D);
3613 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3614 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3615 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3617 // Load the converted int; adjust CPU stack
3618 emit_opcode(cbuf,0x58); // POP EAX
3619 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3620 emit_d32 (cbuf,0x80000000); // 0x80000000
3621 emit_opcode(cbuf,0x75); // JNE around_slow_call
3622 emit_d8 (cbuf,0x07); // Size of slow_call
3623 // Push src onto stack slow-path
3624 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3625 emit_d8 (cbuf,0xC0-1+$src$$reg );
3626 // CALL directly to the runtime
3627 cbuf.set_insts_mark();
3628 emit_opcode(cbuf,0xE8); // Call into runtime
3629 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3630 // Carry on here...
3631 %}
3633 enc_class D2L_encoding( regD src ) %{
3634 emit_opcode(cbuf,0xD9); // FLDCW trunc
3635 emit_opcode(cbuf,0x2D);
3636 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3637 // Allocate a word
3638 emit_opcode(cbuf,0x83); // SUB ESP,8
3639 emit_opcode(cbuf,0xEC);
3640 emit_d8(cbuf,0x08);
3641 // Encoding assumes a double has been pushed into FPR0.
3642 // Store down the double as a long, popping the FPU stack
3643 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3644 emit_opcode(cbuf,0x3C);
3645 emit_d8(cbuf,0x24);
3646 // Restore the rounding mode; mask the exception
3647 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3648 emit_opcode(cbuf,0x2D);
3649 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3650 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3651 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3653 // Load the converted int; adjust CPU stack
3654 emit_opcode(cbuf,0x58); // POP EAX
3655 emit_opcode(cbuf,0x5A); // POP EDX
3656 emit_opcode(cbuf,0x81); // CMP EDX,imm
3657 emit_d8 (cbuf,0xFA); // rdx
3658 emit_d32 (cbuf,0x80000000); // 0x80000000
3659 emit_opcode(cbuf,0x75); // JNE around_slow_call
3660 emit_d8 (cbuf,0x07+4); // Size of slow_call
3661 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3662 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3663 emit_opcode(cbuf,0x75); // JNE around_slow_call
3664 emit_d8 (cbuf,0x07); // Size of slow_call
3665 // Push src onto stack slow-path
3666 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3667 emit_d8 (cbuf,0xC0-1+$src$$reg );
3668 // CALL directly to the runtime
3669 cbuf.set_insts_mark();
3670 emit_opcode(cbuf,0xE8); // Call into runtime
3671 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3672 // Carry on here...
3673 %}
3675 enc_class FMul_ST_reg( eRegF src1 ) %{
3676 // Operand was loaded from memory into fp ST (stack top)
3677 // FMUL ST,$src /* D8 C8+i */
3678 emit_opcode(cbuf, 0xD8);
3679 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3680 %}
3682 enc_class FAdd_ST_reg( eRegF src2 ) %{
3683 // FADDP ST,src2 /* D8 C0+i */
3684 emit_opcode(cbuf, 0xD8);
3685 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3686 //could use FADDP src2,fpST /* DE C0+i */
3687 %}
3689 enc_class FAddP_reg_ST( eRegF src2 ) %{
3690 // FADDP src2,ST /* DE C0+i */
3691 emit_opcode(cbuf, 0xDE);
3692 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3693 %}
3695 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{
3696 // Operand has been loaded into fp ST (stack top)
3697 // FSUB ST,$src1
3698 emit_opcode(cbuf, 0xD8);
3699 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3701 // FDIV
3702 emit_opcode(cbuf, 0xD8);
3703 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3704 %}
3706 enc_class MulFAddF (eRegF src1, eRegF src2) %{
3707 // Operand was loaded from memory into fp ST (stack top)
3708 // FADD ST,$src /* D8 C0+i */
3709 emit_opcode(cbuf, 0xD8);
3710 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3712 // FMUL ST,src2 /* D8 C*+i */
3713 emit_opcode(cbuf, 0xD8);
3714 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3715 %}
3718 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{
3719 // Operand was loaded from memory into fp ST (stack top)
3720 // FADD ST,$src /* D8 C0+i */
3721 emit_opcode(cbuf, 0xD8);
3722 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3724 // FMULP src2,ST /* DE C8+i */
3725 emit_opcode(cbuf, 0xDE);
3726 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3727 %}
3729 // Atomically load the volatile long
3730 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3731 emit_opcode(cbuf,0xDF);
3732 int rm_byte_opcode = 0x05;
3733 int base = $mem$$base;
3734 int index = $mem$$index;
3735 int scale = $mem$$scale;
3736 int displace = $mem$$disp;
3737 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
3738 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
3739 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3740 %}
3742 // Volatile Store Long. Must be atomic, so move it into
3743 // the FP TOS and then do a 64-bit FIST. Has to probe the
3744 // target address before the store (for null-ptr checks)
3745 // so the memory operand is used twice in the encoding.
3746 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3747 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3748 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3749 emit_opcode(cbuf,0xDF);
3750 int rm_byte_opcode = 0x07;
3751 int base = $mem$$base;
3752 int index = $mem$$index;
3753 int scale = $mem$$scale;
3754 int displace = $mem$$disp;
3755 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
3756 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
3757 %}
3759 // Safepoint Poll. This polls the safepoint page, and causes an
3760 // exception if it is not readable. Unfortunately, it kills the condition code
3761 // in the process
3762 // We current use TESTL [spp],EDI
3763 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3765 enc_class Safepoint_Poll() %{
3766 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3767 emit_opcode(cbuf,0x85);
3768 emit_rm (cbuf, 0x0, 0x7, 0x5);
3769 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3770 %}
3771 %}
3774 //----------FRAME--------------------------------------------------------------
3775 // Definition of frame structure and management information.
3776 //
3777 // S T A C K L A Y O U T Allocators stack-slot number
3778 // | (to get allocators register number
3779 // G Owned by | | v add OptoReg::stack0())
3780 // r CALLER | |
3781 // o | +--------+ pad to even-align allocators stack-slot
3782 // w V | pad0 | numbers; owned by CALLER
3783 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3784 // h ^ | in | 5
3785 // | | args | 4 Holes in incoming args owned by SELF
3786 // | | | | 3
3787 // | | +--------+
3788 // V | | old out| Empty on Intel, window on Sparc
3789 // | old |preserve| Must be even aligned.
3790 // | SP-+--------+----> Matcher::_old_SP, even aligned
3791 // | | in | 3 area for Intel ret address
3792 // Owned by |preserve| Empty on Sparc.
3793 // SELF +--------+
3794 // | | pad2 | 2 pad to align old SP
3795 // | +--------+ 1
3796 // | | locks | 0
3797 // | +--------+----> OptoReg::stack0(), even aligned
3798 // | | pad1 | 11 pad to align new SP
3799 // | +--------+
3800 // | | | 10
3801 // | | spills | 9 spills
3802 // V | | 8 (pad0 slot for callee)
3803 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3804 // ^ | out | 7
3805 // | | args | 6 Holes in outgoing args owned by CALLEE
3806 // Owned by +--------+
3807 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3808 // | new |preserve| Must be even-aligned.
3809 // | SP-+--------+----> Matcher::_new_SP, even aligned
3810 // | | |
3811 //
3812 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3813 // known from SELF's arguments and the Java calling convention.
3814 // Region 6-7 is determined per call site.
3815 // Note 2: If the calling convention leaves holes in the incoming argument
3816 // area, those holes are owned by SELF. Holes in the outgoing area
3817 // are owned by the CALLEE. Holes should not be nessecary in the
3818 // incoming area, as the Java calling convention is completely under
3819 // the control of the AD file. Doubles can be sorted and packed to
3820 // avoid holes. Holes in the outgoing arguments may be nessecary for
3821 // varargs C calling conventions.
3822 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3823 // even aligned with pad0 as needed.
3824 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3825 // region 6-11 is even aligned; it may be padded out more so that
3826 // the region from SP to FP meets the minimum stack alignment.
3828 frame %{
3829 // What direction does stack grow in (assumed to be same for C & Java)
3830 stack_direction(TOWARDS_LOW);
3832 // These three registers define part of the calling convention
3833 // between compiled code and the interpreter.
3834 inline_cache_reg(EAX); // Inline Cache Register
3835 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3837 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3838 cisc_spilling_operand_name(indOffset32);
3840 // Number of stack slots consumed by locking an object
3841 sync_stack_slots(1);
3843 // Compiled code's Frame Pointer
3844 frame_pointer(ESP);
3845 // Interpreter stores its frame pointer in a register which is
3846 // stored to the stack by I2CAdaptors.
3847 // I2CAdaptors convert from interpreted java to compiled java.
3848 interpreter_frame_pointer(EBP);
3850 // Stack alignment requirement
3851 // Alignment size in bytes (128-bit -> 16 bytes)
3852 stack_alignment(StackAlignmentInBytes);
3854 // Number of stack slots between incoming argument block and the start of
3855 // a new frame. The PROLOG must add this many slots to the stack. The
3856 // EPILOG must remove this many slots. Intel needs one slot for
3857 // return address and one for rbp, (must save rbp)
3858 in_preserve_stack_slots(2+VerifyStackAtCalls);
3860 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3861 // for calls to C. Supports the var-args backing area for register parms.
3862 varargs_C_out_slots_killed(0);
3864 // The after-PROLOG location of the return address. Location of
3865 // return address specifies a type (REG or STACK) and a number
3866 // representing the register number (i.e. - use a register name) or
3867 // stack slot.
3868 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3869 // Otherwise, it is above the locks and verification slot and alignment word
3870 return_addr(STACK - 1 +
3871 round_to(1+VerifyStackAtCalls+
3872 Compile::current()->fixed_slots(),
3873 (StackAlignmentInBytes/wordSize)));
3875 // Body of function which returns an integer array locating
3876 // arguments either in registers or in stack slots. Passed an array
3877 // of ideal registers called "sig" and a "length" count. Stack-slot
3878 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3879 // arguments for a CALLEE. Incoming stack arguments are
3880 // automatically biased by the preserve_stack_slots field above.
3881 calling_convention %{
3882 // No difference between ingoing/outgoing just pass false
3883 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3884 %}
3887 // Body of function which returns an integer array locating
3888 // arguments either in registers or in stack slots. Passed an array
3889 // of ideal registers called "sig" and a "length" count. Stack-slot
3890 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3891 // arguments for a CALLEE. Incoming stack arguments are
3892 // automatically biased by the preserve_stack_slots field above.
3893 c_calling_convention %{
3894 // This is obviously always outgoing
3895 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3896 %}
3898 // Location of C & interpreter return values
3899 c_return_value %{
3900 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3901 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3902 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3904 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3905 // that C functions return float and double results in XMM0.
3906 if( ideal_reg == Op_RegD && UseSSE>=2 )
3907 return OptoRegPair(XMM0b_num,XMM0a_num);
3908 if( ideal_reg == Op_RegF && UseSSE>=2 )
3909 return OptoRegPair(OptoReg::Bad,XMM0a_num);
3911 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3912 %}
3914 // Location of return values
3915 return_value %{
3916 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3917 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3918 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3919 if( ideal_reg == Op_RegD && UseSSE>=2 )
3920 return OptoRegPair(XMM0b_num,XMM0a_num);
3921 if( ideal_reg == Op_RegF && UseSSE>=1 )
3922 return OptoRegPair(OptoReg::Bad,XMM0a_num);
3923 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3924 %}
3926 %}
3928 //----------ATTRIBUTES---------------------------------------------------------
3929 //----------Operand Attributes-------------------------------------------------
3930 op_attrib op_cost(0); // Required cost attribute
3932 //----------Instruction Attributes---------------------------------------------
3933 ins_attrib ins_cost(100); // Required cost attribute
3934 ins_attrib ins_size(8); // Required size attribute (in bits)
3935 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3936 // non-matching short branch variant of some
3937 // long branch?
3938 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3939 // specifies the alignment that some part of the instruction (not
3940 // necessarily the start) requires. If > 1, a compute_padding()
3941 // function must be provided for the instruction
3943 //----------OPERANDS-----------------------------------------------------------
3944 // Operand definitions must precede instruction definitions for correct parsing
3945 // in the ADLC because operands constitute user defined types which are used in
3946 // instruction definitions.
3948 //----------Simple Operands----------------------------------------------------
3949 // Immediate Operands
3950 // Integer Immediate
3951 operand immI() %{
3952 match(ConI);
3954 op_cost(10);
3955 format %{ %}
3956 interface(CONST_INTER);
3957 %}
3959 // Constant for test vs zero
3960 operand immI0() %{
3961 predicate(n->get_int() == 0);
3962 match(ConI);
3964 op_cost(0);
3965 format %{ %}
3966 interface(CONST_INTER);
3967 %}
3969 // Constant for increment
3970 operand immI1() %{
3971 predicate(n->get_int() == 1);
3972 match(ConI);
3974 op_cost(0);
3975 format %{ %}
3976 interface(CONST_INTER);
3977 %}
3979 // Constant for decrement
3980 operand immI_M1() %{
3981 predicate(n->get_int() == -1);
3982 match(ConI);
3984 op_cost(0);
3985 format %{ %}
3986 interface(CONST_INTER);
3987 %}
3989 // Valid scale values for addressing modes
3990 operand immI2() %{
3991 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3992 match(ConI);
3994 format %{ %}
3995 interface(CONST_INTER);
3996 %}
3998 operand immI8() %{
3999 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
4000 match(ConI);
4002 op_cost(5);
4003 format %{ %}
4004 interface(CONST_INTER);
4005 %}
4007 operand immI16() %{
4008 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4009 match(ConI);
4011 op_cost(10);
4012 format %{ %}
4013 interface(CONST_INTER);
4014 %}
4016 // Constant for long shifts
4017 operand immI_32() %{
4018 predicate( n->get_int() == 32 );
4019 match(ConI);
4021 op_cost(0);
4022 format %{ %}
4023 interface(CONST_INTER);
4024 %}
4026 operand immI_1_31() %{
4027 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
4028 match(ConI);
4030 op_cost(0);
4031 format %{ %}
4032 interface(CONST_INTER);
4033 %}
4035 operand immI_32_63() %{
4036 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
4037 match(ConI);
4038 op_cost(0);
4040 format %{ %}
4041 interface(CONST_INTER);
4042 %}
4044 operand immI_1() %{
4045 predicate( n->get_int() == 1 );
4046 match(ConI);
4048 op_cost(0);
4049 format %{ %}
4050 interface(CONST_INTER);
4051 %}
4053 operand immI_2() %{
4054 predicate( n->get_int() == 2 );
4055 match(ConI);
4057 op_cost(0);
4058 format %{ %}
4059 interface(CONST_INTER);
4060 %}
4062 operand immI_3() %{
4063 predicate( n->get_int() == 3 );
4064 match(ConI);
4066 op_cost(0);
4067 format %{ %}
4068 interface(CONST_INTER);
4069 %}
4071 // Pointer Immediate
4072 operand immP() %{
4073 match(ConP);
4075 op_cost(10);
4076 format %{ %}
4077 interface(CONST_INTER);
4078 %}
4080 // NULL Pointer Immediate
4081 operand immP0() %{
4082 predicate( n->get_ptr() == 0 );
4083 match(ConP);
4084 op_cost(0);
4086 format %{ %}
4087 interface(CONST_INTER);
4088 %}
4090 // Long Immediate
4091 operand immL() %{
4092 match(ConL);
4094 op_cost(20);
4095 format %{ %}
4096 interface(CONST_INTER);
4097 %}
4099 // Long Immediate zero
4100 operand immL0() %{
4101 predicate( n->get_long() == 0L );
4102 match(ConL);
4103 op_cost(0);
4105 format %{ %}
4106 interface(CONST_INTER);
4107 %}
4109 // Long Immediate zero
4110 operand immL_M1() %{
4111 predicate( n->get_long() == -1L );
4112 match(ConL);
4113 op_cost(0);
4115 format %{ %}
4116 interface(CONST_INTER);
4117 %}
4119 // Long immediate from 0 to 127.
4120 // Used for a shorter form of long mul by 10.
4121 operand immL_127() %{
4122 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4123 match(ConL);
4124 op_cost(0);
4126 format %{ %}
4127 interface(CONST_INTER);
4128 %}
4130 // Long Immediate: low 32-bit mask
4131 operand immL_32bits() %{
4132 predicate(n->get_long() == 0xFFFFFFFFL);
4133 match(ConL);
4134 op_cost(0);
4136 format %{ %}
4137 interface(CONST_INTER);
4138 %}
4140 // Long Immediate: low 32-bit mask
4141 operand immL32() %{
4142 predicate(n->get_long() == (int)(n->get_long()));
4143 match(ConL);
4144 op_cost(20);
4146 format %{ %}
4147 interface(CONST_INTER);
4148 %}
4150 //Double Immediate zero
4151 operand immD0() %{
4152 // Do additional (and counter-intuitive) test against NaN to work around VC++
4153 // bug that generates code such that NaNs compare equal to 0.0
4154 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4155 match(ConD);
4157 op_cost(5);
4158 format %{ %}
4159 interface(CONST_INTER);
4160 %}
4162 // Double Immediate one
4163 operand immD1() %{
4164 predicate( UseSSE<=1 && n->getd() == 1.0 );
4165 match(ConD);
4167 op_cost(5);
4168 format %{ %}
4169 interface(CONST_INTER);
4170 %}
4172 // Double Immediate
4173 operand immD() %{
4174 predicate(UseSSE<=1);
4175 match(ConD);
4177 op_cost(5);
4178 format %{ %}
4179 interface(CONST_INTER);
4180 %}
4182 operand immXD() %{
4183 predicate(UseSSE>=2);
4184 match(ConD);
4186 op_cost(5);
4187 format %{ %}
4188 interface(CONST_INTER);
4189 %}
4191 // Double Immediate zero
4192 operand immXD0() %{
4193 // Do additional (and counter-intuitive) test against NaN to work around VC++
4194 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4195 // compare equal to -0.0.
4196 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4197 match(ConD);
4199 format %{ %}
4200 interface(CONST_INTER);
4201 %}
4203 // Float Immediate zero
4204 operand immF0() %{
4205 predicate(UseSSE == 0 && n->getf() == 0.0F);
4206 match(ConF);
4208 op_cost(5);
4209 format %{ %}
4210 interface(CONST_INTER);
4211 %}
4213 // Float Immediate one
4214 operand immF1() %{
4215 predicate(UseSSE == 0 && n->getf() == 1.0F);
4216 match(ConF);
4218 op_cost(5);
4219 format %{ %}
4220 interface(CONST_INTER);
4221 %}
4223 // Float Immediate
4224 operand immF() %{
4225 predicate( UseSSE == 0 );
4226 match(ConF);
4228 op_cost(5);
4229 format %{ %}
4230 interface(CONST_INTER);
4231 %}
4233 // Float Immediate
4234 operand immXF() %{
4235 predicate(UseSSE >= 1);
4236 match(ConF);
4238 op_cost(5);
4239 format %{ %}
4240 interface(CONST_INTER);
4241 %}
4243 // Float Immediate zero. Zero and not -0.0
4244 operand immXF0() %{
4245 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4246 match(ConF);
4248 op_cost(5);
4249 format %{ %}
4250 interface(CONST_INTER);
4251 %}
4253 // Immediates for special shifts (sign extend)
4255 // Constants for increment
4256 operand immI_16() %{
4257 predicate( n->get_int() == 16 );
4258 match(ConI);
4260 format %{ %}
4261 interface(CONST_INTER);
4262 %}
4264 operand immI_24() %{
4265 predicate( n->get_int() == 24 );
4266 match(ConI);
4268 format %{ %}
4269 interface(CONST_INTER);
4270 %}
4272 // Constant for byte-wide masking
4273 operand immI_255() %{
4274 predicate( n->get_int() == 255 );
4275 match(ConI);
4277 format %{ %}
4278 interface(CONST_INTER);
4279 %}
4281 // Constant for short-wide masking
4282 operand immI_65535() %{
4283 predicate(n->get_int() == 65535);
4284 match(ConI);
4286 format %{ %}
4287 interface(CONST_INTER);
4288 %}
4290 // Register Operands
4291 // Integer Register
4292 operand eRegI() %{
4293 constraint(ALLOC_IN_RC(e_reg));
4294 match(RegI);
4295 match(xRegI);
4296 match(eAXRegI);
4297 match(eBXRegI);
4298 match(eCXRegI);
4299 match(eDXRegI);
4300 match(eDIRegI);
4301 match(eSIRegI);
4303 format %{ %}
4304 interface(REG_INTER);
4305 %}
4307 // Subset of Integer Register
4308 operand xRegI(eRegI reg) %{
4309 constraint(ALLOC_IN_RC(x_reg));
4310 match(reg);
4311 match(eAXRegI);
4312 match(eBXRegI);
4313 match(eCXRegI);
4314 match(eDXRegI);
4316 format %{ %}
4317 interface(REG_INTER);
4318 %}
4320 // Special Registers
4321 operand eAXRegI(xRegI reg) %{
4322 constraint(ALLOC_IN_RC(eax_reg));
4323 match(reg);
4324 match(eRegI);
4326 format %{ "EAX" %}
4327 interface(REG_INTER);
4328 %}
4330 // Special Registers
4331 operand eBXRegI(xRegI reg) %{
4332 constraint(ALLOC_IN_RC(ebx_reg));
4333 match(reg);
4334 match(eRegI);
4336 format %{ "EBX" %}
4337 interface(REG_INTER);
4338 %}
4340 operand eCXRegI(xRegI reg) %{
4341 constraint(ALLOC_IN_RC(ecx_reg));
4342 match(reg);
4343 match(eRegI);
4345 format %{ "ECX" %}
4346 interface(REG_INTER);
4347 %}
4349 operand eDXRegI(xRegI reg) %{
4350 constraint(ALLOC_IN_RC(edx_reg));
4351 match(reg);
4352 match(eRegI);
4354 format %{ "EDX" %}
4355 interface(REG_INTER);
4356 %}
4358 operand eDIRegI(xRegI reg) %{
4359 constraint(ALLOC_IN_RC(edi_reg));
4360 match(reg);
4361 match(eRegI);
4363 format %{ "EDI" %}
4364 interface(REG_INTER);
4365 %}
4367 operand naxRegI() %{
4368 constraint(ALLOC_IN_RC(nax_reg));
4369 match(RegI);
4370 match(eCXRegI);
4371 match(eDXRegI);
4372 match(eSIRegI);
4373 match(eDIRegI);
4375 format %{ %}
4376 interface(REG_INTER);
4377 %}
4379 operand nadxRegI() %{
4380 constraint(ALLOC_IN_RC(nadx_reg));
4381 match(RegI);
4382 match(eBXRegI);
4383 match(eCXRegI);
4384 match(eSIRegI);
4385 match(eDIRegI);
4387 format %{ %}
4388 interface(REG_INTER);
4389 %}
4391 operand ncxRegI() %{
4392 constraint(ALLOC_IN_RC(ncx_reg));
4393 match(RegI);
4394 match(eAXRegI);
4395 match(eDXRegI);
4396 match(eSIRegI);
4397 match(eDIRegI);
4399 format %{ %}
4400 interface(REG_INTER);
4401 %}
4403 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4404 // //
4405 operand eSIRegI(xRegI reg) %{
4406 constraint(ALLOC_IN_RC(esi_reg));
4407 match(reg);
4408 match(eRegI);
4410 format %{ "ESI" %}
4411 interface(REG_INTER);
4412 %}
4414 // Pointer Register
4415 operand anyRegP() %{
4416 constraint(ALLOC_IN_RC(any_reg));
4417 match(RegP);
4418 match(eAXRegP);
4419 match(eBXRegP);
4420 match(eCXRegP);
4421 match(eDIRegP);
4422 match(eRegP);
4424 format %{ %}
4425 interface(REG_INTER);
4426 %}
4428 operand eRegP() %{
4429 constraint(ALLOC_IN_RC(e_reg));
4430 match(RegP);
4431 match(eAXRegP);
4432 match(eBXRegP);
4433 match(eCXRegP);
4434 match(eDIRegP);
4436 format %{ %}
4437 interface(REG_INTER);
4438 %}
4440 // On windows95, EBP is not safe to use for implicit null tests.
4441 operand eRegP_no_EBP() %{
4442 constraint(ALLOC_IN_RC(e_reg_no_rbp));
4443 match(RegP);
4444 match(eAXRegP);
4445 match(eBXRegP);
4446 match(eCXRegP);
4447 match(eDIRegP);
4449 op_cost(100);
4450 format %{ %}
4451 interface(REG_INTER);
4452 %}
4454 operand naxRegP() %{
4455 constraint(ALLOC_IN_RC(nax_reg));
4456 match(RegP);
4457 match(eBXRegP);
4458 match(eDXRegP);
4459 match(eCXRegP);
4460 match(eSIRegP);
4461 match(eDIRegP);
4463 format %{ %}
4464 interface(REG_INTER);
4465 %}
4467 operand nabxRegP() %{
4468 constraint(ALLOC_IN_RC(nabx_reg));
4469 match(RegP);
4470 match(eCXRegP);
4471 match(eDXRegP);
4472 match(eSIRegP);
4473 match(eDIRegP);
4475 format %{ %}
4476 interface(REG_INTER);
4477 %}
4479 operand pRegP() %{
4480 constraint(ALLOC_IN_RC(p_reg));
4481 match(RegP);
4482 match(eBXRegP);
4483 match(eDXRegP);
4484 match(eSIRegP);
4485 match(eDIRegP);
4487 format %{ %}
4488 interface(REG_INTER);
4489 %}
4491 // Special Registers
4492 // Return a pointer value
4493 operand eAXRegP(eRegP reg) %{
4494 constraint(ALLOC_IN_RC(eax_reg));
4495 match(reg);
4496 format %{ "EAX" %}
4497 interface(REG_INTER);
4498 %}
4500 // Used in AtomicAdd
4501 operand eBXRegP(eRegP reg) %{
4502 constraint(ALLOC_IN_RC(ebx_reg));
4503 match(reg);
4504 format %{ "EBX" %}
4505 interface(REG_INTER);
4506 %}
4508 // Tail-call (interprocedural jump) to interpreter
4509 operand eCXRegP(eRegP reg) %{
4510 constraint(ALLOC_IN_RC(ecx_reg));
4511 match(reg);
4512 format %{ "ECX" %}
4513 interface(REG_INTER);
4514 %}
4516 operand eSIRegP(eRegP reg) %{
4517 constraint(ALLOC_IN_RC(esi_reg));
4518 match(reg);
4519 format %{ "ESI" %}
4520 interface(REG_INTER);
4521 %}
4523 // Used in rep stosw
4524 operand eDIRegP(eRegP reg) %{
4525 constraint(ALLOC_IN_RC(edi_reg));
4526 match(reg);
4527 format %{ "EDI" %}
4528 interface(REG_INTER);
4529 %}
4531 operand eBPRegP() %{
4532 constraint(ALLOC_IN_RC(ebp_reg));
4533 match(RegP);
4534 format %{ "EBP" %}
4535 interface(REG_INTER);
4536 %}
4538 operand eRegL() %{
4539 constraint(ALLOC_IN_RC(long_reg));
4540 match(RegL);
4541 match(eADXRegL);
4543 format %{ %}
4544 interface(REG_INTER);
4545 %}
4547 operand eADXRegL( eRegL reg ) %{
4548 constraint(ALLOC_IN_RC(eadx_reg));
4549 match(reg);
4551 format %{ "EDX:EAX" %}
4552 interface(REG_INTER);
4553 %}
4555 operand eBCXRegL( eRegL reg ) %{
4556 constraint(ALLOC_IN_RC(ebcx_reg));
4557 match(reg);
4559 format %{ "EBX:ECX" %}
4560 interface(REG_INTER);
4561 %}
4563 // Special case for integer high multiply
4564 operand eADXRegL_low_only() %{
4565 constraint(ALLOC_IN_RC(eadx_reg));
4566 match(RegL);
4568 format %{ "EAX" %}
4569 interface(REG_INTER);
4570 %}
4572 // Flags register, used as output of compare instructions
4573 operand eFlagsReg() %{
4574 constraint(ALLOC_IN_RC(int_flags));
4575 match(RegFlags);
4577 format %{ "EFLAGS" %}
4578 interface(REG_INTER);
4579 %}
4581 // Flags register, used as output of FLOATING POINT compare instructions
4582 operand eFlagsRegU() %{
4583 constraint(ALLOC_IN_RC(int_flags));
4584 match(RegFlags);
4586 format %{ "EFLAGS_U" %}
4587 interface(REG_INTER);
4588 %}
4590 operand eFlagsRegUCF() %{
4591 constraint(ALLOC_IN_RC(int_flags));
4592 match(RegFlags);
4593 predicate(false);
4595 format %{ "EFLAGS_U_CF" %}
4596 interface(REG_INTER);
4597 %}
4599 // Condition Code Register used by long compare
4600 operand flagsReg_long_LTGE() %{
4601 constraint(ALLOC_IN_RC(int_flags));
4602 match(RegFlags);
4603 format %{ "FLAGS_LTGE" %}
4604 interface(REG_INTER);
4605 %}
4606 operand flagsReg_long_EQNE() %{
4607 constraint(ALLOC_IN_RC(int_flags));
4608 match(RegFlags);
4609 format %{ "FLAGS_EQNE" %}
4610 interface(REG_INTER);
4611 %}
4612 operand flagsReg_long_LEGT() %{
4613 constraint(ALLOC_IN_RC(int_flags));
4614 match(RegFlags);
4615 format %{ "FLAGS_LEGT" %}
4616 interface(REG_INTER);
4617 %}
4619 // Float register operands
4620 operand regD() %{
4621 predicate( UseSSE < 2 );
4622 constraint(ALLOC_IN_RC(dbl_reg));
4623 match(RegD);
4624 match(regDPR1);
4625 match(regDPR2);
4626 format %{ %}
4627 interface(REG_INTER);
4628 %}
4630 operand regDPR1(regD reg) %{
4631 predicate( UseSSE < 2 );
4632 constraint(ALLOC_IN_RC(dbl_reg0));
4633 match(reg);
4634 format %{ "FPR1" %}
4635 interface(REG_INTER);
4636 %}
4638 operand regDPR2(regD reg) %{
4639 predicate( UseSSE < 2 );
4640 constraint(ALLOC_IN_RC(dbl_reg1));
4641 match(reg);
4642 format %{ "FPR2" %}
4643 interface(REG_INTER);
4644 %}
4646 operand regnotDPR1(regD reg) %{
4647 predicate( UseSSE < 2 );
4648 constraint(ALLOC_IN_RC(dbl_notreg0));
4649 match(reg);
4650 format %{ %}
4651 interface(REG_INTER);
4652 %}
4654 // XMM Double register operands
4655 operand regXD() %{
4656 predicate( UseSSE>=2 );
4657 constraint(ALLOC_IN_RC(xdb_reg));
4658 match(RegD);
4659 match(regXD6);
4660 match(regXD7);
4661 format %{ %}
4662 interface(REG_INTER);
4663 %}
4665 // XMM6 double register operands
4666 operand regXD6(regXD reg) %{
4667 predicate( UseSSE>=2 );
4668 constraint(ALLOC_IN_RC(xdb_reg6));
4669 match(reg);
4670 format %{ "XMM6" %}
4671 interface(REG_INTER);
4672 %}
4674 // XMM7 double register operands
4675 operand regXD7(regXD reg) %{
4676 predicate( UseSSE>=2 );
4677 constraint(ALLOC_IN_RC(xdb_reg7));
4678 match(reg);
4679 format %{ "XMM7" %}
4680 interface(REG_INTER);
4681 %}
4683 // Float register operands
4684 operand regF() %{
4685 predicate( UseSSE < 2 );
4686 constraint(ALLOC_IN_RC(flt_reg));
4687 match(RegF);
4688 match(regFPR1);
4689 format %{ %}
4690 interface(REG_INTER);
4691 %}
4693 // Float register operands
4694 operand regFPR1(regF reg) %{
4695 predicate( UseSSE < 2 );
4696 constraint(ALLOC_IN_RC(flt_reg0));
4697 match(reg);
4698 format %{ "FPR1" %}
4699 interface(REG_INTER);
4700 %}
4702 // XMM register operands
4703 operand regX() %{
4704 predicate( UseSSE>=1 );
4705 constraint(ALLOC_IN_RC(xmm_reg));
4706 match(RegF);
4707 format %{ %}
4708 interface(REG_INTER);
4709 %}
4712 //----------Memory Operands----------------------------------------------------
4713 // Direct Memory Operand
4714 operand direct(immP addr) %{
4715 match(addr);
4717 format %{ "[$addr]" %}
4718 interface(MEMORY_INTER) %{
4719 base(0xFFFFFFFF);
4720 index(0x4);
4721 scale(0x0);
4722 disp($addr);
4723 %}
4724 %}
4726 // Indirect Memory Operand
4727 operand indirect(eRegP reg) %{
4728 constraint(ALLOC_IN_RC(e_reg));
4729 match(reg);
4731 format %{ "[$reg]" %}
4732 interface(MEMORY_INTER) %{
4733 base($reg);
4734 index(0x4);
4735 scale(0x0);
4736 disp(0x0);
4737 %}
4738 %}
4740 // Indirect Memory Plus Short Offset Operand
4741 operand indOffset8(eRegP reg, immI8 off) %{
4742 match(AddP reg off);
4744 format %{ "[$reg + $off]" %}
4745 interface(MEMORY_INTER) %{
4746 base($reg);
4747 index(0x4);
4748 scale(0x0);
4749 disp($off);
4750 %}
4751 %}
4753 // Indirect Memory Plus Long Offset Operand
4754 operand indOffset32(eRegP reg, immI off) %{
4755 match(AddP reg off);
4757 format %{ "[$reg + $off]" %}
4758 interface(MEMORY_INTER) %{
4759 base($reg);
4760 index(0x4);
4761 scale(0x0);
4762 disp($off);
4763 %}
4764 %}
4766 // Indirect Memory Plus Long Offset Operand
4767 operand indOffset32X(eRegI reg, immP off) %{
4768 match(AddP off reg);
4770 format %{ "[$reg + $off]" %}
4771 interface(MEMORY_INTER) %{
4772 base($reg);
4773 index(0x4);
4774 scale(0x0);
4775 disp($off);
4776 %}
4777 %}
4779 // Indirect Memory Plus Index Register Plus Offset Operand
4780 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
4781 match(AddP (AddP reg ireg) off);
4783 op_cost(10);
4784 format %{"[$reg + $off + $ireg]" %}
4785 interface(MEMORY_INTER) %{
4786 base($reg);
4787 index($ireg);
4788 scale(0x0);
4789 disp($off);
4790 %}
4791 %}
4793 // Indirect Memory Plus Index Register Plus Offset Operand
4794 operand indIndex(eRegP reg, eRegI ireg) %{
4795 match(AddP reg ireg);
4797 op_cost(10);
4798 format %{"[$reg + $ireg]" %}
4799 interface(MEMORY_INTER) %{
4800 base($reg);
4801 index($ireg);
4802 scale(0x0);
4803 disp(0x0);
4804 %}
4805 %}
4807 // // -------------------------------------------------------------------------
4808 // // 486 architecture doesn't support "scale * index + offset" with out a base
4809 // // -------------------------------------------------------------------------
4810 // // Scaled Memory Operands
4811 // // Indirect Memory Times Scale Plus Offset Operand
4812 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
4813 // match(AddP off (LShiftI ireg scale));
4814 //
4815 // op_cost(10);
4816 // format %{"[$off + $ireg << $scale]" %}
4817 // interface(MEMORY_INTER) %{
4818 // base(0x4);
4819 // index($ireg);
4820 // scale($scale);
4821 // disp($off);
4822 // %}
4823 // %}
4825 // Indirect Memory Times Scale Plus Index Register
4826 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
4827 match(AddP reg (LShiftI ireg scale));
4829 op_cost(10);
4830 format %{"[$reg + $ireg << $scale]" %}
4831 interface(MEMORY_INTER) %{
4832 base($reg);
4833 index($ireg);
4834 scale($scale);
4835 disp(0x0);
4836 %}
4837 %}
4839 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4840 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
4841 match(AddP (AddP reg (LShiftI ireg scale)) off);
4843 op_cost(10);
4844 format %{"[$reg + $off + $ireg << $scale]" %}
4845 interface(MEMORY_INTER) %{
4846 base($reg);
4847 index($ireg);
4848 scale($scale);
4849 disp($off);
4850 %}
4851 %}
4853 //----------Load Long Memory Operands------------------------------------------
4854 // The load-long idiom will use it's address expression again after loading
4855 // the first word of the long. If the load-long destination overlaps with
4856 // registers used in the addressing expression, the 2nd half will be loaded
4857 // from a clobbered address. Fix this by requiring that load-long use
4858 // address registers that do not overlap with the load-long target.
4860 // load-long support
4861 operand load_long_RegP() %{
4862 constraint(ALLOC_IN_RC(esi_reg));
4863 match(RegP);
4864 match(eSIRegP);
4865 op_cost(100);
4866 format %{ %}
4867 interface(REG_INTER);
4868 %}
4870 // Indirect Memory Operand Long
4871 operand load_long_indirect(load_long_RegP reg) %{
4872 constraint(ALLOC_IN_RC(esi_reg));
4873 match(reg);
4875 format %{ "[$reg]" %}
4876 interface(MEMORY_INTER) %{
4877 base($reg);
4878 index(0x4);
4879 scale(0x0);
4880 disp(0x0);
4881 %}
4882 %}
4884 // Indirect Memory Plus Long Offset Operand
4885 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4886 match(AddP reg off);
4888 format %{ "[$reg + $off]" %}
4889 interface(MEMORY_INTER) %{
4890 base($reg);
4891 index(0x4);
4892 scale(0x0);
4893 disp($off);
4894 %}
4895 %}
4897 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4900 //----------Special Memory Operands--------------------------------------------
4901 // Stack Slot Operand - This operand is used for loading and storing temporary
4902 // values on the stack where a match requires a value to
4903 // flow through memory.
4904 operand stackSlotP(sRegP reg) %{
4905 constraint(ALLOC_IN_RC(stack_slots));
4906 // No match rule because this operand is only generated in matching
4907 format %{ "[$reg]" %}
4908 interface(MEMORY_INTER) %{
4909 base(0x4); // ESP
4910 index(0x4); // No Index
4911 scale(0x0); // No Scale
4912 disp($reg); // Stack Offset
4913 %}
4914 %}
4916 operand stackSlotI(sRegI reg) %{
4917 constraint(ALLOC_IN_RC(stack_slots));
4918 // No match rule because this operand is only generated in matching
4919 format %{ "[$reg]" %}
4920 interface(MEMORY_INTER) %{
4921 base(0x4); // ESP
4922 index(0x4); // No Index
4923 scale(0x0); // No Scale
4924 disp($reg); // Stack Offset
4925 %}
4926 %}
4928 operand stackSlotF(sRegF reg) %{
4929 constraint(ALLOC_IN_RC(stack_slots));
4930 // No match rule because this operand is only generated in matching
4931 format %{ "[$reg]" %}
4932 interface(MEMORY_INTER) %{
4933 base(0x4); // ESP
4934 index(0x4); // No Index
4935 scale(0x0); // No Scale
4936 disp($reg); // Stack Offset
4937 %}
4938 %}
4940 operand stackSlotD(sRegD reg) %{
4941 constraint(ALLOC_IN_RC(stack_slots));
4942 // No match rule because this operand is only generated in matching
4943 format %{ "[$reg]" %}
4944 interface(MEMORY_INTER) %{
4945 base(0x4); // ESP
4946 index(0x4); // No Index
4947 scale(0x0); // No Scale
4948 disp($reg); // Stack Offset
4949 %}
4950 %}
4952 operand stackSlotL(sRegL reg) %{
4953 constraint(ALLOC_IN_RC(stack_slots));
4954 // No match rule because this operand is only generated in matching
4955 format %{ "[$reg]" %}
4956 interface(MEMORY_INTER) %{
4957 base(0x4); // ESP
4958 index(0x4); // No Index
4959 scale(0x0); // No Scale
4960 disp($reg); // Stack Offset
4961 %}
4962 %}
4964 //----------Memory Operands - Win95 Implicit Null Variants----------------
4965 // Indirect Memory Operand
4966 operand indirect_win95_safe(eRegP_no_EBP reg)
4967 %{
4968 constraint(ALLOC_IN_RC(e_reg));
4969 match(reg);
4971 op_cost(100);
4972 format %{ "[$reg]" %}
4973 interface(MEMORY_INTER) %{
4974 base($reg);
4975 index(0x4);
4976 scale(0x0);
4977 disp(0x0);
4978 %}
4979 %}
4981 // Indirect Memory Plus Short Offset Operand
4982 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4983 %{
4984 match(AddP reg off);
4986 op_cost(100);
4987 format %{ "[$reg + $off]" %}
4988 interface(MEMORY_INTER) %{
4989 base($reg);
4990 index(0x4);
4991 scale(0x0);
4992 disp($off);
4993 %}
4994 %}
4996 // Indirect Memory Plus Long Offset Operand
4997 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4998 %{
4999 match(AddP reg off);
5001 op_cost(100);
5002 format %{ "[$reg + $off]" %}
5003 interface(MEMORY_INTER) %{
5004 base($reg);
5005 index(0x4);
5006 scale(0x0);
5007 disp($off);
5008 %}
5009 %}
5011 // Indirect Memory Plus Index Register Plus Offset Operand
5012 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
5013 %{
5014 match(AddP (AddP reg ireg) off);
5016 op_cost(100);
5017 format %{"[$reg + $off + $ireg]" %}
5018 interface(MEMORY_INTER) %{
5019 base($reg);
5020 index($ireg);
5021 scale(0x0);
5022 disp($off);
5023 %}
5024 %}
5026 // Indirect Memory Times Scale Plus Index Register
5027 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
5028 %{
5029 match(AddP reg (LShiftI ireg scale));
5031 op_cost(100);
5032 format %{"[$reg + $ireg << $scale]" %}
5033 interface(MEMORY_INTER) %{
5034 base($reg);
5035 index($ireg);
5036 scale($scale);
5037 disp(0x0);
5038 %}
5039 %}
5041 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5042 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
5043 %{
5044 match(AddP (AddP reg (LShiftI ireg scale)) off);
5046 op_cost(100);
5047 format %{"[$reg + $off + $ireg << $scale]" %}
5048 interface(MEMORY_INTER) %{
5049 base($reg);
5050 index($ireg);
5051 scale($scale);
5052 disp($off);
5053 %}
5054 %}
5056 //----------Conditional Branch Operands----------------------------------------
5057 // Comparison Op - This is the operation of the comparison, and is limited to
5058 // the following set of codes:
5059 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5060 //
5061 // Other attributes of the comparison, such as unsignedness, are specified
5062 // by the comparison instruction that sets a condition code flags register.
5063 // That result is represented by a flags operand whose subtype is appropriate
5064 // to the unsignedness (etc.) of the comparison.
5065 //
5066 // Later, the instruction which matches both the Comparison Op (a Bool) and
5067 // the flags (produced by the Cmp) specifies the coding of the comparison op
5068 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5070 // Comparision Code
5071 operand cmpOp() %{
5072 match(Bool);
5074 format %{ "" %}
5075 interface(COND_INTER) %{
5076 equal(0x4, "e");
5077 not_equal(0x5, "ne");
5078 less(0xC, "l");
5079 greater_equal(0xD, "ge");
5080 less_equal(0xE, "le");
5081 greater(0xF, "g");
5082 %}
5083 %}
5085 // Comparison Code, unsigned compare. Used by FP also, with
5086 // C2 (unordered) turned into GT or LT already. The other bits
5087 // C0 and C3 are turned into Carry & Zero flags.
5088 operand cmpOpU() %{
5089 match(Bool);
5091 format %{ "" %}
5092 interface(COND_INTER) %{
5093 equal(0x4, "e");
5094 not_equal(0x5, "ne");
5095 less(0x2, "b");
5096 greater_equal(0x3, "nb");
5097 less_equal(0x6, "be");
5098 greater(0x7, "nbe");
5099 %}
5100 %}
5102 // Floating comparisons that don't require any fixup for the unordered case
5103 operand cmpOpUCF() %{
5104 match(Bool);
5105 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
5106 n->as_Bool()->_test._test == BoolTest::ge ||
5107 n->as_Bool()->_test._test == BoolTest::le ||
5108 n->as_Bool()->_test._test == BoolTest::gt);
5109 format %{ "" %}
5110 interface(COND_INTER) %{
5111 equal(0x4, "e");
5112 not_equal(0x5, "ne");
5113 less(0x2, "b");
5114 greater_equal(0x3, "nb");
5115 less_equal(0x6, "be");
5116 greater(0x7, "nbe");
5117 %}
5118 %}
5121 // Floating comparisons that can be fixed up with extra conditional jumps
5122 operand cmpOpUCF2() %{
5123 match(Bool);
5124 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5125 n->as_Bool()->_test._test == BoolTest::eq);
5126 format %{ "" %}
5127 interface(COND_INTER) %{
5128 equal(0x4, "e");
5129 not_equal(0x5, "ne");
5130 less(0x2, "b");
5131 greater_equal(0x3, "nb");
5132 less_equal(0x6, "be");
5133 greater(0x7, "nbe");
5134 %}
5135 %}
5137 // Comparison Code for FP conditional move
5138 operand cmpOp_fcmov() %{
5139 match(Bool);
5141 format %{ "" %}
5142 interface(COND_INTER) %{
5143 equal (0x0C8);
5144 not_equal (0x1C8);
5145 less (0x0C0);
5146 greater_equal(0x1C0);
5147 less_equal (0x0D0);
5148 greater (0x1D0);
5149 %}
5150 %}
5152 // Comparision Code used in long compares
5153 operand cmpOp_commute() %{
5154 match(Bool);
5156 format %{ "" %}
5157 interface(COND_INTER) %{
5158 equal(0x4, "e");
5159 not_equal(0x5, "ne");
5160 less(0xF, "g");
5161 greater_equal(0xE, "le");
5162 less_equal(0xD, "ge");
5163 greater(0xC, "l");
5164 %}
5165 %}
5167 //----------OPERAND CLASSES----------------------------------------------------
5168 // Operand Classes are groups of operands that are used as to simplify
5169 // instruction definitions by not requiring the AD writer to specify separate
5170 // instructions for every form of operand when the instruction accepts
5171 // multiple operand types with the same basic encoding and format. The classic
5172 // case of this is memory operands.
5174 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5175 indIndex, indIndexScale, indIndexScaleOffset);
5177 // Long memory operations are encoded in 2 instructions and a +4 offset.
5178 // This means some kind of offset is always required and you cannot use
5179 // an oop as the offset (done when working on static globals).
5180 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5181 indIndex, indIndexScale, indIndexScaleOffset);
5184 //----------PIPELINE-----------------------------------------------------------
5185 // Rules which define the behavior of the target architectures pipeline.
5186 pipeline %{
5188 //----------ATTRIBUTES---------------------------------------------------------
5189 attributes %{
5190 variable_size_instructions; // Fixed size instructions
5191 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5192 instruction_unit_size = 1; // An instruction is 1 bytes long
5193 instruction_fetch_unit_size = 16; // The processor fetches one line
5194 instruction_fetch_units = 1; // of 16 bytes
5196 // List of nop instructions
5197 nops( MachNop );
5198 %}
5200 //----------RESOURCES----------------------------------------------------------
5201 // Resources are the functional units available to the machine
5203 // Generic P2/P3 pipeline
5204 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5205 // 3 instructions decoded per cycle.
5206 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5207 // 2 ALU op, only ALU0 handles mul/div instructions.
5208 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5209 MS0, MS1, MEM = MS0 | MS1,
5210 BR, FPU,
5211 ALU0, ALU1, ALU = ALU0 | ALU1 );
5213 //----------PIPELINE DESCRIPTION-----------------------------------------------
5214 // Pipeline Description specifies the stages in the machine's pipeline
5216 // Generic P2/P3 pipeline
5217 pipe_desc(S0, S1, S2, S3, S4, S5);
5219 //----------PIPELINE CLASSES---------------------------------------------------
5220 // Pipeline Classes describe the stages in which input and output are
5221 // referenced by the hardware pipeline.
5223 // Naming convention: ialu or fpu
5224 // Then: _reg
5225 // Then: _reg if there is a 2nd register
5226 // Then: _long if it's a pair of instructions implementing a long
5227 // Then: _fat if it requires the big decoder
5228 // Or: _mem if it requires the big decoder and a memory unit.
5230 // Integer ALU reg operation
5231 pipe_class ialu_reg(eRegI dst) %{
5232 single_instruction;
5233 dst : S4(write);
5234 dst : S3(read);
5235 DECODE : S0; // any decoder
5236 ALU : S3; // any alu
5237 %}
5239 // Long ALU reg operation
5240 pipe_class ialu_reg_long(eRegL dst) %{
5241 instruction_count(2);
5242 dst : S4(write);
5243 dst : S3(read);
5244 DECODE : S0(2); // any 2 decoders
5245 ALU : S3(2); // both alus
5246 %}
5248 // Integer ALU reg operation using big decoder
5249 pipe_class ialu_reg_fat(eRegI dst) %{
5250 single_instruction;
5251 dst : S4(write);
5252 dst : S3(read);
5253 D0 : S0; // big decoder only
5254 ALU : S3; // any alu
5255 %}
5257 // Long ALU reg operation using big decoder
5258 pipe_class ialu_reg_long_fat(eRegL dst) %{
5259 instruction_count(2);
5260 dst : S4(write);
5261 dst : S3(read);
5262 D0 : S0(2); // big decoder only; twice
5263 ALU : S3(2); // any 2 alus
5264 %}
5266 // Integer ALU reg-reg operation
5267 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
5268 single_instruction;
5269 dst : S4(write);
5270 src : S3(read);
5271 DECODE : S0; // any decoder
5272 ALU : S3; // any alu
5273 %}
5275 // Long ALU reg-reg operation
5276 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5277 instruction_count(2);
5278 dst : S4(write);
5279 src : S3(read);
5280 DECODE : S0(2); // any 2 decoders
5281 ALU : S3(2); // both alus
5282 %}
5284 // Integer ALU reg-reg operation
5285 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
5286 single_instruction;
5287 dst : S4(write);
5288 src : S3(read);
5289 D0 : S0; // big decoder only
5290 ALU : S3; // any alu
5291 %}
5293 // Long ALU reg-reg operation
5294 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5295 instruction_count(2);
5296 dst : S4(write);
5297 src : S3(read);
5298 D0 : S0(2); // big decoder only; twice
5299 ALU : S3(2); // both alus
5300 %}
5302 // Integer ALU reg-mem operation
5303 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
5304 single_instruction;
5305 dst : S5(write);
5306 mem : S3(read);
5307 D0 : S0; // big decoder only
5308 ALU : S4; // any alu
5309 MEM : S3; // any mem
5310 %}
5312 // Long ALU reg-mem operation
5313 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5314 instruction_count(2);
5315 dst : S5(write);
5316 mem : S3(read);
5317 D0 : S0(2); // big decoder only; twice
5318 ALU : S4(2); // any 2 alus
5319 MEM : S3(2); // both mems
5320 %}
5322 // Integer mem operation (prefetch)
5323 pipe_class ialu_mem(memory mem)
5324 %{
5325 single_instruction;
5326 mem : S3(read);
5327 D0 : S0; // big decoder only
5328 MEM : S3; // any mem
5329 %}
5331 // Integer Store to Memory
5332 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
5333 single_instruction;
5334 mem : S3(read);
5335 src : S5(read);
5336 D0 : S0; // big decoder only
5337 ALU : S4; // any alu
5338 MEM : S3;
5339 %}
5341 // Long Store to Memory
5342 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5343 instruction_count(2);
5344 mem : S3(read);
5345 src : S5(read);
5346 D0 : S0(2); // big decoder only; twice
5347 ALU : S4(2); // any 2 alus
5348 MEM : S3(2); // Both mems
5349 %}
5351 // Integer Store to Memory
5352 pipe_class ialu_mem_imm(memory mem) %{
5353 single_instruction;
5354 mem : S3(read);
5355 D0 : S0; // big decoder only
5356 ALU : S4; // any alu
5357 MEM : S3;
5358 %}
5360 // Integer ALU0 reg-reg operation
5361 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
5362 single_instruction;
5363 dst : S4(write);
5364 src : S3(read);
5365 D0 : S0; // Big decoder only
5366 ALU0 : S3; // only alu0
5367 %}
5369 // Integer ALU0 reg-mem operation
5370 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
5371 single_instruction;
5372 dst : S5(write);
5373 mem : S3(read);
5374 D0 : S0; // big decoder only
5375 ALU0 : S4; // ALU0 only
5376 MEM : S3; // any mem
5377 %}
5379 // Integer ALU reg-reg operation
5380 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
5381 single_instruction;
5382 cr : S4(write);
5383 src1 : S3(read);
5384 src2 : S3(read);
5385 DECODE : S0; // any decoder
5386 ALU : S3; // any alu
5387 %}
5389 // Integer ALU reg-imm operation
5390 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
5391 single_instruction;
5392 cr : S4(write);
5393 src1 : S3(read);
5394 DECODE : S0; // any decoder
5395 ALU : S3; // any alu
5396 %}
5398 // Integer ALU reg-mem operation
5399 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
5400 single_instruction;
5401 cr : S4(write);
5402 src1 : S3(read);
5403 src2 : S3(read);
5404 D0 : S0; // big decoder only
5405 ALU : S4; // any alu
5406 MEM : S3;
5407 %}
5409 // Conditional move reg-reg
5410 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
5411 instruction_count(4);
5412 y : S4(read);
5413 q : S3(read);
5414 p : S3(read);
5415 DECODE : S0(4); // any decoder
5416 %}
5418 // Conditional move reg-reg
5419 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
5420 single_instruction;
5421 dst : S4(write);
5422 src : S3(read);
5423 cr : S3(read);
5424 DECODE : S0; // any decoder
5425 %}
5427 // Conditional move reg-mem
5428 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
5429 single_instruction;
5430 dst : S4(write);
5431 src : S3(read);
5432 cr : S3(read);
5433 DECODE : S0; // any decoder
5434 MEM : S3;
5435 %}
5437 // Conditional move reg-reg long
5438 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5439 single_instruction;
5440 dst : S4(write);
5441 src : S3(read);
5442 cr : S3(read);
5443 DECODE : S0(2); // any 2 decoders
5444 %}
5446 // Conditional move double reg-reg
5447 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{
5448 single_instruction;
5449 dst : S4(write);
5450 src : S3(read);
5451 cr : S3(read);
5452 DECODE : S0; // any decoder
5453 %}
5455 // Float reg-reg operation
5456 pipe_class fpu_reg(regD dst) %{
5457 instruction_count(2);
5458 dst : S3(read);
5459 DECODE : S0(2); // any 2 decoders
5460 FPU : S3;
5461 %}
5463 // Float reg-reg operation
5464 pipe_class fpu_reg_reg(regD dst, regD src) %{
5465 instruction_count(2);
5466 dst : S4(write);
5467 src : S3(read);
5468 DECODE : S0(2); // any 2 decoders
5469 FPU : S3;
5470 %}
5472 // Float reg-reg operation
5473 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{
5474 instruction_count(3);
5475 dst : S4(write);
5476 src1 : S3(read);
5477 src2 : S3(read);
5478 DECODE : S0(3); // any 3 decoders
5479 FPU : S3(2);
5480 %}
5482 // Float reg-reg operation
5483 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
5484 instruction_count(4);
5485 dst : S4(write);
5486 src1 : S3(read);
5487 src2 : S3(read);
5488 src3 : S3(read);
5489 DECODE : S0(4); // any 3 decoders
5490 FPU : S3(2);
5491 %}
5493 // Float reg-reg operation
5494 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{
5495 instruction_count(4);
5496 dst : S4(write);
5497 src1 : S3(read);
5498 src2 : S3(read);
5499 src3 : S3(read);
5500 DECODE : S1(3); // any 3 decoders
5501 D0 : S0; // Big decoder only
5502 FPU : S3(2);
5503 MEM : S3;
5504 %}
5506 // Float reg-mem operation
5507 pipe_class fpu_reg_mem(regD dst, memory mem) %{
5508 instruction_count(2);
5509 dst : S5(write);
5510 mem : S3(read);
5511 D0 : S0; // big decoder only
5512 DECODE : S1; // any decoder for FPU POP
5513 FPU : S4;
5514 MEM : S3; // any mem
5515 %}
5517 // Float reg-mem operation
5518 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{
5519 instruction_count(3);
5520 dst : S5(write);
5521 src1 : S3(read);
5522 mem : S3(read);
5523 D0 : S0; // big decoder only
5524 DECODE : S1(2); // any decoder for FPU POP
5525 FPU : S4;
5526 MEM : S3; // any mem
5527 %}
5529 // Float mem-reg operation
5530 pipe_class fpu_mem_reg(memory mem, regD src) %{
5531 instruction_count(2);
5532 src : S5(read);
5533 mem : S3(read);
5534 DECODE : S0; // any decoder for FPU PUSH
5535 D0 : S1; // big decoder only
5536 FPU : S4;
5537 MEM : S3; // any mem
5538 %}
5540 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{
5541 instruction_count(3);
5542 src1 : S3(read);
5543 src2 : S3(read);
5544 mem : S3(read);
5545 DECODE : S0(2); // any decoder for FPU PUSH
5546 D0 : S1; // big decoder only
5547 FPU : S4;
5548 MEM : S3; // any mem
5549 %}
5551 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{
5552 instruction_count(3);
5553 src1 : S3(read);
5554 src2 : S3(read);
5555 mem : S4(read);
5556 DECODE : S0; // any decoder for FPU PUSH
5557 D0 : S0(2); // big decoder only
5558 FPU : S4;
5559 MEM : S3(2); // any mem
5560 %}
5562 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5563 instruction_count(2);
5564 src1 : S3(read);
5565 dst : S4(read);
5566 D0 : S0(2); // big decoder only
5567 MEM : S3(2); // any mem
5568 %}
5570 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5571 instruction_count(3);
5572 src1 : S3(read);
5573 src2 : S3(read);
5574 dst : S4(read);
5575 D0 : S0(3); // big decoder only
5576 FPU : S4;
5577 MEM : S3(3); // any mem
5578 %}
5580 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{
5581 instruction_count(3);
5582 src1 : S4(read);
5583 mem : S4(read);
5584 DECODE : S0; // any decoder for FPU PUSH
5585 D0 : S0(2); // big decoder only
5586 FPU : S4;
5587 MEM : S3(2); // any mem
5588 %}
5590 // Float load constant
5591 pipe_class fpu_reg_con(regD dst) %{
5592 instruction_count(2);
5593 dst : S5(write);
5594 D0 : S0; // big decoder only for the load
5595 DECODE : S1; // any decoder for FPU POP
5596 FPU : S4;
5597 MEM : S3; // any mem
5598 %}
5600 // Float load constant
5601 pipe_class fpu_reg_reg_con(regD dst, regD src) %{
5602 instruction_count(3);
5603 dst : S5(write);
5604 src : S3(read);
5605 D0 : S0; // big decoder only for the load
5606 DECODE : S1(2); // any decoder for FPU POP
5607 FPU : S4;
5608 MEM : S3; // any mem
5609 %}
5611 // UnConditional branch
5612 pipe_class pipe_jmp( label labl ) %{
5613 single_instruction;
5614 BR : S3;
5615 %}
5617 // Conditional branch
5618 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5619 single_instruction;
5620 cr : S1(read);
5621 BR : S3;
5622 %}
5624 // Allocation idiom
5625 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5626 instruction_count(1); force_serialization;
5627 fixed_latency(6);
5628 heap_ptr : S3(read);
5629 DECODE : S0(3);
5630 D0 : S2;
5631 MEM : S3;
5632 ALU : S3(2);
5633 dst : S5(write);
5634 BR : S5;
5635 %}
5637 // Generic big/slow expanded idiom
5638 pipe_class pipe_slow( ) %{
5639 instruction_count(10); multiple_bundles; force_serialization;
5640 fixed_latency(100);
5641 D0 : S0(2);
5642 MEM : S3(2);
5643 %}
5645 // The real do-nothing guy
5646 pipe_class empty( ) %{
5647 instruction_count(0);
5648 %}
5650 // Define the class for the Nop node
5651 define %{
5652 MachNop = empty;
5653 %}
5655 %}
5657 //----------INSTRUCTIONS-------------------------------------------------------
5658 //
5659 // match -- States which machine-independent subtree may be replaced
5660 // by this instruction.
5661 // ins_cost -- The estimated cost of this instruction is used by instruction
5662 // selection to identify a minimum cost tree of machine
5663 // instructions that matches a tree of machine-independent
5664 // instructions.
5665 // format -- A string providing the disassembly for this instruction.
5666 // The value of an instruction's operand may be inserted
5667 // by referring to it with a '$' prefix.
5668 // opcode -- Three instruction opcodes may be provided. These are referred
5669 // to within an encode class as $primary, $secondary, and $tertiary
5670 // respectively. The primary opcode is commonly used to
5671 // indicate the type of machine instruction, while secondary
5672 // and tertiary are often used for prefix options or addressing
5673 // modes.
5674 // ins_encode -- A list of encode classes with parameters. The encode class
5675 // name must have been defined in an 'enc_class' specification
5676 // in the encode section of the architecture description.
5678 //----------BSWAP-Instruction--------------------------------------------------
5679 instruct bytes_reverse_int(eRegI dst) %{
5680 match(Set dst (ReverseBytesI dst));
5682 format %{ "BSWAP $dst" %}
5683 opcode(0x0F, 0xC8);
5684 ins_encode( OpcP, OpcSReg(dst) );
5685 ins_pipe( ialu_reg );
5686 %}
5688 instruct bytes_reverse_long(eRegL dst) %{
5689 match(Set dst (ReverseBytesL dst));
5691 format %{ "BSWAP $dst.lo\n\t"
5692 "BSWAP $dst.hi\n\t"
5693 "XCHG $dst.lo $dst.hi" %}
5695 ins_cost(125);
5696 ins_encode( bswap_long_bytes(dst) );
5697 ins_pipe( ialu_reg_reg);
5698 %}
5700 instruct bytes_reverse_unsigned_short(eRegI dst) %{
5701 match(Set dst (ReverseBytesUS dst));
5703 format %{ "BSWAP $dst\n\t"
5704 "SHR $dst,16\n\t" %}
5705 ins_encode %{
5706 __ bswapl($dst$$Register);
5707 __ shrl($dst$$Register, 16);
5708 %}
5709 ins_pipe( ialu_reg );
5710 %}
5712 instruct bytes_reverse_short(eRegI dst) %{
5713 match(Set dst (ReverseBytesS dst));
5715 format %{ "BSWAP $dst\n\t"
5716 "SAR $dst,16\n\t" %}
5717 ins_encode %{
5718 __ bswapl($dst$$Register);
5719 __ sarl($dst$$Register, 16);
5720 %}
5721 ins_pipe( ialu_reg );
5722 %}
5725 //---------- Zeros Count Instructions ------------------------------------------
5727 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
5728 predicate(UseCountLeadingZerosInstruction);
5729 match(Set dst (CountLeadingZerosI src));
5730 effect(KILL cr);
5732 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5733 ins_encode %{
5734 __ lzcntl($dst$$Register, $src$$Register);
5735 %}
5736 ins_pipe(ialu_reg);
5737 %}
5739 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{
5740 predicate(!UseCountLeadingZerosInstruction);
5741 match(Set dst (CountLeadingZerosI src));
5742 effect(KILL cr);
5744 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5745 "JNZ skip\n\t"
5746 "MOV $dst, -1\n"
5747 "skip:\n\t"
5748 "NEG $dst\n\t"
5749 "ADD $dst, 31" %}
5750 ins_encode %{
5751 Register Rdst = $dst$$Register;
5752 Register Rsrc = $src$$Register;
5753 Label skip;
5754 __ bsrl(Rdst, Rsrc);
5755 __ jccb(Assembler::notZero, skip);
5756 __ movl(Rdst, -1);
5757 __ bind(skip);
5758 __ negl(Rdst);
5759 __ addl(Rdst, BitsPerInt - 1);
5760 %}
5761 ins_pipe(ialu_reg);
5762 %}
5764 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
5765 predicate(UseCountLeadingZerosInstruction);
5766 match(Set dst (CountLeadingZerosL src));
5767 effect(TEMP dst, KILL cr);
5769 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5770 "JNC done\n\t"
5771 "LZCNT $dst, $src.lo\n\t"
5772 "ADD $dst, 32\n"
5773 "done:" %}
5774 ins_encode %{
5775 Register Rdst = $dst$$Register;
5776 Register Rsrc = $src$$Register;
5777 Label done;
5778 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5779 __ jccb(Assembler::carryClear, done);
5780 __ lzcntl(Rdst, Rsrc);
5781 __ addl(Rdst, BitsPerInt);
5782 __ bind(done);
5783 %}
5784 ins_pipe(ialu_reg);
5785 %}
5787 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{
5788 predicate(!UseCountLeadingZerosInstruction);
5789 match(Set dst (CountLeadingZerosL src));
5790 effect(TEMP dst, KILL cr);
5792 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5793 "JZ msw_is_zero\n\t"
5794 "ADD $dst, 32\n\t"
5795 "JMP not_zero\n"
5796 "msw_is_zero:\n\t"
5797 "BSR $dst, $src.lo\n\t"
5798 "JNZ not_zero\n\t"
5799 "MOV $dst, -1\n"
5800 "not_zero:\n\t"
5801 "NEG $dst\n\t"
5802 "ADD $dst, 63\n" %}
5803 ins_encode %{
5804 Register Rdst = $dst$$Register;
5805 Register Rsrc = $src$$Register;
5806 Label msw_is_zero;
5807 Label not_zero;
5808 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5809 __ jccb(Assembler::zero, msw_is_zero);
5810 __ addl(Rdst, BitsPerInt);
5811 __ jmpb(not_zero);
5812 __ bind(msw_is_zero);
5813 __ bsrl(Rdst, Rsrc);
5814 __ jccb(Assembler::notZero, not_zero);
5815 __ movl(Rdst, -1);
5816 __ bind(not_zero);
5817 __ negl(Rdst);
5818 __ addl(Rdst, BitsPerLong - 1);
5819 %}
5820 ins_pipe(ialu_reg);
5821 %}
5823 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
5824 match(Set dst (CountTrailingZerosI src));
5825 effect(KILL cr);
5827 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5828 "JNZ done\n\t"
5829 "MOV $dst, 32\n"
5830 "done:" %}
5831 ins_encode %{
5832 Register Rdst = $dst$$Register;
5833 Label done;
5834 __ bsfl(Rdst, $src$$Register);
5835 __ jccb(Assembler::notZero, done);
5836 __ movl(Rdst, BitsPerInt);
5837 __ bind(done);
5838 %}
5839 ins_pipe(ialu_reg);
5840 %}
5842 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
5843 match(Set dst (CountTrailingZerosL src));
5844 effect(TEMP dst, KILL cr);
5846 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5847 "JNZ done\n\t"
5848 "BSF $dst, $src.hi\n\t"
5849 "JNZ msw_not_zero\n\t"
5850 "MOV $dst, 32\n"
5851 "msw_not_zero:\n\t"
5852 "ADD $dst, 32\n"
5853 "done:" %}
5854 ins_encode %{
5855 Register Rdst = $dst$$Register;
5856 Register Rsrc = $src$$Register;
5857 Label msw_not_zero;
5858 Label done;
5859 __ bsfl(Rdst, Rsrc);
5860 __ jccb(Assembler::notZero, done);
5861 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5862 __ jccb(Assembler::notZero, msw_not_zero);
5863 __ movl(Rdst, BitsPerInt);
5864 __ bind(msw_not_zero);
5865 __ addl(Rdst, BitsPerInt);
5866 __ bind(done);
5867 %}
5868 ins_pipe(ialu_reg);
5869 %}
5872 //---------- Population Count Instructions -------------------------------------
5874 instruct popCountI(eRegI dst, eRegI src) %{
5875 predicate(UsePopCountInstruction);
5876 match(Set dst (PopCountI src));
5878 format %{ "POPCNT $dst, $src" %}
5879 ins_encode %{
5880 __ popcntl($dst$$Register, $src$$Register);
5881 %}
5882 ins_pipe(ialu_reg);
5883 %}
5885 instruct popCountI_mem(eRegI dst, memory mem) %{
5886 predicate(UsePopCountInstruction);
5887 match(Set dst (PopCountI (LoadI mem)));
5889 format %{ "POPCNT $dst, $mem" %}
5890 ins_encode %{
5891 __ popcntl($dst$$Register, $mem$$Address);
5892 %}
5893 ins_pipe(ialu_reg);
5894 %}
5896 // Note: Long.bitCount(long) returns an int.
5897 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
5898 predicate(UsePopCountInstruction);
5899 match(Set dst (PopCountL src));
5900 effect(KILL cr, TEMP tmp, TEMP dst);
5902 format %{ "POPCNT $dst, $src.lo\n\t"
5903 "POPCNT $tmp, $src.hi\n\t"
5904 "ADD $dst, $tmp" %}
5905 ins_encode %{
5906 __ popcntl($dst$$Register, $src$$Register);
5907 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5908 __ addl($dst$$Register, $tmp$$Register);
5909 %}
5910 ins_pipe(ialu_reg);
5911 %}
5913 // Note: Long.bitCount(long) returns an int.
5914 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{
5915 predicate(UsePopCountInstruction);
5916 match(Set dst (PopCountL (LoadL mem)));
5917 effect(KILL cr, TEMP tmp, TEMP dst);
5919 format %{ "POPCNT $dst, $mem\n\t"
5920 "POPCNT $tmp, $mem+4\n\t"
5921 "ADD $dst, $tmp" %}
5922 ins_encode %{
5923 //__ popcntl($dst$$Register, $mem$$Address$$first);
5924 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5925 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
5926 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
5927 __ addl($dst$$Register, $tmp$$Register);
5928 %}
5929 ins_pipe(ialu_reg);
5930 %}
5933 //----------Load/Store/Move Instructions---------------------------------------
5934 //----------Load Instructions--------------------------------------------------
5935 // Load Byte (8bit signed)
5936 instruct loadB(xRegI dst, memory mem) %{
5937 match(Set dst (LoadB mem));
5939 ins_cost(125);
5940 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5942 ins_encode %{
5943 __ movsbl($dst$$Register, $mem$$Address);
5944 %}
5946 ins_pipe(ialu_reg_mem);
5947 %}
5949 // Load Byte (8bit signed) into Long Register
5950 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5951 match(Set dst (ConvI2L (LoadB mem)));
5952 effect(KILL cr);
5954 ins_cost(375);
5955 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5956 "MOV $dst.hi,$dst.lo\n\t"
5957 "SAR $dst.hi,7" %}
5959 ins_encode %{
5960 __ movsbl($dst$$Register, $mem$$Address);
5961 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5962 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5963 %}
5965 ins_pipe(ialu_reg_mem);
5966 %}
5968 // Load Unsigned Byte (8bit UNsigned)
5969 instruct loadUB(xRegI dst, memory mem) %{
5970 match(Set dst (LoadUB mem));
5972 ins_cost(125);
5973 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5975 ins_encode %{
5976 __ movzbl($dst$$Register, $mem$$Address);
5977 %}
5979 ins_pipe(ialu_reg_mem);
5980 %}
5982 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5983 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5984 match(Set dst (ConvI2L (LoadUB mem)));
5985 effect(KILL cr);
5987 ins_cost(250);
5988 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5989 "XOR $dst.hi,$dst.hi" %}
5991 ins_encode %{
5992 Register Rdst = $dst$$Register;
5993 __ movzbl(Rdst, $mem$$Address);
5994 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5995 %}
5997 ins_pipe(ialu_reg_mem);
5998 %}
6000 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
6001 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
6002 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
6003 effect(KILL cr);
6005 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
6006 "XOR $dst.hi,$dst.hi\n\t"
6007 "AND $dst.lo,$mask" %}
6008 ins_encode %{
6009 Register Rdst = $dst$$Register;
6010 __ movzbl(Rdst, $mem$$Address);
6011 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6012 __ andl(Rdst, $mask$$constant);
6013 %}
6014 ins_pipe(ialu_reg_mem);
6015 %}
6017 // Load Short (16bit signed)
6018 instruct loadS(eRegI dst, memory mem) %{
6019 match(Set dst (LoadS mem));
6021 ins_cost(125);
6022 format %{ "MOVSX $dst,$mem\t# short" %}
6024 ins_encode %{
6025 __ movswl($dst$$Register, $mem$$Address);
6026 %}
6028 ins_pipe(ialu_reg_mem);
6029 %}
6031 // Load Short (16 bit signed) to Byte (8 bit signed)
6032 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6033 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
6035 ins_cost(125);
6036 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
6037 ins_encode %{
6038 __ movsbl($dst$$Register, $mem$$Address);
6039 %}
6040 ins_pipe(ialu_reg_mem);
6041 %}
6043 // Load Short (16bit signed) into Long Register
6044 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6045 match(Set dst (ConvI2L (LoadS mem)));
6046 effect(KILL cr);
6048 ins_cost(375);
6049 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
6050 "MOV $dst.hi,$dst.lo\n\t"
6051 "SAR $dst.hi,15" %}
6053 ins_encode %{
6054 __ movswl($dst$$Register, $mem$$Address);
6055 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6056 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
6057 %}
6059 ins_pipe(ialu_reg_mem);
6060 %}
6062 // Load Unsigned Short/Char (16bit unsigned)
6063 instruct loadUS(eRegI dst, memory mem) %{
6064 match(Set dst (LoadUS mem));
6066 ins_cost(125);
6067 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
6069 ins_encode %{
6070 __ movzwl($dst$$Register, $mem$$Address);
6071 %}
6073 ins_pipe(ialu_reg_mem);
6074 %}
6076 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
6077 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6078 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
6080 ins_cost(125);
6081 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
6082 ins_encode %{
6083 __ movsbl($dst$$Register, $mem$$Address);
6084 %}
6085 ins_pipe(ialu_reg_mem);
6086 %}
6088 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
6089 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6090 match(Set dst (ConvI2L (LoadUS mem)));
6091 effect(KILL cr);
6093 ins_cost(250);
6094 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
6095 "XOR $dst.hi,$dst.hi" %}
6097 ins_encode %{
6098 __ movzwl($dst$$Register, $mem$$Address);
6099 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6100 %}
6102 ins_pipe(ialu_reg_mem);
6103 %}
6105 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
6106 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6107 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6108 effect(KILL cr);
6110 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
6111 "XOR $dst.hi,$dst.hi" %}
6112 ins_encode %{
6113 Register Rdst = $dst$$Register;
6114 __ movzbl(Rdst, $mem$$Address);
6115 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6116 %}
6117 ins_pipe(ialu_reg_mem);
6118 %}
6120 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6121 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6122 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6123 effect(KILL cr);
6125 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6126 "XOR $dst.hi,$dst.hi\n\t"
6127 "AND $dst.lo,$mask" %}
6128 ins_encode %{
6129 Register Rdst = $dst$$Register;
6130 __ movzwl(Rdst, $mem$$Address);
6131 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6132 __ andl(Rdst, $mask$$constant);
6133 %}
6134 ins_pipe(ialu_reg_mem);
6135 %}
6137 // Load Integer
6138 instruct loadI(eRegI dst, memory mem) %{
6139 match(Set dst (LoadI mem));
6141 ins_cost(125);
6142 format %{ "MOV $dst,$mem\t# int" %}
6144 ins_encode %{
6145 __ movl($dst$$Register, $mem$$Address);
6146 %}
6148 ins_pipe(ialu_reg_mem);
6149 %}
6151 // Load Integer (32 bit signed) to Byte (8 bit signed)
6152 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6153 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6155 ins_cost(125);
6156 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6157 ins_encode %{
6158 __ movsbl($dst$$Register, $mem$$Address);
6159 %}
6160 ins_pipe(ialu_reg_mem);
6161 %}
6163 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6164 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{
6165 match(Set dst (AndI (LoadI mem) mask));
6167 ins_cost(125);
6168 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6169 ins_encode %{
6170 __ movzbl($dst$$Register, $mem$$Address);
6171 %}
6172 ins_pipe(ialu_reg_mem);
6173 %}
6175 // Load Integer (32 bit signed) to Short (16 bit signed)
6176 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{
6177 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6179 ins_cost(125);
6180 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6181 ins_encode %{
6182 __ movswl($dst$$Register, $mem$$Address);
6183 %}
6184 ins_pipe(ialu_reg_mem);
6185 %}
6187 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6188 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{
6189 match(Set dst (AndI (LoadI mem) mask));
6191 ins_cost(125);
6192 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6193 ins_encode %{
6194 __ movzwl($dst$$Register, $mem$$Address);
6195 %}
6196 ins_pipe(ialu_reg_mem);
6197 %}
6199 // Load Integer into Long Register
6200 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6201 match(Set dst (ConvI2L (LoadI mem)));
6202 effect(KILL cr);
6204 ins_cost(375);
6205 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6206 "MOV $dst.hi,$dst.lo\n\t"
6207 "SAR $dst.hi,31" %}
6209 ins_encode %{
6210 __ movl($dst$$Register, $mem$$Address);
6211 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6212 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6213 %}
6215 ins_pipe(ialu_reg_mem);
6216 %}
6218 // Load Integer with mask 0xFF into Long Register
6219 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6220 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6221 effect(KILL cr);
6223 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6224 "XOR $dst.hi,$dst.hi" %}
6225 ins_encode %{
6226 Register Rdst = $dst$$Register;
6227 __ movzbl(Rdst, $mem$$Address);
6228 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6229 %}
6230 ins_pipe(ialu_reg_mem);
6231 %}
6233 // Load Integer with mask 0xFFFF into Long Register
6234 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6235 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6236 effect(KILL cr);
6238 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6239 "XOR $dst.hi,$dst.hi" %}
6240 ins_encode %{
6241 Register Rdst = $dst$$Register;
6242 __ movzwl(Rdst, $mem$$Address);
6243 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6244 %}
6245 ins_pipe(ialu_reg_mem);
6246 %}
6248 // Load Integer with 32-bit mask into Long Register
6249 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6250 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6251 effect(KILL cr);
6253 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6254 "XOR $dst.hi,$dst.hi\n\t"
6255 "AND $dst.lo,$mask" %}
6256 ins_encode %{
6257 Register Rdst = $dst$$Register;
6258 __ movl(Rdst, $mem$$Address);
6259 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6260 __ andl(Rdst, $mask$$constant);
6261 %}
6262 ins_pipe(ialu_reg_mem);
6263 %}
6265 // Load Unsigned Integer into Long Register
6266 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6267 match(Set dst (LoadUI2L mem));
6268 effect(KILL cr);
6270 ins_cost(250);
6271 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6272 "XOR $dst.hi,$dst.hi" %}
6274 ins_encode %{
6275 __ movl($dst$$Register, $mem$$Address);
6276 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6277 %}
6279 ins_pipe(ialu_reg_mem);
6280 %}
6282 // Load Long. Cannot clobber address while loading, so restrict address
6283 // register to ESI
6284 instruct loadL(eRegL dst, load_long_memory mem) %{
6285 predicate(!((LoadLNode*)n)->require_atomic_access());
6286 match(Set dst (LoadL mem));
6288 ins_cost(250);
6289 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6290 "MOV $dst.hi,$mem+4" %}
6292 ins_encode %{
6293 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
6294 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
6295 __ movl($dst$$Register, Amemlo);
6296 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6297 %}
6299 ins_pipe(ialu_reg_long_mem);
6300 %}
6302 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6303 // then store it down to the stack and reload on the int
6304 // side.
6305 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6306 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6307 match(Set dst (LoadL mem));
6309 ins_cost(200);
6310 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6311 "FISTp $dst" %}
6312 ins_encode(enc_loadL_volatile(mem,dst));
6313 ins_pipe( fpu_reg_mem );
6314 %}
6316 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{
6317 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6318 match(Set dst (LoadL mem));
6319 effect(TEMP tmp);
6320 ins_cost(180);
6321 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6322 "MOVSD $dst,$tmp" %}
6323 ins_encode %{
6324 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6325 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6326 %}
6327 ins_pipe( pipe_slow );
6328 %}
6330 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{
6331 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6332 match(Set dst (LoadL mem));
6333 effect(TEMP tmp);
6334 ins_cost(160);
6335 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6336 "MOVD $dst.lo,$tmp\n\t"
6337 "PSRLQ $tmp,32\n\t"
6338 "MOVD $dst.hi,$tmp" %}
6339 ins_encode %{
6340 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6341 __ movdl($dst$$Register, $tmp$$XMMRegister);
6342 __ psrlq($tmp$$XMMRegister, 32);
6343 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6344 %}
6345 ins_pipe( pipe_slow );
6346 %}
6348 // Load Range
6349 instruct loadRange(eRegI dst, memory mem) %{
6350 match(Set dst (LoadRange mem));
6352 ins_cost(125);
6353 format %{ "MOV $dst,$mem" %}
6354 opcode(0x8B);
6355 ins_encode( OpcP, RegMem(dst,mem));
6356 ins_pipe( ialu_reg_mem );
6357 %}
6360 // Load Pointer
6361 instruct loadP(eRegP dst, memory mem) %{
6362 match(Set dst (LoadP mem));
6364 ins_cost(125);
6365 format %{ "MOV $dst,$mem" %}
6366 opcode(0x8B);
6367 ins_encode( OpcP, RegMem(dst,mem));
6368 ins_pipe( ialu_reg_mem );
6369 %}
6371 // Load Klass Pointer
6372 instruct loadKlass(eRegP dst, memory mem) %{
6373 match(Set dst (LoadKlass mem));
6375 ins_cost(125);
6376 format %{ "MOV $dst,$mem" %}
6377 opcode(0x8B);
6378 ins_encode( OpcP, RegMem(dst,mem));
6379 ins_pipe( ialu_reg_mem );
6380 %}
6382 // Load Double
6383 instruct loadD(regD dst, memory mem) %{
6384 predicate(UseSSE<=1);
6385 match(Set dst (LoadD mem));
6387 ins_cost(150);
6388 format %{ "FLD_D ST,$mem\n\t"
6389 "FSTP $dst" %}
6390 opcode(0xDD); /* DD /0 */
6391 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6392 Pop_Reg_D(dst) );
6393 ins_pipe( fpu_reg_mem );
6394 %}
6396 // Load Double to XMM
6397 instruct loadXD(regXD dst, memory mem) %{
6398 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6399 match(Set dst (LoadD mem));
6400 ins_cost(145);
6401 format %{ "MOVSD $dst,$mem" %}
6402 ins_encode %{
6403 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6404 %}
6405 ins_pipe( pipe_slow );
6406 %}
6408 instruct loadXD_partial(regXD dst, memory mem) %{
6409 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6410 match(Set dst (LoadD mem));
6411 ins_cost(145);
6412 format %{ "MOVLPD $dst,$mem" %}
6413 ins_encode %{
6414 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6415 %}
6416 ins_pipe( pipe_slow );
6417 %}
6419 // Load to XMM register (single-precision floating point)
6420 // MOVSS instruction
6421 instruct loadX(regX dst, memory mem) %{
6422 predicate(UseSSE>=1);
6423 match(Set dst (LoadF mem));
6424 ins_cost(145);
6425 format %{ "MOVSS $dst,$mem" %}
6426 ins_encode %{
6427 __ movflt ($dst$$XMMRegister, $mem$$Address);
6428 %}
6429 ins_pipe( pipe_slow );
6430 %}
6432 // Load Float
6433 instruct loadF(regF dst, memory mem) %{
6434 predicate(UseSSE==0);
6435 match(Set dst (LoadF mem));
6437 ins_cost(150);
6438 format %{ "FLD_S ST,$mem\n\t"
6439 "FSTP $dst" %}
6440 opcode(0xD9); /* D9 /0 */
6441 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6442 Pop_Reg_F(dst) );
6443 ins_pipe( fpu_reg_mem );
6444 %}
6446 // Load Aligned Packed Byte to XMM register
6447 instruct loadA8B(regXD dst, memory mem) %{
6448 predicate(UseSSE>=1);
6449 match(Set dst (Load8B mem));
6450 ins_cost(125);
6451 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6452 ins_encode %{
6453 __ movq($dst$$XMMRegister, $mem$$Address);
6454 %}
6455 ins_pipe( pipe_slow );
6456 %}
6458 // Load Aligned Packed Short to XMM register
6459 instruct loadA4S(regXD dst, memory mem) %{
6460 predicate(UseSSE>=1);
6461 match(Set dst (Load4S mem));
6462 ins_cost(125);
6463 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6464 ins_encode %{
6465 __ movq($dst$$XMMRegister, $mem$$Address);
6466 %}
6467 ins_pipe( pipe_slow );
6468 %}
6470 // Load Aligned Packed Char to XMM register
6471 instruct loadA4C(regXD dst, memory mem) %{
6472 predicate(UseSSE>=1);
6473 match(Set dst (Load4C mem));
6474 ins_cost(125);
6475 format %{ "MOVQ $dst,$mem\t! packed4C" %}
6476 ins_encode %{
6477 __ movq($dst$$XMMRegister, $mem$$Address);
6478 %}
6479 ins_pipe( pipe_slow );
6480 %}
6482 // Load Aligned Packed Integer to XMM register
6483 instruct load2IU(regXD dst, memory mem) %{
6484 predicate(UseSSE>=1);
6485 match(Set dst (Load2I mem));
6486 ins_cost(125);
6487 format %{ "MOVQ $dst,$mem\t! packed2I" %}
6488 ins_encode %{
6489 __ movq($dst$$XMMRegister, $mem$$Address);
6490 %}
6491 ins_pipe( pipe_slow );
6492 %}
6494 // Load Aligned Packed Single to XMM
6495 instruct loadA2F(regXD dst, memory mem) %{
6496 predicate(UseSSE>=1);
6497 match(Set dst (Load2F mem));
6498 ins_cost(145);
6499 format %{ "MOVQ $dst,$mem\t! packed2F" %}
6500 ins_encode %{
6501 __ movq($dst$$XMMRegister, $mem$$Address);
6502 %}
6503 ins_pipe( pipe_slow );
6504 %}
6506 // Load Effective Address
6507 instruct leaP8(eRegP dst, indOffset8 mem) %{
6508 match(Set dst mem);
6510 ins_cost(110);
6511 format %{ "LEA $dst,$mem" %}
6512 opcode(0x8D);
6513 ins_encode( OpcP, RegMem(dst,mem));
6514 ins_pipe( ialu_reg_reg_fat );
6515 %}
6517 instruct leaP32(eRegP dst, indOffset32 mem) %{
6518 match(Set dst mem);
6520 ins_cost(110);
6521 format %{ "LEA $dst,$mem" %}
6522 opcode(0x8D);
6523 ins_encode( OpcP, RegMem(dst,mem));
6524 ins_pipe( ialu_reg_reg_fat );
6525 %}
6527 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6528 match(Set dst mem);
6530 ins_cost(110);
6531 format %{ "LEA $dst,$mem" %}
6532 opcode(0x8D);
6533 ins_encode( OpcP, RegMem(dst,mem));
6534 ins_pipe( ialu_reg_reg_fat );
6535 %}
6537 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6538 match(Set dst mem);
6540 ins_cost(110);
6541 format %{ "LEA $dst,$mem" %}
6542 opcode(0x8D);
6543 ins_encode( OpcP, RegMem(dst,mem));
6544 ins_pipe( ialu_reg_reg_fat );
6545 %}
6547 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6548 match(Set dst mem);
6550 ins_cost(110);
6551 format %{ "LEA $dst,$mem" %}
6552 opcode(0x8D);
6553 ins_encode( OpcP, RegMem(dst,mem));
6554 ins_pipe( ialu_reg_reg_fat );
6555 %}
6557 // Load Constant
6558 instruct loadConI(eRegI dst, immI src) %{
6559 match(Set dst src);
6561 format %{ "MOV $dst,$src" %}
6562 ins_encode( LdImmI(dst, src) );
6563 ins_pipe( ialu_reg_fat );
6564 %}
6566 // Load Constant zero
6567 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
6568 match(Set dst src);
6569 effect(KILL cr);
6571 ins_cost(50);
6572 format %{ "XOR $dst,$dst" %}
6573 opcode(0x33); /* + rd */
6574 ins_encode( OpcP, RegReg( dst, dst ) );
6575 ins_pipe( ialu_reg );
6576 %}
6578 instruct loadConP(eRegP dst, immP src) %{
6579 match(Set dst src);
6581 format %{ "MOV $dst,$src" %}
6582 opcode(0xB8); /* + rd */
6583 ins_encode( LdImmP(dst, src) );
6584 ins_pipe( ialu_reg_fat );
6585 %}
6587 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6588 match(Set dst src);
6589 effect(KILL cr);
6590 ins_cost(200);
6591 format %{ "MOV $dst.lo,$src.lo\n\t"
6592 "MOV $dst.hi,$src.hi" %}
6593 opcode(0xB8);
6594 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6595 ins_pipe( ialu_reg_long_fat );
6596 %}
6598 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6599 match(Set dst src);
6600 effect(KILL cr);
6601 ins_cost(150);
6602 format %{ "XOR $dst.lo,$dst.lo\n\t"
6603 "XOR $dst.hi,$dst.hi" %}
6604 opcode(0x33,0x33);
6605 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6606 ins_pipe( ialu_reg_long );
6607 %}
6609 // The instruction usage is guarded by predicate in operand immF().
6610 instruct loadConF(regF dst, immF con) %{
6611 match(Set dst con);
6612 ins_cost(125);
6613 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6614 "FSTP $dst" %}
6615 ins_encode %{
6616 __ fld_s($constantaddress($con));
6617 __ fstp_d($dst$$reg);
6618 %}
6619 ins_pipe(fpu_reg_con);
6620 %}
6622 // The instruction usage is guarded by predicate in operand immF0().
6623 instruct loadConF0(regF dst, immF0 con) %{
6624 match(Set dst con);
6625 ins_cost(125);
6626 format %{ "FLDZ ST\n\t"
6627 "FSTP $dst" %}
6628 ins_encode %{
6629 __ fldz();
6630 __ fstp_d($dst$$reg);
6631 %}
6632 ins_pipe(fpu_reg_con);
6633 %}
6635 // The instruction usage is guarded by predicate in operand immF1().
6636 instruct loadConF1(regF dst, immF1 con) %{
6637 match(Set dst con);
6638 ins_cost(125);
6639 format %{ "FLD1 ST\n\t"
6640 "FSTP $dst" %}
6641 ins_encode %{
6642 __ fld1();
6643 __ fstp_d($dst$$reg);
6644 %}
6645 ins_pipe(fpu_reg_con);
6646 %}
6648 // The instruction usage is guarded by predicate in operand immXF().
6649 instruct loadConX(regX dst, immXF con) %{
6650 match(Set dst con);
6651 ins_cost(125);
6652 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6653 ins_encode %{
6654 __ movflt($dst$$XMMRegister, $constantaddress($con));
6655 %}
6656 ins_pipe(pipe_slow);
6657 %}
6659 // The instruction usage is guarded by predicate in operand immXF0().
6660 instruct loadConX0(regX dst, immXF0 src) %{
6661 match(Set dst src);
6662 ins_cost(100);
6663 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6664 ins_encode %{
6665 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6666 %}
6667 ins_pipe(pipe_slow);
6668 %}
6670 // The instruction usage is guarded by predicate in operand immD().
6671 instruct loadConD(regD dst, immD con) %{
6672 match(Set dst con);
6673 ins_cost(125);
6675 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6676 "FSTP $dst" %}
6677 ins_encode %{
6678 __ fld_d($constantaddress($con));
6679 __ fstp_d($dst$$reg);
6680 %}
6681 ins_pipe(fpu_reg_con);
6682 %}
6684 // The instruction usage is guarded by predicate in operand immD0().
6685 instruct loadConD0(regD dst, immD0 con) %{
6686 match(Set dst con);
6687 ins_cost(125);
6689 format %{ "FLDZ ST\n\t"
6690 "FSTP $dst" %}
6691 ins_encode %{
6692 __ fldz();
6693 __ fstp_d($dst$$reg);
6694 %}
6695 ins_pipe(fpu_reg_con);
6696 %}
6698 // The instruction usage is guarded by predicate in operand immD1().
6699 instruct loadConD1(regD dst, immD1 con) %{
6700 match(Set dst con);
6701 ins_cost(125);
6703 format %{ "FLD1 ST\n\t"
6704 "FSTP $dst" %}
6705 ins_encode %{
6706 __ fld1();
6707 __ fstp_d($dst$$reg);
6708 %}
6709 ins_pipe(fpu_reg_con);
6710 %}
6712 // The instruction usage is guarded by predicate in operand immXD().
6713 instruct loadConXD(regXD dst, immXD con) %{
6714 match(Set dst con);
6715 ins_cost(125);
6716 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6717 ins_encode %{
6718 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6719 %}
6720 ins_pipe(pipe_slow);
6721 %}
6723 // The instruction usage is guarded by predicate in operand immXD0().
6724 instruct loadConXD0(regXD dst, immXD0 src) %{
6725 match(Set dst src);
6726 ins_cost(100);
6727 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6728 ins_encode %{
6729 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6730 %}
6731 ins_pipe( pipe_slow );
6732 %}
6734 // Load Stack Slot
6735 instruct loadSSI(eRegI dst, stackSlotI src) %{
6736 match(Set dst src);
6737 ins_cost(125);
6739 format %{ "MOV $dst,$src" %}
6740 opcode(0x8B);
6741 ins_encode( OpcP, RegMem(dst,src));
6742 ins_pipe( ialu_reg_mem );
6743 %}
6745 instruct loadSSL(eRegL dst, stackSlotL src) %{
6746 match(Set dst src);
6748 ins_cost(200);
6749 format %{ "MOV $dst,$src.lo\n\t"
6750 "MOV $dst+4,$src.hi" %}
6751 opcode(0x8B, 0x8B);
6752 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6753 ins_pipe( ialu_mem_long_reg );
6754 %}
6756 // Load Stack Slot
6757 instruct loadSSP(eRegP dst, stackSlotP src) %{
6758 match(Set dst src);
6759 ins_cost(125);
6761 format %{ "MOV $dst,$src" %}
6762 opcode(0x8B);
6763 ins_encode( OpcP, RegMem(dst,src));
6764 ins_pipe( ialu_reg_mem );
6765 %}
6767 // Load Stack Slot
6768 instruct loadSSF(regF dst, stackSlotF src) %{
6769 match(Set dst src);
6770 ins_cost(125);
6772 format %{ "FLD_S $src\n\t"
6773 "FSTP $dst" %}
6774 opcode(0xD9); /* D9 /0, FLD m32real */
6775 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6776 Pop_Reg_F(dst) );
6777 ins_pipe( fpu_reg_mem );
6778 %}
6780 // Load Stack Slot
6781 instruct loadSSD(regD dst, stackSlotD src) %{
6782 match(Set dst src);
6783 ins_cost(125);
6785 format %{ "FLD_D $src\n\t"
6786 "FSTP $dst" %}
6787 opcode(0xDD); /* DD /0, FLD m64real */
6788 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6789 Pop_Reg_D(dst) );
6790 ins_pipe( fpu_reg_mem );
6791 %}
6793 // Prefetch instructions.
6794 // Must be safe to execute with invalid address (cannot fault).
6796 instruct prefetchr0( memory mem ) %{
6797 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6798 match(PrefetchRead mem);
6799 ins_cost(0);
6800 size(0);
6801 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6802 ins_encode();
6803 ins_pipe(empty);
6804 %}
6806 instruct prefetchr( memory mem ) %{
6807 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6808 match(PrefetchRead mem);
6809 ins_cost(100);
6811 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6812 ins_encode %{
6813 __ prefetchr($mem$$Address);
6814 %}
6815 ins_pipe(ialu_mem);
6816 %}
6818 instruct prefetchrNTA( memory mem ) %{
6819 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6820 match(PrefetchRead mem);
6821 ins_cost(100);
6823 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6824 ins_encode %{
6825 __ prefetchnta($mem$$Address);
6826 %}
6827 ins_pipe(ialu_mem);
6828 %}
6830 instruct prefetchrT0( memory mem ) %{
6831 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6832 match(PrefetchRead mem);
6833 ins_cost(100);
6835 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6836 ins_encode %{
6837 __ prefetcht0($mem$$Address);
6838 %}
6839 ins_pipe(ialu_mem);
6840 %}
6842 instruct prefetchrT2( memory mem ) %{
6843 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6844 match(PrefetchRead mem);
6845 ins_cost(100);
6847 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6848 ins_encode %{
6849 __ prefetcht2($mem$$Address);
6850 %}
6851 ins_pipe(ialu_mem);
6852 %}
6854 instruct prefetchw0( memory mem ) %{
6855 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6856 match(PrefetchWrite mem);
6857 ins_cost(0);
6858 size(0);
6859 format %{ "Prefetch (non-SSE is empty encoding)" %}
6860 ins_encode();
6861 ins_pipe(empty);
6862 %}
6864 instruct prefetchw( memory mem ) %{
6865 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6866 match( PrefetchWrite mem );
6867 ins_cost(100);
6869 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6870 ins_encode %{
6871 __ prefetchw($mem$$Address);
6872 %}
6873 ins_pipe(ialu_mem);
6874 %}
6876 instruct prefetchwNTA( memory mem ) %{
6877 predicate(UseSSE>=1);
6878 match(PrefetchWrite mem);
6879 ins_cost(100);
6881 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6882 ins_encode %{
6883 __ prefetchnta($mem$$Address);
6884 %}
6885 ins_pipe(ialu_mem);
6886 %}
6888 // Prefetch instructions for allocation.
6890 instruct prefetchAlloc0( memory mem ) %{
6891 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6892 match(PrefetchAllocation mem);
6893 ins_cost(0);
6894 size(0);
6895 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6896 ins_encode();
6897 ins_pipe(empty);
6898 %}
6900 instruct prefetchAlloc( memory mem ) %{
6901 predicate(AllocatePrefetchInstr==3);
6902 match( PrefetchAllocation mem );
6903 ins_cost(100);
6905 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6906 ins_encode %{
6907 __ prefetchw($mem$$Address);
6908 %}
6909 ins_pipe(ialu_mem);
6910 %}
6912 instruct prefetchAllocNTA( memory mem ) %{
6913 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6914 match(PrefetchAllocation mem);
6915 ins_cost(100);
6917 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6918 ins_encode %{
6919 __ prefetchnta($mem$$Address);
6920 %}
6921 ins_pipe(ialu_mem);
6922 %}
6924 instruct prefetchAllocT0( memory mem ) %{
6925 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6926 match(PrefetchAllocation mem);
6927 ins_cost(100);
6929 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6930 ins_encode %{
6931 __ prefetcht0($mem$$Address);
6932 %}
6933 ins_pipe(ialu_mem);
6934 %}
6936 instruct prefetchAllocT2( memory mem ) %{
6937 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6938 match(PrefetchAllocation mem);
6939 ins_cost(100);
6941 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6942 ins_encode %{
6943 __ prefetcht2($mem$$Address);
6944 %}
6945 ins_pipe(ialu_mem);
6946 %}
6948 //----------Store Instructions-------------------------------------------------
6950 // Store Byte
6951 instruct storeB(memory mem, xRegI src) %{
6952 match(Set mem (StoreB mem src));
6954 ins_cost(125);
6955 format %{ "MOV8 $mem,$src" %}
6956 opcode(0x88);
6957 ins_encode( OpcP, RegMem( src, mem ) );
6958 ins_pipe( ialu_mem_reg );
6959 %}
6961 // Store Char/Short
6962 instruct storeC(memory mem, eRegI src) %{
6963 match(Set mem (StoreC mem src));
6965 ins_cost(125);
6966 format %{ "MOV16 $mem,$src" %}
6967 opcode(0x89, 0x66);
6968 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6969 ins_pipe( ialu_mem_reg );
6970 %}
6972 // Store Integer
6973 instruct storeI(memory mem, eRegI src) %{
6974 match(Set mem (StoreI mem src));
6976 ins_cost(125);
6977 format %{ "MOV $mem,$src" %}
6978 opcode(0x89);
6979 ins_encode( OpcP, RegMem( src, mem ) );
6980 ins_pipe( ialu_mem_reg );
6981 %}
6983 // Store Long
6984 instruct storeL(long_memory mem, eRegL src) %{
6985 predicate(!((StoreLNode*)n)->require_atomic_access());
6986 match(Set mem (StoreL mem src));
6988 ins_cost(200);
6989 format %{ "MOV $mem,$src.lo\n\t"
6990 "MOV $mem+4,$src.hi" %}
6991 opcode(0x89, 0x89);
6992 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6993 ins_pipe( ialu_mem_long_reg );
6994 %}
6996 // Store Long to Integer
6997 instruct storeL2I(memory mem, eRegL src) %{
6998 match(Set mem (StoreI mem (ConvL2I src)));
7000 format %{ "MOV $mem,$src.lo\t# long -> int" %}
7001 ins_encode %{
7002 __ movl($mem$$Address, $src$$Register);
7003 %}
7004 ins_pipe(ialu_mem_reg);
7005 %}
7007 // Volatile Store Long. Must be atomic, so move it into
7008 // the FP TOS and then do a 64-bit FIST. Has to probe the
7009 // target address before the store (for null-ptr checks)
7010 // so the memory operand is used twice in the encoding.
7011 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
7012 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
7013 match(Set mem (StoreL mem src));
7014 effect( KILL cr );
7015 ins_cost(400);
7016 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7017 "FILD $src\n\t"
7018 "FISTp $mem\t # 64-bit atomic volatile long store" %}
7019 opcode(0x3B);
7020 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
7021 ins_pipe( fpu_reg_mem );
7022 %}
7024 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{
7025 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7026 match(Set mem (StoreL mem src));
7027 effect( TEMP tmp, KILL cr );
7028 ins_cost(380);
7029 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7030 "MOVSD $tmp,$src\n\t"
7031 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7032 ins_encode %{
7033 __ cmpl(rax, $mem$$Address);
7034 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
7035 __ movdbl($mem$$Address, $tmp$$XMMRegister);
7036 %}
7037 ins_pipe( pipe_slow );
7038 %}
7040 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{
7041 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7042 match(Set mem (StoreL mem src));
7043 effect( TEMP tmp2 , TEMP tmp, KILL cr );
7044 ins_cost(360);
7045 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7046 "MOVD $tmp,$src.lo\n\t"
7047 "MOVD $tmp2,$src.hi\n\t"
7048 "PUNPCKLDQ $tmp,$tmp2\n\t"
7049 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7050 ins_encode %{
7051 __ cmpl(rax, $mem$$Address);
7052 __ movdl($tmp$$XMMRegister, $src$$Register);
7053 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
7054 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
7055 __ movdbl($mem$$Address, $tmp$$XMMRegister);
7056 %}
7057 ins_pipe( pipe_slow );
7058 %}
7060 // Store Pointer; for storing unknown oops and raw pointers
7061 instruct storeP(memory mem, anyRegP src) %{
7062 match(Set mem (StoreP mem src));
7064 ins_cost(125);
7065 format %{ "MOV $mem,$src" %}
7066 opcode(0x89);
7067 ins_encode( OpcP, RegMem( src, mem ) );
7068 ins_pipe( ialu_mem_reg );
7069 %}
7071 // Store Integer Immediate
7072 instruct storeImmI(memory mem, immI src) %{
7073 match(Set mem (StoreI mem src));
7075 ins_cost(150);
7076 format %{ "MOV $mem,$src" %}
7077 opcode(0xC7); /* C7 /0 */
7078 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7079 ins_pipe( ialu_mem_imm );
7080 %}
7082 // Store Short/Char Immediate
7083 instruct storeImmI16(memory mem, immI16 src) %{
7084 predicate(UseStoreImmI16);
7085 match(Set mem (StoreC mem src));
7087 ins_cost(150);
7088 format %{ "MOV16 $mem,$src" %}
7089 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7090 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
7091 ins_pipe( ialu_mem_imm );
7092 %}
7094 // Store Pointer Immediate; null pointers or constant oops that do not
7095 // need card-mark barriers.
7096 instruct storeImmP(memory mem, immP src) %{
7097 match(Set mem (StoreP mem src));
7099 ins_cost(150);
7100 format %{ "MOV $mem,$src" %}
7101 opcode(0xC7); /* C7 /0 */
7102 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7103 ins_pipe( ialu_mem_imm );
7104 %}
7106 // Store Byte Immediate
7107 instruct storeImmB(memory mem, immI8 src) %{
7108 match(Set mem (StoreB mem src));
7110 ins_cost(150);
7111 format %{ "MOV8 $mem,$src" %}
7112 opcode(0xC6); /* C6 /0 */
7113 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7114 ins_pipe( ialu_mem_imm );
7115 %}
7117 // Store Aligned Packed Byte XMM register to memory
7118 instruct storeA8B(memory mem, regXD src) %{
7119 predicate(UseSSE>=1);
7120 match(Set mem (Store8B mem src));
7121 ins_cost(145);
7122 format %{ "MOVQ $mem,$src\t! packed8B" %}
7123 ins_encode %{
7124 __ movq($mem$$Address, $src$$XMMRegister);
7125 %}
7126 ins_pipe( pipe_slow );
7127 %}
7129 // Store Aligned Packed Char/Short XMM register to memory
7130 instruct storeA4C(memory mem, regXD src) %{
7131 predicate(UseSSE>=1);
7132 match(Set mem (Store4C mem src));
7133 ins_cost(145);
7134 format %{ "MOVQ $mem,$src\t! packed4C" %}
7135 ins_encode %{
7136 __ movq($mem$$Address, $src$$XMMRegister);
7137 %}
7138 ins_pipe( pipe_slow );
7139 %}
7141 // Store Aligned Packed Integer XMM register to memory
7142 instruct storeA2I(memory mem, regXD src) %{
7143 predicate(UseSSE>=1);
7144 match(Set mem (Store2I mem src));
7145 ins_cost(145);
7146 format %{ "MOVQ $mem,$src\t! packed2I" %}
7147 ins_encode %{
7148 __ movq($mem$$Address, $src$$XMMRegister);
7149 %}
7150 ins_pipe( pipe_slow );
7151 %}
7153 // Store CMS card-mark Immediate
7154 instruct storeImmCM(memory mem, immI8 src) %{
7155 match(Set mem (StoreCM mem src));
7157 ins_cost(150);
7158 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7159 opcode(0xC6); /* C6 /0 */
7160 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7161 ins_pipe( ialu_mem_imm );
7162 %}
7164 // Store Double
7165 instruct storeD( memory mem, regDPR1 src) %{
7166 predicate(UseSSE<=1);
7167 match(Set mem (StoreD mem src));
7169 ins_cost(100);
7170 format %{ "FST_D $mem,$src" %}
7171 opcode(0xDD); /* DD /2 */
7172 ins_encode( enc_FP_store(mem,src) );
7173 ins_pipe( fpu_mem_reg );
7174 %}
7176 // Store double does rounding on x86
7177 instruct storeD_rounded( memory mem, regDPR1 src) %{
7178 predicate(UseSSE<=1);
7179 match(Set mem (StoreD mem (RoundDouble src)));
7181 ins_cost(100);
7182 format %{ "FST_D $mem,$src\t# round" %}
7183 opcode(0xDD); /* DD /2 */
7184 ins_encode( enc_FP_store(mem,src) );
7185 ins_pipe( fpu_mem_reg );
7186 %}
7188 // Store XMM register to memory (double-precision floating points)
7189 // MOVSD instruction
7190 instruct storeXD(memory mem, regXD src) %{
7191 predicate(UseSSE>=2);
7192 match(Set mem (StoreD mem src));
7193 ins_cost(95);
7194 format %{ "MOVSD $mem,$src" %}
7195 ins_encode %{
7196 __ movdbl($mem$$Address, $src$$XMMRegister);
7197 %}
7198 ins_pipe( pipe_slow );
7199 %}
7201 // Store XMM register to memory (single-precision floating point)
7202 // MOVSS instruction
7203 instruct storeX(memory mem, regX src) %{
7204 predicate(UseSSE>=1);
7205 match(Set mem (StoreF mem src));
7206 ins_cost(95);
7207 format %{ "MOVSS $mem,$src" %}
7208 ins_encode %{
7209 __ movflt($mem$$Address, $src$$XMMRegister);
7210 %}
7211 ins_pipe( pipe_slow );
7212 %}
7214 // Store Aligned Packed Single Float XMM register to memory
7215 instruct storeA2F(memory mem, regXD src) %{
7216 predicate(UseSSE>=1);
7217 match(Set mem (Store2F mem src));
7218 ins_cost(145);
7219 format %{ "MOVQ $mem,$src\t! packed2F" %}
7220 ins_encode %{
7221 __ movq($mem$$Address, $src$$XMMRegister);
7222 %}
7223 ins_pipe( pipe_slow );
7224 %}
7226 // Store Float
7227 instruct storeF( memory mem, regFPR1 src) %{
7228 predicate(UseSSE==0);
7229 match(Set mem (StoreF mem src));
7231 ins_cost(100);
7232 format %{ "FST_S $mem,$src" %}
7233 opcode(0xD9); /* D9 /2 */
7234 ins_encode( enc_FP_store(mem,src) );
7235 ins_pipe( fpu_mem_reg );
7236 %}
7238 // Store Float does rounding on x86
7239 instruct storeF_rounded( memory mem, regFPR1 src) %{
7240 predicate(UseSSE==0);
7241 match(Set mem (StoreF mem (RoundFloat src)));
7243 ins_cost(100);
7244 format %{ "FST_S $mem,$src\t# round" %}
7245 opcode(0xD9); /* D9 /2 */
7246 ins_encode( enc_FP_store(mem,src) );
7247 ins_pipe( fpu_mem_reg );
7248 %}
7250 // Store Float does rounding on x86
7251 instruct storeF_Drounded( memory mem, regDPR1 src) %{
7252 predicate(UseSSE<=1);
7253 match(Set mem (StoreF mem (ConvD2F src)));
7255 ins_cost(100);
7256 format %{ "FST_S $mem,$src\t# D-round" %}
7257 opcode(0xD9); /* D9 /2 */
7258 ins_encode( enc_FP_store(mem,src) );
7259 ins_pipe( fpu_mem_reg );
7260 %}
7262 // Store immediate Float value (it is faster than store from FPU register)
7263 // The instruction usage is guarded by predicate in operand immF().
7264 instruct storeF_imm( memory mem, immF src) %{
7265 match(Set mem (StoreF mem src));
7267 ins_cost(50);
7268 format %{ "MOV $mem,$src\t# store float" %}
7269 opcode(0xC7); /* C7 /0 */
7270 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7271 ins_pipe( ialu_mem_imm );
7272 %}
7274 // Store immediate Float value (it is faster than store from XMM register)
7275 // The instruction usage is guarded by predicate in operand immXF().
7276 instruct storeX_imm( memory mem, immXF src) %{
7277 match(Set mem (StoreF mem src));
7279 ins_cost(50);
7280 format %{ "MOV $mem,$src\t# store float" %}
7281 opcode(0xC7); /* C7 /0 */
7282 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src ));
7283 ins_pipe( ialu_mem_imm );
7284 %}
7286 // Store Integer to stack slot
7287 instruct storeSSI(stackSlotI dst, eRegI src) %{
7288 match(Set dst src);
7290 ins_cost(100);
7291 format %{ "MOV $dst,$src" %}
7292 opcode(0x89);
7293 ins_encode( OpcPRegSS( dst, src ) );
7294 ins_pipe( ialu_mem_reg );
7295 %}
7297 // Store Integer to stack slot
7298 instruct storeSSP(stackSlotP dst, eRegP src) %{
7299 match(Set dst src);
7301 ins_cost(100);
7302 format %{ "MOV $dst,$src" %}
7303 opcode(0x89);
7304 ins_encode( OpcPRegSS( dst, src ) );
7305 ins_pipe( ialu_mem_reg );
7306 %}
7308 // Store Long to stack slot
7309 instruct storeSSL(stackSlotL dst, eRegL src) %{
7310 match(Set dst src);
7312 ins_cost(200);
7313 format %{ "MOV $dst,$src.lo\n\t"
7314 "MOV $dst+4,$src.hi" %}
7315 opcode(0x89, 0x89);
7316 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7317 ins_pipe( ialu_mem_long_reg );
7318 %}
7320 //----------MemBar Instructions-----------------------------------------------
7321 // Memory barrier flavors
7323 instruct membar_acquire() %{
7324 match(MemBarAcquire);
7325 ins_cost(400);
7327 size(0);
7328 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7329 ins_encode();
7330 ins_pipe(empty);
7331 %}
7333 instruct membar_acquire_lock() %{
7334 match(MemBarAcquireLock);
7335 ins_cost(0);
7337 size(0);
7338 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7339 ins_encode( );
7340 ins_pipe(empty);
7341 %}
7343 instruct membar_release() %{
7344 match(MemBarRelease);
7345 ins_cost(400);
7347 size(0);
7348 format %{ "MEMBAR-release ! (empty encoding)" %}
7349 ins_encode( );
7350 ins_pipe(empty);
7351 %}
7353 instruct membar_release_lock() %{
7354 match(MemBarReleaseLock);
7355 ins_cost(0);
7357 size(0);
7358 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7359 ins_encode( );
7360 ins_pipe(empty);
7361 %}
7363 instruct membar_volatile(eFlagsReg cr) %{
7364 match(MemBarVolatile);
7365 effect(KILL cr);
7366 ins_cost(400);
7368 format %{
7369 $$template
7370 if (os::is_MP()) {
7371 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7372 } else {
7373 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7374 }
7375 %}
7376 ins_encode %{
7377 __ membar(Assembler::StoreLoad);
7378 %}
7379 ins_pipe(pipe_slow);
7380 %}
7382 instruct unnecessary_membar_volatile() %{
7383 match(MemBarVolatile);
7384 predicate(Matcher::post_store_load_barrier(n));
7385 ins_cost(0);
7387 size(0);
7388 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7389 ins_encode( );
7390 ins_pipe(empty);
7391 %}
7393 //----------Move Instructions--------------------------------------------------
7394 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7395 match(Set dst (CastX2P src));
7396 format %{ "# X2P $dst, $src" %}
7397 ins_encode( /*empty encoding*/ );
7398 ins_cost(0);
7399 ins_pipe(empty);
7400 %}
7402 instruct castP2X(eRegI dst, eRegP src ) %{
7403 match(Set dst (CastP2X src));
7404 ins_cost(50);
7405 format %{ "MOV $dst, $src\t# CastP2X" %}
7406 ins_encode( enc_Copy( dst, src) );
7407 ins_pipe( ialu_reg_reg );
7408 %}
7410 //----------Conditional Move---------------------------------------------------
7411 // Conditional move
7412 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, eRegI dst, eRegI src) %{
7413 predicate(!VM_Version::supports_cmov() );
7414 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7415 ins_cost(200);
7416 format %{ "J$cop,us skip\t# signed cmove\n\t"
7417 "MOV $dst,$src\n"
7418 "skip:" %}
7419 ins_encode %{
7420 Label Lskip;
7421 // Invert sense of branch from sense of CMOV
7422 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7423 __ movl($dst$$Register, $src$$Register);
7424 __ bind(Lskip);
7425 %}
7426 ins_pipe( pipe_cmov_reg );
7427 %}
7429 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src) %{
7430 predicate(!VM_Version::supports_cmov() );
7431 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7432 ins_cost(200);
7433 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7434 "MOV $dst,$src\n"
7435 "skip:" %}
7436 ins_encode %{
7437 Label Lskip;
7438 // Invert sense of branch from sense of CMOV
7439 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7440 __ movl($dst$$Register, $src$$Register);
7441 __ bind(Lskip);
7442 %}
7443 ins_pipe( pipe_cmov_reg );
7444 %}
7446 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
7447 predicate(VM_Version::supports_cmov() );
7448 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7449 ins_cost(200);
7450 format %{ "CMOV$cop $dst,$src" %}
7451 opcode(0x0F,0x40);
7452 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7453 ins_pipe( pipe_cmov_reg );
7454 %}
7456 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
7457 predicate(VM_Version::supports_cmov() );
7458 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7459 ins_cost(200);
7460 format %{ "CMOV$cop $dst,$src" %}
7461 opcode(0x0F,0x40);
7462 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7463 ins_pipe( pipe_cmov_reg );
7464 %}
7466 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
7467 predicate(VM_Version::supports_cmov() );
7468 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7469 ins_cost(200);
7470 expand %{
7471 cmovI_regU(cop, cr, dst, src);
7472 %}
7473 %}
7475 // Conditional move
7476 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
7477 predicate(VM_Version::supports_cmov() );
7478 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7479 ins_cost(250);
7480 format %{ "CMOV$cop $dst,$src" %}
7481 opcode(0x0F,0x40);
7482 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7483 ins_pipe( pipe_cmov_mem );
7484 %}
7486 // Conditional move
7487 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
7488 predicate(VM_Version::supports_cmov() );
7489 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7490 ins_cost(250);
7491 format %{ "CMOV$cop $dst,$src" %}
7492 opcode(0x0F,0x40);
7493 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7494 ins_pipe( pipe_cmov_mem );
7495 %}
7497 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
7498 predicate(VM_Version::supports_cmov() );
7499 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7500 ins_cost(250);
7501 expand %{
7502 cmovI_memU(cop, cr, dst, src);
7503 %}
7504 %}
7506 // Conditional move
7507 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7508 predicate(VM_Version::supports_cmov() );
7509 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7510 ins_cost(200);
7511 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7512 opcode(0x0F,0x40);
7513 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7514 ins_pipe( pipe_cmov_reg );
7515 %}
7517 // Conditional move (non-P6 version)
7518 // Note: a CMoveP is generated for stubs and native wrappers
7519 // regardless of whether we are on a P6, so we
7520 // emulate a cmov here
7521 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7522 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7523 ins_cost(300);
7524 format %{ "Jn$cop skip\n\t"
7525 "MOV $dst,$src\t# pointer\n"
7526 "skip:" %}
7527 opcode(0x8b);
7528 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7529 ins_pipe( pipe_cmov_reg );
7530 %}
7532 // Conditional move
7533 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7534 predicate(VM_Version::supports_cmov() );
7535 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7536 ins_cost(200);
7537 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7538 opcode(0x0F,0x40);
7539 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7540 ins_pipe( pipe_cmov_reg );
7541 %}
7543 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7544 predicate(VM_Version::supports_cmov() );
7545 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7546 ins_cost(200);
7547 expand %{
7548 cmovP_regU(cop, cr, dst, src);
7549 %}
7550 %}
7552 // DISABLED: Requires the ADLC to emit a bottom_type call that
7553 // correctly meets the two pointer arguments; one is an incoming
7554 // register but the other is a memory operand. ALSO appears to
7555 // be buggy with implicit null checks.
7556 //
7557 //// Conditional move
7558 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7559 // predicate(VM_Version::supports_cmov() );
7560 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7561 // ins_cost(250);
7562 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7563 // opcode(0x0F,0x40);
7564 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7565 // ins_pipe( pipe_cmov_mem );
7566 //%}
7567 //
7568 //// Conditional move
7569 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7570 // predicate(VM_Version::supports_cmov() );
7571 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7572 // ins_cost(250);
7573 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7574 // opcode(0x0F,0x40);
7575 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7576 // ins_pipe( pipe_cmov_mem );
7577 //%}
7579 // Conditional move
7580 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{
7581 predicate(UseSSE<=1);
7582 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7583 ins_cost(200);
7584 format %{ "FCMOV$cop $dst,$src\t# double" %}
7585 opcode(0xDA);
7586 ins_encode( enc_cmov_d(cop,src) );
7587 ins_pipe( pipe_cmovD_reg );
7588 %}
7590 // Conditional move
7591 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{
7592 predicate(UseSSE==0);
7593 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7594 ins_cost(200);
7595 format %{ "FCMOV$cop $dst,$src\t# float" %}
7596 opcode(0xDA);
7597 ins_encode( enc_cmov_d(cop,src) );
7598 ins_pipe( pipe_cmovD_reg );
7599 %}
7601 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7602 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7603 predicate(UseSSE<=1);
7604 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7605 ins_cost(200);
7606 format %{ "Jn$cop skip\n\t"
7607 "MOV $dst,$src\t# double\n"
7608 "skip:" %}
7609 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7610 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) );
7611 ins_pipe( pipe_cmovD_reg );
7612 %}
7614 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7615 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7616 predicate(UseSSE==0);
7617 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7618 ins_cost(200);
7619 format %{ "Jn$cop skip\n\t"
7620 "MOV $dst,$src\t# float\n"
7621 "skip:" %}
7622 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7623 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) );
7624 ins_pipe( pipe_cmovD_reg );
7625 %}
7627 // No CMOVE with SSE/SSE2
7628 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{
7629 predicate (UseSSE>=1);
7630 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7631 ins_cost(200);
7632 format %{ "Jn$cop skip\n\t"
7633 "MOVSS $dst,$src\t# float\n"
7634 "skip:" %}
7635 ins_encode %{
7636 Label skip;
7637 // Invert sense of branch from sense of CMOV
7638 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7639 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7640 __ bind(skip);
7641 %}
7642 ins_pipe( pipe_slow );
7643 %}
7645 // No CMOVE with SSE/SSE2
7646 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{
7647 predicate (UseSSE>=2);
7648 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7649 ins_cost(200);
7650 format %{ "Jn$cop skip\n\t"
7651 "MOVSD $dst,$src\t# float\n"
7652 "skip:" %}
7653 ins_encode %{
7654 Label skip;
7655 // Invert sense of branch from sense of CMOV
7656 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7657 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7658 __ bind(skip);
7659 %}
7660 ins_pipe( pipe_slow );
7661 %}
7663 // unsigned version
7664 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{
7665 predicate (UseSSE>=1);
7666 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7667 ins_cost(200);
7668 format %{ "Jn$cop skip\n\t"
7669 "MOVSS $dst,$src\t# float\n"
7670 "skip:" %}
7671 ins_encode %{
7672 Label skip;
7673 // Invert sense of branch from sense of CMOV
7674 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7675 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7676 __ bind(skip);
7677 %}
7678 ins_pipe( pipe_slow );
7679 %}
7681 instruct fcmovX_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regX dst, regX src) %{
7682 predicate (UseSSE>=1);
7683 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7684 ins_cost(200);
7685 expand %{
7686 fcmovX_regU(cop, cr, dst, src);
7687 %}
7688 %}
7690 // unsigned version
7691 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{
7692 predicate (UseSSE>=2);
7693 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7694 ins_cost(200);
7695 format %{ "Jn$cop skip\n\t"
7696 "MOVSD $dst,$src\t# float\n"
7697 "skip:" %}
7698 ins_encode %{
7699 Label skip;
7700 // Invert sense of branch from sense of CMOV
7701 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7702 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7703 __ bind(skip);
7704 %}
7705 ins_pipe( pipe_slow );
7706 %}
7708 instruct fcmovXD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regXD dst, regXD src) %{
7709 predicate (UseSSE>=2);
7710 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7711 ins_cost(200);
7712 expand %{
7713 fcmovXD_regU(cop, cr, dst, src);
7714 %}
7715 %}
7717 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7718 predicate(VM_Version::supports_cmov() );
7719 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7720 ins_cost(200);
7721 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7722 "CMOV$cop $dst.hi,$src.hi" %}
7723 opcode(0x0F,0x40);
7724 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7725 ins_pipe( pipe_cmov_reg_long );
7726 %}
7728 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7729 predicate(VM_Version::supports_cmov() );
7730 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7731 ins_cost(200);
7732 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7733 "CMOV$cop $dst.hi,$src.hi" %}
7734 opcode(0x0F,0x40);
7735 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7736 ins_pipe( pipe_cmov_reg_long );
7737 %}
7739 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7740 predicate(VM_Version::supports_cmov() );
7741 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7742 ins_cost(200);
7743 expand %{
7744 cmovL_regU(cop, cr, dst, src);
7745 %}
7746 %}
7748 //----------Arithmetic Instructions--------------------------------------------
7749 //----------Addition Instructions----------------------------------------------
7750 // Integer Addition Instructions
7751 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7752 match(Set dst (AddI dst src));
7753 effect(KILL cr);
7755 size(2);
7756 format %{ "ADD $dst,$src" %}
7757 opcode(0x03);
7758 ins_encode( OpcP, RegReg( dst, src) );
7759 ins_pipe( ialu_reg_reg );
7760 %}
7762 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
7763 match(Set dst (AddI dst src));
7764 effect(KILL cr);
7766 format %{ "ADD $dst,$src" %}
7767 opcode(0x81, 0x00); /* /0 id */
7768 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7769 ins_pipe( ialu_reg );
7770 %}
7772 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
7773 predicate(UseIncDec);
7774 match(Set dst (AddI dst src));
7775 effect(KILL cr);
7777 size(1);
7778 format %{ "INC $dst" %}
7779 opcode(0x40); /* */
7780 ins_encode( Opc_plus( primary, dst ) );
7781 ins_pipe( ialu_reg );
7782 %}
7784 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
7785 match(Set dst (AddI src0 src1));
7786 ins_cost(110);
7788 format %{ "LEA $dst,[$src0 + $src1]" %}
7789 opcode(0x8D); /* 0x8D /r */
7790 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7791 ins_pipe( ialu_reg_reg );
7792 %}
7794 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7795 match(Set dst (AddP src0 src1));
7796 ins_cost(110);
7798 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7799 opcode(0x8D); /* 0x8D /r */
7800 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7801 ins_pipe( ialu_reg_reg );
7802 %}
7804 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
7805 predicate(UseIncDec);
7806 match(Set dst (AddI dst src));
7807 effect(KILL cr);
7809 size(1);
7810 format %{ "DEC $dst" %}
7811 opcode(0x48); /* */
7812 ins_encode( Opc_plus( primary, dst ) );
7813 ins_pipe( ialu_reg );
7814 %}
7816 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
7817 match(Set dst (AddP dst src));
7818 effect(KILL cr);
7820 size(2);
7821 format %{ "ADD $dst,$src" %}
7822 opcode(0x03);
7823 ins_encode( OpcP, RegReg( dst, src) );
7824 ins_pipe( ialu_reg_reg );
7825 %}
7827 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7828 match(Set dst (AddP dst src));
7829 effect(KILL cr);
7831 format %{ "ADD $dst,$src" %}
7832 opcode(0x81,0x00); /* Opcode 81 /0 id */
7833 // ins_encode( RegImm( dst, src) );
7834 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7835 ins_pipe( ialu_reg );
7836 %}
7838 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
7839 match(Set dst (AddI dst (LoadI src)));
7840 effect(KILL cr);
7842 ins_cost(125);
7843 format %{ "ADD $dst,$src" %}
7844 opcode(0x03);
7845 ins_encode( OpcP, RegMem( dst, src) );
7846 ins_pipe( ialu_reg_mem );
7847 %}
7849 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
7850 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7851 effect(KILL cr);
7853 ins_cost(150);
7854 format %{ "ADD $dst,$src" %}
7855 opcode(0x01); /* Opcode 01 /r */
7856 ins_encode( OpcP, RegMem( src, dst ) );
7857 ins_pipe( ialu_mem_reg );
7858 %}
7860 // Add Memory with Immediate
7861 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7862 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7863 effect(KILL cr);
7865 ins_cost(125);
7866 format %{ "ADD $dst,$src" %}
7867 opcode(0x81); /* Opcode 81 /0 id */
7868 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7869 ins_pipe( ialu_mem_imm );
7870 %}
7872 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7873 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7874 effect(KILL cr);
7876 ins_cost(125);
7877 format %{ "INC $dst" %}
7878 opcode(0xFF); /* Opcode FF /0 */
7879 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7880 ins_pipe( ialu_mem_imm );
7881 %}
7883 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7884 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7885 effect(KILL cr);
7887 ins_cost(125);
7888 format %{ "DEC $dst" %}
7889 opcode(0xFF); /* Opcode FF /1 */
7890 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7891 ins_pipe( ialu_mem_imm );
7892 %}
7895 instruct checkCastPP( eRegP dst ) %{
7896 match(Set dst (CheckCastPP dst));
7898 size(0);
7899 format %{ "#checkcastPP of $dst" %}
7900 ins_encode( /*empty encoding*/ );
7901 ins_pipe( empty );
7902 %}
7904 instruct castPP( eRegP dst ) %{
7905 match(Set dst (CastPP dst));
7906 format %{ "#castPP of $dst" %}
7907 ins_encode( /*empty encoding*/ );
7908 ins_pipe( empty );
7909 %}
7911 instruct castII( eRegI dst ) %{
7912 match(Set dst (CastII dst));
7913 format %{ "#castII of $dst" %}
7914 ins_encode( /*empty encoding*/ );
7915 ins_cost(0);
7916 ins_pipe( empty );
7917 %}
7920 // Load-locked - same as a regular pointer load when used with compare-swap
7921 instruct loadPLocked(eRegP dst, memory mem) %{
7922 match(Set dst (LoadPLocked mem));
7924 ins_cost(125);
7925 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7926 opcode(0x8B);
7927 ins_encode( OpcP, RegMem(dst,mem));
7928 ins_pipe( ialu_reg_mem );
7929 %}
7931 // LoadLong-locked - same as a volatile long load when used with compare-swap
7932 instruct loadLLocked(stackSlotL dst, memory mem) %{
7933 predicate(UseSSE<=1);
7934 match(Set dst (LoadLLocked mem));
7936 ins_cost(200);
7937 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
7938 "FISTp $dst" %}
7939 ins_encode(enc_loadL_volatile(mem,dst));
7940 ins_pipe( fpu_reg_mem );
7941 %}
7943 instruct loadLX_Locked(stackSlotL dst, memory mem, regXD tmp) %{
7944 predicate(UseSSE>=2);
7945 match(Set dst (LoadLLocked mem));
7946 effect(TEMP tmp);
7947 ins_cost(180);
7948 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7949 "MOVSD $dst,$tmp" %}
7950 ins_encode %{
7951 __ movdbl($tmp$$XMMRegister, $mem$$Address);
7952 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
7953 %}
7954 ins_pipe( pipe_slow );
7955 %}
7957 instruct loadLX_reg_Locked(eRegL dst, memory mem, regXD tmp) %{
7958 predicate(UseSSE>=2);
7959 match(Set dst (LoadLLocked mem));
7960 effect(TEMP tmp);
7961 ins_cost(160);
7962 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7963 "MOVD $dst.lo,$tmp\n\t"
7964 "PSRLQ $tmp,32\n\t"
7965 "MOVD $dst.hi,$tmp" %}
7966 ins_encode %{
7967 __ movdbl($tmp$$XMMRegister, $mem$$Address);
7968 __ movdl($dst$$Register, $tmp$$XMMRegister);
7969 __ psrlq($tmp$$XMMRegister, 32);
7970 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
7971 %}
7972 ins_pipe( pipe_slow );
7973 %}
7975 // Conditional-store of the updated heap-top.
7976 // Used during allocation of the shared heap.
7977 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7978 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7979 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7980 // EAX is killed if there is contention, but then it's also unused.
7981 // In the common case of no contention, EAX holds the new oop address.
7982 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7983 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7984 ins_pipe( pipe_cmpxchg );
7985 %}
7987 // Conditional-store of an int value.
7988 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7989 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
7990 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7991 effect(KILL oldval);
7992 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7993 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7994 ins_pipe( pipe_cmpxchg );
7995 %}
7997 // Conditional-store of a long value.
7998 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7999 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8000 match(Set cr (StoreLConditional mem (Binary oldval newval)));
8001 effect(KILL oldval);
8002 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
8003 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
8004 "XCHG EBX,ECX"
8005 %}
8006 ins_encode %{
8007 // Note: we need to swap rbx, and rcx before and after the
8008 // cmpxchg8 instruction because the instruction uses
8009 // rcx as the high order word of the new value to store but
8010 // our register encoding uses rbx.
8011 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8012 if( os::is_MP() )
8013 __ lock();
8014 __ cmpxchg8($mem$$Address);
8015 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8016 %}
8017 ins_pipe( pipe_cmpxchg );
8018 %}
8020 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
8022 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8023 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
8024 effect(KILL cr, KILL oldval);
8025 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8026 "MOV $res,0\n\t"
8027 "JNE,s fail\n\t"
8028 "MOV $res,1\n"
8029 "fail:" %}
8030 ins_encode( enc_cmpxchg8(mem_ptr),
8031 enc_flags_ne_to_boolean(res) );
8032 ins_pipe( pipe_cmpxchg );
8033 %}
8035 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
8036 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
8037 effect(KILL cr, KILL oldval);
8038 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8039 "MOV $res,0\n\t"
8040 "JNE,s fail\n\t"
8041 "MOV $res,1\n"
8042 "fail:" %}
8043 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8044 ins_pipe( pipe_cmpxchg );
8045 %}
8047 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
8048 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
8049 effect(KILL cr, KILL oldval);
8050 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8051 "MOV $res,0\n\t"
8052 "JNE,s fail\n\t"
8053 "MOV $res,1\n"
8054 "fail:" %}
8055 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8056 ins_pipe( pipe_cmpxchg );
8057 %}
8059 //----------Subtraction Instructions-------------------------------------------
8060 // Integer Subtraction Instructions
8061 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8062 match(Set dst (SubI dst src));
8063 effect(KILL cr);
8065 size(2);
8066 format %{ "SUB $dst,$src" %}
8067 opcode(0x2B);
8068 ins_encode( OpcP, RegReg( dst, src) );
8069 ins_pipe( ialu_reg_reg );
8070 %}
8072 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8073 match(Set dst (SubI dst src));
8074 effect(KILL cr);
8076 format %{ "SUB $dst,$src" %}
8077 opcode(0x81,0x05); /* Opcode 81 /5 */
8078 // ins_encode( RegImm( dst, src) );
8079 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8080 ins_pipe( ialu_reg );
8081 %}
8083 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8084 match(Set dst (SubI dst (LoadI src)));
8085 effect(KILL cr);
8087 ins_cost(125);
8088 format %{ "SUB $dst,$src" %}
8089 opcode(0x2B);
8090 ins_encode( OpcP, RegMem( dst, src) );
8091 ins_pipe( ialu_reg_mem );
8092 %}
8094 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8095 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8096 effect(KILL cr);
8098 ins_cost(150);
8099 format %{ "SUB $dst,$src" %}
8100 opcode(0x29); /* Opcode 29 /r */
8101 ins_encode( OpcP, RegMem( src, dst ) );
8102 ins_pipe( ialu_mem_reg );
8103 %}
8105 // Subtract from a pointer
8106 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
8107 match(Set dst (AddP dst (SubI zero src)));
8108 effect(KILL cr);
8110 size(2);
8111 format %{ "SUB $dst,$src" %}
8112 opcode(0x2B);
8113 ins_encode( OpcP, RegReg( dst, src) );
8114 ins_pipe( ialu_reg_reg );
8115 %}
8117 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
8118 match(Set dst (SubI zero dst));
8119 effect(KILL cr);
8121 size(2);
8122 format %{ "NEG $dst" %}
8123 opcode(0xF7,0x03); // Opcode F7 /3
8124 ins_encode( OpcP, RegOpc( dst ) );
8125 ins_pipe( ialu_reg );
8126 %}
8129 //----------Multiplication/Division Instructions-------------------------------
8130 // Integer Multiplication Instructions
8131 // Multiply Register
8132 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8133 match(Set dst (MulI dst src));
8134 effect(KILL cr);
8136 size(3);
8137 ins_cost(300);
8138 format %{ "IMUL $dst,$src" %}
8139 opcode(0xAF, 0x0F);
8140 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8141 ins_pipe( ialu_reg_reg_alu0 );
8142 %}
8144 // Multiply 32-bit Immediate
8145 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
8146 match(Set dst (MulI src imm));
8147 effect(KILL cr);
8149 ins_cost(300);
8150 format %{ "IMUL $dst,$src,$imm" %}
8151 opcode(0x69); /* 69 /r id */
8152 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8153 ins_pipe( ialu_reg_reg_alu0 );
8154 %}
8156 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8157 match(Set dst src);
8158 effect(KILL cr);
8160 // Note that this is artificially increased to make it more expensive than loadConL
8161 ins_cost(250);
8162 format %{ "MOV EAX,$src\t// low word only" %}
8163 opcode(0xB8);
8164 ins_encode( LdImmL_Lo(dst, src) );
8165 ins_pipe( ialu_reg_fat );
8166 %}
8168 // Multiply by 32-bit Immediate, taking the shifted high order results
8169 // (special case for shift by 32)
8170 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8171 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8172 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8173 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8174 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8175 effect(USE src1, KILL cr);
8177 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8178 ins_cost(0*100 + 1*400 - 150);
8179 format %{ "IMUL EDX:EAX,$src1" %}
8180 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8181 ins_pipe( pipe_slow );
8182 %}
8184 // Multiply by 32-bit Immediate, taking the shifted high order results
8185 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8186 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8187 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8188 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8189 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8190 effect(USE src1, KILL cr);
8192 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8193 ins_cost(1*100 + 1*400 - 150);
8194 format %{ "IMUL EDX:EAX,$src1\n\t"
8195 "SAR EDX,$cnt-32" %}
8196 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8197 ins_pipe( pipe_slow );
8198 %}
8200 // Multiply Memory 32-bit Immediate
8201 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8202 match(Set dst (MulI (LoadI src) imm));
8203 effect(KILL cr);
8205 ins_cost(300);
8206 format %{ "IMUL $dst,$src,$imm" %}
8207 opcode(0x69); /* 69 /r id */
8208 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8209 ins_pipe( ialu_reg_mem_alu0 );
8210 %}
8212 // Multiply Memory
8213 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8214 match(Set dst (MulI dst (LoadI src)));
8215 effect(KILL cr);
8217 ins_cost(350);
8218 format %{ "IMUL $dst,$src" %}
8219 opcode(0xAF, 0x0F);
8220 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8221 ins_pipe( ialu_reg_mem_alu0 );
8222 %}
8224 // Multiply Register Int to Long
8225 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8226 // Basic Idea: long = (long)int * (long)int
8227 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8228 effect(DEF dst, USE src, USE src1, KILL flags);
8230 ins_cost(300);
8231 format %{ "IMUL $dst,$src1" %}
8233 ins_encode( long_int_multiply( dst, src1 ) );
8234 ins_pipe( ialu_reg_reg_alu0 );
8235 %}
8237 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8238 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8239 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8240 effect(KILL flags);
8242 ins_cost(300);
8243 format %{ "MUL $dst,$src1" %}
8245 ins_encode( long_uint_multiply(dst, src1) );
8246 ins_pipe( ialu_reg_reg_alu0 );
8247 %}
8249 // Multiply Register Long
8250 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8251 match(Set dst (MulL dst src));
8252 effect(KILL cr, TEMP tmp);
8253 ins_cost(4*100+3*400);
8254 // Basic idea: lo(result) = lo(x_lo * y_lo)
8255 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8256 format %{ "MOV $tmp,$src.lo\n\t"
8257 "IMUL $tmp,EDX\n\t"
8258 "MOV EDX,$src.hi\n\t"
8259 "IMUL EDX,EAX\n\t"
8260 "ADD $tmp,EDX\n\t"
8261 "MUL EDX:EAX,$src.lo\n\t"
8262 "ADD EDX,$tmp" %}
8263 ins_encode( long_multiply( dst, src, tmp ) );
8264 ins_pipe( pipe_slow );
8265 %}
8267 // Multiply Register Long where the left operand's high 32 bits are zero
8268 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8269 predicate(is_operand_hi32_zero(n->in(1)));
8270 match(Set dst (MulL dst src));
8271 effect(KILL cr, TEMP tmp);
8272 ins_cost(2*100+2*400);
8273 // Basic idea: lo(result) = lo(x_lo * y_lo)
8274 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8275 format %{ "MOV $tmp,$src.hi\n\t"
8276 "IMUL $tmp,EAX\n\t"
8277 "MUL EDX:EAX,$src.lo\n\t"
8278 "ADD EDX,$tmp" %}
8279 ins_encode %{
8280 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8281 __ imull($tmp$$Register, rax);
8282 __ mull($src$$Register);
8283 __ addl(rdx, $tmp$$Register);
8284 %}
8285 ins_pipe( pipe_slow );
8286 %}
8288 // Multiply Register Long where the right operand's high 32 bits are zero
8289 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8290 predicate(is_operand_hi32_zero(n->in(2)));
8291 match(Set dst (MulL dst src));
8292 effect(KILL cr, TEMP tmp);
8293 ins_cost(2*100+2*400);
8294 // Basic idea: lo(result) = lo(x_lo * y_lo)
8295 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8296 format %{ "MOV $tmp,$src.lo\n\t"
8297 "IMUL $tmp,EDX\n\t"
8298 "MUL EDX:EAX,$src.lo\n\t"
8299 "ADD EDX,$tmp" %}
8300 ins_encode %{
8301 __ movl($tmp$$Register, $src$$Register);
8302 __ imull($tmp$$Register, rdx);
8303 __ mull($src$$Register);
8304 __ addl(rdx, $tmp$$Register);
8305 %}
8306 ins_pipe( pipe_slow );
8307 %}
8309 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8310 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8311 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8312 match(Set dst (MulL dst src));
8313 effect(KILL cr);
8314 ins_cost(1*400);
8315 // Basic idea: lo(result) = lo(x_lo * y_lo)
8316 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8317 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8318 ins_encode %{
8319 __ mull($src$$Register);
8320 %}
8321 ins_pipe( pipe_slow );
8322 %}
8324 // Multiply Register Long by small constant
8325 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8326 match(Set dst (MulL dst src));
8327 effect(KILL cr, TEMP tmp);
8328 ins_cost(2*100+2*400);
8329 size(12);
8330 // Basic idea: lo(result) = lo(src * EAX)
8331 // hi(result) = hi(src * EAX) + lo(src * EDX)
8332 format %{ "IMUL $tmp,EDX,$src\n\t"
8333 "MOV EDX,$src\n\t"
8334 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8335 "ADD EDX,$tmp" %}
8336 ins_encode( long_multiply_con( dst, src, tmp ) );
8337 ins_pipe( pipe_slow );
8338 %}
8340 // Integer DIV with Register
8341 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8342 match(Set rax (DivI rax div));
8343 effect(KILL rdx, KILL cr);
8344 size(26);
8345 ins_cost(30*100+10*100);
8346 format %{ "CMP EAX,0x80000000\n\t"
8347 "JNE,s normal\n\t"
8348 "XOR EDX,EDX\n\t"
8349 "CMP ECX,-1\n\t"
8350 "JE,s done\n"
8351 "normal: CDQ\n\t"
8352 "IDIV $div\n\t"
8353 "done:" %}
8354 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8355 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8356 ins_pipe( ialu_reg_reg_alu0 );
8357 %}
8359 // Divide Register Long
8360 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8361 match(Set dst (DivL src1 src2));
8362 effect( KILL cr, KILL cx, KILL bx );
8363 ins_cost(10000);
8364 format %{ "PUSH $src1.hi\n\t"
8365 "PUSH $src1.lo\n\t"
8366 "PUSH $src2.hi\n\t"
8367 "PUSH $src2.lo\n\t"
8368 "CALL SharedRuntime::ldiv\n\t"
8369 "ADD ESP,16" %}
8370 ins_encode( long_div(src1,src2) );
8371 ins_pipe( pipe_slow );
8372 %}
8374 // Integer DIVMOD with Register, both quotient and mod results
8375 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8376 match(DivModI rax div);
8377 effect(KILL cr);
8378 size(26);
8379 ins_cost(30*100+10*100);
8380 format %{ "CMP EAX,0x80000000\n\t"
8381 "JNE,s normal\n\t"
8382 "XOR EDX,EDX\n\t"
8383 "CMP ECX,-1\n\t"
8384 "JE,s done\n"
8385 "normal: CDQ\n\t"
8386 "IDIV $div\n\t"
8387 "done:" %}
8388 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8389 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8390 ins_pipe( pipe_slow );
8391 %}
8393 // Integer MOD with Register
8394 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8395 match(Set rdx (ModI rax div));
8396 effect(KILL rax, KILL cr);
8398 size(26);
8399 ins_cost(300);
8400 format %{ "CDQ\n\t"
8401 "IDIV $div" %}
8402 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8403 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8404 ins_pipe( ialu_reg_reg_alu0 );
8405 %}
8407 // Remainder Register Long
8408 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8409 match(Set dst (ModL src1 src2));
8410 effect( KILL cr, KILL cx, KILL bx );
8411 ins_cost(10000);
8412 format %{ "PUSH $src1.hi\n\t"
8413 "PUSH $src1.lo\n\t"
8414 "PUSH $src2.hi\n\t"
8415 "PUSH $src2.lo\n\t"
8416 "CALL SharedRuntime::lrem\n\t"
8417 "ADD ESP,16" %}
8418 ins_encode( long_mod(src1,src2) );
8419 ins_pipe( pipe_slow );
8420 %}
8422 // Divide Register Long (no special case since divisor != -1)
8423 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{
8424 match(Set dst (DivL dst imm));
8425 effect( TEMP tmp, TEMP tmp2, KILL cr );
8426 ins_cost(1000);
8427 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8428 "XOR $tmp2,$tmp2\n\t"
8429 "CMP $tmp,EDX\n\t"
8430 "JA,s fast\n\t"
8431 "MOV $tmp2,EAX\n\t"
8432 "MOV EAX,EDX\n\t"
8433 "MOV EDX,0\n\t"
8434 "JLE,s pos\n\t"
8435 "LNEG EAX : $tmp2\n\t"
8436 "DIV $tmp # unsigned division\n\t"
8437 "XCHG EAX,$tmp2\n\t"
8438 "DIV $tmp\n\t"
8439 "LNEG $tmp2 : EAX\n\t"
8440 "JMP,s done\n"
8441 "pos:\n\t"
8442 "DIV $tmp\n\t"
8443 "XCHG EAX,$tmp2\n"
8444 "fast:\n\t"
8445 "DIV $tmp\n"
8446 "done:\n\t"
8447 "MOV EDX,$tmp2\n\t"
8448 "NEG EDX:EAX # if $imm < 0" %}
8449 ins_encode %{
8450 int con = (int)$imm$$constant;
8451 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8452 int pcon = (con > 0) ? con : -con;
8453 Label Lfast, Lpos, Ldone;
8455 __ movl($tmp$$Register, pcon);
8456 __ xorl($tmp2$$Register,$tmp2$$Register);
8457 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8458 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8460 __ movl($tmp2$$Register, $dst$$Register); // save
8461 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8462 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8463 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8465 // Negative dividend.
8466 // convert value to positive to use unsigned division
8467 __ lneg($dst$$Register, $tmp2$$Register);
8468 __ divl($tmp$$Register);
8469 __ xchgl($dst$$Register, $tmp2$$Register);
8470 __ divl($tmp$$Register);
8471 // revert result back to negative
8472 __ lneg($tmp2$$Register, $dst$$Register);
8473 __ jmpb(Ldone);
8475 __ bind(Lpos);
8476 __ divl($tmp$$Register); // Use unsigned division
8477 __ xchgl($dst$$Register, $tmp2$$Register);
8478 // Fallthrow for final divide, tmp2 has 32 bit hi result
8480 __ bind(Lfast);
8481 // fast path: src is positive
8482 __ divl($tmp$$Register); // Use unsigned division
8484 __ bind(Ldone);
8485 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8486 if (con < 0) {
8487 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8488 }
8489 %}
8490 ins_pipe( pipe_slow );
8491 %}
8493 // Remainder Register Long (remainder fit into 32 bits)
8494 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{
8495 match(Set dst (ModL dst imm));
8496 effect( TEMP tmp, TEMP tmp2, KILL cr );
8497 ins_cost(1000);
8498 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8499 "CMP $tmp,EDX\n\t"
8500 "JA,s fast\n\t"
8501 "MOV $tmp2,EAX\n\t"
8502 "MOV EAX,EDX\n\t"
8503 "MOV EDX,0\n\t"
8504 "JLE,s pos\n\t"
8505 "LNEG EAX : $tmp2\n\t"
8506 "DIV $tmp # unsigned division\n\t"
8507 "MOV EAX,$tmp2\n\t"
8508 "DIV $tmp\n\t"
8509 "NEG EDX\n\t"
8510 "JMP,s done\n"
8511 "pos:\n\t"
8512 "DIV $tmp\n\t"
8513 "MOV EAX,$tmp2\n"
8514 "fast:\n\t"
8515 "DIV $tmp\n"
8516 "done:\n\t"
8517 "MOV EAX,EDX\n\t"
8518 "SAR EDX,31\n\t" %}
8519 ins_encode %{
8520 int con = (int)$imm$$constant;
8521 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8522 int pcon = (con > 0) ? con : -con;
8523 Label Lfast, Lpos, Ldone;
8525 __ movl($tmp$$Register, pcon);
8526 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8527 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8529 __ movl($tmp2$$Register, $dst$$Register); // save
8530 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8531 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8532 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8534 // Negative dividend.
8535 // convert value to positive to use unsigned division
8536 __ lneg($dst$$Register, $tmp2$$Register);
8537 __ divl($tmp$$Register);
8538 __ movl($dst$$Register, $tmp2$$Register);
8539 __ divl($tmp$$Register);
8540 // revert remainder back to negative
8541 __ negl(HIGH_FROM_LOW($dst$$Register));
8542 __ jmpb(Ldone);
8544 __ bind(Lpos);
8545 __ divl($tmp$$Register);
8546 __ movl($dst$$Register, $tmp2$$Register);
8548 __ bind(Lfast);
8549 // fast path: src is positive
8550 __ divl($tmp$$Register);
8552 __ bind(Ldone);
8553 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8554 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8556 %}
8557 ins_pipe( pipe_slow );
8558 %}
8560 // Integer Shift Instructions
8561 // Shift Left by one
8562 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8563 match(Set dst (LShiftI dst shift));
8564 effect(KILL cr);
8566 size(2);
8567 format %{ "SHL $dst,$shift" %}
8568 opcode(0xD1, 0x4); /* D1 /4 */
8569 ins_encode( OpcP, RegOpc( dst ) );
8570 ins_pipe( ialu_reg );
8571 %}
8573 // Shift Left by 8-bit immediate
8574 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8575 match(Set dst (LShiftI dst shift));
8576 effect(KILL cr);
8578 size(3);
8579 format %{ "SHL $dst,$shift" %}
8580 opcode(0xC1, 0x4); /* C1 /4 ib */
8581 ins_encode( RegOpcImm( dst, shift) );
8582 ins_pipe( ialu_reg );
8583 %}
8585 // Shift Left by variable
8586 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8587 match(Set dst (LShiftI dst shift));
8588 effect(KILL cr);
8590 size(2);
8591 format %{ "SHL $dst,$shift" %}
8592 opcode(0xD3, 0x4); /* D3 /4 */
8593 ins_encode( OpcP, RegOpc( dst ) );
8594 ins_pipe( ialu_reg_reg );
8595 %}
8597 // Arithmetic shift right by one
8598 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8599 match(Set dst (RShiftI dst shift));
8600 effect(KILL cr);
8602 size(2);
8603 format %{ "SAR $dst,$shift" %}
8604 opcode(0xD1, 0x7); /* D1 /7 */
8605 ins_encode( OpcP, RegOpc( dst ) );
8606 ins_pipe( ialu_reg );
8607 %}
8609 // Arithmetic shift right by one
8610 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8611 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8612 effect(KILL cr);
8613 format %{ "SAR $dst,$shift" %}
8614 opcode(0xD1, 0x7); /* D1 /7 */
8615 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8616 ins_pipe( ialu_mem_imm );
8617 %}
8619 // Arithmetic Shift Right by 8-bit immediate
8620 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8621 match(Set dst (RShiftI dst shift));
8622 effect(KILL cr);
8624 size(3);
8625 format %{ "SAR $dst,$shift" %}
8626 opcode(0xC1, 0x7); /* C1 /7 ib */
8627 ins_encode( RegOpcImm( dst, shift ) );
8628 ins_pipe( ialu_mem_imm );
8629 %}
8631 // Arithmetic Shift Right by 8-bit immediate
8632 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8633 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8634 effect(KILL cr);
8636 format %{ "SAR $dst,$shift" %}
8637 opcode(0xC1, 0x7); /* C1 /7 ib */
8638 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8639 ins_pipe( ialu_mem_imm );
8640 %}
8642 // Arithmetic Shift Right by variable
8643 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8644 match(Set dst (RShiftI dst shift));
8645 effect(KILL cr);
8647 size(2);
8648 format %{ "SAR $dst,$shift" %}
8649 opcode(0xD3, 0x7); /* D3 /7 */
8650 ins_encode( OpcP, RegOpc( dst ) );
8651 ins_pipe( ialu_reg_reg );
8652 %}
8654 // Logical shift right by one
8655 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8656 match(Set dst (URShiftI dst shift));
8657 effect(KILL cr);
8659 size(2);
8660 format %{ "SHR $dst,$shift" %}
8661 opcode(0xD1, 0x5); /* D1 /5 */
8662 ins_encode( OpcP, RegOpc( dst ) );
8663 ins_pipe( ialu_reg );
8664 %}
8666 // Logical Shift Right by 8-bit immediate
8667 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8668 match(Set dst (URShiftI dst shift));
8669 effect(KILL cr);
8671 size(3);
8672 format %{ "SHR $dst,$shift" %}
8673 opcode(0xC1, 0x5); /* C1 /5 ib */
8674 ins_encode( RegOpcImm( dst, shift) );
8675 ins_pipe( ialu_reg );
8676 %}
8679 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8680 // This idiom is used by the compiler for the i2b bytecode.
8681 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{
8682 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8684 size(3);
8685 format %{ "MOVSX $dst,$src :8" %}
8686 ins_encode %{
8687 __ movsbl($dst$$Register, $src$$Register);
8688 %}
8689 ins_pipe(ialu_reg_reg);
8690 %}
8692 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8693 // This idiom is used by the compiler the i2s bytecode.
8694 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{
8695 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8697 size(3);
8698 format %{ "MOVSX $dst,$src :16" %}
8699 ins_encode %{
8700 __ movswl($dst$$Register, $src$$Register);
8701 %}
8702 ins_pipe(ialu_reg_reg);
8703 %}
8706 // Logical Shift Right by variable
8707 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8708 match(Set dst (URShiftI dst shift));
8709 effect(KILL cr);
8711 size(2);
8712 format %{ "SHR $dst,$shift" %}
8713 opcode(0xD3, 0x5); /* D3 /5 */
8714 ins_encode( OpcP, RegOpc( dst ) );
8715 ins_pipe( ialu_reg_reg );
8716 %}
8719 //----------Logical Instructions-----------------------------------------------
8720 //----------Integer Logical Instructions---------------------------------------
8721 // And Instructions
8722 // And Register with Register
8723 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8724 match(Set dst (AndI dst src));
8725 effect(KILL cr);
8727 size(2);
8728 format %{ "AND $dst,$src" %}
8729 opcode(0x23);
8730 ins_encode( OpcP, RegReg( dst, src) );
8731 ins_pipe( ialu_reg_reg );
8732 %}
8734 // And Register with Immediate
8735 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8736 match(Set dst (AndI dst src));
8737 effect(KILL cr);
8739 format %{ "AND $dst,$src" %}
8740 opcode(0x81,0x04); /* Opcode 81 /4 */
8741 // ins_encode( RegImm( dst, src) );
8742 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8743 ins_pipe( ialu_reg );
8744 %}
8746 // And Register with Memory
8747 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8748 match(Set dst (AndI dst (LoadI src)));
8749 effect(KILL cr);
8751 ins_cost(125);
8752 format %{ "AND $dst,$src" %}
8753 opcode(0x23);
8754 ins_encode( OpcP, RegMem( dst, src) );
8755 ins_pipe( ialu_reg_mem );
8756 %}
8758 // And Memory with Register
8759 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8760 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8761 effect(KILL cr);
8763 ins_cost(150);
8764 format %{ "AND $dst,$src" %}
8765 opcode(0x21); /* Opcode 21 /r */
8766 ins_encode( OpcP, RegMem( src, dst ) );
8767 ins_pipe( ialu_mem_reg );
8768 %}
8770 // And Memory with Immediate
8771 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8772 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8773 effect(KILL cr);
8775 ins_cost(125);
8776 format %{ "AND $dst,$src" %}
8777 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8778 // ins_encode( MemImm( dst, src) );
8779 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8780 ins_pipe( ialu_mem_imm );
8781 %}
8783 // Or Instructions
8784 // Or Register with Register
8785 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8786 match(Set dst (OrI dst src));
8787 effect(KILL cr);
8789 size(2);
8790 format %{ "OR $dst,$src" %}
8791 opcode(0x0B);
8792 ins_encode( OpcP, RegReg( dst, src) );
8793 ins_pipe( ialu_reg_reg );
8794 %}
8796 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
8797 match(Set dst (OrI dst (CastP2X src)));
8798 effect(KILL cr);
8800 size(2);
8801 format %{ "OR $dst,$src" %}
8802 opcode(0x0B);
8803 ins_encode( OpcP, RegReg( dst, src) );
8804 ins_pipe( ialu_reg_reg );
8805 %}
8808 // Or Register with Immediate
8809 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8810 match(Set dst (OrI dst src));
8811 effect(KILL cr);
8813 format %{ "OR $dst,$src" %}
8814 opcode(0x81,0x01); /* Opcode 81 /1 id */
8815 // ins_encode( RegImm( dst, src) );
8816 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8817 ins_pipe( ialu_reg );
8818 %}
8820 // Or Register with Memory
8821 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8822 match(Set dst (OrI dst (LoadI src)));
8823 effect(KILL cr);
8825 ins_cost(125);
8826 format %{ "OR $dst,$src" %}
8827 opcode(0x0B);
8828 ins_encode( OpcP, RegMem( dst, src) );
8829 ins_pipe( ialu_reg_mem );
8830 %}
8832 // Or Memory with Register
8833 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8834 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8835 effect(KILL cr);
8837 ins_cost(150);
8838 format %{ "OR $dst,$src" %}
8839 opcode(0x09); /* Opcode 09 /r */
8840 ins_encode( OpcP, RegMem( src, dst ) );
8841 ins_pipe( ialu_mem_reg );
8842 %}
8844 // Or Memory with Immediate
8845 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8846 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8847 effect(KILL cr);
8849 ins_cost(125);
8850 format %{ "OR $dst,$src" %}
8851 opcode(0x81,0x1); /* Opcode 81 /1 id */
8852 // ins_encode( MemImm( dst, src) );
8853 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8854 ins_pipe( ialu_mem_imm );
8855 %}
8857 // ROL/ROR
8858 // ROL expand
8859 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8860 effect(USE_DEF dst, USE shift, KILL cr);
8862 format %{ "ROL $dst, $shift" %}
8863 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8864 ins_encode( OpcP, RegOpc( dst ));
8865 ins_pipe( ialu_reg );
8866 %}
8868 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8869 effect(USE_DEF dst, USE shift, KILL cr);
8871 format %{ "ROL $dst, $shift" %}
8872 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8873 ins_encode( RegOpcImm(dst, shift) );
8874 ins_pipe(ialu_reg);
8875 %}
8877 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8878 effect(USE_DEF dst, USE shift, KILL cr);
8880 format %{ "ROL $dst, $shift" %}
8881 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8882 ins_encode(OpcP, RegOpc(dst));
8883 ins_pipe( ialu_reg_reg );
8884 %}
8885 // end of ROL expand
8887 // ROL 32bit by one once
8888 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8889 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8891 expand %{
8892 rolI_eReg_imm1(dst, lshift, cr);
8893 %}
8894 %}
8896 // ROL 32bit var by imm8 once
8897 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8898 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8899 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8901 expand %{
8902 rolI_eReg_imm8(dst, lshift, cr);
8903 %}
8904 %}
8906 // ROL 32bit var by var once
8907 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8908 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8910 expand %{
8911 rolI_eReg_CL(dst, shift, cr);
8912 %}
8913 %}
8915 // ROL 32bit var by var once
8916 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8917 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8919 expand %{
8920 rolI_eReg_CL(dst, shift, cr);
8921 %}
8922 %}
8924 // ROR expand
8925 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8926 effect(USE_DEF dst, USE shift, KILL cr);
8928 format %{ "ROR $dst, $shift" %}
8929 opcode(0xD1,0x1); /* Opcode D1 /1 */
8930 ins_encode( OpcP, RegOpc( dst ) );
8931 ins_pipe( ialu_reg );
8932 %}
8934 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8935 effect (USE_DEF dst, USE shift, KILL cr);
8937 format %{ "ROR $dst, $shift" %}
8938 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8939 ins_encode( RegOpcImm(dst, shift) );
8940 ins_pipe( ialu_reg );
8941 %}
8943 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8944 effect(USE_DEF dst, USE shift, KILL cr);
8946 format %{ "ROR $dst, $shift" %}
8947 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8948 ins_encode(OpcP, RegOpc(dst));
8949 ins_pipe( ialu_reg_reg );
8950 %}
8951 // end of ROR expand
8953 // ROR right once
8954 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8955 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8957 expand %{
8958 rorI_eReg_imm1(dst, rshift, cr);
8959 %}
8960 %}
8962 // ROR 32bit by immI8 once
8963 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8964 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8965 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8967 expand %{
8968 rorI_eReg_imm8(dst, rshift, cr);
8969 %}
8970 %}
8972 // ROR 32bit var by var once
8973 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8974 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8976 expand %{
8977 rorI_eReg_CL(dst, shift, cr);
8978 %}
8979 %}
8981 // ROR 32bit var by var once
8982 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8983 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8985 expand %{
8986 rorI_eReg_CL(dst, shift, cr);
8987 %}
8988 %}
8990 // Xor Instructions
8991 // Xor Register with Register
8992 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8993 match(Set dst (XorI dst src));
8994 effect(KILL cr);
8996 size(2);
8997 format %{ "XOR $dst,$src" %}
8998 opcode(0x33);
8999 ins_encode( OpcP, RegReg( dst, src) );
9000 ins_pipe( ialu_reg_reg );
9001 %}
9003 // Xor Register with Immediate -1
9004 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
9005 match(Set dst (XorI dst imm));
9007 size(2);
9008 format %{ "NOT $dst" %}
9009 ins_encode %{
9010 __ notl($dst$$Register);
9011 %}
9012 ins_pipe( ialu_reg );
9013 %}
9015 // Xor Register with Immediate
9016 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9017 match(Set dst (XorI dst src));
9018 effect(KILL cr);
9020 format %{ "XOR $dst,$src" %}
9021 opcode(0x81,0x06); /* Opcode 81 /6 id */
9022 // ins_encode( RegImm( dst, src) );
9023 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9024 ins_pipe( ialu_reg );
9025 %}
9027 // Xor Register with Memory
9028 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9029 match(Set dst (XorI dst (LoadI src)));
9030 effect(KILL cr);
9032 ins_cost(125);
9033 format %{ "XOR $dst,$src" %}
9034 opcode(0x33);
9035 ins_encode( OpcP, RegMem(dst, src) );
9036 ins_pipe( ialu_reg_mem );
9037 %}
9039 // Xor Memory with Register
9040 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9041 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9042 effect(KILL cr);
9044 ins_cost(150);
9045 format %{ "XOR $dst,$src" %}
9046 opcode(0x31); /* Opcode 31 /r */
9047 ins_encode( OpcP, RegMem( src, dst ) );
9048 ins_pipe( ialu_mem_reg );
9049 %}
9051 // Xor Memory with Immediate
9052 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9053 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9054 effect(KILL cr);
9056 ins_cost(125);
9057 format %{ "XOR $dst,$src" %}
9058 opcode(0x81,0x6); /* Opcode 81 /6 id */
9059 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9060 ins_pipe( ialu_mem_imm );
9061 %}
9063 //----------Convert Int to Boolean---------------------------------------------
9065 instruct movI_nocopy(eRegI dst, eRegI src) %{
9066 effect( DEF dst, USE src );
9067 format %{ "MOV $dst,$src" %}
9068 ins_encode( enc_Copy( dst, src) );
9069 ins_pipe( ialu_reg_reg );
9070 %}
9072 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
9073 effect( USE_DEF dst, USE src, KILL cr );
9075 size(4);
9076 format %{ "NEG $dst\n\t"
9077 "ADC $dst,$src" %}
9078 ins_encode( neg_reg(dst),
9079 OpcRegReg(0x13,dst,src) );
9080 ins_pipe( ialu_reg_reg_long );
9081 %}
9083 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
9084 match(Set dst (Conv2B src));
9086 expand %{
9087 movI_nocopy(dst,src);
9088 ci2b(dst,src,cr);
9089 %}
9090 %}
9092 instruct movP_nocopy(eRegI dst, eRegP src) %{
9093 effect( DEF dst, USE src );
9094 format %{ "MOV $dst,$src" %}
9095 ins_encode( enc_Copy( dst, src) );
9096 ins_pipe( ialu_reg_reg );
9097 %}
9099 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
9100 effect( USE_DEF dst, USE src, KILL cr );
9101 format %{ "NEG $dst\n\t"
9102 "ADC $dst,$src" %}
9103 ins_encode( neg_reg(dst),
9104 OpcRegReg(0x13,dst,src) );
9105 ins_pipe( ialu_reg_reg_long );
9106 %}
9108 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
9109 match(Set dst (Conv2B src));
9111 expand %{
9112 movP_nocopy(dst,src);
9113 cp2b(dst,src,cr);
9114 %}
9115 %}
9117 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
9118 match(Set dst (CmpLTMask p q));
9119 effect( KILL cr );
9120 ins_cost(400);
9122 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9123 format %{ "XOR $dst,$dst\n\t"
9124 "CMP $p,$q\n\t"
9125 "SETlt $dst\n\t"
9126 "NEG $dst" %}
9127 ins_encode( OpcRegReg(0x33,dst,dst),
9128 OpcRegReg(0x3B,p,q),
9129 setLT_reg(dst), neg_reg(dst) );
9130 ins_pipe( pipe_slow );
9131 %}
9133 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
9134 match(Set dst (CmpLTMask dst zero));
9135 effect( DEF dst, KILL cr );
9136 ins_cost(100);
9138 format %{ "SAR $dst,31" %}
9139 opcode(0xC1, 0x7); /* C1 /7 ib */
9140 ins_encode( RegOpcImm( dst, 0x1F ) );
9141 ins_pipe( ialu_reg );
9142 %}
9145 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
9146 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9147 effect( KILL tmp, KILL cr );
9148 ins_cost(400);
9149 // annoyingly, $tmp has no edges so you cant ask for it in
9150 // any format or encoding
9151 format %{ "SUB $p,$q\n\t"
9152 "SBB ECX,ECX\n\t"
9153 "AND ECX,$y\n\t"
9154 "ADD $p,ECX" %}
9155 ins_encode( enc_cmpLTP(p,q,y,tmp) );
9156 ins_pipe( pipe_cmplt );
9157 %}
9159 /* If I enable this, I encourage spilling in the inner loop of compress.
9160 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
9161 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9162 effect( USE_KILL tmp, KILL cr );
9163 ins_cost(400);
9165 format %{ "SUB $p,$q\n\t"
9166 "SBB ECX,ECX\n\t"
9167 "AND ECX,$y\n\t"
9168 "ADD $p,ECX" %}
9169 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
9170 %}
9171 */
9173 //----------Long Instructions------------------------------------------------
9174 // Add Long Register with Register
9175 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9176 match(Set dst (AddL dst src));
9177 effect(KILL cr);
9178 ins_cost(200);
9179 format %{ "ADD $dst.lo,$src.lo\n\t"
9180 "ADC $dst.hi,$src.hi" %}
9181 opcode(0x03, 0x13);
9182 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9183 ins_pipe( ialu_reg_reg_long );
9184 %}
9186 // Add Long Register with Immediate
9187 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9188 match(Set dst (AddL dst src));
9189 effect(KILL cr);
9190 format %{ "ADD $dst.lo,$src.lo\n\t"
9191 "ADC $dst.hi,$src.hi" %}
9192 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9193 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9194 ins_pipe( ialu_reg_long );
9195 %}
9197 // Add Long Register with Memory
9198 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9199 match(Set dst (AddL dst (LoadL mem)));
9200 effect(KILL cr);
9201 ins_cost(125);
9202 format %{ "ADD $dst.lo,$mem\n\t"
9203 "ADC $dst.hi,$mem+4" %}
9204 opcode(0x03, 0x13);
9205 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9206 ins_pipe( ialu_reg_long_mem );
9207 %}
9209 // Subtract Long Register with Register.
9210 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9211 match(Set dst (SubL dst src));
9212 effect(KILL cr);
9213 ins_cost(200);
9214 format %{ "SUB $dst.lo,$src.lo\n\t"
9215 "SBB $dst.hi,$src.hi" %}
9216 opcode(0x2B, 0x1B);
9217 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9218 ins_pipe( ialu_reg_reg_long );
9219 %}
9221 // Subtract Long Register with Immediate
9222 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9223 match(Set dst (SubL dst src));
9224 effect(KILL cr);
9225 format %{ "SUB $dst.lo,$src.lo\n\t"
9226 "SBB $dst.hi,$src.hi" %}
9227 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9228 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9229 ins_pipe( ialu_reg_long );
9230 %}
9232 // Subtract Long Register with Memory
9233 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9234 match(Set dst (SubL dst (LoadL mem)));
9235 effect(KILL cr);
9236 ins_cost(125);
9237 format %{ "SUB $dst.lo,$mem\n\t"
9238 "SBB $dst.hi,$mem+4" %}
9239 opcode(0x2B, 0x1B);
9240 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9241 ins_pipe( ialu_reg_long_mem );
9242 %}
9244 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9245 match(Set dst (SubL zero dst));
9246 effect(KILL cr);
9247 ins_cost(300);
9248 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9249 ins_encode( neg_long(dst) );
9250 ins_pipe( ialu_reg_reg_long );
9251 %}
9253 // And Long Register with Register
9254 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9255 match(Set dst (AndL dst src));
9256 effect(KILL cr);
9257 format %{ "AND $dst.lo,$src.lo\n\t"
9258 "AND $dst.hi,$src.hi" %}
9259 opcode(0x23,0x23);
9260 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9261 ins_pipe( ialu_reg_reg_long );
9262 %}
9264 // And Long Register with Immediate
9265 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9266 match(Set dst (AndL dst src));
9267 effect(KILL cr);
9268 format %{ "AND $dst.lo,$src.lo\n\t"
9269 "AND $dst.hi,$src.hi" %}
9270 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9271 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9272 ins_pipe( ialu_reg_long );
9273 %}
9275 // And Long Register with Memory
9276 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9277 match(Set dst (AndL dst (LoadL mem)));
9278 effect(KILL cr);
9279 ins_cost(125);
9280 format %{ "AND $dst.lo,$mem\n\t"
9281 "AND $dst.hi,$mem+4" %}
9282 opcode(0x23, 0x23);
9283 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9284 ins_pipe( ialu_reg_long_mem );
9285 %}
9287 // Or Long Register with Register
9288 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9289 match(Set dst (OrL dst src));
9290 effect(KILL cr);
9291 format %{ "OR $dst.lo,$src.lo\n\t"
9292 "OR $dst.hi,$src.hi" %}
9293 opcode(0x0B,0x0B);
9294 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9295 ins_pipe( ialu_reg_reg_long );
9296 %}
9298 // Or Long Register with Immediate
9299 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9300 match(Set dst (OrL dst src));
9301 effect(KILL cr);
9302 format %{ "OR $dst.lo,$src.lo\n\t"
9303 "OR $dst.hi,$src.hi" %}
9304 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9305 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9306 ins_pipe( ialu_reg_long );
9307 %}
9309 // Or Long Register with Memory
9310 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9311 match(Set dst (OrL dst (LoadL mem)));
9312 effect(KILL cr);
9313 ins_cost(125);
9314 format %{ "OR $dst.lo,$mem\n\t"
9315 "OR $dst.hi,$mem+4" %}
9316 opcode(0x0B,0x0B);
9317 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9318 ins_pipe( ialu_reg_long_mem );
9319 %}
9321 // Xor Long Register with Register
9322 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9323 match(Set dst (XorL dst src));
9324 effect(KILL cr);
9325 format %{ "XOR $dst.lo,$src.lo\n\t"
9326 "XOR $dst.hi,$src.hi" %}
9327 opcode(0x33,0x33);
9328 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9329 ins_pipe( ialu_reg_reg_long );
9330 %}
9332 // Xor Long Register with Immediate -1
9333 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9334 match(Set dst (XorL dst imm));
9335 format %{ "NOT $dst.lo\n\t"
9336 "NOT $dst.hi" %}
9337 ins_encode %{
9338 __ notl($dst$$Register);
9339 __ notl(HIGH_FROM_LOW($dst$$Register));
9340 %}
9341 ins_pipe( ialu_reg_long );
9342 %}
9344 // Xor Long Register with Immediate
9345 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9346 match(Set dst (XorL dst src));
9347 effect(KILL cr);
9348 format %{ "XOR $dst.lo,$src.lo\n\t"
9349 "XOR $dst.hi,$src.hi" %}
9350 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9351 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9352 ins_pipe( ialu_reg_long );
9353 %}
9355 // Xor Long Register with Memory
9356 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9357 match(Set dst (XorL dst (LoadL mem)));
9358 effect(KILL cr);
9359 ins_cost(125);
9360 format %{ "XOR $dst.lo,$mem\n\t"
9361 "XOR $dst.hi,$mem+4" %}
9362 opcode(0x33,0x33);
9363 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9364 ins_pipe( ialu_reg_long_mem );
9365 %}
9367 // Shift Left Long by 1
9368 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9369 predicate(UseNewLongLShift);
9370 match(Set dst (LShiftL dst cnt));
9371 effect(KILL cr);
9372 ins_cost(100);
9373 format %{ "ADD $dst.lo,$dst.lo\n\t"
9374 "ADC $dst.hi,$dst.hi" %}
9375 ins_encode %{
9376 __ addl($dst$$Register,$dst$$Register);
9377 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9378 %}
9379 ins_pipe( ialu_reg_long );
9380 %}
9382 // Shift Left Long by 2
9383 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9384 predicate(UseNewLongLShift);
9385 match(Set dst (LShiftL dst cnt));
9386 effect(KILL cr);
9387 ins_cost(100);
9388 format %{ "ADD $dst.lo,$dst.lo\n\t"
9389 "ADC $dst.hi,$dst.hi\n\t"
9390 "ADD $dst.lo,$dst.lo\n\t"
9391 "ADC $dst.hi,$dst.hi" %}
9392 ins_encode %{
9393 __ addl($dst$$Register,$dst$$Register);
9394 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9395 __ addl($dst$$Register,$dst$$Register);
9396 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9397 %}
9398 ins_pipe( ialu_reg_long );
9399 %}
9401 // Shift Left Long by 3
9402 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9403 predicate(UseNewLongLShift);
9404 match(Set dst (LShiftL dst cnt));
9405 effect(KILL cr);
9406 ins_cost(100);
9407 format %{ "ADD $dst.lo,$dst.lo\n\t"
9408 "ADC $dst.hi,$dst.hi\n\t"
9409 "ADD $dst.lo,$dst.lo\n\t"
9410 "ADC $dst.hi,$dst.hi\n\t"
9411 "ADD $dst.lo,$dst.lo\n\t"
9412 "ADC $dst.hi,$dst.hi" %}
9413 ins_encode %{
9414 __ addl($dst$$Register,$dst$$Register);
9415 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9416 __ addl($dst$$Register,$dst$$Register);
9417 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9418 __ addl($dst$$Register,$dst$$Register);
9419 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9420 %}
9421 ins_pipe( ialu_reg_long );
9422 %}
9424 // Shift Left Long by 1-31
9425 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9426 match(Set dst (LShiftL dst cnt));
9427 effect(KILL cr);
9428 ins_cost(200);
9429 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9430 "SHL $dst.lo,$cnt" %}
9431 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9432 ins_encode( move_long_small_shift(dst,cnt) );
9433 ins_pipe( ialu_reg_long );
9434 %}
9436 // Shift Left Long by 32-63
9437 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9438 match(Set dst (LShiftL dst cnt));
9439 effect(KILL cr);
9440 ins_cost(300);
9441 format %{ "MOV $dst.hi,$dst.lo\n"
9442 "\tSHL $dst.hi,$cnt-32\n"
9443 "\tXOR $dst.lo,$dst.lo" %}
9444 opcode(0xC1, 0x4); /* C1 /4 ib */
9445 ins_encode( move_long_big_shift_clr(dst,cnt) );
9446 ins_pipe( ialu_reg_long );
9447 %}
9449 // Shift Left Long by variable
9450 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9451 match(Set dst (LShiftL dst shift));
9452 effect(KILL cr);
9453 ins_cost(500+200);
9454 size(17);
9455 format %{ "TEST $shift,32\n\t"
9456 "JEQ,s small\n\t"
9457 "MOV $dst.hi,$dst.lo\n\t"
9458 "XOR $dst.lo,$dst.lo\n"
9459 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9460 "SHL $dst.lo,$shift" %}
9461 ins_encode( shift_left_long( dst, shift ) );
9462 ins_pipe( pipe_slow );
9463 %}
9465 // Shift Right Long by 1-31
9466 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9467 match(Set dst (URShiftL dst cnt));
9468 effect(KILL cr);
9469 ins_cost(200);
9470 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9471 "SHR $dst.hi,$cnt" %}
9472 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9473 ins_encode( move_long_small_shift(dst,cnt) );
9474 ins_pipe( ialu_reg_long );
9475 %}
9477 // Shift Right Long by 32-63
9478 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9479 match(Set dst (URShiftL dst cnt));
9480 effect(KILL cr);
9481 ins_cost(300);
9482 format %{ "MOV $dst.lo,$dst.hi\n"
9483 "\tSHR $dst.lo,$cnt-32\n"
9484 "\tXOR $dst.hi,$dst.hi" %}
9485 opcode(0xC1, 0x5); /* C1 /5 ib */
9486 ins_encode( move_long_big_shift_clr(dst,cnt) );
9487 ins_pipe( ialu_reg_long );
9488 %}
9490 // Shift Right Long by variable
9491 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9492 match(Set dst (URShiftL dst shift));
9493 effect(KILL cr);
9494 ins_cost(600);
9495 size(17);
9496 format %{ "TEST $shift,32\n\t"
9497 "JEQ,s small\n\t"
9498 "MOV $dst.lo,$dst.hi\n\t"
9499 "XOR $dst.hi,$dst.hi\n"
9500 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9501 "SHR $dst.hi,$shift" %}
9502 ins_encode( shift_right_long( dst, shift ) );
9503 ins_pipe( pipe_slow );
9504 %}
9506 // Shift Right Long by 1-31
9507 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9508 match(Set dst (RShiftL dst cnt));
9509 effect(KILL cr);
9510 ins_cost(200);
9511 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9512 "SAR $dst.hi,$cnt" %}
9513 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9514 ins_encode( move_long_small_shift(dst,cnt) );
9515 ins_pipe( ialu_reg_long );
9516 %}
9518 // Shift Right Long by 32-63
9519 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9520 match(Set dst (RShiftL dst cnt));
9521 effect(KILL cr);
9522 ins_cost(300);
9523 format %{ "MOV $dst.lo,$dst.hi\n"
9524 "\tSAR $dst.lo,$cnt-32\n"
9525 "\tSAR $dst.hi,31" %}
9526 opcode(0xC1, 0x7); /* C1 /7 ib */
9527 ins_encode( move_long_big_shift_sign(dst,cnt) );
9528 ins_pipe( ialu_reg_long );
9529 %}
9531 // Shift Right arithmetic Long by variable
9532 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9533 match(Set dst (RShiftL dst shift));
9534 effect(KILL cr);
9535 ins_cost(600);
9536 size(18);
9537 format %{ "TEST $shift,32\n\t"
9538 "JEQ,s small\n\t"
9539 "MOV $dst.lo,$dst.hi\n\t"
9540 "SAR $dst.hi,31\n"
9541 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9542 "SAR $dst.hi,$shift" %}
9543 ins_encode( shift_right_arith_long( dst, shift ) );
9544 ins_pipe( pipe_slow );
9545 %}
9548 //----------Double Instructions------------------------------------------------
9549 // Double Math
9551 // Compare & branch
9553 // P6 version of float compare, sets condition codes in EFLAGS
9554 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9555 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9556 match(Set cr (CmpD src1 src2));
9557 effect(KILL rax);
9558 ins_cost(150);
9559 format %{ "FLD $src1\n\t"
9560 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9561 "JNP exit\n\t"
9562 "MOV ah,1 // saw a NaN, set CF\n\t"
9563 "SAHF\n"
9564 "exit:\tNOP // avoid branch to branch" %}
9565 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9566 ins_encode( Push_Reg_D(src1),
9567 OpcP, RegOpc(src2),
9568 cmpF_P6_fixup );
9569 ins_pipe( pipe_slow );
9570 %}
9572 instruct cmpD_cc_P6CF(eFlagsRegUCF cr, regD src1, regD src2) %{
9573 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9574 match(Set cr (CmpD src1 src2));
9575 ins_cost(150);
9576 format %{ "FLD $src1\n\t"
9577 "FUCOMIP ST,$src2 // P6 instruction" %}
9578 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9579 ins_encode( Push_Reg_D(src1),
9580 OpcP, RegOpc(src2));
9581 ins_pipe( pipe_slow );
9582 %}
9584 // Compare & branch
9585 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9586 predicate(UseSSE<=1);
9587 match(Set cr (CmpD src1 src2));
9588 effect(KILL rax);
9589 ins_cost(200);
9590 format %{ "FLD $src1\n\t"
9591 "FCOMp $src2\n\t"
9592 "FNSTSW AX\n\t"
9593 "TEST AX,0x400\n\t"
9594 "JZ,s flags\n\t"
9595 "MOV AH,1\t# unordered treat as LT\n"
9596 "flags:\tSAHF" %}
9597 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9598 ins_encode( Push_Reg_D(src1),
9599 OpcP, RegOpc(src2),
9600 fpu_flags);
9601 ins_pipe( pipe_slow );
9602 %}
9604 // Compare vs zero into -1,0,1
9605 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{
9606 predicate(UseSSE<=1);
9607 match(Set dst (CmpD3 src1 zero));
9608 effect(KILL cr, KILL rax);
9609 ins_cost(280);
9610 format %{ "FTSTD $dst,$src1" %}
9611 opcode(0xE4, 0xD9);
9612 ins_encode( Push_Reg_D(src1),
9613 OpcS, OpcP, PopFPU,
9614 CmpF_Result(dst));
9615 ins_pipe( pipe_slow );
9616 %}
9618 // Compare into -1,0,1
9619 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{
9620 predicate(UseSSE<=1);
9621 match(Set dst (CmpD3 src1 src2));
9622 effect(KILL cr, KILL rax);
9623 ins_cost(300);
9624 format %{ "FCMPD $dst,$src1,$src2" %}
9625 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9626 ins_encode( Push_Reg_D(src1),
9627 OpcP, RegOpc(src2),
9628 CmpF_Result(dst));
9629 ins_pipe( pipe_slow );
9630 %}
9632 // float compare and set condition codes in EFLAGS by XMM regs
9633 instruct cmpXD_cc(eFlagsRegU cr, regXD src1, regXD src2) %{
9634 predicate(UseSSE>=2);
9635 match(Set cr (CmpD src1 src2));
9636 ins_cost(145);
9637 format %{ "UCOMISD $src1,$src2\n\t"
9638 "JNP,s exit\n\t"
9639 "PUSHF\t# saw NaN, set CF\n\t"
9640 "AND [rsp], #0xffffff2b\n\t"
9641 "POPF\n"
9642 "exit:" %}
9643 ins_encode %{
9644 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9645 emit_cmpfp_fixup(_masm);
9646 %}
9647 ins_pipe( pipe_slow );
9648 %}
9650 instruct cmpXD_ccCF(eFlagsRegUCF cr, regXD src1, regXD src2) %{
9651 predicate(UseSSE>=2);
9652 match(Set cr (CmpD src1 src2));
9653 ins_cost(100);
9654 format %{ "UCOMISD $src1,$src2" %}
9655 ins_encode %{
9656 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9657 %}
9658 ins_pipe( pipe_slow );
9659 %}
9661 // float compare and set condition codes in EFLAGS by XMM regs
9662 instruct cmpXD_ccmem(eFlagsRegU cr, regXD src1, memory src2) %{
9663 predicate(UseSSE>=2);
9664 match(Set cr (CmpD src1 (LoadD src2)));
9665 ins_cost(145);
9666 format %{ "UCOMISD $src1,$src2\n\t"
9667 "JNP,s exit\n\t"
9668 "PUSHF\t# saw NaN, set CF\n\t"
9669 "AND [rsp], #0xffffff2b\n\t"
9670 "POPF\n"
9671 "exit:" %}
9672 ins_encode %{
9673 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9674 emit_cmpfp_fixup(_masm);
9675 %}
9676 ins_pipe( pipe_slow );
9677 %}
9679 instruct cmpXD_ccmemCF(eFlagsRegUCF cr, regXD src1, memory src2) %{
9680 predicate(UseSSE>=2);
9681 match(Set cr (CmpD src1 (LoadD src2)));
9682 ins_cost(100);
9683 format %{ "UCOMISD $src1,$src2" %}
9684 ins_encode %{
9685 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9686 %}
9687 ins_pipe( pipe_slow );
9688 %}
9690 // Compare into -1,0,1 in XMM
9691 instruct cmpXD_reg(xRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{
9692 predicate(UseSSE>=2);
9693 match(Set dst (CmpD3 src1 src2));
9694 effect(KILL cr);
9695 ins_cost(255);
9696 format %{ "UCOMISD $src1, $src2\n\t"
9697 "MOV $dst, #-1\n\t"
9698 "JP,s done\n\t"
9699 "JB,s done\n\t"
9700 "SETNE $dst\n\t"
9701 "MOVZB $dst, $dst\n"
9702 "done:" %}
9703 ins_encode %{
9704 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9705 emit_cmpfp3(_masm, $dst$$Register);
9706 %}
9707 ins_pipe( pipe_slow );
9708 %}
9710 // Compare into -1,0,1 in XMM and memory
9711 instruct cmpXD_regmem(xRegI dst, regXD src1, memory src2, eFlagsReg cr) %{
9712 predicate(UseSSE>=2);
9713 match(Set dst (CmpD3 src1 (LoadD src2)));
9714 effect(KILL cr);
9715 ins_cost(275);
9716 format %{ "UCOMISD $src1, $src2\n\t"
9717 "MOV $dst, #-1\n\t"
9718 "JP,s done\n\t"
9719 "JB,s done\n\t"
9720 "SETNE $dst\n\t"
9721 "MOVZB $dst, $dst\n"
9722 "done:" %}
9723 ins_encode %{
9724 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9725 emit_cmpfp3(_masm, $dst$$Register);
9726 %}
9727 ins_pipe( pipe_slow );
9728 %}
9731 instruct subD_reg(regD dst, regD src) %{
9732 predicate (UseSSE <=1);
9733 match(Set dst (SubD dst src));
9735 format %{ "FLD $src\n\t"
9736 "DSUBp $dst,ST" %}
9737 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9738 ins_cost(150);
9739 ins_encode( Push_Reg_D(src),
9740 OpcP, RegOpc(dst) );
9741 ins_pipe( fpu_reg_reg );
9742 %}
9744 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9745 predicate (UseSSE <=1);
9746 match(Set dst (RoundDouble (SubD src1 src2)));
9747 ins_cost(250);
9749 format %{ "FLD $src2\n\t"
9750 "DSUB ST,$src1\n\t"
9751 "FSTP_D $dst\t# D-round" %}
9752 opcode(0xD8, 0x5);
9753 ins_encode( Push_Reg_D(src2),
9754 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9755 ins_pipe( fpu_mem_reg_reg );
9756 %}
9759 instruct subD_reg_mem(regD dst, memory src) %{
9760 predicate (UseSSE <=1);
9761 match(Set dst (SubD dst (LoadD src)));
9762 ins_cost(150);
9764 format %{ "FLD $src\n\t"
9765 "DSUBp $dst,ST" %}
9766 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9767 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9768 OpcP, RegOpc(dst) );
9769 ins_pipe( fpu_reg_mem );
9770 %}
9772 instruct absD_reg(regDPR1 dst, regDPR1 src) %{
9773 predicate (UseSSE<=1);
9774 match(Set dst (AbsD src));
9775 ins_cost(100);
9776 format %{ "FABS" %}
9777 opcode(0xE1, 0xD9);
9778 ins_encode( OpcS, OpcP );
9779 ins_pipe( fpu_reg_reg );
9780 %}
9782 instruct absXD_reg( regXD dst ) %{
9783 predicate(UseSSE>=2);
9784 match(Set dst (AbsD dst));
9785 ins_cost(150);
9786 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %}
9787 ins_encode %{
9788 __ andpd($dst$$XMMRegister,
9789 ExternalAddress((address)double_signmask_pool));
9790 %}
9791 ins_pipe( pipe_slow );
9792 %}
9794 instruct negD_reg(regDPR1 dst, regDPR1 src) %{
9795 predicate(UseSSE<=1);
9796 match(Set dst (NegD src));
9797 ins_cost(100);
9798 format %{ "FCHS" %}
9799 opcode(0xE0, 0xD9);
9800 ins_encode( OpcS, OpcP );
9801 ins_pipe( fpu_reg_reg );
9802 %}
9804 instruct negXD_reg( regXD dst ) %{
9805 predicate(UseSSE>=2);
9806 match(Set dst (NegD dst));
9807 ins_cost(150);
9808 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %}
9809 ins_encode %{
9810 __ xorpd($dst$$XMMRegister,
9811 ExternalAddress((address)double_signflip_pool));
9812 %}
9813 ins_pipe( pipe_slow );
9814 %}
9816 instruct addD_reg(regD dst, regD src) %{
9817 predicate(UseSSE<=1);
9818 match(Set dst (AddD dst src));
9819 format %{ "FLD $src\n\t"
9820 "DADD $dst,ST" %}
9821 size(4);
9822 ins_cost(150);
9823 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9824 ins_encode( Push_Reg_D(src),
9825 OpcP, RegOpc(dst) );
9826 ins_pipe( fpu_reg_reg );
9827 %}
9830 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9831 predicate(UseSSE<=1);
9832 match(Set dst (RoundDouble (AddD src1 src2)));
9833 ins_cost(250);
9835 format %{ "FLD $src2\n\t"
9836 "DADD ST,$src1\n\t"
9837 "FSTP_D $dst\t# D-round" %}
9838 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9839 ins_encode( Push_Reg_D(src2),
9840 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9841 ins_pipe( fpu_mem_reg_reg );
9842 %}
9845 instruct addD_reg_mem(regD dst, memory src) %{
9846 predicate(UseSSE<=1);
9847 match(Set dst (AddD dst (LoadD src)));
9848 ins_cost(150);
9850 format %{ "FLD $src\n\t"
9851 "DADDp $dst,ST" %}
9852 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9853 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9854 OpcP, RegOpc(dst) );
9855 ins_pipe( fpu_reg_mem );
9856 %}
9858 // add-to-memory
9859 instruct addD_mem_reg(memory dst, regD src) %{
9860 predicate(UseSSE<=1);
9861 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9862 ins_cost(150);
9864 format %{ "FLD_D $dst\n\t"
9865 "DADD ST,$src\n\t"
9866 "FST_D $dst" %}
9867 opcode(0xDD, 0x0);
9868 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9869 Opcode(0xD8), RegOpc(src),
9870 set_instruction_start,
9871 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9872 ins_pipe( fpu_reg_mem );
9873 %}
9875 instruct addD_reg_imm1(regD dst, immD1 con) %{
9876 predicate(UseSSE<=1);
9877 match(Set dst (AddD dst con));
9878 ins_cost(125);
9879 format %{ "FLD1\n\t"
9880 "DADDp $dst,ST" %}
9881 ins_encode %{
9882 __ fld1();
9883 __ faddp($dst$$reg);
9884 %}
9885 ins_pipe(fpu_reg);
9886 %}
9888 instruct addD_reg_imm(regD dst, immD con) %{
9889 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9890 match(Set dst (AddD dst con));
9891 ins_cost(200);
9892 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9893 "DADDp $dst,ST" %}
9894 ins_encode %{
9895 __ fld_d($constantaddress($con));
9896 __ faddp($dst$$reg);
9897 %}
9898 ins_pipe(fpu_reg_mem);
9899 %}
9901 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{
9902 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9903 match(Set dst (RoundDouble (AddD src con)));
9904 ins_cost(200);
9905 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9906 "DADD ST,$src\n\t"
9907 "FSTP_D $dst\t# D-round" %}
9908 ins_encode %{
9909 __ fld_d($constantaddress($con));
9910 __ fadd($src$$reg);
9911 __ fstp_d(Address(rsp, $dst$$disp));
9912 %}
9913 ins_pipe(fpu_mem_reg_con);
9914 %}
9916 // Add two double precision floating point values in xmm
9917 instruct addXD_reg(regXD dst, regXD src) %{
9918 predicate(UseSSE>=2);
9919 match(Set dst (AddD dst src));
9920 format %{ "ADDSD $dst,$src" %}
9921 ins_encode %{
9922 __ addsd($dst$$XMMRegister, $src$$XMMRegister);
9923 %}
9924 ins_pipe( pipe_slow );
9925 %}
9927 instruct addXD_imm(regXD dst, immXD con) %{
9928 predicate(UseSSE>=2);
9929 match(Set dst (AddD dst con));
9930 format %{ "ADDSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
9931 ins_encode %{
9932 __ addsd($dst$$XMMRegister, $constantaddress($con));
9933 %}
9934 ins_pipe(pipe_slow);
9935 %}
9937 instruct addXD_mem(regXD dst, memory mem) %{
9938 predicate(UseSSE>=2);
9939 match(Set dst (AddD dst (LoadD mem)));
9940 format %{ "ADDSD $dst,$mem" %}
9941 ins_encode %{
9942 __ addsd($dst$$XMMRegister, $mem$$Address);
9943 %}
9944 ins_pipe( pipe_slow );
9945 %}
9947 // Sub two double precision floating point values in xmm
9948 instruct subXD_reg(regXD dst, regXD src) %{
9949 predicate(UseSSE>=2);
9950 match(Set dst (SubD dst src));
9951 ins_cost(150);
9952 format %{ "SUBSD $dst,$src" %}
9953 ins_encode %{
9954 __ subsd($dst$$XMMRegister, $src$$XMMRegister);
9955 %}
9956 ins_pipe( pipe_slow );
9957 %}
9959 instruct subXD_imm(regXD dst, immXD con) %{
9960 predicate(UseSSE>=2);
9961 match(Set dst (SubD dst con));
9962 ins_cost(150);
9963 format %{ "SUBSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
9964 ins_encode %{
9965 __ subsd($dst$$XMMRegister, $constantaddress($con));
9966 %}
9967 ins_pipe(pipe_slow);
9968 %}
9970 instruct subXD_mem(regXD dst, memory mem) %{
9971 predicate(UseSSE>=2);
9972 match(Set dst (SubD dst (LoadD mem)));
9973 ins_cost(150);
9974 format %{ "SUBSD $dst,$mem" %}
9975 ins_encode %{
9976 __ subsd($dst$$XMMRegister, $mem$$Address);
9977 %}
9978 ins_pipe( pipe_slow );
9979 %}
9981 // Mul two double precision floating point values in xmm
9982 instruct mulXD_reg(regXD dst, regXD src) %{
9983 predicate(UseSSE>=2);
9984 match(Set dst (MulD dst src));
9985 format %{ "MULSD $dst,$src" %}
9986 ins_encode %{
9987 __ mulsd($dst$$XMMRegister, $src$$XMMRegister);
9988 %}
9989 ins_pipe( pipe_slow );
9990 %}
9992 instruct mulXD_imm(regXD dst, immXD con) %{
9993 predicate(UseSSE>=2);
9994 match(Set dst (MulD dst con));
9995 format %{ "MULSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
9996 ins_encode %{
9997 __ mulsd($dst$$XMMRegister, $constantaddress($con));
9998 %}
9999 ins_pipe(pipe_slow);
10000 %}
10002 instruct mulXD_mem(regXD dst, memory mem) %{
10003 predicate(UseSSE>=2);
10004 match(Set dst (MulD dst (LoadD mem)));
10005 format %{ "MULSD $dst,$mem" %}
10006 ins_encode %{
10007 __ mulsd($dst$$XMMRegister, $mem$$Address);
10008 %}
10009 ins_pipe( pipe_slow );
10010 %}
10012 // Div two double precision floating point values in xmm
10013 instruct divXD_reg(regXD dst, regXD src) %{
10014 predicate(UseSSE>=2);
10015 match(Set dst (DivD dst src));
10016 format %{ "DIVSD $dst,$src" %}
10017 opcode(0xF2, 0x0F, 0x5E);
10018 ins_encode %{
10019 __ divsd($dst$$XMMRegister, $src$$XMMRegister);
10020 %}
10021 ins_pipe( pipe_slow );
10022 %}
10024 instruct divXD_imm(regXD dst, immXD con) %{
10025 predicate(UseSSE>=2);
10026 match(Set dst (DivD dst con));
10027 format %{ "DIVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
10028 ins_encode %{
10029 __ divsd($dst$$XMMRegister, $constantaddress($con));
10030 %}
10031 ins_pipe(pipe_slow);
10032 %}
10034 instruct divXD_mem(regXD dst, memory mem) %{
10035 predicate(UseSSE>=2);
10036 match(Set dst (DivD dst (LoadD mem)));
10037 format %{ "DIVSD $dst,$mem" %}
10038 ins_encode %{
10039 __ divsd($dst$$XMMRegister, $mem$$Address);
10040 %}
10041 ins_pipe( pipe_slow );
10042 %}
10045 instruct mulD_reg(regD dst, regD src) %{
10046 predicate(UseSSE<=1);
10047 match(Set dst (MulD dst src));
10048 format %{ "FLD $src\n\t"
10049 "DMULp $dst,ST" %}
10050 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10051 ins_cost(150);
10052 ins_encode( Push_Reg_D(src),
10053 OpcP, RegOpc(dst) );
10054 ins_pipe( fpu_reg_reg );
10055 %}
10057 // Strict FP instruction biases argument before multiply then
10058 // biases result to avoid double rounding of subnormals.
10059 //
10060 // scale arg1 by multiplying arg1 by 2^(-15360)
10061 // load arg2
10062 // multiply scaled arg1 by arg2
10063 // rescale product by 2^(15360)
10064 //
10065 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{
10066 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10067 match(Set dst (MulD dst src));
10068 ins_cost(1); // Select this instruction for all strict FP double multiplies
10070 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10071 "DMULp $dst,ST\n\t"
10072 "FLD $src\n\t"
10073 "DMULp $dst,ST\n\t"
10074 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10075 "DMULp $dst,ST\n\t" %}
10076 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10077 ins_encode( strictfp_bias1(dst),
10078 Push_Reg_D(src),
10079 OpcP, RegOpc(dst),
10080 strictfp_bias2(dst) );
10081 ins_pipe( fpu_reg_reg );
10082 %}
10084 instruct mulD_reg_imm(regD dst, immD con) %{
10085 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10086 match(Set dst (MulD dst con));
10087 ins_cost(200);
10088 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
10089 "DMULp $dst,ST" %}
10090 ins_encode %{
10091 __ fld_d($constantaddress($con));
10092 __ fmulp($dst$$reg);
10093 %}
10094 ins_pipe(fpu_reg_mem);
10095 %}
10098 instruct mulD_reg_mem(regD dst, memory src) %{
10099 predicate( UseSSE<=1 );
10100 match(Set dst (MulD dst (LoadD src)));
10101 ins_cost(200);
10102 format %{ "FLD_D $src\n\t"
10103 "DMULp $dst,ST" %}
10104 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
10105 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10106 OpcP, RegOpc(dst) );
10107 ins_pipe( fpu_reg_mem );
10108 %}
10110 //
10111 // Cisc-alternate to reg-reg multiply
10112 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{
10113 predicate( UseSSE<=1 );
10114 match(Set dst (MulD src (LoadD mem)));
10115 ins_cost(250);
10116 format %{ "FLD_D $mem\n\t"
10117 "DMUL ST,$src\n\t"
10118 "FSTP_D $dst" %}
10119 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
10120 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
10121 OpcReg_F(src),
10122 Pop_Reg_D(dst) );
10123 ins_pipe( fpu_reg_reg_mem );
10124 %}
10127 // MACRO3 -- addD a mulD
10128 // This instruction is a '2-address' instruction in that the result goes
10129 // back to src2. This eliminates a move from the macro; possibly the
10130 // register allocator will have to add it back (and maybe not).
10131 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{
10132 predicate( UseSSE<=1 );
10133 match(Set src2 (AddD (MulD src0 src1) src2));
10134 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10135 "DMUL ST,$src1\n\t"
10136 "DADDp $src2,ST" %}
10137 ins_cost(250);
10138 opcode(0xDD); /* LoadD DD /0 */
10139 ins_encode( Push_Reg_F(src0),
10140 FMul_ST_reg(src1),
10141 FAddP_reg_ST(src2) );
10142 ins_pipe( fpu_reg_reg_reg );
10143 %}
10146 // MACRO3 -- subD a mulD
10147 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{
10148 predicate( UseSSE<=1 );
10149 match(Set src2 (SubD (MulD src0 src1) src2));
10150 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10151 "DMUL ST,$src1\n\t"
10152 "DSUBRp $src2,ST" %}
10153 ins_cost(250);
10154 ins_encode( Push_Reg_F(src0),
10155 FMul_ST_reg(src1),
10156 Opcode(0xDE), Opc_plus(0xE0,src2));
10157 ins_pipe( fpu_reg_reg_reg );
10158 %}
10161 instruct divD_reg(regD dst, regD src) %{
10162 predicate( UseSSE<=1 );
10163 match(Set dst (DivD dst src));
10165 format %{ "FLD $src\n\t"
10166 "FDIVp $dst,ST" %}
10167 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10168 ins_cost(150);
10169 ins_encode( Push_Reg_D(src),
10170 OpcP, RegOpc(dst) );
10171 ins_pipe( fpu_reg_reg );
10172 %}
10174 // Strict FP instruction biases argument before division then
10175 // biases result, to avoid double rounding of subnormals.
10176 //
10177 // scale dividend by multiplying dividend by 2^(-15360)
10178 // load divisor
10179 // divide scaled dividend by divisor
10180 // rescale quotient by 2^(15360)
10181 //
10182 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{
10183 predicate (UseSSE<=1);
10184 match(Set dst (DivD dst src));
10185 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10186 ins_cost(01);
10188 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10189 "DMULp $dst,ST\n\t"
10190 "FLD $src\n\t"
10191 "FDIVp $dst,ST\n\t"
10192 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10193 "DMULp $dst,ST\n\t" %}
10194 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10195 ins_encode( strictfp_bias1(dst),
10196 Push_Reg_D(src),
10197 OpcP, RegOpc(dst),
10198 strictfp_bias2(dst) );
10199 ins_pipe( fpu_reg_reg );
10200 %}
10202 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10203 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
10204 match(Set dst (RoundDouble (DivD src1 src2)));
10206 format %{ "FLD $src1\n\t"
10207 "FDIV ST,$src2\n\t"
10208 "FSTP_D $dst\t# D-round" %}
10209 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
10210 ins_encode( Push_Reg_D(src1),
10211 OpcP, RegOpc(src2), Pop_Mem_D(dst) );
10212 ins_pipe( fpu_mem_reg_reg );
10213 %}
10216 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{
10217 predicate(UseSSE<=1);
10218 match(Set dst (ModD dst src));
10219 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10221 format %{ "DMOD $dst,$src" %}
10222 ins_cost(250);
10223 ins_encode(Push_Reg_Mod_D(dst, src),
10224 emitModD(),
10225 Push_Result_Mod_D(src),
10226 Pop_Reg_D(dst));
10227 ins_pipe( pipe_slow );
10228 %}
10230 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{
10231 predicate(UseSSE>=2);
10232 match(Set dst (ModD src0 src1));
10233 effect(KILL rax, KILL cr);
10235 format %{ "SUB ESP,8\t # DMOD\n"
10236 "\tMOVSD [ESP+0],$src1\n"
10237 "\tFLD_D [ESP+0]\n"
10238 "\tMOVSD [ESP+0],$src0\n"
10239 "\tFLD_D [ESP+0]\n"
10240 "loop:\tFPREM\n"
10241 "\tFWAIT\n"
10242 "\tFNSTSW AX\n"
10243 "\tSAHF\n"
10244 "\tJP loop\n"
10245 "\tFSTP_D [ESP+0]\n"
10246 "\tMOVSD $dst,[ESP+0]\n"
10247 "\tADD ESP,8\n"
10248 "\tFSTP ST0\t # Restore FPU Stack"
10249 %}
10250 ins_cost(250);
10251 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU);
10252 ins_pipe( pipe_slow );
10253 %}
10255 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{
10256 predicate (UseSSE<=1);
10257 match(Set dst (SinD src));
10258 ins_cost(1800);
10259 format %{ "DSIN $dst" %}
10260 opcode(0xD9, 0xFE);
10261 ins_encode( OpcP, OpcS );
10262 ins_pipe( pipe_slow );
10263 %}
10265 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{
10266 predicate (UseSSE>=2);
10267 match(Set dst (SinD dst));
10268 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10269 ins_cost(1800);
10270 format %{ "DSIN $dst" %}
10271 opcode(0xD9, 0xFE);
10272 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10273 ins_pipe( pipe_slow );
10274 %}
10276 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{
10277 predicate (UseSSE<=1);
10278 match(Set dst (CosD src));
10279 ins_cost(1800);
10280 format %{ "DCOS $dst" %}
10281 opcode(0xD9, 0xFF);
10282 ins_encode( OpcP, OpcS );
10283 ins_pipe( pipe_slow );
10284 %}
10286 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{
10287 predicate (UseSSE>=2);
10288 match(Set dst (CosD dst));
10289 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10290 ins_cost(1800);
10291 format %{ "DCOS $dst" %}
10292 opcode(0xD9, 0xFF);
10293 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10294 ins_pipe( pipe_slow );
10295 %}
10297 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{
10298 predicate (UseSSE<=1);
10299 match(Set dst(TanD src));
10300 format %{ "DTAN $dst" %}
10301 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10302 Opcode(0xDD), Opcode(0xD8)); // fstp st
10303 ins_pipe( pipe_slow );
10304 %}
10306 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{
10307 predicate (UseSSE>=2);
10308 match(Set dst(TanD dst));
10309 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10310 format %{ "DTAN $dst" %}
10311 ins_encode( Push_SrcXD(dst),
10312 Opcode(0xD9), Opcode(0xF2), // fptan
10313 Opcode(0xDD), Opcode(0xD8), // fstp st
10314 Push_ResultXD(dst) );
10315 ins_pipe( pipe_slow );
10316 %}
10318 instruct atanD_reg(regD dst, regD src) %{
10319 predicate (UseSSE<=1);
10320 match(Set dst(AtanD dst src));
10321 format %{ "DATA $dst,$src" %}
10322 opcode(0xD9, 0xF3);
10323 ins_encode( Push_Reg_D(src),
10324 OpcP, OpcS, RegOpc(dst) );
10325 ins_pipe( pipe_slow );
10326 %}
10328 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10329 predicate (UseSSE>=2);
10330 match(Set dst(AtanD dst src));
10331 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10332 format %{ "DATA $dst,$src" %}
10333 opcode(0xD9, 0xF3);
10334 ins_encode( Push_SrcXD(src),
10335 OpcP, OpcS, Push_ResultXD(dst) );
10336 ins_pipe( pipe_slow );
10337 %}
10339 instruct sqrtD_reg(regD dst, regD src) %{
10340 predicate (UseSSE<=1);
10341 match(Set dst (SqrtD src));
10342 format %{ "DSQRT $dst,$src" %}
10343 opcode(0xFA, 0xD9);
10344 ins_encode( Push_Reg_D(src),
10345 OpcS, OpcP, Pop_Reg_D(dst) );
10346 ins_pipe( pipe_slow );
10347 %}
10349 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10350 predicate (UseSSE<=1);
10351 match(Set Y (PowD X Y)); // Raise X to the Yth power
10352 effect(KILL rax, KILL rbx, KILL rcx);
10353 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10354 "FLD_D $X\n\t"
10355 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10357 "FDUP \t\t\t# Q Q\n\t"
10358 "FRNDINT\t\t\t# int(Q) Q\n\t"
10359 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10360 "FISTP dword [ESP]\n\t"
10361 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10362 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10363 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10364 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10365 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10366 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10367 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10368 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10369 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10370 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10371 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10372 "MOV [ESP+0],0\n\t"
10373 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10375 "ADD ESP,8"
10376 %}
10377 ins_encode( push_stack_temp_qword,
10378 Push_Reg_D(X),
10379 Opcode(0xD9), Opcode(0xF1), // fyl2x
10380 pow_exp_core_encoding,
10381 pop_stack_temp_qword);
10382 ins_pipe( pipe_slow );
10383 %}
10385 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{
10386 predicate (UseSSE>=2);
10387 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10388 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx );
10389 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10390 "MOVSD [ESP],$src1\n\t"
10391 "FLD FPR1,$src1\n\t"
10392 "MOVSD [ESP],$src0\n\t"
10393 "FLD FPR1,$src0\n\t"
10394 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10396 "FDUP \t\t\t# Q Q\n\t"
10397 "FRNDINT\t\t\t# int(Q) Q\n\t"
10398 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10399 "FISTP dword [ESP]\n\t"
10400 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10401 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10402 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10403 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10404 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10405 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10406 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10407 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10408 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10409 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10410 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10411 "MOV [ESP+0],0\n\t"
10412 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10414 "FST_D [ESP]\n\t"
10415 "MOVSD $dst,[ESP]\n\t"
10416 "ADD ESP,8"
10417 %}
10418 ins_encode( push_stack_temp_qword,
10419 push_xmm_to_fpr1(src1),
10420 push_xmm_to_fpr1(src0),
10421 Opcode(0xD9), Opcode(0xF1), // fyl2x
10422 pow_exp_core_encoding,
10423 Push_ResultXD(dst) );
10424 ins_pipe( pipe_slow );
10425 %}
10428 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10429 predicate (UseSSE<=1);
10430 match(Set dpr1 (ExpD dpr1));
10431 effect(KILL rax, KILL rbx, KILL rcx);
10432 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding"
10433 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10434 "FMULP \t\t\t# Q=X*log2(e)\n\t"
10436 "FDUP \t\t\t# Q Q\n\t"
10437 "FRNDINT\t\t\t# int(Q) Q\n\t"
10438 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10439 "FISTP dword [ESP]\n\t"
10440 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10441 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10442 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10443 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10444 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10445 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10446 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10447 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10448 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10449 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10450 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10451 "MOV [ESP+0],0\n\t"
10452 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10454 "ADD ESP,8"
10455 %}
10456 ins_encode( push_stack_temp_qword,
10457 Opcode(0xD9), Opcode(0xEA), // fldl2e
10458 Opcode(0xDE), Opcode(0xC9), // fmulp
10459 pow_exp_core_encoding,
10460 pop_stack_temp_qword);
10461 ins_pipe( pipe_slow );
10462 %}
10464 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10465 predicate (UseSSE>=2);
10466 match(Set dst (ExpD src));
10467 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx);
10468 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t"
10469 "MOVSD [ESP],$src\n\t"
10470 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10471 "FMULP \t\t\t# Q=X*log2(e) X\n\t"
10473 "FDUP \t\t\t# Q Q\n\t"
10474 "FRNDINT\t\t\t# int(Q) Q\n\t"
10475 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10476 "FISTP dword [ESP]\n\t"
10477 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10478 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10479 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10480 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10481 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10482 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10483 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10484 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10485 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10486 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10487 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10488 "MOV [ESP+0],0\n\t"
10489 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10491 "FST_D [ESP]\n\t"
10492 "MOVSD $dst,[ESP]\n\t"
10493 "ADD ESP,8"
10494 %}
10495 ins_encode( Push_SrcXD(src),
10496 Opcode(0xD9), Opcode(0xEA), // fldl2e
10497 Opcode(0xDE), Opcode(0xC9), // fmulp
10498 pow_exp_core_encoding,
10499 Push_ResultXD(dst) );
10500 ins_pipe( pipe_slow );
10501 %}
10505 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{
10506 predicate (UseSSE<=1);
10507 // The source Double operand on FPU stack
10508 match(Set dst (Log10D src));
10509 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10510 // fxch ; swap ST(0) with ST(1)
10511 // fyl2x ; compute log_10(2) * log_2(x)
10512 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10513 "FXCH \n\t"
10514 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10515 %}
10516 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10517 Opcode(0xD9), Opcode(0xC9), // fxch
10518 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10520 ins_pipe( pipe_slow );
10521 %}
10523 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10524 predicate (UseSSE>=2);
10525 effect(KILL cr);
10526 match(Set dst (Log10D src));
10527 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10528 // fyl2x ; compute log_10(2) * log_2(x)
10529 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10530 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10531 %}
10532 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10533 Push_SrcXD(src),
10534 Opcode(0xD9), Opcode(0xF1), // fyl2x
10535 Push_ResultXD(dst));
10537 ins_pipe( pipe_slow );
10538 %}
10540 instruct logD_reg(regDPR1 dst, regDPR1 src) %{
10541 predicate (UseSSE<=1);
10542 // The source Double operand on FPU stack
10543 match(Set dst (LogD src));
10544 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10545 // fxch ; swap ST(0) with ST(1)
10546 // fyl2x ; compute log_e(2) * log_2(x)
10547 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10548 "FXCH \n\t"
10549 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10550 %}
10551 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10552 Opcode(0xD9), Opcode(0xC9), // fxch
10553 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10555 ins_pipe( pipe_slow );
10556 %}
10558 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10559 predicate (UseSSE>=2);
10560 effect(KILL cr);
10561 // The source and result Double operands in XMM registers
10562 match(Set dst (LogD src));
10563 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10564 // fyl2x ; compute log_e(2) * log_2(x)
10565 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10566 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10567 %}
10568 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10569 Push_SrcXD(src),
10570 Opcode(0xD9), Opcode(0xF1), // fyl2x
10571 Push_ResultXD(dst));
10572 ins_pipe( pipe_slow );
10573 %}
10575 //-------------Float Instructions-------------------------------
10576 // Float Math
10578 // Code for float compare:
10579 // fcompp();
10580 // fwait(); fnstsw_ax();
10581 // sahf();
10582 // movl(dst, unordered_result);
10583 // jcc(Assembler::parity, exit);
10584 // movl(dst, less_result);
10585 // jcc(Assembler::below, exit);
10586 // movl(dst, equal_result);
10587 // jcc(Assembler::equal, exit);
10588 // movl(dst, greater_result);
10589 // exit:
10591 // P6 version of float compare, sets condition codes in EFLAGS
10592 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10593 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10594 match(Set cr (CmpF src1 src2));
10595 effect(KILL rax);
10596 ins_cost(150);
10597 format %{ "FLD $src1\n\t"
10598 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10599 "JNP exit\n\t"
10600 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10601 "SAHF\n"
10602 "exit:\tNOP // avoid branch to branch" %}
10603 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10604 ins_encode( Push_Reg_D(src1),
10605 OpcP, RegOpc(src2),
10606 cmpF_P6_fixup );
10607 ins_pipe( pipe_slow );
10608 %}
10610 instruct cmpF_cc_P6CF(eFlagsRegUCF cr, regF src1, regF src2) %{
10611 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10612 match(Set cr (CmpF src1 src2));
10613 ins_cost(100);
10614 format %{ "FLD $src1\n\t"
10615 "FUCOMIP ST,$src2 // P6 instruction" %}
10616 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10617 ins_encode( Push_Reg_D(src1),
10618 OpcP, RegOpc(src2));
10619 ins_pipe( pipe_slow );
10620 %}
10623 // Compare & branch
10624 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10625 predicate(UseSSE == 0);
10626 match(Set cr (CmpF src1 src2));
10627 effect(KILL rax);
10628 ins_cost(200);
10629 format %{ "FLD $src1\n\t"
10630 "FCOMp $src2\n\t"
10631 "FNSTSW AX\n\t"
10632 "TEST AX,0x400\n\t"
10633 "JZ,s flags\n\t"
10634 "MOV AH,1\t# unordered treat as LT\n"
10635 "flags:\tSAHF" %}
10636 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10637 ins_encode( Push_Reg_D(src1),
10638 OpcP, RegOpc(src2),
10639 fpu_flags);
10640 ins_pipe( pipe_slow );
10641 %}
10643 // Compare vs zero into -1,0,1
10644 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{
10645 predicate(UseSSE == 0);
10646 match(Set dst (CmpF3 src1 zero));
10647 effect(KILL cr, KILL rax);
10648 ins_cost(280);
10649 format %{ "FTSTF $dst,$src1" %}
10650 opcode(0xE4, 0xD9);
10651 ins_encode( Push_Reg_D(src1),
10652 OpcS, OpcP, PopFPU,
10653 CmpF_Result(dst));
10654 ins_pipe( pipe_slow );
10655 %}
10657 // Compare into -1,0,1
10658 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
10659 predicate(UseSSE == 0);
10660 match(Set dst (CmpF3 src1 src2));
10661 effect(KILL cr, KILL rax);
10662 ins_cost(300);
10663 format %{ "FCMPF $dst,$src1,$src2" %}
10664 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10665 ins_encode( Push_Reg_D(src1),
10666 OpcP, RegOpc(src2),
10667 CmpF_Result(dst));
10668 ins_pipe( pipe_slow );
10669 %}
10671 // float compare and set condition codes in EFLAGS by XMM regs
10672 instruct cmpX_cc(eFlagsRegU cr, regX src1, regX src2) %{
10673 predicate(UseSSE>=1);
10674 match(Set cr (CmpF src1 src2));
10675 ins_cost(145);
10676 format %{ "UCOMISS $src1,$src2\n\t"
10677 "JNP,s exit\n\t"
10678 "PUSHF\t# saw NaN, set CF\n\t"
10679 "AND [rsp], #0xffffff2b\n\t"
10680 "POPF\n"
10681 "exit:" %}
10682 ins_encode %{
10683 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10684 emit_cmpfp_fixup(_masm);
10685 %}
10686 ins_pipe( pipe_slow );
10687 %}
10689 instruct cmpX_ccCF(eFlagsRegUCF cr, regX src1, regX src2) %{
10690 predicate(UseSSE>=1);
10691 match(Set cr (CmpF src1 src2));
10692 ins_cost(100);
10693 format %{ "UCOMISS $src1,$src2" %}
10694 ins_encode %{
10695 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10696 %}
10697 ins_pipe( pipe_slow );
10698 %}
10700 // float compare and set condition codes in EFLAGS by XMM regs
10701 instruct cmpX_ccmem(eFlagsRegU cr, regX src1, memory src2) %{
10702 predicate(UseSSE>=1);
10703 match(Set cr (CmpF src1 (LoadF src2)));
10704 ins_cost(165);
10705 format %{ "UCOMISS $src1,$src2\n\t"
10706 "JNP,s exit\n\t"
10707 "PUSHF\t# saw NaN, set CF\n\t"
10708 "AND [rsp], #0xffffff2b\n\t"
10709 "POPF\n"
10710 "exit:" %}
10711 ins_encode %{
10712 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10713 emit_cmpfp_fixup(_masm);
10714 %}
10715 ins_pipe( pipe_slow );
10716 %}
10718 instruct cmpX_ccmemCF(eFlagsRegUCF cr, regX src1, memory src2) %{
10719 predicate(UseSSE>=1);
10720 match(Set cr (CmpF src1 (LoadF src2)));
10721 ins_cost(100);
10722 format %{ "UCOMISS $src1,$src2" %}
10723 ins_encode %{
10724 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10725 %}
10726 ins_pipe( pipe_slow );
10727 %}
10729 // Compare into -1,0,1 in XMM
10730 instruct cmpX_reg(xRegI dst, regX src1, regX src2, eFlagsReg cr) %{
10731 predicate(UseSSE>=1);
10732 match(Set dst (CmpF3 src1 src2));
10733 effect(KILL cr);
10734 ins_cost(255);
10735 format %{ "UCOMISS $src1, $src2\n\t"
10736 "MOV $dst, #-1\n\t"
10737 "JP,s done\n\t"
10738 "JB,s done\n\t"
10739 "SETNE $dst\n\t"
10740 "MOVZB $dst, $dst\n"
10741 "done:" %}
10742 ins_encode %{
10743 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10744 emit_cmpfp3(_masm, $dst$$Register);
10745 %}
10746 ins_pipe( pipe_slow );
10747 %}
10749 // Compare into -1,0,1 in XMM and memory
10750 instruct cmpX_regmem(xRegI dst, regX src1, memory src2, eFlagsReg cr) %{
10751 predicate(UseSSE>=1);
10752 match(Set dst (CmpF3 src1 (LoadF src2)));
10753 effect(KILL cr);
10754 ins_cost(275);
10755 format %{ "UCOMISS $src1, $src2\n\t"
10756 "MOV $dst, #-1\n\t"
10757 "JP,s done\n\t"
10758 "JB,s done\n\t"
10759 "SETNE $dst\n\t"
10760 "MOVZB $dst, $dst\n"
10761 "done:" %}
10762 ins_encode %{
10763 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10764 emit_cmpfp3(_masm, $dst$$Register);
10765 %}
10766 ins_pipe( pipe_slow );
10767 %}
10769 // Spill to obtain 24-bit precision
10770 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{
10771 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10772 match(Set dst (SubF src1 src2));
10774 format %{ "FSUB $dst,$src1 - $src2" %}
10775 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10776 ins_encode( Push_Reg_F(src1),
10777 OpcReg_F(src2),
10778 Pop_Mem_F(dst) );
10779 ins_pipe( fpu_mem_reg_reg );
10780 %}
10781 //
10782 // This instruction does not round to 24-bits
10783 instruct subF_reg(regF dst, regF src) %{
10784 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10785 match(Set dst (SubF dst src));
10787 format %{ "FSUB $dst,$src" %}
10788 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10789 ins_encode( Push_Reg_F(src),
10790 OpcP, RegOpc(dst) );
10791 ins_pipe( fpu_reg_reg );
10792 %}
10794 // Spill to obtain 24-bit precision
10795 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{
10796 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10797 match(Set dst (AddF src1 src2));
10799 format %{ "FADD $dst,$src1,$src2" %}
10800 opcode(0xD8, 0x0); /* D8 C0+i */
10801 ins_encode( Push_Reg_F(src2),
10802 OpcReg_F(src1),
10803 Pop_Mem_F(dst) );
10804 ins_pipe( fpu_mem_reg_reg );
10805 %}
10806 //
10807 // This instruction does not round to 24-bits
10808 instruct addF_reg(regF dst, regF src) %{
10809 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10810 match(Set dst (AddF dst src));
10812 format %{ "FLD $src\n\t"
10813 "FADDp $dst,ST" %}
10814 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10815 ins_encode( Push_Reg_F(src),
10816 OpcP, RegOpc(dst) );
10817 ins_pipe( fpu_reg_reg );
10818 %}
10820 // Add two single precision floating point values in xmm
10821 instruct addX_reg(regX dst, regX src) %{
10822 predicate(UseSSE>=1);
10823 match(Set dst (AddF dst src));
10824 format %{ "ADDSS $dst,$src" %}
10825 ins_encode %{
10826 __ addss($dst$$XMMRegister, $src$$XMMRegister);
10827 %}
10828 ins_pipe( pipe_slow );
10829 %}
10831 instruct addX_imm(regX dst, immXF con) %{
10832 predicate(UseSSE>=1);
10833 match(Set dst (AddF dst con));
10834 format %{ "ADDSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
10835 ins_encode %{
10836 __ addss($dst$$XMMRegister, $constantaddress($con));
10837 %}
10838 ins_pipe(pipe_slow);
10839 %}
10841 instruct addX_mem(regX dst, memory mem) %{
10842 predicate(UseSSE>=1);
10843 match(Set dst (AddF dst (LoadF mem)));
10844 format %{ "ADDSS $dst,$mem" %}
10845 ins_encode %{
10846 __ addss($dst$$XMMRegister, $mem$$Address);
10847 %}
10848 ins_pipe( pipe_slow );
10849 %}
10851 // Subtract two single precision floating point values in xmm
10852 instruct subX_reg(regX dst, regX src) %{
10853 predicate(UseSSE>=1);
10854 match(Set dst (SubF dst src));
10855 ins_cost(150);
10856 format %{ "SUBSS $dst,$src" %}
10857 ins_encode %{
10858 __ subss($dst$$XMMRegister, $src$$XMMRegister);
10859 %}
10860 ins_pipe( pipe_slow );
10861 %}
10863 instruct subX_imm(regX dst, immXF con) %{
10864 predicate(UseSSE>=1);
10865 match(Set dst (SubF dst con));
10866 ins_cost(150);
10867 format %{ "SUBSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
10868 ins_encode %{
10869 __ subss($dst$$XMMRegister, $constantaddress($con));
10870 %}
10871 ins_pipe(pipe_slow);
10872 %}
10874 instruct subX_mem(regX dst, memory mem) %{
10875 predicate(UseSSE>=1);
10876 match(Set dst (SubF dst (LoadF mem)));
10877 ins_cost(150);
10878 format %{ "SUBSS $dst,$mem" %}
10879 ins_encode %{
10880 __ subss($dst$$XMMRegister, $mem$$Address);
10881 %}
10882 ins_pipe( pipe_slow );
10883 %}
10885 // Multiply two single precision floating point values in xmm
10886 instruct mulX_reg(regX dst, regX src) %{
10887 predicate(UseSSE>=1);
10888 match(Set dst (MulF dst src));
10889 format %{ "MULSS $dst,$src" %}
10890 ins_encode %{
10891 __ mulss($dst$$XMMRegister, $src$$XMMRegister);
10892 %}
10893 ins_pipe( pipe_slow );
10894 %}
10896 instruct mulX_imm(regX dst, immXF con) %{
10897 predicate(UseSSE>=1);
10898 match(Set dst (MulF dst con));
10899 format %{ "MULSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
10900 ins_encode %{
10901 __ mulss($dst$$XMMRegister, $constantaddress($con));
10902 %}
10903 ins_pipe(pipe_slow);
10904 %}
10906 instruct mulX_mem(regX dst, memory mem) %{
10907 predicate(UseSSE>=1);
10908 match(Set dst (MulF dst (LoadF mem)));
10909 format %{ "MULSS $dst,$mem" %}
10910 ins_encode %{
10911 __ mulss($dst$$XMMRegister, $mem$$Address);
10912 %}
10913 ins_pipe( pipe_slow );
10914 %}
10916 // Divide two single precision floating point values in xmm
10917 instruct divX_reg(regX dst, regX src) %{
10918 predicate(UseSSE>=1);
10919 match(Set dst (DivF dst src));
10920 format %{ "DIVSS $dst,$src" %}
10921 ins_encode %{
10922 __ divss($dst$$XMMRegister, $src$$XMMRegister);
10923 %}
10924 ins_pipe( pipe_slow );
10925 %}
10927 instruct divX_imm(regX dst, immXF con) %{
10928 predicate(UseSSE>=1);
10929 match(Set dst (DivF dst con));
10930 format %{ "DIVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
10931 ins_encode %{
10932 __ divss($dst$$XMMRegister, $constantaddress($con));
10933 %}
10934 ins_pipe(pipe_slow);
10935 %}
10937 instruct divX_mem(regX dst, memory mem) %{
10938 predicate(UseSSE>=1);
10939 match(Set dst (DivF dst (LoadF mem)));
10940 format %{ "DIVSS $dst,$mem" %}
10941 ins_encode %{
10942 __ divss($dst$$XMMRegister, $mem$$Address);
10943 %}
10944 ins_pipe( pipe_slow );
10945 %}
10947 // Get the square root of a single precision floating point values in xmm
10948 instruct sqrtX_reg(regX dst, regX src) %{
10949 predicate(UseSSE>=1);
10950 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10951 ins_cost(150);
10952 format %{ "SQRTSS $dst,$src" %}
10953 ins_encode %{
10954 __ sqrtss($dst$$XMMRegister, $src$$XMMRegister);
10955 %}
10956 ins_pipe( pipe_slow );
10957 %}
10959 instruct sqrtX_mem(regX dst, memory mem) %{
10960 predicate(UseSSE>=1);
10961 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem)))));
10962 ins_cost(150);
10963 format %{ "SQRTSS $dst,$mem" %}
10964 ins_encode %{
10965 __ sqrtss($dst$$XMMRegister, $mem$$Address);
10966 %}
10967 ins_pipe( pipe_slow );
10968 %}
10970 // Get the square root of a double precision floating point values in xmm
10971 instruct sqrtXD_reg(regXD dst, regXD src) %{
10972 predicate(UseSSE>=2);
10973 match(Set dst (SqrtD src));
10974 ins_cost(150);
10975 format %{ "SQRTSD $dst,$src" %}
10976 ins_encode %{
10977 __ sqrtsd($dst$$XMMRegister, $src$$XMMRegister);
10978 %}
10979 ins_pipe( pipe_slow );
10980 %}
10982 instruct sqrtXD_mem(regXD dst, memory mem) %{
10983 predicate(UseSSE>=2);
10984 match(Set dst (SqrtD (LoadD mem)));
10985 ins_cost(150);
10986 format %{ "SQRTSD $dst,$mem" %}
10987 ins_encode %{
10988 __ sqrtsd($dst$$XMMRegister, $mem$$Address);
10989 %}
10990 ins_pipe( pipe_slow );
10991 %}
10993 instruct absF_reg(regFPR1 dst, regFPR1 src) %{
10994 predicate(UseSSE==0);
10995 match(Set dst (AbsF src));
10996 ins_cost(100);
10997 format %{ "FABS" %}
10998 opcode(0xE1, 0xD9);
10999 ins_encode( OpcS, OpcP );
11000 ins_pipe( fpu_reg_reg );
11001 %}
11003 instruct absX_reg(regX dst ) %{
11004 predicate(UseSSE>=1);
11005 match(Set dst (AbsF dst));
11006 ins_cost(150);
11007 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %}
11008 ins_encode %{
11009 __ andps($dst$$XMMRegister,
11010 ExternalAddress((address)float_signmask_pool));
11011 %}
11012 ins_pipe( pipe_slow );
11013 %}
11015 instruct negF_reg(regFPR1 dst, regFPR1 src) %{
11016 predicate(UseSSE==0);
11017 match(Set dst (NegF src));
11018 ins_cost(100);
11019 format %{ "FCHS" %}
11020 opcode(0xE0, 0xD9);
11021 ins_encode( OpcS, OpcP );
11022 ins_pipe( fpu_reg_reg );
11023 %}
11025 instruct negX_reg( regX dst ) %{
11026 predicate(UseSSE>=1);
11027 match(Set dst (NegF dst));
11028 ins_cost(150);
11029 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %}
11030 ins_encode %{
11031 __ xorps($dst$$XMMRegister,
11032 ExternalAddress((address)float_signflip_pool));
11033 %}
11034 ins_pipe( pipe_slow );
11035 %}
11037 // Cisc-alternate to addF_reg
11038 // Spill to obtain 24-bit precision
11039 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11040 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11041 match(Set dst (AddF src1 (LoadF src2)));
11043 format %{ "FLD $src2\n\t"
11044 "FADD ST,$src1\n\t"
11045 "FSTP_S $dst" %}
11046 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11047 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11048 OpcReg_F(src1),
11049 Pop_Mem_F(dst) );
11050 ins_pipe( fpu_mem_reg_mem );
11051 %}
11052 //
11053 // Cisc-alternate to addF_reg
11054 // This instruction does not round to 24-bits
11055 instruct addF_reg_mem(regF dst, memory src) %{
11056 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11057 match(Set dst (AddF dst (LoadF src)));
11059 format %{ "FADD $dst,$src" %}
11060 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
11061 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
11062 OpcP, RegOpc(dst) );
11063 ins_pipe( fpu_reg_mem );
11064 %}
11066 // // Following two instructions for _222_mpegaudio
11067 // Spill to obtain 24-bit precision
11068 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{
11069 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11070 match(Set dst (AddF src1 src2));
11072 format %{ "FADD $dst,$src1,$src2" %}
11073 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11074 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
11075 OpcReg_F(src2),
11076 Pop_Mem_F(dst) );
11077 ins_pipe( fpu_mem_reg_mem );
11078 %}
11080 // Cisc-spill variant
11081 // Spill to obtain 24-bit precision
11082 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
11083 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11084 match(Set dst (AddF src1 (LoadF src2)));
11086 format %{ "FADD $dst,$src1,$src2 cisc" %}
11087 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11088 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11089 set_instruction_start,
11090 OpcP, RMopc_Mem(secondary,src1),
11091 Pop_Mem_F(dst) );
11092 ins_pipe( fpu_mem_mem_mem );
11093 %}
11095 // Spill to obtain 24-bit precision
11096 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11097 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11098 match(Set dst (AddF src1 src2));
11100 format %{ "FADD $dst,$src1,$src2" %}
11101 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
11102 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11103 set_instruction_start,
11104 OpcP, RMopc_Mem(secondary,src1),
11105 Pop_Mem_F(dst) );
11106 ins_pipe( fpu_mem_mem_mem );
11107 %}
11110 // Spill to obtain 24-bit precision
11111 instruct addF24_reg_imm(stackSlotF dst, regF src, immF con) %{
11112 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11113 match(Set dst (AddF src con));
11114 format %{ "FLD $src\n\t"
11115 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
11116 "FSTP_S $dst" %}
11117 ins_encode %{
11118 __ fld_s($src$$reg - 1); // FLD ST(i-1)
11119 __ fadd_s($constantaddress($con));
11120 __ fstp_s(Address(rsp, $dst$$disp));
11121 %}
11122 ins_pipe(fpu_mem_reg_con);
11123 %}
11124 //
11125 // This instruction does not round to 24-bits
11126 instruct addF_reg_imm(regF dst, regF src, immF con) %{
11127 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11128 match(Set dst (AddF src con));
11129 format %{ "FLD $src\n\t"
11130 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
11131 "FSTP $dst" %}
11132 ins_encode %{
11133 __ fld_s($src$$reg - 1); // FLD ST(i-1)
11134 __ fadd_s($constantaddress($con));
11135 __ fstp_d($dst$$reg);
11136 %}
11137 ins_pipe(fpu_reg_reg_con);
11138 %}
11140 // Spill to obtain 24-bit precision
11141 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{
11142 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11143 match(Set dst (MulF src1 src2));
11145 format %{ "FLD $src1\n\t"
11146 "FMUL $src2\n\t"
11147 "FSTP_S $dst" %}
11148 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
11149 ins_encode( Push_Reg_F(src1),
11150 OpcReg_F(src2),
11151 Pop_Mem_F(dst) );
11152 ins_pipe( fpu_mem_reg_reg );
11153 %}
11154 //
11155 // This instruction does not round to 24-bits
11156 instruct mulF_reg(regF dst, regF src1, regF src2) %{
11157 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11158 match(Set dst (MulF src1 src2));
11160 format %{ "FLD $src1\n\t"
11161 "FMUL $src2\n\t"
11162 "FSTP_S $dst" %}
11163 opcode(0xD8, 0x1); /* D8 C8+i */
11164 ins_encode( Push_Reg_F(src2),
11165 OpcReg_F(src1),
11166 Pop_Reg_F(dst) );
11167 ins_pipe( fpu_reg_reg_reg );
11168 %}
11171 // Spill to obtain 24-bit precision
11172 // Cisc-alternate to reg-reg multiply
11173 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11174 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11175 match(Set dst (MulF src1 (LoadF src2)));
11177 format %{ "FLD_S $src2\n\t"
11178 "FMUL $src1\n\t"
11179 "FSTP_S $dst" %}
11180 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
11181 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11182 OpcReg_F(src1),
11183 Pop_Mem_F(dst) );
11184 ins_pipe( fpu_mem_reg_mem );
11185 %}
11186 //
11187 // This instruction does not round to 24-bits
11188 // Cisc-alternate to reg-reg multiply
11189 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{
11190 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11191 match(Set dst (MulF src1 (LoadF src2)));
11193 format %{ "FMUL $dst,$src1,$src2" %}
11194 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
11195 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11196 OpcReg_F(src1),
11197 Pop_Reg_F(dst) );
11198 ins_pipe( fpu_reg_reg_mem );
11199 %}
11201 // Spill to obtain 24-bit precision
11202 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11203 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11204 match(Set dst (MulF src1 src2));
11206 format %{ "FMUL $dst,$src1,$src2" %}
11207 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
11208 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11209 set_instruction_start,
11210 OpcP, RMopc_Mem(secondary,src1),
11211 Pop_Mem_F(dst) );
11212 ins_pipe( fpu_mem_mem_mem );
11213 %}
11215 // Spill to obtain 24-bit precision
11216 instruct mulF24_reg_imm(stackSlotF dst, regF src, immF con) %{
11217 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11218 match(Set dst (MulF src con));
11220 format %{ "FLD $src\n\t"
11221 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
11222 "FSTP_S $dst" %}
11223 ins_encode %{
11224 __ fld_s($src$$reg - 1); // FLD ST(i-1)
11225 __ fmul_s($constantaddress($con));
11226 __ fstp_s(Address(rsp, $dst$$disp));
11227 %}
11228 ins_pipe(fpu_mem_reg_con);
11229 %}
11230 //
11231 // This instruction does not round to 24-bits
11232 instruct mulF_reg_imm(regF dst, regF src, immF con) %{
11233 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11234 match(Set dst (MulF src con));
11236 format %{ "FLD $src\n\t"
11237 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
11238 "FSTP $dst" %}
11239 ins_encode %{
11240 __ fld_s($src$$reg - 1); // FLD ST(i-1)
11241 __ fmul_s($constantaddress($con));
11242 __ fstp_d($dst$$reg);
11243 %}
11244 ins_pipe(fpu_reg_reg_con);
11245 %}
11248 //
11249 // MACRO1 -- subsume unshared load into mulF
11250 // This instruction does not round to 24-bits
11251 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{
11252 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11253 match(Set dst (MulF (LoadF mem1) src));
11255 format %{ "FLD $mem1 ===MACRO1===\n\t"
11256 "FMUL ST,$src\n\t"
11257 "FSTP $dst" %}
11258 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
11259 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
11260 OpcReg_F(src),
11261 Pop_Reg_F(dst) );
11262 ins_pipe( fpu_reg_reg_mem );
11263 %}
11264 //
11265 // MACRO2 -- addF a mulF which subsumed an unshared load
11266 // This instruction does not round to 24-bits
11267 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{
11268 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11269 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
11270 ins_cost(95);
11272 format %{ "FLD $mem1 ===MACRO2===\n\t"
11273 "FMUL ST,$src1 subsume mulF left load\n\t"
11274 "FADD ST,$src2\n\t"
11275 "FSTP $dst" %}
11276 opcode(0xD9); /* LoadF D9 /0 */
11277 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
11278 FMul_ST_reg(src1),
11279 FAdd_ST_reg(src2),
11280 Pop_Reg_F(dst) );
11281 ins_pipe( fpu_reg_mem_reg_reg );
11282 %}
11284 // MACRO3 -- addF a mulF
11285 // This instruction does not round to 24-bits. It is a '2-address'
11286 // instruction in that the result goes back to src2. This eliminates
11287 // a move from the macro; possibly the register allocator will have
11288 // to add it back (and maybe not).
11289 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{
11290 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11291 match(Set src2 (AddF (MulF src0 src1) src2));
11293 format %{ "FLD $src0 ===MACRO3===\n\t"
11294 "FMUL ST,$src1\n\t"
11295 "FADDP $src2,ST" %}
11296 opcode(0xD9); /* LoadF D9 /0 */
11297 ins_encode( Push_Reg_F(src0),
11298 FMul_ST_reg(src1),
11299 FAddP_reg_ST(src2) );
11300 ins_pipe( fpu_reg_reg_reg );
11301 %}
11303 // MACRO4 -- divF subF
11304 // This instruction does not round to 24-bits
11305 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{
11306 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11307 match(Set dst (DivF (SubF src2 src1) src3));
11309 format %{ "FLD $src2 ===MACRO4===\n\t"
11310 "FSUB ST,$src1\n\t"
11311 "FDIV ST,$src3\n\t"
11312 "FSTP $dst" %}
11313 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11314 ins_encode( Push_Reg_F(src2),
11315 subF_divF_encode(src1,src3),
11316 Pop_Reg_F(dst) );
11317 ins_pipe( fpu_reg_reg_reg_reg );
11318 %}
11320 // Spill to obtain 24-bit precision
11321 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{
11322 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11323 match(Set dst (DivF src1 src2));
11325 format %{ "FDIV $dst,$src1,$src2" %}
11326 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
11327 ins_encode( Push_Reg_F(src1),
11328 OpcReg_F(src2),
11329 Pop_Mem_F(dst) );
11330 ins_pipe( fpu_mem_reg_reg );
11331 %}
11332 //
11333 // This instruction does not round to 24-bits
11334 instruct divF_reg(regF dst, regF src) %{
11335 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11336 match(Set dst (DivF dst src));
11338 format %{ "FDIV $dst,$src" %}
11339 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11340 ins_encode( Push_Reg_F(src),
11341 OpcP, RegOpc(dst) );
11342 ins_pipe( fpu_reg_reg );
11343 %}
11346 // Spill to obtain 24-bit precision
11347 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
11348 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11349 match(Set dst (ModF src1 src2));
11350 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11352 format %{ "FMOD $dst,$src1,$src2" %}
11353 ins_encode( Push_Reg_Mod_D(src1, src2),
11354 emitModD(),
11355 Push_Result_Mod_D(src2),
11356 Pop_Mem_F(dst));
11357 ins_pipe( pipe_slow );
11358 %}
11359 //
11360 // This instruction does not round to 24-bits
11361 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{
11362 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11363 match(Set dst (ModF dst src));
11364 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11366 format %{ "FMOD $dst,$src" %}
11367 ins_encode(Push_Reg_Mod_D(dst, src),
11368 emitModD(),
11369 Push_Result_Mod_D(src),
11370 Pop_Reg_F(dst));
11371 ins_pipe( pipe_slow );
11372 %}
11374 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{
11375 predicate(UseSSE>=1);
11376 match(Set dst (ModF src0 src1));
11377 effect(KILL rax, KILL cr);
11378 format %{ "SUB ESP,4\t # FMOD\n"
11379 "\tMOVSS [ESP+0],$src1\n"
11380 "\tFLD_S [ESP+0]\n"
11381 "\tMOVSS [ESP+0],$src0\n"
11382 "\tFLD_S [ESP+0]\n"
11383 "loop:\tFPREM\n"
11384 "\tFWAIT\n"
11385 "\tFNSTSW AX\n"
11386 "\tSAHF\n"
11387 "\tJP loop\n"
11388 "\tFSTP_S [ESP+0]\n"
11389 "\tMOVSS $dst,[ESP+0]\n"
11390 "\tADD ESP,4\n"
11391 "\tFSTP ST0\t # Restore FPU Stack"
11392 %}
11393 ins_cost(250);
11394 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU);
11395 ins_pipe( pipe_slow );
11396 %}
11399 //----------Arithmetic Conversion Instructions---------------------------------
11400 // The conversions operations are all Alpha sorted. Please keep it that way!
11402 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{
11403 predicate(UseSSE==0);
11404 match(Set dst (RoundFloat src));
11405 ins_cost(125);
11406 format %{ "FST_S $dst,$src\t# F-round" %}
11407 ins_encode( Pop_Mem_Reg_F(dst, src) );
11408 ins_pipe( fpu_mem_reg );
11409 %}
11411 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{
11412 predicate(UseSSE<=1);
11413 match(Set dst (RoundDouble src));
11414 ins_cost(125);
11415 format %{ "FST_D $dst,$src\t# D-round" %}
11416 ins_encode( Pop_Mem_Reg_D(dst, src) );
11417 ins_pipe( fpu_mem_reg );
11418 %}
11420 // Force rounding to 24-bit precision and 6-bit exponent
11421 instruct convD2F_reg(stackSlotF dst, regD src) %{
11422 predicate(UseSSE==0);
11423 match(Set dst (ConvD2F src));
11424 format %{ "FST_S $dst,$src\t# F-round" %}
11425 expand %{
11426 roundFloat_mem_reg(dst,src);
11427 %}
11428 %}
11430 // Force rounding to 24-bit precision and 6-bit exponent
11431 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{
11432 predicate(UseSSE==1);
11433 match(Set dst (ConvD2F src));
11434 effect( KILL cr );
11435 format %{ "SUB ESP,4\n\t"
11436 "FST_S [ESP],$src\t# F-round\n\t"
11437 "MOVSS $dst,[ESP]\n\t"
11438 "ADD ESP,4" %}
11439 ins_encode %{
11440 __ subptr(rsp, 4);
11441 if ($src$$reg != FPR1L_enc) {
11442 __ fld_s($src$$reg-1);
11443 __ fstp_s(Address(rsp, 0));
11444 } else {
11445 __ fst_s(Address(rsp, 0));
11446 }
11447 __ movflt($dst$$XMMRegister, Address(rsp, 0));
11448 __ addptr(rsp, 4);
11449 %}
11450 ins_pipe( pipe_slow );
11451 %}
11453 // Force rounding double precision to single precision
11454 instruct convXD2X_reg(regX dst, regXD src) %{
11455 predicate(UseSSE>=2);
11456 match(Set dst (ConvD2F src));
11457 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
11458 ins_encode %{
11459 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
11460 %}
11461 ins_pipe( pipe_slow );
11462 %}
11464 instruct convF2D_reg_reg(regD dst, regF src) %{
11465 predicate(UseSSE==0);
11466 match(Set dst (ConvF2D src));
11467 format %{ "FST_S $dst,$src\t# D-round" %}
11468 ins_encode( Pop_Reg_Reg_D(dst, src));
11469 ins_pipe( fpu_reg_reg );
11470 %}
11472 instruct convF2D_reg(stackSlotD dst, regF src) %{
11473 predicate(UseSSE==1);
11474 match(Set dst (ConvF2D src));
11475 format %{ "FST_D $dst,$src\t# D-round" %}
11476 expand %{
11477 roundDouble_mem_reg(dst,src);
11478 %}
11479 %}
11481 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{
11482 predicate(UseSSE==1);
11483 match(Set dst (ConvF2D src));
11484 effect( KILL cr );
11485 format %{ "SUB ESP,4\n\t"
11486 "MOVSS [ESP] $src\n\t"
11487 "FLD_S [ESP]\n\t"
11488 "ADD ESP,4\n\t"
11489 "FSTP $dst\t# D-round" %}
11490 ins_encode %{
11491 __ subptr(rsp, 4);
11492 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11493 __ fld_s(Address(rsp, 0));
11494 __ addptr(rsp, 4);
11495 __ fstp_d($dst$$reg);
11496 %}
11497 ins_pipe( pipe_slow );
11498 %}
11500 instruct convX2XD_reg(regXD dst, regX src) %{
11501 predicate(UseSSE>=2);
11502 match(Set dst (ConvF2D src));
11503 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11504 ins_encode %{
11505 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
11506 %}
11507 ins_pipe( pipe_slow );
11508 %}
11510 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11511 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11512 predicate(UseSSE<=1);
11513 match(Set dst (ConvD2I src));
11514 effect( KILL tmp, KILL cr );
11515 format %{ "FLD $src\t# Convert double to int \n\t"
11516 "FLDCW trunc mode\n\t"
11517 "SUB ESP,4\n\t"
11518 "FISTp [ESP + #0]\n\t"
11519 "FLDCW std/24-bit mode\n\t"
11520 "POP EAX\n\t"
11521 "CMP EAX,0x80000000\n\t"
11522 "JNE,s fast\n\t"
11523 "FLD_D $src\n\t"
11524 "CALL d2i_wrapper\n"
11525 "fast:" %}
11526 ins_encode( Push_Reg_D(src), D2I_encoding(src) );
11527 ins_pipe( pipe_slow );
11528 %}
11530 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11531 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{
11532 predicate(UseSSE>=2);
11533 match(Set dst (ConvD2I src));
11534 effect( KILL tmp, KILL cr );
11535 format %{ "CVTTSD2SI $dst, $src\n\t"
11536 "CMP $dst,0x80000000\n\t"
11537 "JNE,s fast\n\t"
11538 "SUB ESP, 8\n\t"
11539 "MOVSD [ESP], $src\n\t"
11540 "FLD_D [ESP]\n\t"
11541 "ADD ESP, 8\n\t"
11542 "CALL d2i_wrapper\n"
11543 "fast:" %}
11544 ins_encode %{
11545 Label fast;
11546 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
11547 __ cmpl($dst$$Register, 0x80000000);
11548 __ jccb(Assembler::notEqual, fast);
11549 __ subptr(rsp, 8);
11550 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11551 __ fld_d(Address(rsp, 0));
11552 __ addptr(rsp, 8);
11553 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11554 __ bind(fast);
11555 %}
11556 ins_pipe( pipe_slow );
11557 %}
11559 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11560 predicate(UseSSE<=1);
11561 match(Set dst (ConvD2L src));
11562 effect( KILL cr );
11563 format %{ "FLD $src\t# Convert double to long\n\t"
11564 "FLDCW trunc mode\n\t"
11565 "SUB ESP,8\n\t"
11566 "FISTp [ESP + #0]\n\t"
11567 "FLDCW std/24-bit mode\n\t"
11568 "POP EAX\n\t"
11569 "POP EDX\n\t"
11570 "CMP EDX,0x80000000\n\t"
11571 "JNE,s fast\n\t"
11572 "TEST EAX,EAX\n\t"
11573 "JNE,s fast\n\t"
11574 "FLD $src\n\t"
11575 "CALL d2l_wrapper\n"
11576 "fast:" %}
11577 ins_encode( Push_Reg_D(src), D2L_encoding(src) );
11578 ins_pipe( pipe_slow );
11579 %}
11581 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11582 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{
11583 predicate (UseSSE>=2);
11584 match(Set dst (ConvD2L src));
11585 effect( KILL cr );
11586 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11587 "MOVSD [ESP],$src\n\t"
11588 "FLD_D [ESP]\n\t"
11589 "FLDCW trunc mode\n\t"
11590 "FISTp [ESP + #0]\n\t"
11591 "FLDCW std/24-bit mode\n\t"
11592 "POP EAX\n\t"
11593 "POP EDX\n\t"
11594 "CMP EDX,0x80000000\n\t"
11595 "JNE,s fast\n\t"
11596 "TEST EAX,EAX\n\t"
11597 "JNE,s fast\n\t"
11598 "SUB ESP,8\n\t"
11599 "MOVSD [ESP],$src\n\t"
11600 "FLD_D [ESP]\n\t"
11601 "ADD ESP,8\n\t"
11602 "CALL d2l_wrapper\n"
11603 "fast:" %}
11604 ins_encode %{
11605 Label fast;
11606 __ subptr(rsp, 8);
11607 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11608 __ fld_d(Address(rsp, 0));
11609 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11610 __ fistp_d(Address(rsp, 0));
11611 // Restore the rounding mode, mask the exception
11612 if (Compile::current()->in_24_bit_fp_mode()) {
11613 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11614 } else {
11615 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11616 }
11617 // Load the converted long, adjust CPU stack
11618 __ pop(rax);
11619 __ pop(rdx);
11620 __ cmpl(rdx, 0x80000000);
11621 __ jccb(Assembler::notEqual, fast);
11622 __ testl(rax, rax);
11623 __ jccb(Assembler::notEqual, fast);
11624 __ subptr(rsp, 8);
11625 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11626 __ fld_d(Address(rsp, 0));
11627 __ addptr(rsp, 8);
11628 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11629 __ bind(fast);
11630 %}
11631 ins_pipe( pipe_slow );
11632 %}
11634 // Convert a double to an int. Java semantics require we do complex
11635 // manglations in the corner cases. So we set the rounding mode to
11636 // 'zero', store the darned double down as an int, and reset the
11637 // rounding mode to 'nearest'. The hardware stores a flag value down
11638 // if we would overflow or converted a NAN; we check for this and
11639 // and go the slow path if needed.
11640 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11641 predicate(UseSSE==0);
11642 match(Set dst (ConvF2I src));
11643 effect( KILL tmp, KILL cr );
11644 format %{ "FLD $src\t# Convert float to int \n\t"
11645 "FLDCW trunc mode\n\t"
11646 "SUB ESP,4\n\t"
11647 "FISTp [ESP + #0]\n\t"
11648 "FLDCW std/24-bit mode\n\t"
11649 "POP EAX\n\t"
11650 "CMP EAX,0x80000000\n\t"
11651 "JNE,s fast\n\t"
11652 "FLD $src\n\t"
11653 "CALL d2i_wrapper\n"
11654 "fast:" %}
11655 // D2I_encoding works for F2I
11656 ins_encode( Push_Reg_F(src), D2I_encoding(src) );
11657 ins_pipe( pipe_slow );
11658 %}
11660 // Convert a float in xmm to an int reg.
11661 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{
11662 predicate(UseSSE>=1);
11663 match(Set dst (ConvF2I src));
11664 effect( KILL tmp, KILL cr );
11665 format %{ "CVTTSS2SI $dst, $src\n\t"
11666 "CMP $dst,0x80000000\n\t"
11667 "JNE,s fast\n\t"
11668 "SUB ESP, 4\n\t"
11669 "MOVSS [ESP], $src\n\t"
11670 "FLD [ESP]\n\t"
11671 "ADD ESP, 4\n\t"
11672 "CALL d2i_wrapper\n"
11673 "fast:" %}
11674 ins_encode %{
11675 Label fast;
11676 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11677 __ cmpl($dst$$Register, 0x80000000);
11678 __ jccb(Assembler::notEqual, fast);
11679 __ subptr(rsp, 4);
11680 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11681 __ fld_s(Address(rsp, 0));
11682 __ addptr(rsp, 4);
11683 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11684 __ bind(fast);
11685 %}
11686 ins_pipe( pipe_slow );
11687 %}
11689 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11690 predicate(UseSSE==0);
11691 match(Set dst (ConvF2L src));
11692 effect( KILL cr );
11693 format %{ "FLD $src\t# Convert float to long\n\t"
11694 "FLDCW trunc mode\n\t"
11695 "SUB ESP,8\n\t"
11696 "FISTp [ESP + #0]\n\t"
11697 "FLDCW std/24-bit mode\n\t"
11698 "POP EAX\n\t"
11699 "POP EDX\n\t"
11700 "CMP EDX,0x80000000\n\t"
11701 "JNE,s fast\n\t"
11702 "TEST EAX,EAX\n\t"
11703 "JNE,s fast\n\t"
11704 "FLD $src\n\t"
11705 "CALL d2l_wrapper\n"
11706 "fast:" %}
11707 // D2L_encoding works for F2L
11708 ins_encode( Push_Reg_F(src), D2L_encoding(src) );
11709 ins_pipe( pipe_slow );
11710 %}
11712 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11713 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{
11714 predicate (UseSSE>=1);
11715 match(Set dst (ConvF2L src));
11716 effect( KILL cr );
11717 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11718 "MOVSS [ESP],$src\n\t"
11719 "FLD_S [ESP]\n\t"
11720 "FLDCW trunc mode\n\t"
11721 "FISTp [ESP + #0]\n\t"
11722 "FLDCW std/24-bit mode\n\t"
11723 "POP EAX\n\t"
11724 "POP EDX\n\t"
11725 "CMP EDX,0x80000000\n\t"
11726 "JNE,s fast\n\t"
11727 "TEST EAX,EAX\n\t"
11728 "JNE,s fast\n\t"
11729 "SUB ESP,4\t# Convert float to long\n\t"
11730 "MOVSS [ESP],$src\n\t"
11731 "FLD_S [ESP]\n\t"
11732 "ADD ESP,4\n\t"
11733 "CALL d2l_wrapper\n"
11734 "fast:" %}
11735 ins_encode %{
11736 Label fast;
11737 __ subptr(rsp, 8);
11738 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11739 __ fld_s(Address(rsp, 0));
11740 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11741 __ fistp_d(Address(rsp, 0));
11742 // Restore the rounding mode, mask the exception
11743 if (Compile::current()->in_24_bit_fp_mode()) {
11744 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11745 } else {
11746 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11747 }
11748 // Load the converted long, adjust CPU stack
11749 __ pop(rax);
11750 __ pop(rdx);
11751 __ cmpl(rdx, 0x80000000);
11752 __ jccb(Assembler::notEqual, fast);
11753 __ testl(rax, rax);
11754 __ jccb(Assembler::notEqual, fast);
11755 __ subptr(rsp, 4);
11756 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11757 __ fld_s(Address(rsp, 0));
11758 __ addptr(rsp, 4);
11759 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11760 __ bind(fast);
11761 %}
11762 ins_pipe( pipe_slow );
11763 %}
11765 instruct convI2D_reg(regD dst, stackSlotI src) %{
11766 predicate( UseSSE<=1 );
11767 match(Set dst (ConvI2D src));
11768 format %{ "FILD $src\n\t"
11769 "FSTP $dst" %}
11770 opcode(0xDB, 0x0); /* DB /0 */
11771 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst));
11772 ins_pipe( fpu_reg_mem );
11773 %}
11775 instruct convI2XD_reg(regXD dst, eRegI src) %{
11776 predicate( UseSSE>=2 && !UseXmmI2D );
11777 match(Set dst (ConvI2D src));
11778 format %{ "CVTSI2SD $dst,$src" %}
11779 ins_encode %{
11780 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11781 %}
11782 ins_pipe( pipe_slow );
11783 %}
11785 instruct convI2XD_mem(regXD dst, memory mem) %{
11786 predicate( UseSSE>=2 );
11787 match(Set dst (ConvI2D (LoadI mem)));
11788 format %{ "CVTSI2SD $dst,$mem" %}
11789 ins_encode %{
11790 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11791 %}
11792 ins_pipe( pipe_slow );
11793 %}
11795 instruct convXI2XD_reg(regXD dst, eRegI src)
11796 %{
11797 predicate( UseSSE>=2 && UseXmmI2D );
11798 match(Set dst (ConvI2D src));
11800 format %{ "MOVD $dst,$src\n\t"
11801 "CVTDQ2PD $dst,$dst\t# i2d" %}
11802 ins_encode %{
11803 __ movdl($dst$$XMMRegister, $src$$Register);
11804 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11805 %}
11806 ins_pipe(pipe_slow); // XXX
11807 %}
11809 instruct convI2D_mem(regD dst, memory mem) %{
11810 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11811 match(Set dst (ConvI2D (LoadI mem)));
11812 format %{ "FILD $mem\n\t"
11813 "FSTP $dst" %}
11814 opcode(0xDB); /* DB /0 */
11815 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11816 Pop_Reg_D(dst));
11817 ins_pipe( fpu_reg_mem );
11818 %}
11820 // Convert a byte to a float; no rounding step needed.
11821 instruct conv24I2F_reg(regF dst, stackSlotI src) %{
11822 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11823 match(Set dst (ConvI2F src));
11824 format %{ "FILD $src\n\t"
11825 "FSTP $dst" %}
11827 opcode(0xDB, 0x0); /* DB /0 */
11828 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst));
11829 ins_pipe( fpu_reg_mem );
11830 %}
11832 // In 24-bit mode, force exponent rounding by storing back out
11833 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{
11834 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11835 match(Set dst (ConvI2F src));
11836 ins_cost(200);
11837 format %{ "FILD $src\n\t"
11838 "FSTP_S $dst" %}
11839 opcode(0xDB, 0x0); /* DB /0 */
11840 ins_encode( Push_Mem_I(src),
11841 Pop_Mem_F(dst));
11842 ins_pipe( fpu_mem_mem );
11843 %}
11845 // In 24-bit mode, force exponent rounding by storing back out
11846 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{
11847 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11848 match(Set dst (ConvI2F (LoadI mem)));
11849 ins_cost(200);
11850 format %{ "FILD $mem\n\t"
11851 "FSTP_S $dst" %}
11852 opcode(0xDB); /* DB /0 */
11853 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11854 Pop_Mem_F(dst));
11855 ins_pipe( fpu_mem_mem );
11856 %}
11858 // This instruction does not round to 24-bits
11859 instruct convI2F_reg(regF dst, stackSlotI src) %{
11860 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11861 match(Set dst (ConvI2F src));
11862 format %{ "FILD $src\n\t"
11863 "FSTP $dst" %}
11864 opcode(0xDB, 0x0); /* DB /0 */
11865 ins_encode( Push_Mem_I(src),
11866 Pop_Reg_F(dst));
11867 ins_pipe( fpu_reg_mem );
11868 %}
11870 // This instruction does not round to 24-bits
11871 instruct convI2F_mem(regF dst, memory mem) %{
11872 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11873 match(Set dst (ConvI2F (LoadI mem)));
11874 format %{ "FILD $mem\n\t"
11875 "FSTP $dst" %}
11876 opcode(0xDB); /* DB /0 */
11877 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11878 Pop_Reg_F(dst));
11879 ins_pipe( fpu_reg_mem );
11880 %}
11882 // Convert an int to a float in xmm; no rounding step needed.
11883 instruct convI2X_reg(regX dst, eRegI src) %{
11884 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11885 match(Set dst (ConvI2F src));
11886 format %{ "CVTSI2SS $dst, $src" %}
11887 ins_encode %{
11888 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11889 %}
11890 ins_pipe( pipe_slow );
11891 %}
11893 instruct convXI2X_reg(regX dst, eRegI src)
11894 %{
11895 predicate( UseSSE>=2 && UseXmmI2F );
11896 match(Set dst (ConvI2F src));
11898 format %{ "MOVD $dst,$src\n\t"
11899 "CVTDQ2PS $dst,$dst\t# i2f" %}
11900 ins_encode %{
11901 __ movdl($dst$$XMMRegister, $src$$Register);
11902 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11903 %}
11904 ins_pipe(pipe_slow); // XXX
11905 %}
11907 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
11908 match(Set dst (ConvI2L src));
11909 effect(KILL cr);
11910 ins_cost(375);
11911 format %{ "MOV $dst.lo,$src\n\t"
11912 "MOV $dst.hi,$src\n\t"
11913 "SAR $dst.hi,31" %}
11914 ins_encode(convert_int_long(dst,src));
11915 ins_pipe( ialu_reg_reg_long );
11916 %}
11918 // Zero-extend convert int to long
11919 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
11920 match(Set dst (AndL (ConvI2L src) mask) );
11921 effect( KILL flags );
11922 ins_cost(250);
11923 format %{ "MOV $dst.lo,$src\n\t"
11924 "XOR $dst.hi,$dst.hi" %}
11925 opcode(0x33); // XOR
11926 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11927 ins_pipe( ialu_reg_reg_long );
11928 %}
11930 // Zero-extend long
11931 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11932 match(Set dst (AndL src mask) );
11933 effect( KILL flags );
11934 ins_cost(250);
11935 format %{ "MOV $dst.lo,$src.lo\n\t"
11936 "XOR $dst.hi,$dst.hi\n\t" %}
11937 opcode(0x33); // XOR
11938 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11939 ins_pipe( ialu_reg_reg_long );
11940 %}
11942 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11943 predicate (UseSSE<=1);
11944 match(Set dst (ConvL2D src));
11945 effect( KILL cr );
11946 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11947 "PUSH $src.lo\n\t"
11948 "FILD ST,[ESP + #0]\n\t"
11949 "ADD ESP,8\n\t"
11950 "FSTP_D $dst\t# D-round" %}
11951 opcode(0xDF, 0x5); /* DF /5 */
11952 ins_encode(convert_long_double(src), Pop_Mem_D(dst));
11953 ins_pipe( pipe_slow );
11954 %}
11956 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{
11957 predicate (UseSSE>=2);
11958 match(Set dst (ConvL2D src));
11959 effect( KILL cr );
11960 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11961 "PUSH $src.lo\n\t"
11962 "FILD_D [ESP]\n\t"
11963 "FSTP_D [ESP]\n\t"
11964 "MOVSD $dst,[ESP]\n\t"
11965 "ADD ESP,8" %}
11966 opcode(0xDF, 0x5); /* DF /5 */
11967 ins_encode(convert_long_double2(src), Push_ResultXD(dst));
11968 ins_pipe( pipe_slow );
11969 %}
11971 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{
11972 predicate (UseSSE>=1);
11973 match(Set dst (ConvL2F src));
11974 effect( KILL cr );
11975 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11976 "PUSH $src.lo\n\t"
11977 "FILD_D [ESP]\n\t"
11978 "FSTP_S [ESP]\n\t"
11979 "MOVSS $dst,[ESP]\n\t"
11980 "ADD ESP,8" %}
11981 opcode(0xDF, 0x5); /* DF /5 */
11982 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8));
11983 ins_pipe( pipe_slow );
11984 %}
11986 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11987 match(Set dst (ConvL2F src));
11988 effect( KILL cr );
11989 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11990 "PUSH $src.lo\n\t"
11991 "FILD ST,[ESP + #0]\n\t"
11992 "ADD ESP,8\n\t"
11993 "FSTP_S $dst\t# F-round" %}
11994 opcode(0xDF, 0x5); /* DF /5 */
11995 ins_encode(convert_long_double(src), Pop_Mem_F(dst));
11996 ins_pipe( pipe_slow );
11997 %}
11999 instruct convL2I_reg( eRegI dst, eRegL src ) %{
12000 match(Set dst (ConvL2I src));
12001 effect( DEF dst, USE src );
12002 format %{ "MOV $dst,$src.lo" %}
12003 ins_encode(enc_CopyL_Lo(dst,src));
12004 ins_pipe( ialu_reg_reg );
12005 %}
12008 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
12009 match(Set dst (MoveF2I src));
12010 effect( DEF dst, USE src );
12011 ins_cost(100);
12012 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
12013 ins_encode %{
12014 __ movl($dst$$Register, Address(rsp, $src$$disp));
12015 %}
12016 ins_pipe( ialu_reg_mem );
12017 %}
12019 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
12020 predicate(UseSSE==0);
12021 match(Set dst (MoveF2I src));
12022 effect( DEF dst, USE src );
12024 ins_cost(125);
12025 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
12026 ins_encode( Pop_Mem_Reg_F(dst, src) );
12027 ins_pipe( fpu_mem_reg );
12028 %}
12030 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{
12031 predicate(UseSSE>=1);
12032 match(Set dst (MoveF2I src));
12033 effect( DEF dst, USE src );
12035 ins_cost(95);
12036 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
12037 ins_encode %{
12038 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
12039 %}
12040 ins_pipe( pipe_slow );
12041 %}
12043 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{
12044 predicate(UseSSE>=2);
12045 match(Set dst (MoveF2I src));
12046 effect( DEF dst, USE src );
12047 ins_cost(85);
12048 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
12049 ins_encode %{
12050 __ movdl($dst$$Register, $src$$XMMRegister);
12051 %}
12052 ins_pipe( pipe_slow );
12053 %}
12055 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
12056 match(Set dst (MoveI2F src));
12057 effect( DEF dst, USE src );
12059 ins_cost(100);
12060 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
12061 ins_encode %{
12062 __ movl(Address(rsp, $dst$$disp), $src$$Register);
12063 %}
12064 ins_pipe( ialu_mem_reg );
12065 %}
12068 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
12069 predicate(UseSSE==0);
12070 match(Set dst (MoveI2F src));
12071 effect(DEF dst, USE src);
12073 ins_cost(125);
12074 format %{ "FLD_S $src\n\t"
12075 "FSTP $dst\t# MoveI2F_stack_reg" %}
12076 opcode(0xD9); /* D9 /0, FLD m32real */
12077 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12078 Pop_Reg_F(dst) );
12079 ins_pipe( fpu_reg_mem );
12080 %}
12082 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{
12083 predicate(UseSSE>=1);
12084 match(Set dst (MoveI2F src));
12085 effect( DEF dst, USE src );
12087 ins_cost(95);
12088 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
12089 ins_encode %{
12090 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
12091 %}
12092 ins_pipe( pipe_slow );
12093 %}
12095 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{
12096 predicate(UseSSE>=2);
12097 match(Set dst (MoveI2F src));
12098 effect( DEF dst, USE src );
12100 ins_cost(85);
12101 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
12102 ins_encode %{
12103 __ movdl($dst$$XMMRegister, $src$$Register);
12104 %}
12105 ins_pipe( pipe_slow );
12106 %}
12108 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
12109 match(Set dst (MoveD2L src));
12110 effect(DEF dst, USE src);
12112 ins_cost(250);
12113 format %{ "MOV $dst.lo,$src\n\t"
12114 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
12115 opcode(0x8B, 0x8B);
12116 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
12117 ins_pipe( ialu_mem_long_reg );
12118 %}
12120 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
12121 predicate(UseSSE<=1);
12122 match(Set dst (MoveD2L src));
12123 effect(DEF dst, USE src);
12125 ins_cost(125);
12126 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
12127 ins_encode( Pop_Mem_Reg_D(dst, src) );
12128 ins_pipe( fpu_mem_reg );
12129 %}
12131 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{
12132 predicate(UseSSE>=2);
12133 match(Set dst (MoveD2L src));
12134 effect(DEF dst, USE src);
12135 ins_cost(95);
12136 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
12137 ins_encode %{
12138 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
12139 %}
12140 ins_pipe( pipe_slow );
12141 %}
12143 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{
12144 predicate(UseSSE>=2);
12145 match(Set dst (MoveD2L src));
12146 effect(DEF dst, USE src, TEMP tmp);
12147 ins_cost(85);
12148 format %{ "MOVD $dst.lo,$src\n\t"
12149 "PSHUFLW $tmp,$src,0x4E\n\t"
12150 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
12151 ins_encode %{
12152 __ movdl($dst$$Register, $src$$XMMRegister);
12153 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
12154 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
12155 %}
12156 ins_pipe( pipe_slow );
12157 %}
12159 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
12160 match(Set dst (MoveL2D src));
12161 effect(DEF dst, USE src);
12163 ins_cost(200);
12164 format %{ "MOV $dst,$src.lo\n\t"
12165 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
12166 opcode(0x89, 0x89);
12167 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
12168 ins_pipe( ialu_mem_long_reg );
12169 %}
12172 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
12173 predicate(UseSSE<=1);
12174 match(Set dst (MoveL2D src));
12175 effect(DEF dst, USE src);
12176 ins_cost(125);
12178 format %{ "FLD_D $src\n\t"
12179 "FSTP $dst\t# MoveL2D_stack_reg" %}
12180 opcode(0xDD); /* DD /0, FLD m64real */
12181 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12182 Pop_Reg_D(dst) );
12183 ins_pipe( fpu_reg_mem );
12184 %}
12187 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{
12188 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
12189 match(Set dst (MoveL2D src));
12190 effect(DEF dst, USE src);
12192 ins_cost(95);
12193 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12194 ins_encode %{
12195 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
12196 %}
12197 ins_pipe( pipe_slow );
12198 %}
12200 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{
12201 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
12202 match(Set dst (MoveL2D src));
12203 effect(DEF dst, USE src);
12205 ins_cost(95);
12206 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12207 ins_encode %{
12208 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
12209 %}
12210 ins_pipe( pipe_slow );
12211 %}
12213 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{
12214 predicate(UseSSE>=2);
12215 match(Set dst (MoveL2D src));
12216 effect(TEMP dst, USE src, TEMP tmp);
12217 ins_cost(85);
12218 format %{ "MOVD $dst,$src.lo\n\t"
12219 "MOVD $tmp,$src.hi\n\t"
12220 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
12221 ins_encode %{
12222 __ movdl($dst$$XMMRegister, $src$$Register);
12223 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
12224 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
12225 %}
12226 ins_pipe( pipe_slow );
12227 %}
12229 // Replicate scalar to packed byte (1 byte) values in xmm
12230 instruct Repl8B_reg(regXD dst, regXD src) %{
12231 predicate(UseSSE>=2);
12232 match(Set dst (Replicate8B src));
12233 format %{ "MOVDQA $dst,$src\n\t"
12234 "PUNPCKLBW $dst,$dst\n\t"
12235 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12236 ins_encode %{
12237 if ($dst$$reg != $src$$reg) {
12238 __ movdqa($dst$$XMMRegister, $src$$XMMRegister);
12239 }
12240 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
12241 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
12242 %}
12243 ins_pipe( pipe_slow );
12244 %}
12246 // Replicate scalar to packed byte (1 byte) values in xmm
12247 instruct Repl8B_eRegI(regXD dst, eRegI src) %{
12248 predicate(UseSSE>=2);
12249 match(Set dst (Replicate8B src));
12250 format %{ "MOVD $dst,$src\n\t"
12251 "PUNPCKLBW $dst,$dst\n\t"
12252 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12253 ins_encode %{
12254 __ movdl($dst$$XMMRegister, $src$$Register);
12255 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
12256 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
12257 %}
12258 ins_pipe( pipe_slow );
12259 %}
12261 // Replicate scalar zero to packed byte (1 byte) values in xmm
12262 instruct Repl8B_immI0(regXD dst, immI0 zero) %{
12263 predicate(UseSSE>=2);
12264 match(Set dst (Replicate8B zero));
12265 format %{ "PXOR $dst,$dst\t! replicate8B" %}
12266 ins_encode %{
12267 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
12268 %}
12269 ins_pipe( fpu_reg_reg );
12270 %}
12272 // Replicate scalar to packed shore (2 byte) values in xmm
12273 instruct Repl4S_reg(regXD dst, regXD src) %{
12274 predicate(UseSSE>=2);
12275 match(Set dst (Replicate4S src));
12276 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
12277 ins_encode %{
12278 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00);
12279 %}
12280 ins_pipe( fpu_reg_reg );
12281 %}
12283 // Replicate scalar to packed shore (2 byte) values in xmm
12284 instruct Repl4S_eRegI(regXD dst, eRegI src) %{
12285 predicate(UseSSE>=2);
12286 match(Set dst (Replicate4S src));
12287 format %{ "MOVD $dst,$src\n\t"
12288 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
12289 ins_encode %{
12290 __ movdl($dst$$XMMRegister, $src$$Register);
12291 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
12292 %}
12293 ins_pipe( fpu_reg_reg );
12294 %}
12296 // Replicate scalar zero to packed short (2 byte) values in xmm
12297 instruct Repl4S_immI0(regXD dst, immI0 zero) %{
12298 predicate(UseSSE>=2);
12299 match(Set dst (Replicate4S zero));
12300 format %{ "PXOR $dst,$dst\t! replicate4S" %}
12301 ins_encode %{
12302 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
12303 %}
12304 ins_pipe( fpu_reg_reg );
12305 %}
12307 // Replicate scalar to packed char (2 byte) values in xmm
12308 instruct Repl4C_reg(regXD dst, regXD src) %{
12309 predicate(UseSSE>=2);
12310 match(Set dst (Replicate4C src));
12311 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
12312 ins_encode %{
12313 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00);
12314 %}
12315 ins_pipe( fpu_reg_reg );
12316 %}
12318 // Replicate scalar to packed char (2 byte) values in xmm
12319 instruct Repl4C_eRegI(regXD dst, eRegI src) %{
12320 predicate(UseSSE>=2);
12321 match(Set dst (Replicate4C src));
12322 format %{ "MOVD $dst,$src\n\t"
12323 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
12324 ins_encode %{
12325 __ movdl($dst$$XMMRegister, $src$$Register);
12326 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
12327 %}
12328 ins_pipe( fpu_reg_reg );
12329 %}
12331 // Replicate scalar zero to packed char (2 byte) values in xmm
12332 instruct Repl4C_immI0(regXD dst, immI0 zero) %{
12333 predicate(UseSSE>=2);
12334 match(Set dst (Replicate4C zero));
12335 format %{ "PXOR $dst,$dst\t! replicate4C" %}
12336 ins_encode %{
12337 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
12338 %}
12339 ins_pipe( fpu_reg_reg );
12340 %}
12342 // Replicate scalar to packed integer (4 byte) values in xmm
12343 instruct Repl2I_reg(regXD dst, regXD src) %{
12344 predicate(UseSSE>=2);
12345 match(Set dst (Replicate2I src));
12346 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
12347 ins_encode %{
12348 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00);
12349 %}
12350 ins_pipe( fpu_reg_reg );
12351 %}
12353 // Replicate scalar to packed integer (4 byte) values in xmm
12354 instruct Repl2I_eRegI(regXD dst, eRegI src) %{
12355 predicate(UseSSE>=2);
12356 match(Set dst (Replicate2I src));
12357 format %{ "MOVD $dst,$src\n\t"
12358 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
12359 ins_encode %{
12360 __ movdl($dst$$XMMRegister, $src$$Register);
12361 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
12362 %}
12363 ins_pipe( fpu_reg_reg );
12364 %}
12366 // Replicate scalar zero to packed integer (2 byte) values in xmm
12367 instruct Repl2I_immI0(regXD dst, immI0 zero) %{
12368 predicate(UseSSE>=2);
12369 match(Set dst (Replicate2I zero));
12370 format %{ "PXOR $dst,$dst\t! replicate2I" %}
12371 ins_encode %{
12372 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
12373 %}
12374 ins_pipe( fpu_reg_reg );
12375 %}
12377 // Replicate scalar to packed single precision floating point values in xmm
12378 instruct Repl2F_reg(regXD dst, regXD src) %{
12379 predicate(UseSSE>=2);
12380 match(Set dst (Replicate2F src));
12381 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12382 ins_encode %{
12383 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0);
12384 %}
12385 ins_pipe( fpu_reg_reg );
12386 %}
12388 // Replicate scalar to packed single precision floating point values in xmm
12389 instruct Repl2F_regX(regXD dst, regX src) %{
12390 predicate(UseSSE>=2);
12391 match(Set dst (Replicate2F src));
12392 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12393 ins_encode %{
12394 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0);
12395 %}
12396 ins_pipe( fpu_reg_reg );
12397 %}
12399 // Replicate scalar to packed single precision floating point values in xmm
12400 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{
12401 predicate(UseSSE>=2);
12402 match(Set dst (Replicate2F zero));
12403 format %{ "PXOR $dst,$dst\t! replicate2F" %}
12404 ins_encode %{
12405 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
12406 %}
12407 ins_pipe( fpu_reg_reg );
12408 %}
12410 // =======================================================================
12411 // fast clearing of an array
12412 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
12413 match(Set dummy (ClearArray cnt base));
12414 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
12415 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
12416 "XOR EAX,EAX\n\t"
12417 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
12418 opcode(0,0x4);
12419 ins_encode( Opcode(0xD1), RegOpc(ECX),
12420 OpcRegReg(0x33,EAX,EAX),
12421 Opcode(0xF3), Opcode(0xAB) );
12422 ins_pipe( pipe_slow );
12423 %}
12425 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
12426 eAXRegI result, regXD tmp1, eFlagsReg cr) %{
12427 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12428 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12430 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12431 ins_encode %{
12432 __ string_compare($str1$$Register, $str2$$Register,
12433 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12434 $tmp1$$XMMRegister);
12435 %}
12436 ins_pipe( pipe_slow );
12437 %}
12439 // fast string equals
12440 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
12441 regXD tmp1, regXD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
12442 match(Set result (StrEquals (Binary str1 str2) cnt));
12443 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
12445 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12446 ins_encode %{
12447 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
12448 $cnt$$Register, $result$$Register, $tmp3$$Register,
12449 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12450 %}
12451 ins_pipe( pipe_slow );
12452 %}
12454 // fast search of substring with known size.
12455 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
12456 eBXRegI result, regXD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
12457 predicate(UseSSE42Intrinsics);
12458 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
12459 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
12461 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
12462 ins_encode %{
12463 int icnt2 = (int)$int_cnt2$$constant;
12464 if (icnt2 >= 8) {
12465 // IndexOf for constant substrings with size >= 8 elements
12466 // which don't need to be loaded through stack.
12467 __ string_indexofC8($str1$$Register, $str2$$Register,
12468 $cnt1$$Register, $cnt2$$Register,
12469 icnt2, $result$$Register,
12470 $vec$$XMMRegister, $tmp$$Register);
12471 } else {
12472 // Small strings are loaded through stack if they cross page boundary.
12473 __ string_indexof($str1$$Register, $str2$$Register,
12474 $cnt1$$Register, $cnt2$$Register,
12475 icnt2, $result$$Register,
12476 $vec$$XMMRegister, $tmp$$Register);
12477 }
12478 %}
12479 ins_pipe( pipe_slow );
12480 %}
12482 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
12483 eBXRegI result, regXD vec, eCXRegI tmp, eFlagsReg cr) %{
12484 predicate(UseSSE42Intrinsics);
12485 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12486 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
12488 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
12489 ins_encode %{
12490 __ string_indexof($str1$$Register, $str2$$Register,
12491 $cnt1$$Register, $cnt2$$Register,
12492 (-1), $result$$Register,
12493 $vec$$XMMRegister, $tmp$$Register);
12494 %}
12495 ins_pipe( pipe_slow );
12496 %}
12498 // fast array equals
12499 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
12500 regXD tmp1, regXD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
12501 %{
12502 match(Set result (AryEq ary1 ary2));
12503 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12504 //ins_cost(300);
12506 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12507 ins_encode %{
12508 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
12509 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12510 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12511 %}
12512 ins_pipe( pipe_slow );
12513 %}
12515 //----------Control Flow Instructions------------------------------------------
12516 // Signed compare Instructions
12517 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
12518 match(Set cr (CmpI op1 op2));
12519 effect( DEF cr, USE op1, USE op2 );
12520 format %{ "CMP $op1,$op2" %}
12521 opcode(0x3B); /* Opcode 3B /r */
12522 ins_encode( OpcP, RegReg( op1, op2) );
12523 ins_pipe( ialu_cr_reg_reg );
12524 %}
12526 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
12527 match(Set cr (CmpI op1 op2));
12528 effect( DEF cr, USE op1 );
12529 format %{ "CMP $op1,$op2" %}
12530 opcode(0x81,0x07); /* Opcode 81 /7 */
12531 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
12532 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12533 ins_pipe( ialu_cr_reg_imm );
12534 %}
12536 // Cisc-spilled version of cmpI_eReg
12537 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
12538 match(Set cr (CmpI op1 (LoadI op2)));
12540 format %{ "CMP $op1,$op2" %}
12541 ins_cost(500);
12542 opcode(0x3B); /* Opcode 3B /r */
12543 ins_encode( OpcP, RegMem( op1, op2) );
12544 ins_pipe( ialu_cr_reg_mem );
12545 %}
12547 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
12548 match(Set cr (CmpI src zero));
12549 effect( DEF cr, USE src );
12551 format %{ "TEST $src,$src" %}
12552 opcode(0x85);
12553 ins_encode( OpcP, RegReg( src, src ) );
12554 ins_pipe( ialu_cr_reg_imm );
12555 %}
12557 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
12558 match(Set cr (CmpI (AndI src con) zero));
12560 format %{ "TEST $src,$con" %}
12561 opcode(0xF7,0x00);
12562 ins_encode( OpcP, RegOpc(src), Con32(con) );
12563 ins_pipe( ialu_cr_reg_imm );
12564 %}
12566 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
12567 match(Set cr (CmpI (AndI src mem) zero));
12569 format %{ "TEST $src,$mem" %}
12570 opcode(0x85);
12571 ins_encode( OpcP, RegMem( src, mem ) );
12572 ins_pipe( ialu_cr_reg_mem );
12573 %}
12575 // Unsigned compare Instructions; really, same as signed except they
12576 // produce an eFlagsRegU instead of eFlagsReg.
12577 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
12578 match(Set cr (CmpU op1 op2));
12580 format %{ "CMPu $op1,$op2" %}
12581 opcode(0x3B); /* Opcode 3B /r */
12582 ins_encode( OpcP, RegReg( op1, op2) );
12583 ins_pipe( ialu_cr_reg_reg );
12584 %}
12586 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
12587 match(Set cr (CmpU op1 op2));
12589 format %{ "CMPu $op1,$op2" %}
12590 opcode(0x81,0x07); /* Opcode 81 /7 */
12591 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12592 ins_pipe( ialu_cr_reg_imm );
12593 %}
12595 // // Cisc-spilled version of cmpU_eReg
12596 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
12597 match(Set cr (CmpU op1 (LoadI op2)));
12599 format %{ "CMPu $op1,$op2" %}
12600 ins_cost(500);
12601 opcode(0x3B); /* Opcode 3B /r */
12602 ins_encode( OpcP, RegMem( op1, op2) );
12603 ins_pipe( ialu_cr_reg_mem );
12604 %}
12606 // // Cisc-spilled version of cmpU_eReg
12607 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
12608 // match(Set cr (CmpU (LoadI op1) op2));
12609 //
12610 // format %{ "CMPu $op1,$op2" %}
12611 // ins_cost(500);
12612 // opcode(0x39); /* Opcode 39 /r */
12613 // ins_encode( OpcP, RegMem( op1, op2) );
12614 //%}
12616 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
12617 match(Set cr (CmpU src zero));
12619 format %{ "TESTu $src,$src" %}
12620 opcode(0x85);
12621 ins_encode( OpcP, RegReg( src, src ) );
12622 ins_pipe( ialu_cr_reg_imm );
12623 %}
12625 // Unsigned pointer compare Instructions
12626 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12627 match(Set cr (CmpP op1 op2));
12629 format %{ "CMPu $op1,$op2" %}
12630 opcode(0x3B); /* Opcode 3B /r */
12631 ins_encode( OpcP, RegReg( op1, op2) );
12632 ins_pipe( ialu_cr_reg_reg );
12633 %}
12635 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12636 match(Set cr (CmpP op1 op2));
12638 format %{ "CMPu $op1,$op2" %}
12639 opcode(0x81,0x07); /* Opcode 81 /7 */
12640 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12641 ins_pipe( ialu_cr_reg_imm );
12642 %}
12644 // // Cisc-spilled version of cmpP_eReg
12645 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12646 match(Set cr (CmpP op1 (LoadP op2)));
12648 format %{ "CMPu $op1,$op2" %}
12649 ins_cost(500);
12650 opcode(0x3B); /* Opcode 3B /r */
12651 ins_encode( OpcP, RegMem( op1, op2) );
12652 ins_pipe( ialu_cr_reg_mem );
12653 %}
12655 // // Cisc-spilled version of cmpP_eReg
12656 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12657 // match(Set cr (CmpP (LoadP op1) op2));
12658 //
12659 // format %{ "CMPu $op1,$op2" %}
12660 // ins_cost(500);
12661 // opcode(0x39); /* Opcode 39 /r */
12662 // ins_encode( OpcP, RegMem( op1, op2) );
12663 //%}
12665 // Compare raw pointer (used in out-of-heap check).
12666 // Only works because non-oop pointers must be raw pointers
12667 // and raw pointers have no anti-dependencies.
12668 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12669 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
12670 match(Set cr (CmpP op1 (LoadP op2)));
12672 format %{ "CMPu $op1,$op2" %}
12673 opcode(0x3B); /* Opcode 3B /r */
12674 ins_encode( OpcP, RegMem( op1, op2) );
12675 ins_pipe( ialu_cr_reg_mem );
12676 %}
12678 //
12679 // This will generate a signed flags result. This should be ok
12680 // since any compare to a zero should be eq/neq.
12681 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12682 match(Set cr (CmpP src zero));
12684 format %{ "TEST $src,$src" %}
12685 opcode(0x85);
12686 ins_encode( OpcP, RegReg( src, src ) );
12687 ins_pipe( ialu_cr_reg_imm );
12688 %}
12690 // Cisc-spilled version of testP_reg
12691 // This will generate a signed flags result. This should be ok
12692 // since any compare to a zero should be eq/neq.
12693 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12694 match(Set cr (CmpP (LoadP op) zero));
12696 format %{ "TEST $op,0xFFFFFFFF" %}
12697 ins_cost(500);
12698 opcode(0xF7); /* Opcode F7 /0 */
12699 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12700 ins_pipe( ialu_cr_reg_imm );
12701 %}
12703 // Yanked all unsigned pointer compare operations.
12704 // Pointer compares are done with CmpP which is already unsigned.
12706 //----------Max and Min--------------------------------------------------------
12707 // Min Instructions
12708 ////
12709 // *** Min and Max using the conditional move are slower than the
12710 // *** branch version on a Pentium III.
12711 // // Conditional move for min
12712 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12713 // effect( USE_DEF op2, USE op1, USE cr );
12714 // format %{ "CMOVlt $op2,$op1\t! min" %}
12715 // opcode(0x4C,0x0F);
12716 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12717 // ins_pipe( pipe_cmov_reg );
12718 //%}
12719 //
12720 //// Min Register with Register (P6 version)
12721 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12722 // predicate(VM_Version::supports_cmov() );
12723 // match(Set op2 (MinI op1 op2));
12724 // ins_cost(200);
12725 // expand %{
12726 // eFlagsReg cr;
12727 // compI_eReg(cr,op1,op2);
12728 // cmovI_reg_lt(op2,op1,cr);
12729 // %}
12730 //%}
12732 // Min Register with Register (generic version)
12733 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12734 match(Set dst (MinI dst src));
12735 effect(KILL flags);
12736 ins_cost(300);
12738 format %{ "MIN $dst,$src" %}
12739 opcode(0xCC);
12740 ins_encode( min_enc(dst,src) );
12741 ins_pipe( pipe_slow );
12742 %}
12744 // Max Register with Register
12745 // *** Min and Max using the conditional move are slower than the
12746 // *** branch version on a Pentium III.
12747 // // Conditional move for max
12748 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12749 // effect( USE_DEF op2, USE op1, USE cr );
12750 // format %{ "CMOVgt $op2,$op1\t! max" %}
12751 // opcode(0x4F,0x0F);
12752 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12753 // ins_pipe( pipe_cmov_reg );
12754 //%}
12755 //
12756 // // Max Register with Register (P6 version)
12757 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
12758 // predicate(VM_Version::supports_cmov() );
12759 // match(Set op2 (MaxI op1 op2));
12760 // ins_cost(200);
12761 // expand %{
12762 // eFlagsReg cr;
12763 // compI_eReg(cr,op1,op2);
12764 // cmovI_reg_gt(op2,op1,cr);
12765 // %}
12766 //%}
12768 // Max Register with Register (generic version)
12769 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12770 match(Set dst (MaxI dst src));
12771 effect(KILL flags);
12772 ins_cost(300);
12774 format %{ "MAX $dst,$src" %}
12775 opcode(0xCC);
12776 ins_encode( max_enc(dst,src) );
12777 ins_pipe( pipe_slow );
12778 %}
12780 // ============================================================================
12781 // Counted Loop limit node which represents exact final iterator value.
12782 // Note: the resulting value should fit into integer range since
12783 // counted loops have limit check on overflow.
12784 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
12785 match(Set limit (LoopLimit (Binary init limit) stride));
12786 effect(TEMP limit_hi, TEMP tmp, KILL flags);
12787 ins_cost(300);
12789 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
12790 ins_encode %{
12791 int strd = (int)$stride$$constant;
12792 assert(strd != 1 && strd != -1, "sanity");
12793 int m1 = (strd > 0) ? 1 : -1;
12794 // Convert limit to long (EAX:EDX)
12795 __ cdql();
12796 // Convert init to long (init:tmp)
12797 __ movl($tmp$$Register, $init$$Register);
12798 __ sarl($tmp$$Register, 31);
12799 // $limit - $init
12800 __ subl($limit$$Register, $init$$Register);
12801 __ sbbl($limit_hi$$Register, $tmp$$Register);
12802 // + ($stride - 1)
12803 if (strd > 0) {
12804 __ addl($limit$$Register, (strd - 1));
12805 __ adcl($limit_hi$$Register, 0);
12806 __ movl($tmp$$Register, strd);
12807 } else {
12808 __ addl($limit$$Register, (strd + 1));
12809 __ adcl($limit_hi$$Register, -1);
12810 __ lneg($limit_hi$$Register, $limit$$Register);
12811 __ movl($tmp$$Register, -strd);
12812 }
12813 // signed devision: (EAX:EDX) / pos_stride
12814 __ idivl($tmp$$Register);
12815 if (strd < 0) {
12816 // restore sign
12817 __ negl($tmp$$Register);
12818 }
12819 // (EAX) * stride
12820 __ mull($tmp$$Register);
12821 // + init (ignore upper bits)
12822 __ addl($limit$$Register, $init$$Register);
12823 %}
12824 ins_pipe( pipe_slow );
12825 %}
12827 // ============================================================================
12828 // Branch Instructions
12829 // Jump Table
12830 instruct jumpXtnd(eRegI switch_val) %{
12831 match(Jump switch_val);
12832 ins_cost(350);
12833 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
12834 ins_encode %{
12835 // Jump to Address(table_base + switch_reg)
12836 Address index(noreg, $switch_val$$Register, Address::times_1);
12837 __ jump(ArrayAddress($constantaddress, index));
12838 %}
12839 ins_pipe(pipe_jmp);
12840 %}
12842 // Jump Direct - Label defines a relative address from JMP+1
12843 instruct jmpDir(label labl) %{
12844 match(Goto);
12845 effect(USE labl);
12847 ins_cost(300);
12848 format %{ "JMP $labl" %}
12849 size(5);
12850 ins_encode %{
12851 Label* L = $labl$$label;
12852 __ jmp(*L, false); // Always long jump
12853 %}
12854 ins_pipe( pipe_jmp );
12855 %}
12857 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12858 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12859 match(If cop cr);
12860 effect(USE labl);
12862 ins_cost(300);
12863 format %{ "J$cop $labl" %}
12864 size(6);
12865 ins_encode %{
12866 Label* L = $labl$$label;
12867 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12868 %}
12869 ins_pipe( pipe_jcc );
12870 %}
12872 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12873 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12874 match(CountedLoopEnd cop cr);
12875 effect(USE labl);
12877 ins_cost(300);
12878 format %{ "J$cop $labl\t# Loop end" %}
12879 size(6);
12880 ins_encode %{
12881 Label* L = $labl$$label;
12882 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12883 %}
12884 ins_pipe( pipe_jcc );
12885 %}
12887 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12888 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12889 match(CountedLoopEnd cop cmp);
12890 effect(USE labl);
12892 ins_cost(300);
12893 format %{ "J$cop,u $labl\t# Loop end" %}
12894 size(6);
12895 ins_encode %{
12896 Label* L = $labl$$label;
12897 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12898 %}
12899 ins_pipe( pipe_jcc );
12900 %}
12902 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12903 match(CountedLoopEnd cop cmp);
12904 effect(USE labl);
12906 ins_cost(200);
12907 format %{ "J$cop,u $labl\t# Loop end" %}
12908 size(6);
12909 ins_encode %{
12910 Label* L = $labl$$label;
12911 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12912 %}
12913 ins_pipe( pipe_jcc );
12914 %}
12916 // Jump Direct Conditional - using unsigned comparison
12917 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12918 match(If cop cmp);
12919 effect(USE labl);
12921 ins_cost(300);
12922 format %{ "J$cop,u $labl" %}
12923 size(6);
12924 ins_encode %{
12925 Label* L = $labl$$label;
12926 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12927 %}
12928 ins_pipe(pipe_jcc);
12929 %}
12931 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12932 match(If cop cmp);
12933 effect(USE labl);
12935 ins_cost(200);
12936 format %{ "J$cop,u $labl" %}
12937 size(6);
12938 ins_encode %{
12939 Label* L = $labl$$label;
12940 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12941 %}
12942 ins_pipe(pipe_jcc);
12943 %}
12945 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12946 match(If cop cmp);
12947 effect(USE labl);
12949 ins_cost(200);
12950 format %{ $$template
12951 if ($cop$$cmpcode == Assembler::notEqual) {
12952 $$emit$$"JP,u $labl\n\t"
12953 $$emit$$"J$cop,u $labl"
12954 } else {
12955 $$emit$$"JP,u done\n\t"
12956 $$emit$$"J$cop,u $labl\n\t"
12957 $$emit$$"done:"
12958 }
12959 %}
12960 ins_encode %{
12961 Label* l = $labl$$label;
12962 if ($cop$$cmpcode == Assembler::notEqual) {
12963 __ jcc(Assembler::parity, *l, false);
12964 __ jcc(Assembler::notEqual, *l, false);
12965 } else if ($cop$$cmpcode == Assembler::equal) {
12966 Label done;
12967 __ jccb(Assembler::parity, done);
12968 __ jcc(Assembler::equal, *l, false);
12969 __ bind(done);
12970 } else {
12971 ShouldNotReachHere();
12972 }
12973 %}
12974 ins_pipe(pipe_jcc);
12975 %}
12977 // ============================================================================
12978 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12979 // array for an instance of the superklass. Set a hidden internal cache on a
12980 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12981 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12982 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12983 match(Set result (PartialSubtypeCheck sub super));
12984 effect( KILL rcx, KILL cr );
12986 ins_cost(1100); // slightly larger than the next version
12987 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12988 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12989 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12990 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12991 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12992 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12993 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12994 "miss:\t" %}
12996 opcode(0x1); // Force a XOR of EDI
12997 ins_encode( enc_PartialSubtypeCheck() );
12998 ins_pipe( pipe_slow );
12999 %}
13001 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
13002 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
13003 effect( KILL rcx, KILL result );
13005 ins_cost(1000);
13006 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
13007 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
13008 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
13009 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
13010 "JNE,s miss\t\t# Missed: flags NZ\n\t"
13011 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
13012 "miss:\t" %}
13014 opcode(0x0); // No need to XOR EDI
13015 ins_encode( enc_PartialSubtypeCheck() );
13016 ins_pipe( pipe_slow );
13017 %}
13019 // ============================================================================
13020 // Branch Instructions -- short offset versions
13021 //
13022 // These instructions are used to replace jumps of a long offset (the default
13023 // match) with jumps of a shorter offset. These instructions are all tagged
13024 // with the ins_short_branch attribute, which causes the ADLC to suppress the
13025 // match rules in general matching. Instead, the ADLC generates a conversion
13026 // method in the MachNode which can be used to do in-place replacement of the
13027 // long variant with the shorter variant. The compiler will determine if a
13028 // branch can be taken by the is_short_branch_offset() predicate in the machine
13029 // specific code section of the file.
13031 // Jump Direct - Label defines a relative address from JMP+1
13032 instruct jmpDir_short(label labl) %{
13033 match(Goto);
13034 effect(USE labl);
13036 ins_cost(300);
13037 format %{ "JMP,s $labl" %}
13038 size(2);
13039 ins_encode %{
13040 Label* L = $labl$$label;
13041 __ jmpb(*L);
13042 %}
13043 ins_pipe( pipe_jmp );
13044 ins_short_branch(1);
13045 %}
13047 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13048 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
13049 match(If cop cr);
13050 effect(USE labl);
13052 ins_cost(300);
13053 format %{ "J$cop,s $labl" %}
13054 size(2);
13055 ins_encode %{
13056 Label* L = $labl$$label;
13057 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13058 %}
13059 ins_pipe( pipe_jcc );
13060 ins_short_branch(1);
13061 %}
13063 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13064 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
13065 match(CountedLoopEnd cop cr);
13066 effect(USE labl);
13068 ins_cost(300);
13069 format %{ "J$cop,s $labl\t# Loop end" %}
13070 size(2);
13071 ins_encode %{
13072 Label* L = $labl$$label;
13073 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13074 %}
13075 ins_pipe( pipe_jcc );
13076 ins_short_branch(1);
13077 %}
13079 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13080 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13081 match(CountedLoopEnd cop cmp);
13082 effect(USE labl);
13084 ins_cost(300);
13085 format %{ "J$cop,us $labl\t# Loop end" %}
13086 size(2);
13087 ins_encode %{
13088 Label* L = $labl$$label;
13089 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13090 %}
13091 ins_pipe( pipe_jcc );
13092 ins_short_branch(1);
13093 %}
13095 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13096 match(CountedLoopEnd cop cmp);
13097 effect(USE labl);
13099 ins_cost(300);
13100 format %{ "J$cop,us $labl\t# Loop end" %}
13101 size(2);
13102 ins_encode %{
13103 Label* L = $labl$$label;
13104 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13105 %}
13106 ins_pipe( pipe_jcc );
13107 ins_short_branch(1);
13108 %}
13110 // Jump Direct Conditional - using unsigned comparison
13111 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13112 match(If cop cmp);
13113 effect(USE labl);
13115 ins_cost(300);
13116 format %{ "J$cop,us $labl" %}
13117 size(2);
13118 ins_encode %{
13119 Label* L = $labl$$label;
13120 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13121 %}
13122 ins_pipe( pipe_jcc );
13123 ins_short_branch(1);
13124 %}
13126 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13127 match(If cop cmp);
13128 effect(USE labl);
13130 ins_cost(300);
13131 format %{ "J$cop,us $labl" %}
13132 size(2);
13133 ins_encode %{
13134 Label* L = $labl$$label;
13135 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13136 %}
13137 ins_pipe( pipe_jcc );
13138 ins_short_branch(1);
13139 %}
13141 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
13142 match(If cop cmp);
13143 effect(USE labl);
13145 ins_cost(300);
13146 format %{ $$template
13147 if ($cop$$cmpcode == Assembler::notEqual) {
13148 $$emit$$"JP,u,s $labl\n\t"
13149 $$emit$$"J$cop,u,s $labl"
13150 } else {
13151 $$emit$$"JP,u,s done\n\t"
13152 $$emit$$"J$cop,u,s $labl\n\t"
13153 $$emit$$"done:"
13154 }
13155 %}
13156 size(4);
13157 ins_encode %{
13158 Label* l = $labl$$label;
13159 if ($cop$$cmpcode == Assembler::notEqual) {
13160 __ jccb(Assembler::parity, *l);
13161 __ jccb(Assembler::notEqual, *l);
13162 } else if ($cop$$cmpcode == Assembler::equal) {
13163 Label done;
13164 __ jccb(Assembler::parity, done);
13165 __ jccb(Assembler::equal, *l);
13166 __ bind(done);
13167 } else {
13168 ShouldNotReachHere();
13169 }
13170 %}
13171 ins_pipe(pipe_jcc);
13172 ins_short_branch(1);
13173 %}
13175 // ============================================================================
13176 // Long Compare
13177 //
13178 // Currently we hold longs in 2 registers. Comparing such values efficiently
13179 // is tricky. The flavor of compare used depends on whether we are testing
13180 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
13181 // The GE test is the negated LT test. The LE test can be had by commuting
13182 // the operands (yielding a GE test) and then negating; negate again for the
13183 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
13184 // NE test is negated from that.
13186 // Due to a shortcoming in the ADLC, it mixes up expressions like:
13187 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
13188 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
13189 // are collapsed internally in the ADLC's dfa-gen code. The match for
13190 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
13191 // foo match ends up with the wrong leaf. One fix is to not match both
13192 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
13193 // both forms beat the trinary form of long-compare and both are very useful
13194 // on Intel which has so few registers.
13196 // Manifest a CmpL result in an integer register. Very painful.
13197 // This is the test to avoid.
13198 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
13199 match(Set dst (CmpL3 src1 src2));
13200 effect( KILL flags );
13201 ins_cost(1000);
13202 format %{ "XOR $dst,$dst\n\t"
13203 "CMP $src1.hi,$src2.hi\n\t"
13204 "JLT,s m_one\n\t"
13205 "JGT,s p_one\n\t"
13206 "CMP $src1.lo,$src2.lo\n\t"
13207 "JB,s m_one\n\t"
13208 "JEQ,s done\n"
13209 "p_one:\tINC $dst\n\t"
13210 "JMP,s done\n"
13211 "m_one:\tDEC $dst\n"
13212 "done:" %}
13213 ins_encode %{
13214 Label p_one, m_one, done;
13215 __ xorptr($dst$$Register, $dst$$Register);
13216 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
13217 __ jccb(Assembler::less, m_one);
13218 __ jccb(Assembler::greater, p_one);
13219 __ cmpl($src1$$Register, $src2$$Register);
13220 __ jccb(Assembler::below, m_one);
13221 __ jccb(Assembler::equal, done);
13222 __ bind(p_one);
13223 __ incrementl($dst$$Register);
13224 __ jmpb(done);
13225 __ bind(m_one);
13226 __ decrementl($dst$$Register);
13227 __ bind(done);
13228 %}
13229 ins_pipe( pipe_slow );
13230 %}
13232 //======
13233 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13234 // compares. Can be used for LE or GT compares by reversing arguments.
13235 // NOT GOOD FOR EQ/NE tests.
13236 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
13237 match( Set flags (CmpL src zero ));
13238 ins_cost(100);
13239 format %{ "TEST $src.hi,$src.hi" %}
13240 opcode(0x85);
13241 ins_encode( OpcP, RegReg_Hi2( src, src ) );
13242 ins_pipe( ialu_cr_reg_reg );
13243 %}
13245 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13246 // compares. Can be used for LE or GT compares by reversing arguments.
13247 // NOT GOOD FOR EQ/NE tests.
13248 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13249 match( Set flags (CmpL src1 src2 ));
13250 effect( TEMP tmp );
13251 ins_cost(300);
13252 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13253 "MOV $tmp,$src1.hi\n\t"
13254 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
13255 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
13256 ins_pipe( ialu_cr_reg_reg );
13257 %}
13259 // Long compares reg < zero/req OR reg >= zero/req.
13260 // Just a wrapper for a normal branch, plus the predicate test.
13261 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
13262 match(If cmp flags);
13263 effect(USE labl);
13264 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13265 expand %{
13266 jmpCon(cmp,flags,labl); // JLT or JGE...
13267 %}
13268 %}
13270 // Compare 2 longs and CMOVE longs.
13271 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
13272 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13273 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13274 ins_cost(400);
13275 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13276 "CMOV$cmp $dst.hi,$src.hi" %}
13277 opcode(0x0F,0x40);
13278 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13279 ins_pipe( pipe_cmov_reg_long );
13280 %}
13282 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
13283 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13284 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13285 ins_cost(500);
13286 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13287 "CMOV$cmp $dst.hi,$src.hi" %}
13288 opcode(0x0F,0x40);
13289 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13290 ins_pipe( pipe_cmov_reg_long );
13291 %}
13293 // Compare 2 longs and CMOVE ints.
13294 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
13295 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13296 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13297 ins_cost(200);
13298 format %{ "CMOV$cmp $dst,$src" %}
13299 opcode(0x0F,0x40);
13300 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13301 ins_pipe( pipe_cmov_reg );
13302 %}
13304 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
13305 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13306 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13307 ins_cost(250);
13308 format %{ "CMOV$cmp $dst,$src" %}
13309 opcode(0x0F,0x40);
13310 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13311 ins_pipe( pipe_cmov_mem );
13312 %}
13314 // Compare 2 longs and CMOVE ints.
13315 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
13316 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13317 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13318 ins_cost(200);
13319 format %{ "CMOV$cmp $dst,$src" %}
13320 opcode(0x0F,0x40);
13321 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13322 ins_pipe( pipe_cmov_reg );
13323 %}
13325 // Compare 2 longs and CMOVE doubles
13326 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
13327 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13328 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13329 ins_cost(200);
13330 expand %{
13331 fcmovD_regS(cmp,flags,dst,src);
13332 %}
13333 %}
13335 // Compare 2 longs and CMOVE doubles
13336 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{
13337 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13338 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13339 ins_cost(200);
13340 expand %{
13341 fcmovXD_regS(cmp,flags,dst,src);
13342 %}
13343 %}
13345 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
13346 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13347 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13348 ins_cost(200);
13349 expand %{
13350 fcmovF_regS(cmp,flags,dst,src);
13351 %}
13352 %}
13354 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{
13355 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13356 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13357 ins_cost(200);
13358 expand %{
13359 fcmovX_regS(cmp,flags,dst,src);
13360 %}
13361 %}
13363 //======
13364 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13365 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
13366 match( Set flags (CmpL src zero ));
13367 effect(TEMP tmp);
13368 ins_cost(200);
13369 format %{ "MOV $tmp,$src.lo\n\t"
13370 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
13371 ins_encode( long_cmp_flags0( src, tmp ) );
13372 ins_pipe( ialu_reg_reg_long );
13373 %}
13375 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13376 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
13377 match( Set flags (CmpL src1 src2 ));
13378 ins_cost(200+300);
13379 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13380 "JNE,s skip\n\t"
13381 "CMP $src1.hi,$src2.hi\n\t"
13382 "skip:\t" %}
13383 ins_encode( long_cmp_flags1( src1, src2 ) );
13384 ins_pipe( ialu_cr_reg_reg );
13385 %}
13387 // Long compare reg == zero/reg OR reg != zero/reg
13388 // Just a wrapper for a normal branch, plus the predicate test.
13389 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
13390 match(If cmp flags);
13391 effect(USE labl);
13392 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13393 expand %{
13394 jmpCon(cmp,flags,labl); // JEQ or JNE...
13395 %}
13396 %}
13398 // Compare 2 longs and CMOVE longs.
13399 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
13400 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13401 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13402 ins_cost(400);
13403 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13404 "CMOV$cmp $dst.hi,$src.hi" %}
13405 opcode(0x0F,0x40);
13406 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13407 ins_pipe( pipe_cmov_reg_long );
13408 %}
13410 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
13411 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13412 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13413 ins_cost(500);
13414 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13415 "CMOV$cmp $dst.hi,$src.hi" %}
13416 opcode(0x0F,0x40);
13417 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13418 ins_pipe( pipe_cmov_reg_long );
13419 %}
13421 // Compare 2 longs and CMOVE ints.
13422 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
13423 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13424 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13425 ins_cost(200);
13426 format %{ "CMOV$cmp $dst,$src" %}
13427 opcode(0x0F,0x40);
13428 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13429 ins_pipe( pipe_cmov_reg );
13430 %}
13432 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
13433 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13434 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13435 ins_cost(250);
13436 format %{ "CMOV$cmp $dst,$src" %}
13437 opcode(0x0F,0x40);
13438 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13439 ins_pipe( pipe_cmov_mem );
13440 %}
13442 // Compare 2 longs and CMOVE ints.
13443 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
13444 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13445 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13446 ins_cost(200);
13447 format %{ "CMOV$cmp $dst,$src" %}
13448 opcode(0x0F,0x40);
13449 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13450 ins_pipe( pipe_cmov_reg );
13451 %}
13453 // Compare 2 longs and CMOVE doubles
13454 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
13455 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13456 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13457 ins_cost(200);
13458 expand %{
13459 fcmovD_regS(cmp,flags,dst,src);
13460 %}
13461 %}
13463 // Compare 2 longs and CMOVE doubles
13464 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{
13465 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13466 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13467 ins_cost(200);
13468 expand %{
13469 fcmovXD_regS(cmp,flags,dst,src);
13470 %}
13471 %}
13473 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
13474 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13475 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13476 ins_cost(200);
13477 expand %{
13478 fcmovF_regS(cmp,flags,dst,src);
13479 %}
13480 %}
13482 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{
13483 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13484 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13485 ins_cost(200);
13486 expand %{
13487 fcmovX_regS(cmp,flags,dst,src);
13488 %}
13489 %}
13491 //======
13492 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13493 // Same as cmpL_reg_flags_LEGT except must negate src
13494 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
13495 match( Set flags (CmpL src zero ));
13496 effect( TEMP tmp );
13497 ins_cost(300);
13498 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
13499 "CMP $tmp,$src.lo\n\t"
13500 "SBB $tmp,$src.hi\n\t" %}
13501 ins_encode( long_cmp_flags3(src, tmp) );
13502 ins_pipe( ialu_reg_reg_long );
13503 %}
13505 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13506 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
13507 // requires a commuted test to get the same result.
13508 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13509 match( Set flags (CmpL src1 src2 ));
13510 effect( TEMP tmp );
13511 ins_cost(300);
13512 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
13513 "MOV $tmp,$src2.hi\n\t"
13514 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
13515 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
13516 ins_pipe( ialu_cr_reg_reg );
13517 %}
13519 // Long compares reg < zero/req OR reg >= zero/req.
13520 // Just a wrapper for a normal branch, plus the predicate test
13521 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
13522 match(If cmp flags);
13523 effect(USE labl);
13524 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
13525 ins_cost(300);
13526 expand %{
13527 jmpCon(cmp,flags,labl); // JGT or JLE...
13528 %}
13529 %}
13531 // Compare 2 longs and CMOVE longs.
13532 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
13533 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13534 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13535 ins_cost(400);
13536 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13537 "CMOV$cmp $dst.hi,$src.hi" %}
13538 opcode(0x0F,0x40);
13539 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13540 ins_pipe( pipe_cmov_reg_long );
13541 %}
13543 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
13544 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13545 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13546 ins_cost(500);
13547 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13548 "CMOV$cmp $dst.hi,$src.hi+4" %}
13549 opcode(0x0F,0x40);
13550 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13551 ins_pipe( pipe_cmov_reg_long );
13552 %}
13554 // Compare 2 longs and CMOVE ints.
13555 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
13556 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13557 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13558 ins_cost(200);
13559 format %{ "CMOV$cmp $dst,$src" %}
13560 opcode(0x0F,0x40);
13561 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13562 ins_pipe( pipe_cmov_reg );
13563 %}
13565 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
13566 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13567 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13568 ins_cost(250);
13569 format %{ "CMOV$cmp $dst,$src" %}
13570 opcode(0x0F,0x40);
13571 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13572 ins_pipe( pipe_cmov_mem );
13573 %}
13575 // Compare 2 longs and CMOVE ptrs.
13576 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
13577 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13578 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13579 ins_cost(200);
13580 format %{ "CMOV$cmp $dst,$src" %}
13581 opcode(0x0F,0x40);
13582 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13583 ins_pipe( pipe_cmov_reg );
13584 %}
13586 // Compare 2 longs and CMOVE doubles
13587 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
13588 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13589 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13590 ins_cost(200);
13591 expand %{
13592 fcmovD_regS(cmp,flags,dst,src);
13593 %}
13594 %}
13596 // Compare 2 longs and CMOVE doubles
13597 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{
13598 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13599 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13600 ins_cost(200);
13601 expand %{
13602 fcmovXD_regS(cmp,flags,dst,src);
13603 %}
13604 %}
13606 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13607 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13608 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13609 ins_cost(200);
13610 expand %{
13611 fcmovF_regS(cmp,flags,dst,src);
13612 %}
13613 %}
13616 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{
13617 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13618 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13619 ins_cost(200);
13620 expand %{
13621 fcmovX_regS(cmp,flags,dst,src);
13622 %}
13623 %}
13626 // ============================================================================
13627 // Procedure Call/Return Instructions
13628 // Call Java Static Instruction
13629 // Note: If this code changes, the corresponding ret_addr_offset() and
13630 // compute_padding() functions will have to be adjusted.
13631 instruct CallStaticJavaDirect(method meth) %{
13632 match(CallStaticJava);
13633 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
13634 effect(USE meth);
13636 ins_cost(300);
13637 format %{ "CALL,static " %}
13638 opcode(0xE8); /* E8 cd */
13639 ins_encode( pre_call_FPU,
13640 Java_Static_Call( meth ),
13641 call_epilog,
13642 post_call_FPU );
13643 ins_pipe( pipe_slow );
13644 ins_alignment(4);
13645 %}
13647 // Call Java Static Instruction (method handle version)
13648 // Note: If this code changes, the corresponding ret_addr_offset() and
13649 // compute_padding() functions will have to be adjusted.
13650 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
13651 match(CallStaticJava);
13652 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
13653 effect(USE meth);
13654 // EBP is saved by all callees (for interpreter stack correction).
13655 // We use it here for a similar purpose, in {preserve,restore}_SP.
13657 ins_cost(300);
13658 format %{ "CALL,static/MethodHandle " %}
13659 opcode(0xE8); /* E8 cd */
13660 ins_encode( pre_call_FPU,
13661 preserve_SP,
13662 Java_Static_Call( meth ),
13663 restore_SP,
13664 call_epilog,
13665 post_call_FPU );
13666 ins_pipe( pipe_slow );
13667 ins_alignment(4);
13668 %}
13670 // Call Java Dynamic Instruction
13671 // Note: If this code changes, the corresponding ret_addr_offset() and
13672 // compute_padding() functions will have to be adjusted.
13673 instruct CallDynamicJavaDirect(method meth) %{
13674 match(CallDynamicJava);
13675 effect(USE meth);
13677 ins_cost(300);
13678 format %{ "MOV EAX,(oop)-1\n\t"
13679 "CALL,dynamic" %}
13680 opcode(0xE8); /* E8 cd */
13681 ins_encode( pre_call_FPU,
13682 Java_Dynamic_Call( meth ),
13683 call_epilog,
13684 post_call_FPU );
13685 ins_pipe( pipe_slow );
13686 ins_alignment(4);
13687 %}
13689 // Call Runtime Instruction
13690 instruct CallRuntimeDirect(method meth) %{
13691 match(CallRuntime );
13692 effect(USE meth);
13694 ins_cost(300);
13695 format %{ "CALL,runtime " %}
13696 opcode(0xE8); /* E8 cd */
13697 // Use FFREEs to clear entries in float stack
13698 ins_encode( pre_call_FPU,
13699 FFree_Float_Stack_All,
13700 Java_To_Runtime( meth ),
13701 post_call_FPU );
13702 ins_pipe( pipe_slow );
13703 %}
13705 // Call runtime without safepoint
13706 instruct CallLeafDirect(method meth) %{
13707 match(CallLeaf);
13708 effect(USE meth);
13710 ins_cost(300);
13711 format %{ "CALL_LEAF,runtime " %}
13712 opcode(0xE8); /* E8 cd */
13713 ins_encode( pre_call_FPU,
13714 FFree_Float_Stack_All,
13715 Java_To_Runtime( meth ),
13716 Verify_FPU_For_Leaf, post_call_FPU );
13717 ins_pipe( pipe_slow );
13718 %}
13720 instruct CallLeafNoFPDirect(method meth) %{
13721 match(CallLeafNoFP);
13722 effect(USE meth);
13724 ins_cost(300);
13725 format %{ "CALL_LEAF_NOFP,runtime " %}
13726 opcode(0xE8); /* E8 cd */
13727 ins_encode(Java_To_Runtime(meth));
13728 ins_pipe( pipe_slow );
13729 %}
13732 // Return Instruction
13733 // Remove the return address & jump to it.
13734 instruct Ret() %{
13735 match(Return);
13736 format %{ "RET" %}
13737 opcode(0xC3);
13738 ins_encode(OpcP);
13739 ins_pipe( pipe_jmp );
13740 %}
13742 // Tail Call; Jump from runtime stub to Java code.
13743 // Also known as an 'interprocedural jump'.
13744 // Target of jump will eventually return to caller.
13745 // TailJump below removes the return address.
13746 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13747 match(TailCall jump_target method_oop );
13748 ins_cost(300);
13749 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13750 opcode(0xFF, 0x4); /* Opcode FF /4 */
13751 ins_encode( OpcP, RegOpc(jump_target) );
13752 ins_pipe( pipe_jmp );
13753 %}
13756 // Tail Jump; remove the return address; jump to target.
13757 // TailCall above leaves the return address around.
13758 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13759 match( TailJump jump_target ex_oop );
13760 ins_cost(300);
13761 format %{ "POP EDX\t# pop return address into dummy\n\t"
13762 "JMP $jump_target " %}
13763 opcode(0xFF, 0x4); /* Opcode FF /4 */
13764 ins_encode( enc_pop_rdx,
13765 OpcP, RegOpc(jump_target) );
13766 ins_pipe( pipe_jmp );
13767 %}
13769 // Create exception oop: created by stack-crawling runtime code.
13770 // Created exception is now available to this handler, and is setup
13771 // just prior to jumping to this handler. No code emitted.
13772 instruct CreateException( eAXRegP ex_oop )
13773 %{
13774 match(Set ex_oop (CreateEx));
13776 size(0);
13777 // use the following format syntax
13778 format %{ "# exception oop is in EAX; no code emitted" %}
13779 ins_encode();
13780 ins_pipe( empty );
13781 %}
13784 // Rethrow exception:
13785 // The exception oop will come in the first argument position.
13786 // Then JUMP (not call) to the rethrow stub code.
13787 instruct RethrowException()
13788 %{
13789 match(Rethrow);
13791 // use the following format syntax
13792 format %{ "JMP rethrow_stub" %}
13793 ins_encode(enc_rethrow);
13794 ins_pipe( pipe_jmp );
13795 %}
13797 // inlined locking and unlocking
13800 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{
13801 match( Set cr (FastLock object box) );
13802 effect( TEMP tmp, TEMP scr );
13803 ins_cost(300);
13804 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %}
13805 ins_encode( Fast_Lock(object,box,tmp,scr) );
13806 ins_pipe( pipe_slow );
13807 %}
13809 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13810 match( Set cr (FastUnlock object box) );
13811 effect( TEMP tmp );
13812 ins_cost(300);
13813 format %{ "FASTUNLOCK $object, $box, $tmp" %}
13814 ins_encode( Fast_Unlock(object,box,tmp) );
13815 ins_pipe( pipe_slow );
13816 %}
13820 // ============================================================================
13821 // Safepoint Instruction
13822 instruct safePoint_poll(eFlagsReg cr) %{
13823 match(SafePoint);
13824 effect(KILL cr);
13826 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13827 // On SPARC that might be acceptable as we can generate the address with
13828 // just a sethi, saving an or. By polling at offset 0 we can end up
13829 // putting additional pressure on the index-0 in the D$. Because of
13830 // alignment (just like the situation at hand) the lower indices tend
13831 // to see more traffic. It'd be better to change the polling address
13832 // to offset 0 of the last $line in the polling page.
13834 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13835 ins_cost(125);
13836 size(6) ;
13837 ins_encode( Safepoint_Poll() );
13838 ins_pipe( ialu_reg_mem );
13839 %}
13841 //----------PEEPHOLE RULES-----------------------------------------------------
13842 // These must follow all instruction definitions as they use the names
13843 // defined in the instructions definitions.
13844 //
13845 // peepmatch ( root_instr_name [preceding_instruction]* );
13846 //
13847 // peepconstraint %{
13848 // (instruction_number.operand_name relational_op instruction_number.operand_name
13849 // [, ...] );
13850 // // instruction numbers are zero-based using left to right order in peepmatch
13851 //
13852 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13853 // // provide an instruction_number.operand_name for each operand that appears
13854 // // in the replacement instruction's match rule
13855 //
13856 // ---------VM FLAGS---------------------------------------------------------
13857 //
13858 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13859 //
13860 // Each peephole rule is given an identifying number starting with zero and
13861 // increasing by one in the order seen by the parser. An individual peephole
13862 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13863 // on the command-line.
13864 //
13865 // ---------CURRENT LIMITATIONS----------------------------------------------
13866 //
13867 // Only match adjacent instructions in same basic block
13868 // Only equality constraints
13869 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13870 // Only one replacement instruction
13871 //
13872 // ---------EXAMPLE----------------------------------------------------------
13873 //
13874 // // pertinent parts of existing instructions in architecture description
13875 // instruct movI(eRegI dst, eRegI src) %{
13876 // match(Set dst (CopyI src));
13877 // %}
13878 //
13879 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13880 // match(Set dst (AddI dst src));
13881 // effect(KILL cr);
13882 // %}
13883 //
13884 // // Change (inc mov) to lea
13885 // peephole %{
13886 // // increment preceeded by register-register move
13887 // peepmatch ( incI_eReg movI );
13888 // // require that the destination register of the increment
13889 // // match the destination register of the move
13890 // peepconstraint ( 0.dst == 1.dst );
13891 // // construct a replacement instruction that sets
13892 // // the destination to ( move's source register + one )
13893 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13894 // %}
13895 //
13896 // Implementation no longer uses movX instructions since
13897 // machine-independent system no longer uses CopyX nodes.
13898 //
13899 // peephole %{
13900 // peepmatch ( incI_eReg movI );
13901 // peepconstraint ( 0.dst == 1.dst );
13902 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13903 // %}
13904 //
13905 // peephole %{
13906 // peepmatch ( decI_eReg movI );
13907 // peepconstraint ( 0.dst == 1.dst );
13908 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13909 // %}
13910 //
13911 // peephole %{
13912 // peepmatch ( addI_eReg_imm movI );
13913 // peepconstraint ( 0.dst == 1.dst );
13914 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13915 // %}
13916 //
13917 // peephole %{
13918 // peepmatch ( addP_eReg_imm movP );
13919 // peepconstraint ( 0.dst == 1.dst );
13920 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13921 // %}
13923 // // Change load of spilled value to only a spill
13924 // instruct storeI(memory mem, eRegI src) %{
13925 // match(Set mem (StoreI mem src));
13926 // %}
13927 //
13928 // instruct loadI(eRegI dst, memory mem) %{
13929 // match(Set dst (LoadI mem));
13930 // %}
13931 //
13932 peephole %{
13933 peepmatch ( loadI storeI );
13934 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13935 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13936 %}
13938 //----------SMARTSPILL RULES---------------------------------------------------
13939 // These must follow all instruction definitions as they use the names
13940 // defined in the instructions definitions.