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src/cpu/ppc/vm/vm_version_ppc.cpp@04ff2f6cd0eb
src/cpu/ppc/vm/vm_version_ppc.cpp
Tue, 17 Oct 2017 12:58:25 +0800
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- aoqi
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- Tue, 17 Oct 2017 12:58:25 +0800
- changeset 7994
- 04ff2f6cd0eb
- parent 7535
- 7ae4e26cb1e0
- child 8856
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1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * Copyright 2012, 2014 SAP AG. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #include "precompiled.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "runtime/java.hpp"
32 #include "runtime/stubCodeGenerator.hpp"
33 #include "utilities/defaultStream.hpp"
34 #include "vm_version_ppc.hpp"
35 #ifdef TARGET_OS_FAMILY_aix
36 # include "os_aix.inline.hpp"
37 #endif
38 #ifdef TARGET_OS_FAMILY_linux
39 # include "os_linux.inline.hpp"
40 #endif
42 # include <sys/sysinfo.h>
44 int VM_Version::_features = VM_Version::unknown_m;
45 int VM_Version::_measured_cache_line_size = 128; // default value
46 const char* VM_Version::_features_str = "";
47 bool VM_Version::_is_determine_features_test_running = false;
50 #define MSG(flag) \
51 if (flag && !FLAG_IS_DEFAULT(flag)) \
52 jio_fprintf(defaultStream::error_stream(), \
53 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
54 " -XX:+" #flag " will be disabled!\n");
56 void VM_Version::initialize() {
58 // Test which instructions are supported and measure cache line size.
59 determine_features();
61 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
62 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
63 if (VM_Version::has_popcntw()) {
64 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
65 } else if (VM_Version::has_cmpb()) {
66 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
67 } else if (VM_Version::has_popcntb()) {
68 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
69 } else {
70 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
71 }
72 }
73 guarantee(PowerArchitecturePPC64 == 0 || PowerArchitecturePPC64 == 5 ||
74 PowerArchitecturePPC64 == 6 || PowerArchitecturePPC64 == 7,
75 "PowerArchitecturePPC64 should be 0, 5, 6 or 7");
77 if (!UseSIGTRAP) {
78 MSG(TrapBasedICMissChecks);
79 MSG(TrapBasedNotEntrantChecks);
80 MSG(TrapBasedNullChecks);
81 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
82 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
83 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
84 }
86 #ifdef COMPILER2
87 if (!UseSIGTRAP) {
88 MSG(TrapBasedRangeChecks);
89 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
90 }
92 // On Power6 test for section size.
93 if (PowerArchitecturePPC64 == 6) {
94 determine_section_size();
95 // TODO: PPC port } else {
96 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
97 }
99 MaxVectorSize = 8;
100 #endif
102 // Create and print feature-string.
103 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
104 jio_snprintf(buf, sizeof(buf),
105 "ppc64%s%s%s%s%s%s%s%s",
106 (has_fsqrt() ? " fsqrt" : ""),
107 (has_isel() ? " isel" : ""),
108 (has_lxarxeh() ? " lxarxeh" : ""),
109 (has_cmpb() ? " cmpb" : ""),
110 //(has_mftgpr()? " mftgpr" : ""),
111 (has_popcntb() ? " popcntb" : ""),
112 (has_popcntw() ? " popcntw" : ""),
113 (has_fcfids() ? " fcfids" : ""),
114 (has_vand() ? " vand" : "")
115 // Make sure number of %s matches num_features!
116 );
117 _features_str = strdup(buf);
118 NOT_PRODUCT(if (Verbose) print_features(););
120 // PPC64 supports 8-byte compare-exchange operations (see
121 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
122 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
123 _supports_cx8 = true;
125 UseSSE = 0; // Only on x86 and x64
127 intx cache_line_size = _measured_cache_line_size;
129 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
131 if (AllocatePrefetchStyle == 4) {
132 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
133 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
134 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
135 } else {
136 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
137 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
138 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
139 }
141 assert(AllocatePrefetchLines > 0, "invalid value");
142 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
143 AllocatePrefetchLines = 1; // Conservative value.
144 }
146 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
147 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
148 }
150 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
152 if (UseCRC32Intrinsics) {
153 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
154 warning("CRC32 intrinsics are not available on this CPU");
155 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
156 }
158 // The AES intrinsic stubs require AES instruction support.
159 if (UseAES) {
160 warning("AES instructions are not available on this CPU");
161 FLAG_SET_DEFAULT(UseAES, false);
162 }
163 if (UseAESIntrinsics) {
164 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
165 warning("AES intrinsics are not available on this CPU");
166 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
167 }
169 if (UseSHA) {
170 warning("SHA instructions are not available on this CPU");
171 FLAG_SET_DEFAULT(UseSHA, false);
172 }
173 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
174 warning("SHA intrinsics are not available on this CPU");
175 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
176 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
177 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
178 }
180 }
182 void VM_Version::print_features() {
183 tty->print_cr("Version: %s cache_line_size = %d", cpu_features(), (int) get_cache_line_size());
184 }
186 #ifdef COMPILER2
187 // Determine section size on power6: If section size is 8 instructions,
188 // there should be a difference between the two testloops of ~15 %. If
189 // no difference is detected the section is assumed to be 32 instructions.
190 void VM_Version::determine_section_size() {
192 int unroll = 80;
194 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
196 // Allocate space for the code.
197 ResourceMark rm;
198 CodeBuffer cb("detect_section_size", code_size, 0);
199 MacroAssembler* a = new MacroAssembler(&cb);
201 uint32_t *code = (uint32_t *)a->pc();
202 // Emit code.
203 void (*test1)() = (void(*)())(void *)a->function_entry();
205 Label l1;
207 a->li(R4, 1);
208 a->sldi(R4, R4, 28);
209 a->b(l1);
210 a->align(CodeEntryAlignment);
212 a->bind(l1);
214 for (int i = 0; i < unroll; i++) {
215 // Schleife 1
216 // ------- sector 0 ------------
217 // ;; 0
218 a->nop(); // 1
219 a->fpnop0(); // 2
220 a->fpnop1(); // 3
221 a->addi(R4,R4, -1); // 4
223 // ;; 1
224 a->nop(); // 5
225 a->fmr(F6, F6); // 6
226 a->fmr(F7, F7); // 7
227 a->endgroup(); // 8
228 // ------- sector 8 ------------
230 // ;; 2
231 a->nop(); // 9
232 a->nop(); // 10
233 a->fmr(F8, F8); // 11
234 a->fmr(F9, F9); // 12
236 // ;; 3
237 a->nop(); // 13
238 a->fmr(F10, F10); // 14
239 a->fmr(F11, F11); // 15
240 a->endgroup(); // 16
241 // -------- sector 16 -------------
243 // ;; 4
244 a->nop(); // 17
245 a->nop(); // 18
246 a->fmr(F15, F15); // 19
247 a->fmr(F16, F16); // 20
249 // ;; 5
250 a->nop(); // 21
251 a->fmr(F17, F17); // 22
252 a->fmr(F18, F18); // 23
253 a->endgroup(); // 24
254 // ------- sector 24 ------------
256 // ;; 6
257 a->nop(); // 25
258 a->nop(); // 26
259 a->fmr(F19, F19); // 27
260 a->fmr(F20, F20); // 28
262 // ;; 7
263 a->nop(); // 29
264 a->fmr(F21, F21); // 30
265 a->fmr(F22, F22); // 31
266 a->brnop0(); // 32
268 // ------- sector 32 ------------
269 }
271 // ;; 8
272 a->cmpdi(CCR0, R4, unroll); // 33
273 a->bge(CCR0, l1); // 34
274 a->blr();
276 // Emit code.
277 void (*test2)() = (void(*)())(void *)a->function_entry();
278 // uint32_t *code = (uint32_t *)a->pc();
280 Label l2;
282 a->li(R4, 1);
283 a->sldi(R4, R4, 28);
284 a->b(l2);
285 a->align(CodeEntryAlignment);
287 a->bind(l2);
289 for (int i = 0; i < unroll; i++) {
290 // Schleife 2
291 // ------- sector 0 ------------
292 // ;; 0
293 a->brnop0(); // 1
294 a->nop(); // 2
295 //a->cmpdi(CCR0, R4, unroll);
296 a->fpnop0(); // 3
297 a->fpnop1(); // 4
298 a->addi(R4,R4, -1); // 5
300 // ;; 1
302 a->nop(); // 6
303 a->fmr(F6, F6); // 7
304 a->fmr(F7, F7); // 8
305 // ------- sector 8 ---------------
307 // ;; 2
308 a->endgroup(); // 9
310 // ;; 3
311 a->nop(); // 10
312 a->nop(); // 11
313 a->fmr(F8, F8); // 12
315 // ;; 4
316 a->fmr(F9, F9); // 13
317 a->nop(); // 14
318 a->fmr(F10, F10); // 15
320 // ;; 5
321 a->fmr(F11, F11); // 16
322 // -------- sector 16 -------------
324 // ;; 6
325 a->endgroup(); // 17
327 // ;; 7
328 a->nop(); // 18
329 a->nop(); // 19
330 a->fmr(F15, F15); // 20
332 // ;; 8
333 a->fmr(F16, F16); // 21
334 a->nop(); // 22
335 a->fmr(F17, F17); // 23
337 // ;; 9
338 a->fmr(F18, F18); // 24
339 // -------- sector 24 -------------
341 // ;; 10
342 a->endgroup(); // 25
344 // ;; 11
345 a->nop(); // 26
346 a->nop(); // 27
347 a->fmr(F19, F19); // 28
349 // ;; 12
350 a->fmr(F20, F20); // 29
351 a->nop(); // 30
352 a->fmr(F21, F21); // 31
354 // ;; 13
355 a->fmr(F22, F22); // 32
356 }
358 // -------- sector 32 -------------
359 // ;; 14
360 a->cmpdi(CCR0, R4, unroll); // 33
361 a->bge(CCR0, l2); // 34
363 a->blr();
364 uint32_t *code_end = (uint32_t *)a->pc();
365 a->flush();
367 double loop1_seconds,loop2_seconds, rel_diff;
368 uint64_t start1, stop1;
370 start1 = os::current_thread_cpu_time(false);
371 (*test1)();
372 stop1 = os::current_thread_cpu_time(false);
373 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
376 start1 = os::current_thread_cpu_time(false);
377 (*test2)();
378 stop1 = os::current_thread_cpu_time(false);
380 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
382 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
384 if (PrintAssembly) {
385 ttyLocker ttyl;
386 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
387 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
388 tty->print_cr("Time loop1 :%f", loop1_seconds);
389 tty->print_cr("Time loop2 :%f", loop2_seconds);
390 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
392 if (rel_diff > 12.0) {
393 tty->print_cr("Section Size 8 Instructions");
394 } else{
395 tty->print_cr("Section Size 32 Instructions or Power5");
396 }
397 }
399 #if 0 // TODO: PPC port
400 // Set sector size (if not set explicitly).
401 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
402 if (rel_diff > 12.0) {
403 PdScheduling::power6SectorSize = 0x20;
404 } else {
405 PdScheduling::power6SectorSize = 0x80;
406 }
407 } else if (Power6SectorSize128PPC64) {
408 PdScheduling::power6SectorSize = 0x80;
409 } else {
410 PdScheduling::power6SectorSize = 0x20;
411 }
412 #endif
413 if (UsePower6SchedulerPPC64) Unimplemented();
414 }
415 #endif // COMPILER2
417 void VM_Version::determine_features() {
418 #if defined(ABI_ELFv2)
419 const int code_size = (num_features+1+2*7)*BytesPerInstWord; // TODO(asmundak): calculation is incorrect.
420 #else
421 // 7 InstWords for each call (function descriptor + blr instruction).
422 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
423 #endif
424 int features = 0;
426 // create test area
427 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
428 char test_area[BUFFER_SIZE];
429 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
431 // Allocate space for the code.
432 ResourceMark rm;
433 CodeBuffer cb("detect_cpu_features", code_size, 0);
434 MacroAssembler* a = new MacroAssembler(&cb);
436 // Must be set to true so we can generate the test code.
437 _features = VM_Version::all_features_m;
439 // Emit code.
440 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
441 uint32_t *code = (uint32_t *)a->pc();
442 // Don't use R0 in ldarx.
443 // Keep R3_ARG1 unmodified, it contains &field (see below).
444 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
445 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
446 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
447 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
448 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
449 a->cmpb(R7, R5, R6); // code[4] -> bcmp
450 //a->mftgpr(R7, F3); // code[5] -> mftgpr
451 a->popcntb(R7, R5); // code[6] -> popcntb
452 a->popcntw(R7, R5); // code[7] -> popcntw
453 a->fcfids(F3, F4); // code[8] -> fcfids
454 a->vand(VR0, VR0, VR0); // code[9] -> vand
455 a->blr();
457 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
458 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
459 a->dcbz(R3_ARG1); // R3_ARG1 = addr
460 a->blr();
462 uint32_t *code_end = (uint32_t *)a->pc();
463 a->flush();
464 _features = VM_Version::unknown_m;
466 // Print the detection code.
467 if (PrintAssembly) {
468 ttyLocker ttyl;
469 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
470 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
471 }
473 // Measure cache line size.
474 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
475 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
476 int count = 0; // count zeroed bytes
477 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
478 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
479 _measured_cache_line_size = count;
481 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
482 VM_Version::_is_determine_features_test_running = true;
483 (*test)((address)mid_of_test_area, (uint64_t)0);
484 VM_Version::_is_determine_features_test_running = false;
486 // determine which instructions are legal.
487 int feature_cntr = 0;
488 if (code[feature_cntr++]) features |= fsqrt_m;
489 if (code[feature_cntr++]) features |= fsqrts_m;
490 if (code[feature_cntr++]) features |= isel_m;
491 if (code[feature_cntr++]) features |= lxarxeh_m;
492 if (code[feature_cntr++]) features |= cmpb_m;
493 //if(code[feature_cntr++])features |= mftgpr_m;
494 if (code[feature_cntr++]) features |= popcntb_m;
495 if (code[feature_cntr++]) features |= popcntw_m;
496 if (code[feature_cntr++]) features |= fcfids_m;
497 if (code[feature_cntr++]) features |= vand_m;
499 // Print the detection code.
500 if (PrintAssembly) {
501 ttyLocker ttyl;
502 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
503 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
504 }
506 _features = features;
507 }
510 static int saved_features = 0;
512 void VM_Version::allow_all() {
513 saved_features = _features;
514 _features = all_features_m;
515 }
517 void VM_Version::revert() {
518 _features = saved_features;
519 }
