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src/cpu/x86/vm/globals_x86.hpp@04d83ba48607
src/cpu/x86/vm/globals_x86.hpp
Thu, 24 May 2018 17:06:56 +0800
- author
- aoqi
- date
- Thu, 24 May 2018 17:06:56 +0800
- changeset 8604
- 04d83ba48607
- parent 7994
- 04ff2f6cd0eb
- child 9852
- 70aa912cebe5
- permissions
- -rw-r--r--
Merge
1 /*
2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #ifndef CPU_X86_VM_GLOBALS_X86_HPP
26 #define CPU_X86_VM_GLOBALS_X86_HPP
28 #include "utilities/globalDefinitions.hpp"
29 #include "utilities/macros.hpp"
31 // Sets the default values for platform dependent flags used by the runtime system.
32 // (see globals.hpp)
34 define_pd_global(bool, ConvertSleepToYield, true);
35 define_pd_global(bool, ShareVtableStubs, true);
36 define_pd_global(bool, CountInterpCalls, true);
37 define_pd_global(bool, NeedsDeoptSuspend, false); // only register window machines need this
39 define_pd_global(bool, ImplicitNullChecks, true); // Generate code for implicit null checks
40 define_pd_global(bool, TrapBasedNullChecks, false); // Not needed on x86.
41 define_pd_global(bool, UncommonNullCast, true); // Uncommon-trap NULLs passed to check cast
43 // See 4827828 for this change. There is no globals_core_i486.hpp. I can't
44 // assign a different value for C2 without touching a number of files. Use
45 // #ifdef to minimize the change as it's late in Mantis. -- FIXME.
46 // c1 doesn't have this problem because the fix to 4858033 assures us
47 // the the vep is aligned at CodeEntryAlignment whereas c2 only aligns
48 // the uep and the vep doesn't get real alignment but just slops on by
49 // only assured that the entry instruction meets the 5 byte size requirement.
50 #ifdef COMPILER2
51 define_pd_global(intx, CodeEntryAlignment, 32);
52 #else
53 define_pd_global(intx, CodeEntryAlignment, 16);
54 #endif // COMPILER2
55 define_pd_global(intx, OptoLoopAlignment, 16);
56 define_pd_global(intx, InlineFrequencyCount, 100);
57 define_pd_global(intx, InlineSmallCode, 1000);
59 define_pd_global(intx, StackYellowPages, NOT_WINDOWS(2) WINDOWS_ONLY(3));
60 define_pd_global(intx, StackRedPages, 1);
61 #ifdef AMD64
62 // Very large C++ stack frames using solaris-amd64 optimized builds
63 // due to lack of optimization caused by C++ compiler bugs
64 define_pd_global(intx, StackShadowPages, NOT_WIN64(20) WIN64_ONLY(6) DEBUG_ONLY(+2));
65 #else
66 define_pd_global(intx, StackShadowPages, 4 DEBUG_ONLY(+5));
67 #endif // AMD64
69 define_pd_global(intx, PreInflateSpin, 10);
71 define_pd_global(bool, RewriteBytecodes, true);
72 define_pd_global(bool, RewriteFrequentPairs, true);
74 #ifdef _ALLBSD_SOURCE
75 define_pd_global(bool, UseMembar, true);
76 #else
77 define_pd_global(bool, UseMembar, false);
78 #endif
80 // GC Ergo Flags
81 define_pd_global(uintx, CMSYoungGenPerWorker, 64*M); // default max size of CMS young gen, per GC worker thread
83 define_pd_global(uintx, TypeProfileLevel, 111);
85 define_pd_global(bool, PreserveFramePointer, false);
87 #define ARCH_FLAGS(develop, product, diagnostic, experimental, notproduct) \
88 \
89 develop(bool, IEEEPrecision, true, \
90 "Enables IEEE precision (for INTEL only)") \
91 \
92 product(intx, FenceInstruction, 0, \
93 "(Unsafe,Unstable) Experimental") \
94 \
95 product(intx, ReadPrefetchInstr, 0, \
96 "Prefetch instruction to prefetch ahead") \
97 \
98 product(bool, UseStoreImmI16, true, \
99 "Use store immediate 16-bits value instruction on x86") \
100 \
101 product(intx, UseAVX, 99, \
102 "Highest supported AVX instructions set on x86/x64") \
103 \
104 product(bool, UseCLMUL, false, \
105 "Control whether CLMUL instructions can be used on x86/x64") \
106 \
107 diagnostic(bool, UseIncDec, true, \
108 "Use INC, DEC instructions on x86") \
109 \
110 product(bool, UseNewLongLShift, false, \
111 "Use optimized bitwise shift left") \
112 \
113 product(bool, UseAddressNop, false, \
114 "Use '0F 1F [addr]' NOP instructions on x86 cpus") \
115 \
116 product(bool, UseXmmLoadAndClearUpper, true, \
117 "Load low part of XMM register and clear upper part") \
118 \
119 product(bool, UseXmmRegToRegMoveAll, false, \
120 "Copy all XMM register bits when moving value between registers") \
121 \
122 product(bool, UseXmmI2D, false, \
123 "Use SSE2 CVTDQ2PD instruction to convert Integer to Double") \
124 \
125 product(bool, UseXmmI2F, false, \
126 "Use SSE2 CVTDQ2PS instruction to convert Integer to Float") \
127 \
128 product(bool, UseUnalignedLoadStores, false, \
129 "Use SSE2 MOVDQU instruction for Arraycopy") \
130 \
131 product(bool, UseFastStosb, false, \
132 "Use fast-string operation for zeroing: rep stosb") \
133 \
134 /* Use Restricted Transactional Memory for lock eliding */ \
135 product(bool, UseRTMLocking, false, \
136 "Enable RTM lock eliding for inflated locks in compiled code") \
137 \
138 experimental(bool, UseRTMForStackLocks, false, \
139 "Enable RTM lock eliding for stack locks in compiled code") \
140 \
141 product(bool, UseRTMDeopt, false, \
142 "Perform deopt and recompilation based on RTM abort ratio") \
143 \
144 product(uintx, RTMRetryCount, 5, \
145 "Number of RTM retries on lock abort or busy") \
146 \
147 experimental(intx, RTMSpinLoopCount, 100, \
148 "Spin count for lock to become free before RTM retry") \
149 \
150 experimental(intx, RTMAbortThreshold, 1000, \
151 "Calculate abort ratio after this number of aborts") \
152 \
153 experimental(intx, RTMLockingThreshold, 10000, \
154 "Lock count at which to do RTM lock eliding without " \
155 "abort ratio calculation") \
156 \
157 experimental(intx, RTMAbortRatio, 50, \
158 "Lock abort ratio at which to stop use RTM lock eliding") \
159 \
160 experimental(intx, RTMTotalCountIncrRate, 64, \
161 "Increment total RTM attempted lock count once every n times") \
162 \
163 experimental(intx, RTMLockingCalculationDelay, 0, \
164 "Number of milliseconds to wait before start calculating aborts " \
165 "for RTM locking") \
166 \
167 experimental(bool, UseRTMXendForLockBusy, true, \
168 "Use RTM Xend instead of Xabort when lock busy") \
169 \
170 /* assembler */ \
171 product(bool, Use486InstrsOnly, false, \
172 "Use 80486 Compliant instruction subset") \
173 \
174 product(bool, UseCountLeadingZerosInstruction, false, \
175 "Use count leading zeros instruction") \
176 \
177 product(bool, UseCountTrailingZerosInstruction, false, \
178 "Use count trailing zeros instruction") \
179 \
180 product(bool, UseBMI1Instructions, false, \
181 "Use BMI1 instructions") \
182 \
183 product(bool, UseBMI2Instructions, false, \
184 "Use BMI2 instructions")
185 #endif // CPU_X86_VM_GLOBALS_X86_HPP
