Thu, 24 May 2018 17:06:56 +0800
Merge
1 /*
2 * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "code/debugInfoRec.hpp"
28 #include "code/icBuffer.hpp"
29 #include "code/vtableStubs.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "oops/compiledICHolder.hpp"
32 #include "prims/jvmtiRedefineClassesTrace.hpp"
33 #include "runtime/sharedRuntime.hpp"
34 #include "runtime/vframeArray.hpp"
35 #include "vmreg_sparc.inline.hpp"
36 #ifdef COMPILER1
37 #include "c1/c1_Runtime1.hpp"
38 #endif
39 #ifdef COMPILER2
40 #include "opto/runtime.hpp"
41 #endif
42 #ifdef SHARK
43 #include "compiler/compileBroker.hpp"
44 #include "shark/sharkCompiler.hpp"
45 #endif
47 #define __ masm->
50 class RegisterSaver {
52 // Used for saving volatile registers. This is Gregs, Fregs, I/L/O.
53 // The Oregs are problematic. In the 32bit build the compiler can
54 // have O registers live with 64 bit quantities. A window save will
55 // cut the heads off of the registers. We have to do a very extensive
56 // stack dance to save and restore these properly.
58 // Note that the Oregs problem only exists if we block at either a polling
59 // page exception a compiled code safepoint that was not originally a call
60 // or deoptimize following one of these kinds of safepoints.
62 // Lots of registers to save. For all builds, a window save will preserve
63 // the %i and %l registers. For the 32-bit longs-in-two entries and 64-bit
64 // builds a window-save will preserve the %o registers. In the LION build
65 // we need to save the 64-bit %o registers which requires we save them
66 // before the window-save (as then they become %i registers and get their
67 // heads chopped off on interrupt). We have to save some %g registers here
68 // as well.
69 enum {
70 // This frame's save area. Includes extra space for the native call:
71 // vararg's layout space and the like. Briefly holds the caller's
72 // register save area.
73 call_args_area = frame::register_save_words_sp_offset +
74 frame::memory_parameter_word_sp_offset*wordSize,
75 // Make sure save locations are always 8 byte aligned.
76 // can't use round_to because it doesn't produce compile time constant
77 start_of_extra_save_area = ((call_args_area + 7) & ~7),
78 g1_offset = start_of_extra_save_area, // g-regs needing saving
79 g3_offset = g1_offset+8,
80 g4_offset = g3_offset+8,
81 g5_offset = g4_offset+8,
82 o0_offset = g5_offset+8,
83 o1_offset = o0_offset+8,
84 o2_offset = o1_offset+8,
85 o3_offset = o2_offset+8,
86 o4_offset = o3_offset+8,
87 o5_offset = o4_offset+8,
88 start_of_flags_save_area = o5_offset+8,
89 ccr_offset = start_of_flags_save_area,
90 fsr_offset = ccr_offset + 8,
91 d00_offset = fsr_offset+8, // Start of float save area
92 register_save_size = d00_offset+8*32
93 };
96 public:
98 static int Oexception_offset() { return o0_offset; };
99 static int G3_offset() { return g3_offset; };
100 static int G5_offset() { return g5_offset; };
101 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);
102 static void restore_live_registers(MacroAssembler* masm);
104 // During deoptimization only the result register need to be restored
105 // all the other values have already been extracted.
107 static void restore_result_registers(MacroAssembler* masm);
108 };
110 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) {
111 // Record volatile registers as callee-save values in an OopMap so their save locations will be
112 // propagated to the caller frame's RegisterMap during StackFrameStream construction (needed for
113 // deoptimization; see compiledVFrame::create_stack_value). The caller's I, L and O registers
114 // are saved in register windows - I's and L's in the caller's frame and O's in the stub frame
115 // (as the stub's I's) when the runtime routine called by the stub creates its frame.
116 int i;
117 // Always make the frame size 16 byte aligned.
118 int frame_size = round_to(additional_frame_words + register_save_size, 16);
119 // OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words
120 int frame_size_in_slots = frame_size / sizeof(jint);
121 // CodeBlob frame size is in words.
122 *total_frame_words = frame_size / wordSize;
123 // OopMap* map = new OopMap(*total_frame_words, 0);
124 OopMap* map = new OopMap(frame_size_in_slots, 0);
126 #if !defined(_LP64)
128 // Save 64-bit O registers; they will get their heads chopped off on a 'save'.
129 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
130 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
131 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
132 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
133 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
134 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
135 #endif /* _LP64 */
137 __ save(SP, -frame_size, SP);
139 #ifndef _LP64
140 // Reload the 64 bit Oregs. Although they are now Iregs we load them
141 // to Oregs here to avoid interrupts cutting off their heads
143 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
144 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
145 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
146 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
147 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
148 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
150 __ stx(O0, SP, o0_offset+STACK_BIAS);
151 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset + 4)>>2), O0->as_VMReg());
153 __ stx(O1, SP, o1_offset+STACK_BIAS);
155 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset + 4)>>2), O1->as_VMReg());
157 __ stx(O2, SP, o2_offset+STACK_BIAS);
158 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset + 4)>>2), O2->as_VMReg());
160 __ stx(O3, SP, o3_offset+STACK_BIAS);
161 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset + 4)>>2), O3->as_VMReg());
163 __ stx(O4, SP, o4_offset+STACK_BIAS);
164 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset + 4)>>2), O4->as_VMReg());
166 __ stx(O5, SP, o5_offset+STACK_BIAS);
167 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset + 4)>>2), O5->as_VMReg());
168 #endif /* _LP64 */
171 #ifdef _LP64
172 int debug_offset = 0;
173 #else
174 int debug_offset = 4;
175 #endif
176 // Save the G's
177 __ stx(G1, SP, g1_offset+STACK_BIAS);
178 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset + debug_offset)>>2), G1->as_VMReg());
180 __ stx(G3, SP, g3_offset+STACK_BIAS);
181 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset + debug_offset)>>2), G3->as_VMReg());
183 __ stx(G4, SP, g4_offset+STACK_BIAS);
184 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset + debug_offset)>>2), G4->as_VMReg());
186 __ stx(G5, SP, g5_offset+STACK_BIAS);
187 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset + debug_offset)>>2), G5->as_VMReg());
189 // This is really a waste but we'll keep things as they were for now
190 if (true) {
191 #ifndef _LP64
192 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset)>>2), O0->as_VMReg()->next());
193 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset)>>2), O1->as_VMReg()->next());
194 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset)>>2), O2->as_VMReg()->next());
195 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset)>>2), O3->as_VMReg()->next());
196 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset)>>2), O4->as_VMReg()->next());
197 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset)>>2), O5->as_VMReg()->next());
198 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset)>>2), G1->as_VMReg()->next());
199 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset)>>2), G3->as_VMReg()->next());
200 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset)>>2), G4->as_VMReg()->next());
201 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset)>>2), G5->as_VMReg()->next());
202 #endif /* _LP64 */
203 }
206 // Save the flags
207 __ rdccr( G5 );
208 __ stx(G5, SP, ccr_offset+STACK_BIAS);
209 __ stxfsr(SP, fsr_offset+STACK_BIAS);
211 // Save all the FP registers: 32 doubles (32 floats correspond to the 2 halves of the first 16 doubles)
212 int offset = d00_offset;
213 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {
214 FloatRegister f = as_FloatRegister(i);
215 __ stf(FloatRegisterImpl::D, f, SP, offset+STACK_BIAS);
216 // Record as callee saved both halves of double registers (2 float registers).
217 map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), f->as_VMReg());
218 map->set_callee_saved(VMRegImpl::stack2reg((offset + sizeof(float))>>2), f->as_VMReg()->next());
219 offset += sizeof(double);
220 }
222 // And we're done.
224 return map;
225 }
228 // Pop the current frame and restore all the registers that we
229 // saved.
230 void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
232 // Restore all the FP registers
233 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {
234 __ ldf(FloatRegisterImpl::D, SP, d00_offset+i*sizeof(float)+STACK_BIAS, as_FloatRegister(i));
235 }
237 __ ldx(SP, ccr_offset+STACK_BIAS, G1);
238 __ wrccr (G1) ;
240 // Restore the G's
241 // Note that G2 (AKA GThread) must be saved and restored separately.
242 // TODO-FIXME: save and restore some of the other ASRs, viz., %asi and %gsr.
244 __ ldx(SP, g1_offset+STACK_BIAS, G1);
245 __ ldx(SP, g3_offset+STACK_BIAS, G3);
246 __ ldx(SP, g4_offset+STACK_BIAS, G4);
247 __ ldx(SP, g5_offset+STACK_BIAS, G5);
250 #if !defined(_LP64)
251 // Restore the 64-bit O's.
252 __ ldx(SP, o0_offset+STACK_BIAS, O0);
253 __ ldx(SP, o1_offset+STACK_BIAS, O1);
254 __ ldx(SP, o2_offset+STACK_BIAS, O2);
255 __ ldx(SP, o3_offset+STACK_BIAS, O3);
256 __ ldx(SP, o4_offset+STACK_BIAS, O4);
257 __ ldx(SP, o5_offset+STACK_BIAS, O5);
259 // And temporarily place them in TLS
261 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
262 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
263 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
264 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
265 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
266 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
267 #endif /* _LP64 */
269 // Restore flags
271 __ ldxfsr(SP, fsr_offset+STACK_BIAS);
273 __ restore();
275 #if !defined(_LP64)
276 // Now reload the 64bit Oregs after we've restore the window.
277 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
278 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
279 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
280 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
281 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
282 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
283 #endif /* _LP64 */
285 }
287 // Pop the current frame and restore the registers that might be holding
288 // a result.
289 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
291 #if !defined(_LP64)
292 // 32bit build returns longs in G1
293 __ ldx(SP, g1_offset+STACK_BIAS, G1);
295 // Retrieve the 64-bit O's.
296 __ ldx(SP, o0_offset+STACK_BIAS, O0);
297 __ ldx(SP, o1_offset+STACK_BIAS, O1);
298 // and save to TLS
299 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
300 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
301 #endif /* _LP64 */
303 __ ldf(FloatRegisterImpl::D, SP, d00_offset+STACK_BIAS, as_FloatRegister(0));
305 __ restore();
307 #if !defined(_LP64)
308 // Now reload the 64bit Oregs after we've restore the window.
309 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
310 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
311 #endif /* _LP64 */
313 }
315 // Is vector's size (in bytes) bigger than a size saved by default?
316 // 8 bytes FP registers are saved by default on SPARC.
317 bool SharedRuntime::is_wide_vector(int size) {
318 // Note, MaxVectorSize == 8 on SPARC.
319 assert(size <= 8, err_msg_res("%d bytes vectors are not supported", size));
320 return size > 8;
321 }
323 // The java_calling_convention describes stack locations as ideal slots on
324 // a frame with no abi restrictions. Since we must observe abi restrictions
325 // (like the placement of the register window) the slots must be biased by
326 // the following value.
327 static int reg2offset(VMReg r) {
328 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
329 }
331 static VMRegPair reg64_to_VMRegPair(Register r) {
332 VMRegPair ret;
333 if (wordSize == 8) {
334 ret.set2(r->as_VMReg());
335 } else {
336 ret.set_pair(r->successor()->as_VMReg(), r->as_VMReg());
337 }
338 return ret;
339 }
341 // ---------------------------------------------------------------------------
342 // Read the array of BasicTypes from a signature, and compute where the
343 // arguments should go. Values in the VMRegPair regs array refer to 4-byte (VMRegImpl::stack_slot_size)
344 // quantities. Values less than VMRegImpl::stack0 are registers, those above
345 // refer to 4-byte stack slots. All stack slots are based off of the window
346 // top. VMRegImpl::stack0 refers to the first slot past the 16-word window,
347 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
348 // values 0-63 (up to RegisterImpl::number_of_registers) are the 64-bit
349 // integer registers. Values 64-95 are the (32-bit only) float registers.
350 // Each 32-bit quantity is given its own number, so the integer registers
351 // (in either 32- or 64-bit builds) use 2 numbers. For example, there is
352 // an O0-low and an O0-high. Essentially, all int register numbers are doubled.
354 // Register results are passed in O0-O5, for outgoing call arguments. To
355 // convert to incoming arguments, convert all O's to I's. The regs array
356 // refer to the low and hi 32-bit words of 64-bit registers or stack slots.
357 // If the regs[].second() field is set to VMRegImpl::Bad(), it means it's unused (a
358 // 32-bit value was passed). If both are VMRegImpl::Bad(), it means no value was
359 // passed (used as a placeholder for the other half of longs and doubles in
360 // the 64-bit build). regs[].second() is either VMRegImpl::Bad() or regs[].second() is
361 // regs[].first()+1 (regs[].first() may be misaligned in the C calling convention).
362 // Sparc never passes a value in regs[].second() but not regs[].first() (regs[].first()
363 // == VMRegImpl::Bad() && regs[].second() != VMRegImpl::Bad()) nor unrelated values in the
364 // same VMRegPair.
366 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
367 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
368 // units regardless of build.
371 // ---------------------------------------------------------------------------
372 // The compiled Java calling convention. The Java convention always passes
373 // 64-bit values in adjacent aligned locations (either registers or stack),
374 // floats in float registers and doubles in aligned float pairs. There is
375 // no backing varargs store for values in registers.
376 // In the 32-bit build, longs are passed on the stack (cannot be
377 // passed in I's, because longs in I's get their heads chopped off at
378 // interrupt).
379 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
380 VMRegPair *regs,
381 int total_args_passed,
382 int is_outgoing) {
383 assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers");
385 const int int_reg_max = SPARC_ARGS_IN_REGS_NUM;
386 const int flt_reg_max = 8;
388 int int_reg = 0;
389 int flt_reg = 0;
390 int slot = 0;
392 for (int i = 0; i < total_args_passed; i++) {
393 switch (sig_bt[i]) {
394 case T_INT:
395 case T_SHORT:
396 case T_CHAR:
397 case T_BYTE:
398 case T_BOOLEAN:
399 #ifndef _LP64
400 case T_OBJECT:
401 case T_ARRAY:
402 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
403 #endif // _LP64
404 if (int_reg < int_reg_max) {
405 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
406 regs[i].set1(r->as_VMReg());
407 } else {
408 regs[i].set1(VMRegImpl::stack2reg(slot++));
409 }
410 break;
412 #ifdef _LP64
413 case T_LONG:
414 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half");
415 // fall-through
416 case T_OBJECT:
417 case T_ARRAY:
418 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
419 if (int_reg < int_reg_max) {
420 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
421 regs[i].set2(r->as_VMReg());
422 } else {
423 slot = round_to(slot, 2); // align
424 regs[i].set2(VMRegImpl::stack2reg(slot));
425 slot += 2;
426 }
427 break;
428 #else
429 case T_LONG:
430 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half");
431 // On 32-bit SPARC put longs always on the stack to keep the pressure off
432 // integer argument registers. They should be used for oops.
433 slot = round_to(slot, 2); // align
434 regs[i].set2(VMRegImpl::stack2reg(slot));
435 slot += 2;
436 #endif
437 break;
439 case T_FLOAT:
440 if (flt_reg < flt_reg_max) {
441 FloatRegister r = as_FloatRegister(flt_reg++);
442 regs[i].set1(r->as_VMReg());
443 } else {
444 regs[i].set1(VMRegImpl::stack2reg(slot++));
445 }
446 break;
448 case T_DOUBLE:
449 assert(sig_bt[i+1] == T_VOID, "expecting half");
450 if (round_to(flt_reg, 2) + 1 < flt_reg_max) {
451 flt_reg = round_to(flt_reg, 2); // align
452 FloatRegister r = as_FloatRegister(flt_reg);
453 regs[i].set2(r->as_VMReg());
454 flt_reg += 2;
455 } else {
456 slot = round_to(slot, 2); // align
457 regs[i].set2(VMRegImpl::stack2reg(slot));
458 slot += 2;
459 }
460 break;
462 case T_VOID:
463 regs[i].set_bad(); // Halves of longs & doubles
464 break;
466 default:
467 fatal(err_msg_res("unknown basic type %d", sig_bt[i]));
468 break;
469 }
470 }
472 // retun the amount of stack space these arguments will need.
473 return slot;
474 }
476 // Helper class mostly to avoid passing masm everywhere, and handle
477 // store displacement overflow logic.
478 class AdapterGenerator {
479 MacroAssembler *masm;
480 Register Rdisp;
481 void set_Rdisp(Register r) { Rdisp = r; }
483 void patch_callers_callsite();
485 // base+st_off points to top of argument
486 int arg_offset(const int st_off) { return st_off; }
487 int next_arg_offset(const int st_off) {
488 return st_off - Interpreter::stackElementSize;
489 }
491 // Argument slot values may be loaded first into a register because
492 // they might not fit into displacement.
493 RegisterOrConstant arg_slot(const int st_off);
494 RegisterOrConstant next_arg_slot(const int st_off);
496 // Stores long into offset pointed to by base
497 void store_c2i_long(Register r, Register base,
498 const int st_off, bool is_stack);
499 void store_c2i_object(Register r, Register base,
500 const int st_off);
501 void store_c2i_int(Register r, Register base,
502 const int st_off);
503 void store_c2i_double(VMReg r_2,
504 VMReg r_1, Register base, const int st_off);
505 void store_c2i_float(FloatRegister f, Register base,
506 const int st_off);
508 public:
509 void gen_c2i_adapter(int total_args_passed,
510 // VMReg max_arg,
511 int comp_args_on_stack, // VMRegStackSlots
512 const BasicType *sig_bt,
513 const VMRegPair *regs,
514 Label& skip_fixup);
515 void gen_i2c_adapter(int total_args_passed,
516 // VMReg max_arg,
517 int comp_args_on_stack, // VMRegStackSlots
518 const BasicType *sig_bt,
519 const VMRegPair *regs);
521 AdapterGenerator(MacroAssembler *_masm) : masm(_masm) {}
522 };
525 // Patch the callers callsite with entry to compiled code if it exists.
526 void AdapterGenerator::patch_callers_callsite() {
527 Label L;
528 __ ld_ptr(G5_method, in_bytes(Method::code_offset()), G3_scratch);
529 __ br_null(G3_scratch, false, Assembler::pt, L);
530 __ delayed()->nop();
531 // Call into the VM to patch the caller, then jump to compiled callee
532 __ save_frame(4); // Args in compiled layout; do not blow them
534 // Must save all the live Gregs the list is:
535 // G1: 1st Long arg (32bit build)
536 // G2: global allocated to TLS
537 // G3: used in inline cache check (scratch)
538 // G4: 2nd Long arg (32bit build);
539 // G5: used in inline cache check (Method*)
541 // The longs must go to the stack by hand since in the 32 bit build they can be trashed by window ops.
543 #ifdef _LP64
544 // mov(s,d)
545 __ mov(G1, L1);
546 __ mov(G4, L4);
547 __ mov(G5_method, L5);
548 __ mov(G5_method, O0); // VM needs target method
549 __ mov(I7, O1); // VM needs caller's callsite
550 // Must be a leaf call...
551 // can be very far once the blob has been relocated
552 AddressLiteral dest(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
553 __ relocate(relocInfo::runtime_call_type);
554 __ jumpl_to(dest, O7, O7);
555 __ delayed()->mov(G2_thread, L7_thread_cache);
556 __ mov(L7_thread_cache, G2_thread);
557 __ mov(L1, G1);
558 __ mov(L4, G4);
559 __ mov(L5, G5_method);
560 #else
561 __ stx(G1, FP, -8 + STACK_BIAS);
562 __ stx(G4, FP, -16 + STACK_BIAS);
563 __ mov(G5_method, L5);
564 __ mov(G5_method, O0); // VM needs target method
565 __ mov(I7, O1); // VM needs caller's callsite
566 // Must be a leaf call...
567 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), relocInfo::runtime_call_type);
568 __ delayed()->mov(G2_thread, L7_thread_cache);
569 __ mov(L7_thread_cache, G2_thread);
570 __ ldx(FP, -8 + STACK_BIAS, G1);
571 __ ldx(FP, -16 + STACK_BIAS, G4);
572 __ mov(L5, G5_method);
573 #endif /* _LP64 */
575 __ restore(); // Restore args
576 __ bind(L);
577 }
580 RegisterOrConstant AdapterGenerator::arg_slot(const int st_off) {
581 RegisterOrConstant roc(arg_offset(st_off));
582 return __ ensure_simm13_or_reg(roc, Rdisp);
583 }
585 RegisterOrConstant AdapterGenerator::next_arg_slot(const int st_off) {
586 RegisterOrConstant roc(next_arg_offset(st_off));
587 return __ ensure_simm13_or_reg(roc, Rdisp);
588 }
591 // Stores long into offset pointed to by base
592 void AdapterGenerator::store_c2i_long(Register r, Register base,
593 const int st_off, bool is_stack) {
594 #ifdef _LP64
595 // In V9, longs are given 2 64-bit slots in the interpreter, but the
596 // data is passed in only 1 slot.
597 __ stx(r, base, next_arg_slot(st_off));
598 #else
599 #ifdef COMPILER2
600 // Misaligned store of 64-bit data
601 __ stw(r, base, arg_slot(st_off)); // lo bits
602 __ srlx(r, 32, r);
603 __ stw(r, base, next_arg_slot(st_off)); // hi bits
604 #else
605 if (is_stack) {
606 // Misaligned store of 64-bit data
607 __ stw(r, base, arg_slot(st_off)); // lo bits
608 __ srlx(r, 32, r);
609 __ stw(r, base, next_arg_slot(st_off)); // hi bits
610 } else {
611 __ stw(r->successor(), base, arg_slot(st_off) ); // lo bits
612 __ stw(r , base, next_arg_slot(st_off)); // hi bits
613 }
614 #endif // COMPILER2
615 #endif // _LP64
616 }
618 void AdapterGenerator::store_c2i_object(Register r, Register base,
619 const int st_off) {
620 __ st_ptr (r, base, arg_slot(st_off));
621 }
623 void AdapterGenerator::store_c2i_int(Register r, Register base,
624 const int st_off) {
625 __ st (r, base, arg_slot(st_off));
626 }
628 // Stores into offset pointed to by base
629 void AdapterGenerator::store_c2i_double(VMReg r_2,
630 VMReg r_1, Register base, const int st_off) {
631 #ifdef _LP64
632 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
633 // data is passed in only 1 slot.
634 __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
635 #else
636 // Need to marshal 64-bit value from misaligned Lesp loads
637 __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
638 __ stf(FloatRegisterImpl::S, r_2->as_FloatRegister(), base, arg_slot(st_off) );
639 #endif
640 }
642 void AdapterGenerator::store_c2i_float(FloatRegister f, Register base,
643 const int st_off) {
644 __ stf(FloatRegisterImpl::S, f, base, arg_slot(st_off));
645 }
647 void AdapterGenerator::gen_c2i_adapter(
648 int total_args_passed,
649 // VMReg max_arg,
650 int comp_args_on_stack, // VMRegStackSlots
651 const BasicType *sig_bt,
652 const VMRegPair *regs,
653 Label& L_skip_fixup) {
655 // Before we get into the guts of the C2I adapter, see if we should be here
656 // at all. We've come from compiled code and are attempting to jump to the
657 // interpreter, which means the caller made a static call to get here
658 // (vcalls always get a compiled target if there is one). Check for a
659 // compiled target. If there is one, we need to patch the caller's call.
660 // However we will run interpreted if we come thru here. The next pass
661 // thru the call site will run compiled. If we ran compiled here then
662 // we can (theorectically) do endless i2c->c2i->i2c transitions during
663 // deopt/uncommon trap cycles. If we always go interpreted here then
664 // we can have at most one and don't need to play any tricks to keep
665 // from endlessly growing the stack.
666 //
667 // Actually if we detected that we had an i2c->c2i transition here we
668 // ought to be able to reset the world back to the state of the interpreted
669 // call and not bother building another interpreter arg area. We don't
670 // do that at this point.
672 patch_callers_callsite();
674 __ bind(L_skip_fixup);
676 // Since all args are passed on the stack, total_args_passed*wordSize is the
677 // space we need. Add in varargs area needed by the interpreter. Round up
678 // to stack alignment.
679 const int arg_size = total_args_passed * Interpreter::stackElementSize;
680 const int varargs_area =
681 (frame::varargs_offset - frame::register_save_words)*wordSize;
682 const int extraspace = round_to(arg_size + varargs_area, 2*wordSize);
684 const int bias = STACK_BIAS;
685 const int interp_arg_offset = frame::varargs_offset*wordSize +
686 (total_args_passed-1)*Interpreter::stackElementSize;
688 const Register base = SP;
690 // Make some extra space on the stack.
691 __ sub(SP, __ ensure_simm13_or_reg(extraspace, G3_scratch), SP);
692 set_Rdisp(G3_scratch);
694 // Write the args into the outgoing interpreter space.
695 for (int i = 0; i < total_args_passed; i++) {
696 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias;
697 VMReg r_1 = regs[i].first();
698 VMReg r_2 = regs[i].second();
699 if (!r_1->is_valid()) {
700 assert(!r_2->is_valid(), "");
701 continue;
702 }
703 if (r_1->is_stack()) { // Pretend stack targets are loaded into G1
704 RegisterOrConstant ld_off = reg2offset(r_1) + extraspace + bias;
705 ld_off = __ ensure_simm13_or_reg(ld_off, Rdisp);
706 r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle
707 if (!r_2->is_valid()) __ ld (base, ld_off, G1_scratch);
708 else __ ldx(base, ld_off, G1_scratch);
709 }
711 if (r_1->is_Register()) {
712 Register r = r_1->as_Register()->after_restore();
713 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
714 store_c2i_object(r, base, st_off);
715 } else if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
716 store_c2i_long(r, base, st_off, r_2->is_stack());
717 } else {
718 store_c2i_int(r, base, st_off);
719 }
720 } else {
721 assert(r_1->is_FloatRegister(), "");
722 if (sig_bt[i] == T_FLOAT) {
723 store_c2i_float(r_1->as_FloatRegister(), base, st_off);
724 } else {
725 assert(sig_bt[i] == T_DOUBLE, "wrong type");
726 store_c2i_double(r_2, r_1, base, st_off);
727 }
728 }
729 }
731 // Load the interpreter entry point.
732 __ ld_ptr(G5_method, in_bytes(Method::interpreter_entry_offset()), G3_scratch);
734 // Pass O5_savedSP as an argument to the interpreter.
735 // The interpreter will restore SP to this value before returning.
736 __ add(SP, __ ensure_simm13_or_reg(extraspace, G1), O5_savedSP);
738 __ mov((frame::varargs_offset)*wordSize -
739 1*Interpreter::stackElementSize+bias+BytesPerWord, G1);
740 // Jump to the interpreter just as if interpreter was doing it.
741 __ jmpl(G3_scratch, 0, G0);
742 // Setup Lesp for the call. Cannot actually set Lesp as the current Lesp
743 // (really L0) is in use by the compiled frame as a generic temp. However,
744 // the interpreter does not know where its args are without some kind of
745 // arg pointer being passed in. Pass it in Gargs.
746 __ delayed()->add(SP, G1, Gargs);
747 }
749 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg, Register temp2_reg,
750 address code_start, address code_end,
751 Label& L_ok) {
752 Label L_fail;
753 __ set(ExternalAddress(code_start), temp_reg);
754 __ set(pointer_delta(code_end, code_start, 1), temp2_reg);
755 __ cmp(pc_reg, temp_reg);
756 __ brx(Assembler::lessEqualUnsigned, false, Assembler::pn, L_fail);
757 __ delayed()->add(temp_reg, temp2_reg, temp_reg);
758 __ cmp(pc_reg, temp_reg);
759 __ cmp_and_brx_short(pc_reg, temp_reg, Assembler::lessUnsigned, Assembler::pt, L_ok);
760 __ bind(L_fail);
761 }
763 void AdapterGenerator::gen_i2c_adapter(
764 int total_args_passed,
765 // VMReg max_arg,
766 int comp_args_on_stack, // VMRegStackSlots
767 const BasicType *sig_bt,
768 const VMRegPair *regs) {
770 // Generate an I2C adapter: adjust the I-frame to make space for the C-frame
771 // layout. Lesp was saved by the calling I-frame and will be restored on
772 // return. Meanwhile, outgoing arg space is all owned by the callee
773 // C-frame, so we can mangle it at will. After adjusting the frame size,
774 // hoist register arguments and repack other args according to the compiled
775 // code convention. Finally, end in a jump to the compiled code. The entry
776 // point address is the start of the buffer.
778 // We will only enter here from an interpreted frame and never from after
779 // passing thru a c2i. Azul allowed this but we do not. If we lose the
780 // race and use a c2i we will remain interpreted for the race loser(s).
781 // This removes all sorts of headaches on the x86 side and also eliminates
782 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions.
784 // More detail:
785 // Adapters can be frameless because they do not require the caller
786 // to perform additional cleanup work, such as correcting the stack pointer.
787 // An i2c adapter is frameless because the *caller* frame, which is interpreted,
788 // routinely repairs its own stack pointer (from interpreter_frame_last_sp),
789 // even if a callee has modified the stack pointer.
790 // A c2i adapter is frameless because the *callee* frame, which is interpreted,
791 // routinely repairs its caller's stack pointer (from sender_sp, which is set
792 // up via the senderSP register).
793 // In other words, if *either* the caller or callee is interpreted, we can
794 // get the stack pointer repaired after a call.
795 // This is why c2i and i2c adapters cannot be indefinitely composed.
796 // In particular, if a c2i adapter were to somehow call an i2c adapter,
797 // both caller and callee would be compiled methods, and neither would
798 // clean up the stack pointer changes performed by the two adapters.
799 // If this happens, control eventually transfers back to the compiled
800 // caller, but with an uncorrected stack, causing delayed havoc.
802 if (VerifyAdapterCalls &&
803 (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) {
804 // So, let's test for cascading c2i/i2c adapters right now.
805 // assert(Interpreter::contains($return_addr) ||
806 // StubRoutines::contains($return_addr),
807 // "i2c adapter must return to an interpreter frame");
808 __ block_comment("verify_i2c { ");
809 Label L_ok;
810 if (Interpreter::code() != NULL)
811 range_check(masm, O7, O0, O1,
812 Interpreter::code()->code_start(), Interpreter::code()->code_end(),
813 L_ok);
814 if (StubRoutines::code1() != NULL)
815 range_check(masm, O7, O0, O1,
816 StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(),
817 L_ok);
818 if (StubRoutines::code2() != NULL)
819 range_check(masm, O7, O0, O1,
820 StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(),
821 L_ok);
822 const char* msg = "i2c adapter must return to an interpreter frame";
823 __ block_comment(msg);
824 __ stop(msg);
825 __ bind(L_ok);
826 __ block_comment("} verify_i2ce ");
827 }
829 // As you can see from the list of inputs & outputs there are not a lot
830 // of temp registers to work with: mostly G1, G3 & G4.
832 // Inputs:
833 // G2_thread - TLS
834 // G5_method - Method oop
835 // G4 (Gargs) - Pointer to interpreter's args
836 // O0..O4 - free for scratch
837 // O5_savedSP - Caller's saved SP, to be restored if needed
838 // O6 - Current SP!
839 // O7 - Valid return address
840 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
842 // Outputs:
843 // G2_thread - TLS
844 // O0-O5 - Outgoing args in compiled layout
845 // O6 - Adjusted or restored SP
846 // O7 - Valid return address
847 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
848 // F0-F7 - more outgoing args
851 // Gargs is the incoming argument base, and also an outgoing argument.
852 __ sub(Gargs, BytesPerWord, Gargs);
854 // ON ENTRY TO THE CODE WE ARE MAKING, WE HAVE AN INTERPRETED FRAME
855 // WITH O7 HOLDING A VALID RETURN PC
856 //
857 // | |
858 // : java stack :
859 // | |
860 // +--------------+ <--- start of outgoing args
861 // | receiver | |
862 // : rest of args : |---size is java-arg-words
863 // | | |
864 // +--------------+ <--- O4_args (misaligned) and Lesp if prior is not C2I
865 // | | |
866 // : unused : |---Space for max Java stack, plus stack alignment
867 // | | |
868 // +--------------+ <--- SP + 16*wordsize
869 // | |
870 // : window :
871 // | |
872 // +--------------+ <--- SP
874 // WE REPACK THE STACK. We use the common calling convention layout as
875 // discovered by calling SharedRuntime::calling_convention. We assume it
876 // causes an arbitrary shuffle of memory, which may require some register
877 // temps to do the shuffle. We hope for (and optimize for) the case where
878 // temps are not needed. We may have to resize the stack slightly, in case
879 // we need alignment padding (32-bit interpreter can pass longs & doubles
880 // misaligned, but the compilers expect them aligned).
881 //
882 // | |
883 // : java stack :
884 // | |
885 // +--------------+ <--- start of outgoing args
886 // | pad, align | |
887 // +--------------+ |
888 // | ints, longs, | |
889 // | floats, | |---Outgoing stack args.
890 // : doubles : | First few args in registers.
891 // | | |
892 // +--------------+ <--- SP' + 16*wordsize
893 // | |
894 // : window :
895 // | |
896 // +--------------+ <--- SP'
898 // ON EXIT FROM THE CODE WE ARE MAKING, WE STILL HAVE AN INTERPRETED FRAME
899 // WITH O7 HOLDING A VALID RETURN PC - ITS JUST THAT THE ARGS ARE NOW SETUP
900 // FOR COMPILED CODE AND THE FRAME SLIGHTLY GROWN.
902 // Cut-out for having no stack args. Since up to 6 args are passed
903 // in registers, we will commonly have no stack args.
904 if (comp_args_on_stack > 0) {
905 // Convert VMReg stack slots to words.
906 int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
907 // Round up to miminum stack alignment, in wordSize
908 comp_words_on_stack = round_to(comp_words_on_stack, 2);
909 // Now compute the distance from Lesp to SP. This calculation does not
910 // include the space for total_args_passed because Lesp has not yet popped
911 // the arguments.
912 __ sub(SP, (comp_words_on_stack)*wordSize, SP);
913 }
915 // Now generate the shuffle code. Pick up all register args and move the
916 // rest through G1_scratch.
917 for (int i = 0; i < total_args_passed; i++) {
918 if (sig_bt[i] == T_VOID) {
919 // Longs and doubles are passed in native word order, but misaligned
920 // in the 32-bit build.
921 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
922 continue;
923 }
925 // Pick up 0, 1 or 2 words from Lesp+offset. Assume mis-aligned in the
926 // 32-bit build and aligned in the 64-bit build. Look for the obvious
927 // ldx/lddf optimizations.
929 // Load in argument order going down.
930 const int ld_off = (total_args_passed-i)*Interpreter::stackElementSize;
931 set_Rdisp(G1_scratch);
933 VMReg r_1 = regs[i].first();
934 VMReg r_2 = regs[i].second();
935 if (!r_1->is_valid()) {
936 assert(!r_2->is_valid(), "");
937 continue;
938 }
939 if (r_1->is_stack()) { // Pretend stack targets are loaded into F8/F9
940 r_1 = F8->as_VMReg(); // as part of the load/store shuffle
941 if (r_2->is_valid()) r_2 = r_1->next();
942 }
943 if (r_1->is_Register()) { // Register argument
944 Register r = r_1->as_Register()->after_restore();
945 if (!r_2->is_valid()) {
946 __ ld(Gargs, arg_slot(ld_off), r);
947 } else {
948 #ifdef _LP64
949 // In V9, longs are given 2 64-bit slots in the interpreter, but the
950 // data is passed in only 1 slot.
951 RegisterOrConstant slot = (sig_bt[i] == T_LONG) ?
952 next_arg_slot(ld_off) : arg_slot(ld_off);
953 __ ldx(Gargs, slot, r);
954 #else
955 fatal("longs should be on stack");
956 #endif
957 }
958 } else {
959 assert(r_1->is_FloatRegister(), "");
960 if (!r_2->is_valid()) {
961 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister());
962 } else {
963 #ifdef _LP64
964 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
965 // data is passed in only 1 slot. This code also handles longs that
966 // are passed on the stack, but need a stack-to-stack move through a
967 // spare float register.
968 RegisterOrConstant slot = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ?
969 next_arg_slot(ld_off) : arg_slot(ld_off);
970 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister());
971 #else
972 // Need to marshal 64-bit value from misaligned Lesp loads
973 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister());
974 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister());
975 #endif
976 }
977 }
978 // Was the argument really intended to be on the stack, but was loaded
979 // into F8/F9?
980 if (regs[i].first()->is_stack()) {
981 assert(r_1->as_FloatRegister() == F8, "fix this code");
982 // Convert stack slot to an SP offset
983 int st_off = reg2offset(regs[i].first()) + STACK_BIAS;
984 // Store down the shuffled stack word. Target address _is_ aligned.
985 RegisterOrConstant slot = __ ensure_simm13_or_reg(st_off, Rdisp);
986 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, slot);
987 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, slot);
988 }
989 }
991 // Jump to the compiled code just as if compiled code was doing it.
992 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3);
994 // 6243940 We might end up in handle_wrong_method if
995 // the callee is deoptimized as we race thru here. If that
996 // happens we don't want to take a safepoint because the
997 // caller frame will look interpreted and arguments are now
998 // "compiled" so it is much better to make this transition
999 // invisible to the stack walking code. Unfortunately if
1000 // we try and find the callee by normal means a safepoint
1001 // is possible. So we stash the desired callee in the thread
1002 // and the vm will find there should this case occur.
1003 Address callee_target_addr(G2_thread, JavaThread::callee_target_offset());
1004 __ st_ptr(G5_method, callee_target_addr);
1005 __ jmpl(G3, 0, G0);
1006 __ delayed()->nop();
1007 }
1009 // ---------------------------------------------------------------
1010 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
1011 int total_args_passed,
1012 // VMReg max_arg,
1013 int comp_args_on_stack, // VMRegStackSlots
1014 const BasicType *sig_bt,
1015 const VMRegPair *regs,
1016 AdapterFingerPrint* fingerprint) {
1017 address i2c_entry = __ pc();
1019 AdapterGenerator agen(masm);
1021 agen.gen_i2c_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs);
1024 // -------------------------------------------------------------------------
1025 // Generate a C2I adapter. On entry we know G5 holds the Method*. The
1026 // args start out packed in the compiled layout. They need to be unpacked
1027 // into the interpreter layout. This will almost always require some stack
1028 // space. We grow the current (compiled) stack, then repack the args. We
1029 // finally end in a jump to the generic interpreter entry point. On exit
1030 // from the interpreter, the interpreter will restore our SP (lest the
1031 // compiled code, which relys solely on SP and not FP, get sick).
1033 address c2i_unverified_entry = __ pc();
1034 Label L_skip_fixup;
1035 {
1036 Register R_temp = G1; // another scratch register
1038 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
1040 __ verify_oop(O0);
1041 __ load_klass(O0, G3_scratch);
1043 __ ld_ptr(G5_method, CompiledICHolder::holder_klass_offset(), R_temp);
1044 __ cmp(G3_scratch, R_temp);
1046 Label ok, ok2;
1047 __ brx(Assembler::equal, false, Assembler::pt, ok);
1048 __ delayed()->ld_ptr(G5_method, CompiledICHolder::holder_method_offset(), G5_method);
1049 __ jump_to(ic_miss, G3_scratch);
1050 __ delayed()->nop();
1052 __ bind(ok);
1053 // Method might have been compiled since the call site was patched to
1054 // interpreted if that is the case treat it as a miss so we can get
1055 // the call site corrected.
1056 __ ld_ptr(G5_method, in_bytes(Method::code_offset()), G3_scratch);
1057 __ bind(ok2);
1058 __ br_null(G3_scratch, false, Assembler::pt, L_skip_fixup);
1059 __ delayed()->nop();
1060 __ jump_to(ic_miss, G3_scratch);
1061 __ delayed()->nop();
1063 }
1065 address c2i_entry = __ pc();
1067 agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, L_skip_fixup);
1069 __ flush();
1070 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
1072 }
1074 // Helper function for native calling conventions
1075 static VMReg int_stk_helper( int i ) {
1076 // Bias any stack based VMReg we get by ignoring the window area
1077 // but not the register parameter save area.
1078 //
1079 // This is strange for the following reasons. We'd normally expect
1080 // the calling convention to return an VMReg for a stack slot
1081 // completely ignoring any abi reserved area. C2 thinks of that
1082 // abi area as only out_preserve_stack_slots. This does not include
1083 // the area allocated by the C abi to store down integer arguments
1084 // because the java calling convention does not use it. So
1085 // since c2 assumes that there are only out_preserve_stack_slots
1086 // to bias the optoregs (which impacts VMRegs) when actually referencing any actual stack
1087 // location the c calling convention must add in this bias amount
1088 // to make up for the fact that the out_preserve_stack_slots is
1089 // insufficient for C calls. What a mess. I sure hope those 6
1090 // stack words were worth it on every java call!
1092 // Another way of cleaning this up would be for out_preserve_stack_slots
1093 // to take a parameter to say whether it was C or java calling conventions.
1094 // Then things might look a little better (but not much).
1096 int mem_parm_offset = i - SPARC_ARGS_IN_REGS_NUM;
1097 if( mem_parm_offset < 0 ) {
1098 return as_oRegister(i)->as_VMReg();
1099 } else {
1100 int actual_offset = (mem_parm_offset + frame::memory_parameter_word_sp_offset) * VMRegImpl::slots_per_word;
1101 // Now return a biased offset that will be correct when out_preserve_slots is added back in
1102 return VMRegImpl::stack2reg(actual_offset - SharedRuntime::out_preserve_stack_slots());
1103 }
1104 }
1107 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
1108 VMRegPair *regs,
1109 VMRegPair *regs2,
1110 int total_args_passed) {
1111 assert(regs2 == NULL, "not needed on sparc");
1113 // Return the number of VMReg stack_slots needed for the args.
1114 // This value does not include an abi space (like register window
1115 // save area).
1117 // The native convention is V8 if !LP64
1118 // The LP64 convention is the V9 convention which is slightly more sane.
1120 // We return the amount of VMReg stack slots we need to reserve for all
1121 // the arguments NOT counting out_preserve_stack_slots. Since we always
1122 // have space for storing at least 6 registers to memory we start with that.
1123 // See int_stk_helper for a further discussion.
1124 int max_stack_slots = (frame::varargs_offset * VMRegImpl::slots_per_word) - SharedRuntime::out_preserve_stack_slots();
1126 #ifdef _LP64
1127 // V9 convention: All things "as-if" on double-wide stack slots.
1128 // Hoist any int/ptr/long's in the first 6 to int regs.
1129 // Hoist any flt/dbl's in the first 16 dbl regs.
1130 int j = 0; // Count of actual args, not HALVES
1131 VMRegPair param_array_reg; // location of the argument in the parameter array
1132 for (int i = 0; i < total_args_passed; i++, j++) {
1133 param_array_reg.set_bad();
1134 switch (sig_bt[i]) {
1135 case T_BOOLEAN:
1136 case T_BYTE:
1137 case T_CHAR:
1138 case T_INT:
1139 case T_SHORT:
1140 regs[i].set1(int_stk_helper(j));
1141 break;
1142 case T_LONG:
1143 assert(sig_bt[i+1] == T_VOID, "expecting half");
1144 case T_ADDRESS: // raw pointers, like current thread, for VM calls
1145 case T_ARRAY:
1146 case T_OBJECT:
1147 case T_METADATA:
1148 regs[i].set2(int_stk_helper(j));
1149 break;
1150 case T_FLOAT:
1151 // Per SPARC Compliance Definition 2.4.1, page 3P-12 available here
1152 // http://www.sparc.org/wp-content/uploads/2014/01/SCD.2.4.1.pdf.gz
1153 //
1154 // "When a callee prototype exists, and does not indicate variable arguments,
1155 // floating-point values assigned to locations %sp+BIAS+128 through %sp+BIAS+248
1156 // will be promoted to floating-point registers"
1157 //
1158 // By "promoted" it means that the argument is located in two places, an unused
1159 // spill slot in the "parameter array" (starts at %sp+BIAS+128), and a live
1160 // float register. In most cases, there are 6 or fewer arguments of any type,
1161 // and the standard parameter array slots (%sp+BIAS+128 to %sp+BIAS+176 exclusive)
1162 // serve as shadow slots. Per the spec floating point registers %d6 to %d16
1163 // require slots beyond that (up to %sp+BIAS+248).
1164 //
1165 {
1166 // V9ism: floats go in ODD registers and stack slots
1167 int float_index = 1 + (j << 1);
1168 param_array_reg.set1(VMRegImpl::stack2reg(float_index));
1169 if (j < 16) {
1170 regs[i].set1(as_FloatRegister(float_index)->as_VMReg());
1171 } else {
1172 regs[i] = param_array_reg;
1173 }
1174 }
1175 break;
1176 case T_DOUBLE:
1177 {
1178 assert(sig_bt[i + 1] == T_VOID, "expecting half");
1179 // V9ism: doubles go in EVEN/ODD regs and stack slots
1180 int double_index = (j << 1);
1181 param_array_reg.set2(VMRegImpl::stack2reg(double_index));
1182 if (j < 16) {
1183 regs[i].set2(as_FloatRegister(double_index)->as_VMReg());
1184 } else {
1185 // V9ism: doubles go in EVEN/ODD stack slots
1186 regs[i] = param_array_reg;
1187 }
1188 }
1189 break;
1190 case T_VOID:
1191 regs[i].set_bad();
1192 j--;
1193 break; // Do not count HALVES
1194 default:
1195 ShouldNotReachHere();
1196 }
1197 // Keep track of the deepest parameter array slot.
1198 if (!param_array_reg.first()->is_valid()) {
1199 param_array_reg = regs[i];
1200 }
1201 if (param_array_reg.first()->is_stack()) {
1202 int off = param_array_reg.first()->reg2stack();
1203 if (off > max_stack_slots) max_stack_slots = off;
1204 }
1205 if (param_array_reg.second()->is_stack()) {
1206 int off = param_array_reg.second()->reg2stack();
1207 if (off > max_stack_slots) max_stack_slots = off;
1208 }
1209 }
1211 #else // _LP64
1212 // V8 convention: first 6 things in O-regs, rest on stack.
1213 // Alignment is willy-nilly.
1214 for (int i = 0; i < total_args_passed; i++) {
1215 switch (sig_bt[i]) {
1216 case T_ADDRESS: // raw pointers, like current thread, for VM calls
1217 case T_ARRAY:
1218 case T_BOOLEAN:
1219 case T_BYTE:
1220 case T_CHAR:
1221 case T_FLOAT:
1222 case T_INT:
1223 case T_OBJECT:
1224 case T_METADATA:
1225 case T_SHORT:
1226 regs[i].set1(int_stk_helper(i));
1227 break;
1228 case T_DOUBLE:
1229 case T_LONG:
1230 assert(sig_bt[i + 1] == T_VOID, "expecting half");
1231 regs[i].set_pair(int_stk_helper(i + 1), int_stk_helper(i));
1232 break;
1233 case T_VOID: regs[i].set_bad(); break;
1234 default:
1235 ShouldNotReachHere();
1236 }
1237 if (regs[i].first()->is_stack()) {
1238 int off = regs[i].first()->reg2stack();
1239 if (off > max_stack_slots) max_stack_slots = off;
1240 }
1241 if (regs[i].second()->is_stack()) {
1242 int off = regs[i].second()->reg2stack();
1243 if (off > max_stack_slots) max_stack_slots = off;
1244 }
1245 }
1246 #endif // _LP64
1248 return round_to(max_stack_slots + 1, 2);
1250 }
1253 // ---------------------------------------------------------------------------
1254 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1255 switch (ret_type) {
1256 case T_FLOAT:
1257 __ stf(FloatRegisterImpl::S, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS);
1258 break;
1259 case T_DOUBLE:
1260 __ stf(FloatRegisterImpl::D, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS);
1261 break;
1262 }
1263 }
1265 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1266 switch (ret_type) {
1267 case T_FLOAT:
1268 __ ldf(FloatRegisterImpl::S, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS, F0);
1269 break;
1270 case T_DOUBLE:
1271 __ ldf(FloatRegisterImpl::D, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS, F0);
1272 break;
1273 }
1274 }
1276 // Check and forward and pending exception. Thread is stored in
1277 // L7_thread_cache and possibly NOT in G2_thread. Since this is a native call, there
1278 // is no exception handler. We merely pop this frame off and throw the
1279 // exception in the caller's frame.
1280 static void check_forward_pending_exception(MacroAssembler *masm, Register Rex_oop) {
1281 Label L;
1282 __ br_null(Rex_oop, false, Assembler::pt, L);
1283 __ delayed()->mov(L7_thread_cache, G2_thread); // restore in case we have exception
1284 // Since this is a native call, we *know* the proper exception handler
1285 // without calling into the VM: it's the empty function. Just pop this
1286 // frame and then jump to forward_exception_entry; O7 will contain the
1287 // native caller's return PC.
1288 AddressLiteral exception_entry(StubRoutines::forward_exception_entry());
1289 __ jump_to(exception_entry, G3_scratch);
1290 __ delayed()->restore(); // Pop this frame off.
1291 __ bind(L);
1292 }
1294 // A simple move of integer like type
1295 static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1296 if (src.first()->is_stack()) {
1297 if (dst.first()->is_stack()) {
1298 // stack to stack
1299 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1300 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1301 } else {
1302 // stack to reg
1303 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1304 }
1305 } else if (dst.first()->is_stack()) {
1306 // reg to stack
1307 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1308 } else {
1309 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1310 }
1311 }
1313 // On 64 bit we will store integer like items to the stack as
1314 // 64 bits items (sparc abi) even though java would only store
1315 // 32bits for a parameter. On 32bit it will simply be 32 bits
1316 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
1317 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1318 if (src.first()->is_stack()) {
1319 if (dst.first()->is_stack()) {
1320 // stack to stack
1321 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1322 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1323 } else {
1324 // stack to reg
1325 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1326 }
1327 } else if (dst.first()->is_stack()) {
1328 // reg to stack
1329 // Some compilers (gcc) expect a clean 32 bit value on function entry
1330 __ signx(src.first()->as_Register(), L5);
1331 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1332 } else {
1333 // Some compilers (gcc) expect a clean 32 bit value on function entry
1334 __ signx(src.first()->as_Register(), dst.first()->as_Register());
1335 }
1336 }
1339 static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1340 if (src.first()->is_stack()) {
1341 if (dst.first()->is_stack()) {
1342 // stack to stack
1343 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1344 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1345 } else {
1346 // stack to reg
1347 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1348 }
1349 } else if (dst.first()->is_stack()) {
1350 // reg to stack
1351 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1352 } else {
1353 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1354 }
1355 }
1358 // An oop arg. Must pass a handle not the oop itself
1359 static void object_move(MacroAssembler* masm,
1360 OopMap* map,
1361 int oop_handle_offset,
1362 int framesize_in_slots,
1363 VMRegPair src,
1364 VMRegPair dst,
1365 bool is_receiver,
1366 int* receiver_offset) {
1368 // must pass a handle. First figure out the location we use as a handle
1370 if (src.first()->is_stack()) {
1371 // Oop is already on the stack
1372 Register rHandle = dst.first()->is_stack() ? L5 : dst.first()->as_Register();
1373 __ add(FP, reg2offset(src.first()) + STACK_BIAS, rHandle);
1374 __ ld_ptr(rHandle, 0, L4);
1375 #ifdef _LP64
1376 __ movr( Assembler::rc_z, L4, G0, rHandle );
1377 #else
1378 __ tst( L4 );
1379 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
1380 #endif
1381 if (dst.first()->is_stack()) {
1382 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
1383 }
1384 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1385 if (is_receiver) {
1386 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1387 }
1388 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1389 } else {
1390 // Oop is in an input register pass we must flush it to the stack
1391 const Register rOop = src.first()->as_Register();
1392 const Register rHandle = L5;
1393 int oop_slot = rOop->input_number() * VMRegImpl::slots_per_word + oop_handle_offset;
1394 int offset = oop_slot * VMRegImpl::stack_slot_size;
1395 __ st_ptr(rOop, SP, offset + STACK_BIAS);
1396 if (is_receiver) {
1397 *receiver_offset = offset;
1398 }
1399 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1400 __ add(SP, offset + STACK_BIAS, rHandle);
1401 #ifdef _LP64
1402 __ movr( Assembler::rc_z, rOop, G0, rHandle );
1403 #else
1404 __ tst( rOop );
1405 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
1406 #endif
1408 if (dst.first()->is_stack()) {
1409 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
1410 } else {
1411 __ mov(rHandle, dst.first()->as_Register());
1412 }
1413 }
1414 }
1416 // A float arg may have to do float reg int reg conversion
1417 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1418 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
1420 if (src.first()->is_stack()) {
1421 if (dst.first()->is_stack()) {
1422 // stack to stack the easiest of the bunch
1423 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1424 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1425 } else {
1426 // stack to reg
1427 if (dst.first()->is_Register()) {
1428 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1429 } else {
1430 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
1431 }
1432 }
1433 } else if (dst.first()->is_stack()) {
1434 // reg to stack
1435 if (src.first()->is_Register()) {
1436 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1437 } else {
1438 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
1439 }
1440 } else {
1441 // reg to reg
1442 if (src.first()->is_Register()) {
1443 if (dst.first()->is_Register()) {
1444 // gpr -> gpr
1445 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1446 } else {
1447 // gpr -> fpr
1448 __ st(src.first()->as_Register(), FP, -4 + STACK_BIAS);
1449 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.first()->as_FloatRegister());
1450 }
1451 } else if (dst.first()->is_Register()) {
1452 // fpr -> gpr
1453 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), FP, -4 + STACK_BIAS);
1454 __ ld(FP, -4 + STACK_BIAS, dst.first()->as_Register());
1455 } else {
1456 // fpr -> fpr
1457 // In theory these overlap but the ordering is such that this is likely a nop
1458 if ( src.first() != dst.first()) {
1459 __ fmov(FloatRegisterImpl::S, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
1460 }
1461 }
1462 }
1463 }
1465 static void split_long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1466 VMRegPair src_lo(src.first());
1467 VMRegPair src_hi(src.second());
1468 VMRegPair dst_lo(dst.first());
1469 VMRegPair dst_hi(dst.second());
1470 simple_move32(masm, src_lo, dst_lo);
1471 simple_move32(masm, src_hi, dst_hi);
1472 }
1474 // A long move
1475 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1477 // Do the simple ones here else do two int moves
1478 if (src.is_single_phys_reg() ) {
1479 if (dst.is_single_phys_reg()) {
1480 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1481 } else {
1482 // split src into two separate registers
1483 // Remember hi means hi address or lsw on sparc
1484 // Move msw to lsw
1485 if (dst.second()->is_reg()) {
1486 // MSW -> MSW
1487 __ srax(src.first()->as_Register(), 32, dst.first()->as_Register());
1488 // Now LSW -> LSW
1489 // this will only move lo -> lo and ignore hi
1490 VMRegPair split(dst.second());
1491 simple_move32(masm, src, split);
1492 } else {
1493 VMRegPair split(src.first(), L4->as_VMReg());
1494 // MSW -> MSW (lo ie. first word)
1495 __ srax(src.first()->as_Register(), 32, L4);
1496 split_long_move(masm, split, dst);
1497 }
1498 }
1499 } else if (dst.is_single_phys_reg()) {
1500 if (src.is_adjacent_aligned_on_stack(2)) {
1501 __ ldx(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1502 } else {
1503 // dst is a single reg.
1504 // Remember lo is low address not msb for stack slots
1505 // and lo is the "real" register for registers
1506 // src is
1508 VMRegPair split;
1510 if (src.first()->is_reg()) {
1511 // src.lo (msw) is a reg, src.hi is stk/reg
1512 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> src.lo [the MSW is in the LSW of the reg]
1513 split.set_pair(dst.first(), src.first());
1514 } else {
1515 // msw is stack move to L5
1516 // lsw is stack move to dst.lo (real reg)
1517 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> L5
1518 split.set_pair(dst.first(), L5->as_VMReg());
1519 }
1521 // src.lo -> src.lo/L5, src.hi -> dst.lo (the real reg)
1522 // msw -> src.lo/L5, lsw -> dst.lo
1523 split_long_move(masm, src, split);
1525 // So dst now has the low order correct position the
1526 // msw half
1527 __ sllx(split.first()->as_Register(), 32, L5);
1529 const Register d = dst.first()->as_Register();
1530 __ or3(L5, d, d);
1531 }
1532 } else {
1533 // For LP64 we can probably do better.
1534 split_long_move(masm, src, dst);
1535 }
1536 }
1538 // A double move
1539 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1541 // The painful thing here is that like long_move a VMRegPair might be
1542 // 1: a single physical register
1543 // 2: two physical registers (v8)
1544 // 3: a physical reg [lo] and a stack slot [hi] (v8)
1545 // 4: two stack slots
1547 // Since src is always a java calling convention we know that the src pair
1548 // is always either all registers or all stack (and aligned?)
1550 // in a register [lo] and a stack slot [hi]
1551 if (src.first()->is_stack()) {
1552 if (dst.first()->is_stack()) {
1553 // stack to stack the easiest of the bunch
1554 // ought to be a way to do this where if alignment is ok we use ldd/std when possible
1555 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1556 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
1557 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1558 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1559 } else {
1560 // stack to reg
1561 if (dst.second()->is_stack()) {
1562 // stack -> reg, stack -> stack
1563 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
1564 if (dst.first()->is_Register()) {
1565 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1566 } else {
1567 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
1568 }
1569 // This was missing. (very rare case)
1570 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1571 } else {
1572 // stack -> reg
1573 // Eventually optimize for alignment QQQ
1574 if (dst.first()->is_Register()) {
1575 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1576 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_Register());
1577 } else {
1578 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
1579 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_FloatRegister());
1580 }
1581 }
1582 }
1583 } else if (dst.first()->is_stack()) {
1584 // reg to stack
1585 if (src.first()->is_Register()) {
1586 // Eventually optimize for alignment QQQ
1587 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1588 if (src.second()->is_stack()) {
1589 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
1590 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1591 } else {
1592 __ st(src.second()->as_Register(), SP, reg2offset(dst.second()) + STACK_BIAS);
1593 }
1594 } else {
1595 // fpr to stack
1596 if (src.second()->is_stack()) {
1597 ShouldNotReachHere();
1598 } else {
1599 // Is the stack aligned?
1600 if (reg2offset(dst.first()) & 0x7) {
1601 // No do as pairs
1602 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
1603 __ stf(FloatRegisterImpl::S, src.second()->as_FloatRegister(), SP, reg2offset(dst.second()) + STACK_BIAS);
1604 } else {
1605 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
1606 }
1607 }
1608 }
1609 } else {
1610 // reg to reg
1611 if (src.first()->is_Register()) {
1612 if (dst.first()->is_Register()) {
1613 // gpr -> gpr
1614 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1615 __ mov(src.second()->as_Register(), dst.second()->as_Register());
1616 } else {
1617 // gpr -> fpr
1618 // ought to be able to do a single store
1619 __ stx(src.first()->as_Register(), FP, -8 + STACK_BIAS);
1620 __ stx(src.second()->as_Register(), FP, -4 + STACK_BIAS);
1621 // ought to be able to do a single load
1622 __ ldf(FloatRegisterImpl::S, FP, -8 + STACK_BIAS, dst.first()->as_FloatRegister());
1623 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.second()->as_FloatRegister());
1624 }
1625 } else if (dst.first()->is_Register()) {
1626 // fpr -> gpr
1627 // ought to be able to do a single store
1628 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), FP, -8 + STACK_BIAS);
1629 // ought to be able to do a single load
1630 // REMEMBER first() is low address not LSB
1631 __ ld(FP, -8 + STACK_BIAS, dst.first()->as_Register());
1632 if (dst.second()->is_Register()) {
1633 __ ld(FP, -4 + STACK_BIAS, dst.second()->as_Register());
1634 } else {
1635 __ ld(FP, -4 + STACK_BIAS, L4);
1636 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1637 }
1638 } else {
1639 // fpr -> fpr
1640 // In theory these overlap but the ordering is such that this is likely a nop
1641 if ( src.first() != dst.first()) {
1642 __ fmov(FloatRegisterImpl::D, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
1643 }
1644 }
1645 }
1646 }
1648 // Creates an inner frame if one hasn't already been created, and
1649 // saves a copy of the thread in L7_thread_cache
1650 static void create_inner_frame(MacroAssembler* masm, bool* already_created) {
1651 if (!*already_created) {
1652 __ save_frame(0);
1653 // Save thread in L7 (INNER FRAME); it crosses a bunch of VM calls below
1654 // Don't use save_thread because it smashes G2 and we merely want to save a
1655 // copy
1656 __ mov(G2_thread, L7_thread_cache);
1657 *already_created = true;
1658 }
1659 }
1662 static void save_or_restore_arguments(MacroAssembler* masm,
1663 const int stack_slots,
1664 const int total_in_args,
1665 const int arg_save_area,
1666 OopMap* map,
1667 VMRegPair* in_regs,
1668 BasicType* in_sig_bt) {
1669 // if map is non-NULL then the code should store the values,
1670 // otherwise it should load them.
1671 if (map != NULL) {
1672 // Fill in the map
1673 for (int i = 0; i < total_in_args; i++) {
1674 if (in_sig_bt[i] == T_ARRAY) {
1675 if (in_regs[i].first()->is_stack()) {
1676 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1677 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots));
1678 } else if (in_regs[i].first()->is_Register()) {
1679 map->set_oop(in_regs[i].first());
1680 } else {
1681 ShouldNotReachHere();
1682 }
1683 }
1684 }
1685 }
1687 // Save or restore double word values
1688 int handle_index = 0;
1689 for (int i = 0; i < total_in_args; i++) {
1690 int slot = handle_index + arg_save_area;
1691 int offset = slot * VMRegImpl::stack_slot_size;
1692 if (in_sig_bt[i] == T_LONG && in_regs[i].first()->is_Register()) {
1693 const Register reg = in_regs[i].first()->as_Register();
1694 if (reg->is_global()) {
1695 handle_index += 2;
1696 assert(handle_index <= stack_slots, "overflow");
1697 if (map != NULL) {
1698 __ stx(reg, SP, offset + STACK_BIAS);
1699 } else {
1700 __ ldx(SP, offset + STACK_BIAS, reg);
1701 }
1702 }
1703 } else if (in_sig_bt[i] == T_DOUBLE && in_regs[i].first()->is_FloatRegister()) {
1704 handle_index += 2;
1705 assert(handle_index <= stack_slots, "overflow");
1706 if (map != NULL) {
1707 __ stf(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS);
1708 } else {
1709 __ ldf(FloatRegisterImpl::D, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister());
1710 }
1711 }
1712 }
1713 // Save floats
1714 for (int i = 0; i < total_in_args; i++) {
1715 int slot = handle_index + arg_save_area;
1716 int offset = slot * VMRegImpl::stack_slot_size;
1717 if (in_sig_bt[i] == T_FLOAT && in_regs[i].first()->is_FloatRegister()) {
1718 handle_index++;
1719 assert(handle_index <= stack_slots, "overflow");
1720 if (map != NULL) {
1721 __ stf(FloatRegisterImpl::S, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS);
1722 } else {
1723 __ ldf(FloatRegisterImpl::S, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister());
1724 }
1725 }
1726 }
1728 }
1731 // Check GC_locker::needs_gc and enter the runtime if it's true. This
1732 // keeps a new JNI critical region from starting until a GC has been
1733 // forced. Save down any oops in registers and describe them in an
1734 // OopMap.
1735 static void check_needs_gc_for_critical_native(MacroAssembler* masm,
1736 const int stack_slots,
1737 const int total_in_args,
1738 const int arg_save_area,
1739 OopMapSet* oop_maps,
1740 VMRegPair* in_regs,
1741 BasicType* in_sig_bt) {
1742 __ block_comment("check GC_locker::needs_gc");
1743 Label cont;
1744 AddressLiteral sync_state(GC_locker::needs_gc_address());
1745 __ load_bool_contents(sync_state, G3_scratch);
1746 __ cmp_zero_and_br(Assembler::equal, G3_scratch, cont);
1747 __ delayed()->nop();
1749 // Save down any values that are live in registers and call into the
1750 // runtime to halt for a GC
1751 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1752 save_or_restore_arguments(masm, stack_slots, total_in_args,
1753 arg_save_area, map, in_regs, in_sig_bt);
1755 __ mov(G2_thread, L7_thread_cache);
1757 __ set_last_Java_frame(SP, noreg);
1759 __ block_comment("block_for_jni_critical");
1760 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical), relocInfo::runtime_call_type);
1761 __ delayed()->mov(L7_thread_cache, O0);
1762 oop_maps->add_gc_map( __ offset(), map);
1764 __ restore_thread(L7_thread_cache); // restore G2_thread
1765 __ reset_last_Java_frame();
1767 // Reload all the register arguments
1768 save_or_restore_arguments(masm, stack_slots, total_in_args,
1769 arg_save_area, NULL, in_regs, in_sig_bt);
1771 __ bind(cont);
1772 #ifdef ASSERT
1773 if (StressCriticalJNINatives) {
1774 // Stress register saving
1775 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1776 save_or_restore_arguments(masm, stack_slots, total_in_args,
1777 arg_save_area, map, in_regs, in_sig_bt);
1778 // Destroy argument registers
1779 for (int i = 0; i < total_in_args; i++) {
1780 if (in_regs[i].first()->is_Register()) {
1781 const Register reg = in_regs[i].first()->as_Register();
1782 if (reg->is_global()) {
1783 __ mov(G0, reg);
1784 }
1785 } else if (in_regs[i].first()->is_FloatRegister()) {
1786 __ fneg(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), in_regs[i].first()->as_FloatRegister());
1787 }
1788 }
1790 save_or_restore_arguments(masm, stack_slots, total_in_args,
1791 arg_save_area, NULL, in_regs, in_sig_bt);
1792 }
1793 #endif
1794 }
1796 // Unpack an array argument into a pointer to the body and the length
1797 // if the array is non-null, otherwise pass 0 for both.
1798 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) {
1799 // Pass the length, ptr pair
1800 Label is_null, done;
1801 if (reg.first()->is_stack()) {
1802 VMRegPair tmp = reg64_to_VMRegPair(L2);
1803 // Load the arg up from the stack
1804 move_ptr(masm, reg, tmp);
1805 reg = tmp;
1806 }
1807 __ cmp(reg.first()->as_Register(), G0);
1808 __ brx(Assembler::equal, false, Assembler::pt, is_null);
1809 __ delayed()->add(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type), L4);
1810 move_ptr(masm, reg64_to_VMRegPair(L4), body_arg);
1811 __ ld(reg.first()->as_Register(), arrayOopDesc::length_offset_in_bytes(), L4);
1812 move32_64(masm, reg64_to_VMRegPair(L4), length_arg);
1813 __ ba_short(done);
1814 __ bind(is_null);
1815 // Pass zeros
1816 move_ptr(masm, reg64_to_VMRegPair(G0), body_arg);
1817 move32_64(masm, reg64_to_VMRegPair(G0), length_arg);
1818 __ bind(done);
1819 }
1821 static void verify_oop_args(MacroAssembler* masm,
1822 methodHandle method,
1823 const BasicType* sig_bt,
1824 const VMRegPair* regs) {
1825 Register temp_reg = G5_method; // not part of any compiled calling seq
1826 if (VerifyOops) {
1827 for (int i = 0; i < method->size_of_parameters(); i++) {
1828 if (sig_bt[i] == T_OBJECT ||
1829 sig_bt[i] == T_ARRAY) {
1830 VMReg r = regs[i].first();
1831 assert(r->is_valid(), "bad oop arg");
1832 if (r->is_stack()) {
1833 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS;
1834 ld_off = __ ensure_simm13_or_reg(ld_off, temp_reg);
1835 __ ld_ptr(SP, ld_off, temp_reg);
1836 __ verify_oop(temp_reg);
1837 } else {
1838 __ verify_oop(r->as_Register());
1839 }
1840 }
1841 }
1842 }
1843 }
1845 static void gen_special_dispatch(MacroAssembler* masm,
1846 methodHandle method,
1847 const BasicType* sig_bt,
1848 const VMRegPair* regs) {
1849 verify_oop_args(masm, method, sig_bt, regs);
1850 vmIntrinsics::ID iid = method->intrinsic_id();
1852 // Now write the args into the outgoing interpreter space
1853 bool has_receiver = false;
1854 Register receiver_reg = noreg;
1855 int member_arg_pos = -1;
1856 Register member_reg = noreg;
1857 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid);
1858 if (ref_kind != 0) {
1859 member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument
1860 member_reg = G5_method; // known to be free at this point
1861 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind);
1862 } else if (iid == vmIntrinsics::_invokeBasic) {
1863 has_receiver = true;
1864 } else {
1865 fatal(err_msg_res("unexpected intrinsic id %d", iid));
1866 }
1868 if (member_reg != noreg) {
1869 // Load the member_arg into register, if necessary.
1870 SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs);
1871 VMReg r = regs[member_arg_pos].first();
1872 if (r->is_stack()) {
1873 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS;
1874 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg);
1875 __ ld_ptr(SP, ld_off, member_reg);
1876 } else {
1877 // no data motion is needed
1878 member_reg = r->as_Register();
1879 }
1880 }
1882 if (has_receiver) {
1883 // Make sure the receiver is loaded into a register.
1884 assert(method->size_of_parameters() > 0, "oob");
1885 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object");
1886 VMReg r = regs[0].first();
1887 assert(r->is_valid(), "bad receiver arg");
1888 if (r->is_stack()) {
1889 // Porting note: This assumes that compiled calling conventions always
1890 // pass the receiver oop in a register. If this is not true on some
1891 // platform, pick a temp and load the receiver from stack.
1892 fatal("receiver always in a register");
1893 receiver_reg = G3_scratch; // known to be free at this point
1894 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS;
1895 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg);
1896 __ ld_ptr(SP, ld_off, receiver_reg);
1897 } else {
1898 // no data motion is needed
1899 receiver_reg = r->as_Register();
1900 }
1901 }
1903 // Figure out which address we are really jumping to:
1904 MethodHandles::generate_method_handle_dispatch(masm, iid,
1905 receiver_reg, member_reg, /*for_compiler_entry:*/ true);
1906 }
1908 // ---------------------------------------------------------------------------
1909 // Generate a native wrapper for a given method. The method takes arguments
1910 // in the Java compiled code convention, marshals them to the native
1911 // convention (handlizes oops, etc), transitions to native, makes the call,
1912 // returns to java state (possibly blocking), unhandlizes any result and
1913 // returns.
1914 //
1915 // Critical native functions are a shorthand for the use of
1916 // GetPrimtiveArrayCritical and disallow the use of any other JNI
1917 // functions. The wrapper is expected to unpack the arguments before
1918 // passing them to the callee and perform checks before and after the
1919 // native call to ensure that they GC_locker
1920 // lock_critical/unlock_critical semantics are followed. Some other
1921 // parts of JNI setup are skipped like the tear down of the JNI handle
1922 // block and the check for pending exceptions it's impossible for them
1923 // to be thrown.
1924 //
1925 // They are roughly structured like this:
1926 // if (GC_locker::needs_gc())
1927 // SharedRuntime::block_for_jni_critical();
1928 // tranistion to thread_in_native
1929 // unpack arrray arguments and call native entry point
1930 // check for safepoint in progress
1931 // check if any thread suspend flags are set
1932 // call into JVM and possible unlock the JNI critical
1933 // if a GC was suppressed while in the critical native.
1934 // transition back to thread_in_Java
1935 // return to caller
1936 //
1937 nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
1938 methodHandle method,
1939 int compile_id,
1940 BasicType* in_sig_bt,
1941 VMRegPair* in_regs,
1942 BasicType ret_type) {
1943 if (method->is_method_handle_intrinsic()) {
1944 vmIntrinsics::ID iid = method->intrinsic_id();
1945 intptr_t start = (intptr_t)__ pc();
1946 int vep_offset = ((intptr_t)__ pc()) - start;
1947 gen_special_dispatch(masm,
1948 method,
1949 in_sig_bt,
1950 in_regs);
1951 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period
1952 __ flush();
1953 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually
1954 return nmethod::new_native_nmethod(method,
1955 compile_id,
1956 masm->code(),
1957 vep_offset,
1958 frame_complete,
1959 stack_slots / VMRegImpl::slots_per_word,
1960 in_ByteSize(-1),
1961 in_ByteSize(-1),
1962 (OopMapSet*)NULL);
1963 }
1964 bool is_critical_native = true;
1965 address native_func = method->critical_native_function();
1966 if (native_func == NULL) {
1967 native_func = method->native_function();
1968 is_critical_native = false;
1969 }
1970 assert(native_func != NULL, "must have function");
1972 // Native nmethod wrappers never take possesion of the oop arguments.
1973 // So the caller will gc the arguments. The only thing we need an
1974 // oopMap for is if the call is static
1975 //
1976 // An OopMap for lock (and class if static), and one for the VM call itself
1977 OopMapSet *oop_maps = new OopMapSet();
1978 intptr_t start = (intptr_t)__ pc();
1980 // First thing make an ic check to see if we should even be here
1981 {
1982 Label L;
1983 const Register temp_reg = G3_scratch;
1984 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
1985 __ verify_oop(O0);
1986 __ load_klass(O0, temp_reg);
1987 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L);
1989 __ jump_to(ic_miss, temp_reg);
1990 __ delayed()->nop();
1991 __ align(CodeEntryAlignment);
1992 __ bind(L);
1993 }
1995 int vep_offset = ((intptr_t)__ pc()) - start;
1997 #ifdef COMPILER1
1998 if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) {
1999 // Object.hashCode can pull the hashCode from the header word
2000 // instead of doing a full VM transition once it's been computed.
2001 // Since hashCode is usually polymorphic at call sites we can't do
2002 // this optimization at the call site without a lot of work.
2003 Label slowCase;
2004 Register receiver = O0;
2005 Register result = O0;
2006 Register header = G3_scratch;
2007 Register hash = G3_scratch; // overwrite header value with hash value
2008 Register mask = G1; // to get hash field from header
2010 // Read the header and build a mask to get its hash field. Give up if the object is not unlocked.
2011 // We depend on hash_mask being at most 32 bits and avoid the use of
2012 // hash_mask_in_place because it could be larger than 32 bits in a 64-bit
2013 // vm: see markOop.hpp.
2014 __ ld_ptr(receiver, oopDesc::mark_offset_in_bytes(), header);
2015 __ sethi(markOopDesc::hash_mask, mask);
2016 __ btst(markOopDesc::unlocked_value, header);
2017 __ br(Assembler::zero, false, Assembler::pn, slowCase);
2018 if (UseBiasedLocking) {
2019 // Check if biased and fall through to runtime if so
2020 __ delayed()->nop();
2021 __ btst(markOopDesc::biased_lock_bit_in_place, header);
2022 __ br(Assembler::notZero, false, Assembler::pn, slowCase);
2023 }
2024 __ delayed()->or3(mask, markOopDesc::hash_mask & 0x3ff, mask);
2026 // Check for a valid (non-zero) hash code and get its value.
2027 #ifdef _LP64
2028 __ srlx(header, markOopDesc::hash_shift, hash);
2029 #else
2030 __ srl(header, markOopDesc::hash_shift, hash);
2031 #endif
2032 __ andcc(hash, mask, hash);
2033 __ br(Assembler::equal, false, Assembler::pn, slowCase);
2034 __ delayed()->nop();
2036 // leaf return.
2037 __ retl();
2038 __ delayed()->mov(hash, result);
2039 __ bind(slowCase);
2040 }
2041 #endif // COMPILER1
2044 // We have received a description of where all the java arg are located
2045 // on entry to the wrapper. We need to convert these args to where
2046 // the jni function will expect them. To figure out where they go
2047 // we convert the java signature to a C signature by inserting
2048 // the hidden arguments as arg[0] and possibly arg[1] (static method)
2050 const int total_in_args = method->size_of_parameters();
2051 int total_c_args = total_in_args;
2052 int total_save_slots = 6 * VMRegImpl::slots_per_word;
2053 if (!is_critical_native) {
2054 total_c_args += 1;
2055 if (method->is_static()) {
2056 total_c_args++;
2057 }
2058 } else {
2059 for (int i = 0; i < total_in_args; i++) {
2060 if (in_sig_bt[i] == T_ARRAY) {
2061 // These have to be saved and restored across the safepoint
2062 total_c_args++;
2063 }
2064 }
2065 }
2067 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
2068 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
2069 BasicType* in_elem_bt = NULL;
2071 int argc = 0;
2072 if (!is_critical_native) {
2073 out_sig_bt[argc++] = T_ADDRESS;
2074 if (method->is_static()) {
2075 out_sig_bt[argc++] = T_OBJECT;
2076 }
2078 for (int i = 0; i < total_in_args ; i++ ) {
2079 out_sig_bt[argc++] = in_sig_bt[i];
2080 }
2081 } else {
2082 Thread* THREAD = Thread::current();
2083 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args);
2084 SignatureStream ss(method->signature());
2085 for (int i = 0; i < total_in_args ; i++ ) {
2086 if (in_sig_bt[i] == T_ARRAY) {
2087 // Arrays are passed as int, elem* pair
2088 out_sig_bt[argc++] = T_INT;
2089 out_sig_bt[argc++] = T_ADDRESS;
2090 Symbol* atype = ss.as_symbol(CHECK_NULL);
2091 const char* at = atype->as_C_string();
2092 if (strlen(at) == 2) {
2093 assert(at[0] == '[', "must be");
2094 switch (at[1]) {
2095 case 'B': in_elem_bt[i] = T_BYTE; break;
2096 case 'C': in_elem_bt[i] = T_CHAR; break;
2097 case 'D': in_elem_bt[i] = T_DOUBLE; break;
2098 case 'F': in_elem_bt[i] = T_FLOAT; break;
2099 case 'I': in_elem_bt[i] = T_INT; break;
2100 case 'J': in_elem_bt[i] = T_LONG; break;
2101 case 'S': in_elem_bt[i] = T_SHORT; break;
2102 case 'Z': in_elem_bt[i] = T_BOOLEAN; break;
2103 default: ShouldNotReachHere();
2104 }
2105 }
2106 } else {
2107 out_sig_bt[argc++] = in_sig_bt[i];
2108 in_elem_bt[i] = T_VOID;
2109 }
2110 if (in_sig_bt[i] != T_VOID) {
2111 assert(in_sig_bt[i] == ss.type(), "must match");
2112 ss.next();
2113 }
2114 }
2115 }
2117 // Now figure out where the args must be stored and how much stack space
2118 // they require (neglecting out_preserve_stack_slots but space for storing
2119 // the 1st six register arguments). It's weird see int_stk_helper.
2120 //
2121 int out_arg_slots;
2122 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args);
2124 if (is_critical_native) {
2125 // Critical natives may have to call out so they need a save area
2126 // for register arguments.
2127 int double_slots = 0;
2128 int single_slots = 0;
2129 for ( int i = 0; i < total_in_args; i++) {
2130 if (in_regs[i].first()->is_Register()) {
2131 const Register reg = in_regs[i].first()->as_Register();
2132 switch (in_sig_bt[i]) {
2133 case T_ARRAY:
2134 case T_BOOLEAN:
2135 case T_BYTE:
2136 case T_SHORT:
2137 case T_CHAR:
2138 case T_INT: assert(reg->is_in(), "don't need to save these"); break;
2139 case T_LONG: if (reg->is_global()) double_slots++; break;
2140 default: ShouldNotReachHere();
2141 }
2142 } else if (in_regs[i].first()->is_FloatRegister()) {
2143 switch (in_sig_bt[i]) {
2144 case T_FLOAT: single_slots++; break;
2145 case T_DOUBLE: double_slots++; break;
2146 default: ShouldNotReachHere();
2147 }
2148 }
2149 }
2150 total_save_slots = double_slots * 2 + single_slots;
2151 }
2153 // Compute framesize for the wrapper. We need to handlize all oops in
2154 // registers. We must create space for them here that is disjoint from
2155 // the windowed save area because we have no control over when we might
2156 // flush the window again and overwrite values that gc has since modified.
2157 // (The live window race)
2158 //
2159 // We always just allocate 6 word for storing down these object. This allow
2160 // us to simply record the base and use the Ireg number to decide which
2161 // slot to use. (Note that the reg number is the inbound number not the
2162 // outbound number).
2163 // We must shuffle args to match the native convention, and include var-args space.
2165 // Calculate the total number of stack slots we will need.
2167 // First count the abi requirement plus all of the outgoing args
2168 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
2170 // Now the space for the inbound oop handle area
2172 int oop_handle_offset = round_to(stack_slots, 2);
2173 stack_slots += total_save_slots;
2175 // Now any space we need for handlizing a klass if static method
2177 int klass_slot_offset = 0;
2178 int klass_offset = -1;
2179 int lock_slot_offset = 0;
2180 bool is_static = false;
2182 if (method->is_static()) {
2183 klass_slot_offset = stack_slots;
2184 stack_slots += VMRegImpl::slots_per_word;
2185 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
2186 is_static = true;
2187 }
2189 // Plus a lock if needed
2191 if (method->is_synchronized()) {
2192 lock_slot_offset = stack_slots;
2193 stack_slots += VMRegImpl::slots_per_word;
2194 }
2196 // Now a place to save return value or as a temporary for any gpr -> fpr moves
2197 stack_slots += 2;
2199 // Ok The space we have allocated will look like:
2200 //
2201 //
2202 // FP-> | |
2203 // |---------------------|
2204 // | 2 slots for moves |
2205 // |---------------------|
2206 // | lock box (if sync) |
2207 // |---------------------| <- lock_slot_offset
2208 // | klass (if static) |
2209 // |---------------------| <- klass_slot_offset
2210 // | oopHandle area |
2211 // |---------------------| <- oop_handle_offset
2212 // | outbound memory |
2213 // | based arguments |
2214 // | |
2215 // |---------------------|
2216 // | vararg area |
2217 // |---------------------|
2218 // | |
2219 // SP-> | out_preserved_slots |
2220 //
2221 //
2224 // Now compute actual number of stack words we need rounding to make
2225 // stack properly aligned.
2226 stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word);
2228 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
2230 // Generate stack overflow check before creating frame
2231 __ generate_stack_overflow_check(stack_size);
2233 // Generate a new frame for the wrapper.
2234 __ save(SP, -stack_size, SP);
2236 int frame_complete = ((intptr_t)__ pc()) - start;
2238 __ verify_thread();
2240 if (is_critical_native) {
2241 check_needs_gc_for_critical_native(masm, stack_slots, total_in_args,
2242 oop_handle_offset, oop_maps, in_regs, in_sig_bt);
2243 }
2245 //
2246 // We immediately shuffle the arguments so that any vm call we have to
2247 // make from here on out (sync slow path, jvmti, etc.) we will have
2248 // captured the oops from our caller and have a valid oopMap for
2249 // them.
2251 // -----------------
2252 // The Grand Shuffle
2253 //
2254 // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv*
2255 // (derived from JavaThread* which is in L7_thread_cache) and, if static,
2256 // the class mirror instead of a receiver. This pretty much guarantees that
2257 // register layout will not match. We ignore these extra arguments during
2258 // the shuffle. The shuffle is described by the two calling convention
2259 // vectors we have in our possession. We simply walk the java vector to
2260 // get the source locations and the c vector to get the destinations.
2261 // Because we have a new window and the argument registers are completely
2262 // disjoint ( I0 -> O1, I1 -> O2, ...) we have nothing to worry about
2263 // here.
2265 // This is a trick. We double the stack slots so we can claim
2266 // the oops in the caller's frame. Since we are sure to have
2267 // more args than the caller doubling is enough to make
2268 // sure we can capture all the incoming oop args from the
2269 // caller.
2270 //
2271 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
2272 // Record sp-based slot for receiver on stack for non-static methods
2273 int receiver_offset = -1;
2275 // We move the arguments backward because the floating point registers
2276 // destination will always be to a register with a greater or equal register
2277 // number or the stack.
2279 #ifdef ASSERT
2280 bool reg_destroyed[RegisterImpl::number_of_registers];
2281 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
2282 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
2283 reg_destroyed[r] = false;
2284 }
2285 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
2286 freg_destroyed[f] = false;
2287 }
2289 #endif /* ASSERT */
2291 for ( int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0 ; i--, c_arg-- ) {
2293 #ifdef ASSERT
2294 if (in_regs[i].first()->is_Register()) {
2295 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "ack!");
2296 } else if (in_regs[i].first()->is_FloatRegister()) {
2297 assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)], "ack!");
2298 }
2299 if (out_regs[c_arg].first()->is_Register()) {
2300 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
2301 } else if (out_regs[c_arg].first()->is_FloatRegister()) {
2302 freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)] = true;
2303 }
2304 #endif /* ASSERT */
2306 switch (in_sig_bt[i]) {
2307 case T_ARRAY:
2308 if (is_critical_native) {
2309 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg], out_regs[c_arg - 1]);
2310 c_arg--;
2311 break;
2312 }
2313 case T_OBJECT:
2314 assert(!is_critical_native, "no oop arguments");
2315 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
2316 ((i == 0) && (!is_static)),
2317 &receiver_offset);
2318 break;
2319 case T_VOID:
2320 break;
2322 case T_FLOAT:
2323 float_move(masm, in_regs[i], out_regs[c_arg]);
2324 break;
2326 case T_DOUBLE:
2327 assert( i + 1 < total_in_args &&
2328 in_sig_bt[i + 1] == T_VOID &&
2329 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
2330 double_move(masm, in_regs[i], out_regs[c_arg]);
2331 break;
2333 case T_LONG :
2334 long_move(masm, in_regs[i], out_regs[c_arg]);
2335 break;
2337 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2339 default:
2340 move32_64(masm, in_regs[i], out_regs[c_arg]);
2341 }
2342 }
2344 // Pre-load a static method's oop into O1. Used both by locking code and
2345 // the normal JNI call code.
2346 if (method->is_static() && !is_critical_native) {
2347 __ set_oop_constant(JNIHandles::make_local(method->method_holder()->java_mirror()), O1);
2349 // Now handlize the static class mirror in O1. It's known not-null.
2350 __ st_ptr(O1, SP, klass_offset + STACK_BIAS);
2351 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
2352 __ add(SP, klass_offset + STACK_BIAS, O1);
2353 }
2356 const Register L6_handle = L6;
2358 if (method->is_synchronized()) {
2359 assert(!is_critical_native, "unhandled");
2360 __ mov(O1, L6_handle);
2361 }
2363 // We have all of the arguments setup at this point. We MUST NOT touch any Oregs
2364 // except O6/O7. So if we must call out we must push a new frame. We immediately
2365 // push a new frame and flush the windows.
2366 #ifdef _LP64
2367 intptr_t thepc = (intptr_t) __ pc();
2368 {
2369 address here = __ pc();
2370 // Call the next instruction
2371 __ call(here + 8, relocInfo::none);
2372 __ delayed()->nop();
2373 }
2374 #else
2375 intptr_t thepc = __ load_pc_address(O7, 0);
2376 #endif /* _LP64 */
2378 // We use the same pc/oopMap repeatedly when we call out
2379 oop_maps->add_gc_map(thepc - start, map);
2381 // O7 now has the pc loaded that we will use when we finally call to native.
2383 // Save thread in L7; it crosses a bunch of VM calls below
2384 // Don't use save_thread because it smashes G2 and we merely
2385 // want to save a copy
2386 __ mov(G2_thread, L7_thread_cache);
2389 // If we create an inner frame once is plenty
2390 // when we create it we must also save G2_thread
2391 bool inner_frame_created = false;
2393 // dtrace method entry support
2394 {
2395 SkipIfEqual skip_if(
2396 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
2397 // create inner frame
2398 __ save_frame(0);
2399 __ mov(G2_thread, L7_thread_cache);
2400 __ set_metadata_constant(method(), O1);
2401 __ call_VM_leaf(L7_thread_cache,
2402 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
2403 G2_thread, O1);
2404 __ restore();
2405 }
2407 // RedefineClasses() tracing support for obsolete method entry
2408 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
2409 // create inner frame
2410 __ save_frame(0);
2411 __ mov(G2_thread, L7_thread_cache);
2412 __ set_metadata_constant(method(), O1);
2413 __ call_VM_leaf(L7_thread_cache,
2414 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
2415 G2_thread, O1);
2416 __ restore();
2417 }
2419 // We are in the jni frame unless saved_frame is true in which case
2420 // we are in one frame deeper (the "inner" frame). If we are in the
2421 // "inner" frames the args are in the Iregs and if the jni frame then
2422 // they are in the Oregs.
2423 // If we ever need to go to the VM (for locking, jvmti) then
2424 // we will always be in the "inner" frame.
2426 // Lock a synchronized method
2427 int lock_offset = -1; // Set if locked
2428 if (method->is_synchronized()) {
2429 Register Roop = O1;
2430 const Register L3_box = L3;
2432 create_inner_frame(masm, &inner_frame_created);
2434 __ ld_ptr(I1, 0, O1);
2435 Label done;
2437 lock_offset = (lock_slot_offset * VMRegImpl::stack_slot_size);
2438 __ add(FP, lock_offset+STACK_BIAS, L3_box);
2439 #ifdef ASSERT
2440 if (UseBiasedLocking) {
2441 // making the box point to itself will make it clear it went unused
2442 // but also be obviously invalid
2443 __ st_ptr(L3_box, L3_box, 0);
2444 }
2445 #endif // ASSERT
2446 //
2447 // Compiler_lock_object (Roop, Rmark, Rbox, Rscratch) -- kills Rmark, Rbox, Rscratch
2448 //
2449 __ compiler_lock_object(Roop, L1, L3_box, L2);
2450 __ br(Assembler::equal, false, Assembler::pt, done);
2451 __ delayed() -> add(FP, lock_offset+STACK_BIAS, L3_box);
2454 // None of the above fast optimizations worked so we have to get into the
2455 // slow case of monitor enter. Inline a special case of call_VM that
2456 // disallows any pending_exception.
2457 __ mov(Roop, O0); // Need oop in O0
2458 __ mov(L3_box, O1);
2460 // Record last_Java_sp, in case the VM code releases the JVM lock.
2462 __ set_last_Java_frame(FP, I7);
2464 // do the call
2465 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), relocInfo::runtime_call_type);
2466 __ delayed()->mov(L7_thread_cache, O2);
2468 __ restore_thread(L7_thread_cache); // restore G2_thread
2469 __ reset_last_Java_frame();
2471 #ifdef ASSERT
2472 { Label L;
2473 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
2474 __ br_null_short(O0, Assembler::pt, L);
2475 __ stop("no pending exception allowed on exit from IR::monitorenter");
2476 __ bind(L);
2477 }
2478 #endif
2479 __ bind(done);
2480 }
2483 // Finally just about ready to make the JNI call
2485 __ flushw();
2486 if (inner_frame_created) {
2487 __ restore();
2488 } else {
2489 // Store only what we need from this frame
2490 // QQQ I think that non-v9 (like we care) we don't need these saves
2491 // either as the flush traps and the current window goes too.
2492 __ st_ptr(FP, SP, FP->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
2493 __ st_ptr(I7, SP, I7->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
2494 }
2496 // get JNIEnv* which is first argument to native
2497 if (!is_critical_native) {
2498 __ add(G2_thread, in_bytes(JavaThread::jni_environment_offset()), O0);
2499 }
2501 // Use that pc we placed in O7 a while back as the current frame anchor
2502 __ set_last_Java_frame(SP, O7);
2504 // We flushed the windows ages ago now mark them as flushed before transitioning.
2505 __ set(JavaFrameAnchor::flushed, G3_scratch);
2506 __ st(G3_scratch, G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
2508 // Transition from _thread_in_Java to _thread_in_native.
2509 __ set(_thread_in_native, G3_scratch);
2511 #ifdef _LP64
2512 AddressLiteral dest(native_func);
2513 __ relocate(relocInfo::runtime_call_type);
2514 __ jumpl_to(dest, O7, O7);
2515 #else
2516 __ call(native_func, relocInfo::runtime_call_type);
2517 #endif
2518 __ delayed()->st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
2520 __ restore_thread(L7_thread_cache); // restore G2_thread
2522 // Unpack native results. For int-types, we do any needed sign-extension
2523 // and move things into I0. The return value there will survive any VM
2524 // calls for blocking or unlocking. An FP or OOP result (handle) is done
2525 // specially in the slow-path code.
2526 switch (ret_type) {
2527 case T_VOID: break; // Nothing to do!
2528 case T_FLOAT: break; // Got it where we want it (unless slow-path)
2529 case T_DOUBLE: break; // Got it where we want it (unless slow-path)
2530 // In 64 bits build result is in O0, in O0, O1 in 32bit build
2531 case T_LONG:
2532 #ifndef _LP64
2533 __ mov(O1, I1);
2534 #endif
2535 // Fall thru
2536 case T_OBJECT: // Really a handle
2537 case T_ARRAY:
2538 case T_INT:
2539 __ mov(O0, I0);
2540 break;
2541 case T_BOOLEAN: __ subcc(G0, O0, G0); __ addc(G0, 0, I0); break; // !0 => true; 0 => false
2542 case T_BYTE : __ sll(O0, 24, O0); __ sra(O0, 24, I0); break;
2543 case T_CHAR : __ sll(O0, 16, O0); __ srl(O0, 16, I0); break; // cannot use and3, 0xFFFF too big as immediate value!
2544 case T_SHORT : __ sll(O0, 16, O0); __ sra(O0, 16, I0); break;
2545 break; // Cannot de-handlize until after reclaiming jvm_lock
2546 default:
2547 ShouldNotReachHere();
2548 }
2550 Label after_transition;
2551 // must we block?
2553 // Block, if necessary, before resuming in _thread_in_Java state.
2554 // In order for GC to work, don't clear the last_Java_sp until after blocking.
2555 { Label no_block;
2556 AddressLiteral sync_state(SafepointSynchronize::address_of_state());
2558 // Switch thread to "native transition" state before reading the synchronization state.
2559 // This additional state is necessary because reading and testing the synchronization
2560 // state is not atomic w.r.t. GC, as this scenario demonstrates:
2561 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
2562 // VM thread changes sync state to synchronizing and suspends threads for GC.
2563 // Thread A is resumed to finish this native method, but doesn't block here since it
2564 // didn't see any synchronization is progress, and escapes.
2565 __ set(_thread_in_native_trans, G3_scratch);
2566 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
2567 if(os::is_MP()) {
2568 if (UseMembar) {
2569 // Force this write out before the read below
2570 __ membar(Assembler::StoreLoad);
2571 } else {
2572 // Write serialization page so VM thread can do a pseudo remote membar.
2573 // We use the current thread pointer to calculate a thread specific
2574 // offset to write to within the page. This minimizes bus traffic
2575 // due to cache line collision.
2576 __ serialize_memory(G2_thread, G1_scratch, G3_scratch);
2577 }
2578 }
2579 __ load_contents(sync_state, G3_scratch);
2580 __ cmp(G3_scratch, SafepointSynchronize::_not_synchronized);
2582 Label L;
2583 Address suspend_state(G2_thread, JavaThread::suspend_flags_offset());
2584 __ br(Assembler::notEqual, false, Assembler::pn, L);
2585 __ delayed()->ld(suspend_state, G3_scratch);
2586 __ cmp_and_br_short(G3_scratch, 0, Assembler::equal, Assembler::pt, no_block);
2587 __ bind(L);
2589 // Block. Save any potential method result value before the operation and
2590 // use a leaf call to leave the last_Java_frame setup undisturbed. Doing this
2591 // lets us share the oopMap we used when we went native rather the create
2592 // a distinct one for this pc
2593 //
2594 save_native_result(masm, ret_type, stack_slots);
2595 if (!is_critical_native) {
2596 __ call_VM_leaf(L7_thread_cache,
2597 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans),
2598 G2_thread);
2599 } else {
2600 __ call_VM_leaf(L7_thread_cache,
2601 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition),
2602 G2_thread);
2603 }
2605 // Restore any method result value
2606 restore_native_result(masm, ret_type, stack_slots);
2608 if (is_critical_native) {
2609 // The call above performed the transition to thread_in_Java so
2610 // skip the transition logic below.
2611 __ ba(after_transition);
2612 __ delayed()->nop();
2613 }
2615 __ bind(no_block);
2616 }
2618 // thread state is thread_in_native_trans. Any safepoint blocking has already
2619 // happened so we can now change state to _thread_in_Java.
2620 __ set(_thread_in_Java, G3_scratch);
2621 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
2622 __ bind(after_transition);
2624 Label no_reguard;
2625 __ ld(G2_thread, JavaThread::stack_guard_state_offset(), G3_scratch);
2626 __ cmp_and_br_short(G3_scratch, JavaThread::stack_guard_yellow_disabled, Assembler::notEqual, Assembler::pt, no_reguard);
2628 save_native_result(masm, ret_type, stack_slots);
2629 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
2630 __ delayed()->nop();
2632 __ restore_thread(L7_thread_cache); // restore G2_thread
2633 restore_native_result(masm, ret_type, stack_slots);
2635 __ bind(no_reguard);
2637 // Handle possible exception (will unlock if necessary)
2639 // native result if any is live in freg or I0 (and I1 if long and 32bit vm)
2641 // Unlock
2642 if (method->is_synchronized()) {
2643 Label done;
2644 Register I2_ex_oop = I2;
2645 const Register L3_box = L3;
2646 // Get locked oop from the handle we passed to jni
2647 __ ld_ptr(L6_handle, 0, L4);
2648 __ add(SP, lock_offset+STACK_BIAS, L3_box);
2649 // Must save pending exception around the slow-path VM call. Since it's a
2650 // leaf call, the pending exception (if any) can be kept in a register.
2651 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), I2_ex_oop);
2652 // Now unlock
2653 // (Roop, Rmark, Rbox, Rscratch)
2654 __ compiler_unlock_object(L4, L1, L3_box, L2);
2655 __ br(Assembler::equal, false, Assembler::pt, done);
2656 __ delayed()-> add(SP, lock_offset+STACK_BIAS, L3_box);
2658 // save and restore any potential method result value around the unlocking
2659 // operation. Will save in I0 (or stack for FP returns).
2660 save_native_result(masm, ret_type, stack_slots);
2662 // Must clear pending-exception before re-entering the VM. Since this is
2663 // a leaf call, pending-exception-oop can be safely kept in a register.
2664 __ st_ptr(G0, G2_thread, in_bytes(Thread::pending_exception_offset()));
2666 // slow case of monitor enter. Inline a special case of call_VM that
2667 // disallows any pending_exception.
2668 __ mov(L3_box, O1);
2670 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C), relocInfo::runtime_call_type);
2671 __ delayed()->mov(L4, O0); // Need oop in O0
2673 __ restore_thread(L7_thread_cache); // restore G2_thread
2675 #ifdef ASSERT
2676 { Label L;
2677 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
2678 __ br_null_short(O0, Assembler::pt, L);
2679 __ stop("no pending exception allowed on exit from IR::monitorexit");
2680 __ bind(L);
2681 }
2682 #endif
2683 restore_native_result(masm, ret_type, stack_slots);
2684 // check_forward_pending_exception jump to forward_exception if any pending
2685 // exception is set. The forward_exception routine expects to see the
2686 // exception in pending_exception and not in a register. Kind of clumsy,
2687 // since all folks who branch to forward_exception must have tested
2688 // pending_exception first and hence have it in a register already.
2689 __ st_ptr(I2_ex_oop, G2_thread, in_bytes(Thread::pending_exception_offset()));
2690 __ bind(done);
2691 }
2693 // Tell dtrace about this method exit
2694 {
2695 SkipIfEqual skip_if(
2696 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
2697 save_native_result(masm, ret_type, stack_slots);
2698 __ set_metadata_constant(method(), O1);
2699 __ call_VM_leaf(L7_thread_cache,
2700 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
2701 G2_thread, O1);
2702 restore_native_result(masm, ret_type, stack_slots);
2703 }
2705 // Clear "last Java frame" SP and PC.
2706 __ verify_thread(); // G2_thread must be correct
2707 __ reset_last_Java_frame();
2709 // Unpack oop result
2710 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
2711 Label L;
2712 __ addcc(G0, I0, G0);
2713 __ brx(Assembler::notZero, true, Assembler::pt, L);
2714 __ delayed()->ld_ptr(I0, 0, I0);
2715 __ mov(G0, I0);
2716 __ bind(L);
2717 __ verify_oop(I0);
2718 }
2720 if (!is_critical_native) {
2721 // reset handle block
2722 __ ld_ptr(G2_thread, in_bytes(JavaThread::active_handles_offset()), L5);
2723 __ st(G0, L5, JNIHandleBlock::top_offset_in_bytes());
2725 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), G3_scratch);
2726 check_forward_pending_exception(masm, G3_scratch);
2727 }
2730 // Return
2732 #ifndef _LP64
2733 if (ret_type == T_LONG) {
2735 // Must leave proper result in O0,O1 and G1 (c2/tiered only)
2736 __ sllx(I0, 32, G1); // Shift bits into high G1
2737 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
2738 __ or3 (I1, G1, G1); // OR 64 bits into G1
2739 }
2740 #endif
2742 __ ret();
2743 __ delayed()->restore();
2745 __ flush();
2747 nmethod *nm = nmethod::new_native_nmethod(method,
2748 compile_id,
2749 masm->code(),
2750 vep_offset,
2751 frame_complete,
2752 stack_slots / VMRegImpl::slots_per_word,
2753 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
2754 in_ByteSize(lock_offset),
2755 oop_maps);
2757 if (is_critical_native) {
2758 nm->set_lazy_critical_native(true);
2759 }
2760 return nm;
2762 }
2764 #ifdef HAVE_DTRACE_H
2765 // ---------------------------------------------------------------------------
2766 // Generate a dtrace nmethod for a given signature. The method takes arguments
2767 // in the Java compiled code convention, marshals them to the native
2768 // abi and then leaves nops at the position you would expect to call a native
2769 // function. When the probe is enabled the nops are replaced with a trap
2770 // instruction that dtrace inserts and the trace will cause a notification
2771 // to dtrace.
2772 //
2773 // The probes are only able to take primitive types and java/lang/String as
2774 // arguments. No other java types are allowed. Strings are converted to utf8
2775 // strings so that from dtrace point of view java strings are converted to C
2776 // strings. There is an arbitrary fixed limit on the total space that a method
2777 // can use for converting the strings. (256 chars per string in the signature).
2778 // So any java string larger then this is truncated.
2780 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 };
2781 static bool offsets_initialized = false;
2783 nmethod *SharedRuntime::generate_dtrace_nmethod(
2784 MacroAssembler *masm, methodHandle method) {
2787 // generate_dtrace_nmethod is guarded by a mutex so we are sure to
2788 // be single threaded in this method.
2789 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
2791 // Fill in the signature array, for the calling-convention call.
2792 int total_args_passed = method->size_of_parameters();
2794 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
2795 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
2797 // The signature we are going to use for the trap that dtrace will see
2798 // java/lang/String is converted. We drop "this" and any other object
2799 // is converted to NULL. (A one-slot java/lang/Long object reference
2800 // is converted to a two-slot long, which is why we double the allocation).
2801 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
2802 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
2804 int i=0;
2805 int total_strings = 0;
2806 int first_arg_to_pass = 0;
2807 int total_c_args = 0;
2809 // Skip the receiver as dtrace doesn't want to see it
2810 if( !method->is_static() ) {
2811 in_sig_bt[i++] = T_OBJECT;
2812 first_arg_to_pass = 1;
2813 }
2815 SignatureStream ss(method->signature());
2816 for ( ; !ss.at_return_type(); ss.next()) {
2817 BasicType bt = ss.type();
2818 in_sig_bt[i++] = bt; // Collect remaining bits of signature
2819 out_sig_bt[total_c_args++] = bt;
2820 if( bt == T_OBJECT) {
2821 Symbol* s = ss.as_symbol_or_null();
2822 if (s == vmSymbols::java_lang_String()) {
2823 total_strings++;
2824 out_sig_bt[total_c_args-1] = T_ADDRESS;
2825 } else if (s == vmSymbols::java_lang_Boolean() ||
2826 s == vmSymbols::java_lang_Byte()) {
2827 out_sig_bt[total_c_args-1] = T_BYTE;
2828 } else if (s == vmSymbols::java_lang_Character() ||
2829 s == vmSymbols::java_lang_Short()) {
2830 out_sig_bt[total_c_args-1] = T_SHORT;
2831 } else if (s == vmSymbols::java_lang_Integer() ||
2832 s == vmSymbols::java_lang_Float()) {
2833 out_sig_bt[total_c_args-1] = T_INT;
2834 } else if (s == vmSymbols::java_lang_Long() ||
2835 s == vmSymbols::java_lang_Double()) {
2836 out_sig_bt[total_c_args-1] = T_LONG;
2837 out_sig_bt[total_c_args++] = T_VOID;
2838 }
2839 } else if ( bt == T_LONG || bt == T_DOUBLE ) {
2840 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
2841 // We convert double to long
2842 out_sig_bt[total_c_args-1] = T_LONG;
2843 out_sig_bt[total_c_args++] = T_VOID;
2844 } else if ( bt == T_FLOAT) {
2845 // We convert float to int
2846 out_sig_bt[total_c_args-1] = T_INT;
2847 }
2848 }
2850 assert(i==total_args_passed, "validly parsed signature");
2852 // Now get the compiled-Java layout as input arguments
2853 int comp_args_on_stack;
2854 comp_args_on_stack = SharedRuntime::java_calling_convention(
2855 in_sig_bt, in_regs, total_args_passed, false);
2857 // We have received a description of where all the java arg are located
2858 // on entry to the wrapper. We need to convert these args to where
2859 // the a native (non-jni) function would expect them. To figure out
2860 // where they go we convert the java signature to a C signature and remove
2861 // T_VOID for any long/double we might have received.
2864 // Now figure out where the args must be stored and how much stack space
2865 // they require (neglecting out_preserve_stack_slots but space for storing
2866 // the 1st six register arguments). It's weird see int_stk_helper.
2867 //
2868 int out_arg_slots;
2869 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args);
2871 // Calculate the total number of stack slots we will need.
2873 // First count the abi requirement plus all of the outgoing args
2874 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
2876 // Plus a temp for possible converion of float/double/long register args
2878 int conversion_temp = stack_slots;
2879 stack_slots += 2;
2882 // Now space for the string(s) we must convert
2884 int string_locs = stack_slots;
2885 stack_slots += total_strings *
2886 (max_dtrace_string_size / VMRegImpl::stack_slot_size);
2888 // Ok The space we have allocated will look like:
2889 //
2890 //
2891 // FP-> | |
2892 // |---------------------|
2893 // | string[n] |
2894 // |---------------------| <- string_locs[n]
2895 // | string[n-1] |
2896 // |---------------------| <- string_locs[n-1]
2897 // | ... |
2898 // | ... |
2899 // |---------------------| <- string_locs[1]
2900 // | string[0] |
2901 // |---------------------| <- string_locs[0]
2902 // | temp |
2903 // |---------------------| <- conversion_temp
2904 // | outbound memory |
2905 // | based arguments |
2906 // | |
2907 // |---------------------|
2908 // | |
2909 // SP-> | out_preserved_slots |
2910 //
2911 //
2913 // Now compute actual number of stack words we need rounding to make
2914 // stack properly aligned.
2915 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word);
2917 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
2919 intptr_t start = (intptr_t)__ pc();
2921 // First thing make an ic check to see if we should even be here
2923 {
2924 Label L;
2925 const Register temp_reg = G3_scratch;
2926 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
2927 __ verify_oop(O0);
2928 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg);
2929 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L);
2931 __ jump_to(ic_miss, temp_reg);
2932 __ delayed()->nop();
2933 __ align(CodeEntryAlignment);
2934 __ bind(L);
2935 }
2937 int vep_offset = ((intptr_t)__ pc()) - start;
2940 // The instruction at the verified entry point must be 5 bytes or longer
2941 // because it can be patched on the fly by make_non_entrant. The stack bang
2942 // instruction fits that requirement.
2944 // Generate stack overflow check before creating frame
2945 __ generate_stack_overflow_check(stack_size);
2947 assert(((intptr_t)__ pc() - start - vep_offset) >= 5,
2948 "valid size for make_non_entrant");
2950 // Generate a new frame for the wrapper.
2951 __ save(SP, -stack_size, SP);
2953 // Frame is now completed as far a size and linkage.
2955 int frame_complete = ((intptr_t)__ pc()) - start;
2957 #ifdef ASSERT
2958 bool reg_destroyed[RegisterImpl::number_of_registers];
2959 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
2960 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
2961 reg_destroyed[r] = false;
2962 }
2963 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
2964 freg_destroyed[f] = false;
2965 }
2967 #endif /* ASSERT */
2969 VMRegPair zero;
2970 const Register g0 = G0; // without this we get a compiler warning (why??)
2971 zero.set2(g0->as_VMReg());
2973 int c_arg, j_arg;
2975 Register conversion_off = noreg;
2977 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2978 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2980 VMRegPair src = in_regs[j_arg];
2981 VMRegPair dst = out_regs[c_arg];
2983 #ifdef ASSERT
2984 if (src.first()->is_Register()) {
2985 assert(!reg_destroyed[src.first()->as_Register()->encoding()], "ack!");
2986 } else if (src.first()->is_FloatRegister()) {
2987 assert(!freg_destroyed[src.first()->as_FloatRegister()->encoding(
2988 FloatRegisterImpl::S)], "ack!");
2989 }
2990 if (dst.first()->is_Register()) {
2991 reg_destroyed[dst.first()->as_Register()->encoding()] = true;
2992 } else if (dst.first()->is_FloatRegister()) {
2993 freg_destroyed[dst.first()->as_FloatRegister()->encoding(
2994 FloatRegisterImpl::S)] = true;
2995 }
2996 #endif /* ASSERT */
2998 switch (in_sig_bt[j_arg]) {
2999 case T_ARRAY:
3000 case T_OBJECT:
3001 {
3002 if (out_sig_bt[c_arg] == T_BYTE || out_sig_bt[c_arg] == T_SHORT ||
3003 out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
3004 // need to unbox a one-slot value
3005 Register in_reg = L0;
3006 Register tmp = L2;
3007 if ( src.first()->is_reg() ) {
3008 in_reg = src.first()->as_Register();
3009 } else {
3010 assert(Assembler::is_simm13(reg2offset(src.first()) + STACK_BIAS),
3011 "must be");
3012 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, in_reg);
3013 }
3014 // If the final destination is an acceptable register
3015 if ( dst.first()->is_reg() ) {
3016 if ( dst.is_single_phys_reg() || out_sig_bt[c_arg] != T_LONG ) {
3017 tmp = dst.first()->as_Register();
3018 }
3019 }
3021 Label skipUnbox;
3022 if ( wordSize == 4 && out_sig_bt[c_arg] == T_LONG ) {
3023 __ mov(G0, tmp->successor());
3024 }
3025 __ br_null(in_reg, true, Assembler::pn, skipUnbox);
3026 __ delayed()->mov(G0, tmp);
3028 BasicType bt = out_sig_bt[c_arg];
3029 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
3030 switch (bt) {
3031 case T_BYTE:
3032 __ ldub(in_reg, box_offset, tmp); break;
3033 case T_SHORT:
3034 __ lduh(in_reg, box_offset, tmp); break;
3035 case T_INT:
3036 __ ld(in_reg, box_offset, tmp); break;
3037 case T_LONG:
3038 __ ld_long(in_reg, box_offset, tmp); break;
3039 default: ShouldNotReachHere();
3040 }
3042 __ bind(skipUnbox);
3043 // If tmp wasn't final destination copy to final destination
3044 if (tmp == L2) {
3045 VMRegPair tmp_as_VM = reg64_to_VMRegPair(L2);
3046 if (out_sig_bt[c_arg] == T_LONG) {
3047 long_move(masm, tmp_as_VM, dst);
3048 } else {
3049 move32_64(masm, tmp_as_VM, out_regs[c_arg]);
3050 }
3051 }
3052 if (out_sig_bt[c_arg] == T_LONG) {
3053 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
3054 ++c_arg; // move over the T_VOID to keep the loop indices in sync
3055 }
3056 } else if (out_sig_bt[c_arg] == T_ADDRESS) {
3057 Register s =
3058 src.first()->is_reg() ? src.first()->as_Register() : L2;
3059 Register d =
3060 dst.first()->is_reg() ? dst.first()->as_Register() : L2;
3062 // We store the oop now so that the conversion pass can reach
3063 // while in the inner frame. This will be the only store if
3064 // the oop is NULL.
3065 if (s != L2) {
3066 // src is register
3067 if (d != L2) {
3068 // dst is register
3069 __ mov(s, d);
3070 } else {
3071 assert(Assembler::is_simm13(reg2offset(dst.first()) +
3072 STACK_BIAS), "must be");
3073 __ st_ptr(s, SP, reg2offset(dst.first()) + STACK_BIAS);
3074 }
3075 } else {
3076 // src not a register
3077 assert(Assembler::is_simm13(reg2offset(src.first()) +
3078 STACK_BIAS), "must be");
3079 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, d);
3080 if (d == L2) {
3081 assert(Assembler::is_simm13(reg2offset(dst.first()) +
3082 STACK_BIAS), "must be");
3083 __ st_ptr(d, SP, reg2offset(dst.first()) + STACK_BIAS);
3084 }
3085 }
3086 } else if (out_sig_bt[c_arg] != T_VOID) {
3087 // Convert the arg to NULL
3088 if (dst.first()->is_reg()) {
3089 __ mov(G0, dst.first()->as_Register());
3090 } else {
3091 assert(Assembler::is_simm13(reg2offset(dst.first()) +
3092 STACK_BIAS), "must be");
3093 __ st_ptr(G0, SP, reg2offset(dst.first()) + STACK_BIAS);
3094 }
3095 }
3096 }
3097 break;
3098 case T_VOID:
3099 break;
3101 case T_FLOAT:
3102 if (src.first()->is_stack()) {
3103 // Stack to stack/reg is simple
3104 move32_64(masm, src, dst);
3105 } else {
3106 if (dst.first()->is_reg()) {
3107 // freg -> reg
3108 int off =
3109 STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
3110 Register d = dst.first()->as_Register();
3111 if (Assembler::is_simm13(off)) {
3112 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
3113 SP, off);
3114 __ ld(SP, off, d);
3115 } else {
3116 if (conversion_off == noreg) {
3117 __ set(off, L6);
3118 conversion_off = L6;
3119 }
3120 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
3121 SP, conversion_off);
3122 __ ld(SP, conversion_off , d);
3123 }
3124 } else {
3125 // freg -> mem
3126 int off = STACK_BIAS + reg2offset(dst.first());
3127 if (Assembler::is_simm13(off)) {
3128 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
3129 SP, off);
3130 } else {
3131 if (conversion_off == noreg) {
3132 __ set(off, L6);
3133 conversion_off = L6;
3134 }
3135 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
3136 SP, conversion_off);
3137 }
3138 }
3139 }
3140 break;
3142 case T_DOUBLE:
3143 assert( j_arg + 1 < total_args_passed &&
3144 in_sig_bt[j_arg + 1] == T_VOID &&
3145 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
3146 if (src.first()->is_stack()) {
3147 // Stack to stack/reg is simple
3148 long_move(masm, src, dst);
3149 } else {
3150 Register d = dst.first()->is_reg() ? dst.first()->as_Register() : L2;
3152 // Destination could be an odd reg on 32bit in which case
3153 // we can't load direct to the destination.
3155 if (!d->is_even() && wordSize == 4) {
3156 d = L2;
3157 }
3158 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
3159 if (Assembler::is_simm13(off)) {
3160 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
3161 SP, off);
3162 __ ld_long(SP, off, d);
3163 } else {
3164 if (conversion_off == noreg) {
3165 __ set(off, L6);
3166 conversion_off = L6;
3167 }
3168 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
3169 SP, conversion_off);
3170 __ ld_long(SP, conversion_off, d);
3171 }
3172 if (d == L2) {
3173 long_move(masm, reg64_to_VMRegPair(L2), dst);
3174 }
3175 }
3176 break;
3178 case T_LONG :
3179 // 32bit can't do a split move of something like g1 -> O0, O1
3180 // so use a memory temp
3181 if (src.is_single_phys_reg() && wordSize == 4) {
3182 Register tmp = L2;
3183 if (dst.first()->is_reg() &&
3184 (wordSize == 8 || dst.first()->as_Register()->is_even())) {
3185 tmp = dst.first()->as_Register();
3186 }
3188 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
3189 if (Assembler::is_simm13(off)) {
3190 __ stx(src.first()->as_Register(), SP, off);
3191 __ ld_long(SP, off, tmp);
3192 } else {
3193 if (conversion_off == noreg) {
3194 __ set(off, L6);
3195 conversion_off = L6;
3196 }
3197 __ stx(src.first()->as_Register(), SP, conversion_off);
3198 __ ld_long(SP, conversion_off, tmp);
3199 }
3201 if (tmp == L2) {
3202 long_move(masm, reg64_to_VMRegPair(L2), dst);
3203 }
3204 } else {
3205 long_move(masm, src, dst);
3206 }
3207 break;
3209 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
3211 default:
3212 move32_64(masm, src, dst);
3213 }
3214 }
3217 // If we have any strings we must store any register based arg to the stack
3218 // This includes any still live xmm registers too.
3220 if (total_strings > 0 ) {
3222 // protect all the arg registers
3223 __ save_frame(0);
3224 __ mov(G2_thread, L7_thread_cache);
3225 const Register L2_string_off = L2;
3227 // Get first string offset
3228 __ set(string_locs * VMRegImpl::stack_slot_size, L2_string_off);
3230 for (c_arg = 0 ; c_arg < total_c_args ; c_arg++ ) {
3231 if (out_sig_bt[c_arg] == T_ADDRESS) {
3233 VMRegPair dst = out_regs[c_arg];
3234 const Register d = dst.first()->is_reg() ?
3235 dst.first()->as_Register()->after_save() : noreg;
3237 // It's a string the oop and it was already copied to the out arg
3238 // position
3239 if (d != noreg) {
3240 __ mov(d, O0);
3241 } else {
3242 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
3243 "must be");
3244 __ ld_ptr(FP, reg2offset(dst.first()) + STACK_BIAS, O0);
3245 }
3246 Label skip;
3248 __ br_null(O0, false, Assembler::pn, skip);
3249 __ delayed()->add(FP, L2_string_off, O1);
3251 if (d != noreg) {
3252 __ mov(O1, d);
3253 } else {
3254 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
3255 "must be");
3256 __ st_ptr(O1, FP, reg2offset(dst.first()) + STACK_BIAS);
3257 }
3259 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::get_utf),
3260 relocInfo::runtime_call_type);
3261 __ delayed()->add(L2_string_off, max_dtrace_string_size, L2_string_off);
3263 __ bind(skip);
3265 }
3267 }
3268 __ mov(L7_thread_cache, G2_thread);
3269 __ restore();
3271 }
3274 // Ok now we are done. Need to place the nop that dtrace wants in order to
3275 // patch in the trap
3277 int patch_offset = ((intptr_t)__ pc()) - start;
3279 __ nop();
3282 // Return
3284 __ ret();
3285 __ delayed()->restore();
3287 __ flush();
3289 nmethod *nm = nmethod::new_dtrace_nmethod(
3290 method, masm->code(), vep_offset, patch_offset, frame_complete,
3291 stack_slots / VMRegImpl::slots_per_word);
3292 return nm;
3294 }
3296 #endif // HAVE_DTRACE_H
3298 // this function returns the adjust size (in number of words) to a c2i adapter
3299 // activation for use during deoptimization
3300 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) {
3301 assert(callee_locals >= callee_parameters,
3302 "test and remove; got more parms than locals");
3303 if (callee_locals < callee_parameters)
3304 return 0; // No adjustment for negative locals
3305 int diff = (callee_locals - callee_parameters) * Interpreter::stackElementWords;
3306 return round_to(diff, WordsPerLong);
3307 }
3309 // "Top of Stack" slots that may be unused by the calling convention but must
3310 // otherwise be preserved.
3311 // On Intel these are not necessary and the value can be zero.
3312 // On Sparc this describes the words reserved for storing a register window
3313 // when an interrupt occurs.
3314 uint SharedRuntime::out_preserve_stack_slots() {
3315 return frame::register_save_words * VMRegImpl::slots_per_word;
3316 }
3318 static void gen_new_frame(MacroAssembler* masm, bool deopt) {
3319 //
3320 // Common out the new frame generation for deopt and uncommon trap
3321 //
3322 Register G3pcs = G3_scratch; // Array of new pcs (input)
3323 Register Oreturn0 = O0;
3324 Register Oreturn1 = O1;
3325 Register O2UnrollBlock = O2;
3326 Register O3array = O3; // Array of frame sizes (input)
3327 Register O4array_size = O4; // number of frames (input)
3328 Register O7frame_size = O7; // number of frames (input)
3330 __ ld_ptr(O3array, 0, O7frame_size);
3331 __ sub(G0, O7frame_size, O7frame_size);
3332 __ save(SP, O7frame_size, SP);
3333 __ ld_ptr(G3pcs, 0, I7); // load frame's new pc
3335 #ifdef ASSERT
3336 // make sure that the frames are aligned properly
3337 #ifndef _LP64
3338 __ btst(wordSize*2-1, SP);
3339 __ breakpoint_trap(Assembler::notZero, Assembler::ptr_cc);
3340 #endif
3341 #endif
3343 // Deopt needs to pass some extra live values from frame to frame
3345 if (deopt) {
3346 __ mov(Oreturn0->after_save(), Oreturn0);
3347 __ mov(Oreturn1->after_save(), Oreturn1);
3348 }
3350 __ mov(O4array_size->after_save(), O4array_size);
3351 __ sub(O4array_size, 1, O4array_size);
3352 __ mov(O3array->after_save(), O3array);
3353 __ mov(O2UnrollBlock->after_save(), O2UnrollBlock);
3354 __ add(G3pcs, wordSize, G3pcs); // point to next pc value
3356 #ifdef ASSERT
3357 // trash registers to show a clear pattern in backtraces
3358 __ set(0xDEAD0000, I0);
3359 __ add(I0, 2, I1);
3360 __ add(I0, 4, I2);
3361 __ add(I0, 6, I3);
3362 __ add(I0, 8, I4);
3363 // Don't touch I5 could have valuable savedSP
3364 __ set(0xDEADBEEF, L0);
3365 __ mov(L0, L1);
3366 __ mov(L0, L2);
3367 __ mov(L0, L3);
3368 __ mov(L0, L4);
3369 __ mov(L0, L5);
3371 // trash the return value as there is nothing to return yet
3372 __ set(0xDEAD0001, O7);
3373 #endif
3375 __ mov(SP, O5_savedSP);
3376 }
3379 static void make_new_frames(MacroAssembler* masm, bool deopt) {
3380 //
3381 // loop through the UnrollBlock info and create new frames
3382 //
3383 Register G3pcs = G3_scratch;
3384 Register Oreturn0 = O0;
3385 Register Oreturn1 = O1;
3386 Register O2UnrollBlock = O2;
3387 Register O3array = O3;
3388 Register O4array_size = O4;
3389 Label loop;
3391 #ifdef ASSERT
3392 // Compilers generate code that bang the stack by as much as the
3393 // interpreter would need. So this stack banging should never
3394 // trigger a fault. Verify that it does not on non product builds.
3395 if (UseStackBanging) {
3396 // Get total frame size for interpreted frames
3397 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes(), O4);
3398 __ bang_stack_size(O4, O3, G3_scratch);
3399 }
3400 #endif
3402 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes(), O4array_size);
3403 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes(), G3pcs);
3404 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes(), O3array);
3406 // Adjust old interpreter frame to make space for new frame's extra java locals
3407 //
3408 // We capture the original sp for the transition frame only because it is needed in
3409 // order to properly calculate interpreter_sp_adjustment. Even though in real life
3410 // every interpreter frame captures a savedSP it is only needed at the transition
3411 // (fortunately). If we had to have it correct everywhere then we would need to
3412 // be told the sp_adjustment for each frame we create. If the frame size array
3413 // were to have twice the frame count entries then we could have pairs [sp_adjustment, frame_size]
3414 // for each frame we create and keep up the illusion every where.
3415 //
3417 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes(), O7);
3418 __ mov(SP, O5_savedSP); // remember initial sender's original sp before adjustment
3419 __ sub(SP, O7, SP);
3421 #ifdef ASSERT
3422 // make sure that there is at least one entry in the array
3423 __ tst(O4array_size);
3424 __ breakpoint_trap(Assembler::zero, Assembler::icc);
3425 #endif
3427 // Now push the new interpreter frames
3428 __ bind(loop);
3430 // allocate a new frame, filling the registers
3432 gen_new_frame(masm, deopt); // allocate an interpreter frame
3434 __ cmp_zero_and_br(Assembler::notZero, O4array_size, loop);
3435 __ delayed()->add(O3array, wordSize, O3array);
3436 __ ld_ptr(G3pcs, 0, O7); // load final frame new pc
3438 }
3440 //------------------------------generate_deopt_blob----------------------------
3441 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
3442 // instead.
3443 void SharedRuntime::generate_deopt_blob() {
3444 // allocate space for the code
3445 ResourceMark rm;
3446 // setup code generation tools
3447 int pad = VerifyThread ? 512 : 0;// Extra slop space for more verify code
3448 #ifdef ASSERT
3449 if (UseStackBanging) {
3450 pad += StackShadowPages*16 + 32;
3451 }
3452 #endif
3453 #ifdef _LP64
3454 CodeBuffer buffer("deopt_blob", 2100+pad, 512);
3455 #else
3456 // Measured 8/7/03 at 1212 in 32bit debug build (no VerifyThread)
3457 // Measured 8/7/03 at 1396 in 32bit debug build (VerifyThread)
3458 CodeBuffer buffer("deopt_blob", 1600+pad, 512);
3459 #endif /* _LP64 */
3460 MacroAssembler* masm = new MacroAssembler(&buffer);
3461 FloatRegister Freturn0 = F0;
3462 Register Greturn1 = G1;
3463 Register Oreturn0 = O0;
3464 Register Oreturn1 = O1;
3465 Register O2UnrollBlock = O2;
3466 Register L0deopt_mode = L0;
3467 Register G4deopt_mode = G4_scratch;
3468 int frame_size_words;
3469 Address saved_Freturn0_addr(FP, -sizeof(double) + STACK_BIAS);
3470 #if !defined(_LP64) && defined(COMPILER2)
3471 Address saved_Greturn1_addr(FP, -sizeof(double) -sizeof(jlong) + STACK_BIAS);
3472 #endif
3473 Label cont;
3475 OopMapSet *oop_maps = new OopMapSet();
3477 //
3478 // This is the entry point for code which is returning to a de-optimized
3479 // frame.
3480 // The steps taken by this frame are as follows:
3481 // - push a dummy "register_save" and save the return values (O0, O1, F0/F1, G1)
3482 // and all potentially live registers (at a pollpoint many registers can be live).
3483 //
3484 // - call the C routine: Deoptimization::fetch_unroll_info (this function
3485 // returns information about the number and size of interpreter frames
3486 // which are equivalent to the frame which is being deoptimized)
3487 // - deallocate the unpack frame, restoring only results values. Other
3488 // volatile registers will now be captured in the vframeArray as needed.
3489 // - deallocate the deoptimization frame
3490 // - in a loop using the information returned in the previous step
3491 // push new interpreter frames (take care to propagate the return
3492 // values through each new frame pushed)
3493 // - create a dummy "unpack_frame" and save the return values (O0, O1, F0)
3494 // - call the C routine: Deoptimization::unpack_frames (this function
3495 // lays out values on the interpreter frame which was just created)
3496 // - deallocate the dummy unpack_frame
3497 // - ensure that all the return values are correctly set and then do
3498 // a return to the interpreter entry point
3499 //
3500 // Refer to the following methods for more information:
3501 // - Deoptimization::fetch_unroll_info
3502 // - Deoptimization::unpack_frames
3504 OopMap* map = NULL;
3506 int start = __ offset();
3508 // restore G2, the trampoline destroyed it
3509 __ get_thread();
3511 // On entry we have been called by the deoptimized nmethod with a call that
3512 // replaced the original call (or safepoint polling location) so the deoptimizing
3513 // pc is now in O7. Return values are still in the expected places
3515 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3516 __ ba(cont);
3517 __ delayed()->mov(Deoptimization::Unpack_deopt, L0deopt_mode);
3519 int exception_offset = __ offset() - start;
3521 // restore G2, the trampoline destroyed it
3522 __ get_thread();
3524 // On entry we have been jumped to by the exception handler (or exception_blob
3525 // for server). O0 contains the exception oop and O7 contains the original
3526 // exception pc. So if we push a frame here it will look to the
3527 // stack walking code (fetch_unroll_info) just like a normal call so
3528 // state will be extracted normally.
3530 // save exception oop in JavaThread and fall through into the
3531 // exception_in_tls case since they are handled in same way except
3532 // for where the pending exception is kept.
3533 __ st_ptr(Oexception, G2_thread, JavaThread::exception_oop_offset());
3535 //
3536 // Vanilla deoptimization with an exception pending in exception_oop
3537 //
3538 int exception_in_tls_offset = __ offset() - start;
3540 // No need to update oop_map as each call to save_live_registers will produce identical oopmap
3541 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3543 // Restore G2_thread
3544 __ get_thread();
3546 #ifdef ASSERT
3547 {
3548 // verify that there is really an exception oop in exception_oop
3549 Label has_exception;
3550 __ ld_ptr(G2_thread, JavaThread::exception_oop_offset(), Oexception);
3551 __ br_notnull_short(Oexception, Assembler::pt, has_exception);
3552 __ stop("no exception in thread");
3553 __ bind(has_exception);
3555 // verify that there is no pending exception
3556 Label no_pending_exception;
3557 Address exception_addr(G2_thread, Thread::pending_exception_offset());
3558 __ ld_ptr(exception_addr, Oexception);
3559 __ br_null_short(Oexception, Assembler::pt, no_pending_exception);
3560 __ stop("must not have pending exception here");
3561 __ bind(no_pending_exception);
3562 }
3563 #endif
3565 __ ba(cont);
3566 __ delayed()->mov(Deoptimization::Unpack_exception, L0deopt_mode);;
3568 //
3569 // Reexecute entry, similar to c2 uncommon trap
3570 //
3571 int reexecute_offset = __ offset() - start;
3573 // No need to update oop_map as each call to save_live_registers will produce identical oopmap
3574 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3576 __ mov(Deoptimization::Unpack_reexecute, L0deopt_mode);
3578 __ bind(cont);
3580 __ set_last_Java_frame(SP, noreg);
3582 // do the call by hand so we can get the oopmap
3584 __ mov(G2_thread, L7_thread_cache);
3585 __ call(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info), relocInfo::runtime_call_type);
3586 __ delayed()->mov(G2_thread, O0);
3588 // Set an oopmap for the call site this describes all our saved volatile registers
3590 oop_maps->add_gc_map( __ offset()-start, map);
3592 __ mov(L7_thread_cache, G2_thread);
3594 __ reset_last_Java_frame();
3596 // NOTE: we know that only O0/O1 will be reloaded by restore_result_registers
3597 // so this move will survive
3599 __ mov(L0deopt_mode, G4deopt_mode);
3601 __ mov(O0, O2UnrollBlock->after_save());
3603 RegisterSaver::restore_result_registers(masm);
3605 Label noException;
3606 __ cmp_and_br_short(G4deopt_mode, Deoptimization::Unpack_exception, Assembler::notEqual, Assembler::pt, noException);
3608 // Move the pending exception from exception_oop to Oexception so
3609 // the pending exception will be picked up the interpreter.
3610 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), Oexception);
3611 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
3612 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset()));
3613 __ bind(noException);
3615 // deallocate the deoptimization frame taking care to preserve the return values
3616 __ mov(Oreturn0, Oreturn0->after_save());
3617 __ mov(Oreturn1, Oreturn1->after_save());
3618 __ mov(O2UnrollBlock, O2UnrollBlock->after_save());
3619 __ restore();
3621 // Allocate new interpreter frame(s) and possible c2i adapter frame
3623 make_new_frames(masm, true);
3625 // push a dummy "unpack_frame" taking care of float return values and
3626 // call Deoptimization::unpack_frames to have the unpacker layout
3627 // information in the interpreter frames just created and then return
3628 // to the interpreter entry point
3629 __ save(SP, -frame_size_words*wordSize, SP);
3630 __ stf(FloatRegisterImpl::D, Freturn0, saved_Freturn0_addr);
3631 #if !defined(_LP64)
3632 #if defined(COMPILER2)
3633 // 32-bit 1-register longs return longs in G1
3634 __ stx(Greturn1, saved_Greturn1_addr);
3635 #endif
3636 __ set_last_Java_frame(SP, noreg);
3637 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, G4deopt_mode);
3638 #else
3639 // LP64 uses g4 in set_last_Java_frame
3640 __ mov(G4deopt_mode, O1);
3641 __ set_last_Java_frame(SP, G0);
3642 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O1);
3643 #endif
3644 __ reset_last_Java_frame();
3645 __ ldf(FloatRegisterImpl::D, saved_Freturn0_addr, Freturn0);
3647 #if !defined(_LP64) && defined(COMPILER2)
3648 // In 32 bit, C2 returns longs in G1 so restore the saved G1 into
3649 // I0/I1 if the return value is long.
3650 Label not_long;
3651 __ cmp_and_br_short(O0,T_LONG, Assembler::notEqual, Assembler::pt, not_long);
3652 __ ldd(saved_Greturn1_addr,I0);
3653 __ bind(not_long);
3654 #endif
3655 __ ret();
3656 __ delayed()->restore();
3658 masm->flush();
3659 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_words);
3660 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
3661 }
3663 #ifdef COMPILER2
3665 //------------------------------generate_uncommon_trap_blob--------------------
3666 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
3667 // instead.
3668 void SharedRuntime::generate_uncommon_trap_blob() {
3669 // allocate space for the code
3670 ResourceMark rm;
3671 // setup code generation tools
3672 int pad = VerifyThread ? 512 : 0;
3673 #ifdef ASSERT
3674 if (UseStackBanging) {
3675 pad += StackShadowPages*16 + 32;
3676 }
3677 #endif
3678 #ifdef _LP64
3679 CodeBuffer buffer("uncommon_trap_blob", 2700+pad, 512);
3680 #else
3681 // Measured 8/7/03 at 660 in 32bit debug build (no VerifyThread)
3682 // Measured 8/7/03 at 1028 in 32bit debug build (VerifyThread)
3683 CodeBuffer buffer("uncommon_trap_blob", 2000+pad, 512);
3684 #endif
3685 MacroAssembler* masm = new MacroAssembler(&buffer);
3686 Register O2UnrollBlock = O2;
3687 Register O2klass_index = O2;
3689 //
3690 // This is the entry point for all traps the compiler takes when it thinks
3691 // it cannot handle further execution of compilation code. The frame is
3692 // deoptimized in these cases and converted into interpreter frames for
3693 // execution
3694 // The steps taken by this frame are as follows:
3695 // - push a fake "unpack_frame"
3696 // - call the C routine Deoptimization::uncommon_trap (this function
3697 // packs the current compiled frame into vframe arrays and returns
3698 // information about the number and size of interpreter frames which
3699 // are equivalent to the frame which is being deoptimized)
3700 // - deallocate the "unpack_frame"
3701 // - deallocate the deoptimization frame
3702 // - in a loop using the information returned in the previous step
3703 // push interpreter frames;
3704 // - create a dummy "unpack_frame"
3705 // - call the C routine: Deoptimization::unpack_frames (this function
3706 // lays out values on the interpreter frame which was just created)
3707 // - deallocate the dummy unpack_frame
3708 // - return to the interpreter entry point
3709 //
3710 // Refer to the following methods for more information:
3711 // - Deoptimization::uncommon_trap
3712 // - Deoptimization::unpack_frame
3714 // the unloaded class index is in O0 (first parameter to this blob)
3716 // push a dummy "unpack_frame"
3717 // and call Deoptimization::uncommon_trap to pack the compiled frame into
3718 // vframe array and return the UnrollBlock information
3719 __ save_frame(0);
3720 __ set_last_Java_frame(SP, noreg);
3721 __ mov(I0, O2klass_index);
3722 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap), G2_thread, O2klass_index);
3723 __ reset_last_Java_frame();
3724 __ mov(O0, O2UnrollBlock->after_save());
3725 __ restore();
3727 // deallocate the deoptimized frame taking care to preserve the return values
3728 __ mov(O2UnrollBlock, O2UnrollBlock->after_save());
3729 __ restore();
3731 // Allocate new interpreter frame(s) and possible c2i adapter frame
3733 make_new_frames(masm, false);
3735 // push a dummy "unpack_frame" taking care of float return values and
3736 // call Deoptimization::unpack_frames to have the unpacker layout
3737 // information in the interpreter frames just created and then return
3738 // to the interpreter entry point
3739 __ save_frame(0);
3740 __ set_last_Java_frame(SP, noreg);
3741 __ mov(Deoptimization::Unpack_uncommon_trap, O3); // indicate it is the uncommon trap case
3742 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O3);
3743 __ reset_last_Java_frame();
3744 __ ret();
3745 __ delayed()->restore();
3747 masm->flush();
3748 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, NULL, __ total_frame_size_in_bytes(0)/wordSize);
3749 }
3751 #endif // COMPILER2
3753 //------------------------------generate_handler_blob-------------------
3754 //
3755 // Generate a special Compile2Runtime blob that saves all registers, and sets
3756 // up an OopMap.
3757 //
3758 // This blob is jumped to (via a breakpoint and the signal handler) from a
3759 // safepoint in compiled code. On entry to this blob, O7 contains the
3760 // address in the original nmethod at which we should resume normal execution.
3761 // Thus, this blob looks like a subroutine which must preserve lots of
3762 // registers and return normally. Note that O7 is never register-allocated,
3763 // so it is guaranteed to be free here.
3764 //
3766 // The hardest part of what this blob must do is to save the 64-bit %o
3767 // registers in the 32-bit build. A simple 'save' turn the %o's to %i's and
3768 // an interrupt will chop off their heads. Making space in the caller's frame
3769 // first will let us save the 64-bit %o's before save'ing, but we cannot hand
3770 // the adjusted FP off to the GC stack-crawler: this will modify the caller's
3771 // SP and mess up HIS OopMaps. So we first adjust the caller's SP, then save
3772 // the 64-bit %o's, then do a save, then fixup the caller's SP (our FP).
3773 // Tricky, tricky, tricky...
3775 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_type) {
3776 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3778 // allocate space for the code
3779 ResourceMark rm;
3780 // setup code generation tools
3781 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread)
3782 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread)
3783 // even larger with TraceJumps
3784 int pad = TraceJumps ? 512 : 0;
3785 CodeBuffer buffer("handler_blob", 1600 + pad, 512);
3786 MacroAssembler* masm = new MacroAssembler(&buffer);
3787 int frame_size_words;
3788 OopMapSet *oop_maps = new OopMapSet();
3789 OopMap* map = NULL;
3791 int start = __ offset();
3793 bool cause_return = (poll_type == POLL_AT_RETURN);
3794 // If this causes a return before the processing, then do a "restore"
3795 if (cause_return) {
3796 __ restore();
3797 } else {
3798 // Make it look like we were called via the poll
3799 // so that frame constructor always sees a valid return address
3800 __ ld_ptr(G2_thread, in_bytes(JavaThread::saved_exception_pc_offset()), O7);
3801 __ sub(O7, frame::pc_return_offset, O7);
3802 }
3804 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3806 // setup last_Java_sp (blows G4)
3807 __ set_last_Java_frame(SP, noreg);
3809 // call into the runtime to handle illegal instructions exception
3810 // Do not use call_VM_leaf, because we need to make a GC map at this call site.
3811 __ mov(G2_thread, O0);
3812 __ save_thread(L7_thread_cache);
3813 __ call(call_ptr);
3814 __ delayed()->nop();
3816 // Set an oopmap for the call site.
3817 // We need this not only for callee-saved registers, but also for volatile
3818 // registers that the compiler might be keeping live across a safepoint.
3820 oop_maps->add_gc_map( __ offset() - start, map);
3822 __ restore_thread(L7_thread_cache);
3823 // clear last_Java_sp
3824 __ reset_last_Java_frame();
3826 // Check for exceptions
3827 Label pending;
3829 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1);
3830 __ br_notnull_short(O1, Assembler::pn, pending);
3832 RegisterSaver::restore_live_registers(masm);
3834 // We are back the the original state on entry and ready to go.
3836 __ retl();
3837 __ delayed()->nop();
3839 // Pending exception after the safepoint
3841 __ bind(pending);
3843 RegisterSaver::restore_live_registers(masm);
3845 // We are back the the original state on entry.
3847 // Tail-call forward_exception_entry, with the issuing PC in O7,
3848 // so it looks like the original nmethod called forward_exception_entry.
3849 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0);
3850 __ JMP(O0, 0);
3851 __ delayed()->nop();
3853 // -------------
3854 // make sure all code is generated
3855 masm->flush();
3857 // return exception blob
3858 return SafepointBlob::create(&buffer, oop_maps, frame_size_words);
3859 }
3861 //
3862 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss
3863 //
3864 // Generate a stub that calls into vm to find out the proper destination
3865 // of a java call. All the argument registers are live at this point
3866 // but since this is generic code we don't know what they are and the caller
3867 // must do any gc of the args.
3868 //
3869 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) {
3870 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3872 // allocate space for the code
3873 ResourceMark rm;
3874 // setup code generation tools
3875 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread)
3876 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread)
3877 // even larger with TraceJumps
3878 int pad = TraceJumps ? 512 : 0;
3879 CodeBuffer buffer(name, 1600 + pad, 512);
3880 MacroAssembler* masm = new MacroAssembler(&buffer);
3881 int frame_size_words;
3882 OopMapSet *oop_maps = new OopMapSet();
3883 OopMap* map = NULL;
3885 int start = __ offset();
3887 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3889 int frame_complete = __ offset();
3891 // setup last_Java_sp (blows G4)
3892 __ set_last_Java_frame(SP, noreg);
3894 // call into the runtime to handle illegal instructions exception
3895 // Do not use call_VM_leaf, because we need to make a GC map at this call site.
3896 __ mov(G2_thread, O0);
3897 __ save_thread(L7_thread_cache);
3898 __ call(destination, relocInfo::runtime_call_type);
3899 __ delayed()->nop();
3901 // O0 contains the address we are going to jump to assuming no exception got installed
3903 // Set an oopmap for the call site.
3904 // We need this not only for callee-saved registers, but also for volatile
3905 // registers that the compiler might be keeping live across a safepoint.
3907 oop_maps->add_gc_map( __ offset() - start, map);
3909 __ restore_thread(L7_thread_cache);
3910 // clear last_Java_sp
3911 __ reset_last_Java_frame();
3913 // Check for exceptions
3914 Label pending;
3916 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1);
3917 __ br_notnull_short(O1, Assembler::pn, pending);
3919 // get the returned Method*
3921 __ get_vm_result_2(G5_method);
3922 __ stx(G5_method, SP, RegisterSaver::G5_offset()+STACK_BIAS);
3924 // O0 is where we want to jump, overwrite G3 which is saved and scratch
3926 __ stx(O0, SP, RegisterSaver::G3_offset()+STACK_BIAS);
3928 RegisterSaver::restore_live_registers(masm);
3930 // We are back the the original state on entry and ready to go.
3932 __ JMP(G3, 0);
3933 __ delayed()->nop();
3935 // Pending exception after the safepoint
3937 __ bind(pending);
3939 RegisterSaver::restore_live_registers(masm);
3941 // We are back the the original state on entry.
3943 // Tail-call forward_exception_entry, with the issuing PC in O7,
3944 // so it looks like the original nmethod called forward_exception_entry.
3945 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0);
3946 __ JMP(O0, 0);
3947 __ delayed()->nop();
3949 // -------------
3950 // make sure all code is generated
3951 masm->flush();
3953 // return the blob
3954 // frame_size_words or bytes??
3955 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true);
3956 }