jdk8-mips64-public/hotspot: src/cpu/sparc/vm/vm_version

8002074: Support for AES on SPARC
Summary: Add intrinsics/stub routines support for single-block and multi-block (as used by Cipher Block Chaining mode) AES encryption and decryption operations on the SPARC platform.
Reviewed-by: kvn, roland
Contributed-by: shrinivas.joshi@oracle.com

     1 /*

     2  * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.

     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

     4  *

     5  * This code is free software; you can redistribute it and/or modify it

     6  * under the terms of the GNU General Public License version 2 only, as

     7  * published by the Free Software Foundation.

     8  *

     9  * This code is distributed in the hope that it will be useful, but WITHOUT

    10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

    12  * version 2 for more details (a copy is included in the LICENSE file that

    13  * accompanied this code).

    14  *

    15  * You should have received a copy of the GNU General Public License version

    16  * 2 along with this work; if not, write to the Free Software Foundation,

    17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

    18  *

    19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

    20  * or visit www.oracle.com if you need additional information or have any

    21  * questions.

    22  *

    23  */

    25 #ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP

    26 #define CPU_SPARC_VM_VM_VERSION_SPARC_HPP

    28 #include "runtime/globals_extension.hpp"

    29 #include "runtime/vm_version.hpp"

    31 class VM_Version: public Abstract_VM_Version {

    32 protected:

    33   enum Feature_Flag {

    34     v8_instructions      = 0,

    35     hardware_mul32       = 1,

    36     hardware_div32       = 2,

    37     hardware_fsmuld      = 3,

    38     hardware_popc        = 4,

    39     v9_instructions      = 5,

    40     vis1_instructions    = 6,

    41     vis2_instructions    = 7,

    42     sun4v_instructions   = 8,

    43     blk_init_instructions = 9,

    44     fmaf_instructions    = 10,

    45     fmau_instructions    = 11,

    46     vis3_instructions    = 12,

    47     cbcond_instructions  = 13,

    48     sparc64_family       = 14,

    49     M_family             = 15,

    50     T_family             = 16,

    51     T1_model             = 17,

    52     aes_instructions     = 18

    53   };

    55   enum Feature_Flag_Set {

    56     unknown_m           = 0,

    57     all_features_m      = -1,

    59     v8_instructions_m       = 1 << v8_instructions,

    60     hardware_mul32_m        = 1 << hardware_mul32,

    61     hardware_div32_m        = 1 << hardware_div32,

    62     hardware_fsmuld_m       = 1 << hardware_fsmuld,

    63     hardware_popc_m         = 1 << hardware_popc,

    64     v9_instructions_m       = 1 << v9_instructions,

    65     vis1_instructions_m     = 1 << vis1_instructions,

    66     vis2_instructions_m     = 1 << vis2_instructions,

    67     sun4v_m                 = 1 << sun4v_instructions,

    68     blk_init_instructions_m = 1 << blk_init_instructions,

    69     fmaf_instructions_m     = 1 << fmaf_instructions,

    70     fmau_instructions_m     = 1 << fmau_instructions,

    71     vis3_instructions_m     = 1 << vis3_instructions,

    72     cbcond_instructions_m   = 1 << cbcond_instructions,

    73     sparc64_family_m        = 1 << sparc64_family,

    74     M_family_m              = 1 << M_family,

    75     T_family_m              = 1 << T_family,

    76     T1_model_m              = 1 << T1_model,

    77     aes_instructions_m      = 1 << aes_instructions,

    79     generic_v8_m        = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m,

    80     generic_v9_m        = generic_v8_m | v9_instructions_m,

    81     ultra3_m            = generic_v9_m | vis1_instructions_m | vis2_instructions_m,

    83     // Temporary until we have something more accurate

    84     niagara1_unique_m   = sun4v_m,

    85     niagara1_m          = generic_v9_m | niagara1_unique_m

    86   };

    88   static int  _features;

    89   static const char* _features_str;

    91   static void print_features();

    92   static int  determine_features();

    93   static int  platform_features(int features);

    95   // Returns true if the platform is in the niagara line (T series)

    96   static bool is_M_family(int features) { return (features & M_family_m) != 0; }

    97   static bool is_T_family(int features) { return (features & T_family_m) != 0; }

    98   static bool is_niagara() { return is_T_family(_features); }

    99 #ifdef ASSERT

   100   static bool is_niagara(int features)  {

   101     // 'sun4v_m' may be defined on both Sun/Oracle Sparc CPUs as well as

   102     // on Fujitsu Sparc64 CPUs, but only Sun/Oracle Sparcs can be 'niagaras'.

   103     return (features & sun4v_m) != 0 && (features & sparc64_family_m) == 0;

   104   }

   105 #endif

   107   // Returns true if it is niagara1 (T1).

   108   static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); }

   110   static int maximum_niagara1_processor_count() { return 32; }

   112 public:

   113   // Initialization

   114   static void initialize();

   116   // Instruction support

   117   static bool has_v8()                  { return (_features & v8_instructions_m) != 0; }

   118   static bool has_v9()                  { return (_features & v9_instructions_m) != 0; }

   119   static bool has_hardware_mul32()      { return (_features & hardware_mul32_m) != 0; }

   120   static bool has_hardware_div32()      { return (_features & hardware_div32_m) != 0; }

   121   static bool has_hardware_fsmuld()     { return (_features & hardware_fsmuld_m) != 0; }

   122   static bool has_hardware_popc()       { return (_features & hardware_popc_m) != 0; }

   123   static bool has_vis1()                { return (_features & vis1_instructions_m) != 0; }

   124   static bool has_vis2()                { return (_features & vis2_instructions_m) != 0; }

   125   static bool has_vis3()                { return (_features & vis3_instructions_m) != 0; }

   126   static bool has_blk_init()            { return (_features & blk_init_instructions_m) != 0; }

   127   static bool has_cbcond()              { return (_features & cbcond_instructions_m) != 0; }

   128   static bool has_aes()                 { return (_features & aes_instructions_m) != 0; }

   130   static bool supports_compare_and_exchange()

   131                                         { return has_v9(); }

   133   // Returns true if the platform is in the niagara line (T series)

   134   // and newer than the niagara1.

   135   static bool is_niagara_plus()         { return is_T_family(_features) && !is_T1_model(_features); }

   137   static bool is_M_series()             { return is_M_family(_features); }

   138   static bool is_T4()                   { return is_T_family(_features) && has_cbcond(); }

   140   // Fujitsu SPARC64

   141   static bool is_sparc64()              { return (_features & sparc64_family_m) != 0; }

   143   static bool is_sun4v()                { return (_features & sun4v_m) != 0; }

   144   static bool is_ultra3()               { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); }

   146   static bool has_fast_fxtof()          { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); }

   147   static bool has_fast_idiv()           { return is_niagara_plus() || is_sparc64(); }

   149   // T4 and newer Sparc have fast RDPC instruction.

   150   static bool has_fast_rdpc()           { return is_T4(); }

   152   // On T4 and newer Sparc BIS to the beginning of cache line always zeros it.

   153   static bool has_block_zeroing()       { return has_blk_init() && is_T4(); }

   155   static const char* cpu_features()     { return _features_str; }

   157   static intx prefetch_data_size()  {

   158     return is_T4() ? 32 : 64;  // default prefetch block size on sparc

   159   }

   161   // Prefetch

   162   static intx prefetch_copy_interval_in_bytes() {

   163     intx interval = PrefetchCopyIntervalInBytes;

   164     return interval >= 0 ? interval : (has_v9() ? 512 : 0);

   165   }

   166   static intx prefetch_scan_interval_in_bytes() {

   167     intx interval = PrefetchScanIntervalInBytes;

   168     return interval >= 0 ? interval : (has_v9() ? 512 : 0);

   169   }

   170   static intx prefetch_fields_ahead() {

   171     intx count = PrefetchFieldsAhead;

   172     return count >= 0 ? count : (is_ultra3() ? 1 : 0);

   173   }

   175   static intx allocate_prefetch_distance() {

   176     // This method should be called before allocate_prefetch_style().

   177     intx count = AllocatePrefetchDistance;

   178     if (count < 0) { // default is not defined ?

   179       count = 512;

   180     }

   181     return count;

   182   }

   183   static intx allocate_prefetch_style() {

   184     assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");

   185     // Return 0 if AllocatePrefetchDistance was not defined.

   186     return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;

   187   }

   189   // Assembler testing

   190   static void allow_all();

   191   static void revert();

   193   // Override the Abstract_VM_Version implementation.

   194   static uint page_size_count() { return is_sun4v() ? 4 : 2; }

   196   // Calculates the number of parallel threads

   197   static unsigned int calc_parallel_worker_threads();

   198 };

   200 #endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP

src/cpu/sparc/vm/vm_version_sparc.hpp@04d32e7fad07

src/cpu/sparc/vm/vm_version_sparc.hpp

Mercurial > jdk8-mips64-public > hotspot / file revision

src/cpu/sparc/vm/vm_version_sparc.hpp@04d32e7fad07

src/cpu/sparc/vm/vm_version_sparc.hpp