Wed, 13 Mar 2013 09:44:45 +0100
8009761: Deoptimization on sparc doesn't set Llast_SP correctly in the interpreter frames it creates
Summary: deoptimization doesn't set up callee frames so that they restore caller frames correctly.
Reviewed-by: kvn
1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #include "precompiled.hpp"
26 #include "asm/assembler.inline.hpp"
27 #include "compiler/disassembler.hpp"
28 #include "gc_interface/collectedHeap.inline.hpp"
29 #include "interpreter/interpreter.hpp"
30 #include "memory/cardTableModRefBS.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
42 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc_implementation/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
54 // Convert the raw encoding form into the form expected by the
55 // constructor for Address.
56 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
57 assert(scale == 0, "not supported");
58 RelocationHolder rspec;
59 if (disp_reloc != relocInfo::none) {
60 rspec = Relocation::spec_simple(disp_reloc);
61 }
63 Register rindex = as_Register(index);
64 if (rindex != G0) {
65 Address madr(as_Register(base), rindex);
66 madr._rspec = rspec;
67 return madr;
68 } else {
69 Address madr(as_Register(base), disp);
70 madr._rspec = rspec;
71 return madr;
72 }
73 }
75 Address Argument::address_in_frame() const {
76 // Warning: In LP64 mode disp will occupy more than 10 bits, but
77 // op codes such as ld or ldx, only access disp() to get
78 // their simm13 argument.
79 int disp = ((_number - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS;
80 if (is_in())
81 return Address(FP, disp); // In argument.
82 else
83 return Address(SP, disp); // Out argument.
84 }
86 static const char* argumentNames[][2] = {
87 {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"},
88 {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"},
89 {"A(n>9)","P(n>9)"}
90 };
92 const char* Argument::name() const {
93 int nofArgs = sizeof argumentNames / sizeof argumentNames[0];
94 int num = number();
95 if (num >= nofArgs) num = nofArgs - 1;
96 return argumentNames[num][is_in() ? 1 : 0];
97 }
99 #ifdef ASSERT
100 // On RISC, there's no benefit to verifying instruction boundaries.
101 bool AbstractAssembler::pd_check_instruction_mark() { return false; }
102 #endif
104 // Patch instruction inst at offset inst_pos to refer to dest_pos
105 // and return the resulting instruction.
106 // We should have pcs, not offsets, but since all is relative, it will work out
107 // OK.
108 int MacroAssembler::patched_branch(int dest_pos, int inst, int inst_pos) {
109 int m; // mask for displacement field
110 int v; // new value for displacement field
111 const int word_aligned_ones = -4;
112 switch (inv_op(inst)) {
113 default: ShouldNotReachHere();
114 case call_op: m = wdisp(word_aligned_ones, 0, 30); v = wdisp(dest_pos, inst_pos, 30); break;
115 case branch_op:
116 switch (inv_op2(inst)) {
117 case fbp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break;
118 case bp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break;
119 case fb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break;
120 case br_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break;
121 case cb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break;
122 case bpr_op2: {
123 if (is_cbcond(inst)) {
124 m = wdisp10(word_aligned_ones, 0);
125 v = wdisp10(dest_pos, inst_pos);
126 } else {
127 m = wdisp16(word_aligned_ones, 0);
128 v = wdisp16(dest_pos, inst_pos);
129 }
130 break;
131 }
132 default: ShouldNotReachHere();
133 }
134 }
135 return inst & ~m | v;
136 }
138 // Return the offset of the branch destionation of instruction inst
139 // at offset pos.
140 // Should have pcs, but since all is relative, it works out.
141 int MacroAssembler::branch_destination(int inst, int pos) {
142 int r;
143 switch (inv_op(inst)) {
144 default: ShouldNotReachHere();
145 case call_op: r = inv_wdisp(inst, pos, 30); break;
146 case branch_op:
147 switch (inv_op2(inst)) {
148 case fbp_op2: r = inv_wdisp( inst, pos, 19); break;
149 case bp_op2: r = inv_wdisp( inst, pos, 19); break;
150 case fb_op2: r = inv_wdisp( inst, pos, 22); break;
151 case br_op2: r = inv_wdisp( inst, pos, 22); break;
152 case cb_op2: r = inv_wdisp( inst, pos, 22); break;
153 case bpr_op2: {
154 if (is_cbcond(inst)) {
155 r = inv_wdisp10(inst, pos);
156 } else {
157 r = inv_wdisp16(inst, pos);
158 }
159 break;
160 }
161 default: ShouldNotReachHere();
162 }
163 }
164 return r;
165 }
167 void MacroAssembler::null_check(Register reg, int offset) {
168 if (needs_explicit_null_check((intptr_t)offset)) {
169 // provoke OS NULL exception if reg = NULL by
170 // accessing M[reg] w/o changing any registers
171 ld_ptr(reg, 0, G0);
172 }
173 else {
174 // nothing to do, (later) access of M[reg + offset]
175 // will provoke OS NULL exception if reg = NULL
176 }
177 }
179 // Ring buffer jumps
181 #ifndef PRODUCT
182 void MacroAssembler::ret( bool trace ) { if (trace) {
183 mov(I7, O7); // traceable register
184 JMP(O7, 2 * BytesPerInstWord);
185 } else {
186 jmpl( I7, 2 * BytesPerInstWord, G0 );
187 }
188 }
190 void MacroAssembler::retl( bool trace ) { if (trace) JMP(O7, 2 * BytesPerInstWord);
191 else jmpl( O7, 2 * BytesPerInstWord, G0 ); }
192 #endif /* PRODUCT */
195 void MacroAssembler::jmp2(Register r1, Register r2, const char* file, int line ) {
196 assert_not_delayed();
197 // This can only be traceable if r1 & r2 are visible after a window save
198 if (TraceJumps) {
199 #ifndef PRODUCT
200 save_frame(0);
201 verify_thread();
202 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
203 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
204 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
205 add(O2, O1, O1);
207 add(r1->after_save(), r2->after_save(), O2);
208 set((intptr_t)file, O3);
209 set(line, O4);
210 Label L;
211 // get nearby pc, store jmp target
212 call(L, relocInfo::none); // No relocation for call to pc+0x8
213 delayed()->st(O2, O1, 0);
214 bind(L);
216 // store nearby pc
217 st(O7, O1, sizeof(intptr_t));
218 // store file
219 st(O3, O1, 2*sizeof(intptr_t));
220 // store line
221 st(O4, O1, 3*sizeof(intptr_t));
222 add(O0, 1, O0);
223 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
224 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
225 restore();
226 #endif /* PRODUCT */
227 }
228 jmpl(r1, r2, G0);
229 }
230 void MacroAssembler::jmp(Register r1, int offset, const char* file, int line ) {
231 assert_not_delayed();
232 // This can only be traceable if r1 is visible after a window save
233 if (TraceJumps) {
234 #ifndef PRODUCT
235 save_frame(0);
236 verify_thread();
237 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
238 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
239 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
240 add(O2, O1, O1);
242 add(r1->after_save(), offset, O2);
243 set((intptr_t)file, O3);
244 set(line, O4);
245 Label L;
246 // get nearby pc, store jmp target
247 call(L, relocInfo::none); // No relocation for call to pc+0x8
248 delayed()->st(O2, O1, 0);
249 bind(L);
251 // store nearby pc
252 st(O7, O1, sizeof(intptr_t));
253 // store file
254 st(O3, O1, 2*sizeof(intptr_t));
255 // store line
256 st(O4, O1, 3*sizeof(intptr_t));
257 add(O0, 1, O0);
258 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
259 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
260 restore();
261 #endif /* PRODUCT */
262 }
263 jmp(r1, offset);
264 }
266 // This code sequence is relocatable to any address, even on LP64.
267 void MacroAssembler::jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line) {
268 assert_not_delayed();
269 // Force fixed length sethi because NativeJump and NativeFarCall don't handle
270 // variable length instruction streams.
271 patchable_sethi(addrlit, temp);
272 Address a(temp, addrlit.low10() + offset); // Add the offset to the displacement.
273 if (TraceJumps) {
274 #ifndef PRODUCT
275 // Must do the add here so relocation can find the remainder of the
276 // value to be relocated.
277 add(a.base(), a.disp(), a.base(), addrlit.rspec(offset));
278 save_frame(0);
279 verify_thread();
280 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
281 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
282 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
283 add(O2, O1, O1);
285 set((intptr_t)file, O3);
286 set(line, O4);
287 Label L;
289 // get nearby pc, store jmp target
290 call(L, relocInfo::none); // No relocation for call to pc+0x8
291 delayed()->st(a.base()->after_save(), O1, 0);
292 bind(L);
294 // store nearby pc
295 st(O7, O1, sizeof(intptr_t));
296 // store file
297 st(O3, O1, 2*sizeof(intptr_t));
298 // store line
299 st(O4, O1, 3*sizeof(intptr_t));
300 add(O0, 1, O0);
301 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
302 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
303 restore();
304 jmpl(a.base(), G0, d);
305 #else
306 jmpl(a.base(), a.disp(), d);
307 #endif /* PRODUCT */
308 } else {
309 jmpl(a.base(), a.disp(), d);
310 }
311 }
313 void MacroAssembler::jump(const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line) {
314 jumpl(addrlit, temp, G0, offset, file, line);
315 }
318 // Conditional breakpoint (for assertion checks in assembly code)
319 void MacroAssembler::breakpoint_trap(Condition c, CC cc) {
320 trap(c, cc, G0, ST_RESERVED_FOR_USER_0);
321 }
323 // We want to use ST_BREAKPOINT here, but the debugger is confused by it.
324 void MacroAssembler::breakpoint_trap() {
325 trap(ST_RESERVED_FOR_USER_0);
326 }
328 // flush windows (except current) using flushw instruction if avail.
329 void MacroAssembler::flush_windows() {
330 if (VM_Version::v9_instructions_work()) flushw();
331 else flush_windows_trap();
332 }
334 // Write serialization page so VM thread can do a pseudo remote membar
335 // We use the current thread pointer to calculate a thread specific
336 // offset to write to within the page. This minimizes bus traffic
337 // due to cache line collision.
338 void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) {
339 srl(thread, os::get_serialize_page_shift_count(), tmp2);
340 if (Assembler::is_simm13(os::vm_page_size())) {
341 and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2);
342 }
343 else {
344 set((os::vm_page_size() - sizeof(int)), tmp1);
345 and3(tmp2, tmp1, tmp2);
346 }
347 set(os::get_memory_serialize_page(), tmp1);
348 st(G0, tmp1, tmp2);
349 }
353 void MacroAssembler::enter() {
354 Unimplemented();
355 }
357 void MacroAssembler::leave() {
358 Unimplemented();
359 }
361 void MacroAssembler::mult(Register s1, Register s2, Register d) {
362 if(VM_Version::v9_instructions_work()) {
363 mulx (s1, s2, d);
364 } else {
365 smul (s1, s2, d);
366 }
367 }
369 void MacroAssembler::mult(Register s1, int simm13a, Register d) {
370 if(VM_Version::v9_instructions_work()) {
371 mulx (s1, simm13a, d);
372 } else {
373 smul (s1, simm13a, d);
374 }
375 }
378 #ifdef ASSERT
379 void MacroAssembler::read_ccr_v8_assert(Register ccr_save) {
380 const Register s1 = G3_scratch;
381 const Register s2 = G4_scratch;
382 Label get_psr_test;
383 // Get the condition codes the V8 way.
384 read_ccr_trap(s1);
385 mov(ccr_save, s2);
386 // This is a test of V8 which has icc but not xcc
387 // so mask off the xcc bits
388 and3(s2, 0xf, s2);
389 // Compare condition codes from the V8 and V9 ways.
390 subcc(s2, s1, G0);
391 br(Assembler::notEqual, true, Assembler::pt, get_psr_test);
392 delayed()->breakpoint_trap();
393 bind(get_psr_test);
394 }
396 void MacroAssembler::write_ccr_v8_assert(Register ccr_save) {
397 const Register s1 = G3_scratch;
398 const Register s2 = G4_scratch;
399 Label set_psr_test;
400 // Write out the saved condition codes the V8 way
401 write_ccr_trap(ccr_save, s1, s2);
402 // Read back the condition codes using the V9 instruction
403 rdccr(s1);
404 mov(ccr_save, s2);
405 // This is a test of V8 which has icc but not xcc
406 // so mask off the xcc bits
407 and3(s2, 0xf, s2);
408 and3(s1, 0xf, s1);
409 // Compare the V8 way with the V9 way.
410 subcc(s2, s1, G0);
411 br(Assembler::notEqual, true, Assembler::pt, set_psr_test);
412 delayed()->breakpoint_trap();
413 bind(set_psr_test);
414 }
415 #else
416 #define read_ccr_v8_assert(x)
417 #define write_ccr_v8_assert(x)
418 #endif // ASSERT
420 void MacroAssembler::read_ccr(Register ccr_save) {
421 if (VM_Version::v9_instructions_work()) {
422 rdccr(ccr_save);
423 // Test code sequence used on V8. Do not move above rdccr.
424 read_ccr_v8_assert(ccr_save);
425 } else {
426 read_ccr_trap(ccr_save);
427 }
428 }
430 void MacroAssembler::write_ccr(Register ccr_save) {
431 if (VM_Version::v9_instructions_work()) {
432 // Test code sequence used on V8. Do not move below wrccr.
433 write_ccr_v8_assert(ccr_save);
434 wrccr(ccr_save);
435 } else {
436 const Register temp_reg1 = G3_scratch;
437 const Register temp_reg2 = G4_scratch;
438 write_ccr_trap(ccr_save, temp_reg1, temp_reg2);
439 }
440 }
443 // Calls to C land
445 #ifdef ASSERT
446 // a hook for debugging
447 static Thread* reinitialize_thread() {
448 return ThreadLocalStorage::thread();
449 }
450 #else
451 #define reinitialize_thread ThreadLocalStorage::thread
452 #endif
454 #ifdef ASSERT
455 address last_get_thread = NULL;
456 #endif
458 // call this when G2_thread is not known to be valid
459 void MacroAssembler::get_thread() {
460 save_frame(0); // to avoid clobbering O0
461 mov(G1, L0); // avoid clobbering G1
462 mov(G5_method, L1); // avoid clobbering G5
463 mov(G3, L2); // avoid clobbering G3 also
464 mov(G4, L5); // avoid clobbering G4
465 #ifdef ASSERT
466 AddressLiteral last_get_thread_addrlit(&last_get_thread);
467 set(last_get_thread_addrlit, L3);
468 inc(L4, get_pc(L4) + 2 * BytesPerInstWord); // skip getpc() code + inc + st_ptr to point L4 at call
469 st_ptr(L4, L3, 0);
470 #endif
471 call(CAST_FROM_FN_PTR(address, reinitialize_thread), relocInfo::runtime_call_type);
472 delayed()->nop();
473 mov(L0, G1);
474 mov(L1, G5_method);
475 mov(L2, G3);
476 mov(L5, G4);
477 restore(O0, 0, G2_thread);
478 }
480 static Thread* verify_thread_subroutine(Thread* gthread_value) {
481 Thread* correct_value = ThreadLocalStorage::thread();
482 guarantee(gthread_value == correct_value, "G2_thread value must be the thread");
483 return correct_value;
484 }
486 void MacroAssembler::verify_thread() {
487 if (VerifyThread) {
488 // NOTE: this chops off the heads of the 64-bit O registers.
489 #ifdef CC_INTERP
490 save_frame(0);
491 #else
492 // make sure G2_thread contains the right value
493 save_frame_and_mov(0, Lmethod, Lmethod); // to avoid clobbering O0 (and propagate Lmethod for -Xprof)
494 mov(G1, L1); // avoid clobbering G1
495 // G2 saved below
496 mov(G3, L3); // avoid clobbering G3
497 mov(G4, L4); // avoid clobbering G4
498 mov(G5_method, L5); // avoid clobbering G5_method
499 #endif /* CC_INTERP */
500 #if defined(COMPILER2) && !defined(_LP64)
501 // Save & restore possible 64-bit Long arguments in G-regs
502 srlx(G1,32,L0);
503 srlx(G4,32,L6);
504 #endif
505 call(CAST_FROM_FN_PTR(address,verify_thread_subroutine), relocInfo::runtime_call_type);
506 delayed()->mov(G2_thread, O0);
508 mov(L1, G1); // Restore G1
509 // G2 restored below
510 mov(L3, G3); // restore G3
511 mov(L4, G4); // restore G4
512 mov(L5, G5_method); // restore G5_method
513 #if defined(COMPILER2) && !defined(_LP64)
514 // Save & restore possible 64-bit Long arguments in G-regs
515 sllx(L0,32,G2); // Move old high G1 bits high in G2
516 srl(G1, 0,G1); // Clear current high G1 bits
517 or3 (G1,G2,G1); // Recover 64-bit G1
518 sllx(L6,32,G2); // Move old high G4 bits high in G2
519 srl(G4, 0,G4); // Clear current high G4 bits
520 or3 (G4,G2,G4); // Recover 64-bit G4
521 #endif
522 restore(O0, 0, G2_thread);
523 }
524 }
527 void MacroAssembler::save_thread(const Register thread_cache) {
528 verify_thread();
529 if (thread_cache->is_valid()) {
530 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile");
531 mov(G2_thread, thread_cache);
532 }
533 if (VerifyThread) {
534 // smash G2_thread, as if the VM were about to anyway
535 set(0x67676767, G2_thread);
536 }
537 }
540 void MacroAssembler::restore_thread(const Register thread_cache) {
541 if (thread_cache->is_valid()) {
542 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile");
543 mov(thread_cache, G2_thread);
544 verify_thread();
545 } else {
546 // do it the slow way
547 get_thread();
548 }
549 }
552 // %%% maybe get rid of [re]set_last_Java_frame
553 void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) {
554 assert_not_delayed();
555 Address flags(G2_thread, JavaThread::frame_anchor_offset() +
556 JavaFrameAnchor::flags_offset());
557 Address pc_addr(G2_thread, JavaThread::last_Java_pc_offset());
559 // Always set last_Java_pc and flags first because once last_Java_sp is visible
560 // has_last_Java_frame is true and users will look at the rest of the fields.
561 // (Note: flags should always be zero before we get here so doesn't need to be set.)
563 #ifdef ASSERT
564 // Verify that flags was zeroed on return to Java
565 Label PcOk;
566 save_frame(0); // to avoid clobbering O0
567 ld_ptr(pc_addr, L0);
568 br_null_short(L0, Assembler::pt, PcOk);
569 STOP("last_Java_pc not zeroed before leaving Java");
570 bind(PcOk);
572 // Verify that flags was zeroed on return to Java
573 Label FlagsOk;
574 ld(flags, L0);
575 tst(L0);
576 br(Assembler::zero, false, Assembler::pt, FlagsOk);
577 delayed() -> restore();
578 STOP("flags not zeroed before leaving Java");
579 bind(FlagsOk);
580 #endif /* ASSERT */
581 //
582 // When returning from calling out from Java mode the frame anchor's last_Java_pc
583 // will always be set to NULL. It is set here so that if we are doing a call to
584 // native (not VM) that we capture the known pc and don't have to rely on the
585 // native call having a standard frame linkage where we can find the pc.
587 if (last_Java_pc->is_valid()) {
588 st_ptr(last_Java_pc, pc_addr);
589 }
591 #ifdef _LP64
592 #ifdef ASSERT
593 // Make sure that we have an odd stack
594 Label StackOk;
595 andcc(last_java_sp, 0x01, G0);
596 br(Assembler::notZero, false, Assembler::pt, StackOk);
597 delayed()->nop();
598 STOP("Stack Not Biased in set_last_Java_frame");
599 bind(StackOk);
600 #endif // ASSERT
601 assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame");
602 add( last_java_sp, STACK_BIAS, G4_scratch );
603 st_ptr(G4_scratch, G2_thread, JavaThread::last_Java_sp_offset());
604 #else
605 st_ptr(last_java_sp, G2_thread, JavaThread::last_Java_sp_offset());
606 #endif // _LP64
607 }
609 void MacroAssembler::reset_last_Java_frame(void) {
610 assert_not_delayed();
612 Address sp_addr(G2_thread, JavaThread::last_Java_sp_offset());
613 Address pc_addr(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
614 Address flags (G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
616 #ifdef ASSERT
617 // check that it WAS previously set
618 #ifdef CC_INTERP
619 save_frame(0);
620 #else
621 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod to helper frame for -Xprof
622 #endif /* CC_INTERP */
623 ld_ptr(sp_addr, L0);
624 tst(L0);
625 breakpoint_trap(Assembler::zero, Assembler::ptr_cc);
626 restore();
627 #endif // ASSERT
629 st_ptr(G0, sp_addr);
630 // Always return last_Java_pc to zero
631 st_ptr(G0, pc_addr);
632 // Always null flags after return to Java
633 st(G0, flags);
634 }
637 void MacroAssembler::call_VM_base(
638 Register oop_result,
639 Register thread_cache,
640 Register last_java_sp,
641 address entry_point,
642 int number_of_arguments,
643 bool check_exceptions)
644 {
645 assert_not_delayed();
647 // determine last_java_sp register
648 if (!last_java_sp->is_valid()) {
649 last_java_sp = SP;
650 }
651 // debugging support
652 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
654 // 64-bit last_java_sp is biased!
655 set_last_Java_frame(last_java_sp, noreg);
656 if (VerifyThread) mov(G2_thread, O0); // about to be smashed; pass early
657 save_thread(thread_cache);
658 // do the call
659 call(entry_point, relocInfo::runtime_call_type);
660 if (!VerifyThread)
661 delayed()->mov(G2_thread, O0); // pass thread as first argument
662 else
663 delayed()->nop(); // (thread already passed)
664 restore_thread(thread_cache);
665 reset_last_Java_frame();
667 // check for pending exceptions. use Gtemp as scratch register.
668 if (check_exceptions) {
669 check_and_forward_exception(Gtemp);
670 }
672 #ifdef ASSERT
673 set(badHeapWordVal, G3);
674 set(badHeapWordVal, G4);
675 set(badHeapWordVal, G5);
676 #endif
678 // get oop result if there is one and reset the value in the thread
679 if (oop_result->is_valid()) {
680 get_vm_result(oop_result);
681 }
682 }
684 void MacroAssembler::check_and_forward_exception(Register scratch_reg)
685 {
686 Label L;
688 check_and_handle_popframe(scratch_reg);
689 check_and_handle_earlyret(scratch_reg);
691 Address exception_addr(G2_thread, Thread::pending_exception_offset());
692 ld_ptr(exception_addr, scratch_reg);
693 br_null_short(scratch_reg, pt, L);
694 // we use O7 linkage so that forward_exception_entry has the issuing PC
695 call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type);
696 delayed()->nop();
697 bind(L);
698 }
701 void MacroAssembler::check_and_handle_popframe(Register scratch_reg) {
702 }
705 void MacroAssembler::check_and_handle_earlyret(Register scratch_reg) {
706 }
709 void MacroAssembler::call_VM(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
710 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
711 }
714 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) {
715 // O0 is reserved for the thread
716 mov(arg_1, O1);
717 call_VM(oop_result, entry_point, 1, check_exceptions);
718 }
721 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
722 // O0 is reserved for the thread
723 mov(arg_1, O1);
724 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
725 call_VM(oop_result, entry_point, 2, check_exceptions);
726 }
729 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
730 // O0 is reserved for the thread
731 mov(arg_1, O1);
732 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
733 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument");
734 call_VM(oop_result, entry_point, 3, check_exceptions);
735 }
739 // Note: The following call_VM overloadings are useful when a "save"
740 // has already been performed by a stub, and the last Java frame is
741 // the previous one. In that case, last_java_sp must be passed as FP
742 // instead of SP.
745 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) {
746 call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions);
747 }
750 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) {
751 // O0 is reserved for the thread
752 mov(arg_1, O1);
753 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
754 }
757 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
758 // O0 is reserved for the thread
759 mov(arg_1, O1);
760 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
761 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
762 }
765 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
766 // O0 is reserved for the thread
767 mov(arg_1, O1);
768 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
769 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument");
770 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
771 }
775 void MacroAssembler::call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments) {
776 assert_not_delayed();
777 save_thread(thread_cache);
778 // do the call
779 call(entry_point, relocInfo::runtime_call_type);
780 delayed()->nop();
781 restore_thread(thread_cache);
782 #ifdef ASSERT
783 set(badHeapWordVal, G3);
784 set(badHeapWordVal, G4);
785 set(badHeapWordVal, G5);
786 #endif
787 }
790 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments) {
791 call_VM_leaf_base(thread_cache, entry_point, number_of_arguments);
792 }
795 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1) {
796 mov(arg_1, O0);
797 call_VM_leaf(thread_cache, entry_point, 1);
798 }
801 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2) {
802 mov(arg_1, O0);
803 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument");
804 call_VM_leaf(thread_cache, entry_point, 2);
805 }
808 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3) {
809 mov(arg_1, O0);
810 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument");
811 mov(arg_3, O2); assert(arg_3 != O0 && arg_3 != O1, "smashed argument");
812 call_VM_leaf(thread_cache, entry_point, 3);
813 }
816 void MacroAssembler::get_vm_result(Register oop_result) {
817 verify_thread();
818 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());
819 ld_ptr( vm_result_addr, oop_result);
820 st_ptr(G0, vm_result_addr);
821 verify_oop(oop_result);
822 }
825 void MacroAssembler::get_vm_result_2(Register metadata_result) {
826 verify_thread();
827 Address vm_result_addr_2(G2_thread, JavaThread::vm_result_2_offset());
828 ld_ptr(vm_result_addr_2, metadata_result);
829 st_ptr(G0, vm_result_addr_2);
830 }
833 // We require that C code which does not return a value in vm_result will
834 // leave it undisturbed.
835 void MacroAssembler::set_vm_result(Register oop_result) {
836 verify_thread();
837 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());
838 verify_oop(oop_result);
840 # ifdef ASSERT
841 // Check that we are not overwriting any other oop.
842 #ifdef CC_INTERP
843 save_frame(0);
844 #else
845 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod for -Xprof
846 #endif /* CC_INTERP */
847 ld_ptr(vm_result_addr, L0);
848 tst(L0);
849 restore();
850 breakpoint_trap(notZero, Assembler::ptr_cc);
851 // }
852 # endif
854 st_ptr(oop_result, vm_result_addr);
855 }
858 void MacroAssembler::ic_call(address entry, bool emit_delay) {
859 RelocationHolder rspec = virtual_call_Relocation::spec(pc());
860 patchable_set((intptr_t)Universe::non_oop_word(), G5_inline_cache_reg);
861 relocate(rspec);
862 call(entry, relocInfo::none);
863 if (emit_delay) {
864 delayed()->nop();
865 }
866 }
869 void MacroAssembler::card_table_write(jbyte* byte_map_base,
870 Register tmp, Register obj) {
871 #ifdef _LP64
872 srlx(obj, CardTableModRefBS::card_shift, obj);
873 #else
874 srl(obj, CardTableModRefBS::card_shift, obj);
875 #endif
876 assert(tmp != obj, "need separate temp reg");
877 set((address) byte_map_base, tmp);
878 stb(G0, tmp, obj);
879 }
882 void MacroAssembler::internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
883 address save_pc;
884 int shiftcnt;
885 #ifdef _LP64
886 # ifdef CHECK_DELAY
887 assert_not_delayed((char*) "cannot put two instructions in delay slot");
888 # endif
889 v9_dep();
890 save_pc = pc();
892 int msb32 = (int) (addrlit.value() >> 32);
893 int lsb32 = (int) (addrlit.value());
895 if (msb32 == 0 && lsb32 >= 0) {
896 Assembler::sethi(lsb32, d, addrlit.rspec());
897 }
898 else if (msb32 == -1) {
899 Assembler::sethi(~lsb32, d, addrlit.rspec());
900 xor3(d, ~low10(~0), d);
901 }
902 else {
903 Assembler::sethi(msb32, d, addrlit.rspec()); // msb 22-bits
904 if (msb32 & 0x3ff) // Any bits?
905 or3(d, msb32 & 0x3ff, d); // msb 32-bits are now in lsb 32
906 if (lsb32 & 0xFFFFFC00) { // done?
907 if ((lsb32 >> 20) & 0xfff) { // Any bits set?
908 sllx(d, 12, d); // Make room for next 12 bits
909 or3(d, (lsb32 >> 20) & 0xfff, d); // Or in next 12
910 shiftcnt = 0; // We already shifted
911 }
912 else
913 shiftcnt = 12;
914 if ((lsb32 >> 10) & 0x3ff) {
915 sllx(d, shiftcnt + 10, d); // Make room for last 10 bits
916 or3(d, (lsb32 >> 10) & 0x3ff, d); // Or in next 10
917 shiftcnt = 0;
918 }
919 else
920 shiftcnt = 10;
921 sllx(d, shiftcnt + 10, d); // Shift leaving disp field 0'd
922 }
923 else
924 sllx(d, 32, d);
925 }
926 // Pad out the instruction sequence so it can be patched later.
927 if (ForceRelocatable || (addrlit.rtype() != relocInfo::none &&
928 addrlit.rtype() != relocInfo::runtime_call_type)) {
929 while (pc() < (save_pc + (7 * BytesPerInstWord)))
930 nop();
931 }
932 #else
933 Assembler::sethi(addrlit.value(), d, addrlit.rspec());
934 #endif
935 }
938 void MacroAssembler::sethi(const AddressLiteral& addrlit, Register d) {
939 internal_sethi(addrlit, d, false);
940 }
943 void MacroAssembler::patchable_sethi(const AddressLiteral& addrlit, Register d) {
944 internal_sethi(addrlit, d, true);
945 }
948 int MacroAssembler::insts_for_sethi(address a, bool worst_case) {
949 #ifdef _LP64
950 if (worst_case) return 7;
951 intptr_t iaddr = (intptr_t) a;
952 int msb32 = (int) (iaddr >> 32);
953 int lsb32 = (int) (iaddr);
954 int count;
955 if (msb32 == 0 && lsb32 >= 0)
956 count = 1;
957 else if (msb32 == -1)
958 count = 2;
959 else {
960 count = 2;
961 if (msb32 & 0x3ff)
962 count++;
963 if (lsb32 & 0xFFFFFC00 ) {
964 if ((lsb32 >> 20) & 0xfff) count += 2;
965 if ((lsb32 >> 10) & 0x3ff) count += 2;
966 }
967 }
968 return count;
969 #else
970 return 1;
971 #endif
972 }
974 int MacroAssembler::worst_case_insts_for_set() {
975 return insts_for_sethi(NULL, true) + 1;
976 }
979 // Keep in sync with MacroAssembler::insts_for_internal_set
980 void MacroAssembler::internal_set(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
981 intptr_t value = addrlit.value();
983 if (!ForceRelocatable && addrlit.rspec().type() == relocInfo::none) {
984 // can optimize
985 if (-4096 <= value && value <= 4095) {
986 or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended)
987 return;
988 }
989 if (inv_hi22(hi22(value)) == value) {
990 sethi(addrlit, d);
991 return;
992 }
993 }
994 assert_not_delayed((char*) "cannot put two instructions in delay slot");
995 internal_sethi(addrlit, d, ForceRelocatable);
996 if (ForceRelocatable || addrlit.rspec().type() != relocInfo::none || addrlit.low10() != 0) {
997 add(d, addrlit.low10(), d, addrlit.rspec());
998 }
999 }
1001 // Keep in sync with MacroAssembler::internal_set
1002 int MacroAssembler::insts_for_internal_set(intptr_t value) {
1003 // can optimize
1004 if (-4096 <= value && value <= 4095) {
1005 return 1;
1006 }
1007 if (inv_hi22(hi22(value)) == value) {
1008 return insts_for_sethi((address) value);
1009 }
1010 int count = insts_for_sethi((address) value);
1011 AddressLiteral al(value);
1012 if (al.low10() != 0) {
1013 count++;
1014 }
1015 return count;
1016 }
1018 void MacroAssembler::set(const AddressLiteral& al, Register d) {
1019 internal_set(al, d, false);
1020 }
1022 void MacroAssembler::set(intptr_t value, Register d) {
1023 AddressLiteral al(value);
1024 internal_set(al, d, false);
1025 }
1027 void MacroAssembler::set(address addr, Register d, RelocationHolder const& rspec) {
1028 AddressLiteral al(addr, rspec);
1029 internal_set(al, d, false);
1030 }
1032 void MacroAssembler::patchable_set(const AddressLiteral& al, Register d) {
1033 internal_set(al, d, true);
1034 }
1036 void MacroAssembler::patchable_set(intptr_t value, Register d) {
1037 AddressLiteral al(value);
1038 internal_set(al, d, true);
1039 }
1042 void MacroAssembler::set64(jlong value, Register d, Register tmp) {
1043 assert_not_delayed();
1044 v9_dep();
1046 int hi = (int)(value >> 32);
1047 int lo = (int)(value & ~0);
1048 // (Matcher::isSimpleConstant64 knows about the following optimizations.)
1049 if (Assembler::is_simm13(lo) && value == lo) {
1050 or3(G0, lo, d);
1051 } else if (hi == 0) {
1052 Assembler::sethi(lo, d); // hardware version zero-extends to upper 32
1053 if (low10(lo) != 0)
1054 or3(d, low10(lo), d);
1055 }
1056 else if (hi == -1) {
1057 Assembler::sethi(~lo, d); // hardware version zero-extends to upper 32
1058 xor3(d, low10(lo) ^ ~low10(~0), d);
1059 }
1060 else if (lo == 0) {
1061 if (Assembler::is_simm13(hi)) {
1062 or3(G0, hi, d);
1063 } else {
1064 Assembler::sethi(hi, d); // hardware version zero-extends to upper 32
1065 if (low10(hi) != 0)
1066 or3(d, low10(hi), d);
1067 }
1068 sllx(d, 32, d);
1069 }
1070 else {
1071 Assembler::sethi(hi, tmp);
1072 Assembler::sethi(lo, d); // macro assembler version sign-extends
1073 if (low10(hi) != 0)
1074 or3 (tmp, low10(hi), tmp);
1075 if (low10(lo) != 0)
1076 or3 ( d, low10(lo), d);
1077 sllx(tmp, 32, tmp);
1078 or3 (d, tmp, d);
1079 }
1080 }
1082 int MacroAssembler::insts_for_set64(jlong value) {
1083 v9_dep();
1085 int hi = (int) (value >> 32);
1086 int lo = (int) (value & ~0);
1087 int count = 0;
1089 // (Matcher::isSimpleConstant64 knows about the following optimizations.)
1090 if (Assembler::is_simm13(lo) && value == lo) {
1091 count++;
1092 } else if (hi == 0) {
1093 count++;
1094 if (low10(lo) != 0)
1095 count++;
1096 }
1097 else if (hi == -1) {
1098 count += 2;
1099 }
1100 else if (lo == 0) {
1101 if (Assembler::is_simm13(hi)) {
1102 count++;
1103 } else {
1104 count++;
1105 if (low10(hi) != 0)
1106 count++;
1107 }
1108 count++;
1109 }
1110 else {
1111 count += 2;
1112 if (low10(hi) != 0)
1113 count++;
1114 if (low10(lo) != 0)
1115 count++;
1116 count += 2;
1117 }
1118 return count;
1119 }
1121 // compute size in bytes of sparc frame, given
1122 // number of extraWords
1123 int MacroAssembler::total_frame_size_in_bytes(int extraWords) {
1125 int nWords = frame::memory_parameter_word_sp_offset;
1127 nWords += extraWords;
1129 if (nWords & 1) ++nWords; // round up to double-word
1131 return nWords * BytesPerWord;
1132 }
1135 // save_frame: given number of "extra" words in frame,
1136 // issue approp. save instruction (p 200, v8 manual)
1138 void MacroAssembler::save_frame(int extraWords) {
1139 int delta = -total_frame_size_in_bytes(extraWords);
1140 if (is_simm13(delta)) {
1141 save(SP, delta, SP);
1142 } else {
1143 set(delta, G3_scratch);
1144 save(SP, G3_scratch, SP);
1145 }
1146 }
1149 void MacroAssembler::save_frame_c1(int size_in_bytes) {
1150 if (is_simm13(-size_in_bytes)) {
1151 save(SP, -size_in_bytes, SP);
1152 } else {
1153 set(-size_in_bytes, G3_scratch);
1154 save(SP, G3_scratch, SP);
1155 }
1156 }
1159 void MacroAssembler::save_frame_and_mov(int extraWords,
1160 Register s1, Register d1,
1161 Register s2, Register d2) {
1162 assert_not_delayed();
1164 // The trick here is to use precisely the same memory word
1165 // that trap handlers also use to save the register.
1166 // This word cannot be used for any other purpose, but
1167 // it works fine to save the register's value, whether or not
1168 // an interrupt flushes register windows at any given moment!
1169 Address s1_addr;
1170 if (s1->is_valid() && (s1->is_in() || s1->is_local())) {
1171 s1_addr = s1->address_in_saved_window();
1172 st_ptr(s1, s1_addr);
1173 }
1175 Address s2_addr;
1176 if (s2->is_valid() && (s2->is_in() || s2->is_local())) {
1177 s2_addr = s2->address_in_saved_window();
1178 st_ptr(s2, s2_addr);
1179 }
1181 save_frame(extraWords);
1183 if (s1_addr.base() == SP) {
1184 ld_ptr(s1_addr.after_save(), d1);
1185 } else if (s1->is_valid()) {
1186 mov(s1->after_save(), d1);
1187 }
1189 if (s2_addr.base() == SP) {
1190 ld_ptr(s2_addr.after_save(), d2);
1191 } else if (s2->is_valid()) {
1192 mov(s2->after_save(), d2);
1193 }
1194 }
1197 AddressLiteral MacroAssembler::allocate_metadata_address(Metadata* obj) {
1198 assert(oop_recorder() != NULL, "this assembler needs a Recorder");
1199 int index = oop_recorder()->allocate_metadata_index(obj);
1200 RelocationHolder rspec = metadata_Relocation::spec(index);
1201 return AddressLiteral((address)obj, rspec);
1202 }
1204 AddressLiteral MacroAssembler::constant_metadata_address(Metadata* obj) {
1205 assert(oop_recorder() != NULL, "this assembler needs a Recorder");
1206 int index = oop_recorder()->find_index(obj);
1207 RelocationHolder rspec = metadata_Relocation::spec(index);
1208 return AddressLiteral((address)obj, rspec);
1209 }
1212 AddressLiteral MacroAssembler::constant_oop_address(jobject obj) {
1213 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1214 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop");
1215 int oop_index = oop_recorder()->find_index(obj);
1216 return AddressLiteral(obj, oop_Relocation::spec(oop_index));
1217 }
1219 void MacroAssembler::set_narrow_oop(jobject obj, Register d) {
1220 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1221 int oop_index = oop_recorder()->find_index(obj);
1222 RelocationHolder rspec = oop_Relocation::spec(oop_index);
1224 assert_not_delayed();
1225 // Relocation with special format (see relocInfo_sparc.hpp).
1226 relocate(rspec, 1);
1227 // Assembler::sethi(0x3fffff, d);
1228 emit_int32( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(0x3fffff) );
1229 // Don't add relocation for 'add'. Do patching during 'sethi' processing.
1230 add(d, 0x3ff, d);
1232 }
1234 void MacroAssembler::set_narrow_klass(Klass* k, Register d) {
1235 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1236 int klass_index = oop_recorder()->find_index(k);
1237 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
1238 narrowOop encoded_k = oopDesc::encode_klass(k);
1240 assert_not_delayed();
1241 // Relocation with special format (see relocInfo_sparc.hpp).
1242 relocate(rspec, 1);
1243 // Assembler::sethi(encoded_k, d);
1244 emit_int32( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(encoded_k) );
1245 // Don't add relocation for 'add'. Do patching during 'sethi' processing.
1246 add(d, low10(encoded_k), d);
1248 }
1250 void MacroAssembler::align(int modulus) {
1251 while (offset() % modulus != 0) nop();
1252 }
1255 void MacroAssembler::safepoint() {
1256 relocate(breakpoint_Relocation::spec(breakpoint_Relocation::safepoint));
1257 }
1260 void RegistersForDebugging::print(outputStream* s) {
1261 FlagSetting fs(Debugging, true);
1262 int j;
1263 for (j = 0; j < 8; ++j) {
1264 if (j != 6) { s->print("i%d = ", j); os::print_location(s, i[j]); }
1265 else { s->print( "fp = " ); os::print_location(s, i[j]); }
1266 }
1267 s->cr();
1269 for (j = 0; j < 8; ++j) {
1270 s->print("l%d = ", j); os::print_location(s, l[j]);
1271 }
1272 s->cr();
1274 for (j = 0; j < 8; ++j) {
1275 if (j != 6) { s->print("o%d = ", j); os::print_location(s, o[j]); }
1276 else { s->print( "sp = " ); os::print_location(s, o[j]); }
1277 }
1278 s->cr();
1280 for (j = 0; j < 8; ++j) {
1281 s->print("g%d = ", j); os::print_location(s, g[j]);
1282 }
1283 s->cr();
1285 // print out floats with compression
1286 for (j = 0; j < 32; ) {
1287 jfloat val = f[j];
1288 int last = j;
1289 for ( ; last+1 < 32; ++last ) {
1290 char b1[1024], b2[1024];
1291 sprintf(b1, "%f", val);
1292 sprintf(b2, "%f", f[last+1]);
1293 if (strcmp(b1, b2))
1294 break;
1295 }
1296 s->print("f%d", j);
1297 if ( j != last ) s->print(" - f%d", last);
1298 s->print(" = %f", val);
1299 s->fill_to(25);
1300 s->print_cr(" (0x%x)", val);
1301 j = last + 1;
1302 }
1303 s->cr();
1305 // and doubles (evens only)
1306 for (j = 0; j < 32; ) {
1307 jdouble val = d[j];
1308 int last = j;
1309 for ( ; last+1 < 32; ++last ) {
1310 char b1[1024], b2[1024];
1311 sprintf(b1, "%f", val);
1312 sprintf(b2, "%f", d[last+1]);
1313 if (strcmp(b1, b2))
1314 break;
1315 }
1316 s->print("d%d", 2 * j);
1317 if ( j != last ) s->print(" - d%d", last);
1318 s->print(" = %f", val);
1319 s->fill_to(30);
1320 s->print("(0x%x)", *(int*)&val);
1321 s->fill_to(42);
1322 s->print_cr("(0x%x)", *(1 + (int*)&val));
1323 j = last + 1;
1324 }
1325 s->cr();
1326 }
1328 void RegistersForDebugging::save_registers(MacroAssembler* a) {
1329 a->sub(FP, round_to(sizeof(RegistersForDebugging), sizeof(jdouble)) - STACK_BIAS, O0);
1330 a->flush_windows();
1331 int i;
1332 for (i = 0; i < 8; ++i) {
1333 a->ld_ptr(as_iRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, i_offset(i));
1334 a->ld_ptr(as_lRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, l_offset(i));
1335 a->st_ptr(as_oRegister(i)->after_save(), O0, o_offset(i));
1336 a->st_ptr(as_gRegister(i)->after_save(), O0, g_offset(i));
1337 }
1338 for (i = 0; i < 32; ++i) {
1339 a->stf(FloatRegisterImpl::S, as_FloatRegister(i), O0, f_offset(i));
1340 }
1341 for (i = 0; i < (VM_Version::v9_instructions_work() ? 64 : 32); i += 2) {
1342 a->stf(FloatRegisterImpl::D, as_FloatRegister(i), O0, d_offset(i));
1343 }
1344 }
1346 void RegistersForDebugging::restore_registers(MacroAssembler* a, Register r) {
1347 for (int i = 1; i < 8; ++i) {
1348 a->ld_ptr(r, g_offset(i), as_gRegister(i));
1349 }
1350 for (int j = 0; j < 32; ++j) {
1351 a->ldf(FloatRegisterImpl::S, O0, f_offset(j), as_FloatRegister(j));
1352 }
1353 for (int k = 0; k < (VM_Version::v9_instructions_work() ? 64 : 32); k += 2) {
1354 a->ldf(FloatRegisterImpl::D, O0, d_offset(k), as_FloatRegister(k));
1355 }
1356 }
1359 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1360 void MacroAssembler::push_fTOS() {
1361 // %%%%%% need to implement this
1362 }
1364 // pops double TOS element from CPU stack and pushes on FPU stack
1365 void MacroAssembler::pop_fTOS() {
1366 // %%%%%% need to implement this
1367 }
1369 void MacroAssembler::empty_FPU_stack() {
1370 // %%%%%% need to implement this
1371 }
1373 void MacroAssembler::_verify_oop(Register reg, const char* msg, const char * file, int line) {
1374 // plausibility check for oops
1375 if (!VerifyOops) return;
1377 if (reg == G0) return; // always NULL, which is always an oop
1379 BLOCK_COMMENT("verify_oop {");
1380 char buffer[64];
1381 #ifdef COMPILER1
1382 if (CommentedAssembly) {
1383 snprintf(buffer, sizeof(buffer), "verify_oop at %d", offset());
1384 block_comment(buffer);
1385 }
1386 #endif
1388 int len = strlen(file) + strlen(msg) + 1 + 4;
1389 sprintf(buffer, "%d", line);
1390 len += strlen(buffer);
1391 sprintf(buffer, " at offset %d ", offset());
1392 len += strlen(buffer);
1393 char * real_msg = new char[len];
1394 sprintf(real_msg, "%s%s(%s:%d)", msg, buffer, file, line);
1396 // Call indirectly to solve generation ordering problem
1397 AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address());
1399 // Make some space on stack above the current register window.
1400 // Enough to hold 8 64-bit registers.
1401 add(SP,-8*8,SP);
1403 // Save some 64-bit registers; a normal 'save' chops the heads off
1404 // of 64-bit longs in the 32-bit build.
1405 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8);
1406 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8);
1407 mov(reg,O0); // Move arg into O0; arg might be in O7 which is about to be crushed
1408 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8);
1410 // Size of set() should stay the same
1411 patchable_set((intptr_t)real_msg, O1);
1412 // Load address to call to into O7
1413 load_ptr_contents(a, O7);
1414 // Register call to verify_oop_subroutine
1415 callr(O7, G0);
1416 delayed()->nop();
1417 // recover frame size
1418 add(SP, 8*8,SP);
1419 BLOCK_COMMENT("} verify_oop");
1420 }
1422 void MacroAssembler::_verify_oop_addr(Address addr, const char* msg, const char * file, int line) {
1423 // plausibility check for oops
1424 if (!VerifyOops) return;
1426 char buffer[64];
1427 sprintf(buffer, "%d", line);
1428 int len = strlen(file) + strlen(msg) + 1 + 4 + strlen(buffer);
1429 sprintf(buffer, " at SP+%d ", addr.disp());
1430 len += strlen(buffer);
1431 char * real_msg = new char[len];
1432 sprintf(real_msg, "%s at SP+%d (%s:%d)", msg, addr.disp(), file, line);
1434 // Call indirectly to solve generation ordering problem
1435 AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address());
1437 // Make some space on stack above the current register window.
1438 // Enough to hold 8 64-bit registers.
1439 add(SP,-8*8,SP);
1441 // Save some 64-bit registers; a normal 'save' chops the heads off
1442 // of 64-bit longs in the 32-bit build.
1443 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8);
1444 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8);
1445 ld_ptr(addr.base(), addr.disp() + 8*8, O0); // Load arg into O0; arg might be in O7 which is about to be crushed
1446 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8);
1448 // Size of set() should stay the same
1449 patchable_set((intptr_t)real_msg, O1);
1450 // Load address to call to into O7
1451 load_ptr_contents(a, O7);
1452 // Register call to verify_oop_subroutine
1453 callr(O7, G0);
1454 delayed()->nop();
1455 // recover frame size
1456 add(SP, 8*8,SP);
1457 }
1459 // side-door communication with signalHandler in os_solaris.cpp
1460 address MacroAssembler::_verify_oop_implicit_branch[3] = { NULL };
1462 // This macro is expanded just once; it creates shared code. Contract:
1463 // receives an oop in O0. Must restore O0 & O7 from TLS. Must not smash ANY
1464 // registers, including flags. May not use a register 'save', as this blows
1465 // the high bits of the O-regs if they contain Long values. Acts as a 'leaf'
1466 // call.
1467 void MacroAssembler::verify_oop_subroutine() {
1468 assert( VM_Version::v9_instructions_work(), "VerifyOops not supported for V8" );
1470 // Leaf call; no frame.
1471 Label succeed, fail, null_or_fail;
1473 // O0 and O7 were saved already (O0 in O0's TLS home, O7 in O5's TLS home).
1474 // O0 is now the oop to be checked. O7 is the return address.
1475 Register O0_obj = O0;
1477 // Save some more registers for temps.
1478 stx(O2,SP,frame::register_save_words*wordSize+STACK_BIAS+2*8);
1479 stx(O3,SP,frame::register_save_words*wordSize+STACK_BIAS+3*8);
1480 stx(O4,SP,frame::register_save_words*wordSize+STACK_BIAS+4*8);
1481 stx(O5,SP,frame::register_save_words*wordSize+STACK_BIAS+5*8);
1483 // Save flags
1484 Register O5_save_flags = O5;
1485 rdccr( O5_save_flags );
1487 { // count number of verifies
1488 Register O2_adr = O2;
1489 Register O3_accum = O3;
1490 inc_counter(StubRoutines::verify_oop_count_addr(), O2_adr, O3_accum);
1491 }
1493 Register O2_mask = O2;
1494 Register O3_bits = O3;
1495 Register O4_temp = O4;
1497 // mark lower end of faulting range
1498 assert(_verify_oop_implicit_branch[0] == NULL, "set once");
1499 _verify_oop_implicit_branch[0] = pc();
1501 // We can't check the mark oop because it could be in the process of
1502 // locking or unlocking while this is running.
1503 set(Universe::verify_oop_mask (), O2_mask);
1504 set(Universe::verify_oop_bits (), O3_bits);
1506 // assert((obj & oop_mask) == oop_bits);
1507 and3(O0_obj, O2_mask, O4_temp);
1508 cmp_and_brx_short(O4_temp, O3_bits, notEqual, pn, null_or_fail);
1510 if ((NULL_WORD & Universe::verify_oop_mask()) == Universe::verify_oop_bits()) {
1511 // the null_or_fail case is useless; must test for null separately
1512 br_null_short(O0_obj, pn, succeed);
1513 }
1515 // Check the Klass* of this object for being in the right area of memory.
1516 // Cannot do the load in the delay above slot in case O0 is null
1517 load_klass(O0_obj, O0_obj);
1518 // assert((klass != NULL)
1519 br_null_short(O0_obj, pn, fail);
1520 // TODO: Future assert that klass is lower 4g memory for UseCompressedKlassPointers
1522 wrccr( O5_save_flags ); // Restore CCR's
1524 // mark upper end of faulting range
1525 _verify_oop_implicit_branch[1] = pc();
1527 //-----------------------
1528 // all tests pass
1529 bind(succeed);
1531 // Restore prior 64-bit registers
1532 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+0*8,O0);
1533 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+1*8,O1);
1534 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+2*8,O2);
1535 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+3*8,O3);
1536 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+4*8,O4);
1537 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+5*8,O5);
1539 retl(); // Leaf return; restore prior O7 in delay slot
1540 delayed()->ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+7*8,O7);
1542 //-----------------------
1543 bind(null_or_fail); // nulls are less common but OK
1544 br_null(O0_obj, false, pt, succeed);
1545 delayed()->wrccr( O5_save_flags ); // Restore CCR's
1547 //-----------------------
1548 // report failure:
1549 bind(fail);
1550 _verify_oop_implicit_branch[2] = pc();
1552 wrccr( O5_save_flags ); // Restore CCR's
1554 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
1556 // stop_subroutine expects message pointer in I1.
1557 mov(I1, O1);
1559 // Restore prior 64-bit registers
1560 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+0*8,I0);
1561 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+1*8,I1);
1562 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+2*8,I2);
1563 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+3*8,I3);
1564 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+4*8,I4);
1565 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+5*8,I5);
1567 // factor long stop-sequence into subroutine to save space
1568 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet");
1570 // call indirectly to solve generation ordering problem
1571 AddressLiteral al(StubRoutines::Sparc::stop_subroutine_entry_address());
1572 load_ptr_contents(al, O5);
1573 jmpl(O5, 0, O7);
1574 delayed()->nop();
1575 }
1578 void MacroAssembler::stop(const char* msg) {
1579 // save frame first to get O7 for return address
1580 // add one word to size in case struct is odd number of words long
1581 // It must be doubleword-aligned for storing doubles into it.
1583 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
1585 // stop_subroutine expects message pointer in I1.
1586 // Size of set() should stay the same
1587 patchable_set((intptr_t)msg, O1);
1589 // factor long stop-sequence into subroutine to save space
1590 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet");
1592 // call indirectly to solve generation ordering problem
1593 AddressLiteral a(StubRoutines::Sparc::stop_subroutine_entry_address());
1594 load_ptr_contents(a, O5);
1595 jmpl(O5, 0, O7);
1596 delayed()->nop();
1598 breakpoint_trap(); // make stop actually stop rather than writing
1599 // unnoticeable results in the output files.
1601 // restore(); done in callee to save space!
1602 }
1605 void MacroAssembler::warn(const char* msg) {
1606 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
1607 RegistersForDebugging::save_registers(this);
1608 mov(O0, L0);
1609 // Size of set() should stay the same
1610 patchable_set((intptr_t)msg, O0);
1611 call( CAST_FROM_FN_PTR(address, warning) );
1612 delayed()->nop();
1613 // ret();
1614 // delayed()->restore();
1615 RegistersForDebugging::restore_registers(this, L0);
1616 restore();
1617 }
1620 void MacroAssembler::untested(const char* what) {
1621 // We must be able to turn interactive prompting off
1622 // in order to run automated test scripts on the VM
1623 // Use the flag ShowMessageBoxOnError
1625 char* b = new char[1024];
1626 sprintf(b, "untested: %s", what);
1628 if (ShowMessageBoxOnError) { STOP(b); }
1629 else { warn(b); }
1630 }
1633 void MacroAssembler::stop_subroutine() {
1634 RegistersForDebugging::save_registers(this);
1636 // for the sake of the debugger, stick a PC on the current frame
1637 // (this assumes that the caller has performed an extra "save")
1638 mov(I7, L7);
1639 add(O7, -7 * BytesPerInt, I7);
1641 save_frame(); // one more save to free up another O7 register
1642 mov(I0, O1); // addr of reg save area
1644 // We expect pointer to message in I1. Caller must set it up in O1
1645 mov(I1, O0); // get msg
1646 call (CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
1647 delayed()->nop();
1649 restore();
1651 RegistersForDebugging::restore_registers(this, O0);
1653 save_frame(0);
1654 call(CAST_FROM_FN_PTR(address,breakpoint));
1655 delayed()->nop();
1656 restore();
1658 mov(L7, I7);
1659 retl();
1660 delayed()->restore(); // see stop above
1661 }
1664 void MacroAssembler::debug(char* msg, RegistersForDebugging* regs) {
1665 if ( ShowMessageBoxOnError ) {
1666 JavaThread* thread = JavaThread::current();
1667 JavaThreadState saved_state = thread->thread_state();
1668 thread->set_thread_state(_thread_in_vm);
1669 {
1670 // In order to get locks work, we need to fake a in_VM state
1671 ttyLocker ttyl;
1672 ::tty->print_cr("EXECUTION STOPPED: %s\n", msg);
1673 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
1674 BytecodeCounter::print();
1675 }
1676 if (os::message_box(msg, "Execution stopped, print registers?"))
1677 regs->print(::tty);
1678 }
1679 BREAKPOINT;
1680 ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state);
1681 }
1682 else {
1683 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
1684 }
1685 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
1686 }
1689 void MacroAssembler::calc_mem_param_words(Register Rparam_words, Register Rresult) {
1690 subcc( Rparam_words, Argument::n_register_parameters, Rresult); // how many mem words?
1691 Label no_extras;
1692 br( negative, true, pt, no_extras ); // if neg, clear reg
1693 delayed()->set(0, Rresult); // annuled, so only if taken
1694 bind( no_extras );
1695 }
1698 void MacroAssembler::calc_frame_size(Register Rextra_words, Register Rresult) {
1699 #ifdef _LP64
1700 add(Rextra_words, frame::memory_parameter_word_sp_offset, Rresult);
1701 #else
1702 add(Rextra_words, frame::memory_parameter_word_sp_offset + 1, Rresult);
1703 #endif
1704 bclr(1, Rresult);
1705 sll(Rresult, LogBytesPerWord, Rresult); // Rresult has total frame bytes
1706 }
1709 void MacroAssembler::calc_frame_size_and_save(Register Rextra_words, Register Rresult) {
1710 calc_frame_size(Rextra_words, Rresult);
1711 neg(Rresult);
1712 save(SP, Rresult, SP);
1713 }
1716 // ---------------------------------------------------------
1717 Assembler::RCondition cond2rcond(Assembler::Condition c) {
1718 switch (c) {
1719 /*case zero: */
1720 case Assembler::equal: return Assembler::rc_z;
1721 case Assembler::lessEqual: return Assembler::rc_lez;
1722 case Assembler::less: return Assembler::rc_lz;
1723 /*case notZero:*/
1724 case Assembler::notEqual: return Assembler::rc_nz;
1725 case Assembler::greater: return Assembler::rc_gz;
1726 case Assembler::greaterEqual: return Assembler::rc_gez;
1727 }
1728 ShouldNotReachHere();
1729 return Assembler::rc_z;
1730 }
1732 // compares (32 bit) register with zero and branches. NOT FOR USE WITH 64-bit POINTERS
1733 void MacroAssembler::cmp_zero_and_br(Condition c, Register s1, Label& L, bool a, Predict p) {
1734 tst(s1);
1735 br (c, a, p, L);
1736 }
1738 // Compares a pointer register with zero and branches on null.
1739 // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
1740 void MacroAssembler::br_null( Register s1, bool a, Predict p, Label& L ) {
1741 assert_not_delayed();
1742 #ifdef _LP64
1743 bpr( rc_z, a, p, s1, L );
1744 #else
1745 tst(s1);
1746 br ( zero, a, p, L );
1747 #endif
1748 }
1750 void MacroAssembler::br_notnull( Register s1, bool a, Predict p, Label& L ) {
1751 assert_not_delayed();
1752 #ifdef _LP64
1753 bpr( rc_nz, a, p, s1, L );
1754 #else
1755 tst(s1);
1756 br ( notZero, a, p, L );
1757 #endif
1758 }
1760 // Compare registers and branch with nop in delay slot or cbcond without delay slot.
1762 // Compare integer (32 bit) values (icc only).
1763 void MacroAssembler::cmp_and_br_short(Register s1, Register s2, Condition c,
1764 Predict p, Label& L) {
1765 assert_not_delayed();
1766 if (use_cbcond(L)) {
1767 Assembler::cbcond(c, icc, s1, s2, L);
1768 } else {
1769 cmp(s1, s2);
1770 br(c, false, p, L);
1771 delayed()->nop();
1772 }
1773 }
1775 // Compare integer (32 bit) values (icc only).
1776 void MacroAssembler::cmp_and_br_short(Register s1, int simm13a, Condition c,
1777 Predict p, Label& L) {
1778 assert_not_delayed();
1779 if (is_simm(simm13a,5) && use_cbcond(L)) {
1780 Assembler::cbcond(c, icc, s1, simm13a, L);
1781 } else {
1782 cmp(s1, simm13a);
1783 br(c, false, p, L);
1784 delayed()->nop();
1785 }
1786 }
1788 // Branch that tests xcc in LP64 and icc in !LP64
1789 void MacroAssembler::cmp_and_brx_short(Register s1, Register s2, Condition c,
1790 Predict p, Label& L) {
1791 assert_not_delayed();
1792 if (use_cbcond(L)) {
1793 Assembler::cbcond(c, ptr_cc, s1, s2, L);
1794 } else {
1795 cmp(s1, s2);
1796 brx(c, false, p, L);
1797 delayed()->nop();
1798 }
1799 }
1801 // Branch that tests xcc in LP64 and icc in !LP64
1802 void MacroAssembler::cmp_and_brx_short(Register s1, int simm13a, Condition c,
1803 Predict p, Label& L) {
1804 assert_not_delayed();
1805 if (is_simm(simm13a,5) && use_cbcond(L)) {
1806 Assembler::cbcond(c, ptr_cc, s1, simm13a, L);
1807 } else {
1808 cmp(s1, simm13a);
1809 brx(c, false, p, L);
1810 delayed()->nop();
1811 }
1812 }
1814 // Short branch version for compares a pointer with zero.
1816 void MacroAssembler::br_null_short(Register s1, Predict p, Label& L) {
1817 assert_not_delayed();
1818 if (use_cbcond(L)) {
1819 Assembler::cbcond(zero, ptr_cc, s1, 0, L);
1820 return;
1821 }
1822 br_null(s1, false, p, L);
1823 delayed()->nop();
1824 }
1826 void MacroAssembler::br_notnull_short(Register s1, Predict p, Label& L) {
1827 assert_not_delayed();
1828 if (use_cbcond(L)) {
1829 Assembler::cbcond(notZero, ptr_cc, s1, 0, L);
1830 return;
1831 }
1832 br_notnull(s1, false, p, L);
1833 delayed()->nop();
1834 }
1836 // Unconditional short branch
1837 void MacroAssembler::ba_short(Label& L) {
1838 if (use_cbcond(L)) {
1839 Assembler::cbcond(equal, icc, G0, G0, L);
1840 return;
1841 }
1842 br(always, false, pt, L);
1843 delayed()->nop();
1844 }
1846 // instruction sequences factored across compiler & interpreter
1849 void MacroAssembler::lcmp( Register Ra_hi, Register Ra_low,
1850 Register Rb_hi, Register Rb_low,
1851 Register Rresult) {
1853 Label check_low_parts, done;
1855 cmp(Ra_hi, Rb_hi ); // compare hi parts
1856 br(equal, true, pt, check_low_parts);
1857 delayed()->cmp(Ra_low, Rb_low); // test low parts
1859 // And, with an unsigned comparison, it does not matter if the numbers
1860 // are negative or not.
1861 // E.g., -2 cmp -1: the low parts are 0xfffffffe and 0xffffffff.
1862 // The second one is bigger (unsignedly).
1864 // Other notes: The first move in each triplet can be unconditional
1865 // (and therefore probably prefetchable).
1866 // And the equals case for the high part does not need testing,
1867 // since that triplet is reached only after finding the high halves differ.
1869 if (VM_Version::v9_instructions_work()) {
1870 mov(-1, Rresult);
1871 ba(done); delayed()-> movcc(greater, false, icc, 1, Rresult);
1872 } else {
1873 br(less, true, pt, done); delayed()-> set(-1, Rresult);
1874 br(greater, true, pt, done); delayed()-> set( 1, Rresult);
1875 }
1877 bind( check_low_parts );
1879 if (VM_Version::v9_instructions_work()) {
1880 mov( -1, Rresult);
1881 movcc(equal, false, icc, 0, Rresult);
1882 movcc(greaterUnsigned, false, icc, 1, Rresult);
1883 } else {
1884 set(-1, Rresult);
1885 br(equal, true, pt, done); delayed()->set( 0, Rresult);
1886 br(greaterUnsigned, true, pt, done); delayed()->set( 1, Rresult);
1887 }
1888 bind( done );
1889 }
1891 void MacroAssembler::lneg( Register Rhi, Register Rlow ) {
1892 subcc( G0, Rlow, Rlow );
1893 subc( G0, Rhi, Rhi );
1894 }
1896 void MacroAssembler::lshl( Register Rin_high, Register Rin_low,
1897 Register Rcount,
1898 Register Rout_high, Register Rout_low,
1899 Register Rtemp ) {
1902 Register Ralt_count = Rtemp;
1903 Register Rxfer_bits = Rtemp;
1905 assert( Ralt_count != Rin_high
1906 && Ralt_count != Rin_low
1907 && Ralt_count != Rcount
1908 && Rxfer_bits != Rin_low
1909 && Rxfer_bits != Rin_high
1910 && Rxfer_bits != Rcount
1911 && Rxfer_bits != Rout_low
1912 && Rout_low != Rin_high,
1913 "register alias checks");
1915 Label big_shift, done;
1917 // This code can be optimized to use the 64 bit shifts in V9.
1918 // Here we use the 32 bit shifts.
1920 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
1921 subcc(Rcount, 31, Ralt_count);
1922 br(greater, true, pn, big_shift);
1923 delayed()->dec(Ralt_count);
1925 // shift < 32 bits, Ralt_count = Rcount-31
1927 // We get the transfer bits by shifting right by 32-count the low
1928 // register. This is done by shifting right by 31-count and then by one
1929 // more to take care of the special (rare) case where count is zero
1930 // (shifting by 32 would not work).
1932 neg(Ralt_count);
1934 // The order of the next two instructions is critical in the case where
1935 // Rin and Rout are the same and should not be reversed.
1937 srl(Rin_low, Ralt_count, Rxfer_bits); // shift right by 31-count
1938 if (Rcount != Rout_low) {
1939 sll(Rin_low, Rcount, Rout_low); // low half
1940 }
1941 sll(Rin_high, Rcount, Rout_high);
1942 if (Rcount == Rout_low) {
1943 sll(Rin_low, Rcount, Rout_low); // low half
1944 }
1945 srl(Rxfer_bits, 1, Rxfer_bits ); // shift right by one more
1946 ba(done);
1947 delayed()->or3(Rout_high, Rxfer_bits, Rout_high); // new hi value: or in shifted old hi part and xfer from low
1949 // shift >= 32 bits, Ralt_count = Rcount-32
1950 bind(big_shift);
1951 sll(Rin_low, Ralt_count, Rout_high );
1952 clr(Rout_low);
1954 bind(done);
1955 }
1958 void MacroAssembler::lshr( Register Rin_high, Register Rin_low,
1959 Register Rcount,
1960 Register Rout_high, Register Rout_low,
1961 Register Rtemp ) {
1963 Register Ralt_count = Rtemp;
1964 Register Rxfer_bits = Rtemp;
1966 assert( Ralt_count != Rin_high
1967 && Ralt_count != Rin_low
1968 && Ralt_count != Rcount
1969 && Rxfer_bits != Rin_low
1970 && Rxfer_bits != Rin_high
1971 && Rxfer_bits != Rcount
1972 && Rxfer_bits != Rout_high
1973 && Rout_high != Rin_low,
1974 "register alias checks");
1976 Label big_shift, done;
1978 // This code can be optimized to use the 64 bit shifts in V9.
1979 // Here we use the 32 bit shifts.
1981 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
1982 subcc(Rcount, 31, Ralt_count);
1983 br(greater, true, pn, big_shift);
1984 delayed()->dec(Ralt_count);
1986 // shift < 32 bits, Ralt_count = Rcount-31
1988 // We get the transfer bits by shifting left by 32-count the high
1989 // register. This is done by shifting left by 31-count and then by one
1990 // more to take care of the special (rare) case where count is zero
1991 // (shifting by 32 would not work).
1993 neg(Ralt_count);
1994 if (Rcount != Rout_low) {
1995 srl(Rin_low, Rcount, Rout_low);
1996 }
1998 // The order of the next two instructions is critical in the case where
1999 // Rin and Rout are the same and should not be reversed.
2001 sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count
2002 sra(Rin_high, Rcount, Rout_high ); // high half
2003 sll(Rxfer_bits, 1, Rxfer_bits); // shift left by one more
2004 if (Rcount == Rout_low) {
2005 srl(Rin_low, Rcount, Rout_low);
2006 }
2007 ba(done);
2008 delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high
2010 // shift >= 32 bits, Ralt_count = Rcount-32
2011 bind(big_shift);
2013 sra(Rin_high, Ralt_count, Rout_low);
2014 sra(Rin_high, 31, Rout_high); // sign into hi
2016 bind( done );
2017 }
2021 void MacroAssembler::lushr( Register Rin_high, Register Rin_low,
2022 Register Rcount,
2023 Register Rout_high, Register Rout_low,
2024 Register Rtemp ) {
2026 Register Ralt_count = Rtemp;
2027 Register Rxfer_bits = Rtemp;
2029 assert( Ralt_count != Rin_high
2030 && Ralt_count != Rin_low
2031 && Ralt_count != Rcount
2032 && Rxfer_bits != Rin_low
2033 && Rxfer_bits != Rin_high
2034 && Rxfer_bits != Rcount
2035 && Rxfer_bits != Rout_high
2036 && Rout_high != Rin_low,
2037 "register alias checks");
2039 Label big_shift, done;
2041 // This code can be optimized to use the 64 bit shifts in V9.
2042 // Here we use the 32 bit shifts.
2044 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
2045 subcc(Rcount, 31, Ralt_count);
2046 br(greater, true, pn, big_shift);
2047 delayed()->dec(Ralt_count);
2049 // shift < 32 bits, Ralt_count = Rcount-31
2051 // We get the transfer bits by shifting left by 32-count the high
2052 // register. This is done by shifting left by 31-count and then by one
2053 // more to take care of the special (rare) case where count is zero
2054 // (shifting by 32 would not work).
2056 neg(Ralt_count);
2057 if (Rcount != Rout_low) {
2058 srl(Rin_low, Rcount, Rout_low);
2059 }
2061 // The order of the next two instructions is critical in the case where
2062 // Rin and Rout are the same and should not be reversed.
2064 sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count
2065 srl(Rin_high, Rcount, Rout_high ); // high half
2066 sll(Rxfer_bits, 1, Rxfer_bits); // shift left by one more
2067 if (Rcount == Rout_low) {
2068 srl(Rin_low, Rcount, Rout_low);
2069 }
2070 ba(done);
2071 delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high
2073 // shift >= 32 bits, Ralt_count = Rcount-32
2074 bind(big_shift);
2076 srl(Rin_high, Ralt_count, Rout_low);
2077 clr(Rout_high);
2079 bind( done );
2080 }
2082 #ifdef _LP64
2083 void MacroAssembler::lcmp( Register Ra, Register Rb, Register Rresult) {
2084 cmp(Ra, Rb);
2085 mov(-1, Rresult);
2086 movcc(equal, false, xcc, 0, Rresult);
2087 movcc(greater, false, xcc, 1, Rresult);
2088 }
2089 #endif
2092 void MacroAssembler::load_sized_value(Address src, Register dst, size_t size_in_bytes, bool is_signed) {
2093 switch (size_in_bytes) {
2094 case 8: ld_long(src, dst); break;
2095 case 4: ld( src, dst); break;
2096 case 2: is_signed ? ldsh(src, dst) : lduh(src, dst); break;
2097 case 1: is_signed ? ldsb(src, dst) : ldub(src, dst); break;
2098 default: ShouldNotReachHere();
2099 }
2100 }
2102 void MacroAssembler::store_sized_value(Register src, Address dst, size_t size_in_bytes) {
2103 switch (size_in_bytes) {
2104 case 8: st_long(src, dst); break;
2105 case 4: st( src, dst); break;
2106 case 2: sth( src, dst); break;
2107 case 1: stb( src, dst); break;
2108 default: ShouldNotReachHere();
2109 }
2110 }
2113 void MacroAssembler::float_cmp( bool is_float, int unordered_result,
2114 FloatRegister Fa, FloatRegister Fb,
2115 Register Rresult) {
2117 fcmp(is_float ? FloatRegisterImpl::S : FloatRegisterImpl::D, fcc0, Fa, Fb);
2119 Condition lt = unordered_result == -1 ? f_unorderedOrLess : f_less;
2120 Condition eq = f_equal;
2121 Condition gt = unordered_result == 1 ? f_unorderedOrGreater : f_greater;
2123 if (VM_Version::v9_instructions_work()) {
2125 mov(-1, Rresult);
2126 movcc(eq, true, fcc0, 0, Rresult);
2127 movcc(gt, true, fcc0, 1, Rresult);
2129 } else {
2130 Label done;
2132 set( -1, Rresult );
2133 //fb(lt, true, pn, done); delayed()->set( -1, Rresult );
2134 fb( eq, true, pn, done); delayed()->set( 0, Rresult );
2135 fb( gt, true, pn, done); delayed()->set( 1, Rresult );
2137 bind (done);
2138 }
2139 }
2142 void MacroAssembler::fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)
2143 {
2144 if (VM_Version::v9_instructions_work()) {
2145 Assembler::fneg(w, s, d);
2146 } else {
2147 if (w == FloatRegisterImpl::S) {
2148 Assembler::fneg(w, s, d);
2149 } else if (w == FloatRegisterImpl::D) {
2150 // number() does a sanity check on the alignment.
2151 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&
2152 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");
2154 Assembler::fneg(FloatRegisterImpl::S, s, d);
2155 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2156 } else {
2157 assert(w == FloatRegisterImpl::Q, "Invalid float register width");
2159 // number() does a sanity check on the alignment.
2160 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&
2161 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");
2163 Assembler::fneg(FloatRegisterImpl::S, s, d);
2164 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2165 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());
2166 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());
2167 }
2168 }
2169 }
2171 void MacroAssembler::fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)
2172 {
2173 if (VM_Version::v9_instructions_work()) {
2174 Assembler::fmov(w, s, d);
2175 } else {
2176 if (w == FloatRegisterImpl::S) {
2177 Assembler::fmov(w, s, d);
2178 } else if (w == FloatRegisterImpl::D) {
2179 // number() does a sanity check on the alignment.
2180 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&
2181 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");
2183 Assembler::fmov(FloatRegisterImpl::S, s, d);
2184 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2185 } else {
2186 assert(w == FloatRegisterImpl::Q, "Invalid float register width");
2188 // number() does a sanity check on the alignment.
2189 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&
2190 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");
2192 Assembler::fmov(FloatRegisterImpl::S, s, d);
2193 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2194 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());
2195 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());
2196 }
2197 }
2198 }
2200 void MacroAssembler::fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)
2201 {
2202 if (VM_Version::v9_instructions_work()) {
2203 Assembler::fabs(w, s, d);
2204 } else {
2205 if (w == FloatRegisterImpl::S) {
2206 Assembler::fabs(w, s, d);
2207 } else if (w == FloatRegisterImpl::D) {
2208 // number() does a sanity check on the alignment.
2209 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&
2210 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");
2212 Assembler::fabs(FloatRegisterImpl::S, s, d);
2213 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2214 } else {
2215 assert(w == FloatRegisterImpl::Q, "Invalid float register width");
2217 // number() does a sanity check on the alignment.
2218 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&
2219 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");
2221 Assembler::fabs(FloatRegisterImpl::S, s, d);
2222 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2223 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());
2224 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());
2225 }
2226 }
2227 }
2229 void MacroAssembler::save_all_globals_into_locals() {
2230 mov(G1,L1);
2231 mov(G2,L2);
2232 mov(G3,L3);
2233 mov(G4,L4);
2234 mov(G5,L5);
2235 mov(G6,L6);
2236 mov(G7,L7);
2237 }
2239 void MacroAssembler::restore_globals_from_locals() {
2240 mov(L1,G1);
2241 mov(L2,G2);
2242 mov(L3,G3);
2243 mov(L4,G4);
2244 mov(L5,G5);
2245 mov(L6,G6);
2246 mov(L7,G7);
2247 }
2249 // Use for 64 bit operation.
2250 void MacroAssembler::casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm)
2251 {
2252 // store ptr_reg as the new top value
2253 #ifdef _LP64
2254 casx(top_ptr_reg, top_reg, ptr_reg);
2255 #else
2256 cas_under_lock(top_ptr_reg, top_reg, ptr_reg, lock_addr, use_call_vm);
2257 #endif // _LP64
2258 }
2260 // [RGV] This routine does not handle 64 bit operations.
2261 // use casx_under_lock() or casx directly!!!
2262 void MacroAssembler::cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm)
2263 {
2264 // store ptr_reg as the new top value
2265 if (VM_Version::v9_instructions_work()) {
2266 cas(top_ptr_reg, top_reg, ptr_reg);
2267 } else {
2269 // If the register is not an out nor global, it is not visible
2270 // after the save. Allocate a register for it, save its
2271 // value in the register save area (the save may not flush
2272 // registers to the save area).
2274 Register top_ptr_reg_after_save;
2275 Register top_reg_after_save;
2276 Register ptr_reg_after_save;
2278 if (top_ptr_reg->is_out() || top_ptr_reg->is_global()) {
2279 top_ptr_reg_after_save = top_ptr_reg->after_save();
2280 } else {
2281 Address reg_save_addr = top_ptr_reg->address_in_saved_window();
2282 top_ptr_reg_after_save = L0;
2283 st(top_ptr_reg, reg_save_addr);
2284 }
2286 if (top_reg->is_out() || top_reg->is_global()) {
2287 top_reg_after_save = top_reg->after_save();
2288 } else {
2289 Address reg_save_addr = top_reg->address_in_saved_window();
2290 top_reg_after_save = L1;
2291 st(top_reg, reg_save_addr);
2292 }
2294 if (ptr_reg->is_out() || ptr_reg->is_global()) {
2295 ptr_reg_after_save = ptr_reg->after_save();
2296 } else {
2297 Address reg_save_addr = ptr_reg->address_in_saved_window();
2298 ptr_reg_after_save = L2;
2299 st(ptr_reg, reg_save_addr);
2300 }
2302 const Register& lock_reg = L3;
2303 const Register& lock_ptr_reg = L4;
2304 const Register& value_reg = L5;
2305 const Register& yield_reg = L6;
2306 const Register& yieldall_reg = L7;
2308 save_frame();
2310 if (top_ptr_reg_after_save == L0) {
2311 ld(top_ptr_reg->address_in_saved_window().after_save(), top_ptr_reg_after_save);
2312 }
2314 if (top_reg_after_save == L1) {
2315 ld(top_reg->address_in_saved_window().after_save(), top_reg_after_save);
2316 }
2318 if (ptr_reg_after_save == L2) {
2319 ld(ptr_reg->address_in_saved_window().after_save(), ptr_reg_after_save);
2320 }
2322 Label(retry_get_lock);
2323 Label(not_same);
2324 Label(dont_yield);
2326 assert(lock_addr, "lock_address should be non null for v8");
2327 set((intptr_t)lock_addr, lock_ptr_reg);
2328 // Initialize yield counter
2329 mov(G0,yield_reg);
2330 mov(G0, yieldall_reg);
2331 set(StubRoutines::Sparc::locked, lock_reg);
2333 bind(retry_get_lock);
2334 cmp_and_br_short(yield_reg, V8AtomicOperationUnderLockSpinCount, Assembler::less, Assembler::pt, dont_yield);
2336 if(use_call_vm) {
2337 Untested("Need to verify global reg consistancy");
2338 call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::yield_all), yieldall_reg);
2339 } else {
2340 // Save the regs and make space for a C call
2341 save(SP, -96, SP);
2342 save_all_globals_into_locals();
2343 call(CAST_FROM_FN_PTR(address,os::yield_all));
2344 delayed()->mov(yieldall_reg, O0);
2345 restore_globals_from_locals();
2346 restore();
2347 }
2349 // reset the counter
2350 mov(G0,yield_reg);
2351 add(yieldall_reg, 1, yieldall_reg);
2353 bind(dont_yield);
2354 // try to get lock
2355 Assembler::swap(lock_ptr_reg, 0, lock_reg);
2357 // did we get the lock?
2358 cmp(lock_reg, StubRoutines::Sparc::unlocked);
2359 br(Assembler::notEqual, true, Assembler::pn, retry_get_lock);
2360 delayed()->add(yield_reg,1,yield_reg);
2362 // yes, got lock. do we have the same top?
2363 ld(top_ptr_reg_after_save, 0, value_reg);
2364 cmp_and_br_short(value_reg, top_reg_after_save, Assembler::notEqual, Assembler::pn, not_same);
2366 // yes, same top.
2367 st(ptr_reg_after_save, top_ptr_reg_after_save, 0);
2368 membar(Assembler::StoreStore);
2370 bind(not_same);
2371 mov(value_reg, ptr_reg_after_save);
2372 st(lock_reg, lock_ptr_reg, 0); // unlock
2374 restore();
2375 }
2376 }
2378 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
2379 Register tmp,
2380 int offset) {
2381 intptr_t value = *delayed_value_addr;
2382 if (value != 0)
2383 return RegisterOrConstant(value + offset);
2385 // load indirectly to solve generation ordering problem
2386 AddressLiteral a(delayed_value_addr);
2387 load_ptr_contents(a, tmp);
2389 #ifdef ASSERT
2390 tst(tmp);
2391 breakpoint_trap(zero, xcc);
2392 #endif
2394 if (offset != 0)
2395 add(tmp, offset, tmp);
2397 return RegisterOrConstant(tmp);
2398 }
2401 RegisterOrConstant MacroAssembler::regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) {
2402 assert(d.register_or_noreg() != G0, "lost side effect");
2403 if ((s2.is_constant() && s2.as_constant() == 0) ||
2404 (s2.is_register() && s2.as_register() == G0)) {
2405 // Do nothing, just move value.
2406 if (s1.is_register()) {
2407 if (d.is_constant()) d = temp;
2408 mov(s1.as_register(), d.as_register());
2409 return d;
2410 } else {
2411 return s1;
2412 }
2413 }
2415 if (s1.is_register()) {
2416 assert_different_registers(s1.as_register(), temp);
2417 if (d.is_constant()) d = temp;
2418 andn(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register());
2419 return d;
2420 } else {
2421 if (s2.is_register()) {
2422 assert_different_registers(s2.as_register(), temp);
2423 if (d.is_constant()) d = temp;
2424 set(s1.as_constant(), temp);
2425 andn(temp, s2.as_register(), d.as_register());
2426 return d;
2427 } else {
2428 intptr_t res = s1.as_constant() & ~s2.as_constant();
2429 return res;
2430 }
2431 }
2432 }
2434 RegisterOrConstant MacroAssembler::regcon_inc_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) {
2435 assert(d.register_or_noreg() != G0, "lost side effect");
2436 if ((s2.is_constant() && s2.as_constant() == 0) ||
2437 (s2.is_register() && s2.as_register() == G0)) {
2438 // Do nothing, just move value.
2439 if (s1.is_register()) {
2440 if (d.is_constant()) d = temp;
2441 mov(s1.as_register(), d.as_register());
2442 return d;
2443 } else {
2444 return s1;
2445 }
2446 }
2448 if (s1.is_register()) {
2449 assert_different_registers(s1.as_register(), temp);
2450 if (d.is_constant()) d = temp;
2451 add(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register());
2452 return d;
2453 } else {
2454 if (s2.is_register()) {
2455 assert_different_registers(s2.as_register(), temp);
2456 if (d.is_constant()) d = temp;
2457 add(s2.as_register(), ensure_simm13_or_reg(s1, temp), d.as_register());
2458 return d;
2459 } else {
2460 intptr_t res = s1.as_constant() + s2.as_constant();
2461 return res;
2462 }
2463 }
2464 }
2466 RegisterOrConstant MacroAssembler::regcon_sll_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) {
2467 assert(d.register_or_noreg() != G0, "lost side effect");
2468 if (!is_simm13(s2.constant_or_zero()))
2469 s2 = (s2.as_constant() & 0xFF);
2470 if ((s2.is_constant() && s2.as_constant() == 0) ||
2471 (s2.is_register() && s2.as_register() == G0)) {
2472 // Do nothing, just move value.
2473 if (s1.is_register()) {
2474 if (d.is_constant()) d = temp;
2475 mov(s1.as_register(), d.as_register());
2476 return d;
2477 } else {
2478 return s1;
2479 }
2480 }
2482 if (s1.is_register()) {
2483 assert_different_registers(s1.as_register(), temp);
2484 if (d.is_constant()) d = temp;
2485 sll_ptr(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register());
2486 return d;
2487 } else {
2488 if (s2.is_register()) {
2489 assert_different_registers(s2.as_register(), temp);
2490 if (d.is_constant()) d = temp;
2491 set(s1.as_constant(), temp);
2492 sll_ptr(temp, s2.as_register(), d.as_register());
2493 return d;
2494 } else {
2495 intptr_t res = s1.as_constant() << s2.as_constant();
2496 return res;
2497 }
2498 }
2499 }
2502 // Look up the method for a megamorphic invokeinterface call.
2503 // The target method is determined by <intf_klass, itable_index>.
2504 // The receiver klass is in recv_klass.
2505 // On success, the result will be in method_result, and execution falls through.
2506 // On failure, execution transfers to the given label.
2507 void MacroAssembler::lookup_interface_method(Register recv_klass,
2508 Register intf_klass,
2509 RegisterOrConstant itable_index,
2510 Register method_result,
2511 Register scan_temp,
2512 Register sethi_temp,
2513 Label& L_no_such_interface) {
2514 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
2515 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
2516 "caller must use same register for non-constant itable index as for method");
2518 Label L_no_such_interface_restore;
2519 bool did_save = false;
2520 if (scan_temp == noreg || sethi_temp == noreg) {
2521 Register recv_2 = recv_klass->is_global() ? recv_klass : L0;
2522 Register intf_2 = intf_klass->is_global() ? intf_klass : L1;
2523 assert(method_result->is_global(), "must be able to return value");
2524 scan_temp = L2;
2525 sethi_temp = L3;
2526 save_frame_and_mov(0, recv_klass, recv_2, intf_klass, intf_2);
2527 recv_klass = recv_2;
2528 intf_klass = intf_2;
2529 did_save = true;
2530 }
2532 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
2533 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
2534 int scan_step = itableOffsetEntry::size() * wordSize;
2535 int vte_size = vtableEntry::size() * wordSize;
2537 lduw(recv_klass, InstanceKlass::vtable_length_offset() * wordSize, scan_temp);
2538 // %%% We should store the aligned, prescaled offset in the klassoop.
2539 // Then the next several instructions would fold away.
2541 int round_to_unit = ((HeapWordsPerLong > 1) ? BytesPerLong : 0);
2542 int itb_offset = vtable_base;
2543 if (round_to_unit != 0) {
2544 // hoist first instruction of round_to(scan_temp, BytesPerLong):
2545 itb_offset += round_to_unit - wordSize;
2546 }
2547 int itb_scale = exact_log2(vtableEntry::size() * wordSize);
2548 sll(scan_temp, itb_scale, scan_temp);
2549 add(scan_temp, itb_offset, scan_temp);
2550 if (round_to_unit != 0) {
2551 // Round up to align_object_offset boundary
2552 // see code for InstanceKlass::start_of_itable!
2553 // Was: round_to(scan_temp, BytesPerLong);
2554 // Hoisted: add(scan_temp, BytesPerLong-1, scan_temp);
2555 and3(scan_temp, -round_to_unit, scan_temp);
2556 }
2557 add(recv_klass, scan_temp, scan_temp);
2559 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
2560 RegisterOrConstant itable_offset = itable_index;
2561 itable_offset = regcon_sll_ptr(itable_index, exact_log2(itableMethodEntry::size() * wordSize), itable_offset);
2562 itable_offset = regcon_inc_ptr(itable_offset, itableMethodEntry::method_offset_in_bytes(), itable_offset);
2563 add(recv_klass, ensure_simm13_or_reg(itable_offset, sethi_temp), recv_klass);
2565 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
2566 // if (scan->interface() == intf) {
2567 // result = (klass + scan->offset() + itable_index);
2568 // }
2569 // }
2570 Label L_search, L_found_method;
2572 for (int peel = 1; peel >= 0; peel--) {
2573 // %%%% Could load both offset and interface in one ldx, if they were
2574 // in the opposite order. This would save a load.
2575 ld_ptr(scan_temp, itableOffsetEntry::interface_offset_in_bytes(), method_result);
2577 // Check that this entry is non-null. A null entry means that
2578 // the receiver class doesn't implement the interface, and wasn't the
2579 // same as when the caller was compiled.
2580 bpr(Assembler::rc_z, false, Assembler::pn, method_result, did_save ? L_no_such_interface_restore : L_no_such_interface);
2581 delayed()->cmp(method_result, intf_klass);
2583 if (peel) {
2584 brx(Assembler::equal, false, Assembler::pt, L_found_method);
2585 } else {
2586 brx(Assembler::notEqual, false, Assembler::pn, L_search);
2587 // (invert the test to fall through to found_method...)
2588 }
2589 delayed()->add(scan_temp, scan_step, scan_temp);
2591 if (!peel) break;
2593 bind(L_search);
2594 }
2596 bind(L_found_method);
2598 // Got a hit.
2599 int ito_offset = itableOffsetEntry::offset_offset_in_bytes();
2600 // scan_temp[-scan_step] points to the vtable offset we need
2601 ito_offset -= scan_step;
2602 lduw(scan_temp, ito_offset, scan_temp);
2603 ld_ptr(recv_klass, scan_temp, method_result);
2605 if (did_save) {
2606 Label L_done;
2607 ba(L_done);
2608 delayed()->restore();
2610 bind(L_no_such_interface_restore);
2611 ba(L_no_such_interface);
2612 delayed()->restore();
2614 bind(L_done);
2615 }
2616 }
2619 // virtual method calling
2620 void MacroAssembler::lookup_virtual_method(Register recv_klass,
2621 RegisterOrConstant vtable_index,
2622 Register method_result) {
2623 assert_different_registers(recv_klass, method_result, vtable_index.register_or_noreg());
2624 Register sethi_temp = method_result;
2625 const int base = (InstanceKlass::vtable_start_offset() * wordSize +
2626 // method pointer offset within the vtable entry:
2627 vtableEntry::method_offset_in_bytes());
2628 RegisterOrConstant vtable_offset = vtable_index;
2629 // Each of the following three lines potentially generates an instruction.
2630 // But the total number of address formation instructions will always be
2631 // at most two, and will often be zero. In any case, it will be optimal.
2632 // If vtable_index is a register, we will have (sll_ptr N,x; inc_ptr B,x; ld_ptr k,x).
2633 // If vtable_index is a constant, we will have at most (set B+X<<N,t; ld_ptr k,t).
2634 vtable_offset = regcon_sll_ptr(vtable_index, exact_log2(vtableEntry::size() * wordSize), vtable_offset);
2635 vtable_offset = regcon_inc_ptr(vtable_offset, base, vtable_offset, sethi_temp);
2636 Address vtable_entry_addr(recv_klass, ensure_simm13_or_reg(vtable_offset, sethi_temp));
2637 ld_ptr(vtable_entry_addr, method_result);
2638 }
2641 void MacroAssembler::check_klass_subtype(Register sub_klass,
2642 Register super_klass,
2643 Register temp_reg,
2644 Register temp2_reg,
2645 Label& L_success) {
2646 Register sub_2 = sub_klass;
2647 Register sup_2 = super_klass;
2648 if (!sub_2->is_global()) sub_2 = L0;
2649 if (!sup_2->is_global()) sup_2 = L1;
2650 bool did_save = false;
2651 if (temp_reg == noreg || temp2_reg == noreg) {
2652 temp_reg = L2;
2653 temp2_reg = L3;
2654 save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2);
2655 sub_klass = sub_2;
2656 super_klass = sup_2;
2657 did_save = true;
2658 }
2659 Label L_failure, L_pop_to_failure, L_pop_to_success;
2660 check_klass_subtype_fast_path(sub_klass, super_klass,
2661 temp_reg, temp2_reg,
2662 (did_save ? &L_pop_to_success : &L_success),
2663 (did_save ? &L_pop_to_failure : &L_failure), NULL);
2665 if (!did_save)
2666 save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2);
2667 check_klass_subtype_slow_path(sub_2, sup_2,
2668 L2, L3, L4, L5,
2669 NULL, &L_pop_to_failure);
2671 // on success:
2672 bind(L_pop_to_success);
2673 restore();
2674 ba_short(L_success);
2676 // on failure:
2677 bind(L_pop_to_failure);
2678 restore();
2679 bind(L_failure);
2680 }
2683 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
2684 Register super_klass,
2685 Register temp_reg,
2686 Register temp2_reg,
2687 Label* L_success,
2688 Label* L_failure,
2689 Label* L_slow_path,
2690 RegisterOrConstant super_check_offset) {
2691 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
2692 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2694 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
2695 bool need_slow_path = (must_load_sco ||
2696 super_check_offset.constant_or_zero() == sco_offset);
2698 assert_different_registers(sub_klass, super_klass, temp_reg);
2699 if (super_check_offset.is_register()) {
2700 assert_different_registers(sub_klass, super_klass, temp_reg,
2701 super_check_offset.as_register());
2702 } else if (must_load_sco) {
2703 assert(temp2_reg != noreg, "supply either a temp or a register offset");
2704 }
2706 Label L_fallthrough;
2707 int label_nulls = 0;
2708 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
2709 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
2710 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
2711 assert(label_nulls <= 1 ||
2712 (L_slow_path == &L_fallthrough && label_nulls <= 2 && !need_slow_path),
2713 "at most one NULL in the batch, usually");
2715 // If the pointers are equal, we are done (e.g., String[] elements).
2716 // This self-check enables sharing of secondary supertype arrays among
2717 // non-primary types such as array-of-interface. Otherwise, each such
2718 // type would need its own customized SSA.
2719 // We move this check to the front of the fast path because many
2720 // type checks are in fact trivially successful in this manner,
2721 // so we get a nicely predicted branch right at the start of the check.
2722 cmp(super_klass, sub_klass);
2723 brx(Assembler::equal, false, Assembler::pn, *L_success);
2724 delayed()->nop();
2726 // Check the supertype display:
2727 if (must_load_sco) {
2728 // The super check offset is always positive...
2729 lduw(super_klass, sco_offset, temp2_reg);
2730 super_check_offset = RegisterOrConstant(temp2_reg);
2731 // super_check_offset is register.
2732 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset.as_register());
2733 }
2734 ld_ptr(sub_klass, super_check_offset, temp_reg);
2735 cmp(super_klass, temp_reg);
2737 // This check has worked decisively for primary supers.
2738 // Secondary supers are sought in the super_cache ('super_cache_addr').
2739 // (Secondary supers are interfaces and very deeply nested subtypes.)
2740 // This works in the same check above because of a tricky aliasing
2741 // between the super_cache and the primary super display elements.
2742 // (The 'super_check_addr' can address either, as the case requires.)
2743 // Note that the cache is updated below if it does not help us find
2744 // what we need immediately.
2745 // So if it was a primary super, we can just fail immediately.
2746 // Otherwise, it's the slow path for us (no success at this point).
2748 // Hacked ba(), which may only be used just before L_fallthrough.
2749 #define FINAL_JUMP(label) \
2750 if (&(label) != &L_fallthrough) { \
2751 ba(label); delayed()->nop(); \
2752 }
2754 if (super_check_offset.is_register()) {
2755 brx(Assembler::equal, false, Assembler::pn, *L_success);
2756 delayed()->cmp(super_check_offset.as_register(), sc_offset);
2758 if (L_failure == &L_fallthrough) {
2759 brx(Assembler::equal, false, Assembler::pt, *L_slow_path);
2760 delayed()->nop();
2761 } else {
2762 brx(Assembler::notEqual, false, Assembler::pn, *L_failure);
2763 delayed()->nop();
2764 FINAL_JUMP(*L_slow_path);
2765 }
2766 } else if (super_check_offset.as_constant() == sc_offset) {
2767 // Need a slow path; fast failure is impossible.
2768 if (L_slow_path == &L_fallthrough) {
2769 brx(Assembler::equal, false, Assembler::pt, *L_success);
2770 delayed()->nop();
2771 } else {
2772 brx(Assembler::notEqual, false, Assembler::pn, *L_slow_path);
2773 delayed()->nop();
2774 FINAL_JUMP(*L_success);
2775 }
2776 } else {
2777 // No slow path; it's a fast decision.
2778 if (L_failure == &L_fallthrough) {
2779 brx(Assembler::equal, false, Assembler::pt, *L_success);
2780 delayed()->nop();
2781 } else {
2782 brx(Assembler::notEqual, false, Assembler::pn, *L_failure);
2783 delayed()->nop();
2784 FINAL_JUMP(*L_success);
2785 }
2786 }
2788 bind(L_fallthrough);
2790 #undef FINAL_JUMP
2791 }
2794 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
2795 Register super_klass,
2796 Register count_temp,
2797 Register scan_temp,
2798 Register scratch_reg,
2799 Register coop_reg,
2800 Label* L_success,
2801 Label* L_failure) {
2802 assert_different_registers(sub_klass, super_klass,
2803 count_temp, scan_temp, scratch_reg, coop_reg);
2805 Label L_fallthrough, L_loop;
2806 int label_nulls = 0;
2807 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
2808 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
2809 assert(label_nulls <= 1, "at most one NULL in the batch");
2811 // a couple of useful fields in sub_klass:
2812 int ss_offset = in_bytes(Klass::secondary_supers_offset());
2813 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
2815 // Do a linear scan of the secondary super-klass chain.
2816 // This code is rarely used, so simplicity is a virtue here.
2818 #ifndef PRODUCT
2819 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
2820 inc_counter((address) pst_counter, count_temp, scan_temp);
2821 #endif
2823 // We will consult the secondary-super array.
2824 ld_ptr(sub_klass, ss_offset, scan_temp);
2826 Register search_key = super_klass;
2828 // Load the array length. (Positive movl does right thing on LP64.)
2829 lduw(scan_temp, Array<Klass*>::length_offset_in_bytes(), count_temp);
2831 // Check for empty secondary super list
2832 tst(count_temp);
2834 // In the array of super classes elements are pointer sized.
2835 int element_size = wordSize;
2837 // Top of search loop
2838 bind(L_loop);
2839 br(Assembler::equal, false, Assembler::pn, *L_failure);
2840 delayed()->add(scan_temp, element_size, scan_temp);
2842 // Skip the array header in all array accesses.
2843 int elem_offset = Array<Klass*>::base_offset_in_bytes();
2844 elem_offset -= element_size; // the scan pointer was pre-incremented also
2846 // Load next super to check
2847 ld_ptr( scan_temp, elem_offset, scratch_reg );
2849 // Look for Rsuper_klass on Rsub_klass's secondary super-class-overflow list
2850 cmp(scratch_reg, search_key);
2852 // A miss means we are NOT a subtype and need to keep looping
2853 brx(Assembler::notEqual, false, Assembler::pn, L_loop);
2854 delayed()->deccc(count_temp); // decrement trip counter in delay slot
2856 // Success. Cache the super we found and proceed in triumph.
2857 st_ptr(super_klass, sub_klass, sc_offset);
2859 if (L_success != &L_fallthrough) {
2860 ba(*L_success);
2861 delayed()->nop();
2862 }
2864 bind(L_fallthrough);
2865 }
2868 RegisterOrConstant MacroAssembler::argument_offset(RegisterOrConstant arg_slot,
2869 Register temp_reg,
2870 int extra_slot_offset) {
2871 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
2872 int stackElementSize = Interpreter::stackElementSize;
2873 int offset = extra_slot_offset * stackElementSize;
2874 if (arg_slot.is_constant()) {
2875 offset += arg_slot.as_constant() * stackElementSize;
2876 return offset;
2877 } else {
2878 assert(temp_reg != noreg, "must specify");
2879 sll_ptr(arg_slot.as_register(), exact_log2(stackElementSize), temp_reg);
2880 if (offset != 0)
2881 add(temp_reg, offset, temp_reg);
2882 return temp_reg;
2883 }
2884 }
2887 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
2888 Register temp_reg,
2889 int extra_slot_offset) {
2890 return Address(Gargs, argument_offset(arg_slot, temp_reg, extra_slot_offset));
2891 }
2894 void MacroAssembler::biased_locking_enter(Register obj_reg, Register mark_reg,
2895 Register temp_reg,
2896 Label& done, Label* slow_case,
2897 BiasedLockingCounters* counters) {
2898 assert(UseBiasedLocking, "why call this otherwise?");
2900 if (PrintBiasedLockingStatistics) {
2901 assert_different_registers(obj_reg, mark_reg, temp_reg, O7);
2902 if (counters == NULL)
2903 counters = BiasedLocking::counters();
2904 }
2906 Label cas_label;
2908 // Biased locking
2909 // See whether the lock is currently biased toward our thread and
2910 // whether the epoch is still valid
2911 // Note that the runtime guarantees sufficient alignment of JavaThread
2912 // pointers to allow age to be placed into low bits
2913 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
2914 and3(mark_reg, markOopDesc::biased_lock_mask_in_place, temp_reg);
2915 cmp_and_brx_short(temp_reg, markOopDesc::biased_lock_pattern, Assembler::notEqual, Assembler::pn, cas_label);
2917 load_klass(obj_reg, temp_reg);
2918 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg);
2919 or3(G2_thread, temp_reg, temp_reg);
2920 xor3(mark_reg, temp_reg, temp_reg);
2921 andcc(temp_reg, ~((int) markOopDesc::age_mask_in_place), temp_reg);
2922 if (counters != NULL) {
2923 cond_inc(Assembler::equal, (address) counters->biased_lock_entry_count_addr(), mark_reg, temp_reg);
2924 // Reload mark_reg as we may need it later
2925 ld_ptr(Address(obj_reg, oopDesc::mark_offset_in_bytes()), mark_reg);
2926 }
2927 brx(Assembler::equal, true, Assembler::pt, done);
2928 delayed()->nop();
2930 Label try_revoke_bias;
2931 Label try_rebias;
2932 Address mark_addr = Address(obj_reg, oopDesc::mark_offset_in_bytes());
2933 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
2935 // At this point we know that the header has the bias pattern and
2936 // that we are not the bias owner in the current epoch. We need to
2937 // figure out more details about the state of the header in order to
2938 // know what operations can be legally performed on the object's
2939 // header.
2941 // If the low three bits in the xor result aren't clear, that means
2942 // the prototype header is no longer biased and we have to revoke
2943 // the bias on this object.
2944 btst(markOopDesc::biased_lock_mask_in_place, temp_reg);
2945 brx(Assembler::notZero, false, Assembler::pn, try_revoke_bias);
2947 // Biasing is still enabled for this data type. See whether the
2948 // epoch of the current bias is still valid, meaning that the epoch
2949 // bits of the mark word are equal to the epoch bits of the
2950 // prototype header. (Note that the prototype header's epoch bits
2951 // only change at a safepoint.) If not, attempt to rebias the object
2952 // toward the current thread. Note that we must be absolutely sure
2953 // that the current epoch is invalid in order to do this because
2954 // otherwise the manipulations it performs on the mark word are
2955 // illegal.
2956 delayed()->btst(markOopDesc::epoch_mask_in_place, temp_reg);
2957 brx(Assembler::notZero, false, Assembler::pn, try_rebias);
2959 // The epoch of the current bias is still valid but we know nothing
2960 // about the owner; it might be set or it might be clear. Try to
2961 // acquire the bias of the object using an atomic operation. If this
2962 // fails we will go in to the runtime to revoke the object's bias.
2963 // Note that we first construct the presumed unbiased header so we
2964 // don't accidentally blow away another thread's valid bias.
2965 delayed()->and3(mark_reg,
2966 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place,
2967 mark_reg);
2968 or3(G2_thread, mark_reg, temp_reg);
2969 casn(mark_addr.base(), mark_reg, temp_reg);
2970 // If the biasing toward our thread failed, this means that
2971 // another thread succeeded in biasing it toward itself and we
2972 // need to revoke that bias. The revocation will occur in the
2973 // interpreter runtime in the slow case.
2974 cmp(mark_reg, temp_reg);
2975 if (counters != NULL) {
2976 cond_inc(Assembler::zero, (address) counters->anonymously_biased_lock_entry_count_addr(), mark_reg, temp_reg);
2977 }
2978 if (slow_case != NULL) {
2979 brx(Assembler::notEqual, true, Assembler::pn, *slow_case);
2980 delayed()->nop();
2981 }
2982 ba_short(done);
2984 bind(try_rebias);
2985 // At this point we know the epoch has expired, meaning that the
2986 // current "bias owner", if any, is actually invalid. Under these
2987 // circumstances _only_, we are allowed to use the current header's
2988 // value as the comparison value when doing the cas to acquire the
2989 // bias in the current epoch. In other words, we allow transfer of
2990 // the bias from one thread to another directly in this situation.
2991 //
2992 // FIXME: due to a lack of registers we currently blow away the age
2993 // bits in this situation. Should attempt to preserve them.
2994 load_klass(obj_reg, temp_reg);
2995 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg);
2996 or3(G2_thread, temp_reg, temp_reg);
2997 casn(mark_addr.base(), mark_reg, temp_reg);
2998 // If the biasing toward our thread failed, this means that
2999 // another thread succeeded in biasing it toward itself and we
3000 // need to revoke that bias. The revocation will occur in the
3001 // interpreter runtime in the slow case.
3002 cmp(mark_reg, temp_reg);
3003 if (counters != NULL) {
3004 cond_inc(Assembler::zero, (address) counters->rebiased_lock_entry_count_addr(), mark_reg, temp_reg);
3005 }
3006 if (slow_case != NULL) {
3007 brx(Assembler::notEqual, true, Assembler::pn, *slow_case);
3008 delayed()->nop();
3009 }
3010 ba_short(done);
3012 bind(try_revoke_bias);
3013 // The prototype mark in the klass doesn't have the bias bit set any
3014 // more, indicating that objects of this data type are not supposed
3015 // to be biased any more. We are going to try to reset the mark of
3016 // this object to the prototype value and fall through to the
3017 // CAS-based locking scheme. Note that if our CAS fails, it means
3018 // that another thread raced us for the privilege of revoking the
3019 // bias of this particular object, so it's okay to continue in the
3020 // normal locking code.
3021 //
3022 // FIXME: due to a lack of registers we currently blow away the age
3023 // bits in this situation. Should attempt to preserve them.
3024 load_klass(obj_reg, temp_reg);
3025 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg);
3026 casn(mark_addr.base(), mark_reg, temp_reg);
3027 // Fall through to the normal CAS-based lock, because no matter what
3028 // the result of the above CAS, some thread must have succeeded in
3029 // removing the bias bit from the object's header.
3030 if (counters != NULL) {
3031 cmp(mark_reg, temp_reg);
3032 cond_inc(Assembler::zero, (address) counters->revoked_lock_entry_count_addr(), mark_reg, temp_reg);
3033 }
3035 bind(cas_label);
3036 }
3038 void MacroAssembler::biased_locking_exit (Address mark_addr, Register temp_reg, Label& done,
3039 bool allow_delay_slot_filling) {
3040 // Check for biased locking unlock case, which is a no-op
3041 // Note: we do not have to check the thread ID for two reasons.
3042 // First, the interpreter checks for IllegalMonitorStateException at
3043 // a higher level. Second, if the bias was revoked while we held the
3044 // lock, the object could not be rebiased toward another thread, so
3045 // the bias bit would be clear.
3046 ld_ptr(mark_addr, temp_reg);
3047 and3(temp_reg, markOopDesc::biased_lock_mask_in_place, temp_reg);
3048 cmp(temp_reg, markOopDesc::biased_lock_pattern);
3049 brx(Assembler::equal, allow_delay_slot_filling, Assembler::pt, done);
3050 delayed();
3051 if (!allow_delay_slot_filling) {
3052 nop();
3053 }
3054 }
3057 // CASN -- 32-64 bit switch hitter similar to the synthetic CASN provided by
3058 // Solaris/SPARC's "as". Another apt name would be cas_ptr()
3060 void MacroAssembler::casn (Register addr_reg, Register cmp_reg, Register set_reg ) {
3061 casx_under_lock (addr_reg, cmp_reg, set_reg, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
3062 }
3066 // compiler_lock_object() and compiler_unlock_object() are direct transliterations
3067 // of i486.ad fast_lock() and fast_unlock(). See those methods for detailed comments.
3068 // The code could be tightened up considerably.
3069 //
3070 // box->dhw disposition - post-conditions at DONE_LABEL.
3071 // - Successful inflated lock: box->dhw != 0.
3072 // Any non-zero value suffices.
3073 // Consider G2_thread, rsp, boxReg, or unused_mark()
3074 // - Successful Stack-lock: box->dhw == mark.
3075 // box->dhw must contain the displaced mark word value
3076 // - Failure -- icc.ZFlag == 0 and box->dhw is undefined.
3077 // The slow-path fast_enter() and slow_enter() operators
3078 // are responsible for setting box->dhw = NonZero (typically ::unused_mark).
3079 // - Biased: box->dhw is undefined
3080 //
3081 // SPARC refworkload performance - specifically jetstream and scimark - are
3082 // extremely sensitive to the size of the code emitted by compiler_lock_object
3083 // and compiler_unlock_object. Critically, the key factor is code size, not path
3084 // length. (Simply experiments to pad CLO with unexecuted NOPs demonstrte the
3085 // effect).
3088 void MacroAssembler::compiler_lock_object(Register Roop, Register Rmark,
3089 Register Rbox, Register Rscratch,
3090 BiasedLockingCounters* counters,
3091 bool try_bias) {
3092 Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
3094 verify_oop(Roop);
3095 Label done ;
3097 if (counters != NULL) {
3098 inc_counter((address) counters->total_entry_count_addr(), Rmark, Rscratch);
3099 }
3101 if (EmitSync & 1) {
3102 mov(3, Rscratch);
3103 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3104 cmp(SP, G0);
3105 return ;
3106 }
3108 if (EmitSync & 2) {
3110 // Fetch object's markword
3111 ld_ptr(mark_addr, Rmark);
3113 if (try_bias) {
3114 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
3115 }
3117 // Save Rbox in Rscratch to be used for the cas operation
3118 mov(Rbox, Rscratch);
3120 // set Rmark to markOop | markOopDesc::unlocked_value
3121 or3(Rmark, markOopDesc::unlocked_value, Rmark);
3123 // Initialize the box. (Must happen before we update the object mark!)
3124 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
3126 // compare object markOop with Rmark and if equal exchange Rscratch with object markOop
3127 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3128 casx_under_lock(mark_addr.base(), Rmark, Rscratch,
3129 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
3131 // if compare/exchange succeeded we found an unlocked object and we now have locked it
3132 // hence we are done
3133 cmp(Rmark, Rscratch);
3134 #ifdef _LP64
3135 sub(Rscratch, STACK_BIAS, Rscratch);
3136 #endif
3137 brx(Assembler::equal, false, Assembler::pt, done);
3138 delayed()->sub(Rscratch, SP, Rscratch); //pull next instruction into delay slot
3140 // we did not find an unlocked object so see if this is a recursive case
3141 // sub(Rscratch, SP, Rscratch);
3142 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
3143 andcc(Rscratch, 0xfffff003, Rscratch);
3144 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3145 bind (done);
3146 return ;
3147 }
3149 Label Egress ;
3151 if (EmitSync & 256) {
3152 Label IsInflated ;
3154 ld_ptr(mark_addr, Rmark); // fetch obj->mark
3155 // Triage: biased, stack-locked, neutral, inflated
3156 if (try_bias) {
3157 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
3158 // Invariant: if control reaches this point in the emitted stream
3159 // then Rmark has not been modified.
3160 }
3162 // Store mark into displaced mark field in the on-stack basic-lock "box"
3163 // Critically, this must happen before the CAS
3164 // Maximize the ST-CAS distance to minimize the ST-before-CAS penalty.
3165 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
3166 andcc(Rmark, 2, G0);
3167 brx(Assembler::notZero, false, Assembler::pn, IsInflated);
3168 delayed()->
3170 // Try stack-lock acquisition.
3171 // Beware: the 1st instruction is in a delay slot
3172 mov(Rbox, Rscratch);
3173 or3(Rmark, markOopDesc::unlocked_value, Rmark);
3174 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3175 casn(mark_addr.base(), Rmark, Rscratch);
3176 cmp(Rmark, Rscratch);
3177 brx(Assembler::equal, false, Assembler::pt, done);
3178 delayed()->sub(Rscratch, SP, Rscratch);
3180 // Stack-lock attempt failed - check for recursive stack-lock.
3181 // See the comments below about how we might remove this case.
3182 #ifdef _LP64
3183 sub(Rscratch, STACK_BIAS, Rscratch);
3184 #endif
3185 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
3186 andcc(Rscratch, 0xfffff003, Rscratch);
3187 br(Assembler::always, false, Assembler::pt, done);
3188 delayed()-> st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3190 bind(IsInflated);
3191 if (EmitSync & 64) {
3192 // If m->owner != null goto IsLocked
3193 // Pessimistic form: Test-and-CAS vs CAS
3194 // The optimistic form avoids RTS->RTO cache line upgrades.
3195 ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
3196 andcc(Rscratch, Rscratch, G0);
3197 brx(Assembler::notZero, false, Assembler::pn, done);
3198 delayed()->nop();
3199 // m->owner == null : it's unlocked.
3200 }
3202 // Try to CAS m->owner from null to Self
3203 // Invariant: if we acquire the lock then _recursions should be 0.
3204 add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark);
3205 mov(G2_thread, Rscratch);
3206 casn(Rmark, G0, Rscratch);
3207 cmp(Rscratch, G0);
3208 // Intentional fall-through into done
3209 } else {
3210 // Aggressively avoid the Store-before-CAS penalty
3211 // Defer the store into box->dhw until after the CAS
3212 Label IsInflated, Recursive ;
3214 // Anticipate CAS -- Avoid RTS->RTO upgrade
3215 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads);
3217 ld_ptr(mark_addr, Rmark); // fetch obj->mark
3218 // Triage: biased, stack-locked, neutral, inflated
3220 if (try_bias) {
3221 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
3222 // Invariant: if control reaches this point in the emitted stream
3223 // then Rmark has not been modified.
3224 }
3225 andcc(Rmark, 2, G0);
3226 brx(Assembler::notZero, false, Assembler::pn, IsInflated);
3227 delayed()-> // Beware - dangling delay-slot
3229 // Try stack-lock acquisition.
3230 // Transiently install BUSY (0) encoding in the mark word.
3231 // if the CAS of 0 into the mark was successful then we execute:
3232 // ST box->dhw = mark -- save fetched mark in on-stack basiclock box
3233 // ST obj->mark = box -- overwrite transient 0 value
3234 // This presumes TSO, of course.
3236 mov(0, Rscratch);
3237 or3(Rmark, markOopDesc::unlocked_value, Rmark);
3238 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3239 casn(mark_addr.base(), Rmark, Rscratch);
3240 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads);
3241 cmp(Rscratch, Rmark);
3242 brx(Assembler::notZero, false, Assembler::pn, Recursive);
3243 delayed()->st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
3244 if (counters != NULL) {
3245 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch);
3246 }
3247 ba(done);
3248 delayed()->st_ptr(Rbox, mark_addr);
3250 bind(Recursive);
3251 // Stack-lock attempt failed - check for recursive stack-lock.
3252 // Tests show that we can remove the recursive case with no impact
3253 // on refworkload 0.83. If we need to reduce the size of the code
3254 // emitted by compiler_lock_object() the recursive case is perfect
3255 // candidate.
3256 //
3257 // A more extreme idea is to always inflate on stack-lock recursion.
3258 // This lets us eliminate the recursive checks in compiler_lock_object
3259 // and compiler_unlock_object and the (box->dhw == 0) encoding.
3260 // A brief experiment - requiring changes to synchronizer.cpp, interpreter,
3261 // and showed a performance *increase*. In the same experiment I eliminated
3262 // the fast-path stack-lock code from the interpreter and always passed
3263 // control to the "slow" operators in synchronizer.cpp.
3265 // RScratch contains the fetched obj->mark value from the failed CASN.
3266 #ifdef _LP64
3267 sub(Rscratch, STACK_BIAS, Rscratch);
3268 #endif
3269 sub(Rscratch, SP, Rscratch);
3270 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
3271 andcc(Rscratch, 0xfffff003, Rscratch);
3272 if (counters != NULL) {
3273 // Accounting needs the Rscratch register
3274 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3275 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch);
3276 ba_short(done);
3277 } else {
3278 ba(done);
3279 delayed()->st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3280 }
3282 bind (IsInflated);
3283 if (EmitSync & 64) {
3284 // If m->owner != null goto IsLocked
3285 // Test-and-CAS vs CAS
3286 // Pessimistic form avoids futile (doomed) CAS attempts
3287 // The optimistic form avoids RTS->RTO cache line upgrades.
3288 ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
3289 andcc(Rscratch, Rscratch, G0);
3290 brx(Assembler::notZero, false, Assembler::pn, done);
3291 delayed()->nop();
3292 // m->owner == null : it's unlocked.
3293 }
3295 // Try to CAS m->owner from null to Self
3296 // Invariant: if we acquire the lock then _recursions should be 0.
3297 add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark);
3298 mov(G2_thread, Rscratch);
3299 casn(Rmark, G0, Rscratch);
3300 cmp(Rscratch, G0);
3301 // ST box->displaced_header = NonZero.
3302 // Any non-zero value suffices:
3303 // unused_mark(), G2_thread, RBox, RScratch, rsp, etc.
3304 st_ptr(Rbox, Rbox, BasicLock::displaced_header_offset_in_bytes());
3305 // Intentional fall-through into done
3306 }
3308 bind (done);
3309 }
3311 void MacroAssembler::compiler_unlock_object(Register Roop, Register Rmark,
3312 Register Rbox, Register Rscratch,
3313 bool try_bias) {
3314 Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
3316 Label done ;
3318 if (EmitSync & 4) {
3319 cmp(SP, G0);
3320 return ;
3321 }
3323 if (EmitSync & 8) {
3324 if (try_bias) {
3325 biased_locking_exit(mark_addr, Rscratch, done);
3326 }
3328 // Test first if it is a fast recursive unlock
3329 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rmark);
3330 br_null_short(Rmark, Assembler::pt, done);
3332 // Check if it is still a light weight lock, this is is true if we see
3333 // the stack address of the basicLock in the markOop of the object
3334 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3335 casx_under_lock(mark_addr.base(), Rbox, Rmark,
3336 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
3337 ba(done);
3338 delayed()->cmp(Rbox, Rmark);
3339 bind(done);
3340 return ;
3341 }
3343 // Beware ... If the aggregate size of the code emitted by CLO and CUO is
3344 // is too large performance rolls abruptly off a cliff.
3345 // This could be related to inlining policies, code cache management, or
3346 // I$ effects.
3347 Label LStacked ;
3349 if (try_bias) {
3350 // TODO: eliminate redundant LDs of obj->mark
3351 biased_locking_exit(mark_addr, Rscratch, done);
3352 }
3354 ld_ptr(Roop, oopDesc::mark_offset_in_bytes(), Rmark);
3355 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rscratch);
3356 andcc(Rscratch, Rscratch, G0);
3357 brx(Assembler::zero, false, Assembler::pn, done);
3358 delayed()->nop(); // consider: relocate fetch of mark, above, into this DS
3359 andcc(Rmark, 2, G0);
3360 brx(Assembler::zero, false, Assembler::pt, LStacked);
3361 delayed()->nop();
3363 // It's inflated
3364 // Conceptually we need a #loadstore|#storestore "release" MEMBAR before
3365 // the ST of 0 into _owner which releases the lock. This prevents loads
3366 // and stores within the critical section from reordering (floating)
3367 // past the store that releases the lock. But TSO is a strong memory model
3368 // and that particular flavor of barrier is a noop, so we can safely elide it.
3369 // Note that we use 1-0 locking by default for the inflated case. We
3370 // close the resultant (and rare) race by having contented threads in
3371 // monitorenter periodically poll _owner.
3372 ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
3373 ld_ptr(Rmark, ObjectMonitor::recursions_offset_in_bytes() - 2, Rbox);
3374 xor3(Rscratch, G2_thread, Rscratch);
3375 orcc(Rbox, Rscratch, Rbox);
3376 brx(Assembler::notZero, false, Assembler::pn, done);
3377 delayed()->
3378 ld_ptr(Rmark, ObjectMonitor::EntryList_offset_in_bytes() - 2, Rscratch);
3379 ld_ptr(Rmark, ObjectMonitor::cxq_offset_in_bytes() - 2, Rbox);
3380 orcc(Rbox, Rscratch, G0);
3381 if (EmitSync & 65536) {
3382 Label LSucc ;
3383 brx(Assembler::notZero, false, Assembler::pn, LSucc);
3384 delayed()->nop();
3385 ba(done);
3386 delayed()->st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
3388 bind(LSucc);
3389 st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
3390 if (os::is_MP()) { membar (StoreLoad); }
3391 ld_ptr(Rmark, ObjectMonitor::succ_offset_in_bytes() - 2, Rscratch);
3392 andcc(Rscratch, Rscratch, G0);
3393 brx(Assembler::notZero, false, Assembler::pt, done);
3394 delayed()->andcc(G0, G0, G0);
3395 add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark);
3396 mov(G2_thread, Rscratch);
3397 casn(Rmark, G0, Rscratch);
3398 // invert icc.zf and goto done
3399 br_notnull(Rscratch, false, Assembler::pt, done);
3400 delayed()->cmp(G0, G0);
3401 ba(done);
3402 delayed()->cmp(G0, 1);
3403 } else {
3404 brx(Assembler::notZero, false, Assembler::pn, done);
3405 delayed()->nop();
3406 ba(done);
3407 delayed()->st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
3408 }
3410 bind (LStacked);
3411 // Consider: we could replace the expensive CAS in the exit
3412 // path with a simple ST of the displaced mark value fetched from
3413 // the on-stack basiclock box. That admits a race where a thread T2
3414 // in the slow lock path -- inflating with monitor M -- could race a
3415 // thread T1 in the fast unlock path, resulting in a missed wakeup for T2.
3416 // More precisely T1 in the stack-lock unlock path could "stomp" the
3417 // inflated mark value M installed by T2, resulting in an orphan
3418 // object monitor M and T2 becoming stranded. We can remedy that situation
3419 // by having T2 periodically poll the object's mark word using timed wait
3420 // operations. If T2 discovers that a stomp has occurred it vacates
3421 // the monitor M and wakes any other threads stranded on the now-orphan M.
3422 // In addition the monitor scavenger, which performs deflation,
3423 // would also need to check for orpan monitors and stranded threads.
3424 //
3425 // Finally, inflation is also used when T2 needs to assign a hashCode
3426 // to O and O is stack-locked by T1. The "stomp" race could cause
3427 // an assigned hashCode value to be lost. We can avoid that condition
3428 // and provide the necessary hashCode stability invariants by ensuring
3429 // that hashCode generation is idempotent between copying GCs.
3430 // For example we could compute the hashCode of an object O as
3431 // O's heap address XOR some high quality RNG value that is refreshed
3432 // at GC-time. The monitor scavenger would install the hashCode
3433 // found in any orphan monitors. Again, the mechanism admits a
3434 // lost-update "stomp" WAW race but detects and recovers as needed.
3435 //
3436 // A prototype implementation showed excellent results, although
3437 // the scavenger and timeout code was rather involved.
3439 casn(mark_addr.base(), Rbox, Rscratch);
3440 cmp(Rbox, Rscratch);
3441 // Intentional fall through into done ...
3443 bind(done);
3444 }
3448 void MacroAssembler::print_CPU_state() {
3449 // %%%%% need to implement this
3450 }
3452 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
3453 // %%%%% need to implement this
3454 }
3456 void MacroAssembler::push_IU_state() {
3457 // %%%%% need to implement this
3458 }
3461 void MacroAssembler::pop_IU_state() {
3462 // %%%%% need to implement this
3463 }
3466 void MacroAssembler::push_FPU_state() {
3467 // %%%%% need to implement this
3468 }
3471 void MacroAssembler::pop_FPU_state() {
3472 // %%%%% need to implement this
3473 }
3476 void MacroAssembler::push_CPU_state() {
3477 // %%%%% need to implement this
3478 }
3481 void MacroAssembler::pop_CPU_state() {
3482 // %%%%% need to implement this
3483 }
3487 void MacroAssembler::verify_tlab() {
3488 #ifdef ASSERT
3489 if (UseTLAB && VerifyOops) {
3490 Label next, next2, ok;
3491 Register t1 = L0;
3492 Register t2 = L1;
3493 Register t3 = L2;
3495 save_frame(0);
3496 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1);
3497 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t2);
3498 or3(t1, t2, t3);
3499 cmp_and_br_short(t1, t2, Assembler::greaterEqual, Assembler::pn, next);
3500 STOP("assert(top >= start)");
3501 should_not_reach_here();
3503 bind(next);
3504 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1);
3505 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t2);
3506 or3(t3, t2, t3);
3507 cmp_and_br_short(t1, t2, Assembler::lessEqual, Assembler::pn, next2);
3508 STOP("assert(top <= end)");
3509 should_not_reach_here();
3511 bind(next2);
3512 and3(t3, MinObjAlignmentInBytesMask, t3);
3513 cmp_and_br_short(t3, 0, Assembler::lessEqual, Assembler::pn, ok);
3514 STOP("assert(aligned)");
3515 should_not_reach_here();
3517 bind(ok);
3518 restore();
3519 }
3520 #endif
3521 }
3524 void MacroAssembler::eden_allocate(
3525 Register obj, // result: pointer to object after successful allocation
3526 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
3527 int con_size_in_bytes, // object size in bytes if known at compile time
3528 Register t1, // temp register
3529 Register t2, // temp register
3530 Label& slow_case // continuation point if fast allocation fails
3531 ){
3532 // make sure arguments make sense
3533 assert_different_registers(obj, var_size_in_bytes, t1, t2);
3534 assert(0 <= con_size_in_bytes && Assembler::is_simm13(con_size_in_bytes), "illegal object size");
3535 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment");
3537 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
3538 // No allocation in the shared eden.
3539 ba_short(slow_case);
3540 } else {
3541 // get eden boundaries
3542 // note: we need both top & top_addr!
3543 const Register top_addr = t1;
3544 const Register end = t2;
3546 CollectedHeap* ch = Universe::heap();
3547 set((intx)ch->top_addr(), top_addr);
3548 intx delta = (intx)ch->end_addr() - (intx)ch->top_addr();
3549 ld_ptr(top_addr, delta, end);
3550 ld_ptr(top_addr, 0, obj);
3552 // try to allocate
3553 Label retry;
3554 bind(retry);
3555 #ifdef ASSERT
3556 // make sure eden top is properly aligned
3557 {
3558 Label L;
3559 btst(MinObjAlignmentInBytesMask, obj);
3560 br(Assembler::zero, false, Assembler::pt, L);
3561 delayed()->nop();
3562 STOP("eden top is not properly aligned");
3563 bind(L);
3564 }
3565 #endif // ASSERT
3566 const Register free = end;
3567 sub(end, obj, free); // compute amount of free space
3568 if (var_size_in_bytes->is_valid()) {
3569 // size is unknown at compile time
3570 cmp(free, var_size_in_bytes);
3571 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case
3572 delayed()->add(obj, var_size_in_bytes, end);
3573 } else {
3574 // size is known at compile time
3575 cmp(free, con_size_in_bytes);
3576 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case
3577 delayed()->add(obj, con_size_in_bytes, end);
3578 }
3579 // Compare obj with the value at top_addr; if still equal, swap the value of
3580 // end with the value at top_addr. If not equal, read the value at top_addr
3581 // into end.
3582 casx_under_lock(top_addr, obj, end, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
3583 // if someone beat us on the allocation, try again, otherwise continue
3584 cmp(obj, end);
3585 brx(Assembler::notEqual, false, Assembler::pn, retry);
3586 delayed()->mov(end, obj); // nop if successfull since obj == end
3588 #ifdef ASSERT
3589 // make sure eden top is properly aligned
3590 {
3591 Label L;
3592 const Register top_addr = t1;
3594 set((intx)ch->top_addr(), top_addr);
3595 ld_ptr(top_addr, 0, top_addr);
3596 btst(MinObjAlignmentInBytesMask, top_addr);
3597 br(Assembler::zero, false, Assembler::pt, L);
3598 delayed()->nop();
3599 STOP("eden top is not properly aligned");
3600 bind(L);
3601 }
3602 #endif // ASSERT
3603 }
3604 }
3607 void MacroAssembler::tlab_allocate(
3608 Register obj, // result: pointer to object after successful allocation
3609 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
3610 int con_size_in_bytes, // object size in bytes if known at compile time
3611 Register t1, // temp register
3612 Label& slow_case // continuation point if fast allocation fails
3613 ){
3614 // make sure arguments make sense
3615 assert_different_registers(obj, var_size_in_bytes, t1);
3616 assert(0 <= con_size_in_bytes && is_simm13(con_size_in_bytes), "illegal object size");
3617 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment");
3619 const Register free = t1;
3621 verify_tlab();
3623 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), obj);
3625 // calculate amount of free space
3626 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), free);
3627 sub(free, obj, free);
3629 Label done;
3630 if (var_size_in_bytes == noreg) {
3631 cmp(free, con_size_in_bytes);
3632 } else {
3633 cmp(free, var_size_in_bytes);
3634 }
3635 br(Assembler::less, false, Assembler::pn, slow_case);
3636 // calculate the new top pointer
3637 if (var_size_in_bytes == noreg) {
3638 delayed()->add(obj, con_size_in_bytes, free);
3639 } else {
3640 delayed()->add(obj, var_size_in_bytes, free);
3641 }
3643 bind(done);
3645 #ifdef ASSERT
3646 // make sure new free pointer is properly aligned
3647 {
3648 Label L;
3649 btst(MinObjAlignmentInBytesMask, free);
3650 br(Assembler::zero, false, Assembler::pt, L);
3651 delayed()->nop();
3652 STOP("updated TLAB free is not properly aligned");
3653 bind(L);
3654 }
3655 #endif // ASSERT
3657 // update the tlab top pointer
3658 st_ptr(free, G2_thread, in_bytes(JavaThread::tlab_top_offset()));
3659 verify_tlab();
3660 }
3663 void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) {
3664 Register top = O0;
3665 Register t1 = G1;
3666 Register t2 = G3;
3667 Register t3 = O1;
3668 assert_different_registers(top, t1, t2, t3, G4, G5 /* preserve G4 and G5 */);
3669 Label do_refill, discard_tlab;
3671 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
3672 // No allocation in the shared eden.
3673 ba_short(slow_case);
3674 }
3676 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), top);
3677 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t1);
3678 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), t2);
3680 // calculate amount of free space
3681 sub(t1, top, t1);
3682 srl_ptr(t1, LogHeapWordSize, t1);
3684 // Retain tlab and allocate object in shared space if
3685 // the amount free in the tlab is too large to discard.
3686 cmp(t1, t2);
3687 brx(Assembler::lessEqual, false, Assembler::pt, discard_tlab);
3689 // increment waste limit to prevent getting stuck on this slow path
3690 delayed()->add(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment(), t2);
3691 st_ptr(t2, G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()));
3692 if (TLABStats) {
3693 // increment number of slow_allocations
3694 ld(G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()), t2);
3695 add(t2, 1, t2);
3696 stw(t2, G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()));
3697 }
3698 ba_short(try_eden);
3700 bind(discard_tlab);
3701 if (TLABStats) {
3702 // increment number of refills
3703 ld(G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()), t2);
3704 add(t2, 1, t2);
3705 stw(t2, G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()));
3706 // accumulate wastage
3707 ld(G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()), t2);
3708 add(t2, t1, t2);
3709 stw(t2, G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()));
3710 }
3712 // if tlab is currently allocated (top or end != null) then
3713 // fill [top, end + alignment_reserve) with array object
3714 br_null_short(top, Assembler::pn, do_refill);
3716 set((intptr_t)markOopDesc::prototype()->copy_set_hash(0x2), t2);
3717 st_ptr(t2, top, oopDesc::mark_offset_in_bytes()); // set up the mark word
3718 // set klass to intArrayKlass
3719 sub(t1, typeArrayOopDesc::header_size(T_INT), t1);
3720 add(t1, ThreadLocalAllocBuffer::alignment_reserve(), t1);
3721 sll_ptr(t1, log2_intptr(HeapWordSize/sizeof(jint)), t1);
3722 st(t1, top, arrayOopDesc::length_offset_in_bytes());
3723 set((intptr_t)Universe::intArrayKlassObj_addr(), t2);
3724 ld_ptr(t2, 0, t2);
3725 // store klass last. concurrent gcs assumes klass length is valid if
3726 // klass field is not null.
3727 store_klass(t2, top);
3728 verify_oop(top);
3730 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t1);
3731 sub(top, t1, t1); // size of tlab's allocated portion
3732 incr_allocated_bytes(t1, t2, t3);
3734 // refill the tlab with an eden allocation
3735 bind(do_refill);
3736 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t1);
3737 sll_ptr(t1, LogHeapWordSize, t1);
3738 // allocate new tlab, address returned in top
3739 eden_allocate(top, t1, 0, t2, t3, slow_case);
3741 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_start_offset()));
3742 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_top_offset()));
3743 #ifdef ASSERT
3744 // check that tlab_size (t1) is still valid
3745 {
3746 Label ok;
3747 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t2);
3748 sll_ptr(t2, LogHeapWordSize, t2);
3749 cmp_and_br_short(t1, t2, Assembler::equal, Assembler::pt, ok);
3750 STOP("assert(t1 == tlab_size)");
3751 should_not_reach_here();
3753 bind(ok);
3754 }
3755 #endif // ASSERT
3756 add(top, t1, top); // t1 is tlab_size
3757 sub(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes(), top);
3758 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_end_offset()));
3759 verify_tlab();
3760 ba_short(retry);
3761 }
3763 void MacroAssembler::incr_allocated_bytes(RegisterOrConstant size_in_bytes,
3764 Register t1, Register t2) {
3765 // Bump total bytes allocated by this thread
3766 assert(t1->is_global(), "must be global reg"); // so all 64 bits are saved on a context switch
3767 assert_different_registers(size_in_bytes.register_or_noreg(), t1, t2);
3768 // v8 support has gone the way of the dodo
3769 ldx(G2_thread, in_bytes(JavaThread::allocated_bytes_offset()), t1);
3770 add(t1, ensure_simm13_or_reg(size_in_bytes, t2), t1);
3771 stx(t1, G2_thread, in_bytes(JavaThread::allocated_bytes_offset()));
3772 }
3774 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
3775 switch (cond) {
3776 // Note some conditions are synonyms for others
3777 case Assembler::never: return Assembler::always;
3778 case Assembler::zero: return Assembler::notZero;
3779 case Assembler::lessEqual: return Assembler::greater;
3780 case Assembler::less: return Assembler::greaterEqual;
3781 case Assembler::lessEqualUnsigned: return Assembler::greaterUnsigned;
3782 case Assembler::lessUnsigned: return Assembler::greaterEqualUnsigned;
3783 case Assembler::negative: return Assembler::positive;
3784 case Assembler::overflowSet: return Assembler::overflowClear;
3785 case Assembler::always: return Assembler::never;
3786 case Assembler::notZero: return Assembler::zero;
3787 case Assembler::greater: return Assembler::lessEqual;
3788 case Assembler::greaterEqual: return Assembler::less;
3789 case Assembler::greaterUnsigned: return Assembler::lessEqualUnsigned;
3790 case Assembler::greaterEqualUnsigned: return Assembler::lessUnsigned;
3791 case Assembler::positive: return Assembler::negative;
3792 case Assembler::overflowClear: return Assembler::overflowSet;
3793 }
3795 ShouldNotReachHere(); return Assembler::overflowClear;
3796 }
3798 void MacroAssembler::cond_inc(Assembler::Condition cond, address counter_ptr,
3799 Register Rtmp1, Register Rtmp2 /*, Register Rtmp3, Register Rtmp4 */) {
3800 Condition negated_cond = negate_condition(cond);
3801 Label L;
3802 brx(negated_cond, false, Assembler::pt, L);
3803 delayed()->nop();
3804 inc_counter(counter_ptr, Rtmp1, Rtmp2);
3805 bind(L);
3806 }
3808 void MacroAssembler::inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2) {
3809 AddressLiteral addrlit(counter_addr);
3810 sethi(addrlit, Rtmp1); // Move hi22 bits into temporary register.
3811 Address addr(Rtmp1, addrlit.low10()); // Build an address with low10 bits.
3812 ld(addr, Rtmp2);
3813 inc(Rtmp2);
3814 st(Rtmp2, addr);
3815 }
3817 void MacroAssembler::inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2) {
3818 inc_counter((address) counter_addr, Rtmp1, Rtmp2);
3819 }
3821 SkipIfEqual::SkipIfEqual(
3822 MacroAssembler* masm, Register temp, const bool* flag_addr,
3823 Assembler::Condition condition) {
3824 _masm = masm;
3825 AddressLiteral flag(flag_addr);
3826 _masm->sethi(flag, temp);
3827 _masm->ldub(temp, flag.low10(), temp);
3828 _masm->tst(temp);
3829 _masm->br(condition, false, Assembler::pt, _label);
3830 _masm->delayed()->nop();
3831 }
3833 SkipIfEqual::~SkipIfEqual() {
3834 _masm->bind(_label);
3835 }
3838 // Writes to stack successive pages until offset reached to check for
3839 // stack overflow + shadow pages. This clobbers tsp and scratch.
3840 void MacroAssembler::bang_stack_size(Register Rsize, Register Rtsp,
3841 Register Rscratch) {
3842 // Use stack pointer in temp stack pointer
3843 mov(SP, Rtsp);
3845 // Bang stack for total size given plus stack shadow page size.
3846 // Bang one page at a time because a large size can overflow yellow and
3847 // red zones (the bang will fail but stack overflow handling can't tell that
3848 // it was a stack overflow bang vs a regular segv).
3849 int offset = os::vm_page_size();
3850 Register Roffset = Rscratch;
3852 Label loop;
3853 bind(loop);
3854 set((-offset)+STACK_BIAS, Rscratch);
3855 st(G0, Rtsp, Rscratch);
3856 set(offset, Roffset);
3857 sub(Rsize, Roffset, Rsize);
3858 cmp(Rsize, G0);
3859 br(Assembler::greater, false, Assembler::pn, loop);
3860 delayed()->sub(Rtsp, Roffset, Rtsp);
3862 // Bang down shadow pages too.
3863 // The -1 because we already subtracted 1 page.
3864 for (int i = 0; i< StackShadowPages-1; i++) {
3865 set((-i*offset)+STACK_BIAS, Rscratch);
3866 st(G0, Rtsp, Rscratch);
3867 }
3868 }
3870 ///////////////////////////////////////////////////////////////////////////////////
3871 #if INCLUDE_ALL_GCS
3873 static address satb_log_enqueue_with_frame = NULL;
3874 static u_char* satb_log_enqueue_with_frame_end = NULL;
3876 static address satb_log_enqueue_frameless = NULL;
3877 static u_char* satb_log_enqueue_frameless_end = NULL;
3879 static int EnqueueCodeSize = 128 DEBUG_ONLY( + 256); // Instructions?
3881 static void generate_satb_log_enqueue(bool with_frame) {
3882 BufferBlob* bb = BufferBlob::create("enqueue_with_frame", EnqueueCodeSize);
3883 CodeBuffer buf(bb);
3884 MacroAssembler masm(&buf);
3886 #define __ masm.
3888 address start = __ pc();
3889 Register pre_val;
3891 Label refill, restart;
3892 if (with_frame) {
3893 __ save_frame(0);
3894 pre_val = I0; // Was O0 before the save.
3895 } else {
3896 pre_val = O0;
3897 }
3899 int satb_q_index_byte_offset =
3900 in_bytes(JavaThread::satb_mark_queue_offset() +
3901 PtrQueue::byte_offset_of_index());
3903 int satb_q_buf_byte_offset =
3904 in_bytes(JavaThread::satb_mark_queue_offset() +
3905 PtrQueue::byte_offset_of_buf());
3907 assert(in_bytes(PtrQueue::byte_width_of_index()) == sizeof(intptr_t) &&
3908 in_bytes(PtrQueue::byte_width_of_buf()) == sizeof(intptr_t),
3909 "check sizes in assembly below");
3911 __ bind(restart);
3913 // Load the index into the SATB buffer. PtrQueue::_index is a size_t
3914 // so ld_ptr is appropriate.
3915 __ ld_ptr(G2_thread, satb_q_index_byte_offset, L0);
3917 // index == 0?
3918 __ cmp_and_brx_short(L0, G0, Assembler::equal, Assembler::pn, refill);
3920 __ ld_ptr(G2_thread, satb_q_buf_byte_offset, L1);
3921 __ sub(L0, oopSize, L0);
3923 __ st_ptr(pre_val, L1, L0); // [_buf + index] := I0
3924 if (!with_frame) {
3925 // Use return-from-leaf
3926 __ retl();
3927 __ delayed()->st_ptr(L0, G2_thread, satb_q_index_byte_offset);
3928 } else {
3929 // Not delayed.
3930 __ st_ptr(L0, G2_thread, satb_q_index_byte_offset);
3931 }
3932 if (with_frame) {
3933 __ ret();
3934 __ delayed()->restore();
3935 }
3936 __ bind(refill);
3938 address handle_zero =
3939 CAST_FROM_FN_PTR(address,
3940 &SATBMarkQueueSet::handle_zero_index_for_thread);
3941 // This should be rare enough that we can afford to save all the
3942 // scratch registers that the calling context might be using.
3943 __ mov(G1_scratch, L0);
3944 __ mov(G3_scratch, L1);
3945 __ mov(G4, L2);
3946 // We need the value of O0 above (for the write into the buffer), so we
3947 // save and restore it.
3948 __ mov(O0, L3);
3949 // Since the call will overwrite O7, we save and restore that, as well.
3950 __ mov(O7, L4);
3951 __ call_VM_leaf(L5, handle_zero, G2_thread);
3952 __ mov(L0, G1_scratch);
3953 __ mov(L1, G3_scratch);
3954 __ mov(L2, G4);
3955 __ mov(L3, O0);
3956 __ br(Assembler::always, /*annul*/false, Assembler::pt, restart);
3957 __ delayed()->mov(L4, O7);
3959 if (with_frame) {
3960 satb_log_enqueue_with_frame = start;
3961 satb_log_enqueue_with_frame_end = __ pc();
3962 } else {
3963 satb_log_enqueue_frameless = start;
3964 satb_log_enqueue_frameless_end = __ pc();
3965 }
3967 #undef __
3968 }
3970 static inline void generate_satb_log_enqueue_if_necessary(bool with_frame) {
3971 if (with_frame) {
3972 if (satb_log_enqueue_with_frame == 0) {
3973 generate_satb_log_enqueue(with_frame);
3974 assert(satb_log_enqueue_with_frame != 0, "postcondition.");
3975 if (G1SATBPrintStubs) {
3976 tty->print_cr("Generated with-frame satb enqueue:");
3977 Disassembler::decode((u_char*)satb_log_enqueue_with_frame,
3978 satb_log_enqueue_with_frame_end,
3979 tty);
3980 }
3981 }
3982 } else {
3983 if (satb_log_enqueue_frameless == 0) {
3984 generate_satb_log_enqueue(with_frame);
3985 assert(satb_log_enqueue_frameless != 0, "postcondition.");
3986 if (G1SATBPrintStubs) {
3987 tty->print_cr("Generated frameless satb enqueue:");
3988 Disassembler::decode((u_char*)satb_log_enqueue_frameless,
3989 satb_log_enqueue_frameless_end,
3990 tty);
3991 }
3992 }
3993 }
3994 }
3996 void MacroAssembler::g1_write_barrier_pre(Register obj,
3997 Register index,
3998 int offset,
3999 Register pre_val,
4000 Register tmp,
4001 bool preserve_o_regs) {
4002 Label filtered;
4004 if (obj == noreg) {
4005 // We are not loading the previous value so make
4006 // sure that we don't trash the value in pre_val
4007 // with the code below.
4008 assert_different_registers(pre_val, tmp);
4009 } else {
4010 // We will be loading the previous value
4011 // in this code so...
4012 assert(offset == 0 || index == noreg, "choose one");
4013 assert(pre_val == noreg, "check this code");
4014 }
4016 // Is marking active?
4017 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
4018 ld(G2,
4019 in_bytes(JavaThread::satb_mark_queue_offset() +
4020 PtrQueue::byte_offset_of_active()),
4021 tmp);
4022 } else {
4023 guarantee(in_bytes(PtrQueue::byte_width_of_active()) == 1,
4024 "Assumption");
4025 ldsb(G2,
4026 in_bytes(JavaThread::satb_mark_queue_offset() +
4027 PtrQueue::byte_offset_of_active()),
4028 tmp);
4029 }
4031 // Is marking active?
4032 cmp_and_br_short(tmp, G0, Assembler::equal, Assembler::pt, filtered);
4034 // Do we need to load the previous value?
4035 if (obj != noreg) {
4036 // Load the previous value...
4037 if (index == noreg) {
4038 if (Assembler::is_simm13(offset)) {
4039 load_heap_oop(obj, offset, tmp);
4040 } else {
4041 set(offset, tmp);
4042 load_heap_oop(obj, tmp, tmp);
4043 }
4044 } else {
4045 load_heap_oop(obj, index, tmp);
4046 }
4047 // Previous value has been loaded into tmp
4048 pre_val = tmp;
4049 }
4051 assert(pre_val != noreg, "must have a real register");
4053 // Is the previous value null?
4054 cmp_and_brx_short(pre_val, G0, Assembler::equal, Assembler::pt, filtered);
4056 // OK, it's not filtered, so we'll need to call enqueue. In the normal
4057 // case, pre_val will be a scratch G-reg, but there are some cases in
4058 // which it's an O-reg. In the first case, do a normal call. In the
4059 // latter, do a save here and call the frameless version.
4061 guarantee(pre_val->is_global() || pre_val->is_out(),
4062 "Or we need to think harder.");
4064 if (pre_val->is_global() && !preserve_o_regs) {
4065 generate_satb_log_enqueue_if_necessary(true); // with frame
4067 call(satb_log_enqueue_with_frame);
4068 delayed()->mov(pre_val, O0);
4069 } else {
4070 generate_satb_log_enqueue_if_necessary(false); // frameless
4072 save_frame(0);
4073 call(satb_log_enqueue_frameless);
4074 delayed()->mov(pre_val->after_save(), O0);
4075 restore();
4076 }
4078 bind(filtered);
4079 }
4081 static address dirty_card_log_enqueue = 0;
4082 static u_char* dirty_card_log_enqueue_end = 0;
4084 // This gets to assume that o0 contains the object address.
4085 static void generate_dirty_card_log_enqueue(jbyte* byte_map_base) {
4086 BufferBlob* bb = BufferBlob::create("dirty_card_enqueue", EnqueueCodeSize*2);
4087 CodeBuffer buf(bb);
4088 MacroAssembler masm(&buf);
4089 #define __ masm.
4090 address start = __ pc();
4092 Label not_already_dirty, restart, refill;
4094 #ifdef _LP64
4095 __ srlx(O0, CardTableModRefBS::card_shift, O0);
4096 #else
4097 __ srl(O0, CardTableModRefBS::card_shift, O0);
4098 #endif
4099 AddressLiteral addrlit(byte_map_base);
4100 __ set(addrlit, O1); // O1 := <card table base>
4101 __ ldub(O0, O1, O2); // O2 := [O0 + O1]
4103 assert(CardTableModRefBS::dirty_card_val() == 0, "otherwise check this code");
4104 __ cmp_and_br_short(O2, G0, Assembler::notEqual, Assembler::pt, not_already_dirty);
4106 // We didn't take the branch, so we're already dirty: return.
4107 // Use return-from-leaf
4108 __ retl();
4109 __ delayed()->nop();
4111 // Not dirty.
4112 __ bind(not_already_dirty);
4114 // Get O0 + O1 into a reg by itself
4115 __ add(O0, O1, O3);
4117 // First, dirty it.
4118 __ stb(G0, O3, G0); // [cardPtr] := 0 (i.e., dirty).
4120 int dirty_card_q_index_byte_offset =
4121 in_bytes(JavaThread::dirty_card_queue_offset() +
4122 PtrQueue::byte_offset_of_index());
4123 int dirty_card_q_buf_byte_offset =
4124 in_bytes(JavaThread::dirty_card_queue_offset() +
4125 PtrQueue::byte_offset_of_buf());
4126 __ bind(restart);
4128 // Load the index into the update buffer. PtrQueue::_index is
4129 // a size_t so ld_ptr is appropriate here.
4130 __ ld_ptr(G2_thread, dirty_card_q_index_byte_offset, L0);
4132 // index == 0?
4133 __ cmp_and_brx_short(L0, G0, Assembler::equal, Assembler::pn, refill);
4135 __ ld_ptr(G2_thread, dirty_card_q_buf_byte_offset, L1);
4136 __ sub(L0, oopSize, L0);
4138 __ st_ptr(O3, L1, L0); // [_buf + index] := I0
4139 // Use return-from-leaf
4140 __ retl();
4141 __ delayed()->st_ptr(L0, G2_thread, dirty_card_q_index_byte_offset);
4143 __ bind(refill);
4144 address handle_zero =
4145 CAST_FROM_FN_PTR(address,
4146 &DirtyCardQueueSet::handle_zero_index_for_thread);
4147 // This should be rare enough that we can afford to save all the
4148 // scratch registers that the calling context might be using.
4149 __ mov(G1_scratch, L3);
4150 __ mov(G3_scratch, L5);
4151 // We need the value of O3 above (for the write into the buffer), so we
4152 // save and restore it.
4153 __ mov(O3, L6);
4154 // Since the call will overwrite O7, we save and restore that, as well.
4155 __ mov(O7, L4);
4157 __ call_VM_leaf(L7_thread_cache, handle_zero, G2_thread);
4158 __ mov(L3, G1_scratch);
4159 __ mov(L5, G3_scratch);
4160 __ mov(L6, O3);
4161 __ br(Assembler::always, /*annul*/false, Assembler::pt, restart);
4162 __ delayed()->mov(L4, O7);
4164 dirty_card_log_enqueue = start;
4165 dirty_card_log_enqueue_end = __ pc();
4166 // XXX Should have a guarantee here about not going off the end!
4167 // Does it already do so? Do an experiment...
4169 #undef __
4171 }
4173 static inline void
4174 generate_dirty_card_log_enqueue_if_necessary(jbyte* byte_map_base) {
4175 if (dirty_card_log_enqueue == 0) {
4176 generate_dirty_card_log_enqueue(byte_map_base);
4177 assert(dirty_card_log_enqueue != 0, "postcondition.");
4178 if (G1SATBPrintStubs) {
4179 tty->print_cr("Generated dirty_card enqueue:");
4180 Disassembler::decode((u_char*)dirty_card_log_enqueue,
4181 dirty_card_log_enqueue_end,
4182 tty);
4183 }
4184 }
4185 }
4188 void MacroAssembler::g1_write_barrier_post(Register store_addr, Register new_val, Register tmp) {
4190 Label filtered;
4191 MacroAssembler* post_filter_masm = this;
4193 if (new_val == G0) return;
4195 G1SATBCardTableModRefBS* bs = (G1SATBCardTableModRefBS*) Universe::heap()->barrier_set();
4196 assert(bs->kind() == BarrierSet::G1SATBCT ||
4197 bs->kind() == BarrierSet::G1SATBCTLogging, "wrong barrier");
4199 if (G1RSBarrierRegionFilter) {
4200 xor3(store_addr, new_val, tmp);
4201 #ifdef _LP64
4202 srlx(tmp, HeapRegion::LogOfHRGrainBytes, tmp);
4203 #else
4204 srl(tmp, HeapRegion::LogOfHRGrainBytes, tmp);
4205 #endif
4207 // XXX Should I predict this taken or not? Does it matter?
4208 cmp_and_brx_short(tmp, G0, Assembler::equal, Assembler::pt, filtered);
4209 }
4211 // If the "store_addr" register is an "in" or "local" register, move it to
4212 // a scratch reg so we can pass it as an argument.
4213 bool use_scr = !(store_addr->is_global() || store_addr->is_out());
4214 // Pick a scratch register different from "tmp".
4215 Register scr = (tmp == G1_scratch ? G3_scratch : G1_scratch);
4216 // Make sure we use up the delay slot!
4217 if (use_scr) {
4218 post_filter_masm->mov(store_addr, scr);
4219 } else {
4220 post_filter_masm->nop();
4221 }
4222 generate_dirty_card_log_enqueue_if_necessary(bs->byte_map_base);
4223 save_frame(0);
4224 call(dirty_card_log_enqueue);
4225 if (use_scr) {
4226 delayed()->mov(scr, O0);
4227 } else {
4228 delayed()->mov(store_addr->after_save(), O0);
4229 }
4230 restore();
4232 bind(filtered);
4233 }
4235 #endif // INCLUDE_ALL_GCS
4236 ///////////////////////////////////////////////////////////////////////////////////
4238 void MacroAssembler::card_write_barrier_post(Register store_addr, Register new_val, Register tmp) {
4239 // If we're writing constant NULL, we can skip the write barrier.
4240 if (new_val == G0) return;
4241 CardTableModRefBS* bs = (CardTableModRefBS*) Universe::heap()->barrier_set();
4242 assert(bs->kind() == BarrierSet::CardTableModRef ||
4243 bs->kind() == BarrierSet::CardTableExtension, "wrong barrier");
4244 card_table_write(bs->byte_map_base, tmp, store_addr);
4245 }
4247 void MacroAssembler::load_klass(Register src_oop, Register klass) {
4248 // The number of bytes in this code is used by
4249 // MachCallDynamicJavaNode::ret_addr_offset()
4250 // if this changes, change that.
4251 if (UseCompressedKlassPointers) {
4252 lduw(src_oop, oopDesc::klass_offset_in_bytes(), klass);
4253 decode_klass_not_null(klass);
4254 } else {
4255 ld_ptr(src_oop, oopDesc::klass_offset_in_bytes(), klass);
4256 }
4257 }
4259 void MacroAssembler::store_klass(Register klass, Register dst_oop) {
4260 if (UseCompressedKlassPointers) {
4261 assert(dst_oop != klass, "not enough registers");
4262 encode_klass_not_null(klass);
4263 st(klass, dst_oop, oopDesc::klass_offset_in_bytes());
4264 } else {
4265 st_ptr(klass, dst_oop, oopDesc::klass_offset_in_bytes());
4266 }
4267 }
4269 void MacroAssembler::store_klass_gap(Register s, Register d) {
4270 if (UseCompressedKlassPointers) {
4271 assert(s != d, "not enough registers");
4272 st(s, d, oopDesc::klass_gap_offset_in_bytes());
4273 }
4274 }
4276 void MacroAssembler::load_heap_oop(const Address& s, Register d) {
4277 if (UseCompressedOops) {
4278 lduw(s, d);
4279 decode_heap_oop(d);
4280 } else {
4281 ld_ptr(s, d);
4282 }
4283 }
4285 void MacroAssembler::load_heap_oop(Register s1, Register s2, Register d) {
4286 if (UseCompressedOops) {
4287 lduw(s1, s2, d);
4288 decode_heap_oop(d, d);
4289 } else {
4290 ld_ptr(s1, s2, d);
4291 }
4292 }
4294 void MacroAssembler::load_heap_oop(Register s1, int simm13a, Register d) {
4295 if (UseCompressedOops) {
4296 lduw(s1, simm13a, d);
4297 decode_heap_oop(d, d);
4298 } else {
4299 ld_ptr(s1, simm13a, d);
4300 }
4301 }
4303 void MacroAssembler::load_heap_oop(Register s1, RegisterOrConstant s2, Register d) {
4304 if (s2.is_constant()) load_heap_oop(s1, s2.as_constant(), d);
4305 else load_heap_oop(s1, s2.as_register(), d);
4306 }
4308 void MacroAssembler::store_heap_oop(Register d, Register s1, Register s2) {
4309 if (UseCompressedOops) {
4310 assert(s1 != d && s2 != d, "not enough registers");
4311 encode_heap_oop(d);
4312 st(d, s1, s2);
4313 } else {
4314 st_ptr(d, s1, s2);
4315 }
4316 }
4318 void MacroAssembler::store_heap_oop(Register d, Register s1, int simm13a) {
4319 if (UseCompressedOops) {
4320 assert(s1 != d, "not enough registers");
4321 encode_heap_oop(d);
4322 st(d, s1, simm13a);
4323 } else {
4324 st_ptr(d, s1, simm13a);
4325 }
4326 }
4328 void MacroAssembler::store_heap_oop(Register d, const Address& a, int offset) {
4329 if (UseCompressedOops) {
4330 assert(a.base() != d, "not enough registers");
4331 encode_heap_oop(d);
4332 st(d, a, offset);
4333 } else {
4334 st_ptr(d, a, offset);
4335 }
4336 }
4339 void MacroAssembler::encode_heap_oop(Register src, Register dst) {
4340 assert (UseCompressedOops, "must be compressed");
4341 assert (Universe::heap() != NULL, "java heap should be initialized");
4342 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4343 verify_oop(src);
4344 if (Universe::narrow_oop_base() == NULL) {
4345 srlx(src, LogMinObjAlignmentInBytes, dst);
4346 return;
4347 }
4348 Label done;
4349 if (src == dst) {
4350 // optimize for frequent case src == dst
4351 bpr(rc_nz, true, Assembler::pt, src, done);
4352 delayed() -> sub(src, G6_heapbase, dst); // annuled if not taken
4353 bind(done);
4354 srlx(src, LogMinObjAlignmentInBytes, dst);
4355 } else {
4356 bpr(rc_z, false, Assembler::pn, src, done);
4357 delayed() -> mov(G0, dst);
4358 // could be moved before branch, and annulate delay,
4359 // but may add some unneeded work decoding null
4360 sub(src, G6_heapbase, dst);
4361 srlx(dst, LogMinObjAlignmentInBytes, dst);
4362 bind(done);
4363 }
4364 }
4367 void MacroAssembler::encode_heap_oop_not_null(Register r) {
4368 assert (UseCompressedOops, "must be compressed");
4369 assert (Universe::heap() != NULL, "java heap should be initialized");
4370 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4371 verify_oop(r);
4372 if (Universe::narrow_oop_base() != NULL)
4373 sub(r, G6_heapbase, r);
4374 srlx(r, LogMinObjAlignmentInBytes, r);
4375 }
4377 void MacroAssembler::encode_heap_oop_not_null(Register src, Register dst) {
4378 assert (UseCompressedOops, "must be compressed");
4379 assert (Universe::heap() != NULL, "java heap should be initialized");
4380 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4381 verify_oop(src);
4382 if (Universe::narrow_oop_base() == NULL) {
4383 srlx(src, LogMinObjAlignmentInBytes, dst);
4384 } else {
4385 sub(src, G6_heapbase, dst);
4386 srlx(dst, LogMinObjAlignmentInBytes, dst);
4387 }
4388 }
4390 // Same algorithm as oops.inline.hpp decode_heap_oop.
4391 void MacroAssembler::decode_heap_oop(Register src, Register dst) {
4392 assert (UseCompressedOops, "must be compressed");
4393 assert (Universe::heap() != NULL, "java heap should be initialized");
4394 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4395 sllx(src, LogMinObjAlignmentInBytes, dst);
4396 if (Universe::narrow_oop_base() != NULL) {
4397 Label done;
4398 bpr(rc_nz, true, Assembler::pt, dst, done);
4399 delayed() -> add(dst, G6_heapbase, dst); // annuled if not taken
4400 bind(done);
4401 }
4402 verify_oop(dst);
4403 }
4405 void MacroAssembler::decode_heap_oop_not_null(Register r) {
4406 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
4407 // pd_code_size_limit.
4408 // Also do not verify_oop as this is called by verify_oop.
4409 assert (UseCompressedOops, "must be compressed");
4410 assert (Universe::heap() != NULL, "java heap should be initialized");
4411 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4412 sllx(r, LogMinObjAlignmentInBytes, r);
4413 if (Universe::narrow_oop_base() != NULL)
4414 add(r, G6_heapbase, r);
4415 }
4417 void MacroAssembler::decode_heap_oop_not_null(Register src, Register dst) {
4418 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
4419 // pd_code_size_limit.
4420 // Also do not verify_oop as this is called by verify_oop.
4421 assert (UseCompressedOops, "must be compressed");
4422 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4423 sllx(src, LogMinObjAlignmentInBytes, dst);
4424 if (Universe::narrow_oop_base() != NULL)
4425 add(dst, G6_heapbase, dst);
4426 }
4428 void MacroAssembler::encode_klass_not_null(Register r) {
4429 assert(Metaspace::is_initialized(), "metaspace should be initialized");
4430 assert (UseCompressedKlassPointers, "must be compressed");
4431 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
4432 if (Universe::narrow_klass_base() != NULL)
4433 sub(r, G6_heapbase, r);
4434 srlx(r, LogKlassAlignmentInBytes, r);
4435 }
4437 void MacroAssembler::encode_klass_not_null(Register src, Register dst) {
4438 assert(Metaspace::is_initialized(), "metaspace should be initialized");
4439 assert (UseCompressedKlassPointers, "must be compressed");
4440 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
4441 if (Universe::narrow_klass_base() == NULL) {
4442 srlx(src, LogKlassAlignmentInBytes, dst);
4443 } else {
4444 sub(src, G6_heapbase, dst);
4445 srlx(dst, LogKlassAlignmentInBytes, dst);
4446 }
4447 }
4449 void MacroAssembler::decode_klass_not_null(Register r) {
4450 assert(Metaspace::is_initialized(), "metaspace should be initialized");
4451 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
4452 // pd_code_size_limit.
4453 assert (UseCompressedKlassPointers, "must be compressed");
4454 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
4455 sllx(r, LogKlassAlignmentInBytes, r);
4456 if (Universe::narrow_klass_base() != NULL)
4457 add(r, G6_heapbase, r);
4458 }
4460 void MacroAssembler::decode_klass_not_null(Register src, Register dst) {
4461 assert(Metaspace::is_initialized(), "metaspace should be initialized");
4462 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
4463 // pd_code_size_limit.
4464 assert (UseCompressedKlassPointers, "must be compressed");
4465 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
4466 sllx(src, LogKlassAlignmentInBytes, dst);
4467 if (Universe::narrow_klass_base() != NULL)
4468 add(dst, G6_heapbase, dst);
4469 }
4471 void MacroAssembler::reinit_heapbase() {
4472 if (UseCompressedOops || UseCompressedKlassPointers) {
4473 AddressLiteral base(Universe::narrow_ptrs_base_addr());
4474 load_ptr_contents(base, G6_heapbase);
4475 }
4476 }
4478 // Compare char[] arrays aligned to 4 bytes.
4479 void MacroAssembler::char_arrays_equals(Register ary1, Register ary2,
4480 Register limit, Register result,
4481 Register chr1, Register chr2, Label& Ldone) {
4482 Label Lvector, Lloop;
4483 assert(chr1 == result, "should be the same");
4485 // Note: limit contains number of bytes (2*char_elements) != 0.
4486 andcc(limit, 0x2, chr1); // trailing character ?
4487 br(Assembler::zero, false, Assembler::pt, Lvector);
4488 delayed()->nop();
4490 // compare the trailing char
4491 sub(limit, sizeof(jchar), limit);
4492 lduh(ary1, limit, chr1);
4493 lduh(ary2, limit, chr2);
4494 cmp(chr1, chr2);
4495 br(Assembler::notEqual, true, Assembler::pt, Ldone);
4496 delayed()->mov(G0, result); // not equal
4498 // only one char ?
4499 cmp_zero_and_br(zero, limit, Ldone, true, Assembler::pn);
4500 delayed()->add(G0, 1, result); // zero-length arrays are equal
4502 // word by word compare, dont't need alignment check
4503 bind(Lvector);
4504 // Shift ary1 and ary2 to the end of the arrays, negate limit
4505 add(ary1, limit, ary1);
4506 add(ary2, limit, ary2);
4507 neg(limit, limit);
4509 lduw(ary1, limit, chr1);
4510 bind(Lloop);
4511 lduw(ary2, limit, chr2);
4512 cmp(chr1, chr2);
4513 br(Assembler::notEqual, true, Assembler::pt, Ldone);
4514 delayed()->mov(G0, result); // not equal
4515 inccc(limit, 2*sizeof(jchar));
4516 // annul LDUW if branch is not taken to prevent access past end of array
4517 br(Assembler::notZero, true, Assembler::pt, Lloop);
4518 delayed()->lduw(ary1, limit, chr1); // hoisted
4520 // Caller should set it:
4521 // add(G0, 1, result); // equals
4522 }
4524 // Use BIS for zeroing (count is in bytes).
4525 void MacroAssembler::bis_zeroing(Register to, Register count, Register temp, Label& Ldone) {
4526 assert(UseBlockZeroing && VM_Version::has_block_zeroing(), "only works with BIS zeroing");
4527 Register end = count;
4528 int cache_line_size = VM_Version::prefetch_data_size();
4529 // Minimum count when BIS zeroing can be used since
4530 // it needs membar which is expensive.
4531 int block_zero_size = MAX2(cache_line_size*3, (int)BlockZeroingLowLimit);
4533 Label small_loop;
4534 // Check if count is negative (dead code) or zero.
4535 // Note, count uses 64bit in 64 bit VM.
4536 cmp_and_brx_short(count, 0, Assembler::lessEqual, Assembler::pn, Ldone);
4538 // Use BIS zeroing only for big arrays since it requires membar.
4539 if (Assembler::is_simm13(block_zero_size)) { // < 4096
4540 cmp(count, block_zero_size);
4541 } else {
4542 set(block_zero_size, temp);
4543 cmp(count, temp);
4544 }
4545 br(Assembler::lessUnsigned, false, Assembler::pt, small_loop);
4546 delayed()->add(to, count, end);
4548 // Note: size is >= three (32 bytes) cache lines.
4550 // Clean the beginning of space up to next cache line.
4551 for (int offs = 0; offs < cache_line_size; offs += 8) {
4552 stx(G0, to, offs);
4553 }
4555 // align to next cache line
4556 add(to, cache_line_size, to);
4557 and3(to, -cache_line_size, to);
4559 // Note: size left >= two (32 bytes) cache lines.
4561 // BIS should not be used to zero tail (64 bytes)
4562 // to avoid zeroing a header of the following object.
4563 sub(end, (cache_line_size*2)-8, end);
4565 Label bis_loop;
4566 bind(bis_loop);
4567 stxa(G0, to, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
4568 add(to, cache_line_size, to);
4569 cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, bis_loop);
4571 // BIS needs membar.
4572 membar(Assembler::StoreLoad);
4574 add(end, (cache_line_size*2)-8, end); // restore end
4575 cmp_and_brx_short(to, end, Assembler::greaterEqualUnsigned, Assembler::pn, Ldone);
4577 // Clean the tail.
4578 bind(small_loop);
4579 stx(G0, to, 0);
4580 add(to, 8, to);
4581 cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, small_loop);
4582 nop(); // Separate short branches
4583 }