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src/cpu/x86/vm/x86_64.ad@006050192a5a
src/cpu/x86/vm/x86_64.ad
Mon, 20 Aug 2012 09:07:21 -0700
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- kvn
- date
- Mon, 20 Aug 2012 09:07:21 -0700
- changeset 4001
- 006050192a5a
- parent 3882
- 8c92982cbbc4
- child 4037
- da91efe96a93
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- -rw-r--r--
6340864: Implement vectorization optimizations in hotspot-server
Summary: Added asm encoding and mach nodes for vector arithmetic instructions on x86.
Reviewed-by: roland
1 //
2 // Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
25 // AMD64 Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
89 #ifdef _WIN64
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
97 #else
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
105 #endif
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
132 // Floating Point Registers
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
169 // Class for all pointer registers (including RSP)
170 reg_class any_reg(RAX, RAX_H,
171 RDX, RDX_H,
172 RBP, RBP_H,
173 RDI, RDI_H,
174 RSI, RSI_H,
175 RCX, RCX_H,
176 RBX, RBX_H,
177 RSP, RSP_H,
178 R8, R8_H,
179 R9, R9_H,
180 R10, R10_H,
181 R11, R11_H,
182 R12, R12_H,
183 R13, R13_H,
184 R14, R14_H,
185 R15, R15_H);
187 // Class for all pointer registers except RSP
188 reg_class ptr_reg(RAX, RAX_H,
189 RDX, RDX_H,
190 RBP, RBP_H,
191 RDI, RDI_H,
192 RSI, RSI_H,
193 RCX, RCX_H,
194 RBX, RBX_H,
195 R8, R8_H,
196 R9, R9_H,
197 R10, R10_H,
198 R11, R11_H,
199 R13, R13_H,
200 R14, R14_H);
202 // Class for all pointer registers except RAX and RSP
203 reg_class ptr_no_rax_reg(RDX, RDX_H,
204 RBP, RBP_H,
205 RDI, RDI_H,
206 RSI, RSI_H,
207 RCX, RCX_H,
208 RBX, RBX_H,
209 R8, R8_H,
210 R9, R9_H,
211 R10, R10_H,
212 R11, R11_H,
213 R13, R13_H,
214 R14, R14_H);
216 reg_class ptr_no_rbp_reg(RDX, RDX_H,
217 RAX, RAX_H,
218 RDI, RDI_H,
219 RSI, RSI_H,
220 RCX, RCX_H,
221 RBX, RBX_H,
222 R8, R8_H,
223 R9, R9_H,
224 R10, R10_H,
225 R11, R11_H,
226 R13, R13_H,
227 R14, R14_H);
229 // Class for all pointer registers except RAX, RBX and RSP
230 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
231 RBP, RBP_H,
232 RDI, RDI_H,
233 RSI, RSI_H,
234 RCX, RCX_H,
235 R8, R8_H,
236 R9, R9_H,
237 R10, R10_H,
238 R11, R11_H,
239 R13, R13_H,
240 R14, R14_H);
242 // Singleton class for RAX pointer register
243 reg_class ptr_rax_reg(RAX, RAX_H);
245 // Singleton class for RBX pointer register
246 reg_class ptr_rbx_reg(RBX, RBX_H);
248 // Singleton class for RSI pointer register
249 reg_class ptr_rsi_reg(RSI, RSI_H);
251 // Singleton class for RDI pointer register
252 reg_class ptr_rdi_reg(RDI, RDI_H);
254 // Singleton class for RBP pointer register
255 reg_class ptr_rbp_reg(RBP, RBP_H);
257 // Singleton class for stack pointer
258 reg_class ptr_rsp_reg(RSP, RSP_H);
260 // Singleton class for TLS pointer
261 reg_class ptr_r15_reg(R15, R15_H);
263 // Class for all long registers (except RSP)
264 reg_class long_reg(RAX, RAX_H,
265 RDX, RDX_H,
266 RBP, RBP_H,
267 RDI, RDI_H,
268 RSI, RSI_H,
269 RCX, RCX_H,
270 RBX, RBX_H,
271 R8, R8_H,
272 R9, R9_H,
273 R10, R10_H,
274 R11, R11_H,
275 R13, R13_H,
276 R14, R14_H);
278 // Class for all long registers except RAX, RDX (and RSP)
279 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
280 RDI, RDI_H,
281 RSI, RSI_H,
282 RCX, RCX_H,
283 RBX, RBX_H,
284 R8, R8_H,
285 R9, R9_H,
286 R10, R10_H,
287 R11, R11_H,
288 R13, R13_H,
289 R14, R14_H);
291 // Class for all long registers except RCX (and RSP)
292 reg_class long_no_rcx_reg(RBP, RBP_H,
293 RDI, RDI_H,
294 RSI, RSI_H,
295 RAX, RAX_H,
296 RDX, RDX_H,
297 RBX, RBX_H,
298 R8, R8_H,
299 R9, R9_H,
300 R10, R10_H,
301 R11, R11_H,
302 R13, R13_H,
303 R14, R14_H);
305 // Class for all long registers except RAX (and RSP)
306 reg_class long_no_rax_reg(RBP, RBP_H,
307 RDX, RDX_H,
308 RDI, RDI_H,
309 RSI, RSI_H,
310 RCX, RCX_H,
311 RBX, RBX_H,
312 R8, R8_H,
313 R9, R9_H,
314 R10, R10_H,
315 R11, R11_H,
316 R13, R13_H,
317 R14, R14_H);
319 // Singleton class for RAX long register
320 reg_class long_rax_reg(RAX, RAX_H);
322 // Singleton class for RCX long register
323 reg_class long_rcx_reg(RCX, RCX_H);
325 // Singleton class for RDX long register
326 reg_class long_rdx_reg(RDX, RDX_H);
328 // Class for all int registers (except RSP)
329 reg_class int_reg(RAX,
330 RDX,
331 RBP,
332 RDI,
333 RSI,
334 RCX,
335 RBX,
336 R8,
337 R9,
338 R10,
339 R11,
340 R13,
341 R14);
343 // Class for all int registers except RCX (and RSP)
344 reg_class int_no_rcx_reg(RAX,
345 RDX,
346 RBP,
347 RDI,
348 RSI,
349 RBX,
350 R8,
351 R9,
352 R10,
353 R11,
354 R13,
355 R14);
357 // Class for all int registers except RAX, RDX (and RSP)
358 reg_class int_no_rax_rdx_reg(RBP,
359 RDI,
360 RSI,
361 RCX,
362 RBX,
363 R8,
364 R9,
365 R10,
366 R11,
367 R13,
368 R14);
370 // Singleton class for RAX int register
371 reg_class int_rax_reg(RAX);
373 // Singleton class for RBX int register
374 reg_class int_rbx_reg(RBX);
376 // Singleton class for RCX int register
377 reg_class int_rcx_reg(RCX);
379 // Singleton class for RCX int register
380 reg_class int_rdx_reg(RDX);
382 // Singleton class for RCX int register
383 reg_class int_rdi_reg(RDI);
385 // Singleton class for instruction pointer
386 // reg_class ip_reg(RIP);
388 %}
390 //----------SOURCE BLOCK-------------------------------------------------------
391 // This is a block of C++ code which provides values, functions, and
392 // definitions necessary in the rest of the architecture description
393 source %{
394 #define RELOC_IMM64 Assembler::imm_operand
395 #define RELOC_DISP32 Assembler::disp32_operand
397 #define __ _masm.
399 static int preserve_SP_size() {
400 return 3; // rex.w, op, rm(reg/reg)
401 }
403 // !!!!! Special hack to get all types of calls to specify the byte offset
404 // from the start of the call to the point where the return address
405 // will point.
406 int MachCallStaticJavaNode::ret_addr_offset()
407 {
408 int offset = 5; // 5 bytes from start of call to where return address points
409 if (_method_handle_invoke)
410 offset += preserve_SP_size();
411 return offset;
412 }
414 int MachCallDynamicJavaNode::ret_addr_offset()
415 {
416 return 15; // 15 bytes from start of call to where return address points
417 }
419 // In os_cpu .ad file
420 // int MachCallRuntimeNode::ret_addr_offset()
422 // Indicate if the safepoint node needs the polling page as an input,
423 // it does if the polling page is more than disp32 away.
424 bool SafePointNode::needs_polling_address_input()
425 {
426 return Assembler::is_polling_page_far();
427 }
429 //
430 // Compute padding required for nodes which need alignment
431 //
433 // The address of the call instruction needs to be 4-byte aligned to
434 // ensure that it does not span a cache line so that it can be patched.
435 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
436 {
437 current_offset += 1; // skip call opcode byte
438 return round_to(current_offset, alignment_required()) - current_offset;
439 }
441 // The address of the call instruction needs to be 4-byte aligned to
442 // ensure that it does not span a cache line so that it can be patched.
443 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
444 {
445 current_offset += preserve_SP_size(); // skip mov rbp, rsp
446 current_offset += 1; // skip call opcode byte
447 return round_to(current_offset, alignment_required()) - current_offset;
448 }
450 // The address of the call instruction needs to be 4-byte aligned to
451 // ensure that it does not span a cache line so that it can be patched.
452 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
453 {
454 current_offset += 11; // skip movq instruction + call opcode byte
455 return round_to(current_offset, alignment_required()) - current_offset;
456 }
458 // EMIT_RM()
459 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
460 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
461 cbuf.insts()->emit_int8(c);
462 }
464 // EMIT_CC()
465 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
466 unsigned char c = (unsigned char) (f1 | f2);
467 cbuf.insts()->emit_int8(c);
468 }
470 // EMIT_OPCODE()
471 void emit_opcode(CodeBuffer &cbuf, int code) {
472 cbuf.insts()->emit_int8((unsigned char) code);
473 }
475 // EMIT_OPCODE() w/ relocation information
476 void emit_opcode(CodeBuffer &cbuf,
477 int code, relocInfo::relocType reloc, int offset, int format)
478 {
479 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
480 emit_opcode(cbuf, code);
481 }
483 // EMIT_D8()
484 void emit_d8(CodeBuffer &cbuf, int d8) {
485 cbuf.insts()->emit_int8((unsigned char) d8);
486 }
488 // EMIT_D16()
489 void emit_d16(CodeBuffer &cbuf, int d16) {
490 cbuf.insts()->emit_int16(d16);
491 }
493 // EMIT_D32()
494 void emit_d32(CodeBuffer &cbuf, int d32) {
495 cbuf.insts()->emit_int32(d32);
496 }
498 // EMIT_D64()
499 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
500 cbuf.insts()->emit_int64(d64);
501 }
503 // emit 32 bit value and construct relocation entry from relocInfo::relocType
504 void emit_d32_reloc(CodeBuffer& cbuf,
505 int d32,
506 relocInfo::relocType reloc,
507 int format)
508 {
509 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
510 cbuf.relocate(cbuf.insts_mark(), reloc, format);
511 cbuf.insts()->emit_int32(d32);
512 }
514 // emit 32 bit value and construct relocation entry from RelocationHolder
515 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
516 #ifdef ASSERT
517 if (rspec.reloc()->type() == relocInfo::oop_type &&
518 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
519 assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
520 }
521 #endif
522 cbuf.relocate(cbuf.insts_mark(), rspec, format);
523 cbuf.insts()->emit_int32(d32);
524 }
526 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
527 address next_ip = cbuf.insts_end() + 4;
528 emit_d32_reloc(cbuf, (int) (addr - next_ip),
529 external_word_Relocation::spec(addr),
530 RELOC_DISP32);
531 }
534 // emit 64 bit value and construct relocation entry from relocInfo::relocType
535 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
536 cbuf.relocate(cbuf.insts_mark(), reloc, format);
537 cbuf.insts()->emit_int64(d64);
538 }
540 // emit 64 bit value and construct relocation entry from RelocationHolder
541 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
542 #ifdef ASSERT
543 if (rspec.reloc()->type() == relocInfo::oop_type &&
544 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
545 assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()),
546 "cannot embed scavengable oops in code");
547 }
548 #endif
549 cbuf.relocate(cbuf.insts_mark(), rspec, format);
550 cbuf.insts()->emit_int64(d64);
551 }
553 // Access stack slot for load or store
554 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
555 {
556 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
557 if (-0x80 <= disp && disp < 0x80) {
558 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
559 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
560 emit_d8(cbuf, disp); // Displacement // R/M byte
561 } else {
562 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
563 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
564 emit_d32(cbuf, disp); // Displacement // R/M byte
565 }
566 }
568 // rRegI ereg, memory mem) %{ // emit_reg_mem
569 void encode_RegMem(CodeBuffer &cbuf,
570 int reg,
571 int base, int index, int scale, int disp, bool disp_is_oop)
572 {
573 assert(!disp_is_oop, "cannot have disp");
574 int regenc = reg & 7;
575 int baseenc = base & 7;
576 int indexenc = index & 7;
578 // There is no index & no scale, use form without SIB byte
579 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
580 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
581 if (disp == 0 && base != RBP_enc && base != R13_enc) {
582 emit_rm(cbuf, 0x0, regenc, baseenc); // *
583 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
584 // If 8-bit displacement, mode 0x1
585 emit_rm(cbuf, 0x1, regenc, baseenc); // *
586 emit_d8(cbuf, disp);
587 } else {
588 // If 32-bit displacement
589 if (base == -1) { // Special flag for absolute address
590 emit_rm(cbuf, 0x0, regenc, 0x5); // *
591 if (disp_is_oop) {
592 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
593 } else {
594 emit_d32(cbuf, disp);
595 }
596 } else {
597 // Normal base + offset
598 emit_rm(cbuf, 0x2, regenc, baseenc); // *
599 if (disp_is_oop) {
600 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
601 } else {
602 emit_d32(cbuf, disp);
603 }
604 }
605 }
606 } else {
607 // Else, encode with the SIB byte
608 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
609 if (disp == 0 && base != RBP_enc && base != R13_enc) {
610 // If no displacement
611 emit_rm(cbuf, 0x0, regenc, 0x4); // *
612 emit_rm(cbuf, scale, indexenc, baseenc);
613 } else {
614 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
615 // If 8-bit displacement, mode 0x1
616 emit_rm(cbuf, 0x1, regenc, 0x4); // *
617 emit_rm(cbuf, scale, indexenc, baseenc);
618 emit_d8(cbuf, disp);
619 } else {
620 // If 32-bit displacement
621 if (base == 0x04 ) {
622 emit_rm(cbuf, 0x2, regenc, 0x4);
623 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
624 } else {
625 emit_rm(cbuf, 0x2, regenc, 0x4);
626 emit_rm(cbuf, scale, indexenc, baseenc); // *
627 }
628 if (disp_is_oop) {
629 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
630 } else {
631 emit_d32(cbuf, disp);
632 }
633 }
634 }
635 }
636 }
638 // This could be in MacroAssembler but it's fairly C2 specific
639 void emit_cmpfp_fixup(MacroAssembler& _masm) {
640 Label exit;
641 __ jccb(Assembler::noParity, exit);
642 __ pushf();
643 //
644 // comiss/ucomiss instructions set ZF,PF,CF flags and
645 // zero OF,AF,SF for NaN values.
646 // Fixup flags by zeroing ZF,PF so that compare of NaN
647 // values returns 'less than' result (CF is set).
648 // Leave the rest of flags unchanged.
649 //
650 // 7 6 5 4 3 2 1 0
651 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
652 // 0 0 1 0 1 0 1 1 (0x2B)
653 //
654 __ andq(Address(rsp, 0), 0xffffff2b);
655 __ popf();
656 __ bind(exit);
657 }
659 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
660 Label done;
661 __ movl(dst, -1);
662 __ jcc(Assembler::parity, done);
663 __ jcc(Assembler::below, done);
664 __ setb(Assembler::notEqual, dst);
665 __ movzbl(dst, dst);
666 __ bind(done);
667 }
670 //=============================================================================
671 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
673 int Compile::ConstantTable::calculate_table_base_offset() const {
674 return 0; // absolute addressing, no offset
675 }
677 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
678 // Empty encoding
679 }
681 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
682 return 0;
683 }
685 #ifndef PRODUCT
686 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
687 st->print("# MachConstantBaseNode (empty encoding)");
688 }
689 #endif
692 //=============================================================================
693 #ifndef PRODUCT
694 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
695 Compile* C = ra_->C;
697 int framesize = C->frame_slots() << LogBytesPerInt;
698 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
699 // Remove wordSize for return addr which is already pushed.
700 framesize -= wordSize;
702 if (C->need_stack_bang(framesize)) {
703 framesize -= wordSize;
704 st->print("# stack bang");
705 st->print("\n\t");
706 st->print("pushq rbp\t# Save rbp");
707 if (framesize) {
708 st->print("\n\t");
709 st->print("subq rsp, #%d\t# Create frame",framesize);
710 }
711 } else {
712 st->print("subq rsp, #%d\t# Create frame",framesize);
713 st->print("\n\t");
714 framesize -= wordSize;
715 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
716 }
718 if (VerifyStackAtCalls) {
719 st->print("\n\t");
720 framesize -= wordSize;
721 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
722 #ifdef ASSERT
723 st->print("\n\t");
724 st->print("# stack alignment check");
725 #endif
726 }
727 st->cr();
728 }
729 #endif
731 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
732 Compile* C = ra_->C;
733 MacroAssembler _masm(&cbuf);
735 int framesize = C->frame_slots() << LogBytesPerInt;
737 __ verified_entry(framesize, C->need_stack_bang(framesize), false);
739 C->set_frame_complete(cbuf.insts_size());
741 if (C->has_mach_constant_base_node()) {
742 // NOTE: We set the table base offset here because users might be
743 // emitted before MachConstantBaseNode.
744 Compile::ConstantTable& constant_table = C->constant_table();
745 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
746 }
747 }
749 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
750 {
751 return MachNode::size(ra_); // too many variables; just compute it
752 // the hard way
753 }
755 int MachPrologNode::reloc() const
756 {
757 return 0; // a large enough number
758 }
760 //=============================================================================
761 #ifndef PRODUCT
762 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
763 {
764 Compile* C = ra_->C;
765 int framesize = C->frame_slots() << LogBytesPerInt;
766 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
767 // Remove word for return adr already pushed
768 // and RBP
769 framesize -= 2*wordSize;
771 if (framesize) {
772 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
773 st->print("\t");
774 }
776 st->print_cr("popq rbp");
777 if (do_polling() && C->is_method_compilation()) {
778 st->print("\t");
779 if (Assembler::is_polling_page_far()) {
780 st->print_cr("movq rscratch1, #polling_page_address\n\t"
781 "testl rax, [rscratch1]\t"
782 "# Safepoint: poll for GC");
783 } else {
784 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
785 "# Safepoint: poll for GC");
786 }
787 }
788 }
789 #endif
791 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
792 {
793 Compile* C = ra_->C;
794 int framesize = C->frame_slots() << LogBytesPerInt;
795 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
796 // Remove word for return adr already pushed
797 // and RBP
798 framesize -= 2*wordSize;
800 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
802 if (framesize) {
803 emit_opcode(cbuf, Assembler::REX_W);
804 if (framesize < 0x80) {
805 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
806 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
807 emit_d8(cbuf, framesize);
808 } else {
809 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
810 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
811 emit_d32(cbuf, framesize);
812 }
813 }
815 // popq rbp
816 emit_opcode(cbuf, 0x58 | RBP_enc);
818 if (do_polling() && C->is_method_compilation()) {
819 MacroAssembler _masm(&cbuf);
820 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
821 if (Assembler::is_polling_page_far()) {
822 __ lea(rscratch1, polling_page);
823 __ relocate(relocInfo::poll_return_type);
824 __ testl(rax, Address(rscratch1, 0));
825 } else {
826 __ testl(rax, polling_page);
827 }
828 }
829 }
831 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
832 {
833 return MachNode::size(ra_); // too many variables; just compute it
834 // the hard way
835 }
837 int MachEpilogNode::reloc() const
838 {
839 return 2; // a large enough number
840 }
842 const Pipeline* MachEpilogNode::pipeline() const
843 {
844 return MachNode::pipeline_class();
845 }
847 int MachEpilogNode::safepoint_offset() const
848 {
849 return 0;
850 }
852 //=============================================================================
854 enum RC {
855 rc_bad,
856 rc_int,
857 rc_float,
858 rc_stack
859 };
861 static enum RC rc_class(OptoReg::Name reg)
862 {
863 if( !OptoReg::is_valid(reg) ) return rc_bad;
865 if (OptoReg::is_stack(reg)) return rc_stack;
867 VMReg r = OptoReg::as_VMReg(reg);
869 if (r->is_Register()) return rc_int;
871 assert(r->is_XMMRegister(), "must be");
872 return rc_float;
873 }
875 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
876 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
877 int src_hi, int dst_hi, uint ireg, outputStream* st);
879 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
880 int stack_offset, int reg, uint ireg, outputStream* st);
882 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
883 int dst_offset, uint ireg, outputStream* st) {
884 if (cbuf) {
885 MacroAssembler _masm(cbuf);
886 switch (ireg) {
887 case Op_VecS:
888 __ movq(Address(rsp, -8), rax);
889 __ movl(rax, Address(rsp, src_offset));
890 __ movl(Address(rsp, dst_offset), rax);
891 __ movq(rax, Address(rsp, -8));
892 break;
893 case Op_VecD:
894 __ pushq(Address(rsp, src_offset));
895 __ popq (Address(rsp, dst_offset));
896 break;
897 case Op_VecX:
898 __ pushq(Address(rsp, src_offset));
899 __ popq (Address(rsp, dst_offset));
900 __ pushq(Address(rsp, src_offset+8));
901 __ popq (Address(rsp, dst_offset+8));
902 break;
903 case Op_VecY:
904 __ vmovdqu(Address(rsp, -32), xmm0);
905 __ vmovdqu(xmm0, Address(rsp, src_offset));
906 __ vmovdqu(Address(rsp, dst_offset), xmm0);
907 __ vmovdqu(xmm0, Address(rsp, -32));
908 break;
909 default:
910 ShouldNotReachHere();
911 }
912 #ifndef PRODUCT
913 } else {
914 switch (ireg) {
915 case Op_VecS:
916 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
917 "movl rax, [rsp + #%d]\n\t"
918 "movl [rsp + #%d], rax\n\t"
919 "movq rax, [rsp - #8]",
920 src_offset, dst_offset);
921 break;
922 case Op_VecD:
923 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
924 "popq [rsp + #%d]",
925 src_offset, dst_offset);
926 break;
927 case Op_VecX:
928 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
929 "popq [rsp + #%d]\n\t"
930 "pushq [rsp + #%d]\n\t"
931 "popq [rsp + #%d]",
932 src_offset, dst_offset, src_offset+8, dst_offset+8);
933 break;
934 case Op_VecY:
935 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
936 "vmovdqu xmm0, [rsp + #%d]\n\t"
937 "vmovdqu [rsp + #%d], xmm0\n\t"
938 "vmovdqu xmm0, [rsp - #32]",
939 src_offset, dst_offset);
940 break;
941 default:
942 ShouldNotReachHere();
943 }
944 #endif
945 }
946 }
948 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
949 PhaseRegAlloc* ra_,
950 bool do_size,
951 outputStream* st) const {
952 assert(cbuf != NULL || st != NULL, "sanity");
953 // Get registers to move
954 OptoReg::Name src_second = ra_->get_reg_second(in(1));
955 OptoReg::Name src_first = ra_->get_reg_first(in(1));
956 OptoReg::Name dst_second = ra_->get_reg_second(this);
957 OptoReg::Name dst_first = ra_->get_reg_first(this);
959 enum RC src_second_rc = rc_class(src_second);
960 enum RC src_first_rc = rc_class(src_first);
961 enum RC dst_second_rc = rc_class(dst_second);
962 enum RC dst_first_rc = rc_class(dst_first);
964 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
965 "must move at least 1 register" );
967 if (src_first == dst_first && src_second == dst_second) {
968 // Self copy, no move
969 return 0;
970 }
971 if (bottom_type()->isa_vect() != NULL) {
972 uint ireg = ideal_reg();
973 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
974 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
975 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
976 // mem -> mem
977 int src_offset = ra_->reg2offset(src_first);
978 int dst_offset = ra_->reg2offset(dst_first);
979 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
980 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
981 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
982 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
983 int stack_offset = ra_->reg2offset(dst_first);
984 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
985 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
986 int stack_offset = ra_->reg2offset(src_first);
987 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
988 } else {
989 ShouldNotReachHere();
990 }
991 return 0;
992 }
993 if (src_first_rc == rc_stack) {
994 // mem ->
995 if (dst_first_rc == rc_stack) {
996 // mem -> mem
997 assert(src_second != dst_first, "overlap");
998 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
999 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1000 // 64-bit
1001 int src_offset = ra_->reg2offset(src_first);
1002 int dst_offset = ra_->reg2offset(dst_first);
1003 if (cbuf) {
1004 MacroAssembler _masm(cbuf);
1005 __ pushq(Address(rsp, src_offset));
1006 __ popq (Address(rsp, dst_offset));
1007 #ifndef PRODUCT
1008 } else {
1009 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1010 "popq [rsp + #%d]",
1011 src_offset, dst_offset);
1012 #endif
1013 }
1014 } else {
1015 // 32-bit
1016 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1017 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1018 // No pushl/popl, so:
1019 int src_offset = ra_->reg2offset(src_first);
1020 int dst_offset = ra_->reg2offset(dst_first);
1021 if (cbuf) {
1022 MacroAssembler _masm(cbuf);
1023 __ movq(Address(rsp, -8), rax);
1024 __ movl(rax, Address(rsp, src_offset));
1025 __ movl(Address(rsp, dst_offset), rax);
1026 __ movq(rax, Address(rsp, -8));
1027 #ifndef PRODUCT
1028 } else {
1029 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1030 "movl rax, [rsp + #%d]\n\t"
1031 "movl [rsp + #%d], rax\n\t"
1032 "movq rax, [rsp - #8]",
1033 src_offset, dst_offset);
1034 #endif
1035 }
1036 }
1037 return 0;
1038 } else if (dst_first_rc == rc_int) {
1039 // mem -> gpr
1040 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1041 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1042 // 64-bit
1043 int offset = ra_->reg2offset(src_first);
1044 if (cbuf) {
1045 MacroAssembler _masm(cbuf);
1046 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1047 #ifndef PRODUCT
1048 } else {
1049 st->print("movq %s, [rsp + #%d]\t# spill",
1050 Matcher::regName[dst_first],
1051 offset);
1052 #endif
1053 }
1054 } else {
1055 // 32-bit
1056 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1057 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1058 int offset = ra_->reg2offset(src_first);
1059 if (cbuf) {
1060 MacroAssembler _masm(cbuf);
1061 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1062 #ifndef PRODUCT
1063 } else {
1064 st->print("movl %s, [rsp + #%d]\t# spill",
1065 Matcher::regName[dst_first],
1066 offset);
1067 #endif
1068 }
1069 }
1070 return 0;
1071 } else if (dst_first_rc == rc_float) {
1072 // mem-> xmm
1073 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1074 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1075 // 64-bit
1076 int offset = ra_->reg2offset(src_first);
1077 if (cbuf) {
1078 MacroAssembler _masm(cbuf);
1079 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1080 #ifndef PRODUCT
1081 } else {
1082 st->print("%s %s, [rsp + #%d]\t# spill",
1083 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1084 Matcher::regName[dst_first],
1085 offset);
1086 #endif
1087 }
1088 } else {
1089 // 32-bit
1090 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1091 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1092 int offset = ra_->reg2offset(src_first);
1093 if (cbuf) {
1094 MacroAssembler _masm(cbuf);
1095 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1096 #ifndef PRODUCT
1097 } else {
1098 st->print("movss %s, [rsp + #%d]\t# spill",
1099 Matcher::regName[dst_first],
1100 offset);
1101 #endif
1102 }
1103 }
1104 return 0;
1105 }
1106 } else if (src_first_rc == rc_int) {
1107 // gpr ->
1108 if (dst_first_rc == rc_stack) {
1109 // gpr -> mem
1110 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1111 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1112 // 64-bit
1113 int offset = ra_->reg2offset(dst_first);
1114 if (cbuf) {
1115 MacroAssembler _masm(cbuf);
1116 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1117 #ifndef PRODUCT
1118 } else {
1119 st->print("movq [rsp + #%d], %s\t# spill",
1120 offset,
1121 Matcher::regName[src_first]);
1122 #endif
1123 }
1124 } else {
1125 // 32-bit
1126 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1127 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1128 int offset = ra_->reg2offset(dst_first);
1129 if (cbuf) {
1130 MacroAssembler _masm(cbuf);
1131 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1132 #ifndef PRODUCT
1133 } else {
1134 st->print("movl [rsp + #%d], %s\t# spill",
1135 offset,
1136 Matcher::regName[src_first]);
1137 #endif
1138 }
1139 }
1140 return 0;
1141 } else if (dst_first_rc == rc_int) {
1142 // gpr -> gpr
1143 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1144 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1145 // 64-bit
1146 if (cbuf) {
1147 MacroAssembler _masm(cbuf);
1148 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1149 as_Register(Matcher::_regEncode[src_first]));
1150 #ifndef PRODUCT
1151 } else {
1152 st->print("movq %s, %s\t# spill",
1153 Matcher::regName[dst_first],
1154 Matcher::regName[src_first]);
1155 #endif
1156 }
1157 return 0;
1158 } else {
1159 // 32-bit
1160 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1161 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1162 if (cbuf) {
1163 MacroAssembler _masm(cbuf);
1164 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1165 as_Register(Matcher::_regEncode[src_first]));
1166 #ifndef PRODUCT
1167 } else {
1168 st->print("movl %s, %s\t# spill",
1169 Matcher::regName[dst_first],
1170 Matcher::regName[src_first]);
1171 #endif
1172 }
1173 return 0;
1174 }
1175 } else if (dst_first_rc == rc_float) {
1176 // gpr -> xmm
1177 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1178 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1179 // 64-bit
1180 if (cbuf) {
1181 MacroAssembler _masm(cbuf);
1182 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1183 #ifndef PRODUCT
1184 } else {
1185 st->print("movdq %s, %s\t# spill",
1186 Matcher::regName[dst_first],
1187 Matcher::regName[src_first]);
1188 #endif
1189 }
1190 } else {
1191 // 32-bit
1192 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1193 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1194 if (cbuf) {
1195 MacroAssembler _masm(cbuf);
1196 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1197 #ifndef PRODUCT
1198 } else {
1199 st->print("movdl %s, %s\t# spill",
1200 Matcher::regName[dst_first],
1201 Matcher::regName[src_first]);
1202 #endif
1203 }
1204 }
1205 return 0;
1206 }
1207 } else if (src_first_rc == rc_float) {
1208 // xmm ->
1209 if (dst_first_rc == rc_stack) {
1210 // xmm -> mem
1211 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1212 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1213 // 64-bit
1214 int offset = ra_->reg2offset(dst_first);
1215 if (cbuf) {
1216 MacroAssembler _masm(cbuf);
1217 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1218 #ifndef PRODUCT
1219 } else {
1220 st->print("movsd [rsp + #%d], %s\t# spill",
1221 offset,
1222 Matcher::regName[src_first]);
1223 #endif
1224 }
1225 } else {
1226 // 32-bit
1227 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1228 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1229 int offset = ra_->reg2offset(dst_first);
1230 if (cbuf) {
1231 MacroAssembler _masm(cbuf);
1232 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1233 #ifndef PRODUCT
1234 } else {
1235 st->print("movss [rsp + #%d], %s\t# spill",
1236 offset,
1237 Matcher::regName[src_first]);
1238 #endif
1239 }
1240 }
1241 return 0;
1242 } else if (dst_first_rc == rc_int) {
1243 // xmm -> gpr
1244 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1245 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1246 // 64-bit
1247 if (cbuf) {
1248 MacroAssembler _masm(cbuf);
1249 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1250 #ifndef PRODUCT
1251 } else {
1252 st->print("movdq %s, %s\t# spill",
1253 Matcher::regName[dst_first],
1254 Matcher::regName[src_first]);
1255 #endif
1256 }
1257 } else {
1258 // 32-bit
1259 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1260 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1261 if (cbuf) {
1262 MacroAssembler _masm(cbuf);
1263 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1264 #ifndef PRODUCT
1265 } else {
1266 st->print("movdl %s, %s\t# spill",
1267 Matcher::regName[dst_first],
1268 Matcher::regName[src_first]);
1269 #endif
1270 }
1271 }
1272 return 0;
1273 } else if (dst_first_rc == rc_float) {
1274 // xmm -> xmm
1275 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1276 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1277 // 64-bit
1278 if (cbuf) {
1279 MacroAssembler _masm(cbuf);
1280 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1281 #ifndef PRODUCT
1282 } else {
1283 st->print("%s %s, %s\t# spill",
1284 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1285 Matcher::regName[dst_first],
1286 Matcher::regName[src_first]);
1287 #endif
1288 }
1289 } else {
1290 // 32-bit
1291 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1292 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1293 if (cbuf) {
1294 MacroAssembler _masm(cbuf);
1295 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1296 #ifndef PRODUCT
1297 } else {
1298 st->print("%s %s, %s\t# spill",
1299 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1300 Matcher::regName[dst_first],
1301 Matcher::regName[src_first]);
1302 #endif
1303 }
1304 }
1305 return 0;
1306 }
1307 }
1309 assert(0," foo ");
1310 Unimplemented();
1311 return 0;
1312 }
1314 #ifndef PRODUCT
1315 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1316 implementation(NULL, ra_, false, st);
1317 }
1318 #endif
1320 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1321 implementation(&cbuf, ra_, false, NULL);
1322 }
1324 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1325 return MachNode::size(ra_);
1326 }
1328 //=============================================================================
1329 #ifndef PRODUCT
1330 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1331 {
1332 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1333 int reg = ra_->get_reg_first(this);
1334 st->print("leaq %s, [rsp + #%d]\t# box lock",
1335 Matcher::regName[reg], offset);
1336 }
1337 #endif
1339 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1340 {
1341 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1342 int reg = ra_->get_encode(this);
1343 if (offset >= 0x80) {
1344 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1345 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1346 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1347 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1348 emit_d32(cbuf, offset);
1349 } else {
1350 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1351 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1352 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1353 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1354 emit_d8(cbuf, offset);
1355 }
1356 }
1358 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1359 {
1360 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1361 return (offset < 0x80) ? 5 : 8; // REX
1362 }
1364 //=============================================================================
1366 // emit call stub, compiled java to interpreter
1367 void emit_java_to_interp(CodeBuffer& cbuf)
1368 {
1369 // Stub is fixed up when the corresponding call is converted from
1370 // calling compiled code to calling interpreted code.
1371 // movq rbx, 0
1372 // jmp -5 # to self
1374 address mark = cbuf.insts_mark(); // get mark within main instrs section
1376 // Note that the code buffer's insts_mark is always relative to insts.
1377 // That's why we must use the macroassembler to generate a stub.
1378 MacroAssembler _masm(&cbuf);
1380 address base =
1381 __ start_a_stub(Compile::MAX_stubs_size);
1382 if (base == NULL) return; // CodeBuffer::expand failed
1383 // static stub relocation stores the instruction address of the call
1384 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64);
1385 // static stub relocation also tags the methodOop in the code-stream.
1386 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time
1387 // This is recognized as unresolved by relocs/nativeinst/ic code
1388 __ jump(RuntimeAddress(__ pc()));
1390 // Update current stubs pointer and restore insts_end.
1391 __ end_a_stub();
1392 }
1394 // size of call stub, compiled java to interpretor
1395 uint size_java_to_interp()
1396 {
1397 return 15; // movq (1+1+8); jmp (1+4)
1398 }
1400 // relocation entries for call stub, compiled java to interpretor
1401 uint reloc_java_to_interp()
1402 {
1403 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1404 }
1406 //=============================================================================
1407 #ifndef PRODUCT
1408 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1409 {
1410 if (UseCompressedOops) {
1411 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1412 if (Universe::narrow_oop_shift() != 0) {
1413 st->print_cr("\tdecode_heap_oop_not_null rscratch1, rscratch1");
1414 }
1415 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1416 } else {
1417 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1418 "# Inline cache check");
1419 }
1420 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1421 st->print_cr("\tnop\t# nops to align entry point");
1422 }
1423 #endif
1425 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1426 {
1427 MacroAssembler masm(&cbuf);
1428 uint insts_size = cbuf.insts_size();
1429 if (UseCompressedOops) {
1430 masm.load_klass(rscratch1, j_rarg0);
1431 masm.cmpptr(rax, rscratch1);
1432 } else {
1433 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1434 }
1436 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1438 /* WARNING these NOPs are critical so that verified entry point is properly
1439 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1440 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1441 if (OptoBreakpoint) {
1442 // Leave space for int3
1443 nops_cnt -= 1;
1444 }
1445 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1446 if (nops_cnt > 0)
1447 masm.nop(nops_cnt);
1448 }
1450 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1451 {
1452 return MachNode::size(ra_); // too many variables; just compute it
1453 // the hard way
1454 }
1457 //=============================================================================
1458 uint size_exception_handler()
1459 {
1460 // NativeCall instruction size is the same as NativeJump.
1461 // Note that this value is also credited (in output.cpp) to
1462 // the size of the code section.
1463 return NativeJump::instruction_size;
1464 }
1466 // Emit exception handler code.
1467 int emit_exception_handler(CodeBuffer& cbuf)
1468 {
1470 // Note that the code buffer's insts_mark is always relative to insts.
1471 // That's why we must use the macroassembler to generate a handler.
1472 MacroAssembler _masm(&cbuf);
1473 address base =
1474 __ start_a_stub(size_exception_handler());
1475 if (base == NULL) return 0; // CodeBuffer::expand failed
1476 int offset = __ offset();
1477 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1478 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1479 __ end_a_stub();
1480 return offset;
1481 }
1483 uint size_deopt_handler()
1484 {
1485 // three 5 byte instructions
1486 return 15;
1487 }
1489 // Emit deopt handler code.
1490 int emit_deopt_handler(CodeBuffer& cbuf)
1491 {
1493 // Note that the code buffer's insts_mark is always relative to insts.
1494 // That's why we must use the macroassembler to generate a handler.
1495 MacroAssembler _masm(&cbuf);
1496 address base =
1497 __ start_a_stub(size_deopt_handler());
1498 if (base == NULL) return 0; // CodeBuffer::expand failed
1499 int offset = __ offset();
1500 address the_pc = (address) __ pc();
1501 Label next;
1502 // push a "the_pc" on the stack without destroying any registers
1503 // as they all may be live.
1505 // push address of "next"
1506 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
1507 __ bind(next);
1508 // adjust it so it matches "the_pc"
1509 __ subptr(Address(rsp, 0), __ offset() - offset);
1510 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1511 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1512 __ end_a_stub();
1513 return offset;
1514 }
1516 int Matcher::regnum_to_fpu_offset(int regnum)
1517 {
1518 return regnum - 32; // The FP registers are in the second chunk
1519 }
1521 // This is UltraSparc specific, true just means we have fast l2f conversion
1522 const bool Matcher::convL2FSupported(void) {
1523 return true;
1524 }
1526 // Is this branch offset short enough that a short branch can be used?
1527 //
1528 // NOTE: If the platform does not provide any short branch variants, then
1529 // this method should return false for offset 0.
1530 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1531 // The passed offset is relative to address of the branch.
1532 // On 86 a branch displacement is calculated relative to address
1533 // of a next instruction.
1534 offset -= br_size;
1536 // the short version of jmpConUCF2 contains multiple branches,
1537 // making the reach slightly less
1538 if (rule == jmpConUCF2_rule)
1539 return (-126 <= offset && offset <= 125);
1540 return (-128 <= offset && offset <= 127);
1541 }
1543 const bool Matcher::isSimpleConstant64(jlong value) {
1544 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1545 //return value == (int) value; // Cf. storeImmL and immL32.
1547 // Probably always true, even if a temp register is required.
1548 return true;
1549 }
1551 // The ecx parameter to rep stosq for the ClearArray node is in words.
1552 const bool Matcher::init_array_count_is_in_bytes = false;
1554 // Threshold size for cleararray.
1555 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1557 // No additional cost for CMOVL.
1558 const int Matcher::long_cmove_cost() { return 0; }
1560 // No CMOVF/CMOVD with SSE2
1561 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1563 // Should the Matcher clone shifts on addressing modes, expecting them
1564 // to be subsumed into complex addressing expressions or compute them
1565 // into registers? True for Intel but false for most RISCs
1566 const bool Matcher::clone_shift_expressions = true;
1568 // Do we need to mask the count passed to shift instructions or does
1569 // the cpu only look at the lower 5/6 bits anyway?
1570 const bool Matcher::need_masked_shift_count = false;
1572 bool Matcher::narrow_oop_use_complex_address() {
1573 assert(UseCompressedOops, "only for compressed oops code");
1574 return (LogMinObjAlignmentInBytes <= 3);
1575 }
1577 // Is it better to copy float constants, or load them directly from
1578 // memory? Intel can load a float constant from a direct address,
1579 // requiring no extra registers. Most RISCs will have to materialize
1580 // an address into a register first, so they would do better to copy
1581 // the constant from stack.
1582 const bool Matcher::rematerialize_float_constants = true; // XXX
1584 // If CPU can load and store mis-aligned doubles directly then no
1585 // fixup is needed. Else we split the double into 2 integer pieces
1586 // and move it piece-by-piece. Only happens when passing doubles into
1587 // C code as the Java calling convention forces doubles to be aligned.
1588 const bool Matcher::misaligned_doubles_ok = true;
1590 // No-op on amd64
1591 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1593 // Advertise here if the CPU requires explicit rounding operations to
1594 // implement the UseStrictFP mode.
1595 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1597 // Are floats conerted to double when stored to stack during deoptimization?
1598 // On x64 it is stored without convertion so we can use normal access.
1599 bool Matcher::float_in_double() { return false; }
1601 // Do ints take an entire long register or just half?
1602 const bool Matcher::int_in_long = true;
1604 // Return whether or not this register is ever used as an argument.
1605 // This function is used on startup to build the trampoline stubs in
1606 // generateOptoStub. Registers not mentioned will be killed by the VM
1607 // call in the trampoline, and arguments in those registers not be
1608 // available to the callee.
1609 bool Matcher::can_be_java_arg(int reg)
1610 {
1611 return
1612 reg == RDI_num || reg == RDI_H_num ||
1613 reg == RSI_num || reg == RSI_H_num ||
1614 reg == RDX_num || reg == RDX_H_num ||
1615 reg == RCX_num || reg == RCX_H_num ||
1616 reg == R8_num || reg == R8_H_num ||
1617 reg == R9_num || reg == R9_H_num ||
1618 reg == R12_num || reg == R12_H_num ||
1619 reg == XMM0_num || reg == XMM0b_num ||
1620 reg == XMM1_num || reg == XMM1b_num ||
1621 reg == XMM2_num || reg == XMM2b_num ||
1622 reg == XMM3_num || reg == XMM3b_num ||
1623 reg == XMM4_num || reg == XMM4b_num ||
1624 reg == XMM5_num || reg == XMM5b_num ||
1625 reg == XMM6_num || reg == XMM6b_num ||
1626 reg == XMM7_num || reg == XMM7b_num;
1627 }
1629 bool Matcher::is_spillable_arg(int reg)
1630 {
1631 return can_be_java_arg(reg);
1632 }
1634 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1635 // In 64 bit mode a code which use multiply when
1636 // devisor is constant is faster than hardware
1637 // DIV instruction (it uses MulHiL).
1638 return false;
1639 }
1641 // Register for DIVI projection of divmodI
1642 RegMask Matcher::divI_proj_mask() {
1643 return INT_RAX_REG_mask();
1644 }
1646 // Register for MODI projection of divmodI
1647 RegMask Matcher::modI_proj_mask() {
1648 return INT_RDX_REG_mask();
1649 }
1651 // Register for DIVL projection of divmodL
1652 RegMask Matcher::divL_proj_mask() {
1653 return LONG_RAX_REG_mask();
1654 }
1656 // Register for MODL projection of divmodL
1657 RegMask Matcher::modL_proj_mask() {
1658 return LONG_RDX_REG_mask();
1659 }
1661 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1662 return PTR_RBP_REG_mask();
1663 }
1665 static Address build_address(int b, int i, int s, int d) {
1666 Register index = as_Register(i);
1667 Address::ScaleFactor scale = (Address::ScaleFactor)s;
1668 if (index == rsp) {
1669 index = noreg;
1670 scale = Address::no_scale;
1671 }
1672 Address addr(as_Register(b), index, scale, d);
1673 return addr;
1674 }
1676 %}
1678 //----------ENCODING BLOCK-----------------------------------------------------
1679 // This block specifies the encoding classes used by the compiler to
1680 // output byte streams. Encoding classes are parameterized macros
1681 // used by Machine Instruction Nodes in order to generate the bit
1682 // encoding of the instruction. Operands specify their base encoding
1683 // interface with the interface keyword. There are currently
1684 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1685 // COND_INTER. REG_INTER causes an operand to generate a function
1686 // which returns its register number when queried. CONST_INTER causes
1687 // an operand to generate a function which returns the value of the
1688 // constant when queried. MEMORY_INTER causes an operand to generate
1689 // four functions which return the Base Register, the Index Register,
1690 // the Scale Value, and the Offset Value of the operand when queried.
1691 // COND_INTER causes an operand to generate six functions which return
1692 // the encoding code (ie - encoding bits for the instruction)
1693 // associated with each basic boolean condition for a conditional
1694 // instruction.
1695 //
1696 // Instructions specify two basic values for encoding. Again, a
1697 // function is available to check if the constant displacement is an
1698 // oop. They use the ins_encode keyword to specify their encoding
1699 // classes (which must be a sequence of enc_class names, and their
1700 // parameters, specified in the encoding block), and they use the
1701 // opcode keyword to specify, in order, their primary, secondary, and
1702 // tertiary opcode. Only the opcode sections which a particular
1703 // instruction needs for encoding need to be specified.
1704 encode %{
1705 // Build emit functions for each basic byte or larger field in the
1706 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1707 // from C++ code in the enc_class source block. Emit functions will
1708 // live in the main source block for now. In future, we can
1709 // generalize this by adding a syntax that specifies the sizes of
1710 // fields in an order, so that the adlc can build the emit functions
1711 // automagically
1713 // Emit primary opcode
1714 enc_class OpcP
1715 %{
1716 emit_opcode(cbuf, $primary);
1717 %}
1719 // Emit secondary opcode
1720 enc_class OpcS
1721 %{
1722 emit_opcode(cbuf, $secondary);
1723 %}
1725 // Emit tertiary opcode
1726 enc_class OpcT
1727 %{
1728 emit_opcode(cbuf, $tertiary);
1729 %}
1731 // Emit opcode directly
1732 enc_class Opcode(immI d8)
1733 %{
1734 emit_opcode(cbuf, $d8$$constant);
1735 %}
1737 // Emit size prefix
1738 enc_class SizePrefix
1739 %{
1740 emit_opcode(cbuf, 0x66);
1741 %}
1743 enc_class reg(rRegI reg)
1744 %{
1745 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1746 %}
1748 enc_class reg_reg(rRegI dst, rRegI src)
1749 %{
1750 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1751 %}
1753 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1754 %{
1755 emit_opcode(cbuf, $opcode$$constant);
1756 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1757 %}
1759 enc_class cdql_enc(no_rax_rdx_RegI div)
1760 %{
1761 // Full implementation of Java idiv and irem; checks for
1762 // special case as described in JVM spec., p.243 & p.271.
1763 //
1764 // normal case special case
1765 //
1766 // input : rax: dividend min_int
1767 // reg: divisor -1
1768 //
1769 // output: rax: quotient (= rax idiv reg) min_int
1770 // rdx: remainder (= rax irem reg) 0
1771 //
1772 // Code sequnce:
1773 //
1774 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1775 // 5: 75 07/08 jne e <normal>
1776 // 7: 33 d2 xor %edx,%edx
1777 // [div >= 8 -> offset + 1]
1778 // [REX_B]
1779 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1780 // c: 74 03/04 je 11 <done>
1781 // 000000000000000e <normal>:
1782 // e: 99 cltd
1783 // [div >= 8 -> offset + 1]
1784 // [REX_B]
1785 // f: f7 f9 idiv $div
1786 // 0000000000000011 <done>:
1788 // cmp $0x80000000,%eax
1789 emit_opcode(cbuf, 0x3d);
1790 emit_d8(cbuf, 0x00);
1791 emit_d8(cbuf, 0x00);
1792 emit_d8(cbuf, 0x00);
1793 emit_d8(cbuf, 0x80);
1795 // jne e <normal>
1796 emit_opcode(cbuf, 0x75);
1797 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1799 // xor %edx,%edx
1800 emit_opcode(cbuf, 0x33);
1801 emit_d8(cbuf, 0xD2);
1803 // cmp $0xffffffffffffffff,%ecx
1804 if ($div$$reg >= 8) {
1805 emit_opcode(cbuf, Assembler::REX_B);
1806 }
1807 emit_opcode(cbuf, 0x83);
1808 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1809 emit_d8(cbuf, 0xFF);
1811 // je 11 <done>
1812 emit_opcode(cbuf, 0x74);
1813 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1815 // <normal>
1816 // cltd
1817 emit_opcode(cbuf, 0x99);
1819 // idivl (note: must be emitted by the user of this rule)
1820 // <done>
1821 %}
1823 enc_class cdqq_enc(no_rax_rdx_RegL div)
1824 %{
1825 // Full implementation of Java ldiv and lrem; checks for
1826 // special case as described in JVM spec., p.243 & p.271.
1827 //
1828 // normal case special case
1829 //
1830 // input : rax: dividend min_long
1831 // reg: divisor -1
1832 //
1833 // output: rax: quotient (= rax idiv reg) min_long
1834 // rdx: remainder (= rax irem reg) 0
1835 //
1836 // Code sequnce:
1837 //
1838 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1839 // 7: 00 00 80
1840 // a: 48 39 d0 cmp %rdx,%rax
1841 // d: 75 08 jne 17 <normal>
1842 // f: 33 d2 xor %edx,%edx
1843 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1844 // 15: 74 05 je 1c <done>
1845 // 0000000000000017 <normal>:
1846 // 17: 48 99 cqto
1847 // 19: 48 f7 f9 idiv $div
1848 // 000000000000001c <done>:
1850 // mov $0x8000000000000000,%rdx
1851 emit_opcode(cbuf, Assembler::REX_W);
1852 emit_opcode(cbuf, 0xBA);
1853 emit_d8(cbuf, 0x00);
1854 emit_d8(cbuf, 0x00);
1855 emit_d8(cbuf, 0x00);
1856 emit_d8(cbuf, 0x00);
1857 emit_d8(cbuf, 0x00);
1858 emit_d8(cbuf, 0x00);
1859 emit_d8(cbuf, 0x00);
1860 emit_d8(cbuf, 0x80);
1862 // cmp %rdx,%rax
1863 emit_opcode(cbuf, Assembler::REX_W);
1864 emit_opcode(cbuf, 0x39);
1865 emit_d8(cbuf, 0xD0);
1867 // jne 17 <normal>
1868 emit_opcode(cbuf, 0x75);
1869 emit_d8(cbuf, 0x08);
1871 // xor %edx,%edx
1872 emit_opcode(cbuf, 0x33);
1873 emit_d8(cbuf, 0xD2);
1875 // cmp $0xffffffffffffffff,$div
1876 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1877 emit_opcode(cbuf, 0x83);
1878 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1879 emit_d8(cbuf, 0xFF);
1881 // je 1e <done>
1882 emit_opcode(cbuf, 0x74);
1883 emit_d8(cbuf, 0x05);
1885 // <normal>
1886 // cqto
1887 emit_opcode(cbuf, Assembler::REX_W);
1888 emit_opcode(cbuf, 0x99);
1890 // idivq (note: must be emitted by the user of this rule)
1891 // <done>
1892 %}
1894 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1895 enc_class OpcSE(immI imm)
1896 %{
1897 // Emit primary opcode and set sign-extend bit
1898 // Check for 8-bit immediate, and set sign extend bit in opcode
1899 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1900 emit_opcode(cbuf, $primary | 0x02);
1901 } else {
1902 // 32-bit immediate
1903 emit_opcode(cbuf, $primary);
1904 }
1905 %}
1907 enc_class OpcSErm(rRegI dst, immI imm)
1908 %{
1909 // OpcSEr/m
1910 int dstenc = $dst$$reg;
1911 if (dstenc >= 8) {
1912 emit_opcode(cbuf, Assembler::REX_B);
1913 dstenc -= 8;
1914 }
1915 // Emit primary opcode and set sign-extend bit
1916 // Check for 8-bit immediate, and set sign extend bit in opcode
1917 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1918 emit_opcode(cbuf, $primary | 0x02);
1919 } else {
1920 // 32-bit immediate
1921 emit_opcode(cbuf, $primary);
1922 }
1923 // Emit r/m byte with secondary opcode, after primary opcode.
1924 emit_rm(cbuf, 0x3, $secondary, dstenc);
1925 %}
1927 enc_class OpcSErm_wide(rRegL dst, immI imm)
1928 %{
1929 // OpcSEr/m
1930 int dstenc = $dst$$reg;
1931 if (dstenc < 8) {
1932 emit_opcode(cbuf, Assembler::REX_W);
1933 } else {
1934 emit_opcode(cbuf, Assembler::REX_WB);
1935 dstenc -= 8;
1936 }
1937 // Emit primary opcode and set sign-extend bit
1938 // Check for 8-bit immediate, and set sign extend bit in opcode
1939 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1940 emit_opcode(cbuf, $primary | 0x02);
1941 } else {
1942 // 32-bit immediate
1943 emit_opcode(cbuf, $primary);
1944 }
1945 // Emit r/m byte with secondary opcode, after primary opcode.
1946 emit_rm(cbuf, 0x3, $secondary, dstenc);
1947 %}
1949 enc_class Con8or32(immI imm)
1950 %{
1951 // Check for 8-bit immediate, and set sign extend bit in opcode
1952 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1953 $$$emit8$imm$$constant;
1954 } else {
1955 // 32-bit immediate
1956 $$$emit32$imm$$constant;
1957 }
1958 %}
1960 enc_class opc2_reg(rRegI dst)
1961 %{
1962 // BSWAP
1963 emit_cc(cbuf, $secondary, $dst$$reg);
1964 %}
1966 enc_class opc3_reg(rRegI dst)
1967 %{
1968 // BSWAP
1969 emit_cc(cbuf, $tertiary, $dst$$reg);
1970 %}
1972 enc_class reg_opc(rRegI div)
1973 %{
1974 // INC, DEC, IDIV, IMOD, JMP indirect, ...
1975 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
1976 %}
1978 enc_class enc_cmov(cmpOp cop)
1979 %{
1980 // CMOV
1981 $$$emit8$primary;
1982 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1983 %}
1985 enc_class enc_PartialSubtypeCheck()
1986 %{
1987 Register Rrdi = as_Register(RDI_enc); // result register
1988 Register Rrax = as_Register(RAX_enc); // super class
1989 Register Rrcx = as_Register(RCX_enc); // killed
1990 Register Rrsi = as_Register(RSI_enc); // sub class
1991 Label miss;
1992 const bool set_cond_codes = true;
1994 MacroAssembler _masm(&cbuf);
1995 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
1996 NULL, &miss,
1997 /*set_cond_codes:*/ true);
1998 if ($primary) {
1999 __ xorptr(Rrdi, Rrdi);
2000 }
2001 __ bind(miss);
2002 %}
2004 enc_class Java_To_Interpreter(method meth)
2005 %{
2006 // CALL Java_To_Interpreter
2007 // This is the instruction starting address for relocation info.
2008 cbuf.set_insts_mark();
2009 $$$emit8$primary;
2010 // CALL directly to the runtime
2011 emit_d32_reloc(cbuf,
2012 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2013 runtime_call_Relocation::spec(),
2014 RELOC_DISP32);
2015 %}
2017 enc_class Java_Static_Call(method meth)
2018 %{
2019 // JAVA STATIC CALL
2020 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2021 // determine who we intended to call.
2022 cbuf.set_insts_mark();
2023 $$$emit8$primary;
2025 if (!_method) {
2026 emit_d32_reloc(cbuf,
2027 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2028 runtime_call_Relocation::spec(),
2029 RELOC_DISP32);
2030 } else if (_optimized_virtual) {
2031 emit_d32_reloc(cbuf,
2032 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2033 opt_virtual_call_Relocation::spec(),
2034 RELOC_DISP32);
2035 } else {
2036 emit_d32_reloc(cbuf,
2037 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2038 static_call_Relocation::spec(),
2039 RELOC_DISP32);
2040 }
2041 if (_method) {
2042 // Emit stub for static call
2043 emit_java_to_interp(cbuf);
2044 }
2045 %}
2047 enc_class Java_Dynamic_Call(method meth)
2048 %{
2049 // JAVA DYNAMIC CALL
2050 // !!!!!
2051 // Generate "movq rax, -1", placeholder instruction to load oop-info
2052 // emit_call_dynamic_prologue( cbuf );
2053 cbuf.set_insts_mark();
2055 // movq rax, -1
2056 emit_opcode(cbuf, Assembler::REX_W);
2057 emit_opcode(cbuf, 0xB8 | RAX_enc);
2058 emit_d64_reloc(cbuf,
2059 (int64_t) Universe::non_oop_word(),
2060 oop_Relocation::spec_for_immediate(), RELOC_IMM64);
2061 address virtual_call_oop_addr = cbuf.insts_mark();
2062 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2063 // who we intended to call.
2064 cbuf.set_insts_mark();
2065 $$$emit8$primary;
2066 emit_d32_reloc(cbuf,
2067 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2068 virtual_call_Relocation::spec(virtual_call_oop_addr),
2069 RELOC_DISP32);
2070 %}
2072 enc_class Java_Compiled_Call(method meth)
2073 %{
2074 // JAVA COMPILED CALL
2075 int disp = in_bytes(methodOopDesc:: from_compiled_offset());
2077 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2078 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2080 // callq *disp(%rax)
2081 cbuf.set_insts_mark();
2082 $$$emit8$primary;
2083 if (disp < 0x80) {
2084 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2085 emit_d8(cbuf, disp); // Displacement
2086 } else {
2087 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2088 emit_d32(cbuf, disp); // Displacement
2089 }
2090 %}
2092 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2093 %{
2094 // SAL, SAR, SHR
2095 int dstenc = $dst$$reg;
2096 if (dstenc >= 8) {
2097 emit_opcode(cbuf, Assembler::REX_B);
2098 dstenc -= 8;
2099 }
2100 $$$emit8$primary;
2101 emit_rm(cbuf, 0x3, $secondary, dstenc);
2102 $$$emit8$shift$$constant;
2103 %}
2105 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2106 %{
2107 // SAL, SAR, SHR
2108 int dstenc = $dst$$reg;
2109 if (dstenc < 8) {
2110 emit_opcode(cbuf, Assembler::REX_W);
2111 } else {
2112 emit_opcode(cbuf, Assembler::REX_WB);
2113 dstenc -= 8;
2114 }
2115 $$$emit8$primary;
2116 emit_rm(cbuf, 0x3, $secondary, dstenc);
2117 $$$emit8$shift$$constant;
2118 %}
2120 enc_class load_immI(rRegI dst, immI src)
2121 %{
2122 int dstenc = $dst$$reg;
2123 if (dstenc >= 8) {
2124 emit_opcode(cbuf, Assembler::REX_B);
2125 dstenc -= 8;
2126 }
2127 emit_opcode(cbuf, 0xB8 | dstenc);
2128 $$$emit32$src$$constant;
2129 %}
2131 enc_class load_immL(rRegL dst, immL src)
2132 %{
2133 int dstenc = $dst$$reg;
2134 if (dstenc < 8) {
2135 emit_opcode(cbuf, Assembler::REX_W);
2136 } else {
2137 emit_opcode(cbuf, Assembler::REX_WB);
2138 dstenc -= 8;
2139 }
2140 emit_opcode(cbuf, 0xB8 | dstenc);
2141 emit_d64(cbuf, $src$$constant);
2142 %}
2144 enc_class load_immUL32(rRegL dst, immUL32 src)
2145 %{
2146 // same as load_immI, but this time we care about zeroes in the high word
2147 int dstenc = $dst$$reg;
2148 if (dstenc >= 8) {
2149 emit_opcode(cbuf, Assembler::REX_B);
2150 dstenc -= 8;
2151 }
2152 emit_opcode(cbuf, 0xB8 | dstenc);
2153 $$$emit32$src$$constant;
2154 %}
2156 enc_class load_immL32(rRegL dst, immL32 src)
2157 %{
2158 int dstenc = $dst$$reg;
2159 if (dstenc < 8) {
2160 emit_opcode(cbuf, Assembler::REX_W);
2161 } else {
2162 emit_opcode(cbuf, Assembler::REX_WB);
2163 dstenc -= 8;
2164 }
2165 emit_opcode(cbuf, 0xC7);
2166 emit_rm(cbuf, 0x03, 0x00, dstenc);
2167 $$$emit32$src$$constant;
2168 %}
2170 enc_class load_immP31(rRegP dst, immP32 src)
2171 %{
2172 // same as load_immI, but this time we care about zeroes in the high word
2173 int dstenc = $dst$$reg;
2174 if (dstenc >= 8) {
2175 emit_opcode(cbuf, Assembler::REX_B);
2176 dstenc -= 8;
2177 }
2178 emit_opcode(cbuf, 0xB8 | dstenc);
2179 $$$emit32$src$$constant;
2180 %}
2182 enc_class load_immP(rRegP dst, immP src)
2183 %{
2184 int dstenc = $dst$$reg;
2185 if (dstenc < 8) {
2186 emit_opcode(cbuf, Assembler::REX_W);
2187 } else {
2188 emit_opcode(cbuf, Assembler::REX_WB);
2189 dstenc -= 8;
2190 }
2191 emit_opcode(cbuf, 0xB8 | dstenc);
2192 // This next line should be generated from ADLC
2193 if ($src->constant_is_oop()) {
2194 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64);
2195 } else {
2196 emit_d64(cbuf, $src$$constant);
2197 }
2198 %}
2200 enc_class Con32(immI src)
2201 %{
2202 // Output immediate
2203 $$$emit32$src$$constant;
2204 %}
2206 enc_class Con64(immL src)
2207 %{
2208 // Output immediate
2209 emit_d64($src$$constant);
2210 %}
2212 enc_class Con32F_as_bits(immF src)
2213 %{
2214 // Output Float immediate bits
2215 jfloat jf = $src$$constant;
2216 jint jf_as_bits = jint_cast(jf);
2217 emit_d32(cbuf, jf_as_bits);
2218 %}
2220 enc_class Con16(immI src)
2221 %{
2222 // Output immediate
2223 $$$emit16$src$$constant;
2224 %}
2226 // How is this different from Con32??? XXX
2227 enc_class Con_d32(immI src)
2228 %{
2229 emit_d32(cbuf,$src$$constant);
2230 %}
2232 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2233 // Output immediate memory reference
2234 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2235 emit_d32(cbuf, 0x00);
2236 %}
2238 enc_class lock_prefix()
2239 %{
2240 if (os::is_MP()) {
2241 emit_opcode(cbuf, 0xF0); // lock
2242 }
2243 %}
2245 enc_class REX_mem(memory mem)
2246 %{
2247 if ($mem$$base >= 8) {
2248 if ($mem$$index < 8) {
2249 emit_opcode(cbuf, Assembler::REX_B);
2250 } else {
2251 emit_opcode(cbuf, Assembler::REX_XB);
2252 }
2253 } else {
2254 if ($mem$$index >= 8) {
2255 emit_opcode(cbuf, Assembler::REX_X);
2256 }
2257 }
2258 %}
2260 enc_class REX_mem_wide(memory mem)
2261 %{
2262 if ($mem$$base >= 8) {
2263 if ($mem$$index < 8) {
2264 emit_opcode(cbuf, Assembler::REX_WB);
2265 } else {
2266 emit_opcode(cbuf, Assembler::REX_WXB);
2267 }
2268 } else {
2269 if ($mem$$index < 8) {
2270 emit_opcode(cbuf, Assembler::REX_W);
2271 } else {
2272 emit_opcode(cbuf, Assembler::REX_WX);
2273 }
2274 }
2275 %}
2277 // for byte regs
2278 enc_class REX_breg(rRegI reg)
2279 %{
2280 if ($reg$$reg >= 4) {
2281 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2282 }
2283 %}
2285 // for byte regs
2286 enc_class REX_reg_breg(rRegI dst, rRegI src)
2287 %{
2288 if ($dst$$reg < 8) {
2289 if ($src$$reg >= 4) {
2290 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2291 }
2292 } else {
2293 if ($src$$reg < 8) {
2294 emit_opcode(cbuf, Assembler::REX_R);
2295 } else {
2296 emit_opcode(cbuf, Assembler::REX_RB);
2297 }
2298 }
2299 %}
2301 // for byte regs
2302 enc_class REX_breg_mem(rRegI reg, memory mem)
2303 %{
2304 if ($reg$$reg < 8) {
2305 if ($mem$$base < 8) {
2306 if ($mem$$index >= 8) {
2307 emit_opcode(cbuf, Assembler::REX_X);
2308 } else if ($reg$$reg >= 4) {
2309 emit_opcode(cbuf, Assembler::REX);
2310 }
2311 } else {
2312 if ($mem$$index < 8) {
2313 emit_opcode(cbuf, Assembler::REX_B);
2314 } else {
2315 emit_opcode(cbuf, Assembler::REX_XB);
2316 }
2317 }
2318 } else {
2319 if ($mem$$base < 8) {
2320 if ($mem$$index < 8) {
2321 emit_opcode(cbuf, Assembler::REX_R);
2322 } else {
2323 emit_opcode(cbuf, Assembler::REX_RX);
2324 }
2325 } else {
2326 if ($mem$$index < 8) {
2327 emit_opcode(cbuf, Assembler::REX_RB);
2328 } else {
2329 emit_opcode(cbuf, Assembler::REX_RXB);
2330 }
2331 }
2332 }
2333 %}
2335 enc_class REX_reg(rRegI reg)
2336 %{
2337 if ($reg$$reg >= 8) {
2338 emit_opcode(cbuf, Assembler::REX_B);
2339 }
2340 %}
2342 enc_class REX_reg_wide(rRegI reg)
2343 %{
2344 if ($reg$$reg < 8) {
2345 emit_opcode(cbuf, Assembler::REX_W);
2346 } else {
2347 emit_opcode(cbuf, Assembler::REX_WB);
2348 }
2349 %}
2351 enc_class REX_reg_reg(rRegI dst, rRegI src)
2352 %{
2353 if ($dst$$reg < 8) {
2354 if ($src$$reg >= 8) {
2355 emit_opcode(cbuf, Assembler::REX_B);
2356 }
2357 } else {
2358 if ($src$$reg < 8) {
2359 emit_opcode(cbuf, Assembler::REX_R);
2360 } else {
2361 emit_opcode(cbuf, Assembler::REX_RB);
2362 }
2363 }
2364 %}
2366 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2367 %{
2368 if ($dst$$reg < 8) {
2369 if ($src$$reg < 8) {
2370 emit_opcode(cbuf, Assembler::REX_W);
2371 } else {
2372 emit_opcode(cbuf, Assembler::REX_WB);
2373 }
2374 } else {
2375 if ($src$$reg < 8) {
2376 emit_opcode(cbuf, Assembler::REX_WR);
2377 } else {
2378 emit_opcode(cbuf, Assembler::REX_WRB);
2379 }
2380 }
2381 %}
2383 enc_class REX_reg_mem(rRegI reg, memory mem)
2384 %{
2385 if ($reg$$reg < 8) {
2386 if ($mem$$base < 8) {
2387 if ($mem$$index >= 8) {
2388 emit_opcode(cbuf, Assembler::REX_X);
2389 }
2390 } else {
2391 if ($mem$$index < 8) {
2392 emit_opcode(cbuf, Assembler::REX_B);
2393 } else {
2394 emit_opcode(cbuf, Assembler::REX_XB);
2395 }
2396 }
2397 } else {
2398 if ($mem$$base < 8) {
2399 if ($mem$$index < 8) {
2400 emit_opcode(cbuf, Assembler::REX_R);
2401 } else {
2402 emit_opcode(cbuf, Assembler::REX_RX);
2403 }
2404 } else {
2405 if ($mem$$index < 8) {
2406 emit_opcode(cbuf, Assembler::REX_RB);
2407 } else {
2408 emit_opcode(cbuf, Assembler::REX_RXB);
2409 }
2410 }
2411 }
2412 %}
2414 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2415 %{
2416 if ($reg$$reg < 8) {
2417 if ($mem$$base < 8) {
2418 if ($mem$$index < 8) {
2419 emit_opcode(cbuf, Assembler::REX_W);
2420 } else {
2421 emit_opcode(cbuf, Assembler::REX_WX);
2422 }
2423 } else {
2424 if ($mem$$index < 8) {
2425 emit_opcode(cbuf, Assembler::REX_WB);
2426 } else {
2427 emit_opcode(cbuf, Assembler::REX_WXB);
2428 }
2429 }
2430 } else {
2431 if ($mem$$base < 8) {
2432 if ($mem$$index < 8) {
2433 emit_opcode(cbuf, Assembler::REX_WR);
2434 } else {
2435 emit_opcode(cbuf, Assembler::REX_WRX);
2436 }
2437 } else {
2438 if ($mem$$index < 8) {
2439 emit_opcode(cbuf, Assembler::REX_WRB);
2440 } else {
2441 emit_opcode(cbuf, Assembler::REX_WRXB);
2442 }
2443 }
2444 }
2445 %}
2447 enc_class reg_mem(rRegI ereg, memory mem)
2448 %{
2449 // High registers handle in encode_RegMem
2450 int reg = $ereg$$reg;
2451 int base = $mem$$base;
2452 int index = $mem$$index;
2453 int scale = $mem$$scale;
2454 int disp = $mem$$disp;
2455 bool disp_is_oop = $mem->disp_is_oop();
2457 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop);
2458 %}
2460 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2461 %{
2462 int rm_byte_opcode = $rm_opcode$$constant;
2464 // High registers handle in encode_RegMem
2465 int base = $mem$$base;
2466 int index = $mem$$index;
2467 int scale = $mem$$scale;
2468 int displace = $mem$$disp;
2470 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when
2471 // working with static
2472 // globals
2473 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2474 disp_is_oop);
2475 %}
2477 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2478 %{
2479 int reg_encoding = $dst$$reg;
2480 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2481 int index = 0x04; // 0x04 indicates no index
2482 int scale = 0x00; // 0x00 indicates no scale
2483 int displace = $src1$$constant; // 0x00 indicates no displacement
2484 bool disp_is_oop = false;
2485 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2486 disp_is_oop);
2487 %}
2489 enc_class neg_reg(rRegI dst)
2490 %{
2491 int dstenc = $dst$$reg;
2492 if (dstenc >= 8) {
2493 emit_opcode(cbuf, Assembler::REX_B);
2494 dstenc -= 8;
2495 }
2496 // NEG $dst
2497 emit_opcode(cbuf, 0xF7);
2498 emit_rm(cbuf, 0x3, 0x03, dstenc);
2499 %}
2501 enc_class neg_reg_wide(rRegI dst)
2502 %{
2503 int dstenc = $dst$$reg;
2504 if (dstenc < 8) {
2505 emit_opcode(cbuf, Assembler::REX_W);
2506 } else {
2507 emit_opcode(cbuf, Assembler::REX_WB);
2508 dstenc -= 8;
2509 }
2510 // NEG $dst
2511 emit_opcode(cbuf, 0xF7);
2512 emit_rm(cbuf, 0x3, 0x03, dstenc);
2513 %}
2515 enc_class setLT_reg(rRegI dst)
2516 %{
2517 int dstenc = $dst$$reg;
2518 if (dstenc >= 8) {
2519 emit_opcode(cbuf, Assembler::REX_B);
2520 dstenc -= 8;
2521 } else if (dstenc >= 4) {
2522 emit_opcode(cbuf, Assembler::REX);
2523 }
2524 // SETLT $dst
2525 emit_opcode(cbuf, 0x0F);
2526 emit_opcode(cbuf, 0x9C);
2527 emit_rm(cbuf, 0x3, 0x0, dstenc);
2528 %}
2530 enc_class setNZ_reg(rRegI dst)
2531 %{
2532 int dstenc = $dst$$reg;
2533 if (dstenc >= 8) {
2534 emit_opcode(cbuf, Assembler::REX_B);
2535 dstenc -= 8;
2536 } else if (dstenc >= 4) {
2537 emit_opcode(cbuf, Assembler::REX);
2538 }
2539 // SETNZ $dst
2540 emit_opcode(cbuf, 0x0F);
2541 emit_opcode(cbuf, 0x95);
2542 emit_rm(cbuf, 0x3, 0x0, dstenc);
2543 %}
2546 // Compare the lonogs and set -1, 0, or 1 into dst
2547 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2548 %{
2549 int src1enc = $src1$$reg;
2550 int src2enc = $src2$$reg;
2551 int dstenc = $dst$$reg;
2553 // cmpq $src1, $src2
2554 if (src1enc < 8) {
2555 if (src2enc < 8) {
2556 emit_opcode(cbuf, Assembler::REX_W);
2557 } else {
2558 emit_opcode(cbuf, Assembler::REX_WB);
2559 }
2560 } else {
2561 if (src2enc < 8) {
2562 emit_opcode(cbuf, Assembler::REX_WR);
2563 } else {
2564 emit_opcode(cbuf, Assembler::REX_WRB);
2565 }
2566 }
2567 emit_opcode(cbuf, 0x3B);
2568 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2570 // movl $dst, -1
2571 if (dstenc >= 8) {
2572 emit_opcode(cbuf, Assembler::REX_B);
2573 }
2574 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2575 emit_d32(cbuf, -1);
2577 // jl,s done
2578 emit_opcode(cbuf, 0x7C);
2579 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2581 // setne $dst
2582 if (dstenc >= 4) {
2583 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2584 }
2585 emit_opcode(cbuf, 0x0F);
2586 emit_opcode(cbuf, 0x95);
2587 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2589 // movzbl $dst, $dst
2590 if (dstenc >= 4) {
2591 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2592 }
2593 emit_opcode(cbuf, 0x0F);
2594 emit_opcode(cbuf, 0xB6);
2595 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2596 %}
2598 enc_class Push_ResultXD(regD dst) %{
2599 MacroAssembler _masm(&cbuf);
2600 __ fstp_d(Address(rsp, 0));
2601 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2602 __ addptr(rsp, 8);
2603 %}
2605 enc_class Push_SrcXD(regD src) %{
2606 MacroAssembler _masm(&cbuf);
2607 __ subptr(rsp, 8);
2608 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2609 __ fld_d(Address(rsp, 0));
2610 %}
2613 // obj: object to lock
2614 // box: box address (header location) -- killed
2615 // tmp: rax -- killed
2616 // scr: rbx -- killed
2617 //
2618 // What follows is a direct transliteration of fast_lock() and fast_unlock()
2619 // from i486.ad. See that file for comments.
2620 // TODO: where possible switch from movq (r, 0) to movl(r,0) and
2621 // use the shorter encoding. (Movl clears the high-order 32-bits).
2624 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
2625 %{
2626 Register objReg = as_Register((int)$obj$$reg);
2627 Register boxReg = as_Register((int)$box$$reg);
2628 Register tmpReg = as_Register($tmp$$reg);
2629 Register scrReg = as_Register($scr$$reg);
2630 MacroAssembler masm(&cbuf);
2632 // Verify uniqueness of register assignments -- necessary but not sufficient
2633 assert (objReg != boxReg && objReg != tmpReg &&
2634 objReg != scrReg && tmpReg != scrReg, "invariant") ;
2636 if (_counters != NULL) {
2637 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
2638 }
2639 if (EmitSync & 1) {
2640 // Without cast to int32_t a movptr will destroy r10 which is typically obj
2641 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
2642 masm.cmpptr(rsp, (int32_t)NULL_WORD) ;
2643 } else
2644 if (EmitSync & 2) {
2645 Label DONE_LABEL;
2646 if (UseBiasedLocking) {
2647 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
2648 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
2649 }
2650 // QQQ was movl...
2651 masm.movptr(tmpReg, 0x1);
2652 masm.orptr(tmpReg, Address(objReg, 0));
2653 masm.movptr(Address(boxReg, 0), tmpReg);
2654 if (os::is_MP()) {
2655 masm.lock();
2656 }
2657 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
2658 masm.jcc(Assembler::equal, DONE_LABEL);
2660 // Recursive locking
2661 masm.subptr(tmpReg, rsp);
2662 masm.andptr(tmpReg, 7 - os::vm_page_size());
2663 masm.movptr(Address(boxReg, 0), tmpReg);
2665 masm.bind(DONE_LABEL);
2666 masm.nop(); // avoid branch to branch
2667 } else {
2668 Label DONE_LABEL, IsInflated, Egress;
2670 masm.movptr(tmpReg, Address(objReg, 0)) ;
2671 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
2672 masm.jcc (Assembler::notZero, IsInflated) ;
2674 // it's stack-locked, biased or neutral
2675 // TODO: optimize markword triage order to reduce the number of
2676 // conditional branches in the most common cases.
2677 // Beware -- there's a subtle invariant that fetch of the markword
2678 // at [FETCH], below, will never observe a biased encoding (*101b).
2679 // If this invariant is not held we'll suffer exclusion (safety) failure.
2681 if (UseBiasedLocking && !UseOptoBiasInlining) {
2682 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
2683 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
2684 }
2686 // was q will it destroy high?
2687 masm.orl (tmpReg, 1) ;
2688 masm.movptr(Address(boxReg, 0), tmpReg) ;
2689 if (os::is_MP()) { masm.lock(); }
2690 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
2691 if (_counters != NULL) {
2692 masm.cond_inc32(Assembler::equal,
2693 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
2694 }
2695 masm.jcc (Assembler::equal, DONE_LABEL);
2697 // Recursive locking
2698 masm.subptr(tmpReg, rsp);
2699 masm.andptr(tmpReg, 7 - os::vm_page_size());
2700 masm.movptr(Address(boxReg, 0), tmpReg);
2701 if (_counters != NULL) {
2702 masm.cond_inc32(Assembler::equal,
2703 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
2704 }
2705 masm.jmp (DONE_LABEL) ;
2707 masm.bind (IsInflated) ;
2708 // It's inflated
2710 // TODO: someday avoid the ST-before-CAS penalty by
2711 // relocating (deferring) the following ST.
2712 // We should also think about trying a CAS without having
2713 // fetched _owner. If the CAS is successful we may
2714 // avoid an RTO->RTS upgrade on the $line.
2715 // Without cast to int32_t a movptr will destroy r10 which is typically obj
2716 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
2718 masm.mov (boxReg, tmpReg) ;
2719 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
2720 masm.testptr(tmpReg, tmpReg) ;
2721 masm.jcc (Assembler::notZero, DONE_LABEL) ;
2723 // It's inflated and appears unlocked
2724 if (os::is_MP()) { masm.lock(); }
2725 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
2726 // Intentional fall-through into DONE_LABEL ...
2728 masm.bind (DONE_LABEL) ;
2729 masm.nop () ; // avoid jmp to jmp
2730 }
2731 %}
2733 // obj: object to unlock
2734 // box: box address (displaced header location), killed
2735 // RBX: killed tmp; cannot be obj nor box
2736 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
2737 %{
2739 Register objReg = as_Register($obj$$reg);
2740 Register boxReg = as_Register($box$$reg);
2741 Register tmpReg = as_Register($tmp$$reg);
2742 MacroAssembler masm(&cbuf);
2744 if (EmitSync & 4) {
2745 masm.cmpptr(rsp, 0) ;
2746 } else
2747 if (EmitSync & 8) {
2748 Label DONE_LABEL;
2749 if (UseBiasedLocking) {
2750 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2751 }
2753 // Check whether the displaced header is 0
2754 //(=> recursive unlock)
2755 masm.movptr(tmpReg, Address(boxReg, 0));
2756 masm.testptr(tmpReg, tmpReg);
2757 masm.jcc(Assembler::zero, DONE_LABEL);
2759 // If not recursive lock, reset the header to displaced header
2760 if (os::is_MP()) {
2761 masm.lock();
2762 }
2763 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2764 masm.bind(DONE_LABEL);
2765 masm.nop(); // avoid branch to branch
2766 } else {
2767 Label DONE_LABEL, Stacked, CheckSucc ;
2769 if (UseBiasedLocking && !UseOptoBiasInlining) {
2770 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2771 }
2773 masm.movptr(tmpReg, Address(objReg, 0)) ;
2774 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ;
2775 masm.jcc (Assembler::zero, DONE_LABEL) ;
2776 masm.testl (tmpReg, 0x02) ;
2777 masm.jcc (Assembler::zero, Stacked) ;
2779 // It's inflated
2780 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
2781 masm.xorptr(boxReg, r15_thread) ;
2782 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
2783 masm.jcc (Assembler::notZero, DONE_LABEL) ;
2784 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
2785 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
2786 masm.jcc (Assembler::notZero, CheckSucc) ;
2787 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
2788 masm.jmp (DONE_LABEL) ;
2790 if ((EmitSync & 65536) == 0) {
2791 Label LSuccess, LGoSlowPath ;
2792 masm.bind (CheckSucc) ;
2793 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
2794 masm.jcc (Assembler::zero, LGoSlowPath) ;
2796 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
2797 // the explicit ST;MEMBAR combination, but masm doesn't currently support
2798 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
2799 // are all faster when the write buffer is populated.
2800 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
2801 if (os::is_MP()) {
2802 masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
2803 }
2804 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
2805 masm.jcc (Assembler::notZero, LSuccess) ;
2807 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX
2808 if (os::is_MP()) { masm.lock(); }
2809 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2810 masm.jcc (Assembler::notEqual, LSuccess) ;
2811 // Intentional fall-through into slow-path
2813 masm.bind (LGoSlowPath) ;
2814 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
2815 masm.jmp (DONE_LABEL) ;
2817 masm.bind (LSuccess) ;
2818 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success
2819 masm.jmp (DONE_LABEL) ;
2820 }
2822 masm.bind (Stacked) ;
2823 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch
2824 if (os::is_MP()) { masm.lock(); }
2825 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2827 if (EmitSync & 65536) {
2828 masm.bind (CheckSucc) ;
2829 }
2830 masm.bind(DONE_LABEL);
2831 if (EmitSync & 32768) {
2832 masm.nop(); // avoid branch to branch
2833 }
2834 }
2835 %}
2838 enc_class enc_rethrow()
2839 %{
2840 cbuf.set_insts_mark();
2841 emit_opcode(cbuf, 0xE9); // jmp entry
2842 emit_d32_reloc(cbuf,
2843 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2844 runtime_call_Relocation::spec(),
2845 RELOC_DISP32);
2846 %}
2848 %}
2852 //----------FRAME--------------------------------------------------------------
2853 // Definition of frame structure and management information.
2854 //
2855 // S T A C K L A Y O U T Allocators stack-slot number
2856 // | (to get allocators register number
2857 // G Owned by | | v add OptoReg::stack0())
2858 // r CALLER | |
2859 // o | +--------+ pad to even-align allocators stack-slot
2860 // w V | pad0 | numbers; owned by CALLER
2861 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2862 // h ^ | in | 5
2863 // | | args | 4 Holes in incoming args owned by SELF
2864 // | | | | 3
2865 // | | +--------+
2866 // V | | old out| Empty on Intel, window on Sparc
2867 // | old |preserve| Must be even aligned.
2868 // | SP-+--------+----> Matcher::_old_SP, even aligned
2869 // | | in | 3 area for Intel ret address
2870 // Owned by |preserve| Empty on Sparc.
2871 // SELF +--------+
2872 // | | pad2 | 2 pad to align old SP
2873 // | +--------+ 1
2874 // | | locks | 0
2875 // | +--------+----> OptoReg::stack0(), even aligned
2876 // | | pad1 | 11 pad to align new SP
2877 // | +--------+
2878 // | | | 10
2879 // | | spills | 9 spills
2880 // V | | 8 (pad0 slot for callee)
2881 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2882 // ^ | out | 7
2883 // | | args | 6 Holes in outgoing args owned by CALLEE
2884 // Owned by +--------+
2885 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2886 // | new |preserve| Must be even-aligned.
2887 // | SP-+--------+----> Matcher::_new_SP, even aligned
2888 // | | |
2889 //
2890 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2891 // known from SELF's arguments and the Java calling convention.
2892 // Region 6-7 is determined per call site.
2893 // Note 2: If the calling convention leaves holes in the incoming argument
2894 // area, those holes are owned by SELF. Holes in the outgoing area
2895 // are owned by the CALLEE. Holes should not be nessecary in the
2896 // incoming area, as the Java calling convention is completely under
2897 // the control of the AD file. Doubles can be sorted and packed to
2898 // avoid holes. Holes in the outgoing arguments may be nessecary for
2899 // varargs C calling conventions.
2900 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2901 // even aligned with pad0 as needed.
2902 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2903 // region 6-11 is even aligned; it may be padded out more so that
2904 // the region from SP to FP meets the minimum stack alignment.
2905 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2906 // alignment. Region 11, pad1, may be dynamically extended so that
2907 // SP meets the minimum alignment.
2909 frame
2910 %{
2911 // What direction does stack grow in (assumed to be same for C & Java)
2912 stack_direction(TOWARDS_LOW);
2914 // These three registers define part of the calling convention
2915 // between compiled code and the interpreter.
2916 inline_cache_reg(RAX); // Inline Cache Register
2917 interpreter_method_oop_reg(RBX); // Method Oop Register when
2918 // calling interpreter
2920 // Optional: name the operand used by cisc-spilling to access
2921 // [stack_pointer + offset]
2922 cisc_spilling_operand_name(indOffset32);
2924 // Number of stack slots consumed by locking an object
2925 sync_stack_slots(2);
2927 // Compiled code's Frame Pointer
2928 frame_pointer(RSP);
2930 // Interpreter stores its frame pointer in a register which is
2931 // stored to the stack by I2CAdaptors.
2932 // I2CAdaptors convert from interpreted java to compiled java.
2933 interpreter_frame_pointer(RBP);
2935 // Stack alignment requirement
2936 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2938 // Number of stack slots between incoming argument block and the start of
2939 // a new frame. The PROLOG must add this many slots to the stack. The
2940 // EPILOG must remove this many slots. amd64 needs two slots for
2941 // return address.
2942 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2944 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2945 // for calls to C. Supports the var-args backing area for register parms.
2946 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2948 // The after-PROLOG location of the return address. Location of
2949 // return address specifies a type (REG or STACK) and a number
2950 // representing the register number (i.e. - use a register name) or
2951 // stack slot.
2952 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2953 // Otherwise, it is above the locks and verification slot and alignment word
2954 return_addr(STACK - 2 +
2955 round_to((Compile::current()->in_preserve_stack_slots() +
2956 Compile::current()->fixed_slots()),
2957 stack_alignment_in_slots()));
2959 // Body of function which returns an integer array locating
2960 // arguments either in registers or in stack slots. Passed an array
2961 // of ideal registers called "sig" and a "length" count. Stack-slot
2962 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2963 // arguments for a CALLEE. Incoming stack arguments are
2964 // automatically biased by the preserve_stack_slots field above.
2966 calling_convention
2967 %{
2968 // No difference between ingoing/outgoing just pass false
2969 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2970 %}
2972 c_calling_convention
2973 %{
2974 // This is obviously always outgoing
2975 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
2976 %}
2978 // Location of compiled Java return values. Same as C for now.
2979 return_value
2980 %{
2981 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2982 "only return normal values");
2984 static const int lo[Op_RegL + 1] = {
2985 0,
2986 0,
2987 RAX_num, // Op_RegN
2988 RAX_num, // Op_RegI
2989 RAX_num, // Op_RegP
2990 XMM0_num, // Op_RegF
2991 XMM0_num, // Op_RegD
2992 RAX_num // Op_RegL
2993 };
2994 static const int hi[Op_RegL + 1] = {
2995 0,
2996 0,
2997 OptoReg::Bad, // Op_RegN
2998 OptoReg::Bad, // Op_RegI
2999 RAX_H_num, // Op_RegP
3000 OptoReg::Bad, // Op_RegF
3001 XMM0b_num, // Op_RegD
3002 RAX_H_num // Op_RegL
3003 };
3004 // Excluded flags and vector registers.
3005 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type");
3006 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
3007 %}
3008 %}
3010 //----------ATTRIBUTES---------------------------------------------------------
3011 //----------Operand Attributes-------------------------------------------------
3012 op_attrib op_cost(0); // Required cost attribute
3014 //----------Instruction Attributes---------------------------------------------
3015 ins_attrib ins_cost(100); // Required cost attribute
3016 ins_attrib ins_size(8); // Required size attribute (in bits)
3017 ins_attrib ins_short_branch(0); // Required flag: is this instruction
3018 // a non-matching short branch variant
3019 // of some long branch?
3020 ins_attrib ins_alignment(1); // Required alignment attribute (must
3021 // be a power of 2) specifies the
3022 // alignment that some part of the
3023 // instruction (not necessarily the
3024 // start) requires. If > 1, a
3025 // compute_padding() function must be
3026 // provided for the instruction
3028 //----------OPERANDS-----------------------------------------------------------
3029 // Operand definitions must precede instruction definitions for correct parsing
3030 // in the ADLC because operands constitute user defined types which are used in
3031 // instruction definitions.
3033 //----------Simple Operands----------------------------------------------------
3034 // Immediate Operands
3035 // Integer Immediate
3036 operand immI()
3037 %{
3038 match(ConI);
3040 op_cost(10);
3041 format %{ %}
3042 interface(CONST_INTER);
3043 %}
3045 // Constant for test vs zero
3046 operand immI0()
3047 %{
3048 predicate(n->get_int() == 0);
3049 match(ConI);
3051 op_cost(0);
3052 format %{ %}
3053 interface(CONST_INTER);
3054 %}
3056 // Constant for increment
3057 operand immI1()
3058 %{
3059 predicate(n->get_int() == 1);
3060 match(ConI);
3062 op_cost(0);
3063 format %{ %}
3064 interface(CONST_INTER);
3065 %}
3067 // Constant for decrement
3068 operand immI_M1()
3069 %{
3070 predicate(n->get_int() == -1);
3071 match(ConI);
3073 op_cost(0);
3074 format %{ %}
3075 interface(CONST_INTER);
3076 %}
3078 // Valid scale values for addressing modes
3079 operand immI2()
3080 %{
3081 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3082 match(ConI);
3084 format %{ %}
3085 interface(CONST_INTER);
3086 %}
3088 operand immI8()
3089 %{
3090 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
3091 match(ConI);
3093 op_cost(5);
3094 format %{ %}
3095 interface(CONST_INTER);
3096 %}
3098 operand immI16()
3099 %{
3100 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3101 match(ConI);
3103 op_cost(10);
3104 format %{ %}
3105 interface(CONST_INTER);
3106 %}
3108 // Constant for long shifts
3109 operand immI_32()
3110 %{
3111 predicate( n->get_int() == 32 );
3112 match(ConI);
3114 op_cost(0);
3115 format %{ %}
3116 interface(CONST_INTER);
3117 %}
3119 // Constant for long shifts
3120 operand immI_64()
3121 %{
3122 predicate( n->get_int() == 64 );
3123 match(ConI);
3125 op_cost(0);
3126 format %{ %}
3127 interface(CONST_INTER);
3128 %}
3130 // Pointer Immediate
3131 operand immP()
3132 %{
3133 match(ConP);
3135 op_cost(10);
3136 format %{ %}
3137 interface(CONST_INTER);
3138 %}
3140 // NULL Pointer Immediate
3141 operand immP0()
3142 %{
3143 predicate(n->get_ptr() == 0);
3144 match(ConP);
3146 op_cost(5);
3147 format %{ %}
3148 interface(CONST_INTER);
3149 %}
3151 // Pointer Immediate
3152 operand immN() %{
3153 match(ConN);
3155 op_cost(10);
3156 format %{ %}
3157 interface(CONST_INTER);
3158 %}
3160 // NULL Pointer Immediate
3161 operand immN0() %{
3162 predicate(n->get_narrowcon() == 0);
3163 match(ConN);
3165 op_cost(5);
3166 format %{ %}
3167 interface(CONST_INTER);
3168 %}
3170 operand immP31()
3171 %{
3172 predicate(!n->as_Type()->type()->isa_oopptr()
3173 && (n->get_ptr() >> 31) == 0);
3174 match(ConP);
3176 op_cost(5);
3177 format %{ %}
3178 interface(CONST_INTER);
3179 %}
3182 // Long Immediate
3183 operand immL()
3184 %{
3185 match(ConL);
3187 op_cost(20);
3188 format %{ %}
3189 interface(CONST_INTER);
3190 %}
3192 // Long Immediate 8-bit
3193 operand immL8()
3194 %{
3195 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3196 match(ConL);
3198 op_cost(5);
3199 format %{ %}
3200 interface(CONST_INTER);
3201 %}
3203 // Long Immediate 32-bit unsigned
3204 operand immUL32()
3205 %{
3206 predicate(n->get_long() == (unsigned int) (n->get_long()));
3207 match(ConL);
3209 op_cost(10);
3210 format %{ %}
3211 interface(CONST_INTER);
3212 %}
3214 // Long Immediate 32-bit signed
3215 operand immL32()
3216 %{
3217 predicate(n->get_long() == (int) (n->get_long()));
3218 match(ConL);
3220 op_cost(15);
3221 format %{ %}
3222 interface(CONST_INTER);
3223 %}
3225 // Long Immediate zero
3226 operand immL0()
3227 %{
3228 predicate(n->get_long() == 0L);
3229 match(ConL);
3231 op_cost(10);
3232 format %{ %}
3233 interface(CONST_INTER);
3234 %}
3236 // Constant for increment
3237 operand immL1()
3238 %{
3239 predicate(n->get_long() == 1);
3240 match(ConL);
3242 format %{ %}
3243 interface(CONST_INTER);
3244 %}
3246 // Constant for decrement
3247 operand immL_M1()
3248 %{
3249 predicate(n->get_long() == -1);
3250 match(ConL);
3252 format %{ %}
3253 interface(CONST_INTER);
3254 %}
3256 // Long Immediate: the value 10
3257 operand immL10()
3258 %{
3259 predicate(n->get_long() == 10);
3260 match(ConL);
3262 format %{ %}
3263 interface(CONST_INTER);
3264 %}
3266 // Long immediate from 0 to 127.
3267 // Used for a shorter form of long mul by 10.
3268 operand immL_127()
3269 %{
3270 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3271 match(ConL);
3273 op_cost(10);
3274 format %{ %}
3275 interface(CONST_INTER);
3276 %}
3278 // Long Immediate: low 32-bit mask
3279 operand immL_32bits()
3280 %{
3281 predicate(n->get_long() == 0xFFFFFFFFL);
3282 match(ConL);
3283 op_cost(20);
3285 format %{ %}
3286 interface(CONST_INTER);
3287 %}
3289 // Float Immediate zero
3290 operand immF0()
3291 %{
3292 predicate(jint_cast(n->getf()) == 0);
3293 match(ConF);
3295 op_cost(5);
3296 format %{ %}
3297 interface(CONST_INTER);
3298 %}
3300 // Float Immediate
3301 operand immF()
3302 %{
3303 match(ConF);
3305 op_cost(15);
3306 format %{ %}
3307 interface(CONST_INTER);
3308 %}
3310 // Double Immediate zero
3311 operand immD0()
3312 %{
3313 predicate(jlong_cast(n->getd()) == 0);
3314 match(ConD);
3316 op_cost(5);
3317 format %{ %}
3318 interface(CONST_INTER);
3319 %}
3321 // Double Immediate
3322 operand immD()
3323 %{
3324 match(ConD);
3326 op_cost(15);
3327 format %{ %}
3328 interface(CONST_INTER);
3329 %}
3331 // Immediates for special shifts (sign extend)
3333 // Constants for increment
3334 operand immI_16()
3335 %{
3336 predicate(n->get_int() == 16);
3337 match(ConI);
3339 format %{ %}
3340 interface(CONST_INTER);
3341 %}
3343 operand immI_24()
3344 %{
3345 predicate(n->get_int() == 24);
3346 match(ConI);
3348 format %{ %}
3349 interface(CONST_INTER);
3350 %}
3352 // Constant for byte-wide masking
3353 operand immI_255()
3354 %{
3355 predicate(n->get_int() == 255);
3356 match(ConI);
3358 format %{ %}
3359 interface(CONST_INTER);
3360 %}
3362 // Constant for short-wide masking
3363 operand immI_65535()
3364 %{
3365 predicate(n->get_int() == 65535);
3366 match(ConI);
3368 format %{ %}
3369 interface(CONST_INTER);
3370 %}
3372 // Constant for byte-wide masking
3373 operand immL_255()
3374 %{
3375 predicate(n->get_long() == 255);
3376 match(ConL);
3378 format %{ %}
3379 interface(CONST_INTER);
3380 %}
3382 // Constant for short-wide masking
3383 operand immL_65535()
3384 %{
3385 predicate(n->get_long() == 65535);
3386 match(ConL);
3388 format %{ %}
3389 interface(CONST_INTER);
3390 %}
3392 // Register Operands
3393 // Integer Register
3394 operand rRegI()
3395 %{
3396 constraint(ALLOC_IN_RC(int_reg));
3397 match(RegI);
3399 match(rax_RegI);
3400 match(rbx_RegI);
3401 match(rcx_RegI);
3402 match(rdx_RegI);
3403 match(rdi_RegI);
3405 format %{ %}
3406 interface(REG_INTER);
3407 %}
3409 // Special Registers
3410 operand rax_RegI()
3411 %{
3412 constraint(ALLOC_IN_RC(int_rax_reg));
3413 match(RegI);
3414 match(rRegI);
3416 format %{ "RAX" %}
3417 interface(REG_INTER);
3418 %}
3420 // Special Registers
3421 operand rbx_RegI()
3422 %{
3423 constraint(ALLOC_IN_RC(int_rbx_reg));
3424 match(RegI);
3425 match(rRegI);
3427 format %{ "RBX" %}
3428 interface(REG_INTER);
3429 %}
3431 operand rcx_RegI()
3432 %{
3433 constraint(ALLOC_IN_RC(int_rcx_reg));
3434 match(RegI);
3435 match(rRegI);
3437 format %{ "RCX" %}
3438 interface(REG_INTER);
3439 %}
3441 operand rdx_RegI()
3442 %{
3443 constraint(ALLOC_IN_RC(int_rdx_reg));
3444 match(RegI);
3445 match(rRegI);
3447 format %{ "RDX" %}
3448 interface(REG_INTER);
3449 %}
3451 operand rdi_RegI()
3452 %{
3453 constraint(ALLOC_IN_RC(int_rdi_reg));
3454 match(RegI);
3455 match(rRegI);
3457 format %{ "RDI" %}
3458 interface(REG_INTER);
3459 %}
3461 operand no_rcx_RegI()
3462 %{
3463 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3464 match(RegI);
3465 match(rax_RegI);
3466 match(rbx_RegI);
3467 match(rdx_RegI);
3468 match(rdi_RegI);
3470 format %{ %}
3471 interface(REG_INTER);
3472 %}
3474 operand no_rax_rdx_RegI()
3475 %{
3476 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3477 match(RegI);
3478 match(rbx_RegI);
3479 match(rcx_RegI);
3480 match(rdi_RegI);
3482 format %{ %}
3483 interface(REG_INTER);
3484 %}
3486 // Pointer Register
3487 operand any_RegP()
3488 %{
3489 constraint(ALLOC_IN_RC(any_reg));
3490 match(RegP);
3491 match(rax_RegP);
3492 match(rbx_RegP);
3493 match(rdi_RegP);
3494 match(rsi_RegP);
3495 match(rbp_RegP);
3496 match(r15_RegP);
3497 match(rRegP);
3499 format %{ %}
3500 interface(REG_INTER);
3501 %}
3503 operand rRegP()
3504 %{
3505 constraint(ALLOC_IN_RC(ptr_reg));
3506 match(RegP);
3507 match(rax_RegP);
3508 match(rbx_RegP);
3509 match(rdi_RegP);
3510 match(rsi_RegP);
3511 match(rbp_RegP);
3512 match(r15_RegP); // See Q&A below about r15_RegP.
3514 format %{ %}
3515 interface(REG_INTER);
3516 %}
3518 operand rRegN() %{
3519 constraint(ALLOC_IN_RC(int_reg));
3520 match(RegN);
3522 format %{ %}
3523 interface(REG_INTER);
3524 %}
3526 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3527 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3528 // It's fine for an instruction input which expects rRegP to match a r15_RegP.
3529 // The output of an instruction is controlled by the allocator, which respects
3530 // register class masks, not match rules. Unless an instruction mentions
3531 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3532 // by the allocator as an input.
3534 operand no_rax_RegP()
3535 %{
3536 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3537 match(RegP);
3538 match(rbx_RegP);
3539 match(rsi_RegP);
3540 match(rdi_RegP);
3542 format %{ %}
3543 interface(REG_INTER);
3544 %}
3546 operand no_rbp_RegP()
3547 %{
3548 constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
3549 match(RegP);
3550 match(rbx_RegP);
3551 match(rsi_RegP);
3552 match(rdi_RegP);
3554 format %{ %}
3555 interface(REG_INTER);
3556 %}
3558 operand no_rax_rbx_RegP()
3559 %{
3560 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3561 match(RegP);
3562 match(rsi_RegP);
3563 match(rdi_RegP);
3565 format %{ %}
3566 interface(REG_INTER);
3567 %}
3569 // Special Registers
3570 // Return a pointer value
3571 operand rax_RegP()
3572 %{
3573 constraint(ALLOC_IN_RC(ptr_rax_reg));
3574 match(RegP);
3575 match(rRegP);
3577 format %{ %}
3578 interface(REG_INTER);
3579 %}
3581 // Special Registers
3582 // Return a compressed pointer value
3583 operand rax_RegN()
3584 %{
3585 constraint(ALLOC_IN_RC(int_rax_reg));
3586 match(RegN);
3587 match(rRegN);
3589 format %{ %}
3590 interface(REG_INTER);
3591 %}
3593 // Used in AtomicAdd
3594 operand rbx_RegP()
3595 %{
3596 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3597 match(RegP);
3598 match(rRegP);
3600 format %{ %}
3601 interface(REG_INTER);
3602 %}
3604 operand rsi_RegP()
3605 %{
3606 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3607 match(RegP);
3608 match(rRegP);
3610 format %{ %}
3611 interface(REG_INTER);
3612 %}
3614 // Used in rep stosq
3615 operand rdi_RegP()
3616 %{
3617 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3618 match(RegP);
3619 match(rRegP);
3621 format %{ %}
3622 interface(REG_INTER);
3623 %}
3625 operand rbp_RegP()
3626 %{
3627 constraint(ALLOC_IN_RC(ptr_rbp_reg));
3628 match(RegP);
3629 match(rRegP);
3631 format %{ %}
3632 interface(REG_INTER);
3633 %}
3635 operand r15_RegP()
3636 %{
3637 constraint(ALLOC_IN_RC(ptr_r15_reg));
3638 match(RegP);
3639 match(rRegP);
3641 format %{ %}
3642 interface(REG_INTER);
3643 %}
3645 operand rRegL()
3646 %{
3647 constraint(ALLOC_IN_RC(long_reg));
3648 match(RegL);
3649 match(rax_RegL);
3650 match(rdx_RegL);
3652 format %{ %}
3653 interface(REG_INTER);
3654 %}
3656 // Special Registers
3657 operand no_rax_rdx_RegL()
3658 %{
3659 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3660 match(RegL);
3661 match(rRegL);
3663 format %{ %}
3664 interface(REG_INTER);
3665 %}
3667 operand no_rax_RegL()
3668 %{
3669 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3670 match(RegL);
3671 match(rRegL);
3672 match(rdx_RegL);
3674 format %{ %}
3675 interface(REG_INTER);
3676 %}
3678 operand no_rcx_RegL()
3679 %{
3680 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3681 match(RegL);
3682 match(rRegL);
3684 format %{ %}
3685 interface(REG_INTER);
3686 %}
3688 operand rax_RegL()
3689 %{
3690 constraint(ALLOC_IN_RC(long_rax_reg));
3691 match(RegL);
3692 match(rRegL);
3694 format %{ "RAX" %}
3695 interface(REG_INTER);
3696 %}
3698 operand rcx_RegL()
3699 %{
3700 constraint(ALLOC_IN_RC(long_rcx_reg));
3701 match(RegL);
3702 match(rRegL);
3704 format %{ %}
3705 interface(REG_INTER);
3706 %}
3708 operand rdx_RegL()
3709 %{
3710 constraint(ALLOC_IN_RC(long_rdx_reg));
3711 match(RegL);
3712 match(rRegL);
3714 format %{ %}
3715 interface(REG_INTER);
3716 %}
3718 // Flags register, used as output of compare instructions
3719 operand rFlagsReg()
3720 %{
3721 constraint(ALLOC_IN_RC(int_flags));
3722 match(RegFlags);
3724 format %{ "RFLAGS" %}
3725 interface(REG_INTER);
3726 %}
3728 // Flags register, used as output of FLOATING POINT compare instructions
3729 operand rFlagsRegU()
3730 %{
3731 constraint(ALLOC_IN_RC(int_flags));
3732 match(RegFlags);
3734 format %{ "RFLAGS_U" %}
3735 interface(REG_INTER);
3736 %}
3738 operand rFlagsRegUCF() %{
3739 constraint(ALLOC_IN_RC(int_flags));
3740 match(RegFlags);
3741 predicate(false);
3743 format %{ "RFLAGS_U_CF" %}
3744 interface(REG_INTER);
3745 %}
3747 // Float register operands
3748 operand regF()
3749 %{
3750 constraint(ALLOC_IN_RC(float_reg));
3751 match(RegF);
3753 format %{ %}
3754 interface(REG_INTER);
3755 %}
3757 // Double register operands
3758 operand regD()
3759 %{
3760 constraint(ALLOC_IN_RC(double_reg));
3761 match(RegD);
3763 format %{ %}
3764 interface(REG_INTER);
3765 %}
3767 //----------Memory Operands----------------------------------------------------
3768 // Direct Memory Operand
3769 // operand direct(immP addr)
3770 // %{
3771 // match(addr);
3773 // format %{ "[$addr]" %}
3774 // interface(MEMORY_INTER) %{
3775 // base(0xFFFFFFFF);
3776 // index(0x4);
3777 // scale(0x0);
3778 // disp($addr);
3779 // %}
3780 // %}
3782 // Indirect Memory Operand
3783 operand indirect(any_RegP reg)
3784 %{
3785 constraint(ALLOC_IN_RC(ptr_reg));
3786 match(reg);
3788 format %{ "[$reg]" %}
3789 interface(MEMORY_INTER) %{
3790 base($reg);
3791 index(0x4);
3792 scale(0x0);
3793 disp(0x0);
3794 %}
3795 %}
3797 // Indirect Memory Plus Short Offset Operand
3798 operand indOffset8(any_RegP reg, immL8 off)
3799 %{
3800 constraint(ALLOC_IN_RC(ptr_reg));
3801 match(AddP reg off);
3803 format %{ "[$reg + $off (8-bit)]" %}
3804 interface(MEMORY_INTER) %{
3805 base($reg);
3806 index(0x4);
3807 scale(0x0);
3808 disp($off);
3809 %}
3810 %}
3812 // Indirect Memory Plus Long Offset Operand
3813 operand indOffset32(any_RegP reg, immL32 off)
3814 %{
3815 constraint(ALLOC_IN_RC(ptr_reg));
3816 match(AddP reg off);
3818 format %{ "[$reg + $off (32-bit)]" %}
3819 interface(MEMORY_INTER) %{
3820 base($reg);
3821 index(0x4);
3822 scale(0x0);
3823 disp($off);
3824 %}
3825 %}
3827 // Indirect Memory Plus Index Register Plus Offset Operand
3828 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3829 %{
3830 constraint(ALLOC_IN_RC(ptr_reg));
3831 match(AddP (AddP reg lreg) off);
3833 op_cost(10);
3834 format %{"[$reg + $off + $lreg]" %}
3835 interface(MEMORY_INTER) %{
3836 base($reg);
3837 index($lreg);
3838 scale(0x0);
3839 disp($off);
3840 %}
3841 %}
3843 // Indirect Memory Plus Index Register Plus Offset Operand
3844 operand indIndex(any_RegP reg, rRegL lreg)
3845 %{
3846 constraint(ALLOC_IN_RC(ptr_reg));
3847 match(AddP reg lreg);
3849 op_cost(10);
3850 format %{"[$reg + $lreg]" %}
3851 interface(MEMORY_INTER) %{
3852 base($reg);
3853 index($lreg);
3854 scale(0x0);
3855 disp(0x0);
3856 %}
3857 %}
3859 // Indirect Memory Times Scale Plus Index Register
3860 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3861 %{
3862 constraint(ALLOC_IN_RC(ptr_reg));
3863 match(AddP reg (LShiftL lreg scale));
3865 op_cost(10);
3866 format %{"[$reg + $lreg << $scale]" %}
3867 interface(MEMORY_INTER) %{
3868 base($reg);
3869 index($lreg);
3870 scale($scale);
3871 disp(0x0);
3872 %}
3873 %}
3875 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3876 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3877 %{
3878 constraint(ALLOC_IN_RC(ptr_reg));
3879 match(AddP (AddP reg (LShiftL lreg scale)) off);
3881 op_cost(10);
3882 format %{"[$reg + $off + $lreg << $scale]" %}
3883 interface(MEMORY_INTER) %{
3884 base($reg);
3885 index($lreg);
3886 scale($scale);
3887 disp($off);
3888 %}
3889 %}
3891 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3892 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3893 %{
3894 constraint(ALLOC_IN_RC(ptr_reg));
3895 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3896 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3898 op_cost(10);
3899 format %{"[$reg + $off + $idx << $scale]" %}
3900 interface(MEMORY_INTER) %{
3901 base($reg);
3902 index($idx);
3903 scale($scale);
3904 disp($off);
3905 %}
3906 %}
3908 // Indirect Narrow Oop Plus Offset Operand
3909 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3910 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3911 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3912 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3913 constraint(ALLOC_IN_RC(ptr_reg));
3914 match(AddP (DecodeN reg) off);
3916 op_cost(10);
3917 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3918 interface(MEMORY_INTER) %{
3919 base(0xc); // R12
3920 index($reg);
3921 scale(0x3);
3922 disp($off);
3923 %}
3924 %}
3926 // Indirect Memory Operand
3927 operand indirectNarrow(rRegN reg)
3928 %{
3929 predicate(Universe::narrow_oop_shift() == 0);
3930 constraint(ALLOC_IN_RC(ptr_reg));
3931 match(DecodeN reg);
3933 format %{ "[$reg]" %}
3934 interface(MEMORY_INTER) %{
3935 base($reg);
3936 index(0x4);
3937 scale(0x0);
3938 disp(0x0);
3939 %}
3940 %}
3942 // Indirect Memory Plus Short Offset Operand
3943 operand indOffset8Narrow(rRegN reg, immL8 off)
3944 %{
3945 predicate(Universe::narrow_oop_shift() == 0);
3946 constraint(ALLOC_IN_RC(ptr_reg));
3947 match(AddP (DecodeN reg) off);
3949 format %{ "[$reg + $off (8-bit)]" %}
3950 interface(MEMORY_INTER) %{
3951 base($reg);
3952 index(0x4);
3953 scale(0x0);
3954 disp($off);
3955 %}
3956 %}
3958 // Indirect Memory Plus Long Offset Operand
3959 operand indOffset32Narrow(rRegN reg, immL32 off)
3960 %{
3961 predicate(Universe::narrow_oop_shift() == 0);
3962 constraint(ALLOC_IN_RC(ptr_reg));
3963 match(AddP (DecodeN reg) off);
3965 format %{ "[$reg + $off (32-bit)]" %}
3966 interface(MEMORY_INTER) %{
3967 base($reg);
3968 index(0x4);
3969 scale(0x0);
3970 disp($off);
3971 %}
3972 %}
3974 // Indirect Memory Plus Index Register Plus Offset Operand
3975 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3976 %{
3977 predicate(Universe::narrow_oop_shift() == 0);
3978 constraint(ALLOC_IN_RC(ptr_reg));
3979 match(AddP (AddP (DecodeN reg) lreg) off);
3981 op_cost(10);
3982 format %{"[$reg + $off + $lreg]" %}
3983 interface(MEMORY_INTER) %{
3984 base($reg);
3985 index($lreg);
3986 scale(0x0);
3987 disp($off);
3988 %}
3989 %}
3991 // Indirect Memory Plus Index Register Plus Offset Operand
3992 operand indIndexNarrow(rRegN reg, rRegL lreg)
3993 %{
3994 predicate(Universe::narrow_oop_shift() == 0);
3995 constraint(ALLOC_IN_RC(ptr_reg));
3996 match(AddP (DecodeN reg) lreg);
3998 op_cost(10);
3999 format %{"[$reg + $lreg]" %}
4000 interface(MEMORY_INTER) %{
4001 base($reg);
4002 index($lreg);
4003 scale(0x0);
4004 disp(0x0);
4005 %}
4006 %}
4008 // Indirect Memory Times Scale Plus Index Register
4009 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
4010 %{
4011 predicate(Universe::narrow_oop_shift() == 0);
4012 constraint(ALLOC_IN_RC(ptr_reg));
4013 match(AddP (DecodeN reg) (LShiftL lreg scale));
4015 op_cost(10);
4016 format %{"[$reg + $lreg << $scale]" %}
4017 interface(MEMORY_INTER) %{
4018 base($reg);
4019 index($lreg);
4020 scale($scale);
4021 disp(0x0);
4022 %}
4023 %}
4025 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4026 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4027 %{
4028 predicate(Universe::narrow_oop_shift() == 0);
4029 constraint(ALLOC_IN_RC(ptr_reg));
4030 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4032 op_cost(10);
4033 format %{"[$reg + $off + $lreg << $scale]" %}
4034 interface(MEMORY_INTER) %{
4035 base($reg);
4036 index($lreg);
4037 scale($scale);
4038 disp($off);
4039 %}
4040 %}
4042 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4043 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4044 %{
4045 constraint(ALLOC_IN_RC(ptr_reg));
4046 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4047 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4049 op_cost(10);
4050 format %{"[$reg + $off + $idx << $scale]" %}
4051 interface(MEMORY_INTER) %{
4052 base($reg);
4053 index($idx);
4054 scale($scale);
4055 disp($off);
4056 %}
4057 %}
4060 //----------Special Memory Operands--------------------------------------------
4061 // Stack Slot Operand - This operand is used for loading and storing temporary
4062 // values on the stack where a match requires a value to
4063 // flow through memory.
4064 operand stackSlotP(sRegP reg)
4065 %{
4066 constraint(ALLOC_IN_RC(stack_slots));
4067 // No match rule because this operand is only generated in matching
4069 format %{ "[$reg]" %}
4070 interface(MEMORY_INTER) %{
4071 base(0x4); // RSP
4072 index(0x4); // No Index
4073 scale(0x0); // No Scale
4074 disp($reg); // Stack Offset
4075 %}
4076 %}
4078 operand stackSlotI(sRegI reg)
4079 %{
4080 constraint(ALLOC_IN_RC(stack_slots));
4081 // No match rule because this operand is only generated in matching
4083 format %{ "[$reg]" %}
4084 interface(MEMORY_INTER) %{
4085 base(0x4); // RSP
4086 index(0x4); // No Index
4087 scale(0x0); // No Scale
4088 disp($reg); // Stack Offset
4089 %}
4090 %}
4092 operand stackSlotF(sRegF reg)
4093 %{
4094 constraint(ALLOC_IN_RC(stack_slots));
4095 // No match rule because this operand is only generated in matching
4097 format %{ "[$reg]" %}
4098 interface(MEMORY_INTER) %{
4099 base(0x4); // RSP
4100 index(0x4); // No Index
4101 scale(0x0); // No Scale
4102 disp($reg); // Stack Offset
4103 %}
4104 %}
4106 operand stackSlotD(sRegD reg)
4107 %{
4108 constraint(ALLOC_IN_RC(stack_slots));
4109 // No match rule because this operand is only generated in matching
4111 format %{ "[$reg]" %}
4112 interface(MEMORY_INTER) %{
4113 base(0x4); // RSP
4114 index(0x4); // No Index
4115 scale(0x0); // No Scale
4116 disp($reg); // Stack Offset
4117 %}
4118 %}
4119 operand stackSlotL(sRegL reg)
4120 %{
4121 constraint(ALLOC_IN_RC(stack_slots));
4122 // No match rule because this operand is only generated in matching
4124 format %{ "[$reg]" %}
4125 interface(MEMORY_INTER) %{
4126 base(0x4); // RSP
4127 index(0x4); // No Index
4128 scale(0x0); // No Scale
4129 disp($reg); // Stack Offset
4130 %}
4131 %}
4133 //----------Conditional Branch Operands----------------------------------------
4134 // Comparison Op - This is the operation of the comparison, and is limited to
4135 // the following set of codes:
4136 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4137 //
4138 // Other attributes of the comparison, such as unsignedness, are specified
4139 // by the comparison instruction that sets a condition code flags register.
4140 // That result is represented by a flags operand whose subtype is appropriate
4141 // to the unsignedness (etc.) of the comparison.
4142 //
4143 // Later, the instruction which matches both the Comparison Op (a Bool) and
4144 // the flags (produced by the Cmp) specifies the coding of the comparison op
4145 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4147 // Comparision Code
4148 operand cmpOp()
4149 %{
4150 match(Bool);
4152 format %{ "" %}
4153 interface(COND_INTER) %{
4154 equal(0x4, "e");
4155 not_equal(0x5, "ne");
4156 less(0xC, "l");
4157 greater_equal(0xD, "ge");
4158 less_equal(0xE, "le");
4159 greater(0xF, "g");
4160 %}
4161 %}
4163 // Comparison Code, unsigned compare. Used by FP also, with
4164 // C2 (unordered) turned into GT or LT already. The other bits
4165 // C0 and C3 are turned into Carry & Zero flags.
4166 operand cmpOpU()
4167 %{
4168 match(Bool);
4170 format %{ "" %}
4171 interface(COND_INTER) %{
4172 equal(0x4, "e");
4173 not_equal(0x5, "ne");
4174 less(0x2, "b");
4175 greater_equal(0x3, "nb");
4176 less_equal(0x6, "be");
4177 greater(0x7, "nbe");
4178 %}
4179 %}
4182 // Floating comparisons that don't require any fixup for the unordered case
4183 operand cmpOpUCF() %{
4184 match(Bool);
4185 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4186 n->as_Bool()->_test._test == BoolTest::ge ||
4187 n->as_Bool()->_test._test == BoolTest::le ||
4188 n->as_Bool()->_test._test == BoolTest::gt);
4189 format %{ "" %}
4190 interface(COND_INTER) %{
4191 equal(0x4, "e");
4192 not_equal(0x5, "ne");
4193 less(0x2, "b");
4194 greater_equal(0x3, "nb");
4195 less_equal(0x6, "be");
4196 greater(0x7, "nbe");
4197 %}
4198 %}
4201 // Floating comparisons that can be fixed up with extra conditional jumps
4202 operand cmpOpUCF2() %{
4203 match(Bool);
4204 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4205 n->as_Bool()->_test._test == BoolTest::eq);
4206 format %{ "" %}
4207 interface(COND_INTER) %{
4208 equal(0x4, "e");
4209 not_equal(0x5, "ne");
4210 less(0x2, "b");
4211 greater_equal(0x3, "nb");
4212 less_equal(0x6, "be");
4213 greater(0x7, "nbe");
4214 %}
4215 %}
4218 //----------OPERAND CLASSES----------------------------------------------------
4219 // Operand Classes are groups of operands that are used as to simplify
4220 // instruction definitions by not requiring the AD writer to specify separate
4221 // instructions for every form of operand when the instruction accepts
4222 // multiple operand types with the same basic encoding and format. The classic
4223 // case of this is memory operands.
4225 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4226 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
4227 indCompressedOopOffset,
4228 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4229 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4230 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow);
4232 //----------PIPELINE-----------------------------------------------------------
4233 // Rules which define the behavior of the target architectures pipeline.
4234 pipeline %{
4236 //----------ATTRIBUTES---------------------------------------------------------
4237 attributes %{
4238 variable_size_instructions; // Fixed size instructions
4239 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4240 instruction_unit_size = 1; // An instruction is 1 bytes long
4241 instruction_fetch_unit_size = 16; // The processor fetches one line
4242 instruction_fetch_units = 1; // of 16 bytes
4244 // List of nop instructions
4245 nops( MachNop );
4246 %}
4248 //----------RESOURCES----------------------------------------------------------
4249 // Resources are the functional units available to the machine
4251 // Generic P2/P3 pipeline
4252 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4253 // 3 instructions decoded per cycle.
4254 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4255 // 3 ALU op, only ALU0 handles mul instructions.
4256 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4257 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4258 BR, FPU,
4259 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4261 //----------PIPELINE DESCRIPTION-----------------------------------------------
4262 // Pipeline Description specifies the stages in the machine's pipeline
4264 // Generic P2/P3 pipeline
4265 pipe_desc(S0, S1, S2, S3, S4, S5);
4267 //----------PIPELINE CLASSES---------------------------------------------------
4268 // Pipeline Classes describe the stages in which input and output are
4269 // referenced by the hardware pipeline.
4271 // Naming convention: ialu or fpu
4272 // Then: _reg
4273 // Then: _reg if there is a 2nd register
4274 // Then: _long if it's a pair of instructions implementing a long
4275 // Then: _fat if it requires the big decoder
4276 // Or: _mem if it requires the big decoder and a memory unit.
4278 // Integer ALU reg operation
4279 pipe_class ialu_reg(rRegI dst)
4280 %{
4281 single_instruction;
4282 dst : S4(write);
4283 dst : S3(read);
4284 DECODE : S0; // any decoder
4285 ALU : S3; // any alu
4286 %}
4288 // Long ALU reg operation
4289 pipe_class ialu_reg_long(rRegL dst)
4290 %{
4291 instruction_count(2);
4292 dst : S4(write);
4293 dst : S3(read);
4294 DECODE : S0(2); // any 2 decoders
4295 ALU : S3(2); // both alus
4296 %}
4298 // Integer ALU reg operation using big decoder
4299 pipe_class ialu_reg_fat(rRegI dst)
4300 %{
4301 single_instruction;
4302 dst : S4(write);
4303 dst : S3(read);
4304 D0 : S0; // big decoder only
4305 ALU : S3; // any alu
4306 %}
4308 // Long ALU reg operation using big decoder
4309 pipe_class ialu_reg_long_fat(rRegL dst)
4310 %{
4311 instruction_count(2);
4312 dst : S4(write);
4313 dst : S3(read);
4314 D0 : S0(2); // big decoder only; twice
4315 ALU : S3(2); // any 2 alus
4316 %}
4318 // Integer ALU reg-reg operation
4319 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4320 %{
4321 single_instruction;
4322 dst : S4(write);
4323 src : S3(read);
4324 DECODE : S0; // any decoder
4325 ALU : S3; // any alu
4326 %}
4328 // Long ALU reg-reg operation
4329 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4330 %{
4331 instruction_count(2);
4332 dst : S4(write);
4333 src : S3(read);
4334 DECODE : S0(2); // any 2 decoders
4335 ALU : S3(2); // both alus
4336 %}
4338 // Integer ALU reg-reg operation
4339 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4340 %{
4341 single_instruction;
4342 dst : S4(write);
4343 src : S3(read);
4344 D0 : S0; // big decoder only
4345 ALU : S3; // any alu
4346 %}
4348 // Long ALU reg-reg operation
4349 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4350 %{
4351 instruction_count(2);
4352 dst : S4(write);
4353 src : S3(read);
4354 D0 : S0(2); // big decoder only; twice
4355 ALU : S3(2); // both alus
4356 %}
4358 // Integer ALU reg-mem operation
4359 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4360 %{
4361 single_instruction;
4362 dst : S5(write);
4363 mem : S3(read);
4364 D0 : S0; // big decoder only
4365 ALU : S4; // any alu
4366 MEM : S3; // any mem
4367 %}
4369 // Integer mem operation (prefetch)
4370 pipe_class ialu_mem(memory mem)
4371 %{
4372 single_instruction;
4373 mem : S3(read);
4374 D0 : S0; // big decoder only
4375 MEM : S3; // any mem
4376 %}
4378 // Integer Store to Memory
4379 pipe_class ialu_mem_reg(memory mem, rRegI src)
4380 %{
4381 single_instruction;
4382 mem : S3(read);
4383 src : S5(read);
4384 D0 : S0; // big decoder only
4385 ALU : S4; // any alu
4386 MEM : S3;
4387 %}
4389 // // Long Store to Memory
4390 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4391 // %{
4392 // instruction_count(2);
4393 // mem : S3(read);
4394 // src : S5(read);
4395 // D0 : S0(2); // big decoder only; twice
4396 // ALU : S4(2); // any 2 alus
4397 // MEM : S3(2); // Both mems
4398 // %}
4400 // Integer Store to Memory
4401 pipe_class ialu_mem_imm(memory mem)
4402 %{
4403 single_instruction;
4404 mem : S3(read);
4405 D0 : S0; // big decoder only
4406 ALU : S4; // any alu
4407 MEM : S3;
4408 %}
4410 // Integer ALU0 reg-reg operation
4411 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4412 %{
4413 single_instruction;
4414 dst : S4(write);
4415 src : S3(read);
4416 D0 : S0; // Big decoder only
4417 ALU0 : S3; // only alu0
4418 %}
4420 // Integer ALU0 reg-mem operation
4421 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4422 %{
4423 single_instruction;
4424 dst : S5(write);
4425 mem : S3(read);
4426 D0 : S0; // big decoder only
4427 ALU0 : S4; // ALU0 only
4428 MEM : S3; // any mem
4429 %}
4431 // Integer ALU reg-reg operation
4432 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4433 %{
4434 single_instruction;
4435 cr : S4(write);
4436 src1 : S3(read);
4437 src2 : S3(read);
4438 DECODE : S0; // any decoder
4439 ALU : S3; // any alu
4440 %}
4442 // Integer ALU reg-imm operation
4443 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4444 %{
4445 single_instruction;
4446 cr : S4(write);
4447 src1 : S3(read);
4448 DECODE : S0; // any decoder
4449 ALU : S3; // any alu
4450 %}
4452 // Integer ALU reg-mem operation
4453 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4454 %{
4455 single_instruction;
4456 cr : S4(write);
4457 src1 : S3(read);
4458 src2 : S3(read);
4459 D0 : S0; // big decoder only
4460 ALU : S4; // any alu
4461 MEM : S3;
4462 %}
4464 // Conditional move reg-reg
4465 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4466 %{
4467 instruction_count(4);
4468 y : S4(read);
4469 q : S3(read);
4470 p : S3(read);
4471 DECODE : S0(4); // any decoder
4472 %}
4474 // Conditional move reg-reg
4475 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4476 %{
4477 single_instruction;
4478 dst : S4(write);
4479 src : S3(read);
4480 cr : S3(read);
4481 DECODE : S0; // any decoder
4482 %}
4484 // Conditional move reg-mem
4485 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4486 %{
4487 single_instruction;
4488 dst : S4(write);
4489 src : S3(read);
4490 cr : S3(read);
4491 DECODE : S0; // any decoder
4492 MEM : S3;
4493 %}
4495 // Conditional move reg-reg long
4496 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4497 %{
4498 single_instruction;
4499 dst : S4(write);
4500 src : S3(read);
4501 cr : S3(read);
4502 DECODE : S0(2); // any 2 decoders
4503 %}
4505 // XXX
4506 // // Conditional move double reg-reg
4507 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4508 // %{
4509 // single_instruction;
4510 // dst : S4(write);
4511 // src : S3(read);
4512 // cr : S3(read);
4513 // DECODE : S0; // any decoder
4514 // %}
4516 // Float reg-reg operation
4517 pipe_class fpu_reg(regD dst)
4518 %{
4519 instruction_count(2);
4520 dst : S3(read);
4521 DECODE : S0(2); // any 2 decoders
4522 FPU : S3;
4523 %}
4525 // Float reg-reg operation
4526 pipe_class fpu_reg_reg(regD dst, regD src)
4527 %{
4528 instruction_count(2);
4529 dst : S4(write);
4530 src : S3(read);
4531 DECODE : S0(2); // any 2 decoders
4532 FPU : S3;
4533 %}
4535 // Float reg-reg operation
4536 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4537 %{
4538 instruction_count(3);
4539 dst : S4(write);
4540 src1 : S3(read);
4541 src2 : S3(read);
4542 DECODE : S0(3); // any 3 decoders
4543 FPU : S3(2);
4544 %}
4546 // Float reg-reg operation
4547 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4548 %{
4549 instruction_count(4);
4550 dst : S4(write);
4551 src1 : S3(read);
4552 src2 : S3(read);
4553 src3 : S3(read);
4554 DECODE : S0(4); // any 3 decoders
4555 FPU : S3(2);
4556 %}
4558 // Float reg-reg operation
4559 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4560 %{
4561 instruction_count(4);
4562 dst : S4(write);
4563 src1 : S3(read);
4564 src2 : S3(read);
4565 src3 : S3(read);
4566 DECODE : S1(3); // any 3 decoders
4567 D0 : S0; // Big decoder only
4568 FPU : S3(2);
4569 MEM : S3;
4570 %}
4572 // Float reg-mem operation
4573 pipe_class fpu_reg_mem(regD dst, memory mem)
4574 %{
4575 instruction_count(2);
4576 dst : S5(write);
4577 mem : S3(read);
4578 D0 : S0; // big decoder only
4579 DECODE : S1; // any decoder for FPU POP
4580 FPU : S4;
4581 MEM : S3; // any mem
4582 %}
4584 // Float reg-mem operation
4585 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4586 %{
4587 instruction_count(3);
4588 dst : S5(write);
4589 src1 : S3(read);
4590 mem : S3(read);
4591 D0 : S0; // big decoder only
4592 DECODE : S1(2); // any decoder for FPU POP
4593 FPU : S4;
4594 MEM : S3; // any mem
4595 %}
4597 // Float mem-reg operation
4598 pipe_class fpu_mem_reg(memory mem, regD src)
4599 %{
4600 instruction_count(2);
4601 src : S5(read);
4602 mem : S3(read);
4603 DECODE : S0; // any decoder for FPU PUSH
4604 D0 : S1; // big decoder only
4605 FPU : S4;
4606 MEM : S3; // any mem
4607 %}
4609 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4610 %{
4611 instruction_count(3);
4612 src1 : S3(read);
4613 src2 : S3(read);
4614 mem : S3(read);
4615 DECODE : S0(2); // any decoder for FPU PUSH
4616 D0 : S1; // big decoder only
4617 FPU : S4;
4618 MEM : S3; // any mem
4619 %}
4621 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4622 %{
4623 instruction_count(3);
4624 src1 : S3(read);
4625 src2 : S3(read);
4626 mem : S4(read);
4627 DECODE : S0; // any decoder for FPU PUSH
4628 D0 : S0(2); // big decoder only
4629 FPU : S4;
4630 MEM : S3(2); // any mem
4631 %}
4633 pipe_class fpu_mem_mem(memory dst, memory src1)
4634 %{
4635 instruction_count(2);
4636 src1 : S3(read);
4637 dst : S4(read);
4638 D0 : S0(2); // big decoder only
4639 MEM : S3(2); // any mem
4640 %}
4642 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4643 %{
4644 instruction_count(3);
4645 src1 : S3(read);
4646 src2 : S3(read);
4647 dst : S4(read);
4648 D0 : S0(3); // big decoder only
4649 FPU : S4;
4650 MEM : S3(3); // any mem
4651 %}
4653 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4654 %{
4655 instruction_count(3);
4656 src1 : S4(read);
4657 mem : S4(read);
4658 DECODE : S0; // any decoder for FPU PUSH
4659 D0 : S0(2); // big decoder only
4660 FPU : S4;
4661 MEM : S3(2); // any mem
4662 %}
4664 // Float load constant
4665 pipe_class fpu_reg_con(regD dst)
4666 %{
4667 instruction_count(2);
4668 dst : S5(write);
4669 D0 : S0; // big decoder only for the load
4670 DECODE : S1; // any decoder for FPU POP
4671 FPU : S4;
4672 MEM : S3; // any mem
4673 %}
4675 // Float load constant
4676 pipe_class fpu_reg_reg_con(regD dst, regD src)
4677 %{
4678 instruction_count(3);
4679 dst : S5(write);
4680 src : S3(read);
4681 D0 : S0; // big decoder only for the load
4682 DECODE : S1(2); // any decoder for FPU POP
4683 FPU : S4;
4684 MEM : S3; // any mem
4685 %}
4687 // UnConditional branch
4688 pipe_class pipe_jmp(label labl)
4689 %{
4690 single_instruction;
4691 BR : S3;
4692 %}
4694 // Conditional branch
4695 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4696 %{
4697 single_instruction;
4698 cr : S1(read);
4699 BR : S3;
4700 %}
4702 // Allocation idiom
4703 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4704 %{
4705 instruction_count(1); force_serialization;
4706 fixed_latency(6);
4707 heap_ptr : S3(read);
4708 DECODE : S0(3);
4709 D0 : S2;
4710 MEM : S3;
4711 ALU : S3(2);
4712 dst : S5(write);
4713 BR : S5;
4714 %}
4716 // Generic big/slow expanded idiom
4717 pipe_class pipe_slow()
4718 %{
4719 instruction_count(10); multiple_bundles; force_serialization;
4720 fixed_latency(100);
4721 D0 : S0(2);
4722 MEM : S3(2);
4723 %}
4725 // The real do-nothing guy
4726 pipe_class empty()
4727 %{
4728 instruction_count(0);
4729 %}
4731 // Define the class for the Nop node
4732 define
4733 %{
4734 MachNop = empty;
4735 %}
4737 %}
4739 //----------INSTRUCTIONS-------------------------------------------------------
4740 //
4741 // match -- States which machine-independent subtree may be replaced
4742 // by this instruction.
4743 // ins_cost -- The estimated cost of this instruction is used by instruction
4744 // selection to identify a minimum cost tree of machine
4745 // instructions that matches a tree of machine-independent
4746 // instructions.
4747 // format -- A string providing the disassembly for this instruction.
4748 // The value of an instruction's operand may be inserted
4749 // by referring to it with a '$' prefix.
4750 // opcode -- Three instruction opcodes may be provided. These are referred
4751 // to within an encode class as $primary, $secondary, and $tertiary
4752 // rrspectively. The primary opcode is commonly used to
4753 // indicate the type of machine instruction, while secondary
4754 // and tertiary are often used for prefix options or addressing
4755 // modes.
4756 // ins_encode -- A list of encode classes with parameters. The encode class
4757 // name must have been defined in an 'enc_class' specification
4758 // in the encode section of the architecture description.
4761 //----------Load/Store/Move Instructions---------------------------------------
4762 //----------Load Instructions--------------------------------------------------
4764 // Load Byte (8 bit signed)
4765 instruct loadB(rRegI dst, memory mem)
4766 %{
4767 match(Set dst (LoadB mem));
4769 ins_cost(125);
4770 format %{ "movsbl $dst, $mem\t# byte" %}
4772 ins_encode %{
4773 __ movsbl($dst$$Register, $mem$$Address);
4774 %}
4776 ins_pipe(ialu_reg_mem);
4777 %}
4779 // Load Byte (8 bit signed) into Long Register
4780 instruct loadB2L(rRegL dst, memory mem)
4781 %{
4782 match(Set dst (ConvI2L (LoadB mem)));
4784 ins_cost(125);
4785 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4787 ins_encode %{
4788 __ movsbq($dst$$Register, $mem$$Address);
4789 %}
4791 ins_pipe(ialu_reg_mem);
4792 %}
4794 // Load Unsigned Byte (8 bit UNsigned)
4795 instruct loadUB(rRegI dst, memory mem)
4796 %{
4797 match(Set dst (LoadUB mem));
4799 ins_cost(125);
4800 format %{ "movzbl $dst, $mem\t# ubyte" %}
4802 ins_encode %{
4803 __ movzbl($dst$$Register, $mem$$Address);
4804 %}
4806 ins_pipe(ialu_reg_mem);
4807 %}
4809 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4810 instruct loadUB2L(rRegL dst, memory mem)
4811 %{
4812 match(Set dst (ConvI2L (LoadUB mem)));
4814 ins_cost(125);
4815 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4817 ins_encode %{
4818 __ movzbq($dst$$Register, $mem$$Address);
4819 %}
4821 ins_pipe(ialu_reg_mem);
4822 %}
4824 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register
4825 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{
4826 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4827 effect(KILL cr);
4829 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t"
4830 "andl $dst, $mask" %}
4831 ins_encode %{
4832 Register Rdst = $dst$$Register;
4833 __ movzbq(Rdst, $mem$$Address);
4834 __ andl(Rdst, $mask$$constant);
4835 %}
4836 ins_pipe(ialu_reg_mem);
4837 %}
4839 // Load Short (16 bit signed)
4840 instruct loadS(rRegI dst, memory mem)
4841 %{
4842 match(Set dst (LoadS mem));
4844 ins_cost(125);
4845 format %{ "movswl $dst, $mem\t# short" %}
4847 ins_encode %{
4848 __ movswl($dst$$Register, $mem$$Address);
4849 %}
4851 ins_pipe(ialu_reg_mem);
4852 %}
4854 // Load Short (16 bit signed) to Byte (8 bit signed)
4855 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4856 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4858 ins_cost(125);
4859 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4860 ins_encode %{
4861 __ movsbl($dst$$Register, $mem$$Address);
4862 %}
4863 ins_pipe(ialu_reg_mem);
4864 %}
4866 // Load Short (16 bit signed) into Long Register
4867 instruct loadS2L(rRegL dst, memory mem)
4868 %{
4869 match(Set dst (ConvI2L (LoadS mem)));
4871 ins_cost(125);
4872 format %{ "movswq $dst, $mem\t# short -> long" %}
4874 ins_encode %{
4875 __ movswq($dst$$Register, $mem$$Address);
4876 %}
4878 ins_pipe(ialu_reg_mem);
4879 %}
4881 // Load Unsigned Short/Char (16 bit UNsigned)
4882 instruct loadUS(rRegI dst, memory mem)
4883 %{
4884 match(Set dst (LoadUS mem));
4886 ins_cost(125);
4887 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4889 ins_encode %{
4890 __ movzwl($dst$$Register, $mem$$Address);
4891 %}
4893 ins_pipe(ialu_reg_mem);
4894 %}
4896 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4897 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4898 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4900 ins_cost(125);
4901 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4902 ins_encode %{
4903 __ movsbl($dst$$Register, $mem$$Address);
4904 %}
4905 ins_pipe(ialu_reg_mem);
4906 %}
4908 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4909 instruct loadUS2L(rRegL dst, memory mem)
4910 %{
4911 match(Set dst (ConvI2L (LoadUS mem)));
4913 ins_cost(125);
4914 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4916 ins_encode %{
4917 __ movzwq($dst$$Register, $mem$$Address);
4918 %}
4920 ins_pipe(ialu_reg_mem);
4921 %}
4923 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4924 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4925 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4927 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4928 ins_encode %{
4929 __ movzbq($dst$$Register, $mem$$Address);
4930 %}
4931 ins_pipe(ialu_reg_mem);
4932 %}
4934 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register
4935 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{
4936 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4937 effect(KILL cr);
4939 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t"
4940 "andl $dst, $mask" %}
4941 ins_encode %{
4942 Register Rdst = $dst$$Register;
4943 __ movzwq(Rdst, $mem$$Address);
4944 __ andl(Rdst, $mask$$constant);
4945 %}
4946 ins_pipe(ialu_reg_mem);
4947 %}
4949 // Load Integer
4950 instruct loadI(rRegI dst, memory mem)
4951 %{
4952 match(Set dst (LoadI mem));
4954 ins_cost(125);
4955 format %{ "movl $dst, $mem\t# int" %}
4957 ins_encode %{
4958 __ movl($dst$$Register, $mem$$Address);
4959 %}
4961 ins_pipe(ialu_reg_mem);
4962 %}
4964 // Load Integer (32 bit signed) to Byte (8 bit signed)
4965 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4966 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4968 ins_cost(125);
4969 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4970 ins_encode %{
4971 __ movsbl($dst$$Register, $mem$$Address);
4972 %}
4973 ins_pipe(ialu_reg_mem);
4974 %}
4976 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4977 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4978 match(Set dst (AndI (LoadI mem) mask));
4980 ins_cost(125);
4981 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4982 ins_encode %{
4983 __ movzbl($dst$$Register, $mem$$Address);
4984 %}
4985 ins_pipe(ialu_reg_mem);
4986 %}
4988 // Load Integer (32 bit signed) to Short (16 bit signed)
4989 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4990 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4992 ins_cost(125);
4993 format %{ "movswl $dst, $mem\t# int -> short" %}
4994 ins_encode %{
4995 __ movswl($dst$$Register, $mem$$Address);
4996 %}
4997 ins_pipe(ialu_reg_mem);
4998 %}
5000 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5001 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5002 match(Set dst (AndI (LoadI mem) mask));
5004 ins_cost(125);
5005 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
5006 ins_encode %{
5007 __ movzwl($dst$$Register, $mem$$Address);
5008 %}
5009 ins_pipe(ialu_reg_mem);
5010 %}
5012 // Load Integer into Long Register
5013 instruct loadI2L(rRegL dst, memory mem)
5014 %{
5015 match(Set dst (ConvI2L (LoadI mem)));
5017 ins_cost(125);
5018 format %{ "movslq $dst, $mem\t# int -> long" %}
5020 ins_encode %{
5021 __ movslq($dst$$Register, $mem$$Address);
5022 %}
5024 ins_pipe(ialu_reg_mem);
5025 %}
5027 // Load Integer with mask 0xFF into Long Register
5028 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5029 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5031 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
5032 ins_encode %{
5033 __ movzbq($dst$$Register, $mem$$Address);
5034 %}
5035 ins_pipe(ialu_reg_mem);
5036 %}
5038 // Load Integer with mask 0xFFFF into Long Register
5039 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5040 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5042 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5043 ins_encode %{
5044 __ movzwq($dst$$Register, $mem$$Address);
5045 %}
5046 ins_pipe(ialu_reg_mem);
5047 %}
5049 // Load Integer with a 32-bit mask into Long Register
5050 instruct loadI2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5051 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5052 effect(KILL cr);
5054 format %{ "movl $dst, $mem\t# int & 32-bit mask -> long\n\t"
5055 "andl $dst, $mask" %}
5056 ins_encode %{
5057 Register Rdst = $dst$$Register;
5058 __ movl(Rdst, $mem$$Address);
5059 __ andl(Rdst, $mask$$constant);
5060 %}
5061 ins_pipe(ialu_reg_mem);
5062 %}
5064 // Load Unsigned Integer into Long Register
5065 instruct loadUI2L(rRegL dst, memory mem)
5066 %{
5067 match(Set dst (LoadUI2L mem));
5069 ins_cost(125);
5070 format %{ "movl $dst, $mem\t# uint -> long" %}
5072 ins_encode %{
5073 __ movl($dst$$Register, $mem$$Address);
5074 %}
5076 ins_pipe(ialu_reg_mem);
5077 %}
5079 // Load Long
5080 instruct loadL(rRegL dst, memory mem)
5081 %{
5082 match(Set dst (LoadL mem));
5084 ins_cost(125);
5085 format %{ "movq $dst, $mem\t# long" %}
5087 ins_encode %{
5088 __ movq($dst$$Register, $mem$$Address);
5089 %}
5091 ins_pipe(ialu_reg_mem); // XXX
5092 %}
5094 // Load Range
5095 instruct loadRange(rRegI dst, memory mem)
5096 %{
5097 match(Set dst (LoadRange mem));
5099 ins_cost(125); // XXX
5100 format %{ "movl $dst, $mem\t# range" %}
5101 opcode(0x8B);
5102 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5103 ins_pipe(ialu_reg_mem);
5104 %}
5106 // Load Pointer
5107 instruct loadP(rRegP dst, memory mem)
5108 %{
5109 match(Set dst (LoadP mem));
5111 ins_cost(125); // XXX
5112 format %{ "movq $dst, $mem\t# ptr" %}
5113 opcode(0x8B);
5114 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5115 ins_pipe(ialu_reg_mem); // XXX
5116 %}
5118 // Load Compressed Pointer
5119 instruct loadN(rRegN dst, memory mem)
5120 %{
5121 match(Set dst (LoadN mem));
5123 ins_cost(125); // XXX
5124 format %{ "movl $dst, $mem\t# compressed ptr" %}
5125 ins_encode %{
5126 __ movl($dst$$Register, $mem$$Address);
5127 %}
5128 ins_pipe(ialu_reg_mem); // XXX
5129 %}
5132 // Load Klass Pointer
5133 instruct loadKlass(rRegP dst, memory mem)
5134 %{
5135 match(Set dst (LoadKlass mem));
5137 ins_cost(125); // XXX
5138 format %{ "movq $dst, $mem\t# class" %}
5139 opcode(0x8B);
5140 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5141 ins_pipe(ialu_reg_mem); // XXX
5142 %}
5144 // Load narrow Klass Pointer
5145 instruct loadNKlass(rRegN dst, memory mem)
5146 %{
5147 match(Set dst (LoadNKlass mem));
5149 ins_cost(125); // XXX
5150 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5151 ins_encode %{
5152 __ movl($dst$$Register, $mem$$Address);
5153 %}
5154 ins_pipe(ialu_reg_mem); // XXX
5155 %}
5157 // Load Float
5158 instruct loadF(regF dst, memory mem)
5159 %{
5160 match(Set dst (LoadF mem));
5162 ins_cost(145); // XXX
5163 format %{ "movss $dst, $mem\t# float" %}
5164 ins_encode %{
5165 __ movflt($dst$$XMMRegister, $mem$$Address);
5166 %}
5167 ins_pipe(pipe_slow); // XXX
5168 %}
5170 // Load Double
5171 instruct loadD_partial(regD dst, memory mem)
5172 %{
5173 predicate(!UseXmmLoadAndClearUpper);
5174 match(Set dst (LoadD mem));
5176 ins_cost(145); // XXX
5177 format %{ "movlpd $dst, $mem\t# double" %}
5178 ins_encode %{
5179 __ movdbl($dst$$XMMRegister, $mem$$Address);
5180 %}
5181 ins_pipe(pipe_slow); // XXX
5182 %}
5184 instruct loadD(regD dst, memory mem)
5185 %{
5186 predicate(UseXmmLoadAndClearUpper);
5187 match(Set dst (LoadD mem));
5189 ins_cost(145); // XXX
5190 format %{ "movsd $dst, $mem\t# double" %}
5191 ins_encode %{
5192 __ movdbl($dst$$XMMRegister, $mem$$Address);
5193 %}
5194 ins_pipe(pipe_slow); // XXX
5195 %}
5197 // Load Effective Address
5198 instruct leaP8(rRegP dst, indOffset8 mem)
5199 %{
5200 match(Set dst mem);
5202 ins_cost(110); // XXX
5203 format %{ "leaq $dst, $mem\t# ptr 8" %}
5204 opcode(0x8D);
5205 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5206 ins_pipe(ialu_reg_reg_fat);
5207 %}
5209 instruct leaP32(rRegP dst, indOffset32 mem)
5210 %{
5211 match(Set dst mem);
5213 ins_cost(110);
5214 format %{ "leaq $dst, $mem\t# ptr 32" %}
5215 opcode(0x8D);
5216 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5217 ins_pipe(ialu_reg_reg_fat);
5218 %}
5220 // instruct leaPIdx(rRegP dst, indIndex mem)
5221 // %{
5222 // match(Set dst mem);
5224 // ins_cost(110);
5225 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5226 // opcode(0x8D);
5227 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5228 // ins_pipe(ialu_reg_reg_fat);
5229 // %}
5231 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5232 %{
5233 match(Set dst mem);
5235 ins_cost(110);
5236 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5237 opcode(0x8D);
5238 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5239 ins_pipe(ialu_reg_reg_fat);
5240 %}
5242 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5243 %{
5244 match(Set dst mem);
5246 ins_cost(110);
5247 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5248 opcode(0x8D);
5249 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5250 ins_pipe(ialu_reg_reg_fat);
5251 %}
5253 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5254 %{
5255 match(Set dst mem);
5257 ins_cost(110);
5258 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5259 opcode(0x8D);
5260 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5261 ins_pipe(ialu_reg_reg_fat);
5262 %}
5264 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5265 %{
5266 match(Set dst mem);
5268 ins_cost(110);
5269 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5270 opcode(0x8D);
5271 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5272 ins_pipe(ialu_reg_reg_fat);
5273 %}
5275 // Load Effective Address which uses Narrow (32-bits) oop
5276 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5277 %{
5278 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5279 match(Set dst mem);
5281 ins_cost(110);
5282 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5283 opcode(0x8D);
5284 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5285 ins_pipe(ialu_reg_reg_fat);
5286 %}
5288 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5289 %{
5290 predicate(Universe::narrow_oop_shift() == 0);
5291 match(Set dst mem);
5293 ins_cost(110); // XXX
5294 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5295 opcode(0x8D);
5296 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5297 ins_pipe(ialu_reg_reg_fat);
5298 %}
5300 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5301 %{
5302 predicate(Universe::narrow_oop_shift() == 0);
5303 match(Set dst mem);
5305 ins_cost(110);
5306 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5307 opcode(0x8D);
5308 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5309 ins_pipe(ialu_reg_reg_fat);
5310 %}
5312 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5313 %{
5314 predicate(Universe::narrow_oop_shift() == 0);
5315 match(Set dst mem);
5317 ins_cost(110);
5318 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5319 opcode(0x8D);
5320 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5321 ins_pipe(ialu_reg_reg_fat);
5322 %}
5324 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5325 %{
5326 predicate(Universe::narrow_oop_shift() == 0);
5327 match(Set dst mem);
5329 ins_cost(110);
5330 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5331 opcode(0x8D);
5332 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5333 ins_pipe(ialu_reg_reg_fat);
5334 %}
5336 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5337 %{
5338 predicate(Universe::narrow_oop_shift() == 0);
5339 match(Set dst mem);
5341 ins_cost(110);
5342 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5343 opcode(0x8D);
5344 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5345 ins_pipe(ialu_reg_reg_fat);
5346 %}
5348 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5349 %{
5350 predicate(Universe::narrow_oop_shift() == 0);
5351 match(Set dst mem);
5353 ins_cost(110);
5354 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5355 opcode(0x8D);
5356 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5357 ins_pipe(ialu_reg_reg_fat);
5358 %}
5360 instruct loadConI(rRegI dst, immI src)
5361 %{
5362 match(Set dst src);
5364 format %{ "movl $dst, $src\t# int" %}
5365 ins_encode(load_immI(dst, src));
5366 ins_pipe(ialu_reg_fat); // XXX
5367 %}
5369 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5370 %{
5371 match(Set dst src);
5372 effect(KILL cr);
5374 ins_cost(50);
5375 format %{ "xorl $dst, $dst\t# int" %}
5376 opcode(0x33); /* + rd */
5377 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5378 ins_pipe(ialu_reg);
5379 %}
5381 instruct loadConL(rRegL dst, immL src)
5382 %{
5383 match(Set dst src);
5385 ins_cost(150);
5386 format %{ "movq $dst, $src\t# long" %}
5387 ins_encode(load_immL(dst, src));
5388 ins_pipe(ialu_reg);
5389 %}
5391 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5392 %{
5393 match(Set dst src);
5394 effect(KILL cr);
5396 ins_cost(50);
5397 format %{ "xorl $dst, $dst\t# long" %}
5398 opcode(0x33); /* + rd */
5399 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5400 ins_pipe(ialu_reg); // XXX
5401 %}
5403 instruct loadConUL32(rRegL dst, immUL32 src)
5404 %{
5405 match(Set dst src);
5407 ins_cost(60);
5408 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5409 ins_encode(load_immUL32(dst, src));
5410 ins_pipe(ialu_reg);
5411 %}
5413 instruct loadConL32(rRegL dst, immL32 src)
5414 %{
5415 match(Set dst src);
5417 ins_cost(70);
5418 format %{ "movq $dst, $src\t# long (32-bit)" %}
5419 ins_encode(load_immL32(dst, src));
5420 ins_pipe(ialu_reg);
5421 %}
5423 instruct loadConP(rRegP dst, immP con) %{
5424 match(Set dst con);
5426 format %{ "movq $dst, $con\t# ptr" %}
5427 ins_encode(load_immP(dst, con));
5428 ins_pipe(ialu_reg_fat); // XXX
5429 %}
5431 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5432 %{
5433 match(Set dst src);
5434 effect(KILL cr);
5436 ins_cost(50);
5437 format %{ "xorl $dst, $dst\t# ptr" %}
5438 opcode(0x33); /* + rd */
5439 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5440 ins_pipe(ialu_reg);
5441 %}
5443 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5444 %{
5445 match(Set dst src);
5446 effect(KILL cr);
5448 ins_cost(60);
5449 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5450 ins_encode(load_immP31(dst, src));
5451 ins_pipe(ialu_reg);
5452 %}
5454 instruct loadConF(regF dst, immF con) %{
5455 match(Set dst con);
5456 ins_cost(125);
5457 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5458 ins_encode %{
5459 __ movflt($dst$$XMMRegister, $constantaddress($con));
5460 %}
5461 ins_pipe(pipe_slow);
5462 %}
5464 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5465 match(Set dst src);
5466 effect(KILL cr);
5467 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5468 ins_encode %{
5469 __ xorq($dst$$Register, $dst$$Register);
5470 %}
5471 ins_pipe(ialu_reg);
5472 %}
5474 instruct loadConN(rRegN dst, immN src) %{
5475 match(Set dst src);
5477 ins_cost(125);
5478 format %{ "movl $dst, $src\t# compressed ptr" %}
5479 ins_encode %{
5480 address con = (address)$src$$constant;
5481 if (con == NULL) {
5482 ShouldNotReachHere();
5483 } else {
5484 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5485 }
5486 %}
5487 ins_pipe(ialu_reg_fat); // XXX
5488 %}
5490 instruct loadConF0(regF dst, immF0 src)
5491 %{
5492 match(Set dst src);
5493 ins_cost(100);
5495 format %{ "xorps $dst, $dst\t# float 0.0" %}
5496 ins_encode %{
5497 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5498 %}
5499 ins_pipe(pipe_slow);
5500 %}
5502 // Use the same format since predicate() can not be used here.
5503 instruct loadConD(regD dst, immD con) %{
5504 match(Set dst con);
5505 ins_cost(125);
5506 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5507 ins_encode %{
5508 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5509 %}
5510 ins_pipe(pipe_slow);
5511 %}
5513 instruct loadConD0(regD dst, immD0 src)
5514 %{
5515 match(Set dst src);
5516 ins_cost(100);
5518 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5519 ins_encode %{
5520 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5521 %}
5522 ins_pipe(pipe_slow);
5523 %}
5525 instruct loadSSI(rRegI dst, stackSlotI src)
5526 %{
5527 match(Set dst src);
5529 ins_cost(125);
5530 format %{ "movl $dst, $src\t# int stk" %}
5531 opcode(0x8B);
5532 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5533 ins_pipe(ialu_reg_mem);
5534 %}
5536 instruct loadSSL(rRegL dst, stackSlotL src)
5537 %{
5538 match(Set dst src);
5540 ins_cost(125);
5541 format %{ "movq $dst, $src\t# long stk" %}
5542 opcode(0x8B);
5543 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5544 ins_pipe(ialu_reg_mem);
5545 %}
5547 instruct loadSSP(rRegP dst, stackSlotP src)
5548 %{
5549 match(Set dst src);
5551 ins_cost(125);
5552 format %{ "movq $dst, $src\t# ptr stk" %}
5553 opcode(0x8B);
5554 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5555 ins_pipe(ialu_reg_mem);
5556 %}
5558 instruct loadSSF(regF dst, stackSlotF src)
5559 %{
5560 match(Set dst src);
5562 ins_cost(125);
5563 format %{ "movss $dst, $src\t# float stk" %}
5564 ins_encode %{
5565 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5566 %}
5567 ins_pipe(pipe_slow); // XXX
5568 %}
5570 // Use the same format since predicate() can not be used here.
5571 instruct loadSSD(regD dst, stackSlotD src)
5572 %{
5573 match(Set dst src);
5575 ins_cost(125);
5576 format %{ "movsd $dst, $src\t# double stk" %}
5577 ins_encode %{
5578 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5579 %}
5580 ins_pipe(pipe_slow); // XXX
5581 %}
5583 // Prefetch instructions.
5584 // Must be safe to execute with invalid address (cannot fault).
5586 instruct prefetchr( memory mem ) %{
5587 predicate(ReadPrefetchInstr==3);
5588 match(PrefetchRead mem);
5589 ins_cost(125);
5591 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
5592 ins_encode %{
5593 __ prefetchr($mem$$Address);
5594 %}
5595 ins_pipe(ialu_mem);
5596 %}
5598 instruct prefetchrNTA( memory mem ) %{
5599 predicate(ReadPrefetchInstr==0);
5600 match(PrefetchRead mem);
5601 ins_cost(125);
5603 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
5604 ins_encode %{
5605 __ prefetchnta($mem$$Address);
5606 %}
5607 ins_pipe(ialu_mem);
5608 %}
5610 instruct prefetchrT0( memory mem ) %{
5611 predicate(ReadPrefetchInstr==1);
5612 match(PrefetchRead mem);
5613 ins_cost(125);
5615 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
5616 ins_encode %{
5617 __ prefetcht0($mem$$Address);
5618 %}
5619 ins_pipe(ialu_mem);
5620 %}
5622 instruct prefetchrT2( memory mem ) %{
5623 predicate(ReadPrefetchInstr==2);
5624 match(PrefetchRead mem);
5625 ins_cost(125);
5627 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
5628 ins_encode %{
5629 __ prefetcht2($mem$$Address);
5630 %}
5631 ins_pipe(ialu_mem);
5632 %}
5634 instruct prefetchwNTA( memory mem ) %{
5635 match(PrefetchWrite mem);
5636 ins_cost(125);
5638 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
5639 ins_encode %{
5640 __ prefetchnta($mem$$Address);
5641 %}
5642 ins_pipe(ialu_mem);
5643 %}
5645 // Prefetch instructions for allocation.
5647 instruct prefetchAlloc( memory mem ) %{
5648 predicate(AllocatePrefetchInstr==3);
5649 match(PrefetchAllocation mem);
5650 ins_cost(125);
5652 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5653 ins_encode %{
5654 __ prefetchw($mem$$Address);
5655 %}
5656 ins_pipe(ialu_mem);
5657 %}
5659 instruct prefetchAllocNTA( memory mem ) %{
5660 predicate(AllocatePrefetchInstr==0);
5661 match(PrefetchAllocation mem);
5662 ins_cost(125);
5664 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5665 ins_encode %{
5666 __ prefetchnta($mem$$Address);
5667 %}
5668 ins_pipe(ialu_mem);
5669 %}
5671 instruct prefetchAllocT0( memory mem ) %{
5672 predicate(AllocatePrefetchInstr==1);
5673 match(PrefetchAllocation mem);
5674 ins_cost(125);
5676 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5677 ins_encode %{
5678 __ prefetcht0($mem$$Address);
5679 %}
5680 ins_pipe(ialu_mem);
5681 %}
5683 instruct prefetchAllocT2( memory mem ) %{
5684 predicate(AllocatePrefetchInstr==2);
5685 match(PrefetchAllocation mem);
5686 ins_cost(125);
5688 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5689 ins_encode %{
5690 __ prefetcht2($mem$$Address);
5691 %}
5692 ins_pipe(ialu_mem);
5693 %}
5695 //----------Store Instructions-------------------------------------------------
5697 // Store Byte
5698 instruct storeB(memory mem, rRegI src)
5699 %{
5700 match(Set mem (StoreB mem src));
5702 ins_cost(125); // XXX
5703 format %{ "movb $mem, $src\t# byte" %}
5704 opcode(0x88);
5705 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5706 ins_pipe(ialu_mem_reg);
5707 %}
5709 // Store Char/Short
5710 instruct storeC(memory mem, rRegI src)
5711 %{
5712 match(Set mem (StoreC mem src));
5714 ins_cost(125); // XXX
5715 format %{ "movw $mem, $src\t# char/short" %}
5716 opcode(0x89);
5717 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5718 ins_pipe(ialu_mem_reg);
5719 %}
5721 // Store Integer
5722 instruct storeI(memory mem, rRegI src)
5723 %{
5724 match(Set mem (StoreI mem src));
5726 ins_cost(125); // XXX
5727 format %{ "movl $mem, $src\t# int" %}
5728 opcode(0x89);
5729 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5730 ins_pipe(ialu_mem_reg);
5731 %}
5733 // Store Long
5734 instruct storeL(memory mem, rRegL src)
5735 %{
5736 match(Set mem (StoreL mem src));
5738 ins_cost(125); // XXX
5739 format %{ "movq $mem, $src\t# long" %}
5740 opcode(0x89);
5741 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5742 ins_pipe(ialu_mem_reg); // XXX
5743 %}
5745 // Store Pointer
5746 instruct storeP(memory mem, any_RegP src)
5747 %{
5748 match(Set mem (StoreP mem src));
5750 ins_cost(125); // XXX
5751 format %{ "movq $mem, $src\t# ptr" %}
5752 opcode(0x89);
5753 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5754 ins_pipe(ialu_mem_reg);
5755 %}
5757 instruct storeImmP0(memory mem, immP0 zero)
5758 %{
5759 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
5760 match(Set mem (StoreP mem zero));
5762 ins_cost(125); // XXX
5763 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5764 ins_encode %{
5765 __ movq($mem$$Address, r12);
5766 %}
5767 ins_pipe(ialu_mem_reg);
5768 %}
5770 // Store NULL Pointer, mark word, or other simple pointer constant.
5771 instruct storeImmP(memory mem, immP31 src)
5772 %{
5773 match(Set mem (StoreP mem src));
5775 ins_cost(150); // XXX
5776 format %{ "movq $mem, $src\t# ptr" %}
5777 opcode(0xC7); /* C7 /0 */
5778 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5779 ins_pipe(ialu_mem_imm);
5780 %}
5782 // Store Compressed Pointer
5783 instruct storeN(memory mem, rRegN src)
5784 %{
5785 match(Set mem (StoreN mem src));
5787 ins_cost(125); // XXX
5788 format %{ "movl $mem, $src\t# compressed ptr" %}
5789 ins_encode %{
5790 __ movl($mem$$Address, $src$$Register);
5791 %}
5792 ins_pipe(ialu_mem_reg);
5793 %}
5795 instruct storeImmN0(memory mem, immN0 zero)
5796 %{
5797 predicate(Universe::narrow_oop_base() == NULL);
5798 match(Set mem (StoreN mem zero));
5800 ins_cost(125); // XXX
5801 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5802 ins_encode %{
5803 __ movl($mem$$Address, r12);
5804 %}
5805 ins_pipe(ialu_mem_reg);
5806 %}
5808 instruct storeImmN(memory mem, immN src)
5809 %{
5810 match(Set mem (StoreN mem src));
5812 ins_cost(150); // XXX
5813 format %{ "movl $mem, $src\t# compressed ptr" %}
5814 ins_encode %{
5815 address con = (address)$src$$constant;
5816 if (con == NULL) {
5817 __ movl($mem$$Address, (int32_t)0);
5818 } else {
5819 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5820 }
5821 %}
5822 ins_pipe(ialu_mem_imm);
5823 %}
5825 // Store Integer Immediate
5826 instruct storeImmI0(memory mem, immI0 zero)
5827 %{
5828 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
5829 match(Set mem (StoreI mem zero));
5831 ins_cost(125); // XXX
5832 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5833 ins_encode %{
5834 __ movl($mem$$Address, r12);
5835 %}
5836 ins_pipe(ialu_mem_reg);
5837 %}
5839 instruct storeImmI(memory mem, immI src)
5840 %{
5841 match(Set mem (StoreI mem src));
5843 ins_cost(150);
5844 format %{ "movl $mem, $src\t# int" %}
5845 opcode(0xC7); /* C7 /0 */
5846 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5847 ins_pipe(ialu_mem_imm);
5848 %}
5850 // Store Long Immediate
5851 instruct storeImmL0(memory mem, immL0 zero)
5852 %{
5853 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
5854 match(Set mem (StoreL mem zero));
5856 ins_cost(125); // XXX
5857 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5858 ins_encode %{
5859 __ movq($mem$$Address, r12);
5860 %}
5861 ins_pipe(ialu_mem_reg);
5862 %}
5864 instruct storeImmL(memory mem, immL32 src)
5865 %{
5866 match(Set mem (StoreL mem src));
5868 ins_cost(150);
5869 format %{ "movq $mem, $src\t# long" %}
5870 opcode(0xC7); /* C7 /0 */
5871 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5872 ins_pipe(ialu_mem_imm);
5873 %}
5875 // Store Short/Char Immediate
5876 instruct storeImmC0(memory mem, immI0 zero)
5877 %{
5878 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
5879 match(Set mem (StoreC mem zero));
5881 ins_cost(125); // XXX
5882 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5883 ins_encode %{
5884 __ movw($mem$$Address, r12);
5885 %}
5886 ins_pipe(ialu_mem_reg);
5887 %}
5889 instruct storeImmI16(memory mem, immI16 src)
5890 %{
5891 predicate(UseStoreImmI16);
5892 match(Set mem (StoreC mem src));
5894 ins_cost(150);
5895 format %{ "movw $mem, $src\t# short/char" %}
5896 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
5897 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
5898 ins_pipe(ialu_mem_imm);
5899 %}
5901 // Store Byte Immediate
5902 instruct storeImmB0(memory mem, immI0 zero)
5903 %{
5904 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
5905 match(Set mem (StoreB mem zero));
5907 ins_cost(125); // XXX
5908 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5909 ins_encode %{
5910 __ movb($mem$$Address, r12);
5911 %}
5912 ins_pipe(ialu_mem_reg);
5913 %}
5915 instruct storeImmB(memory mem, immI8 src)
5916 %{
5917 match(Set mem (StoreB mem src));
5919 ins_cost(150); // XXX
5920 format %{ "movb $mem, $src\t# byte" %}
5921 opcode(0xC6); /* C6 /0 */
5922 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5923 ins_pipe(ialu_mem_imm);
5924 %}
5926 // Store CMS card-mark Immediate
5927 instruct storeImmCM0_reg(memory mem, immI0 zero)
5928 %{
5929 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
5930 match(Set mem (StoreCM mem zero));
5932 ins_cost(125); // XXX
5933 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
5934 ins_encode %{
5935 __ movb($mem$$Address, r12);
5936 %}
5937 ins_pipe(ialu_mem_reg);
5938 %}
5940 instruct storeImmCM0(memory mem, immI0 src)
5941 %{
5942 match(Set mem (StoreCM mem src));
5944 ins_cost(150); // XXX
5945 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
5946 opcode(0xC6); /* C6 /0 */
5947 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5948 ins_pipe(ialu_mem_imm);
5949 %}
5951 // Store Float
5952 instruct storeF(memory mem, regF src)
5953 %{
5954 match(Set mem (StoreF mem src));
5956 ins_cost(95); // XXX
5957 format %{ "movss $mem, $src\t# float" %}
5958 ins_encode %{
5959 __ movflt($mem$$Address, $src$$XMMRegister);
5960 %}
5961 ins_pipe(pipe_slow); // XXX
5962 %}
5964 // Store immediate Float value (it is faster than store from XMM register)
5965 instruct storeF0(memory mem, immF0 zero)
5966 %{
5967 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
5968 match(Set mem (StoreF mem zero));
5970 ins_cost(25); // XXX
5971 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
5972 ins_encode %{
5973 __ movl($mem$$Address, r12);
5974 %}
5975 ins_pipe(ialu_mem_reg);
5976 %}
5978 instruct storeF_imm(memory mem, immF src)
5979 %{
5980 match(Set mem (StoreF mem src));
5982 ins_cost(50);
5983 format %{ "movl $mem, $src\t# float" %}
5984 opcode(0xC7); /* C7 /0 */
5985 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5986 ins_pipe(ialu_mem_imm);
5987 %}
5989 // Store Double
5990 instruct storeD(memory mem, regD src)
5991 %{
5992 match(Set mem (StoreD mem src));
5994 ins_cost(95); // XXX
5995 format %{ "movsd $mem, $src\t# double" %}
5996 ins_encode %{
5997 __ movdbl($mem$$Address, $src$$XMMRegister);
5998 %}
5999 ins_pipe(pipe_slow); // XXX
6000 %}
6002 // Store immediate double 0.0 (it is faster than store from XMM register)
6003 instruct storeD0_imm(memory mem, immD0 src)
6004 %{
6005 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
6006 match(Set mem (StoreD mem src));
6008 ins_cost(50);
6009 format %{ "movq $mem, $src\t# double 0." %}
6010 opcode(0xC7); /* C7 /0 */
6011 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6012 ins_pipe(ialu_mem_imm);
6013 %}
6015 instruct storeD0(memory mem, immD0 zero)
6016 %{
6017 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
6018 match(Set mem (StoreD mem zero));
6020 ins_cost(25); // XXX
6021 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
6022 ins_encode %{
6023 __ movq($mem$$Address, r12);
6024 %}
6025 ins_pipe(ialu_mem_reg);
6026 %}
6028 instruct storeSSI(stackSlotI dst, rRegI src)
6029 %{
6030 match(Set dst src);
6032 ins_cost(100);
6033 format %{ "movl $dst, $src\t# int stk" %}
6034 opcode(0x89);
6035 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6036 ins_pipe( ialu_mem_reg );
6037 %}
6039 instruct storeSSL(stackSlotL dst, rRegL src)
6040 %{
6041 match(Set dst src);
6043 ins_cost(100);
6044 format %{ "movq $dst, $src\t# long stk" %}
6045 opcode(0x89);
6046 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6047 ins_pipe(ialu_mem_reg);
6048 %}
6050 instruct storeSSP(stackSlotP dst, rRegP src)
6051 %{
6052 match(Set dst src);
6054 ins_cost(100);
6055 format %{ "movq $dst, $src\t# ptr stk" %}
6056 opcode(0x89);
6057 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6058 ins_pipe(ialu_mem_reg);
6059 %}
6061 instruct storeSSF(stackSlotF dst, regF src)
6062 %{
6063 match(Set dst src);
6065 ins_cost(95); // XXX
6066 format %{ "movss $dst, $src\t# float stk" %}
6067 ins_encode %{
6068 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6069 %}
6070 ins_pipe(pipe_slow); // XXX
6071 %}
6073 instruct storeSSD(stackSlotD dst, regD src)
6074 %{
6075 match(Set dst src);
6077 ins_cost(95); // XXX
6078 format %{ "movsd $dst, $src\t# double stk" %}
6079 ins_encode %{
6080 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6081 %}
6082 ins_pipe(pipe_slow); // XXX
6083 %}
6085 //----------BSWAP Instructions-------------------------------------------------
6086 instruct bytes_reverse_int(rRegI dst) %{
6087 match(Set dst (ReverseBytesI dst));
6089 format %{ "bswapl $dst" %}
6090 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6091 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6092 ins_pipe( ialu_reg );
6093 %}
6095 instruct bytes_reverse_long(rRegL dst) %{
6096 match(Set dst (ReverseBytesL dst));
6098 format %{ "bswapq $dst" %}
6099 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6100 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6101 ins_pipe( ialu_reg);
6102 %}
6104 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6105 match(Set dst (ReverseBytesUS dst));
6106 effect(KILL cr);
6108 format %{ "bswapl $dst\n\t"
6109 "shrl $dst,16\n\t" %}
6110 ins_encode %{
6111 __ bswapl($dst$$Register);
6112 __ shrl($dst$$Register, 16);
6113 %}
6114 ins_pipe( ialu_reg );
6115 %}
6117 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6118 match(Set dst (ReverseBytesS dst));
6119 effect(KILL cr);
6121 format %{ "bswapl $dst\n\t"
6122 "sar $dst,16\n\t" %}
6123 ins_encode %{
6124 __ bswapl($dst$$Register);
6125 __ sarl($dst$$Register, 16);
6126 %}
6127 ins_pipe( ialu_reg );
6128 %}
6130 //---------- Zeros Count Instructions ------------------------------------------
6132 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6133 predicate(UseCountLeadingZerosInstruction);
6134 match(Set dst (CountLeadingZerosI src));
6135 effect(KILL cr);
6137 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6138 ins_encode %{
6139 __ lzcntl($dst$$Register, $src$$Register);
6140 %}
6141 ins_pipe(ialu_reg);
6142 %}
6144 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6145 predicate(!UseCountLeadingZerosInstruction);
6146 match(Set dst (CountLeadingZerosI src));
6147 effect(KILL cr);
6149 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6150 "jnz skip\n\t"
6151 "movl $dst, -1\n"
6152 "skip:\n\t"
6153 "negl $dst\n\t"
6154 "addl $dst, 31" %}
6155 ins_encode %{
6156 Register Rdst = $dst$$Register;
6157 Register Rsrc = $src$$Register;
6158 Label skip;
6159 __ bsrl(Rdst, Rsrc);
6160 __ jccb(Assembler::notZero, skip);
6161 __ movl(Rdst, -1);
6162 __ bind(skip);
6163 __ negl(Rdst);
6164 __ addl(Rdst, BitsPerInt - 1);
6165 %}
6166 ins_pipe(ialu_reg);
6167 %}
6169 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6170 predicate(UseCountLeadingZerosInstruction);
6171 match(Set dst (CountLeadingZerosL src));
6172 effect(KILL cr);
6174 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6175 ins_encode %{
6176 __ lzcntq($dst$$Register, $src$$Register);
6177 %}
6178 ins_pipe(ialu_reg);
6179 %}
6181 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6182 predicate(!UseCountLeadingZerosInstruction);
6183 match(Set dst (CountLeadingZerosL src));
6184 effect(KILL cr);
6186 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6187 "jnz skip\n\t"
6188 "movl $dst, -1\n"
6189 "skip:\n\t"
6190 "negl $dst\n\t"
6191 "addl $dst, 63" %}
6192 ins_encode %{
6193 Register Rdst = $dst$$Register;
6194 Register Rsrc = $src$$Register;
6195 Label skip;
6196 __ bsrq(Rdst, Rsrc);
6197 __ jccb(Assembler::notZero, skip);
6198 __ movl(Rdst, -1);
6199 __ bind(skip);
6200 __ negl(Rdst);
6201 __ addl(Rdst, BitsPerLong - 1);
6202 %}
6203 ins_pipe(ialu_reg);
6204 %}
6206 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6207 match(Set dst (CountTrailingZerosI src));
6208 effect(KILL cr);
6210 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6211 "jnz done\n\t"
6212 "movl $dst, 32\n"
6213 "done:" %}
6214 ins_encode %{
6215 Register Rdst = $dst$$Register;
6216 Label done;
6217 __ bsfl(Rdst, $src$$Register);
6218 __ jccb(Assembler::notZero, done);
6219 __ movl(Rdst, BitsPerInt);
6220 __ bind(done);
6221 %}
6222 ins_pipe(ialu_reg);
6223 %}
6225 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6226 match(Set dst (CountTrailingZerosL src));
6227 effect(KILL cr);
6229 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6230 "jnz done\n\t"
6231 "movl $dst, 64\n"
6232 "done:" %}
6233 ins_encode %{
6234 Register Rdst = $dst$$Register;
6235 Label done;
6236 __ bsfq(Rdst, $src$$Register);
6237 __ jccb(Assembler::notZero, done);
6238 __ movl(Rdst, BitsPerLong);
6239 __ bind(done);
6240 %}
6241 ins_pipe(ialu_reg);
6242 %}
6245 //---------- Population Count Instructions -------------------------------------
6247 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6248 predicate(UsePopCountInstruction);
6249 match(Set dst (PopCountI src));
6250 effect(KILL cr);
6252 format %{ "popcnt $dst, $src" %}
6253 ins_encode %{
6254 __ popcntl($dst$$Register, $src$$Register);
6255 %}
6256 ins_pipe(ialu_reg);
6257 %}
6259 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6260 predicate(UsePopCountInstruction);
6261 match(Set dst (PopCountI (LoadI mem)));
6262 effect(KILL cr);
6264 format %{ "popcnt $dst, $mem" %}
6265 ins_encode %{
6266 __ popcntl($dst$$Register, $mem$$Address);
6267 %}
6268 ins_pipe(ialu_reg);
6269 %}
6271 // Note: Long.bitCount(long) returns an int.
6272 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6273 predicate(UsePopCountInstruction);
6274 match(Set dst (PopCountL src));
6275 effect(KILL cr);
6277 format %{ "popcnt $dst, $src" %}
6278 ins_encode %{
6279 __ popcntq($dst$$Register, $src$$Register);
6280 %}
6281 ins_pipe(ialu_reg);
6282 %}
6284 // Note: Long.bitCount(long) returns an int.
6285 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6286 predicate(UsePopCountInstruction);
6287 match(Set dst (PopCountL (LoadL mem)));
6288 effect(KILL cr);
6290 format %{ "popcnt $dst, $mem" %}
6291 ins_encode %{
6292 __ popcntq($dst$$Register, $mem$$Address);
6293 %}
6294 ins_pipe(ialu_reg);
6295 %}
6298 //----------MemBar Instructions-----------------------------------------------
6299 // Memory barrier flavors
6301 instruct membar_acquire()
6302 %{
6303 match(MemBarAcquire);
6304 ins_cost(0);
6306 size(0);
6307 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6308 ins_encode();
6309 ins_pipe(empty);
6310 %}
6312 instruct membar_acquire_lock()
6313 %{
6314 match(MemBarAcquireLock);
6315 ins_cost(0);
6317 size(0);
6318 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6319 ins_encode();
6320 ins_pipe(empty);
6321 %}
6323 instruct membar_release()
6324 %{
6325 match(MemBarRelease);
6326 ins_cost(0);
6328 size(0);
6329 format %{ "MEMBAR-release ! (empty encoding)" %}
6330 ins_encode();
6331 ins_pipe(empty);
6332 %}
6334 instruct membar_release_lock()
6335 %{
6336 match(MemBarReleaseLock);
6337 ins_cost(0);
6339 size(0);
6340 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6341 ins_encode();
6342 ins_pipe(empty);
6343 %}
6345 instruct membar_volatile(rFlagsReg cr) %{
6346 match(MemBarVolatile);
6347 effect(KILL cr);
6348 ins_cost(400);
6350 format %{
6351 $$template
6352 if (os::is_MP()) {
6353 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6354 } else {
6355 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6356 }
6357 %}
6358 ins_encode %{
6359 __ membar(Assembler::StoreLoad);
6360 %}
6361 ins_pipe(pipe_slow);
6362 %}
6364 instruct unnecessary_membar_volatile()
6365 %{
6366 match(MemBarVolatile);
6367 predicate(Matcher::post_store_load_barrier(n));
6368 ins_cost(0);
6370 size(0);
6371 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6372 ins_encode();
6373 ins_pipe(empty);
6374 %}
6376 instruct membar_storestore() %{
6377 match(MemBarStoreStore);
6378 ins_cost(0);
6380 size(0);
6381 format %{ "MEMBAR-storestore (empty encoding)" %}
6382 ins_encode( );
6383 ins_pipe(empty);
6384 %}
6386 //----------Move Instructions--------------------------------------------------
6388 instruct castX2P(rRegP dst, rRegL src)
6389 %{
6390 match(Set dst (CastX2P src));
6392 format %{ "movq $dst, $src\t# long->ptr" %}
6393 ins_encode %{
6394 if ($dst$$reg != $src$$reg) {
6395 __ movptr($dst$$Register, $src$$Register);
6396 }
6397 %}
6398 ins_pipe(ialu_reg_reg); // XXX
6399 %}
6401 instruct castP2X(rRegL dst, rRegP src)
6402 %{
6403 match(Set dst (CastP2X src));
6405 format %{ "movq $dst, $src\t# ptr -> long" %}
6406 ins_encode %{
6407 if ($dst$$reg != $src$$reg) {
6408 __ movptr($dst$$Register, $src$$Register);
6409 }
6410 %}
6411 ins_pipe(ialu_reg_reg); // XXX
6412 %}
6414 // Convert oop into int for vectors alignment masking
6415 instruct convP2I(rRegI dst, rRegP src)
6416 %{
6417 match(Set dst (ConvL2I (CastP2X src)));
6419 format %{ "movl $dst, $src\t# ptr -> int" %}
6420 ins_encode %{
6421 __ movl($dst$$Register, $src$$Register);
6422 %}
6423 ins_pipe(ialu_reg_reg); // XXX
6424 %}
6426 // Convert compressed oop into int for vectors alignment masking
6427 // in case of 32bit oops (heap < 4Gb).
6428 instruct convN2I(rRegI dst, rRegN src)
6429 %{
6430 predicate(Universe::narrow_oop_shift() == 0);
6431 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6433 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6434 ins_encode %{
6435 __ movl($dst$$Register, $src$$Register);
6436 %}
6437 ins_pipe(ialu_reg_reg); // XXX
6438 %}
6440 // Convert oop pointer into compressed form
6441 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6442 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6443 match(Set dst (EncodeP src));
6444 effect(KILL cr);
6445 format %{ "encode_heap_oop $dst,$src" %}
6446 ins_encode %{
6447 Register s = $src$$Register;
6448 Register d = $dst$$Register;
6449 if (s != d) {
6450 __ movq(d, s);
6451 }
6452 __ encode_heap_oop(d);
6453 %}
6454 ins_pipe(ialu_reg_long);
6455 %}
6457 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6458 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6459 match(Set dst (EncodeP src));
6460 effect(KILL cr);
6461 format %{ "encode_heap_oop_not_null $dst,$src" %}
6462 ins_encode %{
6463 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6464 %}
6465 ins_pipe(ialu_reg_long);
6466 %}
6468 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6469 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6470 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6471 match(Set dst (DecodeN src));
6472 effect(KILL cr);
6473 format %{ "decode_heap_oop $dst,$src" %}
6474 ins_encode %{
6475 Register s = $src$$Register;
6476 Register d = $dst$$Register;
6477 if (s != d) {
6478 __ movq(d, s);
6479 }
6480 __ decode_heap_oop(d);
6481 %}
6482 ins_pipe(ialu_reg_long);
6483 %}
6485 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6486 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6487 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6488 match(Set dst (DecodeN src));
6489 effect(KILL cr);
6490 format %{ "decode_heap_oop_not_null $dst,$src" %}
6491 ins_encode %{
6492 Register s = $src$$Register;
6493 Register d = $dst$$Register;
6494 if (s != d) {
6495 __ decode_heap_oop_not_null(d, s);
6496 } else {
6497 __ decode_heap_oop_not_null(d);
6498 }
6499 %}
6500 ins_pipe(ialu_reg_long);
6501 %}
6504 //----------Conditional Move---------------------------------------------------
6505 // Jump
6506 // dummy instruction for generating temp registers
6507 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6508 match(Jump (LShiftL switch_val shift));
6509 ins_cost(350);
6510 predicate(false);
6511 effect(TEMP dest);
6513 format %{ "leaq $dest, [$constantaddress]\n\t"
6514 "jmp [$dest + $switch_val << $shift]\n\t" %}
6515 ins_encode %{
6516 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6517 // to do that and the compiler is using that register as one it can allocate.
6518 // So we build it all by hand.
6519 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6520 // ArrayAddress dispatch(table, index);
6521 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6522 __ lea($dest$$Register, $constantaddress);
6523 __ jmp(dispatch);
6524 %}
6525 ins_pipe(pipe_jmp);
6526 %}
6528 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6529 match(Jump (AddL (LShiftL switch_val shift) offset));
6530 ins_cost(350);
6531 effect(TEMP dest);
6533 format %{ "leaq $dest, [$constantaddress]\n\t"
6534 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6535 ins_encode %{
6536 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6537 // to do that and the compiler is using that register as one it can allocate.
6538 // So we build it all by hand.
6539 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6540 // ArrayAddress dispatch(table, index);
6541 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6542 __ lea($dest$$Register, $constantaddress);
6543 __ jmp(dispatch);
6544 %}
6545 ins_pipe(pipe_jmp);
6546 %}
6548 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6549 match(Jump switch_val);
6550 ins_cost(350);
6551 effect(TEMP dest);
6553 format %{ "leaq $dest, [$constantaddress]\n\t"
6554 "jmp [$dest + $switch_val]\n\t" %}
6555 ins_encode %{
6556 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6557 // to do that and the compiler is using that register as one it can allocate.
6558 // So we build it all by hand.
6559 // Address index(noreg, switch_reg, Address::times_1);
6560 // ArrayAddress dispatch(table, index);
6561 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6562 __ lea($dest$$Register, $constantaddress);
6563 __ jmp(dispatch);
6564 %}
6565 ins_pipe(pipe_jmp);
6566 %}
6568 // Conditional move
6569 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6570 %{
6571 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6573 ins_cost(200); // XXX
6574 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6575 opcode(0x0F, 0x40);
6576 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6577 ins_pipe(pipe_cmov_reg);
6578 %}
6580 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6581 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6583 ins_cost(200); // XXX
6584 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6585 opcode(0x0F, 0x40);
6586 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6587 ins_pipe(pipe_cmov_reg);
6588 %}
6590 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6591 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6592 ins_cost(200);
6593 expand %{
6594 cmovI_regU(cop, cr, dst, src);
6595 %}
6596 %}
6598 // Conditional move
6599 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6600 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6602 ins_cost(250); // XXX
6603 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6604 opcode(0x0F, 0x40);
6605 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6606 ins_pipe(pipe_cmov_mem);
6607 %}
6609 // Conditional move
6610 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6611 %{
6612 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6614 ins_cost(250); // XXX
6615 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6616 opcode(0x0F, 0x40);
6617 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6618 ins_pipe(pipe_cmov_mem);
6619 %}
6621 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6622 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6623 ins_cost(250);
6624 expand %{
6625 cmovI_memU(cop, cr, dst, src);
6626 %}
6627 %}
6629 // Conditional move
6630 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6631 %{
6632 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6634 ins_cost(200); // XXX
6635 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6636 opcode(0x0F, 0x40);
6637 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6638 ins_pipe(pipe_cmov_reg);
6639 %}
6641 // Conditional move
6642 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6643 %{
6644 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6646 ins_cost(200); // XXX
6647 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6648 opcode(0x0F, 0x40);
6649 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6650 ins_pipe(pipe_cmov_reg);
6651 %}
6653 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6654 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6655 ins_cost(200);
6656 expand %{
6657 cmovN_regU(cop, cr, dst, src);
6658 %}
6659 %}
6661 // Conditional move
6662 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6663 %{
6664 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6666 ins_cost(200); // XXX
6667 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6668 opcode(0x0F, 0x40);
6669 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6670 ins_pipe(pipe_cmov_reg); // XXX
6671 %}
6673 // Conditional move
6674 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6675 %{
6676 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6678 ins_cost(200); // XXX
6679 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6680 opcode(0x0F, 0x40);
6681 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6682 ins_pipe(pipe_cmov_reg); // XXX
6683 %}
6685 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6686 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6687 ins_cost(200);
6688 expand %{
6689 cmovP_regU(cop, cr, dst, src);
6690 %}
6691 %}
6693 // DISABLED: Requires the ADLC to emit a bottom_type call that
6694 // correctly meets the two pointer arguments; one is an incoming
6695 // register but the other is a memory operand. ALSO appears to
6696 // be buggy with implicit null checks.
6697 //
6698 //// Conditional move
6699 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
6700 //%{
6701 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6702 // ins_cost(250);
6703 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6704 // opcode(0x0F,0x40);
6705 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6706 // ins_pipe( pipe_cmov_mem );
6707 //%}
6708 //
6709 //// Conditional move
6710 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
6711 //%{
6712 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6713 // ins_cost(250);
6714 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6715 // opcode(0x0F,0x40);
6716 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6717 // ins_pipe( pipe_cmov_mem );
6718 //%}
6720 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6721 %{
6722 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6724 ins_cost(200); // XXX
6725 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6726 opcode(0x0F, 0x40);
6727 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6728 ins_pipe(pipe_cmov_reg); // XXX
6729 %}
6731 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6732 %{
6733 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6735 ins_cost(200); // XXX
6736 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6737 opcode(0x0F, 0x40);
6738 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6739 ins_pipe(pipe_cmov_mem); // XXX
6740 %}
6742 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6743 %{
6744 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6746 ins_cost(200); // XXX
6747 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6748 opcode(0x0F, 0x40);
6749 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6750 ins_pipe(pipe_cmov_reg); // XXX
6751 %}
6753 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6754 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6755 ins_cost(200);
6756 expand %{
6757 cmovL_regU(cop, cr, dst, src);
6758 %}
6759 %}
6761 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6762 %{
6763 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6765 ins_cost(200); // XXX
6766 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6767 opcode(0x0F, 0x40);
6768 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6769 ins_pipe(pipe_cmov_mem); // XXX
6770 %}
6772 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6773 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6774 ins_cost(200);
6775 expand %{
6776 cmovL_memU(cop, cr, dst, src);
6777 %}
6778 %}
6780 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6781 %{
6782 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6784 ins_cost(200); // XXX
6785 format %{ "jn$cop skip\t# signed cmove float\n\t"
6786 "movss $dst, $src\n"
6787 "skip:" %}
6788 ins_encode %{
6789 Label Lskip;
6790 // Invert sense of branch from sense of CMOV
6791 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6792 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6793 __ bind(Lskip);
6794 %}
6795 ins_pipe(pipe_slow);
6796 %}
6798 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
6799 // %{
6800 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
6802 // ins_cost(200); // XXX
6803 // format %{ "jn$cop skip\t# signed cmove float\n\t"
6804 // "movss $dst, $src\n"
6805 // "skip:" %}
6806 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
6807 // ins_pipe(pipe_slow);
6808 // %}
6810 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6811 %{
6812 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6814 ins_cost(200); // XXX
6815 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6816 "movss $dst, $src\n"
6817 "skip:" %}
6818 ins_encode %{
6819 Label Lskip;
6820 // Invert sense of branch from sense of CMOV
6821 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6822 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6823 __ bind(Lskip);
6824 %}
6825 ins_pipe(pipe_slow);
6826 %}
6828 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6829 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6830 ins_cost(200);
6831 expand %{
6832 cmovF_regU(cop, cr, dst, src);
6833 %}
6834 %}
6836 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6837 %{
6838 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6840 ins_cost(200); // XXX
6841 format %{ "jn$cop skip\t# signed cmove double\n\t"
6842 "movsd $dst, $src\n"
6843 "skip:" %}
6844 ins_encode %{
6845 Label Lskip;
6846 // Invert sense of branch from sense of CMOV
6847 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6848 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6849 __ bind(Lskip);
6850 %}
6851 ins_pipe(pipe_slow);
6852 %}
6854 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6855 %{
6856 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6858 ins_cost(200); // XXX
6859 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6860 "movsd $dst, $src\n"
6861 "skip:" %}
6862 ins_encode %{
6863 Label Lskip;
6864 // Invert sense of branch from sense of CMOV
6865 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6866 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6867 __ bind(Lskip);
6868 %}
6869 ins_pipe(pipe_slow);
6870 %}
6872 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6873 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6874 ins_cost(200);
6875 expand %{
6876 cmovD_regU(cop, cr, dst, src);
6877 %}
6878 %}
6880 //----------Arithmetic Instructions--------------------------------------------
6881 //----------Addition Instructions----------------------------------------------
6883 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6884 %{
6885 match(Set dst (AddI dst src));
6886 effect(KILL cr);
6888 format %{ "addl $dst, $src\t# int" %}
6889 opcode(0x03);
6890 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
6891 ins_pipe(ialu_reg_reg);
6892 %}
6894 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6895 %{
6896 match(Set dst (AddI dst src));
6897 effect(KILL cr);
6899 format %{ "addl $dst, $src\t# int" %}
6900 opcode(0x81, 0x00); /* /0 id */
6901 ins_encode(OpcSErm(dst, src), Con8or32(src));
6902 ins_pipe( ialu_reg );
6903 %}
6905 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
6906 %{
6907 match(Set dst (AddI dst (LoadI src)));
6908 effect(KILL cr);
6910 ins_cost(125); // XXX
6911 format %{ "addl $dst, $src\t# int" %}
6912 opcode(0x03);
6913 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6914 ins_pipe(ialu_reg_mem);
6915 %}
6917 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
6918 %{
6919 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6920 effect(KILL cr);
6922 ins_cost(150); // XXX
6923 format %{ "addl $dst, $src\t# int" %}
6924 opcode(0x01); /* Opcode 01 /r */
6925 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6926 ins_pipe(ialu_mem_reg);
6927 %}
6929 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
6930 %{
6931 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6932 effect(KILL cr);
6934 ins_cost(125); // XXX
6935 format %{ "addl $dst, $src\t# int" %}
6936 opcode(0x81); /* Opcode 81 /0 id */
6937 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
6938 ins_pipe(ialu_mem_imm);
6939 %}
6941 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
6942 %{
6943 predicate(UseIncDec);
6944 match(Set dst (AddI dst src));
6945 effect(KILL cr);
6947 format %{ "incl $dst\t# int" %}
6948 opcode(0xFF, 0x00); // FF /0
6949 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6950 ins_pipe(ialu_reg);
6951 %}
6953 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
6954 %{
6955 predicate(UseIncDec);
6956 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6957 effect(KILL cr);
6959 ins_cost(125); // XXX
6960 format %{ "incl $dst\t# int" %}
6961 opcode(0xFF); /* Opcode FF /0 */
6962 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
6963 ins_pipe(ialu_mem_imm);
6964 %}
6966 // XXX why does that use AddI
6967 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
6968 %{
6969 predicate(UseIncDec);
6970 match(Set dst (AddI dst src));
6971 effect(KILL cr);
6973 format %{ "decl $dst\t# int" %}
6974 opcode(0xFF, 0x01); // FF /1
6975 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6976 ins_pipe(ialu_reg);
6977 %}
6979 // XXX why does that use AddI
6980 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
6981 %{
6982 predicate(UseIncDec);
6983 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6984 effect(KILL cr);
6986 ins_cost(125); // XXX
6987 format %{ "decl $dst\t# int" %}
6988 opcode(0xFF); /* Opcode FF /1 */
6989 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
6990 ins_pipe(ialu_mem_imm);
6991 %}
6993 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
6994 %{
6995 match(Set dst (AddI src0 src1));
6997 ins_cost(110);
6998 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
6999 opcode(0x8D); /* 0x8D /r */
7000 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7001 ins_pipe(ialu_reg_reg);
7002 %}
7004 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7005 %{
7006 match(Set dst (AddL dst src));
7007 effect(KILL cr);
7009 format %{ "addq $dst, $src\t# long" %}
7010 opcode(0x03);
7011 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7012 ins_pipe(ialu_reg_reg);
7013 %}
7015 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7016 %{
7017 match(Set dst (AddL dst src));
7018 effect(KILL cr);
7020 format %{ "addq $dst, $src\t# long" %}
7021 opcode(0x81, 0x00); /* /0 id */
7022 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7023 ins_pipe( ialu_reg );
7024 %}
7026 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7027 %{
7028 match(Set dst (AddL dst (LoadL src)));
7029 effect(KILL cr);
7031 ins_cost(125); // XXX
7032 format %{ "addq $dst, $src\t# long" %}
7033 opcode(0x03);
7034 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7035 ins_pipe(ialu_reg_mem);
7036 %}
7038 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7039 %{
7040 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7041 effect(KILL cr);
7043 ins_cost(150); // XXX
7044 format %{ "addq $dst, $src\t# long" %}
7045 opcode(0x01); /* Opcode 01 /r */
7046 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7047 ins_pipe(ialu_mem_reg);
7048 %}
7050 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7051 %{
7052 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7053 effect(KILL cr);
7055 ins_cost(125); // XXX
7056 format %{ "addq $dst, $src\t# long" %}
7057 opcode(0x81); /* Opcode 81 /0 id */
7058 ins_encode(REX_mem_wide(dst),
7059 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7060 ins_pipe(ialu_mem_imm);
7061 %}
7063 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7064 %{
7065 predicate(UseIncDec);
7066 match(Set dst (AddL dst src));
7067 effect(KILL cr);
7069 format %{ "incq $dst\t# long" %}
7070 opcode(0xFF, 0x00); // FF /0
7071 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7072 ins_pipe(ialu_reg);
7073 %}
7075 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7076 %{
7077 predicate(UseIncDec);
7078 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7079 effect(KILL cr);
7081 ins_cost(125); // XXX
7082 format %{ "incq $dst\t# long" %}
7083 opcode(0xFF); /* Opcode FF /0 */
7084 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7085 ins_pipe(ialu_mem_imm);
7086 %}
7088 // XXX why does that use AddL
7089 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7090 %{
7091 predicate(UseIncDec);
7092 match(Set dst (AddL dst src));
7093 effect(KILL cr);
7095 format %{ "decq $dst\t# long" %}
7096 opcode(0xFF, 0x01); // FF /1
7097 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7098 ins_pipe(ialu_reg);
7099 %}
7101 // XXX why does that use AddL
7102 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7103 %{
7104 predicate(UseIncDec);
7105 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7106 effect(KILL cr);
7108 ins_cost(125); // XXX
7109 format %{ "decq $dst\t# long" %}
7110 opcode(0xFF); /* Opcode FF /1 */
7111 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7112 ins_pipe(ialu_mem_imm);
7113 %}
7115 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7116 %{
7117 match(Set dst (AddL src0 src1));
7119 ins_cost(110);
7120 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7121 opcode(0x8D); /* 0x8D /r */
7122 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7123 ins_pipe(ialu_reg_reg);
7124 %}
7126 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7127 %{
7128 match(Set dst (AddP dst src));
7129 effect(KILL cr);
7131 format %{ "addq $dst, $src\t# ptr" %}
7132 opcode(0x03);
7133 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7134 ins_pipe(ialu_reg_reg);
7135 %}
7137 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7138 %{
7139 match(Set dst (AddP dst src));
7140 effect(KILL cr);
7142 format %{ "addq $dst, $src\t# ptr" %}
7143 opcode(0x81, 0x00); /* /0 id */
7144 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7145 ins_pipe( ialu_reg );
7146 %}
7148 // XXX addP mem ops ????
7150 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7151 %{
7152 match(Set dst (AddP src0 src1));
7154 ins_cost(110);
7155 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7156 opcode(0x8D); /* 0x8D /r */
7157 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7158 ins_pipe(ialu_reg_reg);
7159 %}
7161 instruct checkCastPP(rRegP dst)
7162 %{
7163 match(Set dst (CheckCastPP dst));
7165 size(0);
7166 format %{ "# checkcastPP of $dst" %}
7167 ins_encode(/* empty encoding */);
7168 ins_pipe(empty);
7169 %}
7171 instruct castPP(rRegP dst)
7172 %{
7173 match(Set dst (CastPP dst));
7175 size(0);
7176 format %{ "# castPP of $dst" %}
7177 ins_encode(/* empty encoding */);
7178 ins_pipe(empty);
7179 %}
7181 instruct castII(rRegI dst)
7182 %{
7183 match(Set dst (CastII dst));
7185 size(0);
7186 format %{ "# castII of $dst" %}
7187 ins_encode(/* empty encoding */);
7188 ins_cost(0);
7189 ins_pipe(empty);
7190 %}
7192 // LoadP-locked same as a regular LoadP when used with compare-swap
7193 instruct loadPLocked(rRegP dst, memory mem)
7194 %{
7195 match(Set dst (LoadPLocked mem));
7197 ins_cost(125); // XXX
7198 format %{ "movq $dst, $mem\t# ptr locked" %}
7199 opcode(0x8B);
7200 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7201 ins_pipe(ialu_reg_mem); // XXX
7202 %}
7204 // Conditional-store of the updated heap-top.
7205 // Used during allocation of the shared heap.
7206 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7208 instruct storePConditional(memory heap_top_ptr,
7209 rax_RegP oldval, rRegP newval,
7210 rFlagsReg cr)
7211 %{
7212 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7214 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7215 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7216 opcode(0x0F, 0xB1);
7217 ins_encode(lock_prefix,
7218 REX_reg_mem_wide(newval, heap_top_ptr),
7219 OpcP, OpcS,
7220 reg_mem(newval, heap_top_ptr));
7221 ins_pipe(pipe_cmpxchg);
7222 %}
7224 // Conditional-store of an int value.
7225 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7226 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7227 %{
7228 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7229 effect(KILL oldval);
7231 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7232 opcode(0x0F, 0xB1);
7233 ins_encode(lock_prefix,
7234 REX_reg_mem(newval, mem),
7235 OpcP, OpcS,
7236 reg_mem(newval, mem));
7237 ins_pipe(pipe_cmpxchg);
7238 %}
7240 // Conditional-store of a long value.
7241 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7242 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7243 %{
7244 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7245 effect(KILL oldval);
7247 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7248 opcode(0x0F, 0xB1);
7249 ins_encode(lock_prefix,
7250 REX_reg_mem_wide(newval, mem),
7251 OpcP, OpcS,
7252 reg_mem(newval, mem));
7253 ins_pipe(pipe_cmpxchg);
7254 %}
7257 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7258 instruct compareAndSwapP(rRegI res,
7259 memory mem_ptr,
7260 rax_RegP oldval, rRegP newval,
7261 rFlagsReg cr)
7262 %{
7263 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7264 effect(KILL cr, KILL oldval);
7266 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7267 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7268 "sete $res\n\t"
7269 "movzbl $res, $res" %}
7270 opcode(0x0F, 0xB1);
7271 ins_encode(lock_prefix,
7272 REX_reg_mem_wide(newval, mem_ptr),
7273 OpcP, OpcS,
7274 reg_mem(newval, mem_ptr),
7275 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7276 REX_reg_breg(res, res), // movzbl
7277 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7278 ins_pipe( pipe_cmpxchg );
7279 %}
7281 instruct compareAndSwapL(rRegI res,
7282 memory mem_ptr,
7283 rax_RegL oldval, rRegL newval,
7284 rFlagsReg cr)
7285 %{
7286 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7287 effect(KILL cr, KILL oldval);
7289 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7290 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7291 "sete $res\n\t"
7292 "movzbl $res, $res" %}
7293 opcode(0x0F, 0xB1);
7294 ins_encode(lock_prefix,
7295 REX_reg_mem_wide(newval, mem_ptr),
7296 OpcP, OpcS,
7297 reg_mem(newval, mem_ptr),
7298 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7299 REX_reg_breg(res, res), // movzbl
7300 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7301 ins_pipe( pipe_cmpxchg );
7302 %}
7304 instruct compareAndSwapI(rRegI res,
7305 memory mem_ptr,
7306 rax_RegI oldval, rRegI newval,
7307 rFlagsReg cr)
7308 %{
7309 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7310 effect(KILL cr, KILL oldval);
7312 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7313 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7314 "sete $res\n\t"
7315 "movzbl $res, $res" %}
7316 opcode(0x0F, 0xB1);
7317 ins_encode(lock_prefix,
7318 REX_reg_mem(newval, mem_ptr),
7319 OpcP, OpcS,
7320 reg_mem(newval, mem_ptr),
7321 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7322 REX_reg_breg(res, res), // movzbl
7323 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7324 ins_pipe( pipe_cmpxchg );
7325 %}
7328 instruct compareAndSwapN(rRegI res,
7329 memory mem_ptr,
7330 rax_RegN oldval, rRegN newval,
7331 rFlagsReg cr) %{
7332 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7333 effect(KILL cr, KILL oldval);
7335 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7336 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7337 "sete $res\n\t"
7338 "movzbl $res, $res" %}
7339 opcode(0x0F, 0xB1);
7340 ins_encode(lock_prefix,
7341 REX_reg_mem(newval, mem_ptr),
7342 OpcP, OpcS,
7343 reg_mem(newval, mem_ptr),
7344 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7345 REX_reg_breg(res, res), // movzbl
7346 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7347 ins_pipe( pipe_cmpxchg );
7348 %}
7350 //----------Subtraction Instructions-------------------------------------------
7352 // Integer Subtraction Instructions
7353 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7354 %{
7355 match(Set dst (SubI dst src));
7356 effect(KILL cr);
7358 format %{ "subl $dst, $src\t# int" %}
7359 opcode(0x2B);
7360 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7361 ins_pipe(ialu_reg_reg);
7362 %}
7364 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7365 %{
7366 match(Set dst (SubI dst src));
7367 effect(KILL cr);
7369 format %{ "subl $dst, $src\t# int" %}
7370 opcode(0x81, 0x05); /* Opcode 81 /5 */
7371 ins_encode(OpcSErm(dst, src), Con8or32(src));
7372 ins_pipe(ialu_reg);
7373 %}
7375 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7376 %{
7377 match(Set dst (SubI dst (LoadI src)));
7378 effect(KILL cr);
7380 ins_cost(125);
7381 format %{ "subl $dst, $src\t# int" %}
7382 opcode(0x2B);
7383 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7384 ins_pipe(ialu_reg_mem);
7385 %}
7387 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7388 %{
7389 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7390 effect(KILL cr);
7392 ins_cost(150);
7393 format %{ "subl $dst, $src\t# int" %}
7394 opcode(0x29); /* Opcode 29 /r */
7395 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7396 ins_pipe(ialu_mem_reg);
7397 %}
7399 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7400 %{
7401 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7402 effect(KILL cr);
7404 ins_cost(125); // XXX
7405 format %{ "subl $dst, $src\t# int" %}
7406 opcode(0x81); /* Opcode 81 /5 id */
7407 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7408 ins_pipe(ialu_mem_imm);
7409 %}
7411 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7412 %{
7413 match(Set dst (SubL dst src));
7414 effect(KILL cr);
7416 format %{ "subq $dst, $src\t# long" %}
7417 opcode(0x2B);
7418 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7419 ins_pipe(ialu_reg_reg);
7420 %}
7422 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7423 %{
7424 match(Set dst (SubL dst src));
7425 effect(KILL cr);
7427 format %{ "subq $dst, $src\t# long" %}
7428 opcode(0x81, 0x05); /* Opcode 81 /5 */
7429 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7430 ins_pipe(ialu_reg);
7431 %}
7433 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7434 %{
7435 match(Set dst (SubL dst (LoadL src)));
7436 effect(KILL cr);
7438 ins_cost(125);
7439 format %{ "subq $dst, $src\t# long" %}
7440 opcode(0x2B);
7441 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7442 ins_pipe(ialu_reg_mem);
7443 %}
7445 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7446 %{
7447 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7448 effect(KILL cr);
7450 ins_cost(150);
7451 format %{ "subq $dst, $src\t# long" %}
7452 opcode(0x29); /* Opcode 29 /r */
7453 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7454 ins_pipe(ialu_mem_reg);
7455 %}
7457 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7458 %{
7459 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7460 effect(KILL cr);
7462 ins_cost(125); // XXX
7463 format %{ "subq $dst, $src\t# long" %}
7464 opcode(0x81); /* Opcode 81 /5 id */
7465 ins_encode(REX_mem_wide(dst),
7466 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7467 ins_pipe(ialu_mem_imm);
7468 %}
7470 // Subtract from a pointer
7471 // XXX hmpf???
7472 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
7473 %{
7474 match(Set dst (AddP dst (SubI zero src)));
7475 effect(KILL cr);
7477 format %{ "subq $dst, $src\t# ptr - int" %}
7478 opcode(0x2B);
7479 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7480 ins_pipe(ialu_reg_reg);
7481 %}
7483 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
7484 %{
7485 match(Set dst (SubI zero dst));
7486 effect(KILL cr);
7488 format %{ "negl $dst\t# int" %}
7489 opcode(0xF7, 0x03); // Opcode F7 /3
7490 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7491 ins_pipe(ialu_reg);
7492 %}
7494 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
7495 %{
7496 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7497 effect(KILL cr);
7499 format %{ "negl $dst\t# int" %}
7500 opcode(0xF7, 0x03); // Opcode F7 /3
7501 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7502 ins_pipe(ialu_reg);
7503 %}
7505 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7506 %{
7507 match(Set dst (SubL zero dst));
7508 effect(KILL cr);
7510 format %{ "negq $dst\t# long" %}
7511 opcode(0xF7, 0x03); // Opcode F7 /3
7512 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7513 ins_pipe(ialu_reg);
7514 %}
7516 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7517 %{
7518 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7519 effect(KILL cr);
7521 format %{ "negq $dst\t# long" %}
7522 opcode(0xF7, 0x03); // Opcode F7 /3
7523 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7524 ins_pipe(ialu_reg);
7525 %}
7528 //----------Multiplication/Division Instructions-------------------------------
7529 // Integer Multiplication Instructions
7530 // Multiply Register
7532 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7533 %{
7534 match(Set dst (MulI dst src));
7535 effect(KILL cr);
7537 ins_cost(300);
7538 format %{ "imull $dst, $src\t# int" %}
7539 opcode(0x0F, 0xAF);
7540 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7541 ins_pipe(ialu_reg_reg_alu0);
7542 %}
7544 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7545 %{
7546 match(Set dst (MulI src imm));
7547 effect(KILL cr);
7549 ins_cost(300);
7550 format %{ "imull $dst, $src, $imm\t# int" %}
7551 opcode(0x69); /* 69 /r id */
7552 ins_encode(REX_reg_reg(dst, src),
7553 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7554 ins_pipe(ialu_reg_reg_alu0);
7555 %}
7557 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
7558 %{
7559 match(Set dst (MulI dst (LoadI src)));
7560 effect(KILL cr);
7562 ins_cost(350);
7563 format %{ "imull $dst, $src\t# int" %}
7564 opcode(0x0F, 0xAF);
7565 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
7566 ins_pipe(ialu_reg_mem_alu0);
7567 %}
7569 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
7570 %{
7571 match(Set dst (MulI (LoadI src) imm));
7572 effect(KILL cr);
7574 ins_cost(300);
7575 format %{ "imull $dst, $src, $imm\t# int" %}
7576 opcode(0x69); /* 69 /r id */
7577 ins_encode(REX_reg_mem(dst, src),
7578 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7579 ins_pipe(ialu_reg_mem_alu0);
7580 %}
7582 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7583 %{
7584 match(Set dst (MulL dst src));
7585 effect(KILL cr);
7587 ins_cost(300);
7588 format %{ "imulq $dst, $src\t# long" %}
7589 opcode(0x0F, 0xAF);
7590 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
7591 ins_pipe(ialu_reg_reg_alu0);
7592 %}
7594 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7595 %{
7596 match(Set dst (MulL src imm));
7597 effect(KILL cr);
7599 ins_cost(300);
7600 format %{ "imulq $dst, $src, $imm\t# long" %}
7601 opcode(0x69); /* 69 /r id */
7602 ins_encode(REX_reg_reg_wide(dst, src),
7603 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7604 ins_pipe(ialu_reg_reg_alu0);
7605 %}
7607 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
7608 %{
7609 match(Set dst (MulL dst (LoadL src)));
7610 effect(KILL cr);
7612 ins_cost(350);
7613 format %{ "imulq $dst, $src\t# long" %}
7614 opcode(0x0F, 0xAF);
7615 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
7616 ins_pipe(ialu_reg_mem_alu0);
7617 %}
7619 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
7620 %{
7621 match(Set dst (MulL (LoadL src) imm));
7622 effect(KILL cr);
7624 ins_cost(300);
7625 format %{ "imulq $dst, $src, $imm\t# long" %}
7626 opcode(0x69); /* 69 /r id */
7627 ins_encode(REX_reg_mem_wide(dst, src),
7628 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7629 ins_pipe(ialu_reg_mem_alu0);
7630 %}
7632 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7633 %{
7634 match(Set dst (MulHiL src rax));
7635 effect(USE_KILL rax, KILL cr);
7637 ins_cost(300);
7638 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7639 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7640 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7641 ins_pipe(ialu_reg_reg_alu0);
7642 %}
7644 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7645 rFlagsReg cr)
7646 %{
7647 match(Set rax (DivI rax div));
7648 effect(KILL rdx, KILL cr);
7650 ins_cost(30*100+10*100); // XXX
7651 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7652 "jne,s normal\n\t"
7653 "xorl rdx, rdx\n\t"
7654 "cmpl $div, -1\n\t"
7655 "je,s done\n"
7656 "normal: cdql\n\t"
7657 "idivl $div\n"
7658 "done:" %}
7659 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7660 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7661 ins_pipe(ialu_reg_reg_alu0);
7662 %}
7664 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7665 rFlagsReg cr)
7666 %{
7667 match(Set rax (DivL rax div));
7668 effect(KILL rdx, KILL cr);
7670 ins_cost(30*100+10*100); // XXX
7671 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7672 "cmpq rax, rdx\n\t"
7673 "jne,s normal\n\t"
7674 "xorl rdx, rdx\n\t"
7675 "cmpq $div, -1\n\t"
7676 "je,s done\n"
7677 "normal: cdqq\n\t"
7678 "idivq $div\n"
7679 "done:" %}
7680 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7681 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7682 ins_pipe(ialu_reg_reg_alu0);
7683 %}
7685 // Integer DIVMOD with Register, both quotient and mod results
7686 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7687 rFlagsReg cr)
7688 %{
7689 match(DivModI rax div);
7690 effect(KILL cr);
7692 ins_cost(30*100+10*100); // XXX
7693 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7694 "jne,s normal\n\t"
7695 "xorl rdx, rdx\n\t"
7696 "cmpl $div, -1\n\t"
7697 "je,s done\n"
7698 "normal: cdql\n\t"
7699 "idivl $div\n"
7700 "done:" %}
7701 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7702 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7703 ins_pipe(pipe_slow);
7704 %}
7706 // Long DIVMOD with Register, both quotient and mod results
7707 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7708 rFlagsReg cr)
7709 %{
7710 match(DivModL rax div);
7711 effect(KILL cr);
7713 ins_cost(30*100+10*100); // XXX
7714 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7715 "cmpq rax, rdx\n\t"
7716 "jne,s normal\n\t"
7717 "xorl rdx, rdx\n\t"
7718 "cmpq $div, -1\n\t"
7719 "je,s done\n"
7720 "normal: cdqq\n\t"
7721 "idivq $div\n"
7722 "done:" %}
7723 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7724 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7725 ins_pipe(pipe_slow);
7726 %}
7728 //----------- DivL-By-Constant-Expansions--------------------------------------
7729 // DivI cases are handled by the compiler
7731 // Magic constant, reciprocal of 10
7732 instruct loadConL_0x6666666666666667(rRegL dst)
7733 %{
7734 effect(DEF dst);
7736 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
7737 ins_encode(load_immL(dst, 0x6666666666666667));
7738 ins_pipe(ialu_reg);
7739 %}
7741 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7742 %{
7743 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
7745 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
7746 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7747 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7748 ins_pipe(ialu_reg_reg_alu0);
7749 %}
7751 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
7752 %{
7753 effect(USE_DEF dst, KILL cr);
7755 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
7756 opcode(0xC1, 0x7); /* C1 /7 ib */
7757 ins_encode(reg_opc_imm_wide(dst, 0x3F));
7758 ins_pipe(ialu_reg);
7759 %}
7761 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
7762 %{
7763 effect(USE_DEF dst, KILL cr);
7765 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
7766 opcode(0xC1, 0x7); /* C1 /7 ib */
7767 ins_encode(reg_opc_imm_wide(dst, 0x2));
7768 ins_pipe(ialu_reg);
7769 %}
7771 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
7772 %{
7773 match(Set dst (DivL src div));
7775 ins_cost((5+8)*100);
7776 expand %{
7777 rax_RegL rax; // Killed temp
7778 rFlagsReg cr; // Killed
7779 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
7780 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
7781 sarL_rReg_63(src, cr); // sarq src, 63
7782 sarL_rReg_2(dst, cr); // sarq rdx, 2
7783 subL_rReg(dst, src, cr); // subl rdx, src
7784 %}
7785 %}
7787 //-----------------------------------------------------------------------------
7789 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
7790 rFlagsReg cr)
7791 %{
7792 match(Set rdx (ModI rax div));
7793 effect(KILL rax, KILL cr);
7795 ins_cost(300); // XXX
7796 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
7797 "jne,s normal\n\t"
7798 "xorl rdx, rdx\n\t"
7799 "cmpl $div, -1\n\t"
7800 "je,s done\n"
7801 "normal: cdql\n\t"
7802 "idivl $div\n"
7803 "done:" %}
7804 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7805 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7806 ins_pipe(ialu_reg_reg_alu0);
7807 %}
7809 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
7810 rFlagsReg cr)
7811 %{
7812 match(Set rdx (ModL rax div));
7813 effect(KILL rax, KILL cr);
7815 ins_cost(300); // XXX
7816 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
7817 "cmpq rax, rdx\n\t"
7818 "jne,s normal\n\t"
7819 "xorl rdx, rdx\n\t"
7820 "cmpq $div, -1\n\t"
7821 "je,s done\n"
7822 "normal: cdqq\n\t"
7823 "idivq $div\n"
7824 "done:" %}
7825 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7826 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7827 ins_pipe(ialu_reg_reg_alu0);
7828 %}
7830 // Integer Shift Instructions
7831 // Shift Left by one
7832 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
7833 %{
7834 match(Set dst (LShiftI dst shift));
7835 effect(KILL cr);
7837 format %{ "sall $dst, $shift" %}
7838 opcode(0xD1, 0x4); /* D1 /4 */
7839 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7840 ins_pipe(ialu_reg);
7841 %}
7843 // Shift Left by one
7844 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7845 %{
7846 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7847 effect(KILL cr);
7849 format %{ "sall $dst, $shift\t" %}
7850 opcode(0xD1, 0x4); /* D1 /4 */
7851 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7852 ins_pipe(ialu_mem_imm);
7853 %}
7855 // Shift Left by 8-bit immediate
7856 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
7857 %{
7858 match(Set dst (LShiftI dst shift));
7859 effect(KILL cr);
7861 format %{ "sall $dst, $shift" %}
7862 opcode(0xC1, 0x4); /* C1 /4 ib */
7863 ins_encode(reg_opc_imm(dst, shift));
7864 ins_pipe(ialu_reg);
7865 %}
7867 // Shift Left by 8-bit immediate
7868 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
7869 %{
7870 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7871 effect(KILL cr);
7873 format %{ "sall $dst, $shift" %}
7874 opcode(0xC1, 0x4); /* C1 /4 ib */
7875 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
7876 ins_pipe(ialu_mem_imm);
7877 %}
7879 // Shift Left by variable
7880 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
7881 %{
7882 match(Set dst (LShiftI dst shift));
7883 effect(KILL cr);
7885 format %{ "sall $dst, $shift" %}
7886 opcode(0xD3, 0x4); /* D3 /4 */
7887 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7888 ins_pipe(ialu_reg_reg);
7889 %}
7891 // Shift Left by variable
7892 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
7893 %{
7894 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7895 effect(KILL cr);
7897 format %{ "sall $dst, $shift" %}
7898 opcode(0xD3, 0x4); /* D3 /4 */
7899 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7900 ins_pipe(ialu_mem_reg);
7901 %}
7903 // Arithmetic shift right by one
7904 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
7905 %{
7906 match(Set dst (RShiftI dst shift));
7907 effect(KILL cr);
7909 format %{ "sarl $dst, $shift" %}
7910 opcode(0xD1, 0x7); /* D1 /7 */
7911 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7912 ins_pipe(ialu_reg);
7913 %}
7915 // Arithmetic shift right by one
7916 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7917 %{
7918 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7919 effect(KILL cr);
7921 format %{ "sarl $dst, $shift" %}
7922 opcode(0xD1, 0x7); /* D1 /7 */
7923 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7924 ins_pipe(ialu_mem_imm);
7925 %}
7927 // Arithmetic Shift Right by 8-bit immediate
7928 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
7929 %{
7930 match(Set dst (RShiftI dst shift));
7931 effect(KILL cr);
7933 format %{ "sarl $dst, $shift" %}
7934 opcode(0xC1, 0x7); /* C1 /7 ib */
7935 ins_encode(reg_opc_imm(dst, shift));
7936 ins_pipe(ialu_mem_imm);
7937 %}
7939 // Arithmetic Shift Right by 8-bit immediate
7940 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
7941 %{
7942 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7943 effect(KILL cr);
7945 format %{ "sarl $dst, $shift" %}
7946 opcode(0xC1, 0x7); /* C1 /7 ib */
7947 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
7948 ins_pipe(ialu_mem_imm);
7949 %}
7951 // Arithmetic Shift Right by variable
7952 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
7953 %{
7954 match(Set dst (RShiftI dst shift));
7955 effect(KILL cr);
7957 format %{ "sarl $dst, $shift" %}
7958 opcode(0xD3, 0x7); /* D3 /7 */
7959 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7960 ins_pipe(ialu_reg_reg);
7961 %}
7963 // Arithmetic Shift Right by variable
7964 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
7965 %{
7966 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7967 effect(KILL cr);
7969 format %{ "sarl $dst, $shift" %}
7970 opcode(0xD3, 0x7); /* D3 /7 */
7971 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7972 ins_pipe(ialu_mem_reg);
7973 %}
7975 // Logical shift right by one
7976 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
7977 %{
7978 match(Set dst (URShiftI dst shift));
7979 effect(KILL cr);
7981 format %{ "shrl $dst, $shift" %}
7982 opcode(0xD1, 0x5); /* D1 /5 */
7983 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7984 ins_pipe(ialu_reg);
7985 %}
7987 // Logical shift right by one
7988 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7989 %{
7990 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
7991 effect(KILL cr);
7993 format %{ "shrl $dst, $shift" %}
7994 opcode(0xD1, 0x5); /* D1 /5 */
7995 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7996 ins_pipe(ialu_mem_imm);
7997 %}
7999 // Logical Shift Right by 8-bit immediate
8000 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8001 %{
8002 match(Set dst (URShiftI dst shift));
8003 effect(KILL cr);
8005 format %{ "shrl $dst, $shift" %}
8006 opcode(0xC1, 0x5); /* C1 /5 ib */
8007 ins_encode(reg_opc_imm(dst, shift));
8008 ins_pipe(ialu_reg);
8009 %}
8011 // Logical Shift Right by 8-bit immediate
8012 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8013 %{
8014 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8015 effect(KILL cr);
8017 format %{ "shrl $dst, $shift" %}
8018 opcode(0xC1, 0x5); /* C1 /5 ib */
8019 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8020 ins_pipe(ialu_mem_imm);
8021 %}
8023 // Logical Shift Right by variable
8024 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8025 %{
8026 match(Set dst (URShiftI dst shift));
8027 effect(KILL cr);
8029 format %{ "shrl $dst, $shift" %}
8030 opcode(0xD3, 0x5); /* D3 /5 */
8031 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8032 ins_pipe(ialu_reg_reg);
8033 %}
8035 // Logical Shift Right by variable
8036 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8037 %{
8038 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8039 effect(KILL cr);
8041 format %{ "shrl $dst, $shift" %}
8042 opcode(0xD3, 0x5); /* D3 /5 */
8043 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8044 ins_pipe(ialu_mem_reg);
8045 %}
8047 // Long Shift Instructions
8048 // Shift Left by one
8049 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8050 %{
8051 match(Set dst (LShiftL dst shift));
8052 effect(KILL cr);
8054 format %{ "salq $dst, $shift" %}
8055 opcode(0xD1, 0x4); /* D1 /4 */
8056 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8057 ins_pipe(ialu_reg);
8058 %}
8060 // Shift Left by one
8061 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8062 %{
8063 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8064 effect(KILL cr);
8066 format %{ "salq $dst, $shift" %}
8067 opcode(0xD1, 0x4); /* D1 /4 */
8068 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8069 ins_pipe(ialu_mem_imm);
8070 %}
8072 // Shift Left by 8-bit immediate
8073 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8074 %{
8075 match(Set dst (LShiftL dst shift));
8076 effect(KILL cr);
8078 format %{ "salq $dst, $shift" %}
8079 opcode(0xC1, 0x4); /* C1 /4 ib */
8080 ins_encode(reg_opc_imm_wide(dst, shift));
8081 ins_pipe(ialu_reg);
8082 %}
8084 // Shift Left by 8-bit immediate
8085 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8086 %{
8087 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8088 effect(KILL cr);
8090 format %{ "salq $dst, $shift" %}
8091 opcode(0xC1, 0x4); /* C1 /4 ib */
8092 ins_encode(REX_mem_wide(dst), OpcP,
8093 RM_opc_mem(secondary, dst), Con8or32(shift));
8094 ins_pipe(ialu_mem_imm);
8095 %}
8097 // Shift Left by variable
8098 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8099 %{
8100 match(Set dst (LShiftL dst shift));
8101 effect(KILL cr);
8103 format %{ "salq $dst, $shift" %}
8104 opcode(0xD3, 0x4); /* D3 /4 */
8105 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8106 ins_pipe(ialu_reg_reg);
8107 %}
8109 // Shift Left by variable
8110 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8111 %{
8112 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8113 effect(KILL cr);
8115 format %{ "salq $dst, $shift" %}
8116 opcode(0xD3, 0x4); /* D3 /4 */
8117 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8118 ins_pipe(ialu_mem_reg);
8119 %}
8121 // Arithmetic shift right by one
8122 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8123 %{
8124 match(Set dst (RShiftL dst shift));
8125 effect(KILL cr);
8127 format %{ "sarq $dst, $shift" %}
8128 opcode(0xD1, 0x7); /* D1 /7 */
8129 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8130 ins_pipe(ialu_reg);
8131 %}
8133 // Arithmetic shift right by one
8134 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8135 %{
8136 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8137 effect(KILL cr);
8139 format %{ "sarq $dst, $shift" %}
8140 opcode(0xD1, 0x7); /* D1 /7 */
8141 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8142 ins_pipe(ialu_mem_imm);
8143 %}
8145 // Arithmetic Shift Right by 8-bit immediate
8146 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8147 %{
8148 match(Set dst (RShiftL dst shift));
8149 effect(KILL cr);
8151 format %{ "sarq $dst, $shift" %}
8152 opcode(0xC1, 0x7); /* C1 /7 ib */
8153 ins_encode(reg_opc_imm_wide(dst, shift));
8154 ins_pipe(ialu_mem_imm);
8155 %}
8157 // Arithmetic Shift Right by 8-bit immediate
8158 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8159 %{
8160 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8161 effect(KILL cr);
8163 format %{ "sarq $dst, $shift" %}
8164 opcode(0xC1, 0x7); /* C1 /7 ib */
8165 ins_encode(REX_mem_wide(dst), OpcP,
8166 RM_opc_mem(secondary, dst), Con8or32(shift));
8167 ins_pipe(ialu_mem_imm);
8168 %}
8170 // Arithmetic Shift Right by variable
8171 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8172 %{
8173 match(Set dst (RShiftL dst shift));
8174 effect(KILL cr);
8176 format %{ "sarq $dst, $shift" %}
8177 opcode(0xD3, 0x7); /* D3 /7 */
8178 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8179 ins_pipe(ialu_reg_reg);
8180 %}
8182 // Arithmetic Shift Right by variable
8183 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8184 %{
8185 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8186 effect(KILL cr);
8188 format %{ "sarq $dst, $shift" %}
8189 opcode(0xD3, 0x7); /* D3 /7 */
8190 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8191 ins_pipe(ialu_mem_reg);
8192 %}
8194 // Logical shift right by one
8195 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8196 %{
8197 match(Set dst (URShiftL dst shift));
8198 effect(KILL cr);
8200 format %{ "shrq $dst, $shift" %}
8201 opcode(0xD1, 0x5); /* D1 /5 */
8202 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8203 ins_pipe(ialu_reg);
8204 %}
8206 // Logical shift right by one
8207 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8208 %{
8209 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8210 effect(KILL cr);
8212 format %{ "shrq $dst, $shift" %}
8213 opcode(0xD1, 0x5); /* D1 /5 */
8214 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8215 ins_pipe(ialu_mem_imm);
8216 %}
8218 // Logical Shift Right by 8-bit immediate
8219 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8220 %{
8221 match(Set dst (URShiftL dst shift));
8222 effect(KILL cr);
8224 format %{ "shrq $dst, $shift" %}
8225 opcode(0xC1, 0x5); /* C1 /5 ib */
8226 ins_encode(reg_opc_imm_wide(dst, shift));
8227 ins_pipe(ialu_reg);
8228 %}
8231 // Logical Shift Right by 8-bit immediate
8232 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8233 %{
8234 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8235 effect(KILL cr);
8237 format %{ "shrq $dst, $shift" %}
8238 opcode(0xC1, 0x5); /* C1 /5 ib */
8239 ins_encode(REX_mem_wide(dst), OpcP,
8240 RM_opc_mem(secondary, dst), Con8or32(shift));
8241 ins_pipe(ialu_mem_imm);
8242 %}
8244 // Logical Shift Right by variable
8245 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8246 %{
8247 match(Set dst (URShiftL dst shift));
8248 effect(KILL cr);
8250 format %{ "shrq $dst, $shift" %}
8251 opcode(0xD3, 0x5); /* D3 /5 */
8252 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8253 ins_pipe(ialu_reg_reg);
8254 %}
8256 // Logical Shift Right by variable
8257 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8258 %{
8259 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8260 effect(KILL cr);
8262 format %{ "shrq $dst, $shift" %}
8263 opcode(0xD3, 0x5); /* D3 /5 */
8264 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8265 ins_pipe(ialu_mem_reg);
8266 %}
8268 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8269 // This idiom is used by the compiler for the i2b bytecode.
8270 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8271 %{
8272 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8274 format %{ "movsbl $dst, $src\t# i2b" %}
8275 opcode(0x0F, 0xBE);
8276 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8277 ins_pipe(ialu_reg_reg);
8278 %}
8280 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8281 // This idiom is used by the compiler the i2s bytecode.
8282 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8283 %{
8284 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8286 format %{ "movswl $dst, $src\t# i2s" %}
8287 opcode(0x0F, 0xBF);
8288 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8289 ins_pipe(ialu_reg_reg);
8290 %}
8292 // ROL/ROR instructions
8294 // ROL expand
8295 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8296 effect(KILL cr, USE_DEF dst);
8298 format %{ "roll $dst" %}
8299 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8300 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8301 ins_pipe(ialu_reg);
8302 %}
8304 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8305 effect(USE_DEF dst, USE shift, KILL cr);
8307 format %{ "roll $dst, $shift" %}
8308 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8309 ins_encode( reg_opc_imm(dst, shift) );
8310 ins_pipe(ialu_reg);
8311 %}
8313 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8314 %{
8315 effect(USE_DEF dst, USE shift, KILL cr);
8317 format %{ "roll $dst, $shift" %}
8318 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8319 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8320 ins_pipe(ialu_reg_reg);
8321 %}
8322 // end of ROL expand
8324 // Rotate Left by one
8325 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8326 %{
8327 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8329 expand %{
8330 rolI_rReg_imm1(dst, cr);
8331 %}
8332 %}
8334 // Rotate Left by 8-bit immediate
8335 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8336 %{
8337 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8338 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8340 expand %{
8341 rolI_rReg_imm8(dst, lshift, cr);
8342 %}
8343 %}
8345 // Rotate Left by variable
8346 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8347 %{
8348 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8350 expand %{
8351 rolI_rReg_CL(dst, shift, cr);
8352 %}
8353 %}
8355 // Rotate Left by variable
8356 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8357 %{
8358 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8360 expand %{
8361 rolI_rReg_CL(dst, shift, cr);
8362 %}
8363 %}
8365 // ROR expand
8366 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8367 %{
8368 effect(USE_DEF dst, KILL cr);
8370 format %{ "rorl $dst" %}
8371 opcode(0xD1, 0x1); /* D1 /1 */
8372 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8373 ins_pipe(ialu_reg);
8374 %}
8376 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8377 %{
8378 effect(USE_DEF dst, USE shift, KILL cr);
8380 format %{ "rorl $dst, $shift" %}
8381 opcode(0xC1, 0x1); /* C1 /1 ib */
8382 ins_encode(reg_opc_imm(dst, shift));
8383 ins_pipe(ialu_reg);
8384 %}
8386 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8387 %{
8388 effect(USE_DEF dst, USE shift, KILL cr);
8390 format %{ "rorl $dst, $shift" %}
8391 opcode(0xD3, 0x1); /* D3 /1 */
8392 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8393 ins_pipe(ialu_reg_reg);
8394 %}
8395 // end of ROR expand
8397 // Rotate Right by one
8398 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8399 %{
8400 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8402 expand %{
8403 rorI_rReg_imm1(dst, cr);
8404 %}
8405 %}
8407 // Rotate Right by 8-bit immediate
8408 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8409 %{
8410 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8411 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8413 expand %{
8414 rorI_rReg_imm8(dst, rshift, cr);
8415 %}
8416 %}
8418 // Rotate Right by variable
8419 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8420 %{
8421 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8423 expand %{
8424 rorI_rReg_CL(dst, shift, cr);
8425 %}
8426 %}
8428 // Rotate Right by variable
8429 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8430 %{
8431 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8433 expand %{
8434 rorI_rReg_CL(dst, shift, cr);
8435 %}
8436 %}
8438 // for long rotate
8439 // ROL expand
8440 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
8441 effect(USE_DEF dst, KILL cr);
8443 format %{ "rolq $dst" %}
8444 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8445 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8446 ins_pipe(ialu_reg);
8447 %}
8449 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
8450 effect(USE_DEF dst, USE shift, KILL cr);
8452 format %{ "rolq $dst, $shift" %}
8453 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8454 ins_encode( reg_opc_imm_wide(dst, shift) );
8455 ins_pipe(ialu_reg);
8456 %}
8458 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8459 %{
8460 effect(USE_DEF dst, USE shift, KILL cr);
8462 format %{ "rolq $dst, $shift" %}
8463 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8464 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8465 ins_pipe(ialu_reg_reg);
8466 %}
8467 // end of ROL expand
8469 // Rotate Left by one
8470 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8471 %{
8472 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8474 expand %{
8475 rolL_rReg_imm1(dst, cr);
8476 %}
8477 %}
8479 // Rotate Left by 8-bit immediate
8480 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8481 %{
8482 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8483 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8485 expand %{
8486 rolL_rReg_imm8(dst, lshift, cr);
8487 %}
8488 %}
8490 // Rotate Left by variable
8491 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8492 %{
8493 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
8495 expand %{
8496 rolL_rReg_CL(dst, shift, cr);
8497 %}
8498 %}
8500 // Rotate Left by variable
8501 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8502 %{
8503 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
8505 expand %{
8506 rolL_rReg_CL(dst, shift, cr);
8507 %}
8508 %}
8510 // ROR expand
8511 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
8512 %{
8513 effect(USE_DEF dst, KILL cr);
8515 format %{ "rorq $dst" %}
8516 opcode(0xD1, 0x1); /* D1 /1 */
8517 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8518 ins_pipe(ialu_reg);
8519 %}
8521 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
8522 %{
8523 effect(USE_DEF dst, USE shift, KILL cr);
8525 format %{ "rorq $dst, $shift" %}
8526 opcode(0xC1, 0x1); /* C1 /1 ib */
8527 ins_encode(reg_opc_imm_wide(dst, shift));
8528 ins_pipe(ialu_reg);
8529 %}
8531 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8532 %{
8533 effect(USE_DEF dst, USE shift, KILL cr);
8535 format %{ "rorq $dst, $shift" %}
8536 opcode(0xD3, 0x1); /* D3 /1 */
8537 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8538 ins_pipe(ialu_reg_reg);
8539 %}
8540 // end of ROR expand
8542 // Rotate Right by one
8543 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8544 %{
8545 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8547 expand %{
8548 rorL_rReg_imm1(dst, cr);
8549 %}
8550 %}
8552 // Rotate Right by 8-bit immediate
8553 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8554 %{
8555 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8556 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8558 expand %{
8559 rorL_rReg_imm8(dst, rshift, cr);
8560 %}
8561 %}
8563 // Rotate Right by variable
8564 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8565 %{
8566 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
8568 expand %{
8569 rorL_rReg_CL(dst, shift, cr);
8570 %}
8571 %}
8573 // Rotate Right by variable
8574 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8575 %{
8576 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
8578 expand %{
8579 rorL_rReg_CL(dst, shift, cr);
8580 %}
8581 %}
8583 // Logical Instructions
8585 // Integer Logical Instructions
8587 // And Instructions
8588 // And Register with Register
8589 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8590 %{
8591 match(Set dst (AndI dst src));
8592 effect(KILL cr);
8594 format %{ "andl $dst, $src\t# int" %}
8595 opcode(0x23);
8596 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8597 ins_pipe(ialu_reg_reg);
8598 %}
8600 // And Register with Immediate 255
8601 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
8602 %{
8603 match(Set dst (AndI dst src));
8605 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
8606 opcode(0x0F, 0xB6);
8607 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8608 ins_pipe(ialu_reg);
8609 %}
8611 // And Register with Immediate 255 and promote to long
8612 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
8613 %{
8614 match(Set dst (ConvI2L (AndI src mask)));
8616 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
8617 opcode(0x0F, 0xB6);
8618 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8619 ins_pipe(ialu_reg);
8620 %}
8622 // And Register with Immediate 65535
8623 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
8624 %{
8625 match(Set dst (AndI dst src));
8627 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
8628 opcode(0x0F, 0xB7);
8629 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8630 ins_pipe(ialu_reg);
8631 %}
8633 // And Register with Immediate 65535 and promote to long
8634 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
8635 %{
8636 match(Set dst (ConvI2L (AndI src mask)));
8638 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
8639 opcode(0x0F, 0xB7);
8640 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8641 ins_pipe(ialu_reg);
8642 %}
8644 // And Register with Immediate
8645 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8646 %{
8647 match(Set dst (AndI dst src));
8648 effect(KILL cr);
8650 format %{ "andl $dst, $src\t# int" %}
8651 opcode(0x81, 0x04); /* Opcode 81 /4 */
8652 ins_encode(OpcSErm(dst, src), Con8or32(src));
8653 ins_pipe(ialu_reg);
8654 %}
8656 // And Register with Memory
8657 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8658 %{
8659 match(Set dst (AndI dst (LoadI src)));
8660 effect(KILL cr);
8662 ins_cost(125);
8663 format %{ "andl $dst, $src\t# int" %}
8664 opcode(0x23);
8665 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8666 ins_pipe(ialu_reg_mem);
8667 %}
8669 // And Memory with Register
8670 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8671 %{
8672 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8673 effect(KILL cr);
8675 ins_cost(150);
8676 format %{ "andl $dst, $src\t# int" %}
8677 opcode(0x21); /* Opcode 21 /r */
8678 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8679 ins_pipe(ialu_mem_reg);
8680 %}
8682 // And Memory with Immediate
8683 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
8684 %{
8685 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8686 effect(KILL cr);
8688 ins_cost(125);
8689 format %{ "andl $dst, $src\t# int" %}
8690 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8691 ins_encode(REX_mem(dst), OpcSE(src),
8692 RM_opc_mem(secondary, dst), Con8or32(src));
8693 ins_pipe(ialu_mem_imm);
8694 %}
8696 // Or Instructions
8697 // Or Register with Register
8698 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8699 %{
8700 match(Set dst (OrI dst src));
8701 effect(KILL cr);
8703 format %{ "orl $dst, $src\t# int" %}
8704 opcode(0x0B);
8705 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8706 ins_pipe(ialu_reg_reg);
8707 %}
8709 // Or Register with Immediate
8710 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8711 %{
8712 match(Set dst (OrI dst src));
8713 effect(KILL cr);
8715 format %{ "orl $dst, $src\t# int" %}
8716 opcode(0x81, 0x01); /* Opcode 81 /1 id */
8717 ins_encode(OpcSErm(dst, src), Con8or32(src));
8718 ins_pipe(ialu_reg);
8719 %}
8721 // Or Register with Memory
8722 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8723 %{
8724 match(Set dst (OrI dst (LoadI src)));
8725 effect(KILL cr);
8727 ins_cost(125);
8728 format %{ "orl $dst, $src\t# int" %}
8729 opcode(0x0B);
8730 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8731 ins_pipe(ialu_reg_mem);
8732 %}
8734 // Or Memory with Register
8735 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8736 %{
8737 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8738 effect(KILL cr);
8740 ins_cost(150);
8741 format %{ "orl $dst, $src\t# int" %}
8742 opcode(0x09); /* Opcode 09 /r */
8743 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8744 ins_pipe(ialu_mem_reg);
8745 %}
8747 // Or Memory with Immediate
8748 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
8749 %{
8750 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8751 effect(KILL cr);
8753 ins_cost(125);
8754 format %{ "orl $dst, $src\t# int" %}
8755 opcode(0x81, 0x1); /* Opcode 81 /1 id */
8756 ins_encode(REX_mem(dst), OpcSE(src),
8757 RM_opc_mem(secondary, dst), Con8or32(src));
8758 ins_pipe(ialu_mem_imm);
8759 %}
8761 // Xor Instructions
8762 // Xor Register with Register
8763 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8764 %{
8765 match(Set dst (XorI dst src));
8766 effect(KILL cr);
8768 format %{ "xorl $dst, $src\t# int" %}
8769 opcode(0x33);
8770 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8771 ins_pipe(ialu_reg_reg);
8772 %}
8774 // Xor Register with Immediate -1
8775 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
8776 match(Set dst (XorI dst imm));
8778 format %{ "not $dst" %}
8779 ins_encode %{
8780 __ notl($dst$$Register);
8781 %}
8782 ins_pipe(ialu_reg);
8783 %}
8785 // Xor Register with Immediate
8786 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8787 %{
8788 match(Set dst (XorI dst src));
8789 effect(KILL cr);
8791 format %{ "xorl $dst, $src\t# int" %}
8792 opcode(0x81, 0x06); /* Opcode 81 /6 id */
8793 ins_encode(OpcSErm(dst, src), Con8or32(src));
8794 ins_pipe(ialu_reg);
8795 %}
8797 // Xor Register with Memory
8798 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8799 %{
8800 match(Set dst (XorI dst (LoadI src)));
8801 effect(KILL cr);
8803 ins_cost(125);
8804 format %{ "xorl $dst, $src\t# int" %}
8805 opcode(0x33);
8806 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8807 ins_pipe(ialu_reg_mem);
8808 %}
8810 // Xor Memory with Register
8811 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8812 %{
8813 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8814 effect(KILL cr);
8816 ins_cost(150);
8817 format %{ "xorl $dst, $src\t# int" %}
8818 opcode(0x31); /* Opcode 31 /r */
8819 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8820 ins_pipe(ialu_mem_reg);
8821 %}
8823 // Xor Memory with Immediate
8824 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
8825 %{
8826 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8827 effect(KILL cr);
8829 ins_cost(125);
8830 format %{ "xorl $dst, $src\t# int" %}
8831 opcode(0x81, 0x6); /* Opcode 81 /6 id */
8832 ins_encode(REX_mem(dst), OpcSE(src),
8833 RM_opc_mem(secondary, dst), Con8or32(src));
8834 ins_pipe(ialu_mem_imm);
8835 %}
8838 // Long Logical Instructions
8840 // And Instructions
8841 // And Register with Register
8842 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8843 %{
8844 match(Set dst (AndL dst src));
8845 effect(KILL cr);
8847 format %{ "andq $dst, $src\t# long" %}
8848 opcode(0x23);
8849 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8850 ins_pipe(ialu_reg_reg);
8851 %}
8853 // And Register with Immediate 255
8854 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
8855 %{
8856 match(Set dst (AndL dst src));
8858 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
8859 opcode(0x0F, 0xB6);
8860 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8861 ins_pipe(ialu_reg);
8862 %}
8864 // And Register with Immediate 65535
8865 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
8866 %{
8867 match(Set dst (AndL dst src));
8869 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
8870 opcode(0x0F, 0xB7);
8871 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8872 ins_pipe(ialu_reg);
8873 %}
8875 // And Register with Immediate
8876 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
8877 %{
8878 match(Set dst (AndL dst src));
8879 effect(KILL cr);
8881 format %{ "andq $dst, $src\t# long" %}
8882 opcode(0x81, 0x04); /* Opcode 81 /4 */
8883 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8884 ins_pipe(ialu_reg);
8885 %}
8887 // And Register with Memory
8888 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8889 %{
8890 match(Set dst (AndL dst (LoadL src)));
8891 effect(KILL cr);
8893 ins_cost(125);
8894 format %{ "andq $dst, $src\t# long" %}
8895 opcode(0x23);
8896 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8897 ins_pipe(ialu_reg_mem);
8898 %}
8900 // And Memory with Register
8901 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8902 %{
8903 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
8904 effect(KILL cr);
8906 ins_cost(150);
8907 format %{ "andq $dst, $src\t# long" %}
8908 opcode(0x21); /* Opcode 21 /r */
8909 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8910 ins_pipe(ialu_mem_reg);
8911 %}
8913 // And Memory with Immediate
8914 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8915 %{
8916 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
8917 effect(KILL cr);
8919 ins_cost(125);
8920 format %{ "andq $dst, $src\t# long" %}
8921 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8922 ins_encode(REX_mem_wide(dst), OpcSE(src),
8923 RM_opc_mem(secondary, dst), Con8or32(src));
8924 ins_pipe(ialu_mem_imm);
8925 %}
8927 // Or Instructions
8928 // Or Register with Register
8929 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8930 %{
8931 match(Set dst (OrL dst src));
8932 effect(KILL cr);
8934 format %{ "orq $dst, $src\t# long" %}
8935 opcode(0x0B);
8936 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8937 ins_pipe(ialu_reg_reg);
8938 %}
8940 // Use any_RegP to match R15 (TLS register) without spilling.
8941 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
8942 match(Set dst (OrL dst (CastP2X src)));
8943 effect(KILL cr);
8945 format %{ "orq $dst, $src\t# long" %}
8946 opcode(0x0B);
8947 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8948 ins_pipe(ialu_reg_reg);
8949 %}
8952 // Or Register with Immediate
8953 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
8954 %{
8955 match(Set dst (OrL dst src));
8956 effect(KILL cr);
8958 format %{ "orq $dst, $src\t# long" %}
8959 opcode(0x81, 0x01); /* Opcode 81 /1 id */
8960 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8961 ins_pipe(ialu_reg);
8962 %}
8964 // Or Register with Memory
8965 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8966 %{
8967 match(Set dst (OrL dst (LoadL src)));
8968 effect(KILL cr);
8970 ins_cost(125);
8971 format %{ "orq $dst, $src\t# long" %}
8972 opcode(0x0B);
8973 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8974 ins_pipe(ialu_reg_mem);
8975 %}
8977 // Or Memory with Register
8978 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8979 %{
8980 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
8981 effect(KILL cr);
8983 ins_cost(150);
8984 format %{ "orq $dst, $src\t# long" %}
8985 opcode(0x09); /* Opcode 09 /r */
8986 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8987 ins_pipe(ialu_mem_reg);
8988 %}
8990 // Or Memory with Immediate
8991 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8992 %{
8993 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
8994 effect(KILL cr);
8996 ins_cost(125);
8997 format %{ "orq $dst, $src\t# long" %}
8998 opcode(0x81, 0x1); /* Opcode 81 /1 id */
8999 ins_encode(REX_mem_wide(dst), OpcSE(src),
9000 RM_opc_mem(secondary, dst), Con8or32(src));
9001 ins_pipe(ialu_mem_imm);
9002 %}
9004 // Xor Instructions
9005 // Xor Register with Register
9006 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9007 %{
9008 match(Set dst (XorL dst src));
9009 effect(KILL cr);
9011 format %{ "xorq $dst, $src\t# long" %}
9012 opcode(0x33);
9013 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9014 ins_pipe(ialu_reg_reg);
9015 %}
9017 // Xor Register with Immediate -1
9018 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9019 match(Set dst (XorL dst imm));
9021 format %{ "notq $dst" %}
9022 ins_encode %{
9023 __ notq($dst$$Register);
9024 %}
9025 ins_pipe(ialu_reg);
9026 %}
9028 // Xor Register with Immediate
9029 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9030 %{
9031 match(Set dst (XorL dst src));
9032 effect(KILL cr);
9034 format %{ "xorq $dst, $src\t# long" %}
9035 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9036 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9037 ins_pipe(ialu_reg);
9038 %}
9040 // Xor Register with Memory
9041 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9042 %{
9043 match(Set dst (XorL dst (LoadL src)));
9044 effect(KILL cr);
9046 ins_cost(125);
9047 format %{ "xorq $dst, $src\t# long" %}
9048 opcode(0x33);
9049 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9050 ins_pipe(ialu_reg_mem);
9051 %}
9053 // Xor Memory with Register
9054 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9055 %{
9056 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9057 effect(KILL cr);
9059 ins_cost(150);
9060 format %{ "xorq $dst, $src\t# long" %}
9061 opcode(0x31); /* Opcode 31 /r */
9062 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9063 ins_pipe(ialu_mem_reg);
9064 %}
9066 // Xor Memory with Immediate
9067 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9068 %{
9069 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9070 effect(KILL cr);
9072 ins_cost(125);
9073 format %{ "xorq $dst, $src\t# long" %}
9074 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9075 ins_encode(REX_mem_wide(dst), OpcSE(src),
9076 RM_opc_mem(secondary, dst), Con8or32(src));
9077 ins_pipe(ialu_mem_imm);
9078 %}
9080 // Convert Int to Boolean
9081 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9082 %{
9083 match(Set dst (Conv2B src));
9084 effect(KILL cr);
9086 format %{ "testl $src, $src\t# ci2b\n\t"
9087 "setnz $dst\n\t"
9088 "movzbl $dst, $dst" %}
9089 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9090 setNZ_reg(dst),
9091 REX_reg_breg(dst, dst), // movzbl
9092 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9093 ins_pipe(pipe_slow); // XXX
9094 %}
9096 // Convert Pointer to Boolean
9097 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9098 %{
9099 match(Set dst (Conv2B src));
9100 effect(KILL cr);
9102 format %{ "testq $src, $src\t# cp2b\n\t"
9103 "setnz $dst\n\t"
9104 "movzbl $dst, $dst" %}
9105 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9106 setNZ_reg(dst),
9107 REX_reg_breg(dst, dst), // movzbl
9108 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9109 ins_pipe(pipe_slow); // XXX
9110 %}
9112 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9113 %{
9114 match(Set dst (CmpLTMask p q));
9115 effect(KILL cr);
9117 ins_cost(400); // XXX
9118 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9119 "setlt $dst\n\t"
9120 "movzbl $dst, $dst\n\t"
9121 "negl $dst" %}
9122 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9123 setLT_reg(dst),
9124 REX_reg_breg(dst, dst), // movzbl
9125 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9126 neg_reg(dst));
9127 ins_pipe(pipe_slow);
9128 %}
9130 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9131 %{
9132 match(Set dst (CmpLTMask dst zero));
9133 effect(KILL cr);
9135 ins_cost(100); // XXX
9136 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9137 opcode(0xC1, 0x7); /* C1 /7 ib */
9138 ins_encode(reg_opc_imm(dst, 0x1F));
9139 ins_pipe(ialu_reg);
9140 %}
9143 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rRegI tmp, rFlagsReg cr)
9144 %{
9145 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9146 effect(TEMP tmp, KILL cr);
9148 ins_cost(400); // XXX
9149 format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t"
9150 "sbbl $tmp, $tmp\n\t"
9151 "andl $tmp, $y\n\t"
9152 "addl $p, $tmp" %}
9153 ins_encode %{
9154 Register Rp = $p$$Register;
9155 Register Rq = $q$$Register;
9156 Register Ry = $y$$Register;
9157 Register Rt = $tmp$$Register;
9158 __ subl(Rp, Rq);
9159 __ sbbl(Rt, Rt);
9160 __ andl(Rt, Ry);
9161 __ addl(Rp, Rt);
9162 %}
9163 ins_pipe(pipe_cmplt);
9164 %}
9166 //---------- FP Instructions------------------------------------------------
9168 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9169 %{
9170 match(Set cr (CmpF src1 src2));
9172 ins_cost(145);
9173 format %{ "ucomiss $src1, $src2\n\t"
9174 "jnp,s exit\n\t"
9175 "pushfq\t# saw NaN, set CF\n\t"
9176 "andq [rsp], #0xffffff2b\n\t"
9177 "popfq\n"
9178 "exit:" %}
9179 ins_encode %{
9180 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9181 emit_cmpfp_fixup(_masm);
9182 %}
9183 ins_pipe(pipe_slow);
9184 %}
9186 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
9187 match(Set cr (CmpF src1 src2));
9189 ins_cost(100);
9190 format %{ "ucomiss $src1, $src2" %}
9191 ins_encode %{
9192 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9193 %}
9194 ins_pipe(pipe_slow);
9195 %}
9197 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
9198 %{
9199 match(Set cr (CmpF src1 (LoadF src2)));
9201 ins_cost(145);
9202 format %{ "ucomiss $src1, $src2\n\t"
9203 "jnp,s exit\n\t"
9204 "pushfq\t# saw NaN, set CF\n\t"
9205 "andq [rsp], #0xffffff2b\n\t"
9206 "popfq\n"
9207 "exit:" %}
9208 ins_encode %{
9209 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9210 emit_cmpfp_fixup(_masm);
9211 %}
9212 ins_pipe(pipe_slow);
9213 %}
9215 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
9216 match(Set cr (CmpF src1 (LoadF src2)));
9218 ins_cost(100);
9219 format %{ "ucomiss $src1, $src2" %}
9220 ins_encode %{
9221 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9222 %}
9223 ins_pipe(pipe_slow);
9224 %}
9226 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
9227 match(Set cr (CmpF src con));
9229 ins_cost(145);
9230 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9231 "jnp,s exit\n\t"
9232 "pushfq\t# saw NaN, set CF\n\t"
9233 "andq [rsp], #0xffffff2b\n\t"
9234 "popfq\n"
9235 "exit:" %}
9236 ins_encode %{
9237 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9238 emit_cmpfp_fixup(_masm);
9239 %}
9240 ins_pipe(pipe_slow);
9241 %}
9243 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
9244 match(Set cr (CmpF src con));
9245 ins_cost(100);
9246 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
9247 ins_encode %{
9248 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9249 %}
9250 ins_pipe(pipe_slow);
9251 %}
9253 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9254 %{
9255 match(Set cr (CmpD src1 src2));
9257 ins_cost(145);
9258 format %{ "ucomisd $src1, $src2\n\t"
9259 "jnp,s exit\n\t"
9260 "pushfq\t# saw NaN, set CF\n\t"
9261 "andq [rsp], #0xffffff2b\n\t"
9262 "popfq\n"
9263 "exit:" %}
9264 ins_encode %{
9265 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9266 emit_cmpfp_fixup(_masm);
9267 %}
9268 ins_pipe(pipe_slow);
9269 %}
9271 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
9272 match(Set cr (CmpD src1 src2));
9274 ins_cost(100);
9275 format %{ "ucomisd $src1, $src2 test" %}
9276 ins_encode %{
9277 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9278 %}
9279 ins_pipe(pipe_slow);
9280 %}
9282 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
9283 %{
9284 match(Set cr (CmpD src1 (LoadD src2)));
9286 ins_cost(145);
9287 format %{ "ucomisd $src1, $src2\n\t"
9288 "jnp,s exit\n\t"
9289 "pushfq\t# saw NaN, set CF\n\t"
9290 "andq [rsp], #0xffffff2b\n\t"
9291 "popfq\n"
9292 "exit:" %}
9293 ins_encode %{
9294 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9295 emit_cmpfp_fixup(_masm);
9296 %}
9297 ins_pipe(pipe_slow);
9298 %}
9300 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
9301 match(Set cr (CmpD src1 (LoadD src2)));
9303 ins_cost(100);
9304 format %{ "ucomisd $src1, $src2" %}
9305 ins_encode %{
9306 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9307 %}
9308 ins_pipe(pipe_slow);
9309 %}
9311 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
9312 match(Set cr (CmpD src con));
9314 ins_cost(145);
9315 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9316 "jnp,s exit\n\t"
9317 "pushfq\t# saw NaN, set CF\n\t"
9318 "andq [rsp], #0xffffff2b\n\t"
9319 "popfq\n"
9320 "exit:" %}
9321 ins_encode %{
9322 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9323 emit_cmpfp_fixup(_masm);
9324 %}
9325 ins_pipe(pipe_slow);
9326 %}
9328 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
9329 match(Set cr (CmpD src con));
9330 ins_cost(100);
9331 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
9332 ins_encode %{
9333 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9334 %}
9335 ins_pipe(pipe_slow);
9336 %}
9338 // Compare into -1,0,1
9339 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9340 %{
9341 match(Set dst (CmpF3 src1 src2));
9342 effect(KILL cr);
9344 ins_cost(275);
9345 format %{ "ucomiss $src1, $src2\n\t"
9346 "movl $dst, #-1\n\t"
9347 "jp,s done\n\t"
9348 "jb,s done\n\t"
9349 "setne $dst\n\t"
9350 "movzbl $dst, $dst\n"
9351 "done:" %}
9352 ins_encode %{
9353 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9354 emit_cmpfp3(_masm, $dst$$Register);
9355 %}
9356 ins_pipe(pipe_slow);
9357 %}
9359 // Compare into -1,0,1
9360 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
9361 %{
9362 match(Set dst (CmpF3 src1 (LoadF src2)));
9363 effect(KILL cr);
9365 ins_cost(275);
9366 format %{ "ucomiss $src1, $src2\n\t"
9367 "movl $dst, #-1\n\t"
9368 "jp,s done\n\t"
9369 "jb,s done\n\t"
9370 "setne $dst\n\t"
9371 "movzbl $dst, $dst\n"
9372 "done:" %}
9373 ins_encode %{
9374 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9375 emit_cmpfp3(_masm, $dst$$Register);
9376 %}
9377 ins_pipe(pipe_slow);
9378 %}
9380 // Compare into -1,0,1
9381 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
9382 match(Set dst (CmpF3 src con));
9383 effect(KILL cr);
9385 ins_cost(275);
9386 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9387 "movl $dst, #-1\n\t"
9388 "jp,s done\n\t"
9389 "jb,s done\n\t"
9390 "setne $dst\n\t"
9391 "movzbl $dst, $dst\n"
9392 "done:" %}
9393 ins_encode %{
9394 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9395 emit_cmpfp3(_masm, $dst$$Register);
9396 %}
9397 ins_pipe(pipe_slow);
9398 %}
9400 // Compare into -1,0,1
9401 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
9402 %{
9403 match(Set dst (CmpD3 src1 src2));
9404 effect(KILL cr);
9406 ins_cost(275);
9407 format %{ "ucomisd $src1, $src2\n\t"
9408 "movl $dst, #-1\n\t"
9409 "jp,s done\n\t"
9410 "jb,s done\n\t"
9411 "setne $dst\n\t"
9412 "movzbl $dst, $dst\n"
9413 "done:" %}
9414 ins_encode %{
9415 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9416 emit_cmpfp3(_masm, $dst$$Register);
9417 %}
9418 ins_pipe(pipe_slow);
9419 %}
9421 // Compare into -1,0,1
9422 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
9423 %{
9424 match(Set dst (CmpD3 src1 (LoadD src2)));
9425 effect(KILL cr);
9427 ins_cost(275);
9428 format %{ "ucomisd $src1, $src2\n\t"
9429 "movl $dst, #-1\n\t"
9430 "jp,s done\n\t"
9431 "jb,s done\n\t"
9432 "setne $dst\n\t"
9433 "movzbl $dst, $dst\n"
9434 "done:" %}
9435 ins_encode %{
9436 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9437 emit_cmpfp3(_masm, $dst$$Register);
9438 %}
9439 ins_pipe(pipe_slow);
9440 %}
9442 // Compare into -1,0,1
9443 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
9444 match(Set dst (CmpD3 src con));
9445 effect(KILL cr);
9447 ins_cost(275);
9448 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9449 "movl $dst, #-1\n\t"
9450 "jp,s done\n\t"
9451 "jb,s done\n\t"
9452 "setne $dst\n\t"
9453 "movzbl $dst, $dst\n"
9454 "done:" %}
9455 ins_encode %{
9456 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9457 emit_cmpfp3(_masm, $dst$$Register);
9458 %}
9459 ins_pipe(pipe_slow);
9460 %}
9462 // -----------Trig and Trancendental Instructions------------------------------
9463 instruct cosD_reg(regD dst) %{
9464 match(Set dst (CosD dst));
9466 format %{ "dcos $dst\n\t" %}
9467 opcode(0xD9, 0xFF);
9468 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9469 ins_pipe( pipe_slow );
9470 %}
9472 instruct sinD_reg(regD dst) %{
9473 match(Set dst (SinD dst));
9475 format %{ "dsin $dst\n\t" %}
9476 opcode(0xD9, 0xFE);
9477 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9478 ins_pipe( pipe_slow );
9479 %}
9481 instruct tanD_reg(regD dst) %{
9482 match(Set dst (TanD dst));
9484 format %{ "dtan $dst\n\t" %}
9485 ins_encode( Push_SrcXD(dst),
9486 Opcode(0xD9), Opcode(0xF2), //fptan
9487 Opcode(0xDD), Opcode(0xD8), //fstp st
9488 Push_ResultXD(dst) );
9489 ins_pipe( pipe_slow );
9490 %}
9492 instruct log10D_reg(regD dst) %{
9493 // The source and result Double operands in XMM registers
9494 match(Set dst (Log10D dst));
9495 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9496 // fyl2x ; compute log_10(2) * log_2(x)
9497 format %{ "fldlg2\t\t\t#Log10\n\t"
9498 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
9499 %}
9500 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
9501 Push_SrcXD(dst),
9502 Opcode(0xD9), Opcode(0xF1), // fyl2x
9503 Push_ResultXD(dst));
9505 ins_pipe( pipe_slow );
9506 %}
9508 instruct logD_reg(regD dst) %{
9509 // The source and result Double operands in XMM registers
9510 match(Set dst (LogD dst));
9511 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9512 // fyl2x ; compute log_e(2) * log_2(x)
9513 format %{ "fldln2\t\t\t#Log_e\n\t"
9514 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
9515 %}
9516 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9517 Push_SrcXD(dst),
9518 Opcode(0xD9), Opcode(0xF1), // fyl2x
9519 Push_ResultXD(dst));
9520 ins_pipe( pipe_slow );
9521 %}
9523 instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9524 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9525 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9526 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9527 ins_encode %{
9528 __ subptr(rsp, 8);
9529 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9530 __ fld_d(Address(rsp, 0));
9531 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9532 __ fld_d(Address(rsp, 0));
9533 __ fast_pow();
9534 __ fstp_d(Address(rsp, 0));
9535 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9536 __ addptr(rsp, 8);
9537 %}
9538 ins_pipe( pipe_slow );
9539 %}
9541 instruct expD_reg(regD dst, regD src, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9542 match(Set dst (ExpD src));
9543 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9544 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
9545 ins_encode %{
9546 __ subptr(rsp, 8);
9547 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9548 __ fld_d(Address(rsp, 0));
9549 __ fast_exp();
9550 __ fstp_d(Address(rsp, 0));
9551 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9552 __ addptr(rsp, 8);
9553 %}
9554 ins_pipe( pipe_slow );
9555 %}
9557 //----------Arithmetic Conversion Instructions---------------------------------
9559 instruct roundFloat_nop(regF dst)
9560 %{
9561 match(Set dst (RoundFloat dst));
9563 ins_cost(0);
9564 ins_encode();
9565 ins_pipe(empty);
9566 %}
9568 instruct roundDouble_nop(regD dst)
9569 %{
9570 match(Set dst (RoundDouble dst));
9572 ins_cost(0);
9573 ins_encode();
9574 ins_pipe(empty);
9575 %}
9577 instruct convF2D_reg_reg(regD dst, regF src)
9578 %{
9579 match(Set dst (ConvF2D src));
9581 format %{ "cvtss2sd $dst, $src" %}
9582 ins_encode %{
9583 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
9584 %}
9585 ins_pipe(pipe_slow); // XXX
9586 %}
9588 instruct convF2D_reg_mem(regD dst, memory src)
9589 %{
9590 match(Set dst (ConvF2D (LoadF src)));
9592 format %{ "cvtss2sd $dst, $src" %}
9593 ins_encode %{
9594 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
9595 %}
9596 ins_pipe(pipe_slow); // XXX
9597 %}
9599 instruct convD2F_reg_reg(regF dst, regD src)
9600 %{
9601 match(Set dst (ConvD2F src));
9603 format %{ "cvtsd2ss $dst, $src" %}
9604 ins_encode %{
9605 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
9606 %}
9607 ins_pipe(pipe_slow); // XXX
9608 %}
9610 instruct convD2F_reg_mem(regF dst, memory src)
9611 %{
9612 match(Set dst (ConvD2F (LoadD src)));
9614 format %{ "cvtsd2ss $dst, $src" %}
9615 ins_encode %{
9616 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
9617 %}
9618 ins_pipe(pipe_slow); // XXX
9619 %}
9621 // XXX do mem variants
9622 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
9623 %{
9624 match(Set dst (ConvF2I src));
9625 effect(KILL cr);
9627 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
9628 "cmpl $dst, #0x80000000\n\t"
9629 "jne,s done\n\t"
9630 "subq rsp, #8\n\t"
9631 "movss [rsp], $src\n\t"
9632 "call f2i_fixup\n\t"
9633 "popq $dst\n"
9634 "done: "%}
9635 ins_encode %{
9636 Label done;
9637 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
9638 __ cmpl($dst$$Register, 0x80000000);
9639 __ jccb(Assembler::notEqual, done);
9640 __ subptr(rsp, 8);
9641 __ movflt(Address(rsp, 0), $src$$XMMRegister);
9642 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
9643 __ pop($dst$$Register);
9644 __ bind(done);
9645 %}
9646 ins_pipe(pipe_slow);
9647 %}
9649 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
9650 %{
9651 match(Set dst (ConvF2L src));
9652 effect(KILL cr);
9654 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
9655 "cmpq $dst, [0x8000000000000000]\n\t"
9656 "jne,s done\n\t"
9657 "subq rsp, #8\n\t"
9658 "movss [rsp], $src\n\t"
9659 "call f2l_fixup\n\t"
9660 "popq $dst\n"
9661 "done: "%}
9662 ins_encode %{
9663 Label done;
9664 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
9665 __ cmp64($dst$$Register,
9666 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9667 __ jccb(Assembler::notEqual, done);
9668 __ subptr(rsp, 8);
9669 __ movflt(Address(rsp, 0), $src$$XMMRegister);
9670 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
9671 __ pop($dst$$Register);
9672 __ bind(done);
9673 %}
9674 ins_pipe(pipe_slow);
9675 %}
9677 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
9678 %{
9679 match(Set dst (ConvD2I src));
9680 effect(KILL cr);
9682 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
9683 "cmpl $dst, #0x80000000\n\t"
9684 "jne,s done\n\t"
9685 "subq rsp, #8\n\t"
9686 "movsd [rsp], $src\n\t"
9687 "call d2i_fixup\n\t"
9688 "popq $dst\n"
9689 "done: "%}
9690 ins_encode %{
9691 Label done;
9692 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
9693 __ cmpl($dst$$Register, 0x80000000);
9694 __ jccb(Assembler::notEqual, done);
9695 __ subptr(rsp, 8);
9696 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9697 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
9698 __ pop($dst$$Register);
9699 __ bind(done);
9700 %}
9701 ins_pipe(pipe_slow);
9702 %}
9704 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
9705 %{
9706 match(Set dst (ConvD2L src));
9707 effect(KILL cr);
9709 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
9710 "cmpq $dst, [0x8000000000000000]\n\t"
9711 "jne,s done\n\t"
9712 "subq rsp, #8\n\t"
9713 "movsd [rsp], $src\n\t"
9714 "call d2l_fixup\n\t"
9715 "popq $dst\n"
9716 "done: "%}
9717 ins_encode %{
9718 Label done;
9719 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
9720 __ cmp64($dst$$Register,
9721 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9722 __ jccb(Assembler::notEqual, done);
9723 __ subptr(rsp, 8);
9724 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9725 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
9726 __ pop($dst$$Register);
9727 __ bind(done);
9728 %}
9729 ins_pipe(pipe_slow);
9730 %}
9732 instruct convI2F_reg_reg(regF dst, rRegI src)
9733 %{
9734 predicate(!UseXmmI2F);
9735 match(Set dst (ConvI2F src));
9737 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
9738 ins_encode %{
9739 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
9740 %}
9741 ins_pipe(pipe_slow); // XXX
9742 %}
9744 instruct convI2F_reg_mem(regF dst, memory src)
9745 %{
9746 match(Set dst (ConvI2F (LoadI src)));
9748 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
9749 ins_encode %{
9750 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
9751 %}
9752 ins_pipe(pipe_slow); // XXX
9753 %}
9755 instruct convI2D_reg_reg(regD dst, rRegI src)
9756 %{
9757 predicate(!UseXmmI2D);
9758 match(Set dst (ConvI2D src));
9760 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
9761 ins_encode %{
9762 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
9763 %}
9764 ins_pipe(pipe_slow); // XXX
9765 %}
9767 instruct convI2D_reg_mem(regD dst, memory src)
9768 %{
9769 match(Set dst (ConvI2D (LoadI src)));
9771 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
9772 ins_encode %{
9773 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
9774 %}
9775 ins_pipe(pipe_slow); // XXX
9776 %}
9778 instruct convXI2F_reg(regF dst, rRegI src)
9779 %{
9780 predicate(UseXmmI2F);
9781 match(Set dst (ConvI2F src));
9783 format %{ "movdl $dst, $src\n\t"
9784 "cvtdq2psl $dst, $dst\t# i2f" %}
9785 ins_encode %{
9786 __ movdl($dst$$XMMRegister, $src$$Register);
9787 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
9788 %}
9789 ins_pipe(pipe_slow); // XXX
9790 %}
9792 instruct convXI2D_reg(regD dst, rRegI src)
9793 %{
9794 predicate(UseXmmI2D);
9795 match(Set dst (ConvI2D src));
9797 format %{ "movdl $dst, $src\n\t"
9798 "cvtdq2pdl $dst, $dst\t# i2d" %}
9799 ins_encode %{
9800 __ movdl($dst$$XMMRegister, $src$$Register);
9801 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
9802 %}
9803 ins_pipe(pipe_slow); // XXX
9804 %}
9806 instruct convL2F_reg_reg(regF dst, rRegL src)
9807 %{
9808 match(Set dst (ConvL2F src));
9810 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
9811 ins_encode %{
9812 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
9813 %}
9814 ins_pipe(pipe_slow); // XXX
9815 %}
9817 instruct convL2F_reg_mem(regF dst, memory src)
9818 %{
9819 match(Set dst (ConvL2F (LoadL src)));
9821 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
9822 ins_encode %{
9823 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
9824 %}
9825 ins_pipe(pipe_slow); // XXX
9826 %}
9828 instruct convL2D_reg_reg(regD dst, rRegL src)
9829 %{
9830 match(Set dst (ConvL2D src));
9832 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
9833 ins_encode %{
9834 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
9835 %}
9836 ins_pipe(pipe_slow); // XXX
9837 %}
9839 instruct convL2D_reg_mem(regD dst, memory src)
9840 %{
9841 match(Set dst (ConvL2D (LoadL src)));
9843 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
9844 ins_encode %{
9845 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
9846 %}
9847 ins_pipe(pipe_slow); // XXX
9848 %}
9850 instruct convI2L_reg_reg(rRegL dst, rRegI src)
9851 %{
9852 match(Set dst (ConvI2L src));
9854 ins_cost(125);
9855 format %{ "movslq $dst, $src\t# i2l" %}
9856 ins_encode %{
9857 __ movslq($dst$$Register, $src$$Register);
9858 %}
9859 ins_pipe(ialu_reg_reg);
9860 %}
9862 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
9863 // %{
9864 // match(Set dst (ConvI2L src));
9865 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
9866 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
9867 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
9868 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
9869 // ((const TypeNode*) n)->type()->is_long()->_lo ==
9870 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
9872 // format %{ "movl $dst, $src\t# unsigned i2l" %}
9873 // ins_encode(enc_copy(dst, src));
9874 // // opcode(0x63); // needs REX.W
9875 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
9876 // ins_pipe(ialu_reg_reg);
9877 // %}
9879 // Zero-extend convert int to long
9880 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
9881 %{
9882 match(Set dst (AndL (ConvI2L src) mask));
9884 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
9885 ins_encode %{
9886 if ($dst$$reg != $src$$reg) {
9887 __ movl($dst$$Register, $src$$Register);
9888 }
9889 %}
9890 ins_pipe(ialu_reg_reg);
9891 %}
9893 // Zero-extend convert int to long
9894 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
9895 %{
9896 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
9898 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
9899 ins_encode %{
9900 __ movl($dst$$Register, $src$$Address);
9901 %}
9902 ins_pipe(ialu_reg_mem);
9903 %}
9905 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
9906 %{
9907 match(Set dst (AndL src mask));
9909 format %{ "movl $dst, $src\t# zero-extend long" %}
9910 ins_encode %{
9911 __ movl($dst$$Register, $src$$Register);
9912 %}
9913 ins_pipe(ialu_reg_reg);
9914 %}
9916 instruct convL2I_reg_reg(rRegI dst, rRegL src)
9917 %{
9918 match(Set dst (ConvL2I src));
9920 format %{ "movl $dst, $src\t# l2i" %}
9921 ins_encode %{
9922 __ movl($dst$$Register, $src$$Register);
9923 %}
9924 ins_pipe(ialu_reg_reg);
9925 %}
9928 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
9929 match(Set dst (MoveF2I src));
9930 effect(DEF dst, USE src);
9932 ins_cost(125);
9933 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
9934 ins_encode %{
9935 __ movl($dst$$Register, Address(rsp, $src$$disp));
9936 %}
9937 ins_pipe(ialu_reg_mem);
9938 %}
9940 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
9941 match(Set dst (MoveI2F src));
9942 effect(DEF dst, USE src);
9944 ins_cost(125);
9945 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
9946 ins_encode %{
9947 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
9948 %}
9949 ins_pipe(pipe_slow);
9950 %}
9952 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
9953 match(Set dst (MoveD2L src));
9954 effect(DEF dst, USE src);
9956 ins_cost(125);
9957 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
9958 ins_encode %{
9959 __ movq($dst$$Register, Address(rsp, $src$$disp));
9960 %}
9961 ins_pipe(ialu_reg_mem);
9962 %}
9964 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
9965 predicate(!UseXmmLoadAndClearUpper);
9966 match(Set dst (MoveL2D src));
9967 effect(DEF dst, USE src);
9969 ins_cost(125);
9970 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
9971 ins_encode %{
9972 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
9973 %}
9974 ins_pipe(pipe_slow);
9975 %}
9977 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
9978 predicate(UseXmmLoadAndClearUpper);
9979 match(Set dst (MoveL2D src));
9980 effect(DEF dst, USE src);
9982 ins_cost(125);
9983 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
9984 ins_encode %{
9985 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
9986 %}
9987 ins_pipe(pipe_slow);
9988 %}
9991 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
9992 match(Set dst (MoveF2I src));
9993 effect(DEF dst, USE src);
9995 ins_cost(95); // XXX
9996 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
9997 ins_encode %{
9998 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
9999 %}
10000 ins_pipe(pipe_slow);
10001 %}
10003 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10004 match(Set dst (MoveI2F src));
10005 effect(DEF dst, USE src);
10007 ins_cost(100);
10008 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10009 ins_encode %{
10010 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10011 %}
10012 ins_pipe( ialu_mem_reg );
10013 %}
10015 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10016 match(Set dst (MoveD2L src));
10017 effect(DEF dst, USE src);
10019 ins_cost(95); // XXX
10020 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10021 ins_encode %{
10022 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10023 %}
10024 ins_pipe(pipe_slow);
10025 %}
10027 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10028 match(Set dst (MoveL2D src));
10029 effect(DEF dst, USE src);
10031 ins_cost(100);
10032 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10033 ins_encode %{
10034 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10035 %}
10036 ins_pipe(ialu_mem_reg);
10037 %}
10039 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10040 match(Set dst (MoveF2I src));
10041 effect(DEF dst, USE src);
10042 ins_cost(85);
10043 format %{ "movd $dst,$src\t# MoveF2I" %}
10044 ins_encode %{
10045 __ movdl($dst$$Register, $src$$XMMRegister);
10046 %}
10047 ins_pipe( pipe_slow );
10048 %}
10050 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10051 match(Set dst (MoveD2L src));
10052 effect(DEF dst, USE src);
10053 ins_cost(85);
10054 format %{ "movd $dst,$src\t# MoveD2L" %}
10055 ins_encode %{
10056 __ movdq($dst$$Register, $src$$XMMRegister);
10057 %}
10058 ins_pipe( pipe_slow );
10059 %}
10061 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10062 match(Set dst (MoveI2F src));
10063 effect(DEF dst, USE src);
10064 ins_cost(100);
10065 format %{ "movd $dst,$src\t# MoveI2F" %}
10066 ins_encode %{
10067 __ movdl($dst$$XMMRegister, $src$$Register);
10068 %}
10069 ins_pipe( pipe_slow );
10070 %}
10072 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10073 match(Set dst (MoveL2D src));
10074 effect(DEF dst, USE src);
10075 ins_cost(100);
10076 format %{ "movd $dst,$src\t# MoveL2D" %}
10077 ins_encode %{
10078 __ movdq($dst$$XMMRegister, $src$$Register);
10079 %}
10080 ins_pipe( pipe_slow );
10081 %}
10084 // =======================================================================
10085 // fast clearing of an array
10086 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10087 rFlagsReg cr)
10088 %{
10089 match(Set dummy (ClearArray cnt base));
10090 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10092 format %{ "xorl rax, rax\t# ClearArray:\n\t"
10093 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
10094 ins_encode(opc_reg_reg(0x33, RAX, RAX), // xorl %eax, %eax
10095 Opcode(0xF3), Opcode(0x48), Opcode(0xAB)); // rep REX_W stos
10096 ins_pipe(pipe_slow);
10097 %}
10099 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10100 rax_RegI result, regD tmp1, rFlagsReg cr)
10101 %{
10102 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10103 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10105 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10106 ins_encode %{
10107 __ string_compare($str1$$Register, $str2$$Register,
10108 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10109 $tmp1$$XMMRegister);
10110 %}
10111 ins_pipe( pipe_slow );
10112 %}
10114 // fast search of substring with known size.
10115 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10116 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10117 %{
10118 predicate(UseSSE42Intrinsics);
10119 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10120 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10122 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10123 ins_encode %{
10124 int icnt2 = (int)$int_cnt2$$constant;
10125 if (icnt2 >= 8) {
10126 // IndexOf for constant substrings with size >= 8 elements
10127 // which don't need to be loaded through stack.
10128 __ string_indexofC8($str1$$Register, $str2$$Register,
10129 $cnt1$$Register, $cnt2$$Register,
10130 icnt2, $result$$Register,
10131 $vec$$XMMRegister, $tmp$$Register);
10132 } else {
10133 // Small strings are loaded through stack if they cross page boundary.
10134 __ string_indexof($str1$$Register, $str2$$Register,
10135 $cnt1$$Register, $cnt2$$Register,
10136 icnt2, $result$$Register,
10137 $vec$$XMMRegister, $tmp$$Register);
10138 }
10139 %}
10140 ins_pipe( pipe_slow );
10141 %}
10143 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10144 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10145 %{
10146 predicate(UseSSE42Intrinsics);
10147 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10148 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10150 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10151 ins_encode %{
10152 __ string_indexof($str1$$Register, $str2$$Register,
10153 $cnt1$$Register, $cnt2$$Register,
10154 (-1), $result$$Register,
10155 $vec$$XMMRegister, $tmp$$Register);
10156 %}
10157 ins_pipe( pipe_slow );
10158 %}
10160 // fast string equals
10161 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
10162 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10163 %{
10164 match(Set result (StrEquals (Binary str1 str2) cnt));
10165 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
10167 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10168 ins_encode %{
10169 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
10170 $cnt$$Register, $result$$Register, $tmp3$$Register,
10171 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10172 %}
10173 ins_pipe( pipe_slow );
10174 %}
10176 // fast array equals
10177 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10178 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10179 %{
10180 match(Set result (AryEq ary1 ary2));
10181 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10182 //ins_cost(300);
10184 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10185 ins_encode %{
10186 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
10187 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10188 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10189 %}
10190 ins_pipe( pipe_slow );
10191 %}
10193 //----------Control Flow Instructions------------------------------------------
10194 // Signed compare Instructions
10196 // XXX more variants!!
10197 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10198 %{
10199 match(Set cr (CmpI op1 op2));
10200 effect(DEF cr, USE op1, USE op2);
10202 format %{ "cmpl $op1, $op2" %}
10203 opcode(0x3B); /* Opcode 3B /r */
10204 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10205 ins_pipe(ialu_cr_reg_reg);
10206 %}
10208 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10209 %{
10210 match(Set cr (CmpI op1 op2));
10212 format %{ "cmpl $op1, $op2" %}
10213 opcode(0x81, 0x07); /* Opcode 81 /7 */
10214 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10215 ins_pipe(ialu_cr_reg_imm);
10216 %}
10218 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
10219 %{
10220 match(Set cr (CmpI op1 (LoadI op2)));
10222 ins_cost(500); // XXX
10223 format %{ "cmpl $op1, $op2" %}
10224 opcode(0x3B); /* Opcode 3B /r */
10225 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10226 ins_pipe(ialu_cr_reg_mem);
10227 %}
10229 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
10230 %{
10231 match(Set cr (CmpI src zero));
10233 format %{ "testl $src, $src" %}
10234 opcode(0x85);
10235 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10236 ins_pipe(ialu_cr_reg_imm);
10237 %}
10239 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
10240 %{
10241 match(Set cr (CmpI (AndI src con) zero));
10243 format %{ "testl $src, $con" %}
10244 opcode(0xF7, 0x00);
10245 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
10246 ins_pipe(ialu_cr_reg_imm);
10247 %}
10249 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
10250 %{
10251 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
10253 format %{ "testl $src, $mem" %}
10254 opcode(0x85);
10255 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
10256 ins_pipe(ialu_cr_reg_mem);
10257 %}
10259 // Unsigned compare Instructions; really, same as signed except they
10260 // produce an rFlagsRegU instead of rFlagsReg.
10261 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
10262 %{
10263 match(Set cr (CmpU op1 op2));
10265 format %{ "cmpl $op1, $op2\t# unsigned" %}
10266 opcode(0x3B); /* Opcode 3B /r */
10267 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10268 ins_pipe(ialu_cr_reg_reg);
10269 %}
10271 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
10272 %{
10273 match(Set cr (CmpU op1 op2));
10275 format %{ "cmpl $op1, $op2\t# unsigned" %}
10276 opcode(0x81,0x07); /* Opcode 81 /7 */
10277 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10278 ins_pipe(ialu_cr_reg_imm);
10279 %}
10281 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
10282 %{
10283 match(Set cr (CmpU op1 (LoadI op2)));
10285 ins_cost(500); // XXX
10286 format %{ "cmpl $op1, $op2\t# unsigned" %}
10287 opcode(0x3B); /* Opcode 3B /r */
10288 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10289 ins_pipe(ialu_cr_reg_mem);
10290 %}
10292 // // // Cisc-spilled version of cmpU_rReg
10293 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
10294 // //%{
10295 // // match(Set cr (CmpU (LoadI op1) op2));
10296 // //
10297 // // format %{ "CMPu $op1,$op2" %}
10298 // // ins_cost(500);
10299 // // opcode(0x39); /* Opcode 39 /r */
10300 // // ins_encode( OpcP, reg_mem( op1, op2) );
10301 // //%}
10303 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
10304 %{
10305 match(Set cr (CmpU src zero));
10307 format %{ "testl $src, $src\t# unsigned" %}
10308 opcode(0x85);
10309 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10310 ins_pipe(ialu_cr_reg_imm);
10311 %}
10313 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
10314 %{
10315 match(Set cr (CmpP op1 op2));
10317 format %{ "cmpq $op1, $op2\t# ptr" %}
10318 opcode(0x3B); /* Opcode 3B /r */
10319 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10320 ins_pipe(ialu_cr_reg_reg);
10321 %}
10323 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
10324 %{
10325 match(Set cr (CmpP op1 (LoadP op2)));
10327 ins_cost(500); // XXX
10328 format %{ "cmpq $op1, $op2\t# ptr" %}
10329 opcode(0x3B); /* Opcode 3B /r */
10330 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10331 ins_pipe(ialu_cr_reg_mem);
10332 %}
10334 // // // Cisc-spilled version of cmpP_rReg
10335 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
10336 // //%{
10337 // // match(Set cr (CmpP (LoadP op1) op2));
10338 // //
10339 // // format %{ "CMPu $op1,$op2" %}
10340 // // ins_cost(500);
10341 // // opcode(0x39); /* Opcode 39 /r */
10342 // // ins_encode( OpcP, reg_mem( op1, op2) );
10343 // //%}
10345 // XXX this is generalized by compP_rReg_mem???
10346 // Compare raw pointer (used in out-of-heap check).
10347 // Only works because non-oop pointers must be raw pointers
10348 // and raw pointers have no anti-dependencies.
10349 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
10350 %{
10351 predicate(!n->in(2)->in(2)->bottom_type()->isa_oop_ptr());
10352 match(Set cr (CmpP op1 (LoadP op2)));
10354 format %{ "cmpq $op1, $op2\t# raw ptr" %}
10355 opcode(0x3B); /* Opcode 3B /r */
10356 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10357 ins_pipe(ialu_cr_reg_mem);
10358 %}
10360 // This will generate a signed flags result. This should be OK since
10361 // any compare to a zero should be eq/neq.
10362 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
10363 %{
10364 match(Set cr (CmpP src zero));
10366 format %{ "testq $src, $src\t# ptr" %}
10367 opcode(0x85);
10368 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
10369 ins_pipe(ialu_cr_reg_imm);
10370 %}
10372 // This will generate a signed flags result. This should be OK since
10373 // any compare to a zero should be eq/neq.
10374 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
10375 %{
10376 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
10377 match(Set cr (CmpP (LoadP op) zero));
10379 ins_cost(500); // XXX
10380 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
10381 opcode(0xF7); /* Opcode F7 /0 */
10382 ins_encode(REX_mem_wide(op),
10383 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
10384 ins_pipe(ialu_cr_reg_imm);
10385 %}
10387 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
10388 %{
10389 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
10390 match(Set cr (CmpP (LoadP mem) zero));
10392 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
10393 ins_encode %{
10394 __ cmpq(r12, $mem$$Address);
10395 %}
10396 ins_pipe(ialu_cr_reg_mem);
10397 %}
10399 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
10400 %{
10401 match(Set cr (CmpN op1 op2));
10403 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10404 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
10405 ins_pipe(ialu_cr_reg_reg);
10406 %}
10408 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
10409 %{
10410 match(Set cr (CmpN src (LoadN mem)));
10412 format %{ "cmpl $src, $mem\t# compressed ptr" %}
10413 ins_encode %{
10414 __ cmpl($src$$Register, $mem$$Address);
10415 %}
10416 ins_pipe(ialu_cr_reg_mem);
10417 %}
10419 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
10420 match(Set cr (CmpN op1 op2));
10422 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10423 ins_encode %{
10424 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
10425 %}
10426 ins_pipe(ialu_cr_reg_imm);
10427 %}
10429 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
10430 %{
10431 match(Set cr (CmpN src (LoadN mem)));
10433 format %{ "cmpl $mem, $src\t# compressed ptr" %}
10434 ins_encode %{
10435 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
10436 %}
10437 ins_pipe(ialu_cr_reg_mem);
10438 %}
10440 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
10441 match(Set cr (CmpN src zero));
10443 format %{ "testl $src, $src\t# compressed ptr" %}
10444 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
10445 ins_pipe(ialu_cr_reg_imm);
10446 %}
10448 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
10449 %{
10450 predicate(Universe::narrow_oop_base() != NULL);
10451 match(Set cr (CmpN (LoadN mem) zero));
10453 ins_cost(500); // XXX
10454 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
10455 ins_encode %{
10456 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
10457 %}
10458 ins_pipe(ialu_cr_reg_mem);
10459 %}
10461 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
10462 %{
10463 predicate(Universe::narrow_oop_base() == NULL);
10464 match(Set cr (CmpN (LoadN mem) zero));
10466 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
10467 ins_encode %{
10468 __ cmpl(r12, $mem$$Address);
10469 %}
10470 ins_pipe(ialu_cr_reg_mem);
10471 %}
10473 // Yanked all unsigned pointer compare operations.
10474 // Pointer compares are done with CmpP which is already unsigned.
10476 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
10477 %{
10478 match(Set cr (CmpL op1 op2));
10480 format %{ "cmpq $op1, $op2" %}
10481 opcode(0x3B); /* Opcode 3B /r */
10482 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10483 ins_pipe(ialu_cr_reg_reg);
10484 %}
10486 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
10487 %{
10488 match(Set cr (CmpL op1 op2));
10490 format %{ "cmpq $op1, $op2" %}
10491 opcode(0x81, 0x07); /* Opcode 81 /7 */
10492 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
10493 ins_pipe(ialu_cr_reg_imm);
10494 %}
10496 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
10497 %{
10498 match(Set cr (CmpL op1 (LoadL op2)));
10500 format %{ "cmpq $op1, $op2" %}
10501 opcode(0x3B); /* Opcode 3B /r */
10502 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10503 ins_pipe(ialu_cr_reg_mem);
10504 %}
10506 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
10507 %{
10508 match(Set cr (CmpL src zero));
10510 format %{ "testq $src, $src" %}
10511 opcode(0x85);
10512 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
10513 ins_pipe(ialu_cr_reg_imm);
10514 %}
10516 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
10517 %{
10518 match(Set cr (CmpL (AndL src con) zero));
10520 format %{ "testq $src, $con\t# long" %}
10521 opcode(0xF7, 0x00);
10522 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
10523 ins_pipe(ialu_cr_reg_imm);
10524 %}
10526 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
10527 %{
10528 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
10530 format %{ "testq $src, $mem" %}
10531 opcode(0x85);
10532 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
10533 ins_pipe(ialu_cr_reg_mem);
10534 %}
10536 // Manifest a CmpL result in an integer register. Very painful.
10537 // This is the test to avoid.
10538 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
10539 %{
10540 match(Set dst (CmpL3 src1 src2));
10541 effect(KILL flags);
10543 ins_cost(275); // XXX
10544 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
10545 "movl $dst, -1\n\t"
10546 "jl,s done\n\t"
10547 "setne $dst\n\t"
10548 "movzbl $dst, $dst\n\t"
10549 "done:" %}
10550 ins_encode(cmpl3_flag(src1, src2, dst));
10551 ins_pipe(pipe_slow);
10552 %}
10554 //----------Max and Min--------------------------------------------------------
10555 // Min Instructions
10557 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
10558 %{
10559 effect(USE_DEF dst, USE src, USE cr);
10561 format %{ "cmovlgt $dst, $src\t# min" %}
10562 opcode(0x0F, 0x4F);
10563 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
10564 ins_pipe(pipe_cmov_reg);
10565 %}
10568 instruct minI_rReg(rRegI dst, rRegI src)
10569 %{
10570 match(Set dst (MinI dst src));
10572 ins_cost(200);
10573 expand %{
10574 rFlagsReg cr;
10575 compI_rReg(cr, dst, src);
10576 cmovI_reg_g(dst, src, cr);
10577 %}
10578 %}
10580 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
10581 %{
10582 effect(USE_DEF dst, USE src, USE cr);
10584 format %{ "cmovllt $dst, $src\t# max" %}
10585 opcode(0x0F, 0x4C);
10586 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
10587 ins_pipe(pipe_cmov_reg);
10588 %}
10591 instruct maxI_rReg(rRegI dst, rRegI src)
10592 %{
10593 match(Set dst (MaxI dst src));
10595 ins_cost(200);
10596 expand %{
10597 rFlagsReg cr;
10598 compI_rReg(cr, dst, src);
10599 cmovI_reg_l(dst, src, cr);
10600 %}
10601 %}
10603 // ============================================================================
10604 // Branch Instructions
10606 // Jump Direct - Label defines a relative address from JMP+1
10607 instruct jmpDir(label labl)
10608 %{
10609 match(Goto);
10610 effect(USE labl);
10612 ins_cost(300);
10613 format %{ "jmp $labl" %}
10614 size(5);
10615 ins_encode %{
10616 Label* L = $labl$$label;
10617 __ jmp(*L, false); // Always long jump
10618 %}
10619 ins_pipe(pipe_jmp);
10620 %}
10622 // Jump Direct Conditional - Label defines a relative address from Jcc+1
10623 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
10624 %{
10625 match(If cop cr);
10626 effect(USE labl);
10628 ins_cost(300);
10629 format %{ "j$cop $labl" %}
10630 size(6);
10631 ins_encode %{
10632 Label* L = $labl$$label;
10633 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10634 %}
10635 ins_pipe(pipe_jcc);
10636 %}
10638 // Jump Direct Conditional - Label defines a relative address from Jcc+1
10639 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
10640 %{
10641 match(CountedLoopEnd cop cr);
10642 effect(USE labl);
10644 ins_cost(300);
10645 format %{ "j$cop $labl\t# loop end" %}
10646 size(6);
10647 ins_encode %{
10648 Label* L = $labl$$label;
10649 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10650 %}
10651 ins_pipe(pipe_jcc);
10652 %}
10654 // Jump Direct Conditional - Label defines a relative address from Jcc+1
10655 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
10656 match(CountedLoopEnd cop cmp);
10657 effect(USE labl);
10659 ins_cost(300);
10660 format %{ "j$cop,u $labl\t# loop end" %}
10661 size(6);
10662 ins_encode %{
10663 Label* L = $labl$$label;
10664 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10665 %}
10666 ins_pipe(pipe_jcc);
10667 %}
10669 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
10670 match(CountedLoopEnd cop cmp);
10671 effect(USE labl);
10673 ins_cost(200);
10674 format %{ "j$cop,u $labl\t# loop end" %}
10675 size(6);
10676 ins_encode %{
10677 Label* L = $labl$$label;
10678 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10679 %}
10680 ins_pipe(pipe_jcc);
10681 %}
10683 // Jump Direct Conditional - using unsigned comparison
10684 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
10685 match(If cop cmp);
10686 effect(USE labl);
10688 ins_cost(300);
10689 format %{ "j$cop,u $labl" %}
10690 size(6);
10691 ins_encode %{
10692 Label* L = $labl$$label;
10693 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10694 %}
10695 ins_pipe(pipe_jcc);
10696 %}
10698 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
10699 match(If cop cmp);
10700 effect(USE labl);
10702 ins_cost(200);
10703 format %{ "j$cop,u $labl" %}
10704 size(6);
10705 ins_encode %{
10706 Label* L = $labl$$label;
10707 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10708 %}
10709 ins_pipe(pipe_jcc);
10710 %}
10712 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
10713 match(If cop cmp);
10714 effect(USE labl);
10716 ins_cost(200);
10717 format %{ $$template
10718 if ($cop$$cmpcode == Assembler::notEqual) {
10719 $$emit$$"jp,u $labl\n\t"
10720 $$emit$$"j$cop,u $labl"
10721 } else {
10722 $$emit$$"jp,u done\n\t"
10723 $$emit$$"j$cop,u $labl\n\t"
10724 $$emit$$"done:"
10725 }
10726 %}
10727 ins_encode %{
10728 Label* l = $labl$$label;
10729 if ($cop$$cmpcode == Assembler::notEqual) {
10730 __ jcc(Assembler::parity, *l, false);
10731 __ jcc(Assembler::notEqual, *l, false);
10732 } else if ($cop$$cmpcode == Assembler::equal) {
10733 Label done;
10734 __ jccb(Assembler::parity, done);
10735 __ jcc(Assembler::equal, *l, false);
10736 __ bind(done);
10737 } else {
10738 ShouldNotReachHere();
10739 }
10740 %}
10741 ins_pipe(pipe_jcc);
10742 %}
10744 // ============================================================================
10745 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
10746 // superklass array for an instance of the superklass. Set a hidden
10747 // internal cache on a hit (cache is checked with exposed code in
10748 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
10749 // encoding ALSO sets flags.
10751 instruct partialSubtypeCheck(rdi_RegP result,
10752 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
10753 rFlagsReg cr)
10754 %{
10755 match(Set result (PartialSubtypeCheck sub super));
10756 effect(KILL rcx, KILL cr);
10758 ins_cost(1100); // slightly larger than the next version
10759 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
10760 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
10761 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
10762 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
10763 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
10764 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
10765 "xorq $result, $result\t\t Hit: rdi zero\n\t"
10766 "miss:\t" %}
10768 opcode(0x1); // Force a XOR of RDI
10769 ins_encode(enc_PartialSubtypeCheck());
10770 ins_pipe(pipe_slow);
10771 %}
10773 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
10774 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
10775 immP0 zero,
10776 rdi_RegP result)
10777 %{
10778 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
10779 effect(KILL rcx, KILL result);
10781 ins_cost(1000);
10782 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
10783 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
10784 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
10785 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
10786 "jne,s miss\t\t# Missed: flags nz\n\t"
10787 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
10788 "miss:\t" %}
10790 opcode(0x0); // No need to XOR RDI
10791 ins_encode(enc_PartialSubtypeCheck());
10792 ins_pipe(pipe_slow);
10793 %}
10795 // ============================================================================
10796 // Branch Instructions -- short offset versions
10797 //
10798 // These instructions are used to replace jumps of a long offset (the default
10799 // match) with jumps of a shorter offset. These instructions are all tagged
10800 // with the ins_short_branch attribute, which causes the ADLC to suppress the
10801 // match rules in general matching. Instead, the ADLC generates a conversion
10802 // method in the MachNode which can be used to do in-place replacement of the
10803 // long variant with the shorter variant. The compiler will determine if a
10804 // branch can be taken by the is_short_branch_offset() predicate in the machine
10805 // specific code section of the file.
10807 // Jump Direct - Label defines a relative address from JMP+1
10808 instruct jmpDir_short(label labl) %{
10809 match(Goto);
10810 effect(USE labl);
10812 ins_cost(300);
10813 format %{ "jmp,s $labl" %}
10814 size(2);
10815 ins_encode %{
10816 Label* L = $labl$$label;
10817 __ jmpb(*L);
10818 %}
10819 ins_pipe(pipe_jmp);
10820 ins_short_branch(1);
10821 %}
10823 // Jump Direct Conditional - Label defines a relative address from Jcc+1
10824 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
10825 match(If cop cr);
10826 effect(USE labl);
10828 ins_cost(300);
10829 format %{ "j$cop,s $labl" %}
10830 size(2);
10831 ins_encode %{
10832 Label* L = $labl$$label;
10833 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
10834 %}
10835 ins_pipe(pipe_jcc);
10836 ins_short_branch(1);
10837 %}
10839 // Jump Direct Conditional - Label defines a relative address from Jcc+1
10840 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
10841 match(CountedLoopEnd cop cr);
10842 effect(USE labl);
10844 ins_cost(300);
10845 format %{ "j$cop,s $labl\t# loop end" %}
10846 size(2);
10847 ins_encode %{
10848 Label* L = $labl$$label;
10849 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
10850 %}
10851 ins_pipe(pipe_jcc);
10852 ins_short_branch(1);
10853 %}
10855 // Jump Direct Conditional - Label defines a relative address from Jcc+1
10856 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
10857 match(CountedLoopEnd cop cmp);
10858 effect(USE labl);
10860 ins_cost(300);
10861 format %{ "j$cop,us $labl\t# loop end" %}
10862 size(2);
10863 ins_encode %{
10864 Label* L = $labl$$label;
10865 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
10866 %}
10867 ins_pipe(pipe_jcc);
10868 ins_short_branch(1);
10869 %}
10871 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
10872 match(CountedLoopEnd cop cmp);
10873 effect(USE labl);
10875 ins_cost(300);
10876 format %{ "j$cop,us $labl\t# loop end" %}
10877 size(2);
10878 ins_encode %{
10879 Label* L = $labl$$label;
10880 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
10881 %}
10882 ins_pipe(pipe_jcc);
10883 ins_short_branch(1);
10884 %}
10886 // Jump Direct Conditional - using unsigned comparison
10887 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
10888 match(If cop cmp);
10889 effect(USE labl);
10891 ins_cost(300);
10892 format %{ "j$cop,us $labl" %}
10893 size(2);
10894 ins_encode %{
10895 Label* L = $labl$$label;
10896 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
10897 %}
10898 ins_pipe(pipe_jcc);
10899 ins_short_branch(1);
10900 %}
10902 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
10903 match(If cop cmp);
10904 effect(USE labl);
10906 ins_cost(300);
10907 format %{ "j$cop,us $labl" %}
10908 size(2);
10909 ins_encode %{
10910 Label* L = $labl$$label;
10911 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
10912 %}
10913 ins_pipe(pipe_jcc);
10914 ins_short_branch(1);
10915 %}
10917 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
10918 match(If cop cmp);
10919 effect(USE labl);
10921 ins_cost(300);
10922 format %{ $$template
10923 if ($cop$$cmpcode == Assembler::notEqual) {
10924 $$emit$$"jp,u,s $labl\n\t"
10925 $$emit$$"j$cop,u,s $labl"
10926 } else {
10927 $$emit$$"jp,u,s done\n\t"
10928 $$emit$$"j$cop,u,s $labl\n\t"
10929 $$emit$$"done:"
10930 }
10931 %}
10932 size(4);
10933 ins_encode %{
10934 Label* l = $labl$$label;
10935 if ($cop$$cmpcode == Assembler::notEqual) {
10936 __ jccb(Assembler::parity, *l);
10937 __ jccb(Assembler::notEqual, *l);
10938 } else if ($cop$$cmpcode == Assembler::equal) {
10939 Label done;
10940 __ jccb(Assembler::parity, done);
10941 __ jccb(Assembler::equal, *l);
10942 __ bind(done);
10943 } else {
10944 ShouldNotReachHere();
10945 }
10946 %}
10947 ins_pipe(pipe_jcc);
10948 ins_short_branch(1);
10949 %}
10951 // ============================================================================
10952 // inlined locking and unlocking
10954 instruct cmpFastLock(rFlagsReg cr,
10955 rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr)
10956 %{
10957 match(Set cr (FastLock object box));
10958 effect(TEMP tmp, TEMP scr, USE_KILL box);
10960 ins_cost(300);
10961 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
10962 ins_encode(Fast_Lock(object, box, tmp, scr));
10963 ins_pipe(pipe_slow);
10964 %}
10966 instruct cmpFastUnlock(rFlagsReg cr,
10967 rRegP object, rax_RegP box, rRegP tmp)
10968 %{
10969 match(Set cr (FastUnlock object box));
10970 effect(TEMP tmp, USE_KILL box);
10972 ins_cost(300);
10973 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
10974 ins_encode(Fast_Unlock(object, box, tmp));
10975 ins_pipe(pipe_slow);
10976 %}
10979 // ============================================================================
10980 // Safepoint Instructions
10981 instruct safePoint_poll(rFlagsReg cr)
10982 %{
10983 predicate(!Assembler::is_polling_page_far());
10984 match(SafePoint);
10985 effect(KILL cr);
10987 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
10988 "# Safepoint: poll for GC" %}
10989 ins_cost(125);
10990 ins_encode %{
10991 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
10992 __ testl(rax, addr);
10993 %}
10994 ins_pipe(ialu_reg_mem);
10995 %}
10997 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
10998 %{
10999 predicate(Assembler::is_polling_page_far());
11000 match(SafePoint poll);
11001 effect(KILL cr, USE poll);
11003 format %{ "testl rax, [$poll]\t"
11004 "# Safepoint: poll for GC" %}
11005 ins_cost(125);
11006 ins_encode %{
11007 __ relocate(relocInfo::poll_type);
11008 __ testl(rax, Address($poll$$Register, 0));
11009 %}
11010 ins_pipe(ialu_reg_mem);
11011 %}
11013 // ============================================================================
11014 // Procedure Call/Return Instructions
11015 // Call Java Static Instruction
11016 // Note: If this code changes, the corresponding ret_addr_offset() and
11017 // compute_padding() functions will have to be adjusted.
11018 instruct CallStaticJavaDirect(method meth) %{
11019 match(CallStaticJava);
11020 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke());
11021 effect(USE meth);
11023 ins_cost(300);
11024 format %{ "call,static " %}
11025 opcode(0xE8); /* E8 cd */
11026 ins_encode(Java_Static_Call(meth), call_epilog);
11027 ins_pipe(pipe_slow);
11028 ins_alignment(4);
11029 %}
11031 // Call Java Static Instruction (method handle version)
11032 // Note: If this code changes, the corresponding ret_addr_offset() and
11033 // compute_padding() functions will have to be adjusted.
11034 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{
11035 match(CallStaticJava);
11036 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke());
11037 effect(USE meth);
11038 // RBP is saved by all callees (for interpreter stack correction).
11039 // We use it here for a similar purpose, in {preserve,restore}_SP.
11041 ins_cost(300);
11042 format %{ "call,static/MethodHandle " %}
11043 opcode(0xE8); /* E8 cd */
11044 ins_encode(preserve_SP,
11045 Java_Static_Call(meth),
11046 restore_SP,
11047 call_epilog);
11048 ins_pipe(pipe_slow);
11049 ins_alignment(4);
11050 %}
11052 // Call Java Dynamic Instruction
11053 // Note: If this code changes, the corresponding ret_addr_offset() and
11054 // compute_padding() functions will have to be adjusted.
11055 instruct CallDynamicJavaDirect(method meth)
11056 %{
11057 match(CallDynamicJava);
11058 effect(USE meth);
11060 ins_cost(300);
11061 format %{ "movq rax, #Universe::non_oop_word()\n\t"
11062 "call,dynamic " %}
11063 opcode(0xE8); /* E8 cd */
11064 ins_encode(Java_Dynamic_Call(meth), call_epilog);
11065 ins_pipe(pipe_slow);
11066 ins_alignment(4);
11067 %}
11069 // Call Runtime Instruction
11070 instruct CallRuntimeDirect(method meth)
11071 %{
11072 match(CallRuntime);
11073 effect(USE meth);
11075 ins_cost(300);
11076 format %{ "call,runtime " %}
11077 opcode(0xE8); /* E8 cd */
11078 ins_encode(Java_To_Runtime(meth));
11079 ins_pipe(pipe_slow);
11080 %}
11082 // Call runtime without safepoint
11083 instruct CallLeafDirect(method meth)
11084 %{
11085 match(CallLeaf);
11086 effect(USE meth);
11088 ins_cost(300);
11089 format %{ "call_leaf,runtime " %}
11090 opcode(0xE8); /* E8 cd */
11091 ins_encode(Java_To_Runtime(meth));
11092 ins_pipe(pipe_slow);
11093 %}
11095 // Call runtime without safepoint
11096 instruct CallLeafNoFPDirect(method meth)
11097 %{
11098 match(CallLeafNoFP);
11099 effect(USE meth);
11101 ins_cost(300);
11102 format %{ "call_leaf_nofp,runtime " %}
11103 opcode(0xE8); /* E8 cd */
11104 ins_encode(Java_To_Runtime(meth));
11105 ins_pipe(pipe_slow);
11106 %}
11108 // Return Instruction
11109 // Remove the return address & jump to it.
11110 // Notice: We always emit a nop after a ret to make sure there is room
11111 // for safepoint patching
11112 instruct Ret()
11113 %{
11114 match(Return);
11116 format %{ "ret" %}
11117 opcode(0xC3);
11118 ins_encode(OpcP);
11119 ins_pipe(pipe_jmp);
11120 %}
11122 // Tail Call; Jump from runtime stub to Java code.
11123 // Also known as an 'interprocedural jump'.
11124 // Target of jump will eventually return to caller.
11125 // TailJump below removes the return address.
11126 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
11127 %{
11128 match(TailCall jump_target method_oop);
11130 ins_cost(300);
11131 format %{ "jmp $jump_target\t# rbx holds method oop" %}
11132 opcode(0xFF, 0x4); /* Opcode FF /4 */
11133 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
11134 ins_pipe(pipe_jmp);
11135 %}
11137 // Tail Jump; remove the return address; jump to target.
11138 // TailCall above leaves the return address around.
11139 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
11140 %{
11141 match(TailJump jump_target ex_oop);
11143 ins_cost(300);
11144 format %{ "popq rdx\t# pop return address\n\t"
11145 "jmp $jump_target" %}
11146 opcode(0xFF, 0x4); /* Opcode FF /4 */
11147 ins_encode(Opcode(0x5a), // popq rdx
11148 REX_reg(jump_target), OpcP, reg_opc(jump_target));
11149 ins_pipe(pipe_jmp);
11150 %}
11152 // Create exception oop: created by stack-crawling runtime code.
11153 // Created exception is now available to this handler, and is setup
11154 // just prior to jumping to this handler. No code emitted.
11155 instruct CreateException(rax_RegP ex_oop)
11156 %{
11157 match(Set ex_oop (CreateEx));
11159 size(0);
11160 // use the following format syntax
11161 format %{ "# exception oop is in rax; no code emitted" %}
11162 ins_encode();
11163 ins_pipe(empty);
11164 %}
11166 // Rethrow exception:
11167 // The exception oop will come in the first argument position.
11168 // Then JUMP (not call) to the rethrow stub code.
11169 instruct RethrowException()
11170 %{
11171 match(Rethrow);
11173 // use the following format syntax
11174 format %{ "jmp rethrow_stub" %}
11175 ins_encode(enc_rethrow);
11176 ins_pipe(pipe_jmp);
11177 %}
11180 // ============================================================================
11181 // This name is KNOWN by the ADLC and cannot be changed.
11182 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11183 // for this guy.
11184 instruct tlsLoadP(r15_RegP dst) %{
11185 match(Set dst (ThreadLocal));
11186 effect(DEF dst);
11188 size(0);
11189 format %{ "# TLS is in R15" %}
11190 ins_encode( /*empty encoding*/ );
11191 ins_pipe(ialu_reg_reg);
11192 %}
11195 //----------PEEPHOLE RULES-----------------------------------------------------
11196 // These must follow all instruction definitions as they use the names
11197 // defined in the instructions definitions.
11198 //
11199 // peepmatch ( root_instr_name [preceding_instruction]* );
11200 //
11201 // peepconstraint %{
11202 // (instruction_number.operand_name relational_op instruction_number.operand_name
11203 // [, ...] );
11204 // // instruction numbers are zero-based using left to right order in peepmatch
11205 //
11206 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11207 // // provide an instruction_number.operand_name for each operand that appears
11208 // // in the replacement instruction's match rule
11209 //
11210 // ---------VM FLAGS---------------------------------------------------------
11211 //
11212 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11213 //
11214 // Each peephole rule is given an identifying number starting with zero and
11215 // increasing by one in the order seen by the parser. An individual peephole
11216 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11217 // on the command-line.
11218 //
11219 // ---------CURRENT LIMITATIONS----------------------------------------------
11220 //
11221 // Only match adjacent instructions in same basic block
11222 // Only equality constraints
11223 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11224 // Only one replacement instruction
11225 //
11226 // ---------EXAMPLE----------------------------------------------------------
11227 //
11228 // // pertinent parts of existing instructions in architecture description
11229 // instruct movI(rRegI dst, rRegI src)
11230 // %{
11231 // match(Set dst (CopyI src));
11232 // %}
11233 //
11234 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
11235 // %{
11236 // match(Set dst (AddI dst src));
11237 // effect(KILL cr);
11238 // %}
11239 //
11240 // // Change (inc mov) to lea
11241 // peephole %{
11242 // // increment preceeded by register-register move
11243 // peepmatch ( incI_rReg movI );
11244 // // require that the destination register of the increment
11245 // // match the destination register of the move
11246 // peepconstraint ( 0.dst == 1.dst );
11247 // // construct a replacement instruction that sets
11248 // // the destination to ( move's source register + one )
11249 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
11250 // %}
11251 //
11253 // Implementation no longer uses movX instructions since
11254 // machine-independent system no longer uses CopyX nodes.
11255 //
11256 // peephole
11257 // %{
11258 // peepmatch (incI_rReg movI);
11259 // peepconstraint (0.dst == 1.dst);
11260 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11261 // %}
11263 // peephole
11264 // %{
11265 // peepmatch (decI_rReg movI);
11266 // peepconstraint (0.dst == 1.dst);
11267 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11268 // %}
11270 // peephole
11271 // %{
11272 // peepmatch (addI_rReg_imm movI);
11273 // peepconstraint (0.dst == 1.dst);
11274 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11275 // %}
11277 // peephole
11278 // %{
11279 // peepmatch (incL_rReg movL);
11280 // peepconstraint (0.dst == 1.dst);
11281 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11282 // %}
11284 // peephole
11285 // %{
11286 // peepmatch (decL_rReg movL);
11287 // peepconstraint (0.dst == 1.dst);
11288 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11289 // %}
11291 // peephole
11292 // %{
11293 // peepmatch (addL_rReg_imm movL);
11294 // peepconstraint (0.dst == 1.dst);
11295 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11296 // %}
11298 // peephole
11299 // %{
11300 // peepmatch (addP_rReg_imm movP);
11301 // peepconstraint (0.dst == 1.dst);
11302 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
11303 // %}
11305 // // Change load of spilled value to only a spill
11306 // instruct storeI(memory mem, rRegI src)
11307 // %{
11308 // match(Set mem (StoreI mem src));
11309 // %}
11310 //
11311 // instruct loadI(rRegI dst, memory mem)
11312 // %{
11313 // match(Set dst (LoadI mem));
11314 // %}
11315 //
11317 peephole
11318 %{
11319 peepmatch (loadI storeI);
11320 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11321 peepreplace (storeI(1.mem 1.mem 1.src));
11322 %}
11324 peephole
11325 %{
11326 peepmatch (loadL storeL);
11327 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11328 peepreplace (storeL(1.mem 1.mem 1.src));
11329 %}
11331 //----------SMARTSPILL RULES---------------------------------------------------
11332 // These must follow all instruction definitions as they use the names
11333 // defined in the instructions definitions.
