1.1 --- a/src/cpu/x86/vm/interp_masm_x86_64.cpp Thu Aug 11 12:08:11 2011 -0700
1.2 +++ b/src/cpu/x86/vm/interp_masm_x86_64.cpp Tue Aug 16 04:14:05 2011 -0700
1.3 @@ -233,7 +233,7 @@
1.4 Register index,
1.5 int bcp_offset,
1.6 size_t index_size) {
1.7 - assert(cache != index, "must use different registers");
1.8 + assert_different_registers(cache, index);
1.9 get_cache_index_at_bcp(index, bcp_offset, index_size);
1.10 movptr(cache, Address(rbp, frame::interpreter_frame_cache_offset * wordSize));
1.11 assert(sizeof(ConstantPoolCacheEntry) == 4 * wordSize, "adjust code below");
1.12 @@ -242,6 +242,22 @@
1.13 }
1.14
1.15
1.16 +void InterpreterMacroAssembler::get_cache_and_index_and_bytecode_at_bcp(Register cache,
1.17 + Register index,
1.18 + Register bytecode,
1.19 + int byte_no,
1.20 + int bcp_offset,
1.21 + size_t index_size) {
1.22 + get_cache_and_index_at_bcp(cache, index, bcp_offset, index_size);
1.23 + // We use a 32-bit load here since the layout of 64-bit words on
1.24 + // little-endian machines allow us that.
1.25 + movl(bytecode, Address(cache, index, Address::times_ptr, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::indices_offset()));
1.26 + const int shift_count = (1 + byte_no) * BitsPerByte;
1.27 + shrl(bytecode, shift_count);
1.28 + andl(bytecode, 0xFF);
1.29 +}
1.30 +
1.31 +
1.32 void InterpreterMacroAssembler::get_cache_entry_pointer_at_bcp(Register cache,
1.33 Register tmp,
1.34 int bcp_offset,
