1.1 --- a/src/cpu/sparc/vm/sparc.ad Thu Jul 07 10:51:07 2011 -0700
1.2 +++ b/src/cpu/sparc/vm/sparc.ad Fri Jul 08 09:38:48 2011 -0700
1.3 @@ -425,7 +425,7 @@
1.4 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
1.5 // This class is usable for mis-aligned loads as happen in I2C adapters.
1.6 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
1.7 - R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 );
1.8 + R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
1.9 %}
1.10
1.11 //----------DEFINITION BLOCK---------------------------------------------------
1.12 @@ -1326,17 +1326,17 @@
1.13
1.14 // --------------------------------------
1.15 // Check for float->int copy; requires a trip through memory
1.16 - if( src_first_rc == rc_float && dst_first_rc == rc_int ) {
1.17 + if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1.18 int offset = frame::register_save_words*wordSize;
1.19 - if( cbuf ) {
1.20 + if (cbuf) {
1.21 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1.22 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1.23 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1.24 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1.25 }
1.26 #ifndef PRODUCT
1.27 - else if( !do_size ) {
1.28 - if( size != 0 ) st->print("\n\t");
1.29 + else if (!do_size) {
1.30 + if (size != 0) st->print("\n\t");
1.31 st->print( "SUB R_SP,16,R_SP\n");
1.32 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1.33 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1.34 @@ -1346,6 +1346,21 @@
1.35 size += 16;
1.36 }
1.37
1.38 + // Check for float->int copy on T4
1.39 + if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1.40 + // Further check for aligned-adjacent pair, so we can use a double move
1.41 + if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1.42 + return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1.43 + size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1.44 + }
1.45 + // Check for int->float copy on T4
1.46 + if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1.47 + // Further check for aligned-adjacent pair, so we can use a double move
1.48 + if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1.49 + return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1.50 + size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1.51 + }
1.52 +
1.53 // --------------------------------------
1.54 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1.55 // In such cases, I have to do the big-endian swap. For aligned targets, the
1.56 @@ -8164,6 +8179,155 @@
1.57 ins_pipe( cadd_cmpltmask );
1.58 %}
1.59
1.60 +
1.61 +//-----------------------------------------------------------------
1.62 +// Direct raw moves between float and general registers using VIS3.
1.63 +
1.64 +// ins_pipe(faddF_reg);
1.65 +instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
1.66 + predicate(UseVIS >= 3);
1.67 + match(Set dst (MoveF2I src));
1.68 +
1.69 + format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
1.70 + ins_encode %{
1.71 + __ movstouw($src$$FloatRegister, $dst$$Register);
1.72 + %}
1.73 + ins_pipe(ialu_reg_reg);
1.74 +%}
1.75 +
1.76 +instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
1.77 + predicate(UseVIS >= 3);
1.78 + match(Set dst (MoveI2F src));
1.79 +
1.80 + format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
1.81 + ins_encode %{
1.82 + __ movwtos($src$$Register, $dst$$FloatRegister);
1.83 + %}
1.84 + ins_pipe(ialu_reg_reg);
1.85 +%}
1.86 +
1.87 +instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
1.88 + predicate(UseVIS >= 3);
1.89 + match(Set dst (MoveD2L src));
1.90 +
1.91 + format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
1.92 + ins_encode %{
1.93 + __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
1.94 + %}
1.95 + ins_pipe(ialu_reg_reg);
1.96 +%}
1.97 +
1.98 +instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
1.99 + predicate(UseVIS >= 3);
1.100 + match(Set dst (MoveL2D src));
1.101 +
1.102 + format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
1.103 + ins_encode %{
1.104 + __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
1.105 + %}
1.106 + ins_pipe(ialu_reg_reg);
1.107 +%}
1.108 +
1.109 +
1.110 +// Raw moves between float and general registers using stack.
1.111 +
1.112 +instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
1.113 + match(Set dst (MoveF2I src));
1.114 + effect(DEF dst, USE src);
1.115 + ins_cost(MEMORY_REF_COST);
1.116 +
1.117 + size(4);
1.118 + format %{ "LDUW $src,$dst\t! MoveF2I" %}
1.119 + opcode(Assembler::lduw_op3);
1.120 + ins_encode(simple_form3_mem_reg( src, dst ) );
1.121 + ins_pipe(iload_mem);
1.122 +%}
1.123 +
1.124 +instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
1.125 + match(Set dst (MoveI2F src));
1.126 + effect(DEF dst, USE src);
1.127 + ins_cost(MEMORY_REF_COST);
1.128 +
1.129 + size(4);
1.130 + format %{ "LDF $src,$dst\t! MoveI2F" %}
1.131 + opcode(Assembler::ldf_op3);
1.132 + ins_encode(simple_form3_mem_reg(src, dst));
1.133 + ins_pipe(floadF_stk);
1.134 +%}
1.135 +
1.136 +instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
1.137 + match(Set dst (MoveD2L src));
1.138 + effect(DEF dst, USE src);
1.139 + ins_cost(MEMORY_REF_COST);
1.140 +
1.141 + size(4);
1.142 + format %{ "LDX $src,$dst\t! MoveD2L" %}
1.143 + opcode(Assembler::ldx_op3);
1.144 + ins_encode(simple_form3_mem_reg( src, dst ) );
1.145 + ins_pipe(iload_mem);
1.146 +%}
1.147 +
1.148 +instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
1.149 + match(Set dst (MoveL2D src));
1.150 + effect(DEF dst, USE src);
1.151 + ins_cost(MEMORY_REF_COST);
1.152 +
1.153 + size(4);
1.154 + format %{ "LDDF $src,$dst\t! MoveL2D" %}
1.155 + opcode(Assembler::lddf_op3);
1.156 + ins_encode(simple_form3_mem_reg(src, dst));
1.157 + ins_pipe(floadD_stk);
1.158 +%}
1.159 +
1.160 +instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
1.161 + match(Set dst (MoveF2I src));
1.162 + effect(DEF dst, USE src);
1.163 + ins_cost(MEMORY_REF_COST);
1.164 +
1.165 + size(4);
1.166 + format %{ "STF $src,$dst\t! MoveF2I" %}
1.167 + opcode(Assembler::stf_op3);
1.168 + ins_encode(simple_form3_mem_reg(dst, src));
1.169 + ins_pipe(fstoreF_stk_reg);
1.170 +%}
1.171 +
1.172 +instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
1.173 + match(Set dst (MoveI2F src));
1.174 + effect(DEF dst, USE src);
1.175 + ins_cost(MEMORY_REF_COST);
1.176 +
1.177 + size(4);
1.178 + format %{ "STW $src,$dst\t! MoveI2F" %}
1.179 + opcode(Assembler::stw_op3);
1.180 + ins_encode(simple_form3_mem_reg( dst, src ) );
1.181 + ins_pipe(istore_mem_reg);
1.182 +%}
1.183 +
1.184 +instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
1.185 + match(Set dst (MoveD2L src));
1.186 + effect(DEF dst, USE src);
1.187 + ins_cost(MEMORY_REF_COST);
1.188 +
1.189 + size(4);
1.190 + format %{ "STDF $src,$dst\t! MoveD2L" %}
1.191 + opcode(Assembler::stdf_op3);
1.192 + ins_encode(simple_form3_mem_reg(dst, src));
1.193 + ins_pipe(fstoreD_stk_reg);
1.194 +%}
1.195 +
1.196 +instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
1.197 + match(Set dst (MoveL2D src));
1.198 + effect(DEF dst, USE src);
1.199 + ins_cost(MEMORY_REF_COST);
1.200 +
1.201 + size(4);
1.202 + format %{ "STX $src,$dst\t! MoveL2D" %}
1.203 + opcode(Assembler::stx_op3);
1.204 + ins_encode(simple_form3_mem_reg( dst, src ) );
1.205 + ins_pipe(istore_mem_reg);
1.206 +%}
1.207 +
1.208 +
1.209 //----------Arithmetic Conversion Instructions---------------------------------
1.210 // The conversions operations are all Alpha sorted. Please keep it that way!
1.211
1.212 @@ -8191,7 +8355,7 @@
1.213 ins_pipe(fcvtD2I);
1.214 %}
1.215
1.216 -instruct convD2I_reg(stackSlotI dst, regD src) %{
1.217 +instruct convD2I_stk(stackSlotI dst, regD src) %{
1.218 match(Set dst (ConvD2I src));
1.219 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
1.220 expand %{
1.221 @@ -8201,6 +8365,18 @@
1.222 %}
1.223 %}
1.224
1.225 +instruct convD2I_reg(iRegI dst, regD src) %{
1.226 + predicate(UseVIS >= 3);
1.227 + match(Set dst (ConvD2I src));
1.228 + ins_cost(DEFAULT_COST*2 + BRANCH_COST);
1.229 + expand %{
1.230 + regF tmp;
1.231 + convD2I_helper(tmp, src);
1.232 + MoveF2I_reg_reg(dst, tmp);
1.233 + %}
1.234 +%}
1.235 +
1.236 +
1.237 // Convert a double to a long in a double register.
1.238 // If the double is a NAN, stuff a zero in instead.
1.239 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
1.240 @@ -8215,9 +8391,7 @@
1.241 ins_pipe(fcvtD2L);
1.242 %}
1.243
1.244 -
1.245 -// Double to Long conversion
1.246 -instruct convD2L_reg(stackSlotL dst, regD src) %{
1.247 +instruct convD2L_stk(stackSlotL dst, regD src) %{
1.248 match(Set dst (ConvD2L src));
1.249 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
1.250 expand %{
1.251 @@ -8227,6 +8401,17 @@
1.252 %}
1.253 %}
1.254
1.255 +instruct convD2L_reg(iRegL dst, regD src) %{
1.256 + predicate(UseVIS >= 3);
1.257 + match(Set dst (ConvD2L src));
1.258 + ins_cost(DEFAULT_COST*2 + BRANCH_COST);
1.259 + expand %{
1.260 + regD tmp;
1.261 + convD2L_helper(tmp, src);
1.262 + MoveD2L_reg_reg(dst, tmp);
1.263 + %}
1.264 +%}
1.265 +
1.266
1.267 instruct convF2D_reg(regD dst, regF src) %{
1.268 match(Set dst (ConvF2D src));
1.269 @@ -8237,6 +8422,8 @@
1.270 %}
1.271
1.272
1.273 +// Convert a float to an int in a float register.
1.274 +// If the float is a NAN, stuff a zero in instead.
1.275 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
1.276 effect(DEF dst, USE src, KILL fcc0);
1.277 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
1.278 @@ -8249,7 +8436,7 @@
1.279 ins_pipe(fcvtF2I);
1.280 %}
1.281
1.282 -instruct convF2I_reg(stackSlotI dst, regF src) %{
1.283 +instruct convF2I_stk(stackSlotI dst, regF src) %{
1.284 match(Set dst (ConvF2I src));
1.285 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
1.286 expand %{
1.287 @@ -8259,7 +8446,20 @@
1.288 %}
1.289 %}
1.290
1.291 -
1.292 +instruct convF2I_reg(iRegI dst, regF src) %{
1.293 + predicate(UseVIS >= 3);
1.294 + match(Set dst (ConvF2I src));
1.295 + ins_cost(DEFAULT_COST*2 + BRANCH_COST);
1.296 + expand %{
1.297 + regF tmp;
1.298 + convF2I_helper(tmp, src);
1.299 + MoveF2I_reg_reg(dst, tmp);
1.300 + %}
1.301 +%}
1.302 +
1.303 +
1.304 +// Convert a float to a long in a float register.
1.305 +// If the float is a NAN, stuff a zero in instead.
1.306 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
1.307 effect(DEF dst, USE src, KILL fcc0);
1.308 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
1.309 @@ -8272,8 +8472,7 @@
1.310 ins_pipe(fcvtF2L);
1.311 %}
1.312
1.313 -// Float to Long conversion
1.314 -instruct convF2L_reg(stackSlotL dst, regF src) %{
1.315 +instruct convF2L_stk(stackSlotL dst, regF src) %{
1.316 match(Set dst (ConvF2L src));
1.317 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
1.318 expand %{
1.319 @@ -8283,6 +8482,17 @@
1.320 %}
1.321 %}
1.322
1.323 +instruct convF2L_reg(iRegL dst, regF src) %{
1.324 + predicate(UseVIS >= 3);
1.325 + match(Set dst (ConvF2L src));
1.326 + ins_cost(DEFAULT_COST*2 + BRANCH_COST);
1.327 + expand %{
1.328 + regD tmp;
1.329 + convF2L_helper(tmp, src);
1.330 + MoveD2L_reg_reg(dst, tmp);
1.331 + %}
1.332 +%}
1.333 +
1.334
1.335 instruct convI2D_helper(regD dst, regF tmp) %{
1.336 effect(USE tmp, DEF dst);
1.337 @@ -8292,17 +8502,27 @@
1.338 ins_pipe(fcvtI2D);
1.339 %}
1.340
1.341 -instruct convI2D_reg(stackSlotI src, regD dst) %{
1.342 +instruct convI2D_stk(stackSlotI src, regD dst) %{
1.343 match(Set dst (ConvI2D src));
1.344 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
1.345 expand %{
1.346 regF tmp;
1.347 - stkI_to_regF( tmp, src);
1.348 - convI2D_helper( dst, tmp);
1.349 - %}
1.350 -%}
1.351 -
1.352 -instruct convI2D_mem( regD_low dst, memory mem ) %{
1.353 + stkI_to_regF(tmp, src);
1.354 + convI2D_helper(dst, tmp);
1.355 + %}
1.356 +%}
1.357 +
1.358 +instruct convI2D_reg(regD_low dst, iRegI src) %{
1.359 + predicate(UseVIS >= 3);
1.360 + match(Set dst (ConvI2D src));
1.361 + expand %{
1.362 + regF tmp;
1.363 + MoveI2F_reg_reg(tmp, src);
1.364 + convI2D_helper(dst, tmp);
1.365 + %}
1.366 +%}
1.367 +
1.368 +instruct convI2D_mem(regD_low dst, memory mem) %{
1.369 match(Set dst (ConvI2D (LoadI mem)));
1.370 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
1.371 size(8);
1.372 @@ -8322,7 +8542,7 @@
1.373 ins_pipe(fcvtI2F);
1.374 %}
1.375
1.376 -instruct convI2F_reg( regF dst, stackSlotI src ) %{
1.377 +instruct convI2F_stk(regF dst, stackSlotI src) %{
1.378 match(Set dst (ConvI2F src));
1.379 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
1.380 expand %{
1.381 @@ -8332,6 +8552,17 @@
1.382 %}
1.383 %}
1.384
1.385 +instruct convI2F_reg(regF dst, iRegI src) %{
1.386 + predicate(UseVIS >= 3);
1.387 + match(Set dst (ConvI2F src));
1.388 + ins_cost(DEFAULT_COST);
1.389 + expand %{
1.390 + regF tmp;
1.391 + MoveI2F_reg_reg(tmp, src);
1.392 + convI2F_helper(dst, tmp);
1.393 + %}
1.394 +%}
1.395 +
1.396 instruct convI2F_mem( regF dst, memory mem ) %{
1.397 match(Set dst (ConvI2F (LoadI mem)));
1.398 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
1.399 @@ -8373,102 +8604,6 @@
1.400 ins_pipe(ialu_reg_reg);
1.401 %}
1.402
1.403 -instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
1.404 - match(Set dst (MoveF2I src));
1.405 - effect(DEF dst, USE src);
1.406 - ins_cost(MEMORY_REF_COST);
1.407 -
1.408 - size(4);
1.409 - format %{ "LDUW $src,$dst\t! MoveF2I" %}
1.410 - opcode(Assembler::lduw_op3);
1.411 - ins_encode(simple_form3_mem_reg( src, dst ) );
1.412 - ins_pipe(iload_mem);
1.413 -%}
1.414 -
1.415 -instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
1.416 - match(Set dst (MoveI2F src));
1.417 - effect(DEF dst, USE src);
1.418 - ins_cost(MEMORY_REF_COST);
1.419 -
1.420 - size(4);
1.421 - format %{ "LDF $src,$dst\t! MoveI2F" %}
1.422 - opcode(Assembler::ldf_op3);
1.423 - ins_encode(simple_form3_mem_reg(src, dst));
1.424 - ins_pipe(floadF_stk);
1.425 -%}
1.426 -
1.427 -instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
1.428 - match(Set dst (MoveD2L src));
1.429 - effect(DEF dst, USE src);
1.430 - ins_cost(MEMORY_REF_COST);
1.431 -
1.432 - size(4);
1.433 - format %{ "LDX $src,$dst\t! MoveD2L" %}
1.434 - opcode(Assembler::ldx_op3);
1.435 - ins_encode(simple_form3_mem_reg( src, dst ) );
1.436 - ins_pipe(iload_mem);
1.437 -%}
1.438 -
1.439 -instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
1.440 - match(Set dst (MoveL2D src));
1.441 - effect(DEF dst, USE src);
1.442 - ins_cost(MEMORY_REF_COST);
1.443 -
1.444 - size(4);
1.445 - format %{ "LDDF $src,$dst\t! MoveL2D" %}
1.446 - opcode(Assembler::lddf_op3);
1.447 - ins_encode(simple_form3_mem_reg(src, dst));
1.448 - ins_pipe(floadD_stk);
1.449 -%}
1.450 -
1.451 -instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
1.452 - match(Set dst (MoveF2I src));
1.453 - effect(DEF dst, USE src);
1.454 - ins_cost(MEMORY_REF_COST);
1.455 -
1.456 - size(4);
1.457 - format %{ "STF $src,$dst\t!MoveF2I" %}
1.458 - opcode(Assembler::stf_op3);
1.459 - ins_encode(simple_form3_mem_reg(dst, src));
1.460 - ins_pipe(fstoreF_stk_reg);
1.461 -%}
1.462 -
1.463 -instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
1.464 - match(Set dst (MoveI2F src));
1.465 - effect(DEF dst, USE src);
1.466 - ins_cost(MEMORY_REF_COST);
1.467 -
1.468 - size(4);
1.469 - format %{ "STW $src,$dst\t!MoveI2F" %}
1.470 - opcode(Assembler::stw_op3);
1.471 - ins_encode(simple_form3_mem_reg( dst, src ) );
1.472 - ins_pipe(istore_mem_reg);
1.473 -%}
1.474 -
1.475 -instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
1.476 - match(Set dst (MoveD2L src));
1.477 - effect(DEF dst, USE src);
1.478 - ins_cost(MEMORY_REF_COST);
1.479 -
1.480 - size(4);
1.481 - format %{ "STDF $src,$dst\t!MoveD2L" %}
1.482 - opcode(Assembler::stdf_op3);
1.483 - ins_encode(simple_form3_mem_reg(dst, src));
1.484 - ins_pipe(fstoreD_stk_reg);
1.485 -%}
1.486 -
1.487 -instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
1.488 - match(Set dst (MoveL2D src));
1.489 - effect(DEF dst, USE src);
1.490 - ins_cost(MEMORY_REF_COST);
1.491 -
1.492 - size(4);
1.493 - format %{ "STX $src,$dst\t!MoveL2D" %}
1.494 - opcode(Assembler::stx_op3);
1.495 - ins_encode(simple_form3_mem_reg( dst, src ) );
1.496 - ins_pipe(istore_mem_reg);
1.497 -%}
1.498 -
1.499
1.500 //-----------
1.501 // Long to Double conversion using V8 opcodes.
1.502 @@ -8589,7 +8724,7 @@
1.503 ins_pipe(fcvtL2D);
1.504 %}
1.505
1.506 -instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{
1.507 +instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
1.508 predicate(VM_Version::has_fast_fxtof());
1.509 match(Set dst (ConvL2D src));
1.510 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
1.511 @@ -8600,10 +8735,15 @@
1.512 %}
1.513 %}
1.514
1.515 -//-----------
1.516 -// Long to Float conversion using V8 opcodes.
1.517 -// Still useful because cheetah traps and becomes
1.518 -// amazingly slow for some common numbers.
1.519 +instruct convL2D_reg(regD dst, iRegL src) %{
1.520 + predicate(UseVIS >= 3);
1.521 + match(Set dst (ConvL2D src));
1.522 + expand %{
1.523 + regD tmp;
1.524 + MoveL2D_reg_reg(tmp, src);
1.525 + convL2D_helper(dst, tmp);
1.526 + %}
1.527 +%}
1.528
1.529 // Long to Float conversion using fast fxtof
1.530 instruct convL2F_helper(regF dst, regD tmp) %{
1.531 @@ -8615,7 +8755,7 @@
1.532 ins_pipe(fcvtL2F);
1.533 %}
1.534
1.535 -instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{
1.536 +instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
1.537 match(Set dst (ConvL2F src));
1.538 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
1.539 expand %{
1.540 @@ -8624,6 +8764,18 @@
1.541 convL2F_helper(dst, tmp);
1.542 %}
1.543 %}
1.544 +
1.545 +instruct convL2F_reg(regF dst, iRegL src) %{
1.546 + predicate(UseVIS >= 3);
1.547 + match(Set dst (ConvL2F src));
1.548 + ins_cost(DEFAULT_COST);
1.549 + expand %{
1.550 + regD tmp;
1.551 + MoveL2D_reg_reg(tmp, src);
1.552 + convL2F_helper(dst, tmp);
1.553 + %}
1.554 +%}
1.555 +
1.556 //-----------
1.557
1.558 instruct convL2I_reg(iRegI dst, iRegL src) %{
