1.1 --- a/src/cpu/sparc/vm/assembler_sparc.hpp Thu Jul 07 10:51:07 2011 -0700
1.2 +++ b/src/cpu/sparc/vm/assembler_sparc.hpp Fri Jul 08 09:38:48 2011 -0700
1.3 @@ -716,6 +716,8 @@
1.4 casa_op3 = 0x3c,
1.5 casxa_op3 = 0x3e,
1.6
1.7 + mftoi_op3 = 0x36,
1.8 +
1.9 alt_bit_op3 = 0x10,
1.10 cc_bit_op3 = 0x10
1.11 };
1.12 @@ -750,7 +752,13 @@
1.13 fitod_opf = 0xc8,
1.14 fstod_opf = 0xc9,
1.15 fstoi_opf = 0xd1,
1.16 - fdtoi_opf = 0xd2
1.17 + fdtoi_opf = 0xd2,
1.18 +
1.19 + mdtox_opf = 0x110,
1.20 + mstouw_opf = 0x111,
1.21 + mstosw_opf = 0x113,
1.22 + mxtod_opf = 0x118,
1.23 + mwtos_opf = 0x119
1.24 };
1.25
1.26 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7 };
1.27 @@ -1061,6 +1069,9 @@
1.28 return x & ((1 << 10) - 1);
1.29 }
1.30
1.31 + // instruction only in VIS3
1.32 + static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
1.33 +
1.34 // instruction only in v9
1.35 static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); }
1.36
1.37 @@ -1247,8 +1258,8 @@
1.38
1.39 // pp 159
1.40
1.41 - void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
1.42 - void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
1.43 + void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
1.44 + void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
1.45
1.46 // pp 160
1.47
1.48 @@ -1256,8 +1267,8 @@
1.49
1.50 // pp 161
1.51
1.52 - void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, w)); }
1.53 - void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, w)); }
1.54 + void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); }
1.55 + void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); }
1.56
1.57 // pp 162
1.58
1.59 @@ -1709,6 +1720,19 @@
1.60 inline void wrasi( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
1.61 inline void wrfprs( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1.62
1.63 +
1.64 + // VIS3 instructions
1.65 +
1.66 + void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_long( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
1.67 + void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_long( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
1.68 + void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_long( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
1.69 +
1.70 + void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_long( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
1.71 + void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_long( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
1.72 +
1.73 +
1.74 +
1.75 +
1.76 // For a given register condition, return the appropriate condition code
1.77 // Condition (the one you would use to get the same effect after "tst" on
1.78 // the target register.)
