1.1 --- a/src/cpu/x86/vm/icache_x86.hpp Tue Nov 23 15:01:43 2010 -0500
1.2 +++ b/src/cpu/x86/vm/icache_x86.hpp Tue Nov 23 13:22:55 2010 -0800
1.3 @@ -1,5 +1,5 @@
1.4 /*
1.5 - * Copyright (c) 1997, 2004, Oracle and/or its affiliates. All rights reserved.
1.6 + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
1.7 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.8 *
1.9 * This code is free software; you can redistribute it and/or modify it
1.10 @@ -22,6 +22,9 @@
1.11 *
1.12 */
1.13
1.14 +#ifndef CPU_X86_VM_ICACHE_X86_HPP
1.15 +#define CPU_X86_VM_ICACHE_X86_HPP
1.16 +
1.17 // Interface for updating the instruction cache. Whenever the VM modifies
1.18 // code, part of the processor instruction cache potentially has to be flushed.
1.19
1.20 @@ -53,3 +56,5 @@
1.21 };
1.22 #endif // AMD64
1.23 };
1.24 +
1.25 +#endif // CPU_X86_VM_ICACHE_X86_HPP
