1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/share/vm/c1/c1_Defs.hpp Wed Apr 27 01:25:04 2016 +0800
1.3 @@ -0,0 +1,85 @@
1.4 +/*
1.5 + * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved.
1.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.7 + *
1.8 + * This code is free software; you can redistribute it and/or modify it
1.9 + * under the terms of the GNU General Public License version 2 only, as
1.10 + * published by the Free Software Foundation.
1.11 + *
1.12 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.14 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.15 + * version 2 for more details (a copy is included in the LICENSE file that
1.16 + * accompanied this code).
1.17 + *
1.18 + * You should have received a copy of the GNU General Public License version
1.19 + * 2 along with this work; if not, write to the Free Software Foundation,
1.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.21 + *
1.22 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1.23 + * or visit www.oracle.com if you need additional information or have any
1.24 + * questions.
1.25 + *
1.26 + */
1.27 +
1.28 +#ifndef SHARE_VM_C1_C1_DEFS_HPP
1.29 +#define SHARE_VM_C1_C1_DEFS_HPP
1.30 +
1.31 +#include "utilities/globalDefinitions.hpp"
1.32 +#ifdef TARGET_ARCH_x86
1.33 +# include "register_x86.hpp"
1.34 +#endif
1.35 +#ifdef TARGET_ARCH_sparc
1.36 +# include "register_sparc.hpp"
1.37 +#endif
1.38 +#ifdef TARGET_ARCH_zero
1.39 +# include "register_zero.hpp"
1.40 +#endif
1.41 +#ifdef TARGET_ARCH_arm
1.42 +# include "register_arm.hpp"
1.43 +#endif
1.44 +#ifdef TARGET_ARCH_ppc
1.45 +# include "register_ppc.hpp"
1.46 +#endif
1.47 +
1.48 +// set frame size and return address offset to these values in blobs
1.49 +// (if the compiled frame uses ebp as link pointer on IA; otherwise,
1.50 +// the frame size must be fixed)
1.51 +enum {
1.52 + no_frame_size = -1
1.53 +};
1.54 +
1.55 +
1.56 +#ifdef TARGET_ARCH_x86
1.57 +# include "c1_Defs_x86.hpp"
1.58 +#endif
1.59 +#ifdef TARGET_ARCH_sparc
1.60 +# include "c1_Defs_sparc.hpp"
1.61 +#endif
1.62 +#ifdef TARGET_ARCH_arm
1.63 +# include "c1_Defs_arm.hpp"
1.64 +#endif
1.65 +#ifdef TARGET_ARCH_ppc
1.66 +# include "c1_Defs_ppc.hpp"
1.67 +#endif
1.68 +
1.69 +
1.70 +// native word offsets from memory address
1.71 +enum {
1.72 + lo_word_offset_in_bytes = pd_lo_word_offset_in_bytes,
1.73 + hi_word_offset_in_bytes = pd_hi_word_offset_in_bytes
1.74 +};
1.75 +
1.76 +
1.77 +// the processor may require explicit rounding operations to implement the strictFP mode
1.78 +enum {
1.79 + strict_fp_requires_explicit_rounding = pd_strict_fp_requires_explicit_rounding
1.80 +};
1.81 +
1.82 +
1.83 +// for debug info: a float value in a register may be saved in double precision by runtime stubs
1.84 +enum {
1.85 + float_saved_as_double = pd_float_saved_as_double
1.86 +};
1.87 +
1.88 +#endif // SHARE_VM_C1_C1_DEFS_HPP
