1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/cpu/x86/vm/vmreg_x86.inline.hpp Wed Apr 27 01:25:04 2016 +0800
1.3 @@ -0,0 +1,89 @@
1.4 +/*
1.5 + * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved.
1.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.7 + *
1.8 + * This code is free software; you can redistribute it and/or modify it
1.9 + * under the terms of the GNU General Public License version 2 only, as
1.10 + * published by the Free Software Foundation.
1.11 + *
1.12 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.14 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.15 + * version 2 for more details (a copy is included in the LICENSE file that
1.16 + * accompanied this code).
1.17 + *
1.18 + * You should have received a copy of the GNU General Public License version
1.19 + * 2 along with this work; if not, write to the Free Software Foundation,
1.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.21 + *
1.22 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1.23 + * or visit www.oracle.com if you need additional information or have any
1.24 + * questions.
1.25 + *
1.26 + */
1.27 +
1.28 +#ifndef CPU_X86_VM_VMREG_X86_INLINE_HPP
1.29 +#define CPU_X86_VM_VMREG_X86_INLINE_HPP
1.30 +
1.31 +inline VMReg RegisterImpl::as_VMReg() {
1.32 + if( this==noreg ) return VMRegImpl::Bad();
1.33 +#ifdef AMD64
1.34 + return VMRegImpl::as_VMReg(encoding() << 1 );
1.35 +#else
1.36 + return VMRegImpl::as_VMReg(encoding() );
1.37 +#endif // AMD64
1.38 +}
1.39 +
1.40 +inline VMReg FloatRegisterImpl::as_VMReg() {
1.41 + return VMRegImpl::as_VMReg((encoding() << 1) + ConcreteRegisterImpl::max_gpr);
1.42 +}
1.43 +
1.44 +inline VMReg XMMRegisterImpl::as_VMReg() {
1.45 + return VMRegImpl::as_VMReg((encoding() << 3) + ConcreteRegisterImpl::max_fpr);
1.46 +}
1.47 +
1.48 +
1.49 +inline bool VMRegImpl::is_Register() {
1.50 + return (unsigned int) value() < (unsigned int) ConcreteRegisterImpl::max_gpr;
1.51 +}
1.52 +
1.53 +inline bool VMRegImpl::is_FloatRegister() {
1.54 + return value() >= ConcreteRegisterImpl::max_gpr && value() < ConcreteRegisterImpl::max_fpr;
1.55 +}
1.56 +
1.57 +inline bool VMRegImpl::is_XMMRegister() {
1.58 + return value() >= ConcreteRegisterImpl::max_fpr && value() < ConcreteRegisterImpl::max_xmm;
1.59 +}
1.60 +
1.61 +inline Register VMRegImpl::as_Register() {
1.62 +
1.63 + assert( is_Register(), "must be");
1.64 + // Yuk
1.65 +#ifdef AMD64
1.66 + return ::as_Register(value() >> 1);
1.67 +#else
1.68 + return ::as_Register(value());
1.69 +#endif // AMD64
1.70 +}
1.71 +
1.72 +inline FloatRegister VMRegImpl::as_FloatRegister() {
1.73 + assert( is_FloatRegister() && is_even(value()), "must be" );
1.74 + // Yuk
1.75 + return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) >> 1);
1.76 +}
1.77 +
1.78 +inline XMMRegister VMRegImpl::as_XMMRegister() {
1.79 + assert( is_XMMRegister() && is_even(value()), "must be" );
1.80 + // Yuk
1.81 + return ::as_XMMRegister((value() - ConcreteRegisterImpl::max_fpr) >> 3);
1.82 +}
1.83 +
1.84 +inline bool VMRegImpl::is_concrete() {
1.85 + assert(is_reg(), "must be");
1.86 +#ifndef AMD64
1.87 + if (is_Register()) return true;
1.88 +#endif // AMD64
1.89 + return is_even(value());
1.90 +}
1.91 +
1.92 +#endif // CPU_X86_VM_VMREG_X86_INLINE_HPP
