1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/cpu/x86/vm/c1_FrameMap_x86.hpp Wed Apr 27 01:25:04 2016 +0800
1.3 @@ -0,0 +1,160 @@
1.4 +/*
1.5 + * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved.
1.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.7 + *
1.8 + * This code is free software; you can redistribute it and/or modify it
1.9 + * under the terms of the GNU General Public License version 2 only, as
1.10 + * published by the Free Software Foundation.
1.11 + *
1.12 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.14 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.15 + * version 2 for more details (a copy is included in the LICENSE file that
1.16 + * accompanied this code).
1.17 + *
1.18 + * You should have received a copy of the GNU General Public License version
1.19 + * 2 along with this work; if not, write to the Free Software Foundation,
1.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.21 + *
1.22 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1.23 + * or visit www.oracle.com if you need additional information or have any
1.24 + * questions.
1.25 + *
1.26 + */
1.27 +
1.28 +#ifndef CPU_X86_VM_C1_FRAMEMAP_X86_HPP
1.29 +#define CPU_X86_VM_C1_FRAMEMAP_X86_HPP
1.30 +
1.31 +// On i486 the frame looks as follows:
1.32 +//
1.33 +// +-----------------------------+---------+----------------------------------------+----------------+-----------
1.34 +// | size_arguments-nof_reg_args | 2 words | size_locals-size_arguments+numreg_args | _size_monitors | spilling .
1.35 +// +-----------------------------+---------+----------------------------------------+----------------+-----------
1.36 +//
1.37 +// The FPU registers are mapped with their offset from TOS; therefore the
1.38 +// status of FPU stack must be updated during code emission.
1.39 +
1.40 + public:
1.41 + static const int pd_c_runtime_reserved_arg_size;
1.42 +
1.43 + enum {
1.44 + nof_xmm_regs = pd_nof_xmm_regs_frame_map,
1.45 + nof_caller_save_xmm_regs = pd_nof_caller_save_xmm_regs_frame_map,
1.46 + first_available_sp_in_frame = 0,
1.47 +#ifndef _LP64
1.48 + frame_pad_in_bytes = 8,
1.49 + nof_reg_args = 2
1.50 +#else
1.51 + frame_pad_in_bytes = 16,
1.52 + nof_reg_args = 6
1.53 +#endif // _LP64
1.54 + };
1.55 +
1.56 + private:
1.57 + static LIR_Opr _caller_save_xmm_regs [nof_caller_save_xmm_regs];
1.58 +
1.59 + static XMMRegister _xmm_regs[nof_xmm_regs];
1.60 +
1.61 + public:
1.62 + static LIR_Opr receiver_opr;
1.63 +
1.64 + static LIR_Opr rsi_opr;
1.65 + static LIR_Opr rdi_opr;
1.66 + static LIR_Opr rbx_opr;
1.67 + static LIR_Opr rax_opr;
1.68 + static LIR_Opr rdx_opr;
1.69 + static LIR_Opr rcx_opr;
1.70 + static LIR_Opr rsp_opr;
1.71 + static LIR_Opr rbp_opr;
1.72 +
1.73 + static LIR_Opr rsi_oop_opr;
1.74 + static LIR_Opr rdi_oop_opr;
1.75 + static LIR_Opr rbx_oop_opr;
1.76 + static LIR_Opr rax_oop_opr;
1.77 + static LIR_Opr rdx_oop_opr;
1.78 + static LIR_Opr rcx_oop_opr;
1.79 +
1.80 + static LIR_Opr rsi_metadata_opr;
1.81 + static LIR_Opr rdi_metadata_opr;
1.82 + static LIR_Opr rbx_metadata_opr;
1.83 + static LIR_Opr rax_metadata_opr;
1.84 + static LIR_Opr rdx_metadata_opr;
1.85 + static LIR_Opr rcx_metadata_opr;
1.86 +
1.87 +#ifdef _LP64
1.88 +
1.89 + static LIR_Opr r8_opr;
1.90 + static LIR_Opr r9_opr;
1.91 + static LIR_Opr r10_opr;
1.92 + static LIR_Opr r11_opr;
1.93 + static LIR_Opr r12_opr;
1.94 + static LIR_Opr r13_opr;
1.95 + static LIR_Opr r14_opr;
1.96 + static LIR_Opr r15_opr;
1.97 +
1.98 + static LIR_Opr r8_oop_opr;
1.99 + static LIR_Opr r9_oop_opr;
1.100 +
1.101 + static LIR_Opr r11_oop_opr;
1.102 + static LIR_Opr r12_oop_opr;
1.103 + static LIR_Opr r13_oop_opr;
1.104 + static LIR_Opr r14_oop_opr;
1.105 +
1.106 + static LIR_Opr r8_metadata_opr;
1.107 + static LIR_Opr r9_metadata_opr;
1.108 +
1.109 + static LIR_Opr r11_metadata_opr;
1.110 + static LIR_Opr r12_metadata_opr;
1.111 + static LIR_Opr r13_metadata_opr;
1.112 + static LIR_Opr r14_metadata_opr;
1.113 +
1.114 +#endif // _LP64
1.115 +
1.116 + static LIR_Opr long0_opr;
1.117 + static LIR_Opr long1_opr;
1.118 + static LIR_Opr fpu0_float_opr;
1.119 + static LIR_Opr fpu0_double_opr;
1.120 + static LIR_Opr xmm0_float_opr;
1.121 + static LIR_Opr xmm0_double_opr;
1.122 +
1.123 +#ifdef _LP64
1.124 + static LIR_Opr as_long_opr(Register r) {
1.125 + return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
1.126 + }
1.127 + static LIR_Opr as_pointer_opr(Register r) {
1.128 + return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
1.129 + }
1.130 +#else
1.131 + static LIR_Opr as_long_opr(Register r, Register r2) {
1.132 + return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r2));
1.133 + }
1.134 + static LIR_Opr as_pointer_opr(Register r) {
1.135 + return LIR_OprFact::single_cpu(cpu_reg2rnr(r));
1.136 + }
1.137 +#endif // _LP64
1.138 +
1.139 + // VMReg name for spilled physical FPU stack slot n
1.140 + static VMReg fpu_regname (int n);
1.141 +
1.142 + static XMMRegister nr2xmmreg(int rnr);
1.143 +
1.144 + static bool is_caller_save_register (LIR_Opr opr) { return true; }
1.145 + static bool is_caller_save_register (Register r) { return true; }
1.146 +
1.147 + static LIR_Opr caller_save_xmm_reg_at(int i) {
1.148 + assert(i >= 0 && i < nof_caller_save_xmm_regs, "out of bounds");
1.149 + return _caller_save_xmm_regs[i];
1.150 + }
1.151 +
1.152 + static int adjust_reg_range(int range) {
1.153 + // Reduce the number of available regs (to free r12) in case of compressed oops
1.154 + if (UseCompressedOops || UseCompressedClassPointers) return range - 1;
1.155 + return range;
1.156 + }
1.157 +
1.158 + static int nof_caller_save_cpu_regs() { return adjust_reg_range(pd_nof_caller_save_cpu_regs_frame_map); }
1.159 + static int last_cpu_reg() { return adjust_reg_range(pd_last_cpu_reg); }
1.160 + static int last_byte_reg() { return adjust_reg_range(pd_last_byte_reg); }
1.161 +
1.162 +#endif // CPU_X86_VM_C1_FRAMEMAP_X86_HPP
1.163 +
