1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/cpu/x86/vm/c1_FrameMap_x86.cpp Wed Apr 27 01:25:04 2016 +0800
1.3 @@ -0,0 +1,356 @@
1.4 +/*
1.5 + * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved.
1.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.7 + *
1.8 + * This code is free software; you can redistribute it and/or modify it
1.9 + * under the terms of the GNU General Public License version 2 only, as
1.10 + * published by the Free Software Foundation.
1.11 + *
1.12 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.14 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.15 + * version 2 for more details (a copy is included in the LICENSE file that
1.16 + * accompanied this code).
1.17 + *
1.18 + * You should have received a copy of the GNU General Public License version
1.19 + * 2 along with this work; if not, write to the Free Software Foundation,
1.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.21 + *
1.22 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1.23 + * or visit www.oracle.com if you need additional information or have any
1.24 + * questions.
1.25 + *
1.26 + */
1.27 +
1.28 +#include "precompiled.hpp"
1.29 +#include "c1/c1_FrameMap.hpp"
1.30 +#include "c1/c1_LIR.hpp"
1.31 +#include "runtime/sharedRuntime.hpp"
1.32 +#include "vmreg_x86.inline.hpp"
1.33 +
1.34 +const int FrameMap::pd_c_runtime_reserved_arg_size = 0;
1.35 +
1.36 +LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool) {
1.37 + LIR_Opr opr = LIR_OprFact::illegalOpr;
1.38 + VMReg r_1 = reg->first();
1.39 + VMReg r_2 = reg->second();
1.40 + if (r_1->is_stack()) {
1.41 + // Convert stack slot to an SP offset
1.42 + // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value
1.43 + // so we must add it in here.
1.44 + int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
1.45 + opr = LIR_OprFact::address(new LIR_Address(rsp_opr, st_off, type));
1.46 + } else if (r_1->is_Register()) {
1.47 + Register reg = r_1->as_Register();
1.48 + if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
1.49 + Register reg2 = r_2->as_Register();
1.50 +#ifdef _LP64
1.51 + assert(reg2 == reg, "must be same register");
1.52 + opr = as_long_opr(reg);
1.53 +#else
1.54 + opr = as_long_opr(reg2, reg);
1.55 +#endif // _LP64
1.56 + } else if (type == T_OBJECT || type == T_ARRAY) {
1.57 + opr = as_oop_opr(reg);
1.58 + } else if (type == T_METADATA) {
1.59 + opr = as_metadata_opr(reg);
1.60 + } else {
1.61 + opr = as_opr(reg);
1.62 + }
1.63 + } else if (r_1->is_FloatRegister()) {
1.64 + assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
1.65 + int num = r_1->as_FloatRegister()->encoding();
1.66 + if (type == T_FLOAT) {
1.67 + opr = LIR_OprFact::single_fpu(num);
1.68 + } else {
1.69 + opr = LIR_OprFact::double_fpu(num);
1.70 + }
1.71 + } else if (r_1->is_XMMRegister()) {
1.72 + assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
1.73 + int num = r_1->as_XMMRegister()->encoding();
1.74 + if (type == T_FLOAT) {
1.75 + opr = LIR_OprFact::single_xmm(num);
1.76 + } else {
1.77 + opr = LIR_OprFact::double_xmm(num);
1.78 + }
1.79 + } else {
1.80 + ShouldNotReachHere();
1.81 + }
1.82 + return opr;
1.83 +}
1.84 +
1.85 +
1.86 +LIR_Opr FrameMap::rsi_opr;
1.87 +LIR_Opr FrameMap::rdi_opr;
1.88 +LIR_Opr FrameMap::rbx_opr;
1.89 +LIR_Opr FrameMap::rax_opr;
1.90 +LIR_Opr FrameMap::rdx_opr;
1.91 +LIR_Opr FrameMap::rcx_opr;
1.92 +LIR_Opr FrameMap::rsp_opr;
1.93 +LIR_Opr FrameMap::rbp_opr;
1.94 +
1.95 +LIR_Opr FrameMap::receiver_opr;
1.96 +
1.97 +LIR_Opr FrameMap::rsi_oop_opr;
1.98 +LIR_Opr FrameMap::rdi_oop_opr;
1.99 +LIR_Opr FrameMap::rbx_oop_opr;
1.100 +LIR_Opr FrameMap::rax_oop_opr;
1.101 +LIR_Opr FrameMap::rdx_oop_opr;
1.102 +LIR_Opr FrameMap::rcx_oop_opr;
1.103 +
1.104 +LIR_Opr FrameMap::rsi_metadata_opr;
1.105 +LIR_Opr FrameMap::rdi_metadata_opr;
1.106 +LIR_Opr FrameMap::rbx_metadata_opr;
1.107 +LIR_Opr FrameMap::rax_metadata_opr;
1.108 +LIR_Opr FrameMap::rdx_metadata_opr;
1.109 +LIR_Opr FrameMap::rcx_metadata_opr;
1.110 +
1.111 +LIR_Opr FrameMap::long0_opr;
1.112 +LIR_Opr FrameMap::long1_opr;
1.113 +LIR_Opr FrameMap::fpu0_float_opr;
1.114 +LIR_Opr FrameMap::fpu0_double_opr;
1.115 +LIR_Opr FrameMap::xmm0_float_opr;
1.116 +LIR_Opr FrameMap::xmm0_double_opr;
1.117 +
1.118 +#ifdef _LP64
1.119 +
1.120 +LIR_Opr FrameMap::r8_opr;
1.121 +LIR_Opr FrameMap::r9_opr;
1.122 +LIR_Opr FrameMap::r10_opr;
1.123 +LIR_Opr FrameMap::r11_opr;
1.124 +LIR_Opr FrameMap::r12_opr;
1.125 +LIR_Opr FrameMap::r13_opr;
1.126 +LIR_Opr FrameMap::r14_opr;
1.127 +LIR_Opr FrameMap::r15_opr;
1.128 +
1.129 +// r10 and r15 can never contain oops since they aren't available to
1.130 +// the allocator
1.131 +LIR_Opr FrameMap::r8_oop_opr;
1.132 +LIR_Opr FrameMap::r9_oop_opr;
1.133 +LIR_Opr FrameMap::r11_oop_opr;
1.134 +LIR_Opr FrameMap::r12_oop_opr;
1.135 +LIR_Opr FrameMap::r13_oop_opr;
1.136 +LIR_Opr FrameMap::r14_oop_opr;
1.137 +
1.138 +LIR_Opr FrameMap::r8_metadata_opr;
1.139 +LIR_Opr FrameMap::r9_metadata_opr;
1.140 +LIR_Opr FrameMap::r11_metadata_opr;
1.141 +LIR_Opr FrameMap::r12_metadata_opr;
1.142 +LIR_Opr FrameMap::r13_metadata_opr;
1.143 +LIR_Opr FrameMap::r14_metadata_opr;
1.144 +#endif // _LP64
1.145 +
1.146 +LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
1.147 +LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
1.148 +LIR_Opr FrameMap::_caller_save_xmm_regs[] = { 0, };
1.149 +
1.150 +XMMRegister FrameMap::_xmm_regs [] = { 0, };
1.151 +
1.152 +XMMRegister FrameMap::nr2xmmreg(int rnr) {
1.153 + assert(_init_done, "tables not initialized");
1.154 + return _xmm_regs[rnr];
1.155 +}
1.156 +
1.157 +//--------------------------------------------------------
1.158 +// FrameMap
1.159 +//--------------------------------------------------------
1.160 +
1.161 +void FrameMap::initialize() {
1.162 + assert(!_init_done, "once");
1.163 +
1.164 + assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers");
1.165 + map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0);
1.166 + map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1);
1.167 + map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2);
1.168 + map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3);
1.169 + map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4);
1.170 + map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5);
1.171 +
1.172 +#ifndef _LP64
1.173 + // The unallocatable registers are at the end
1.174 + map_register(6, rsp);
1.175 + map_register(7, rbp);
1.176 +#else
1.177 + map_register( 6, r8); r8_opr = LIR_OprFact::single_cpu(6);
1.178 + map_register( 7, r9); r9_opr = LIR_OprFact::single_cpu(7);
1.179 + map_register( 8, r11); r11_opr = LIR_OprFact::single_cpu(8);
1.180 + map_register( 9, r13); r13_opr = LIR_OprFact::single_cpu(9);
1.181 + map_register(10, r14); r14_opr = LIR_OprFact::single_cpu(10);
1.182 + // r12 is allocated conditionally. With compressed oops it holds
1.183 + // the heapbase value and is not visible to the allocator.
1.184 + map_register(11, r12); r12_opr = LIR_OprFact::single_cpu(11);
1.185 + // The unallocatable registers are at the end
1.186 + map_register(12, r10); r10_opr = LIR_OprFact::single_cpu(12);
1.187 + map_register(13, r15); r15_opr = LIR_OprFact::single_cpu(13);
1.188 + map_register(14, rsp);
1.189 + map_register(15, rbp);
1.190 +#endif // _LP64
1.191 +
1.192 +#ifdef _LP64
1.193 + long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 3 /*eax*/);
1.194 + long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 2 /*ebx*/);
1.195 +#else
1.196 + long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/);
1.197 + long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/);
1.198 +#endif // _LP64
1.199 + fpu0_float_opr = LIR_OprFact::single_fpu(0);
1.200 + fpu0_double_opr = LIR_OprFact::double_fpu(0);
1.201 + xmm0_float_opr = LIR_OprFact::single_xmm(0);
1.202 + xmm0_double_opr = LIR_OprFact::double_xmm(0);
1.203 +
1.204 + _caller_save_cpu_regs[0] = rsi_opr;
1.205 + _caller_save_cpu_regs[1] = rdi_opr;
1.206 + _caller_save_cpu_regs[2] = rbx_opr;
1.207 + _caller_save_cpu_regs[3] = rax_opr;
1.208 + _caller_save_cpu_regs[4] = rdx_opr;
1.209 + _caller_save_cpu_regs[5] = rcx_opr;
1.210 +
1.211 +#ifdef _LP64
1.212 + _caller_save_cpu_regs[6] = r8_opr;
1.213 + _caller_save_cpu_regs[7] = r9_opr;
1.214 + _caller_save_cpu_regs[8] = r11_opr;
1.215 + _caller_save_cpu_regs[9] = r13_opr;
1.216 + _caller_save_cpu_regs[10] = r14_opr;
1.217 + _caller_save_cpu_regs[11] = r12_opr;
1.218 +#endif // _LP64
1.219 +
1.220 +
1.221 + _xmm_regs[0] = xmm0;
1.222 + _xmm_regs[1] = xmm1;
1.223 + _xmm_regs[2] = xmm2;
1.224 + _xmm_regs[3] = xmm3;
1.225 + _xmm_regs[4] = xmm4;
1.226 + _xmm_regs[5] = xmm5;
1.227 + _xmm_regs[6] = xmm6;
1.228 + _xmm_regs[7] = xmm7;
1.229 +
1.230 +#ifdef _LP64
1.231 + _xmm_regs[8] = xmm8;
1.232 + _xmm_regs[9] = xmm9;
1.233 + _xmm_regs[10] = xmm10;
1.234 + _xmm_regs[11] = xmm11;
1.235 + _xmm_regs[12] = xmm12;
1.236 + _xmm_regs[13] = xmm13;
1.237 + _xmm_regs[14] = xmm14;
1.238 + _xmm_regs[15] = xmm15;
1.239 +#endif // _LP64
1.240 +
1.241 + for (int i = 0; i < 8; i++) {
1.242 + _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
1.243 + }
1.244 +
1.245 + for (int i = 0; i < nof_caller_save_xmm_regs ; i++) {
1.246 + _caller_save_xmm_regs[i] = LIR_OprFact::single_xmm(i);
1.247 + }
1.248 +
1.249 + _init_done = true;
1.250 +
1.251 + rsi_oop_opr = as_oop_opr(rsi);
1.252 + rdi_oop_opr = as_oop_opr(rdi);
1.253 + rbx_oop_opr = as_oop_opr(rbx);
1.254 + rax_oop_opr = as_oop_opr(rax);
1.255 + rdx_oop_opr = as_oop_opr(rdx);
1.256 + rcx_oop_opr = as_oop_opr(rcx);
1.257 +
1.258 + rsi_metadata_opr = as_metadata_opr(rsi);
1.259 + rdi_metadata_opr = as_metadata_opr(rdi);
1.260 + rbx_metadata_opr = as_metadata_opr(rbx);
1.261 + rax_metadata_opr = as_metadata_opr(rax);
1.262 + rdx_metadata_opr = as_metadata_opr(rdx);
1.263 + rcx_metadata_opr = as_metadata_opr(rcx);
1.264 +
1.265 + rsp_opr = as_pointer_opr(rsp);
1.266 + rbp_opr = as_pointer_opr(rbp);
1.267 +
1.268 +#ifdef _LP64
1.269 + r8_oop_opr = as_oop_opr(r8);
1.270 + r9_oop_opr = as_oop_opr(r9);
1.271 + r11_oop_opr = as_oop_opr(r11);
1.272 + r12_oop_opr = as_oop_opr(r12);
1.273 + r13_oop_opr = as_oop_opr(r13);
1.274 + r14_oop_opr = as_oop_opr(r14);
1.275 +
1.276 + r8_metadata_opr = as_metadata_opr(r8);
1.277 + r9_metadata_opr = as_metadata_opr(r9);
1.278 + r11_metadata_opr = as_metadata_opr(r11);
1.279 + r12_metadata_opr = as_metadata_opr(r12);
1.280 + r13_metadata_opr = as_metadata_opr(r13);
1.281 + r14_metadata_opr = as_metadata_opr(r14);
1.282 +#endif // _LP64
1.283 +
1.284 + VMRegPair regs;
1.285 + BasicType sig_bt = T_OBJECT;
1.286 + SharedRuntime::java_calling_convention(&sig_bt, ®s, 1, true);
1.287 + receiver_opr = as_oop_opr(regs.first()->as_Register());
1.288 +
1.289 +}
1.290 +
1.291 +
1.292 +Address FrameMap::make_new_address(ByteSize sp_offset) const {
1.293 + // for rbp, based address use this:
1.294 + // return Address(rbp, in_bytes(sp_offset) - (framesize() - 2) * 4);
1.295 + return Address(rsp, in_bytes(sp_offset));
1.296 +}
1.297 +
1.298 +
1.299 +// ----------------mapping-----------------------
1.300 +// all mapping is based on rbp, addressing, except for simple leaf methods where we access
1.301 +// the locals rsp based (and no frame is built)
1.302 +
1.303 +
1.304 +// Frame for simple leaf methods (quick entries)
1.305 +//
1.306 +// +----------+
1.307 +// | ret addr | <- TOS
1.308 +// +----------+
1.309 +// | args |
1.310 +// | ...... |
1.311 +
1.312 +// Frame for standard methods
1.313 +//
1.314 +// | .........| <- TOS
1.315 +// | locals |
1.316 +// +----------+
1.317 +// | old rbp, | <- EBP
1.318 +// +----------+
1.319 +// | ret addr |
1.320 +// +----------+
1.321 +// | args |
1.322 +// | .........|
1.323 +
1.324 +
1.325 +// For OopMaps, map a local variable or spill index to an VMRegImpl name.
1.326 +// This is the offset from sp() in the frame of the slot for the index,
1.327 +// skewed by VMRegImpl::stack0 to indicate a stack location (vs.a register.)
1.328 +//
1.329 +// framesize +
1.330 +// stack0 stack0 0 <- VMReg
1.331 +// | | <registers> |
1.332 +// ...........|..............|.............|
1.333 +// 0 1 2 3 x x 4 5 6 ... | <- local indices
1.334 +// ^ ^ sp() ( x x indicate link
1.335 +// | | and return addr)
1.336 +// arguments non-argument locals
1.337 +
1.338 +
1.339 +VMReg FrameMap::fpu_regname (int n) {
1.340 + // Return the OptoReg name for the fpu stack slot "n"
1.341 + // A spilled fpu stack slot comprises to two single-word OptoReg's.
1.342 + return as_FloatRegister(n)->as_VMReg();
1.343 +}
1.344 +
1.345 +LIR_Opr FrameMap::stack_pointer() {
1.346 + return FrameMap::rsp_opr;
1.347 +}
1.348 +
1.349 +
1.350 +// JSR 292
1.351 +LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() {
1.352 + assert(rbp == rbp_mh_SP_save, "must be same register");
1.353 + return rbp_opr;
1.354 +}
1.355 +
1.356 +
1.357 +bool FrameMap::validate_frame() {
1.358 + return true;
1.359 +}
