src/cpu/x86/vm/c1_FpuStackSim_x86.hpp

changeset 0
f90c822e73f8
child 6876
710a3c8b516e
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/src/cpu/x86/vm/c1_FpuStackSim_x86.hpp	Wed Apr 27 01:25:04 2016 +0800
     1.3 @@ -0,0 +1,72 @@
     1.4 +/*
     1.5 + * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
     1.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     1.7 + *
     1.8 + * This code is free software; you can redistribute it and/or modify it
     1.9 + * under the terms of the GNU General Public License version 2 only, as
    1.10 + * published by the Free Software Foundation.
    1.11 + *
    1.12 + * This code is distributed in the hope that it will be useful, but WITHOUT
    1.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    1.14 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    1.15 + * version 2 for more details (a copy is included in the LICENSE file that
    1.16 + * accompanied this code).
    1.17 + *
    1.18 + * You should have received a copy of the GNU General Public License version
    1.19 + * 2 along with this work; if not, write to the Free Software Foundation,
    1.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
    1.21 + *
    1.22 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
    1.23 + * or visit www.oracle.com if you need additional information or have any
    1.24 + * questions.
    1.25 + *
    1.26 + */
    1.27 +
    1.28 +#ifndef CPU_X86_VM_C1_FPUSTACKSIM_X86_HPP
    1.29 +#define CPU_X86_VM_C1_FPUSTACKSIM_X86_HPP
    1.30 +
    1.31 +//  Simulates the FPU stack and maintains mapping [fpu-register -> stack offset]
    1.32 +//  FPU registers are described as numbers from 0..nof_fpu_regs-1
    1.33 +
    1.34 +class Compilation;
    1.35 +
    1.36 +class FpuStackSim VALUE_OBJ_CLASS_SPEC {
    1.37 + private:
    1.38 +  Compilation* _compilation;
    1.39 +  int          _stack_size;
    1.40 +  int          _regs[FrameMap::nof_fpu_regs];
    1.41 +
    1.42 +  int tos_index() const                        { return _stack_size - 1; }
    1.43 +
    1.44 +  int regs_at(int i) const;
    1.45 +  void set_regs_at(int i, int val);
    1.46 +  void dec_stack_size();
    1.47 +  void inc_stack_size();
    1.48 +
    1.49 +  // unified bailout support
    1.50 +  Compilation*  compilation() const              { return _compilation; }
    1.51 +  void          bailout(const char* msg) const   { compilation()->bailout(msg); }
    1.52 +  bool          bailed_out() const               { return compilation()->bailed_out(); }
    1.53 +
    1.54 + public:
    1.55 +  FpuStackSim(Compilation* compilation);
    1.56 +  void pop ();
    1.57 +  void pop (int rnr);                          // rnr must be on tos
    1.58 +  void push(int rnr);
    1.59 +  void swap(int offset);                       // exchange tos with tos + offset
    1.60 +  int offset_from_tos(int rnr) const;          // return the offset of the topmost instance of rnr from TOS
    1.61 +  int  get_slot(int tos_offset) const;         // return the entry at the given offset from TOS
    1.62 +  void set_slot(int tos_offset, int rnr);      // set the entry at the given offset from TOS
    1.63 +  void rename(int old_rnr, int new_rnr);       // rename all instances of old_rnr to new_rnr
    1.64 +  bool contains(int rnr);                      // debugging support only
    1.65 +  bool is_empty();
    1.66 +  bool slot_is_empty(int tos_offset);
    1.67 +  int stack_size() const                       { return _stack_size; }
    1.68 +  void clear();
    1.69 +  intArray* write_state();
    1.70 +  void read_state(intArray* fpu_stack_state);
    1.71 +
    1.72 +  void print() PRODUCT_RETURN;
    1.73 +};
    1.74 +
    1.75 +#endif // CPU_X86_VM_C1_FPUSTACKSIM_X86_HPP

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