1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/cpu/x86/vm/c1_Defs_x86.hpp Wed Apr 27 01:25:04 2016 +0800
1.3 @@ -0,0 +1,78 @@
1.4 +/*
1.5 + * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
1.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.7 + *
1.8 + * This code is free software; you can redistribute it and/or modify it
1.9 + * under the terms of the GNU General Public License version 2 only, as
1.10 + * published by the Free Software Foundation.
1.11 + *
1.12 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.14 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.15 + * version 2 for more details (a copy is included in the LICENSE file that
1.16 + * accompanied this code).
1.17 + *
1.18 + * You should have received a copy of the GNU General Public License version
1.19 + * 2 along with this work; if not, write to the Free Software Foundation,
1.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.21 + *
1.22 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1.23 + * or visit www.oracle.com if you need additional information or have any
1.24 + * questions.
1.25 + *
1.26 + */
1.27 +
1.28 +#ifndef CPU_X86_VM_C1_DEFS_X86_HPP
1.29 +#define CPU_X86_VM_C1_DEFS_X86_HPP
1.30 +
1.31 +// native word offsets from memory address (little endian)
1.32 +enum {
1.33 + pd_lo_word_offset_in_bytes = 0,
1.34 + pd_hi_word_offset_in_bytes = BytesPerWord
1.35 +};
1.36 +
1.37 +// explicit rounding operations are required to implement the strictFP mode
1.38 +enum {
1.39 + pd_strict_fp_requires_explicit_rounding = true
1.40 +};
1.41 +
1.42 +
1.43 +// registers
1.44 +enum {
1.45 + pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers, // number of registers used during code emission
1.46 + pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers, // number of registers used during code emission
1.47 + pd_nof_xmm_regs_frame_map = XMMRegisterImpl::number_of_registers, // number of registers used during code emission
1.48 +
1.49 +#ifdef _LP64
1.50 + #define UNALLOCATED 4 // rsp, rbp, r15, r10
1.51 +#else
1.52 + #define UNALLOCATED 2 // rsp, rbp
1.53 +#endif // LP64
1.54 +
1.55 + pd_nof_caller_save_cpu_regs_frame_map = pd_nof_cpu_regs_frame_map - UNALLOCATED, // number of registers killed by calls
1.56 + pd_nof_caller_save_fpu_regs_frame_map = pd_nof_fpu_regs_frame_map, // number of registers killed by calls
1.57 + pd_nof_caller_save_xmm_regs_frame_map = pd_nof_xmm_regs_frame_map, // number of registers killed by calls
1.58 +
1.59 + pd_nof_cpu_regs_reg_alloc = pd_nof_caller_save_cpu_regs_frame_map, // number of registers that are visible to register allocator
1.60 + pd_nof_fpu_regs_reg_alloc = 6, // number of registers that are visible to register allocator
1.61 +
1.62 + pd_nof_cpu_regs_linearscan = pd_nof_cpu_regs_frame_map, // number of registers visible to linear scan
1.63 + pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan
1.64 + pd_nof_xmm_regs_linearscan = pd_nof_xmm_regs_frame_map, // number of registers visible to linear scan
1.65 + pd_first_cpu_reg = 0,
1.66 + pd_last_cpu_reg = NOT_LP64(5) LP64_ONLY(11),
1.67 + pd_first_byte_reg = NOT_LP64(2) LP64_ONLY(0),
1.68 + pd_last_byte_reg = NOT_LP64(5) LP64_ONLY(11),
1.69 + pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
1.70 + pd_last_fpu_reg = pd_first_fpu_reg + 7,
1.71 + pd_first_xmm_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map,
1.72 + pd_last_xmm_reg = pd_first_xmm_reg + pd_nof_xmm_regs_frame_map - 1
1.73 +};
1.74 +
1.75 +
1.76 +// encoding of float value in debug info:
1.77 +enum {
1.78 + pd_float_saved_as_double = true
1.79 +};
1.80 +
1.81 +#endif // CPU_X86_VM_C1_DEFS_X86_HPP
