1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp Wed Apr 27 01:25:04 2016 +0800
1.3 @@ -0,0 +1,3639 @@
1.4 +/*
1.5 + * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
1.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.7 + *
1.8 + * This code is free software; you can redistribute it and/or modify it
1.9 + * under the terms of the GNU General Public License version 2 only, as
1.10 + * published by the Free Software Foundation.
1.11 + *
1.12 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.14 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.15 + * version 2 for more details (a copy is included in the LICENSE file that
1.16 + * accompanied this code).
1.17 + *
1.18 + * You should have received a copy of the GNU General Public License version
1.19 + * 2 along with this work; if not, write to the Free Software Foundation,
1.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.21 + *
1.22 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1.23 + * or visit www.oracle.com if you need additional information or have any
1.24 + * questions.
1.25 + *
1.26 + */
1.27 +
1.28 +#include "precompiled.hpp"
1.29 +#include "c1/c1_Compilation.hpp"
1.30 +#include "c1/c1_LIRAssembler.hpp"
1.31 +#include "c1/c1_MacroAssembler.hpp"
1.32 +#include "c1/c1_Runtime1.hpp"
1.33 +#include "c1/c1_ValueStack.hpp"
1.34 +#include "ci/ciArrayKlass.hpp"
1.35 +#include "ci/ciInstance.hpp"
1.36 +#include "gc_interface/collectedHeap.hpp"
1.37 +#include "memory/barrierSet.hpp"
1.38 +#include "memory/cardTableModRefBS.hpp"
1.39 +#include "nativeInst_sparc.hpp"
1.40 +#include "oops/objArrayKlass.hpp"
1.41 +#include "runtime/sharedRuntime.hpp"
1.42 +
1.43 +#define __ _masm->
1.44 +
1.45 +
1.46 +//------------------------------------------------------------
1.47 +
1.48 +
1.49 +bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
1.50 + if (opr->is_constant()) {
1.51 + LIR_Const* constant = opr->as_constant_ptr();
1.52 + switch (constant->type()) {
1.53 + case T_INT: {
1.54 + jint value = constant->as_jint();
1.55 + return Assembler::is_simm13(value);
1.56 + }
1.57 +
1.58 + default:
1.59 + return false;
1.60 + }
1.61 + }
1.62 + return false;
1.63 +}
1.64 +
1.65 +
1.66 +bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
1.67 + switch (op->code()) {
1.68 + case lir_null_check:
1.69 + return true;
1.70 +
1.71 +
1.72 + case lir_add:
1.73 + case lir_ushr:
1.74 + case lir_shr:
1.75 + case lir_shl:
1.76 + // integer shifts and adds are always one instruction
1.77 + return op->result_opr()->is_single_cpu();
1.78 +
1.79 +
1.80 + case lir_move: {
1.81 + LIR_Op1* op1 = op->as_Op1();
1.82 + LIR_Opr src = op1->in_opr();
1.83 + LIR_Opr dst = op1->result_opr();
1.84 +
1.85 + if (src == dst) {
1.86 + NEEDS_CLEANUP;
1.87 + // this works around a problem where moves with the same src and dst
1.88 + // end up in the delay slot and then the assembler swallows the mov
1.89 + // since it has no effect and then it complains because the delay slot
1.90 + // is empty. returning false stops the optimizer from putting this in
1.91 + // the delay slot
1.92 + return false;
1.93 + }
1.94 +
1.95 + // don't put moves involving oops into the delay slot since the VerifyOops code
1.96 + // will make it much larger than a single instruction.
1.97 + if (VerifyOops) {
1.98 + return false;
1.99 + }
1.100 +
1.101 + if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
1.102 + ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
1.103 + return false;
1.104 + }
1.105 +
1.106 + if (UseCompressedOops) {
1.107 + if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false;
1.108 + if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false;
1.109 + }
1.110 +
1.111 + if (UseCompressedClassPointers) {
1.112 + if (src->is_address() && !src->is_stack() && src->type() == T_ADDRESS &&
1.113 + src->as_address_ptr()->disp() == oopDesc::klass_offset_in_bytes()) return false;
1.114 + }
1.115 +
1.116 + if (dst->is_register()) {
1.117 + if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
1.118 + return !PatchALot;
1.119 + } else if (src->is_single_stack()) {
1.120 + return true;
1.121 + }
1.122 + }
1.123 +
1.124 + if (src->is_register()) {
1.125 + if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
1.126 + return !PatchALot;
1.127 + } else if (dst->is_single_stack()) {
1.128 + return true;
1.129 + }
1.130 + }
1.131 +
1.132 + if (dst->is_register() &&
1.133 + ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
1.134 + (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
1.135 + return true;
1.136 + }
1.137 +
1.138 + return false;
1.139 + }
1.140 +
1.141 + default:
1.142 + return false;
1.143 + }
1.144 + ShouldNotReachHere();
1.145 +}
1.146 +
1.147 +
1.148 +LIR_Opr LIR_Assembler::receiverOpr() {
1.149 + return FrameMap::O0_oop_opr;
1.150 +}
1.151 +
1.152 +
1.153 +LIR_Opr LIR_Assembler::osrBufferPointer() {
1.154 + return FrameMap::I0_opr;
1.155 +}
1.156 +
1.157 +
1.158 +int LIR_Assembler::initial_frame_size_in_bytes() const {
1.159 + return in_bytes(frame_map()->framesize_in_bytes());
1.160 +}
1.161 +
1.162 +
1.163 +// inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
1.164 +// we fetch the class of the receiver (O0) and compare it with the cached class.
1.165 +// If they do not match we jump to slow case.
1.166 +int LIR_Assembler::check_icache() {
1.167 + int offset = __ offset();
1.168 + __ inline_cache_check(O0, G5_inline_cache_reg);
1.169 + return offset;
1.170 +}
1.171 +
1.172 +
1.173 +void LIR_Assembler::osr_entry() {
1.174 + // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
1.175 + //
1.176 + // 1. Create a new compiled activation.
1.177 + // 2. Initialize local variables in the compiled activation. The expression stack must be empty
1.178 + // at the osr_bci; it is not initialized.
1.179 + // 3. Jump to the continuation address in compiled code to resume execution.
1.180 +
1.181 + // OSR entry point
1.182 + offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
1.183 + BlockBegin* osr_entry = compilation()->hir()->osr_entry();
1.184 + ValueStack* entry_state = osr_entry->end()->state();
1.185 + int number_of_locks = entry_state->locks_size();
1.186 +
1.187 + // Create a frame for the compiled activation.
1.188 + __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
1.189 +
1.190 + // OSR buffer is
1.191 + //
1.192 + // locals[nlocals-1..0]
1.193 + // monitors[number_of_locks-1..0]
1.194 + //
1.195 + // locals is a direct copy of the interpreter frame so in the osr buffer
1.196 + // so first slot in the local array is the last local from the interpreter
1.197 + // and last slot is local[0] (receiver) from the interpreter
1.198 + //
1.199 + // Similarly with locks. The first lock slot in the osr buffer is the nth lock
1.200 + // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
1.201 + // in the interpreter frame (the method lock if a sync method)
1.202 +
1.203 + // Initialize monitors in the compiled activation.
1.204 + // I0: pointer to osr buffer
1.205 + //
1.206 + // All other registers are dead at this point and the locals will be
1.207 + // copied into place by code emitted in the IR.
1.208 +
1.209 + Register OSR_buf = osrBufferPointer()->as_register();
1.210 + { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
1.211 + int monitor_offset = BytesPerWord * method()->max_locals() +
1.212 + (2 * BytesPerWord) * (number_of_locks - 1);
1.213 + // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
1.214 + // the OSR buffer using 2 word entries: first the lock and then
1.215 + // the oop.
1.216 + for (int i = 0; i < number_of_locks; i++) {
1.217 + int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
1.218 +#ifdef ASSERT
1.219 + // verify the interpreter's monitor has a non-null object
1.220 + {
1.221 + Label L;
1.222 + __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
1.223 + __ cmp_and_br_short(O7, G0, Assembler::notEqual, Assembler::pt, L);
1.224 + __ stop("locked object is NULL");
1.225 + __ bind(L);
1.226 + }
1.227 +#endif // ASSERT
1.228 + // Copy the lock field into the compiled activation.
1.229 + __ ld_ptr(OSR_buf, slot_offset + 0, O7);
1.230 + __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
1.231 + __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
1.232 + __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
1.233 + }
1.234 + }
1.235 +}
1.236 +
1.237 +
1.238 +// Optimized Library calls
1.239 +// This is the fast version of java.lang.String.compare; it has not
1.240 +// OSR-entry and therefore, we generate a slow version for OSR's
1.241 +void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) {
1.242 + Register str0 = left->as_register();
1.243 + Register str1 = right->as_register();
1.244 +
1.245 + Label Ldone;
1.246 +
1.247 + Register result = dst->as_register();
1.248 + {
1.249 + // Get a pointer to the first character of string0 in tmp0
1.250 + // and get string0.length() in str0
1.251 + // Get a pointer to the first character of string1 in tmp1
1.252 + // and get string1.length() in str1
1.253 + // Also, get string0.length()-string1.length() in
1.254 + // o7 and get the condition code set
1.255 + // Note: some instructions have been hoisted for better instruction scheduling
1.256 +
1.257 + Register tmp0 = L0;
1.258 + Register tmp1 = L1;
1.259 + Register tmp2 = L2;
1.260 +
1.261 + int value_offset = java_lang_String:: value_offset_in_bytes(); // char array
1.262 + if (java_lang_String::has_offset_field()) {
1.263 + int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position
1.264 + int count_offset = java_lang_String:: count_offset_in_bytes();
1.265 + __ load_heap_oop(str0, value_offset, tmp0);
1.266 + __ ld(str0, offset_offset, tmp2);
1.267 + __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);
1.268 + __ ld(str0, count_offset, str0);
1.269 + __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
1.270 + } else {
1.271 + __ load_heap_oop(str0, value_offset, tmp1);
1.272 + __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);
1.273 + __ ld(tmp1, arrayOopDesc::length_offset_in_bytes(), str0);
1.274 + }
1.275 +
1.276 + // str1 may be null
1.277 + add_debug_info_for_null_check_here(info);
1.278 +
1.279 + if (java_lang_String::has_offset_field()) {
1.280 + int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position
1.281 + int count_offset = java_lang_String:: count_offset_in_bytes();
1.282 + __ load_heap_oop(str1, value_offset, tmp1);
1.283 + __ add(tmp0, tmp2, tmp0);
1.284 +
1.285 + __ ld(str1, offset_offset, tmp2);
1.286 + __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);
1.287 + __ ld(str1, count_offset, str1);
1.288 + __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
1.289 + __ add(tmp1, tmp2, tmp1);
1.290 + } else {
1.291 + __ load_heap_oop(str1, value_offset, tmp2);
1.292 + __ add(tmp2, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);
1.293 + __ ld(tmp2, arrayOopDesc::length_offset_in_bytes(), str1);
1.294 + }
1.295 + __ subcc(str0, str1, O7);
1.296 + }
1.297 +
1.298 + {
1.299 + // Compute the minimum of the string lengths, scale it and store it in limit
1.300 + Register count0 = I0;
1.301 + Register count1 = I1;
1.302 + Register limit = L3;
1.303 +
1.304 + Label Lskip;
1.305 + __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter
1.306 + __ br(Assembler::greater, true, Assembler::pt, Lskip);
1.307 + __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter
1.308 + __ bind(Lskip);
1.309 +
1.310 + // If either string is empty (or both of them) the result is the difference in lengths
1.311 + __ cmp(limit, 0);
1.312 + __ br(Assembler::equal, true, Assembler::pn, Ldone);
1.313 + __ delayed()->mov(O7, result); // result is difference in lengths
1.314 + }
1.315 +
1.316 + {
1.317 + // Neither string is empty
1.318 + Label Lloop;
1.319 +
1.320 + Register base0 = L0;
1.321 + Register base1 = L1;
1.322 + Register chr0 = I0;
1.323 + Register chr1 = I1;
1.324 + Register limit = L3;
1.325 +
1.326 + // Shift base0 and base1 to the end of the arrays, negate limit
1.327 + __ add(base0, limit, base0);
1.328 + __ add(base1, limit, base1);
1.329 + __ neg(limit); // limit = -min{string0.length(), string1.length()}
1.330 +
1.331 + __ lduh(base0, limit, chr0);
1.332 + __ bind(Lloop);
1.333 + __ lduh(base1, limit, chr1);
1.334 + __ subcc(chr0, chr1, chr0);
1.335 + __ br(Assembler::notZero, false, Assembler::pn, Ldone);
1.336 + assert(chr0 == result, "result must be pre-placed");
1.337 + __ delayed()->inccc(limit, sizeof(jchar));
1.338 + __ br(Assembler::notZero, true, Assembler::pt, Lloop);
1.339 + __ delayed()->lduh(base0, limit, chr0);
1.340 + }
1.341 +
1.342 + // If strings are equal up to min length, return the length difference.
1.343 + __ mov(O7, result);
1.344 +
1.345 + // Otherwise, return the difference between the first mismatched chars.
1.346 + __ bind(Ldone);
1.347 +}
1.348 +
1.349 +
1.350 +// --------------------------------------------------------------------------------------------
1.351 +
1.352 +void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
1.353 + if (!GenerateSynchronizationCode) return;
1.354 +
1.355 + Register obj_reg = obj_opr->as_register();
1.356 + Register lock_reg = lock_opr->as_register();
1.357 +
1.358 + Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
1.359 + Register reg = mon_addr.base();
1.360 + int offset = mon_addr.disp();
1.361 + // compute pointer to BasicLock
1.362 + if (mon_addr.is_simm13()) {
1.363 + __ add(reg, offset, lock_reg);
1.364 + }
1.365 + else {
1.366 + __ set(offset, lock_reg);
1.367 + __ add(reg, lock_reg, lock_reg);
1.368 + }
1.369 + // unlock object
1.370 + MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
1.371 + // _slow_case_stubs->append(slow_case);
1.372 + // temporary fix: must be created after exceptionhandler, therefore as call stub
1.373 + _slow_case_stubs->append(slow_case);
1.374 + if (UseFastLocking) {
1.375 + // try inlined fast unlocking first, revert to slow locking if it fails
1.376 + // note: lock_reg points to the displaced header since the displaced header offset is 0!
1.377 + assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
1.378 + __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
1.379 + } else {
1.380 + // always do slow unlocking
1.381 + // note: the slow unlocking code could be inlined here, however if we use
1.382 + // slow unlocking, speed doesn't matter anyway and this solution is
1.383 + // simpler and requires less duplicated code - additionally, the
1.384 + // slow unlocking code is the same in either case which simplifies
1.385 + // debugging
1.386 + __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
1.387 + __ delayed()->nop();
1.388 + }
1.389 + // done
1.390 + __ bind(*slow_case->continuation());
1.391 +}
1.392 +
1.393 +
1.394 +int LIR_Assembler::emit_exception_handler() {
1.395 + // if the last instruction is a call (typically to do a throw which
1.396 + // is coming at the end after block reordering) the return address
1.397 + // must still point into the code area in order to avoid assertion
1.398 + // failures when searching for the corresponding bci => add a nop
1.399 + // (was bug 5/14/1999 - gri)
1.400 + __ nop();
1.401 +
1.402 + // generate code for exception handler
1.403 + ciMethod* method = compilation()->method();
1.404 +
1.405 + address handler_base = __ start_a_stub(exception_handler_size);
1.406 +
1.407 + if (handler_base == NULL) {
1.408 + // not enough space left for the handler
1.409 + bailout("exception handler overflow");
1.410 + return -1;
1.411 + }
1.412 +
1.413 + int offset = code_offset();
1.414 +
1.415 + __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type);
1.416 + __ delayed()->nop();
1.417 + __ should_not_reach_here();
1.418 + guarantee(code_offset() - offset <= exception_handler_size, "overflow");
1.419 + __ end_a_stub();
1.420 +
1.421 + return offset;
1.422 +}
1.423 +
1.424 +
1.425 +// Emit the code to remove the frame from the stack in the exception
1.426 +// unwind path.
1.427 +int LIR_Assembler::emit_unwind_handler() {
1.428 +#ifndef PRODUCT
1.429 + if (CommentedAssembly) {
1.430 + _masm->block_comment("Unwind handler");
1.431 + }
1.432 +#endif
1.433 +
1.434 + int offset = code_offset();
1.435 +
1.436 + // Fetch the exception from TLS and clear out exception related thread state
1.437 + __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0);
1.438 + __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
1.439 + __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset()));
1.440 +
1.441 + __ bind(_unwind_handler_entry);
1.442 + __ verify_not_null_oop(O0);
1.443 + if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
1.444 + __ mov(O0, I0); // Preserve the exception
1.445 + }
1.446 +
1.447 + // Preform needed unlocking
1.448 + MonitorExitStub* stub = NULL;
1.449 + if (method()->is_synchronized()) {
1.450 + monitor_address(0, FrameMap::I1_opr);
1.451 + stub = new MonitorExitStub(FrameMap::I1_opr, true, 0);
1.452 + __ unlock_object(I3, I2, I1, *stub->entry());
1.453 + __ bind(*stub->continuation());
1.454 + }
1.455 +
1.456 + if (compilation()->env()->dtrace_method_probes()) {
1.457 + __ mov(G2_thread, O0);
1.458 + __ save_thread(I1); // need to preserve thread in G2 across
1.459 + // runtime call
1.460 + metadata2reg(method()->constant_encoding(), O1);
1.461 + __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type);
1.462 + __ delayed()->nop();
1.463 + __ restore_thread(I1);
1.464 + }
1.465 +
1.466 + if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
1.467 + __ mov(I0, O0); // Restore the exception
1.468 + }
1.469 +
1.470 + // dispatch to the unwind logic
1.471 + __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
1.472 + __ delayed()->nop();
1.473 +
1.474 + // Emit the slow path assembly
1.475 + if (stub != NULL) {
1.476 + stub->emit_code(this);
1.477 + }
1.478 +
1.479 + return offset;
1.480 +}
1.481 +
1.482 +
1.483 +int LIR_Assembler::emit_deopt_handler() {
1.484 + // if the last instruction is a call (typically to do a throw which
1.485 + // is coming at the end after block reordering) the return address
1.486 + // must still point into the code area in order to avoid assertion
1.487 + // failures when searching for the corresponding bci => add a nop
1.488 + // (was bug 5/14/1999 - gri)
1.489 + __ nop();
1.490 +
1.491 + // generate code for deopt handler
1.492 + ciMethod* method = compilation()->method();
1.493 + address handler_base = __ start_a_stub(deopt_handler_size);
1.494 + if (handler_base == NULL) {
1.495 + // not enough space left for the handler
1.496 + bailout("deopt handler overflow");
1.497 + return -1;
1.498 + }
1.499 +
1.500 + int offset = code_offset();
1.501 + AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1.502 + __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
1.503 + __ delayed()->nop();
1.504 + guarantee(code_offset() - offset <= deopt_handler_size, "overflow");
1.505 + __ end_a_stub();
1.506 +
1.507 + return offset;
1.508 +}
1.509 +
1.510 +
1.511 +void LIR_Assembler::jobject2reg(jobject o, Register reg) {
1.512 + if (o == NULL) {
1.513 + __ set(NULL_WORD, reg);
1.514 + } else {
1.515 + int oop_index = __ oop_recorder()->find_index(o);
1.516 + assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(o)), "should be real oop");
1.517 + RelocationHolder rspec = oop_Relocation::spec(oop_index);
1.518 + __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
1.519 + }
1.520 +}
1.521 +
1.522 +
1.523 +void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
1.524 + // Allocate a new index in table to hold the object once it's been patched
1.525 + int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
1.526 + PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
1.527 +
1.528 + AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
1.529 + assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
1.530 + // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
1.531 + // NULL will be dynamically patched later and the patched value may be large. We must
1.532 + // therefore generate the sethi/add as a placeholders
1.533 + __ patchable_set(addrlit, reg);
1.534 +
1.535 + patching_epilog(patch, lir_patch_normal, reg, info);
1.536 +}
1.537 +
1.538 +
1.539 +void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
1.540 + __ set_metadata_constant(o, reg);
1.541 +}
1.542 +
1.543 +void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
1.544 + // Allocate a new index in table to hold the klass once it's been patched
1.545 + int index = __ oop_recorder()->allocate_metadata_index(NULL);
1.546 + PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
1.547 + AddressLiteral addrlit(NULL, metadata_Relocation::spec(index));
1.548 + assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
1.549 + // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
1.550 + // NULL will be dynamically patched later and the patched value may be large. We must
1.551 + // therefore generate the sethi/add as a placeholders
1.552 + __ patchable_set(addrlit, reg);
1.553 +
1.554 + patching_epilog(patch, lir_patch_normal, reg, info);
1.555 +}
1.556 +
1.557 +void LIR_Assembler::emit_op3(LIR_Op3* op) {
1.558 + Register Rdividend = op->in_opr1()->as_register();
1.559 + Register Rdivisor = noreg;
1.560 + Register Rscratch = op->in_opr3()->as_register();
1.561 + Register Rresult = op->result_opr()->as_register();
1.562 + int divisor = -1;
1.563 +
1.564 + if (op->in_opr2()->is_register()) {
1.565 + Rdivisor = op->in_opr2()->as_register();
1.566 + } else {
1.567 + divisor = op->in_opr2()->as_constant_ptr()->as_jint();
1.568 + assert(Assembler::is_simm13(divisor), "can only handle simm13");
1.569 + }
1.570 +
1.571 + assert(Rdividend != Rscratch, "");
1.572 + assert(Rdivisor != Rscratch, "");
1.573 + assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
1.574 +
1.575 + if (Rdivisor == noreg && is_power_of_2(divisor)) {
1.576 + // convert division by a power of two into some shifts and logical operations
1.577 + if (op->code() == lir_idiv) {
1.578 + if (divisor == 2) {
1.579 + __ srl(Rdividend, 31, Rscratch);
1.580 + } else {
1.581 + __ sra(Rdividend, 31, Rscratch);
1.582 + __ and3(Rscratch, divisor - 1, Rscratch);
1.583 + }
1.584 + __ add(Rdividend, Rscratch, Rscratch);
1.585 + __ sra(Rscratch, log2_intptr(divisor), Rresult);
1.586 + return;
1.587 + } else {
1.588 + if (divisor == 2) {
1.589 + __ srl(Rdividend, 31, Rscratch);
1.590 + } else {
1.591 + __ sra(Rdividend, 31, Rscratch);
1.592 + __ and3(Rscratch, divisor - 1,Rscratch);
1.593 + }
1.594 + __ add(Rdividend, Rscratch, Rscratch);
1.595 + __ andn(Rscratch, divisor - 1,Rscratch);
1.596 + __ sub(Rdividend, Rscratch, Rresult);
1.597 + return;
1.598 + }
1.599 + }
1.600 +
1.601 + __ sra(Rdividend, 31, Rscratch);
1.602 + __ wry(Rscratch);
1.603 +
1.604 + add_debug_info_for_div0_here(op->info());
1.605 +
1.606 + if (Rdivisor != noreg) {
1.607 + __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
1.608 + } else {
1.609 + assert(Assembler::is_simm13(divisor), "can only handle simm13");
1.610 + __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
1.611 + }
1.612 +
1.613 + Label skip;
1.614 + __ br(Assembler::overflowSet, true, Assembler::pn, skip);
1.615 + __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
1.616 + __ bind(skip);
1.617 +
1.618 + if (op->code() == lir_irem) {
1.619 + if (Rdivisor != noreg) {
1.620 + __ smul(Rscratch, Rdivisor, Rscratch);
1.621 + } else {
1.622 + __ smul(Rscratch, divisor, Rscratch);
1.623 + }
1.624 + __ sub(Rdividend, Rscratch, Rresult);
1.625 + }
1.626 +}
1.627 +
1.628 +
1.629 +void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1.630 +#ifdef ASSERT
1.631 + assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1.632 + if (op->block() != NULL) _branch_target_blocks.append(op->block());
1.633 + if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1.634 +#endif
1.635 + assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
1.636 +
1.637 + if (op->cond() == lir_cond_always) {
1.638 + __ br(Assembler::always, false, Assembler::pt, *(op->label()));
1.639 + } else if (op->code() == lir_cond_float_branch) {
1.640 + assert(op->ublock() != NULL, "must have unordered successor");
1.641 + bool is_unordered = (op->ublock() == op->block());
1.642 + Assembler::Condition acond;
1.643 + switch (op->cond()) {
1.644 + case lir_cond_equal: acond = Assembler::f_equal; break;
1.645 + case lir_cond_notEqual: acond = Assembler::f_notEqual; break;
1.646 + case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break;
1.647 + case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break;
1.648 + case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break;
1.649 + case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
1.650 + default : ShouldNotReachHere();
1.651 + }
1.652 + __ fb( acond, false, Assembler::pn, *(op->label()));
1.653 + } else {
1.654 + assert (op->code() == lir_branch, "just checking");
1.655 +
1.656 + Assembler::Condition acond;
1.657 + switch (op->cond()) {
1.658 + case lir_cond_equal: acond = Assembler::equal; break;
1.659 + case lir_cond_notEqual: acond = Assembler::notEqual; break;
1.660 + case lir_cond_less: acond = Assembler::less; break;
1.661 + case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1.662 + case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1.663 + case lir_cond_greater: acond = Assembler::greater; break;
1.664 + case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1.665 + case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1.666 + default: ShouldNotReachHere();
1.667 + };
1.668 +
1.669 + // sparc has different condition codes for testing 32-bit
1.670 + // vs. 64-bit values. We could always test xcc is we could
1.671 + // guarantee that 32-bit loads always sign extended but that isn't
1.672 + // true and since sign extension isn't free, it would impose a
1.673 + // slight cost.
1.674 +#ifdef _LP64
1.675 + if (op->type() == T_INT) {
1.676 + __ br(acond, false, Assembler::pn, *(op->label()));
1.677 + } else
1.678 +#endif
1.679 + __ brx(acond, false, Assembler::pn, *(op->label()));
1.680 + }
1.681 + // The peephole pass fills the delay slot
1.682 +}
1.683 +
1.684 +
1.685 +void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1.686 + Bytecodes::Code code = op->bytecode();
1.687 + LIR_Opr dst = op->result_opr();
1.688 +
1.689 + switch(code) {
1.690 + case Bytecodes::_i2l: {
1.691 + Register rlo = dst->as_register_lo();
1.692 + Register rhi = dst->as_register_hi();
1.693 + Register rval = op->in_opr()->as_register();
1.694 +#ifdef _LP64
1.695 + __ sra(rval, 0, rlo);
1.696 +#else
1.697 + __ mov(rval, rlo);
1.698 + __ sra(rval, BitsPerInt-1, rhi);
1.699 +#endif
1.700 + break;
1.701 + }
1.702 + case Bytecodes::_i2d:
1.703 + case Bytecodes::_i2f: {
1.704 + bool is_double = (code == Bytecodes::_i2d);
1.705 + FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
1.706 + FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
1.707 + FloatRegister rsrc = op->in_opr()->as_float_reg();
1.708 + if (rsrc != rdst) {
1.709 + __ fmov(FloatRegisterImpl::S, rsrc, rdst);
1.710 + }
1.711 + __ fitof(w, rdst, rdst);
1.712 + break;
1.713 + }
1.714 + case Bytecodes::_f2i:{
1.715 + FloatRegister rsrc = op->in_opr()->as_float_reg();
1.716 + Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
1.717 + Label L;
1.718 + // result must be 0 if value is NaN; test by comparing value to itself
1.719 + __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
1.720 + __ fb(Assembler::f_unordered, true, Assembler::pn, L);
1.721 + __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
1.722 + __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
1.723 + // move integer result from float register to int register
1.724 + __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
1.725 + __ bind (L);
1.726 + break;
1.727 + }
1.728 + case Bytecodes::_l2i: {
1.729 + Register rlo = op->in_opr()->as_register_lo();
1.730 + Register rhi = op->in_opr()->as_register_hi();
1.731 + Register rdst = dst->as_register();
1.732 +#ifdef _LP64
1.733 + __ sra(rlo, 0, rdst);
1.734 +#else
1.735 + __ mov(rlo, rdst);
1.736 +#endif
1.737 + break;
1.738 + }
1.739 + case Bytecodes::_d2f:
1.740 + case Bytecodes::_f2d: {
1.741 + bool is_double = (code == Bytecodes::_f2d);
1.742 + assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
1.743 + LIR_Opr val = op->in_opr();
1.744 + FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
1.745 + FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
1.746 + FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
1.747 + FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
1.748 + __ ftof(vw, dw, rval, rdst);
1.749 + break;
1.750 + }
1.751 + case Bytecodes::_i2s:
1.752 + case Bytecodes::_i2b: {
1.753 + Register rval = op->in_opr()->as_register();
1.754 + Register rdst = dst->as_register();
1.755 + int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
1.756 + __ sll (rval, shift, rdst);
1.757 + __ sra (rdst, shift, rdst);
1.758 + break;
1.759 + }
1.760 + case Bytecodes::_i2c: {
1.761 + Register rval = op->in_opr()->as_register();
1.762 + Register rdst = dst->as_register();
1.763 + int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
1.764 + __ sll (rval, shift, rdst);
1.765 + __ srl (rdst, shift, rdst);
1.766 + break;
1.767 + }
1.768 +
1.769 + default: ShouldNotReachHere();
1.770 + }
1.771 +}
1.772 +
1.773 +
1.774 +void LIR_Assembler::align_call(LIR_Code) {
1.775 + // do nothing since all instructions are word aligned on sparc
1.776 +}
1.777 +
1.778 +
1.779 +void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
1.780 + __ call(op->addr(), rtype);
1.781 + // The peephole pass fills the delay slot, add_call_info is done in
1.782 + // LIR_Assembler::emit_delay.
1.783 +}
1.784 +
1.785 +
1.786 +void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
1.787 + __ ic_call(op->addr(), false);
1.788 + // The peephole pass fills the delay slot, add_call_info is done in
1.789 + // LIR_Assembler::emit_delay.
1.790 +}
1.791 +
1.792 +
1.793 +void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
1.794 + add_debug_info_for_null_check_here(op->info());
1.795 + __ load_klass(O0, G3_scratch);
1.796 + if (Assembler::is_simm13(op->vtable_offset())) {
1.797 + __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
1.798 + } else {
1.799 + // This will generate 2 instructions
1.800 + __ set(op->vtable_offset(), G5_method);
1.801 + // ld_ptr, set_hi, set
1.802 + __ ld_ptr(G3_scratch, G5_method, G5_method);
1.803 + }
1.804 + __ ld_ptr(G5_method, Method::from_compiled_offset(), G3_scratch);
1.805 + __ callr(G3_scratch, G0);
1.806 + // the peephole pass fills the delay slot
1.807 +}
1.808 +
1.809 +int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
1.810 + int store_offset;
1.811 + if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
1.812 + assert(!unaligned, "can't handle this");
1.813 + // for offsets larger than a simm13 we setup the offset in O7
1.814 + __ set(offset, O7);
1.815 + store_offset = store(from_reg, base, O7, type, wide);
1.816 + } else {
1.817 + if (type == T_ARRAY || type == T_OBJECT) {
1.818 + __ verify_oop(from_reg->as_register());
1.819 + }
1.820 + store_offset = code_offset();
1.821 + switch (type) {
1.822 + case T_BOOLEAN: // fall through
1.823 + case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
1.824 + case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
1.825 + case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
1.826 + case T_INT : __ stw(from_reg->as_register(), base, offset); break;
1.827 + case T_LONG :
1.828 +#ifdef _LP64
1.829 + if (unaligned || PatchALot) {
1.830 + __ srax(from_reg->as_register_lo(), 32, O7);
1.831 + __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
1.832 + __ stw(O7, base, offset + hi_word_offset_in_bytes);
1.833 + } else {
1.834 + __ stx(from_reg->as_register_lo(), base, offset);
1.835 + }
1.836 +#else
1.837 + assert(Assembler::is_simm13(offset + 4), "must be");
1.838 + __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
1.839 + __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes);
1.840 +#endif
1.841 + break;
1.842 + case T_ADDRESS:
1.843 + case T_METADATA:
1.844 + __ st_ptr(from_reg->as_register(), base, offset);
1.845 + break;
1.846 + case T_ARRAY : // fall through
1.847 + case T_OBJECT:
1.848 + {
1.849 + if (UseCompressedOops && !wide) {
1.850 + __ encode_heap_oop(from_reg->as_register(), G3_scratch);
1.851 + store_offset = code_offset();
1.852 + __ stw(G3_scratch, base, offset);
1.853 + } else {
1.854 + __ st_ptr(from_reg->as_register(), base, offset);
1.855 + }
1.856 + break;
1.857 + }
1.858 +
1.859 + case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
1.860 + case T_DOUBLE:
1.861 + {
1.862 + FloatRegister reg = from_reg->as_double_reg();
1.863 + // split unaligned stores
1.864 + if (unaligned || PatchALot) {
1.865 + assert(Assembler::is_simm13(offset + 4), "must be");
1.866 + __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
1.867 + __ stf(FloatRegisterImpl::S, reg, base, offset);
1.868 + } else {
1.869 + __ stf(FloatRegisterImpl::D, reg, base, offset);
1.870 + }
1.871 + break;
1.872 + }
1.873 + default : ShouldNotReachHere();
1.874 + }
1.875 + }
1.876 + return store_offset;
1.877 +}
1.878 +
1.879 +
1.880 +int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
1.881 + if (type == T_ARRAY || type == T_OBJECT) {
1.882 + __ verify_oop(from_reg->as_register());
1.883 + }
1.884 + int store_offset = code_offset();
1.885 + switch (type) {
1.886 + case T_BOOLEAN: // fall through
1.887 + case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
1.888 + case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
1.889 + case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
1.890 + case T_INT : __ stw(from_reg->as_register(), base, disp); break;
1.891 + case T_LONG :
1.892 +#ifdef _LP64
1.893 + __ stx(from_reg->as_register_lo(), base, disp);
1.894 +#else
1.895 + assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match");
1.896 + __ std(from_reg->as_register_hi(), base, disp);
1.897 +#endif
1.898 + break;
1.899 + case T_ADDRESS:
1.900 + __ st_ptr(from_reg->as_register(), base, disp);
1.901 + break;
1.902 + case T_ARRAY : // fall through
1.903 + case T_OBJECT:
1.904 + {
1.905 + if (UseCompressedOops && !wide) {
1.906 + __ encode_heap_oop(from_reg->as_register(), G3_scratch);
1.907 + store_offset = code_offset();
1.908 + __ stw(G3_scratch, base, disp);
1.909 + } else {
1.910 + __ st_ptr(from_reg->as_register(), base, disp);
1.911 + }
1.912 + break;
1.913 + }
1.914 + case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
1.915 + case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
1.916 + default : ShouldNotReachHere();
1.917 + }
1.918 + return store_offset;
1.919 +}
1.920 +
1.921 +
1.922 +int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
1.923 + int load_offset;
1.924 + if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
1.925 + assert(base != O7, "destroying register");
1.926 + assert(!unaligned, "can't handle this");
1.927 + // for offsets larger than a simm13 we setup the offset in O7
1.928 + __ set(offset, O7);
1.929 + load_offset = load(base, O7, to_reg, type, wide);
1.930 + } else {
1.931 + load_offset = code_offset();
1.932 + switch(type) {
1.933 + case T_BOOLEAN: // fall through
1.934 + case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
1.935 + case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
1.936 + case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
1.937 + case T_INT : __ ld(base, offset, to_reg->as_register()); break;
1.938 + case T_LONG :
1.939 + if (!unaligned) {
1.940 +#ifdef _LP64
1.941 + __ ldx(base, offset, to_reg->as_register_lo());
1.942 +#else
1.943 + assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
1.944 + "must be sequential");
1.945 + __ ldd(base, offset, to_reg->as_register_hi());
1.946 +#endif
1.947 + } else {
1.948 +#ifdef _LP64
1.949 + assert(base != to_reg->as_register_lo(), "can't handle this");
1.950 + assert(O7 != to_reg->as_register_lo(), "can't handle this");
1.951 + __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
1.952 + __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
1.953 + __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
1.954 + __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
1.955 +#else
1.956 + if (base == to_reg->as_register_lo()) {
1.957 + __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
1.958 + __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
1.959 + } else {
1.960 + __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
1.961 + __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
1.962 + }
1.963 +#endif
1.964 + }
1.965 + break;
1.966 + case T_METADATA: __ ld_ptr(base, offset, to_reg->as_register()); break;
1.967 + case T_ADDRESS:
1.968 +#ifdef _LP64
1.969 + if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) {
1.970 + __ lduw(base, offset, to_reg->as_register());
1.971 + __ decode_klass_not_null(to_reg->as_register());
1.972 + } else
1.973 +#endif
1.974 + {
1.975 + __ ld_ptr(base, offset, to_reg->as_register());
1.976 + }
1.977 + break;
1.978 + case T_ARRAY : // fall through
1.979 + case T_OBJECT:
1.980 + {
1.981 + if (UseCompressedOops && !wide) {
1.982 + __ lduw(base, offset, to_reg->as_register());
1.983 + __ decode_heap_oop(to_reg->as_register());
1.984 + } else {
1.985 + __ ld_ptr(base, offset, to_reg->as_register());
1.986 + }
1.987 + break;
1.988 + }
1.989 + case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
1.990 + case T_DOUBLE:
1.991 + {
1.992 + FloatRegister reg = to_reg->as_double_reg();
1.993 + // split unaligned loads
1.994 + if (unaligned || PatchALot) {
1.995 + __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
1.996 + __ ldf(FloatRegisterImpl::S, base, offset, reg);
1.997 + } else {
1.998 + __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
1.999 + }
1.1000 + break;
1.1001 + }
1.1002 + default : ShouldNotReachHere();
1.1003 + }
1.1004 + if (type == T_ARRAY || type == T_OBJECT) {
1.1005 + __ verify_oop(to_reg->as_register());
1.1006 + }
1.1007 + }
1.1008 + return load_offset;
1.1009 +}
1.1010 +
1.1011 +
1.1012 +int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
1.1013 + int load_offset = code_offset();
1.1014 + switch(type) {
1.1015 + case T_BOOLEAN: // fall through
1.1016 + case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
1.1017 + case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
1.1018 + case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
1.1019 + case T_INT : __ ld(base, disp, to_reg->as_register()); break;
1.1020 + case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break;
1.1021 + case T_ARRAY : // fall through
1.1022 + case T_OBJECT:
1.1023 + {
1.1024 + if (UseCompressedOops && !wide) {
1.1025 + __ lduw(base, disp, to_reg->as_register());
1.1026 + __ decode_heap_oop(to_reg->as_register());
1.1027 + } else {
1.1028 + __ ld_ptr(base, disp, to_reg->as_register());
1.1029 + }
1.1030 + break;
1.1031 + }
1.1032 + case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
1.1033 + case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
1.1034 + case T_LONG :
1.1035 +#ifdef _LP64
1.1036 + __ ldx(base, disp, to_reg->as_register_lo());
1.1037 +#else
1.1038 + assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
1.1039 + "must be sequential");
1.1040 + __ ldd(base, disp, to_reg->as_register_hi());
1.1041 +#endif
1.1042 + break;
1.1043 + default : ShouldNotReachHere();
1.1044 + }
1.1045 + if (type == T_ARRAY || type == T_OBJECT) {
1.1046 + __ verify_oop(to_reg->as_register());
1.1047 + }
1.1048 + return load_offset;
1.1049 +}
1.1050 +
1.1051 +void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
1.1052 + LIR_Const* c = src->as_constant_ptr();
1.1053 + switch (c->type()) {
1.1054 + case T_INT:
1.1055 + case T_FLOAT: {
1.1056 + Register src_reg = O7;
1.1057 + int value = c->as_jint_bits();
1.1058 + if (value == 0) {
1.1059 + src_reg = G0;
1.1060 + } else {
1.1061 + __ set(value, O7);
1.1062 + }
1.1063 + Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1.1064 + __ stw(src_reg, addr.base(), addr.disp());
1.1065 + break;
1.1066 + }
1.1067 + case T_ADDRESS: {
1.1068 + Register src_reg = O7;
1.1069 + int value = c->as_jint_bits();
1.1070 + if (value == 0) {
1.1071 + src_reg = G0;
1.1072 + } else {
1.1073 + __ set(value, O7);
1.1074 + }
1.1075 + Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1.1076 + __ st_ptr(src_reg, addr.base(), addr.disp());
1.1077 + break;
1.1078 + }
1.1079 + case T_OBJECT: {
1.1080 + Register src_reg = O7;
1.1081 + jobject2reg(c->as_jobject(), src_reg);
1.1082 + Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1.1083 + __ st_ptr(src_reg, addr.base(), addr.disp());
1.1084 + break;
1.1085 + }
1.1086 + case T_LONG:
1.1087 + case T_DOUBLE: {
1.1088 + Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
1.1089 +
1.1090 + Register tmp = O7;
1.1091 + int value_lo = c->as_jint_lo_bits();
1.1092 + if (value_lo == 0) {
1.1093 + tmp = G0;
1.1094 + } else {
1.1095 + __ set(value_lo, O7);
1.1096 + }
1.1097 + __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
1.1098 + int value_hi = c->as_jint_hi_bits();
1.1099 + if (value_hi == 0) {
1.1100 + tmp = G0;
1.1101 + } else {
1.1102 + __ set(value_hi, O7);
1.1103 + }
1.1104 + __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
1.1105 + break;
1.1106 + }
1.1107 + default:
1.1108 + Unimplemented();
1.1109 + }
1.1110 +}
1.1111 +
1.1112 +
1.1113 +void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
1.1114 + LIR_Const* c = src->as_constant_ptr();
1.1115 + LIR_Address* addr = dest->as_address_ptr();
1.1116 + Register base = addr->base()->as_pointer_register();
1.1117 + int offset = -1;
1.1118 +
1.1119 + switch (c->type()) {
1.1120 + case T_INT:
1.1121 + case T_FLOAT:
1.1122 + case T_ADDRESS: {
1.1123 + LIR_Opr tmp = FrameMap::O7_opr;
1.1124 + int value = c->as_jint_bits();
1.1125 + if (value == 0) {
1.1126 + tmp = FrameMap::G0_opr;
1.1127 + } else if (Assembler::is_simm13(value)) {
1.1128 + __ set(value, O7);
1.1129 + }
1.1130 + if (addr->index()->is_valid()) {
1.1131 + assert(addr->disp() == 0, "must be zero");
1.1132 + offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1.1133 + } else {
1.1134 + assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1.1135 + offset = store(tmp, base, addr->disp(), type, wide, false);
1.1136 + }
1.1137 + break;
1.1138 + }
1.1139 + case T_LONG:
1.1140 + case T_DOUBLE: {
1.1141 + assert(!addr->index()->is_valid(), "can't handle reg reg address here");
1.1142 + assert(Assembler::is_simm13(addr->disp()) &&
1.1143 + Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
1.1144 +
1.1145 + LIR_Opr tmp = FrameMap::O7_opr;
1.1146 + int value_lo = c->as_jint_lo_bits();
1.1147 + if (value_lo == 0) {
1.1148 + tmp = FrameMap::G0_opr;
1.1149 + } else {
1.1150 + __ set(value_lo, O7);
1.1151 + }
1.1152 + offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false);
1.1153 + int value_hi = c->as_jint_hi_bits();
1.1154 + if (value_hi == 0) {
1.1155 + tmp = FrameMap::G0_opr;
1.1156 + } else {
1.1157 + __ set(value_hi, O7);
1.1158 + }
1.1159 + store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false);
1.1160 + break;
1.1161 + }
1.1162 + case T_OBJECT: {
1.1163 + jobject obj = c->as_jobject();
1.1164 + LIR_Opr tmp;
1.1165 + if (obj == NULL) {
1.1166 + tmp = FrameMap::G0_opr;
1.1167 + } else {
1.1168 + tmp = FrameMap::O7_opr;
1.1169 + jobject2reg(c->as_jobject(), O7);
1.1170 + }
1.1171 + // handle either reg+reg or reg+disp address
1.1172 + if (addr->index()->is_valid()) {
1.1173 + assert(addr->disp() == 0, "must be zero");
1.1174 + offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1.1175 + } else {
1.1176 + assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1.1177 + offset = store(tmp, base, addr->disp(), type, wide, false);
1.1178 + }
1.1179 +
1.1180 + break;
1.1181 + }
1.1182 + default:
1.1183 + Unimplemented();
1.1184 + }
1.1185 + if (info != NULL) {
1.1186 + assert(offset != -1, "offset should've been set");
1.1187 + add_debug_info_for_null_check(offset, info);
1.1188 + }
1.1189 +}
1.1190 +
1.1191 +
1.1192 +void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1.1193 + LIR_Const* c = src->as_constant_ptr();
1.1194 + LIR_Opr to_reg = dest;
1.1195 +
1.1196 + switch (c->type()) {
1.1197 + case T_INT:
1.1198 + case T_ADDRESS:
1.1199 + {
1.1200 + jint con = c->as_jint();
1.1201 + if (to_reg->is_single_cpu()) {
1.1202 + assert(patch_code == lir_patch_none, "no patching handled here");
1.1203 + __ set(con, to_reg->as_register());
1.1204 + } else {
1.1205 + ShouldNotReachHere();
1.1206 + assert(to_reg->is_single_fpu(), "wrong register kind");
1.1207 +
1.1208 + __ set(con, O7);
1.1209 + Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1.1210 + __ st(O7, temp_slot);
1.1211 + __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1.1212 + }
1.1213 + }
1.1214 + break;
1.1215 +
1.1216 + case T_LONG:
1.1217 + {
1.1218 + jlong con = c->as_jlong();
1.1219 +
1.1220 + if (to_reg->is_double_cpu()) {
1.1221 +#ifdef _LP64
1.1222 + __ set(con, to_reg->as_register_lo());
1.1223 +#else
1.1224 + __ set(low(con), to_reg->as_register_lo());
1.1225 + __ set(high(con), to_reg->as_register_hi());
1.1226 +#endif
1.1227 +#ifdef _LP64
1.1228 + } else if (to_reg->is_single_cpu()) {
1.1229 + __ set(con, to_reg->as_register());
1.1230 +#endif
1.1231 + } else {
1.1232 + ShouldNotReachHere();
1.1233 + assert(to_reg->is_double_fpu(), "wrong register kind");
1.1234 + Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
1.1235 + Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1.1236 + __ set(low(con), O7);
1.1237 + __ st(O7, temp_slot_lo);
1.1238 + __ set(high(con), O7);
1.1239 + __ st(O7, temp_slot_hi);
1.1240 + __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1.1241 + }
1.1242 + }
1.1243 + break;
1.1244 +
1.1245 + case T_OBJECT:
1.1246 + {
1.1247 + if (patch_code == lir_patch_none) {
1.1248 + jobject2reg(c->as_jobject(), to_reg->as_register());
1.1249 + } else {
1.1250 + jobject2reg_with_patching(to_reg->as_register(), info);
1.1251 + }
1.1252 + }
1.1253 + break;
1.1254 +
1.1255 + case T_METADATA:
1.1256 + {
1.1257 + if (patch_code == lir_patch_none) {
1.1258 + metadata2reg(c->as_metadata(), to_reg->as_register());
1.1259 + } else {
1.1260 + klass2reg_with_patching(to_reg->as_register(), info);
1.1261 + }
1.1262 + }
1.1263 + break;
1.1264 +
1.1265 + case T_FLOAT:
1.1266 + {
1.1267 + address const_addr = __ float_constant(c->as_jfloat());
1.1268 + if (const_addr == NULL) {
1.1269 + bailout("const section overflow");
1.1270 + break;
1.1271 + }
1.1272 + RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1.1273 + AddressLiteral const_addrlit(const_addr, rspec);
1.1274 + if (to_reg->is_single_fpu()) {
1.1275 + __ patchable_sethi(const_addrlit, O7);
1.1276 + __ relocate(rspec);
1.1277 + __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1.1278 +
1.1279 + } else {
1.1280 + assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1.1281 +
1.1282 + __ set(const_addrlit, O7);
1.1283 + __ ld(O7, 0, to_reg->as_register());
1.1284 + }
1.1285 + }
1.1286 + break;
1.1287 +
1.1288 + case T_DOUBLE:
1.1289 + {
1.1290 + address const_addr = __ double_constant(c->as_jdouble());
1.1291 + if (const_addr == NULL) {
1.1292 + bailout("const section overflow");
1.1293 + break;
1.1294 + }
1.1295 + RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1.1296 +
1.1297 + if (to_reg->is_double_fpu()) {
1.1298 + AddressLiteral const_addrlit(const_addr, rspec);
1.1299 + __ patchable_sethi(const_addrlit, O7);
1.1300 + __ relocate(rspec);
1.1301 + __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1.1302 + } else {
1.1303 + assert(to_reg->is_double_cpu(), "Must be a long register.");
1.1304 +#ifdef _LP64
1.1305 + __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1.1306 +#else
1.1307 + __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo());
1.1308 + __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi());
1.1309 +#endif
1.1310 + }
1.1311 +
1.1312 + }
1.1313 + break;
1.1314 +
1.1315 + default:
1.1316 + ShouldNotReachHere();
1.1317 + }
1.1318 +}
1.1319 +
1.1320 +Address LIR_Assembler::as_Address(LIR_Address* addr) {
1.1321 + Register reg = addr->base()->as_pointer_register();
1.1322 + LIR_Opr index = addr->index();
1.1323 + if (index->is_illegal()) {
1.1324 + return Address(reg, addr->disp());
1.1325 + } else {
1.1326 + assert (addr->disp() == 0, "unsupported address mode");
1.1327 + return Address(reg, index->as_pointer_register());
1.1328 + }
1.1329 +}
1.1330 +
1.1331 +
1.1332 +void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1.1333 + switch (type) {
1.1334 + case T_INT:
1.1335 + case T_FLOAT: {
1.1336 + Register tmp = O7;
1.1337 + Address from = frame_map()->address_for_slot(src->single_stack_ix());
1.1338 + Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1.1339 + __ lduw(from.base(), from.disp(), tmp);
1.1340 + __ stw(tmp, to.base(), to.disp());
1.1341 + break;
1.1342 + }
1.1343 + case T_OBJECT: {
1.1344 + Register tmp = O7;
1.1345 + Address from = frame_map()->address_for_slot(src->single_stack_ix());
1.1346 + Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1.1347 + __ ld_ptr(from.base(), from.disp(), tmp);
1.1348 + __ st_ptr(tmp, to.base(), to.disp());
1.1349 + break;
1.1350 + }
1.1351 + case T_LONG:
1.1352 + case T_DOUBLE: {
1.1353 + Register tmp = O7;
1.1354 + Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1.1355 + Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1.1356 + __ lduw(from.base(), from.disp(), tmp);
1.1357 + __ stw(tmp, to.base(), to.disp());
1.1358 + __ lduw(from.base(), from.disp() + 4, tmp);
1.1359 + __ stw(tmp, to.base(), to.disp() + 4);
1.1360 + break;
1.1361 + }
1.1362 +
1.1363 + default:
1.1364 + ShouldNotReachHere();
1.1365 + }
1.1366 +}
1.1367 +
1.1368 +
1.1369 +Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1.1370 + Address base = as_Address(addr);
1.1371 + return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1.1372 +}
1.1373 +
1.1374 +
1.1375 +Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1.1376 + Address base = as_Address(addr);
1.1377 + return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1.1378 +}
1.1379 +
1.1380 +
1.1381 +void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1.1382 + LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
1.1383 +
1.1384 + assert(type != T_METADATA, "load of metadata ptr not supported");
1.1385 + LIR_Address* addr = src_opr->as_address_ptr();
1.1386 + LIR_Opr to_reg = dest;
1.1387 +
1.1388 + Register src = addr->base()->as_pointer_register();
1.1389 + Register disp_reg = noreg;
1.1390 + int disp_value = addr->disp();
1.1391 + bool needs_patching = (patch_code != lir_patch_none);
1.1392 +
1.1393 + if (addr->base()->type() == T_OBJECT) {
1.1394 + __ verify_oop(src);
1.1395 + }
1.1396 +
1.1397 + PatchingStub* patch = NULL;
1.1398 + if (needs_patching) {
1.1399 + patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1.1400 + assert(!to_reg->is_double_cpu() ||
1.1401 + patch_code == lir_patch_none ||
1.1402 + patch_code == lir_patch_normal, "patching doesn't match register");
1.1403 + }
1.1404 +
1.1405 + if (addr->index()->is_illegal()) {
1.1406 + if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1.1407 + if (needs_patching) {
1.1408 + __ patchable_set(0, O7);
1.1409 + } else {
1.1410 + __ set(disp_value, O7);
1.1411 + }
1.1412 + disp_reg = O7;
1.1413 + }
1.1414 + } else if (unaligned || PatchALot) {
1.1415 + __ add(src, addr->index()->as_register(), O7);
1.1416 + src = O7;
1.1417 + } else {
1.1418 + disp_reg = addr->index()->as_pointer_register();
1.1419 + assert(disp_value == 0, "can't handle 3 operand addresses");
1.1420 + }
1.1421 +
1.1422 + // remember the offset of the load. The patching_epilog must be done
1.1423 + // before the call to add_debug_info, otherwise the PcDescs don't get
1.1424 + // entered in increasing order.
1.1425 + int offset = code_offset();
1.1426 +
1.1427 + assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1.1428 + if (disp_reg == noreg) {
1.1429 + offset = load(src, disp_value, to_reg, type, wide, unaligned);
1.1430 + } else {
1.1431 + assert(!unaligned, "can't handle this");
1.1432 + offset = load(src, disp_reg, to_reg, type, wide);
1.1433 + }
1.1434 +
1.1435 + if (patch != NULL) {
1.1436 + patching_epilog(patch, patch_code, src, info);
1.1437 + }
1.1438 + if (info != NULL) add_debug_info_for_null_check(offset, info);
1.1439 +}
1.1440 +
1.1441 +
1.1442 +void LIR_Assembler::prefetchr(LIR_Opr src) {
1.1443 + LIR_Address* addr = src->as_address_ptr();
1.1444 + Address from_addr = as_Address(addr);
1.1445 +
1.1446 + if (VM_Version::has_v9()) {
1.1447 + __ prefetch(from_addr, Assembler::severalReads);
1.1448 + }
1.1449 +}
1.1450 +
1.1451 +
1.1452 +void LIR_Assembler::prefetchw(LIR_Opr src) {
1.1453 + LIR_Address* addr = src->as_address_ptr();
1.1454 + Address from_addr = as_Address(addr);
1.1455 +
1.1456 + if (VM_Version::has_v9()) {
1.1457 + __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads);
1.1458 + }
1.1459 +}
1.1460 +
1.1461 +
1.1462 +void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1.1463 + Address addr;
1.1464 + if (src->is_single_word()) {
1.1465 + addr = frame_map()->address_for_slot(src->single_stack_ix());
1.1466 + } else if (src->is_double_word()) {
1.1467 + addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1.1468 + }
1.1469 +
1.1470 + bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1.1471 + load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
1.1472 +}
1.1473 +
1.1474 +
1.1475 +void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1.1476 + Address addr;
1.1477 + if (dest->is_single_word()) {
1.1478 + addr = frame_map()->address_for_slot(dest->single_stack_ix());
1.1479 + } else if (dest->is_double_word()) {
1.1480 + addr = frame_map()->address_for_slot(dest->double_stack_ix());
1.1481 + }
1.1482 + bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1.1483 + store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1.1484 +}
1.1485 +
1.1486 +
1.1487 +void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1.1488 + if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1.1489 + if (from_reg->is_double_fpu()) {
1.1490 + // double to double moves
1.1491 + assert(to_reg->is_double_fpu(), "should match");
1.1492 + __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1.1493 + } else {
1.1494 + // float to float moves
1.1495 + assert(to_reg->is_single_fpu(), "should match");
1.1496 + __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1.1497 + }
1.1498 + } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1.1499 + if (from_reg->is_double_cpu()) {
1.1500 +#ifdef _LP64
1.1501 + __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1.1502 +#else
1.1503 + assert(to_reg->is_double_cpu() &&
1.1504 + from_reg->as_register_hi() != to_reg->as_register_lo() &&
1.1505 + from_reg->as_register_lo() != to_reg->as_register_hi(),
1.1506 + "should both be long and not overlap");
1.1507 + // long to long moves
1.1508 + __ mov(from_reg->as_register_hi(), to_reg->as_register_hi());
1.1509 + __ mov(from_reg->as_register_lo(), to_reg->as_register_lo());
1.1510 +#endif
1.1511 +#ifdef _LP64
1.1512 + } else if (to_reg->is_double_cpu()) {
1.1513 + // int to int moves
1.1514 + __ mov(from_reg->as_register(), to_reg->as_register_lo());
1.1515 +#endif
1.1516 + } else {
1.1517 + // int to int moves
1.1518 + __ mov(from_reg->as_register(), to_reg->as_register());
1.1519 + }
1.1520 + } else {
1.1521 + ShouldNotReachHere();
1.1522 + }
1.1523 + if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1.1524 + __ verify_oop(to_reg->as_register());
1.1525 + }
1.1526 +}
1.1527 +
1.1528 +
1.1529 +void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1.1530 + LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1.1531 + bool wide, bool unaligned) {
1.1532 + assert(type != T_METADATA, "store of metadata ptr not supported");
1.1533 + LIR_Address* addr = dest->as_address_ptr();
1.1534 +
1.1535 + Register src = addr->base()->as_pointer_register();
1.1536 + Register disp_reg = noreg;
1.1537 + int disp_value = addr->disp();
1.1538 + bool needs_patching = (patch_code != lir_patch_none);
1.1539 +
1.1540 + if (addr->base()->is_oop_register()) {
1.1541 + __ verify_oop(src);
1.1542 + }
1.1543 +
1.1544 + PatchingStub* patch = NULL;
1.1545 + if (needs_patching) {
1.1546 + patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1.1547 + assert(!from_reg->is_double_cpu() ||
1.1548 + patch_code == lir_patch_none ||
1.1549 + patch_code == lir_patch_normal, "patching doesn't match register");
1.1550 + }
1.1551 +
1.1552 + if (addr->index()->is_illegal()) {
1.1553 + if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1.1554 + if (needs_patching) {
1.1555 + __ patchable_set(0, O7);
1.1556 + } else {
1.1557 + __ set(disp_value, O7);
1.1558 + }
1.1559 + disp_reg = O7;
1.1560 + }
1.1561 + } else if (unaligned || PatchALot) {
1.1562 + __ add(src, addr->index()->as_register(), O7);
1.1563 + src = O7;
1.1564 + } else {
1.1565 + disp_reg = addr->index()->as_pointer_register();
1.1566 + assert(disp_value == 0, "can't handle 3 operand addresses");
1.1567 + }
1.1568 +
1.1569 + // remember the offset of the store. The patching_epilog must be done
1.1570 + // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1.1571 + // entered in increasing order.
1.1572 + int offset;
1.1573 +
1.1574 + assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1.1575 + if (disp_reg == noreg) {
1.1576 + offset = store(from_reg, src, disp_value, type, wide, unaligned);
1.1577 + } else {
1.1578 + assert(!unaligned, "can't handle this");
1.1579 + offset = store(from_reg, src, disp_reg, type, wide);
1.1580 + }
1.1581 +
1.1582 + if (patch != NULL) {
1.1583 + patching_epilog(patch, patch_code, src, info);
1.1584 + }
1.1585 +
1.1586 + if (info != NULL) add_debug_info_for_null_check(offset, info);
1.1587 +}
1.1588 +
1.1589 +
1.1590 +void LIR_Assembler::return_op(LIR_Opr result) {
1.1591 + // the poll may need a register so just pick one that isn't the return register
1.1592 +#if defined(TIERED) && !defined(_LP64)
1.1593 + if (result->type_field() == LIR_OprDesc::long_type) {
1.1594 + // Must move the result to G1
1.1595 + // Must leave proper result in O0,O1 and G1 (TIERED only)
1.1596 + __ sllx(I0, 32, G1); // Shift bits into high G1
1.1597 + __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
1.1598 + __ or3 (I1, G1, G1); // OR 64 bits into G1
1.1599 +#ifdef ASSERT
1.1600 + // mangle it so any problems will show up
1.1601 + __ set(0xdeadbeef, I0);
1.1602 + __ set(0xdeadbeef, I1);
1.1603 +#endif
1.1604 + }
1.1605 +#endif // TIERED
1.1606 + __ set((intptr_t)os::get_polling_page(), L0);
1.1607 + __ relocate(relocInfo::poll_return_type);
1.1608 + __ ld_ptr(L0, 0, G0);
1.1609 + __ ret();
1.1610 + __ delayed()->restore();
1.1611 +}
1.1612 +
1.1613 +
1.1614 +int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1.1615 + __ set((intptr_t)os::get_polling_page(), tmp->as_register());
1.1616 + if (info != NULL) {
1.1617 + add_debug_info_for_branch(info);
1.1618 + } else {
1.1619 + __ relocate(relocInfo::poll_type);
1.1620 + }
1.1621 +
1.1622 + int offset = __ offset();
1.1623 + __ ld_ptr(tmp->as_register(), 0, G0);
1.1624 +
1.1625 + return offset;
1.1626 +}
1.1627 +
1.1628 +
1.1629 +void LIR_Assembler::emit_static_call_stub() {
1.1630 + address call_pc = __ pc();
1.1631 + address stub = __ start_a_stub(call_stub_size);
1.1632 + if (stub == NULL) {
1.1633 + bailout("static call stub overflow");
1.1634 + return;
1.1635 + }
1.1636 +
1.1637 + int start = __ offset();
1.1638 + __ relocate(static_stub_Relocation::spec(call_pc));
1.1639 +
1.1640 + __ set_metadata(NULL, G5);
1.1641 + // must be set to -1 at code generation time
1.1642 + AddressLiteral addrlit(-1);
1.1643 + __ jump_to(addrlit, G3);
1.1644 + __ delayed()->nop();
1.1645 +
1.1646 + assert(__ offset() - start <= call_stub_size, "stub too big");
1.1647 + __ end_a_stub();
1.1648 +}
1.1649 +
1.1650 +
1.1651 +void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1.1652 + if (opr1->is_single_fpu()) {
1.1653 + __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
1.1654 + } else if (opr1->is_double_fpu()) {
1.1655 + __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
1.1656 + } else if (opr1->is_single_cpu()) {
1.1657 + if (opr2->is_constant()) {
1.1658 + switch (opr2->as_constant_ptr()->type()) {
1.1659 + case T_INT:
1.1660 + { jint con = opr2->as_constant_ptr()->as_jint();
1.1661 + if (Assembler::is_simm13(con)) {
1.1662 + __ cmp(opr1->as_register(), con);
1.1663 + } else {
1.1664 + __ set(con, O7);
1.1665 + __ cmp(opr1->as_register(), O7);
1.1666 + }
1.1667 + }
1.1668 + break;
1.1669 +
1.1670 + case T_OBJECT:
1.1671 + // there are only equal/notequal comparisions on objects
1.1672 + { jobject con = opr2->as_constant_ptr()->as_jobject();
1.1673 + if (con == NULL) {
1.1674 + __ cmp(opr1->as_register(), 0);
1.1675 + } else {
1.1676 + jobject2reg(con, O7);
1.1677 + __ cmp(opr1->as_register(), O7);
1.1678 + }
1.1679 + }
1.1680 + break;
1.1681 +
1.1682 + default:
1.1683 + ShouldNotReachHere();
1.1684 + break;
1.1685 + }
1.1686 + } else {
1.1687 + if (opr2->is_address()) {
1.1688 + LIR_Address * addr = opr2->as_address_ptr();
1.1689 + BasicType type = addr->type();
1.1690 + if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1.1691 + else __ ld(as_Address(addr), O7);
1.1692 + __ cmp(opr1->as_register(), O7);
1.1693 + } else {
1.1694 + __ cmp(opr1->as_register(), opr2->as_register());
1.1695 + }
1.1696 + }
1.1697 + } else if (opr1->is_double_cpu()) {
1.1698 + Register xlo = opr1->as_register_lo();
1.1699 + Register xhi = opr1->as_register_hi();
1.1700 + if (opr2->is_constant() && opr2->as_jlong() == 0) {
1.1701 + assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
1.1702 +#ifdef _LP64
1.1703 + __ orcc(xhi, G0, G0);
1.1704 +#else
1.1705 + __ orcc(xhi, xlo, G0);
1.1706 +#endif
1.1707 + } else if (opr2->is_register()) {
1.1708 + Register ylo = opr2->as_register_lo();
1.1709 + Register yhi = opr2->as_register_hi();
1.1710 +#ifdef _LP64
1.1711 + __ cmp(xlo, ylo);
1.1712 +#else
1.1713 + __ subcc(xlo, ylo, xlo);
1.1714 + __ subccc(xhi, yhi, xhi);
1.1715 + if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
1.1716 + __ orcc(xhi, xlo, G0);
1.1717 + }
1.1718 +#endif
1.1719 + } else {
1.1720 + ShouldNotReachHere();
1.1721 + }
1.1722 + } else if (opr1->is_address()) {
1.1723 + LIR_Address * addr = opr1->as_address_ptr();
1.1724 + BasicType type = addr->type();
1.1725 + assert (opr2->is_constant(), "Checking");
1.1726 + if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1.1727 + else __ ld(as_Address(addr), O7);
1.1728 + __ cmp(O7, opr2->as_constant_ptr()->as_jint());
1.1729 + } else {
1.1730 + ShouldNotReachHere();
1.1731 + }
1.1732 +}
1.1733 +
1.1734 +
1.1735 +void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1.1736 + if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1.1737 + bool is_unordered_less = (code == lir_ucmp_fd2i);
1.1738 + if (left->is_single_fpu()) {
1.1739 + __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1.1740 + } else if (left->is_double_fpu()) {
1.1741 + __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1.1742 + } else {
1.1743 + ShouldNotReachHere();
1.1744 + }
1.1745 + } else if (code == lir_cmp_l2i) {
1.1746 +#ifdef _LP64
1.1747 + __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register());
1.1748 +#else
1.1749 + __ lcmp(left->as_register_hi(), left->as_register_lo(),
1.1750 + right->as_register_hi(), right->as_register_lo(),
1.1751 + dst->as_register());
1.1752 +#endif
1.1753 + } else {
1.1754 + ShouldNotReachHere();
1.1755 + }
1.1756 +}
1.1757 +
1.1758 +
1.1759 +void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1.1760 + Assembler::Condition acond;
1.1761 + switch (condition) {
1.1762 + case lir_cond_equal: acond = Assembler::equal; break;
1.1763 + case lir_cond_notEqual: acond = Assembler::notEqual; break;
1.1764 + case lir_cond_less: acond = Assembler::less; break;
1.1765 + case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1.1766 + case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1.1767 + case lir_cond_greater: acond = Assembler::greater; break;
1.1768 + case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1.1769 + case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1.1770 + default: ShouldNotReachHere();
1.1771 + };
1.1772 +
1.1773 + if (opr1->is_constant() && opr1->type() == T_INT) {
1.1774 + Register dest = result->as_register();
1.1775 + // load up first part of constant before branch
1.1776 + // and do the rest in the delay slot.
1.1777 + if (!Assembler::is_simm13(opr1->as_jint())) {
1.1778 + __ sethi(opr1->as_jint(), dest);
1.1779 + }
1.1780 + } else if (opr1->is_constant()) {
1.1781 + const2reg(opr1, result, lir_patch_none, NULL);
1.1782 + } else if (opr1->is_register()) {
1.1783 + reg2reg(opr1, result);
1.1784 + } else if (opr1->is_stack()) {
1.1785 + stack2reg(opr1, result, result->type());
1.1786 + } else {
1.1787 + ShouldNotReachHere();
1.1788 + }
1.1789 + Label skip;
1.1790 +#ifdef _LP64
1.1791 + if (type == T_INT) {
1.1792 + __ br(acond, false, Assembler::pt, skip);
1.1793 + } else
1.1794 +#endif
1.1795 + __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit
1.1796 + if (opr1->is_constant() && opr1->type() == T_INT) {
1.1797 + Register dest = result->as_register();
1.1798 + if (Assembler::is_simm13(opr1->as_jint())) {
1.1799 + __ delayed()->or3(G0, opr1->as_jint(), dest);
1.1800 + } else {
1.1801 + // the sethi has been done above, so just put in the low 10 bits
1.1802 + __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1.1803 + }
1.1804 + } else {
1.1805 + // can't do anything useful in the delay slot
1.1806 + __ delayed()->nop();
1.1807 + }
1.1808 + if (opr2->is_constant()) {
1.1809 + const2reg(opr2, result, lir_patch_none, NULL);
1.1810 + } else if (opr2->is_register()) {
1.1811 + reg2reg(opr2, result);
1.1812 + } else if (opr2->is_stack()) {
1.1813 + stack2reg(opr2, result, result->type());
1.1814 + } else {
1.1815 + ShouldNotReachHere();
1.1816 + }
1.1817 + __ bind(skip);
1.1818 +}
1.1819 +
1.1820 +
1.1821 +void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1.1822 + assert(info == NULL, "unused on this code path");
1.1823 + assert(left->is_register(), "wrong items state");
1.1824 + assert(dest->is_register(), "wrong items state");
1.1825 +
1.1826 + if (right->is_register()) {
1.1827 + if (dest->is_float_kind()) {
1.1828 +
1.1829 + FloatRegister lreg, rreg, res;
1.1830 + FloatRegisterImpl::Width w;
1.1831 + if (right->is_single_fpu()) {
1.1832 + w = FloatRegisterImpl::S;
1.1833 + lreg = left->as_float_reg();
1.1834 + rreg = right->as_float_reg();
1.1835 + res = dest->as_float_reg();
1.1836 + } else {
1.1837 + w = FloatRegisterImpl::D;
1.1838 + lreg = left->as_double_reg();
1.1839 + rreg = right->as_double_reg();
1.1840 + res = dest->as_double_reg();
1.1841 + }
1.1842 +
1.1843 + switch (code) {
1.1844 + case lir_add: __ fadd(w, lreg, rreg, res); break;
1.1845 + case lir_sub: __ fsub(w, lreg, rreg, res); break;
1.1846 + case lir_mul: // fall through
1.1847 + case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
1.1848 + case lir_div: // fall through
1.1849 + case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
1.1850 + default: ShouldNotReachHere();
1.1851 + }
1.1852 +
1.1853 + } else if (dest->is_double_cpu()) {
1.1854 +#ifdef _LP64
1.1855 + Register dst_lo = dest->as_register_lo();
1.1856 + Register op1_lo = left->as_pointer_register();
1.1857 + Register op2_lo = right->as_pointer_register();
1.1858 +
1.1859 + switch (code) {
1.1860 + case lir_add:
1.1861 + __ add(op1_lo, op2_lo, dst_lo);
1.1862 + break;
1.1863 +
1.1864 + case lir_sub:
1.1865 + __ sub(op1_lo, op2_lo, dst_lo);
1.1866 + break;
1.1867 +
1.1868 + default: ShouldNotReachHere();
1.1869 + }
1.1870 +#else
1.1871 + Register op1_lo = left->as_register_lo();
1.1872 + Register op1_hi = left->as_register_hi();
1.1873 + Register op2_lo = right->as_register_lo();
1.1874 + Register op2_hi = right->as_register_hi();
1.1875 + Register dst_lo = dest->as_register_lo();
1.1876 + Register dst_hi = dest->as_register_hi();
1.1877 +
1.1878 + switch (code) {
1.1879 + case lir_add:
1.1880 + __ addcc(op1_lo, op2_lo, dst_lo);
1.1881 + __ addc (op1_hi, op2_hi, dst_hi);
1.1882 + break;
1.1883 +
1.1884 + case lir_sub:
1.1885 + __ subcc(op1_lo, op2_lo, dst_lo);
1.1886 + __ subc (op1_hi, op2_hi, dst_hi);
1.1887 + break;
1.1888 +
1.1889 + default: ShouldNotReachHere();
1.1890 + }
1.1891 +#endif
1.1892 + } else {
1.1893 + assert (right->is_single_cpu(), "Just Checking");
1.1894 +
1.1895 + Register lreg = left->as_register();
1.1896 + Register res = dest->as_register();
1.1897 + Register rreg = right->as_register();
1.1898 + switch (code) {
1.1899 + case lir_add: __ add (lreg, rreg, res); break;
1.1900 + case lir_sub: __ sub (lreg, rreg, res); break;
1.1901 + case lir_mul: __ mulx (lreg, rreg, res); break;
1.1902 + default: ShouldNotReachHere();
1.1903 + }
1.1904 + }
1.1905 + } else {
1.1906 + assert (right->is_constant(), "must be constant");
1.1907 +
1.1908 + if (dest->is_single_cpu()) {
1.1909 + Register lreg = left->as_register();
1.1910 + Register res = dest->as_register();
1.1911 + int simm13 = right->as_constant_ptr()->as_jint();
1.1912 +
1.1913 + switch (code) {
1.1914 + case lir_add: __ add (lreg, simm13, res); break;
1.1915 + case lir_sub: __ sub (lreg, simm13, res); break;
1.1916 + case lir_mul: __ mulx (lreg, simm13, res); break;
1.1917 + default: ShouldNotReachHere();
1.1918 + }
1.1919 + } else {
1.1920 + Register lreg = left->as_pointer_register();
1.1921 + Register res = dest->as_register_lo();
1.1922 + long con = right->as_constant_ptr()->as_jlong();
1.1923 + assert(Assembler::is_simm13(con), "must be simm13");
1.1924 +
1.1925 + switch (code) {
1.1926 + case lir_add: __ add (lreg, (int)con, res); break;
1.1927 + case lir_sub: __ sub (lreg, (int)con, res); break;
1.1928 + case lir_mul: __ mulx (lreg, (int)con, res); break;
1.1929 + default: ShouldNotReachHere();
1.1930 + }
1.1931 + }
1.1932 + }
1.1933 +}
1.1934 +
1.1935 +
1.1936 +void LIR_Assembler::fpop() {
1.1937 + // do nothing
1.1938 +}
1.1939 +
1.1940 +
1.1941 +void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1.1942 + switch (code) {
1.1943 + case lir_sin:
1.1944 + case lir_tan:
1.1945 + case lir_cos: {
1.1946 + assert(thread->is_valid(), "preserve the thread object for performance reasons");
1.1947 + assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
1.1948 + break;
1.1949 + }
1.1950 + case lir_sqrt: {
1.1951 + assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1.1952 + FloatRegister src_reg = value->as_double_reg();
1.1953 + FloatRegister dst_reg = dest->as_double_reg();
1.1954 + __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
1.1955 + break;
1.1956 + }
1.1957 + case lir_abs: {
1.1958 + assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1.1959 + FloatRegister src_reg = value->as_double_reg();
1.1960 + FloatRegister dst_reg = dest->as_double_reg();
1.1961 + __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
1.1962 + break;
1.1963 + }
1.1964 + default: {
1.1965 + ShouldNotReachHere();
1.1966 + break;
1.1967 + }
1.1968 + }
1.1969 +}
1.1970 +
1.1971 +
1.1972 +void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1.1973 + if (right->is_constant()) {
1.1974 + if (dest->is_single_cpu()) {
1.1975 + int simm13 = right->as_constant_ptr()->as_jint();
1.1976 + switch (code) {
1.1977 + case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
1.1978 + case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
1.1979 + case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
1.1980 + default: ShouldNotReachHere();
1.1981 + }
1.1982 + } else {
1.1983 + long c = right->as_constant_ptr()->as_jlong();
1.1984 + assert(c == (int)c && Assembler::is_simm13(c), "out of range");
1.1985 + int simm13 = (int)c;
1.1986 + switch (code) {
1.1987 + case lir_logic_and:
1.1988 +#ifndef _LP64
1.1989 + __ and3 (left->as_register_hi(), 0, dest->as_register_hi());
1.1990 +#endif
1.1991 + __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
1.1992 + break;
1.1993 +
1.1994 + case lir_logic_or:
1.1995 +#ifndef _LP64
1.1996 + __ or3 (left->as_register_hi(), 0, dest->as_register_hi());
1.1997 +#endif
1.1998 + __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
1.1999 + break;
1.2000 +
1.2001 + case lir_logic_xor:
1.2002 +#ifndef _LP64
1.2003 + __ xor3 (left->as_register_hi(), 0, dest->as_register_hi());
1.2004 +#endif
1.2005 + __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
1.2006 + break;
1.2007 +
1.2008 + default: ShouldNotReachHere();
1.2009 + }
1.2010 + }
1.2011 + } else {
1.2012 + assert(right->is_register(), "right should be in register");
1.2013 +
1.2014 + if (dest->is_single_cpu()) {
1.2015 + switch (code) {
1.2016 + case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
1.2017 + case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
1.2018 + case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
1.2019 + default: ShouldNotReachHere();
1.2020 + }
1.2021 + } else {
1.2022 +#ifdef _LP64
1.2023 + Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1.2024 + left->as_register_lo();
1.2025 + Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1.2026 + right->as_register_lo();
1.2027 +
1.2028 + switch (code) {
1.2029 + case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
1.2030 + case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
1.2031 + case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
1.2032 + default: ShouldNotReachHere();
1.2033 + }
1.2034 +#else
1.2035 + switch (code) {
1.2036 + case lir_logic_and:
1.2037 + __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
1.2038 + __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
1.2039 + break;
1.2040 +
1.2041 + case lir_logic_or:
1.2042 + __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
1.2043 + __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
1.2044 + break;
1.2045 +
1.2046 + case lir_logic_xor:
1.2047 + __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
1.2048 + __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
1.2049 + break;
1.2050 +
1.2051 + default: ShouldNotReachHere();
1.2052 + }
1.2053 +#endif
1.2054 + }
1.2055 + }
1.2056 +}
1.2057 +
1.2058 +
1.2059 +int LIR_Assembler::shift_amount(BasicType t) {
1.2060 + int elem_size = type2aelembytes(t);
1.2061 + switch (elem_size) {
1.2062 + case 1 : return 0;
1.2063 + case 2 : return 1;
1.2064 + case 4 : return 2;
1.2065 + case 8 : return 3;
1.2066 + }
1.2067 + ShouldNotReachHere();
1.2068 + return -1;
1.2069 +}
1.2070 +
1.2071 +
1.2072 +void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1.2073 + assert(exceptionOop->as_register() == Oexception, "should match");
1.2074 + assert(exceptionPC->as_register() == Oissuing_pc, "should match");
1.2075 +
1.2076 + info->add_register_oop(exceptionOop);
1.2077 +
1.2078 + // reuse the debug info from the safepoint poll for the throw op itself
1.2079 + address pc_for_athrow = __ pc();
1.2080 + int pc_for_athrow_offset = __ offset();
1.2081 + RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1.2082 + __ set(pc_for_athrow, Oissuing_pc, rspec);
1.2083 + add_call_info(pc_for_athrow_offset, info); // for exception handler
1.2084 +
1.2085 + __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
1.2086 + __ delayed()->nop();
1.2087 +}
1.2088 +
1.2089 +
1.2090 +void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1.2091 + assert(exceptionOop->as_register() == Oexception, "should match");
1.2092 +
1.2093 + __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry);
1.2094 + __ delayed()->nop();
1.2095 +}
1.2096 +
1.2097 +void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1.2098 + Register src = op->src()->as_register();
1.2099 + Register dst = op->dst()->as_register();
1.2100 + Register src_pos = op->src_pos()->as_register();
1.2101 + Register dst_pos = op->dst_pos()->as_register();
1.2102 + Register length = op->length()->as_register();
1.2103 + Register tmp = op->tmp()->as_register();
1.2104 + Register tmp2 = O7;
1.2105 +
1.2106 + int flags = op->flags();
1.2107 + ciArrayKlass* default_type = op->expected_type();
1.2108 + BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1.2109 + if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1.2110 +
1.2111 +#ifdef _LP64
1.2112 + // higher 32bits must be null
1.2113 + __ sra(dst_pos, 0, dst_pos);
1.2114 + __ sra(src_pos, 0, src_pos);
1.2115 + __ sra(length, 0, length);
1.2116 +#endif
1.2117 +
1.2118 + // set up the arraycopy stub information
1.2119 + ArrayCopyStub* stub = op->stub();
1.2120 +
1.2121 + // always do stub if no type information is available. it's ok if
1.2122 + // the known type isn't loaded since the code sanity checks
1.2123 + // in debug mode and the type isn't required when we know the exact type
1.2124 + // also check that the type is an array type.
1.2125 + if (op->expected_type() == NULL) {
1.2126 + __ mov(src, O0);
1.2127 + __ mov(src_pos, O1);
1.2128 + __ mov(dst, O2);
1.2129 + __ mov(dst_pos, O3);
1.2130 + __ mov(length, O4);
1.2131 + address copyfunc_addr = StubRoutines::generic_arraycopy();
1.2132 +
1.2133 + if (copyfunc_addr == NULL) { // Use C version if stub was not generated
1.2134 + __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
1.2135 + } else {
1.2136 +#ifndef PRODUCT
1.2137 + if (PrintC1Statistics) {
1.2138 + address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1.2139 + __ inc_counter(counter, G1, G3);
1.2140 + }
1.2141 +#endif
1.2142 + __ call_VM_leaf(tmp, copyfunc_addr);
1.2143 + }
1.2144 +
1.2145 + if (copyfunc_addr != NULL) {
1.2146 + __ xor3(O0, -1, tmp);
1.2147 + __ sub(length, tmp, length);
1.2148 + __ add(src_pos, tmp, src_pos);
1.2149 + __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
1.2150 + __ delayed()->add(dst_pos, tmp, dst_pos);
1.2151 + } else {
1.2152 + __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
1.2153 + __ delayed()->nop();
1.2154 + }
1.2155 + __ bind(*stub->continuation());
1.2156 + return;
1.2157 + }
1.2158 +
1.2159 + assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
1.2160 +
1.2161 + // make sure src and dst are non-null and load array length
1.2162 + if (flags & LIR_OpArrayCopy::src_null_check) {
1.2163 + __ tst(src);
1.2164 + __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
1.2165 + __ delayed()->nop();
1.2166 + }
1.2167 +
1.2168 + if (flags & LIR_OpArrayCopy::dst_null_check) {
1.2169 + __ tst(dst);
1.2170 + __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
1.2171 + __ delayed()->nop();
1.2172 + }
1.2173 +
1.2174 + if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1.2175 + // test src_pos register
1.2176 + __ cmp_zero_and_br(Assembler::less, src_pos, *stub->entry());
1.2177 + __ delayed()->nop();
1.2178 + }
1.2179 +
1.2180 + if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1.2181 + // test dst_pos register
1.2182 + __ cmp_zero_and_br(Assembler::less, dst_pos, *stub->entry());
1.2183 + __ delayed()->nop();
1.2184 + }
1.2185 +
1.2186 + if (flags & LIR_OpArrayCopy::length_positive_check) {
1.2187 + // make sure length isn't negative
1.2188 + __ cmp_zero_and_br(Assembler::less, length, *stub->entry());
1.2189 + __ delayed()->nop();
1.2190 + }
1.2191 +
1.2192 + if (flags & LIR_OpArrayCopy::src_range_check) {
1.2193 + __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
1.2194 + __ add(length, src_pos, tmp);
1.2195 + __ cmp(tmp2, tmp);
1.2196 + __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
1.2197 + __ delayed()->nop();
1.2198 + }
1.2199 +
1.2200 + if (flags & LIR_OpArrayCopy::dst_range_check) {
1.2201 + __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
1.2202 + __ add(length, dst_pos, tmp);
1.2203 + __ cmp(tmp2, tmp);
1.2204 + __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
1.2205 + __ delayed()->nop();
1.2206 + }
1.2207 +
1.2208 + int shift = shift_amount(basic_type);
1.2209 +
1.2210 + if (flags & LIR_OpArrayCopy::type_check) {
1.2211 + // We don't know the array types are compatible
1.2212 + if (basic_type != T_OBJECT) {
1.2213 + // Simple test for basic type arrays
1.2214 + if (UseCompressedClassPointers) {
1.2215 + // We don't need decode because we just need to compare
1.2216 + __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp);
1.2217 + __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
1.2218 + __ cmp(tmp, tmp2);
1.2219 + __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
1.2220 + } else {
1.2221 + __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
1.2222 + __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
1.2223 + __ cmp(tmp, tmp2);
1.2224 + __ brx(Assembler::notEqual, false, Assembler::pt, *stub->entry());
1.2225 + }
1.2226 + __ delayed()->nop();
1.2227 + } else {
1.2228 + // For object arrays, if src is a sub class of dst then we can
1.2229 + // safely do the copy.
1.2230 + address copyfunc_addr = StubRoutines::checkcast_arraycopy();
1.2231 +
1.2232 + Label cont, slow;
1.2233 + assert_different_registers(tmp, tmp2, G3, G1);
1.2234 +
1.2235 + __ load_klass(src, G3);
1.2236 + __ load_klass(dst, G1);
1.2237 +
1.2238 + __ check_klass_subtype_fast_path(G3, G1, tmp, tmp2, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL);
1.2239 +
1.2240 + __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1.2241 + __ delayed()->nop();
1.2242 +
1.2243 + __ cmp(G3, 0);
1.2244 + if (copyfunc_addr != NULL) { // use stub if available
1.2245 + // src is not a sub class of dst so we have to do a
1.2246 + // per-element check.
1.2247 + __ br(Assembler::notEqual, false, Assembler::pt, cont);
1.2248 + __ delayed()->nop();
1.2249 +
1.2250 + __ bind(slow);
1.2251 +
1.2252 + int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
1.2253 + if ((flags & mask) != mask) {
1.2254 + // Check that at least both of them object arrays.
1.2255 + assert(flags & mask, "one of the two should be known to be an object array");
1.2256 +
1.2257 + if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1.2258 + __ load_klass(src, tmp);
1.2259 + } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1.2260 + __ load_klass(dst, tmp);
1.2261 + }
1.2262 + int lh_offset = in_bytes(Klass::layout_helper_offset());
1.2263 +
1.2264 + __ lduw(tmp, lh_offset, tmp2);
1.2265 +
1.2266 + jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
1.2267 + __ set(objArray_lh, tmp);
1.2268 + __ cmp(tmp, tmp2);
1.2269 + __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
1.2270 + __ delayed()->nop();
1.2271 + }
1.2272 +
1.2273 + Register src_ptr = O0;
1.2274 + Register dst_ptr = O1;
1.2275 + Register len = O2;
1.2276 + Register chk_off = O3;
1.2277 + Register super_k = O4;
1.2278 +
1.2279 + __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
1.2280 + if (shift == 0) {
1.2281 + __ add(src_ptr, src_pos, src_ptr);
1.2282 + } else {
1.2283 + __ sll(src_pos, shift, tmp);
1.2284 + __ add(src_ptr, tmp, src_ptr);
1.2285 + }
1.2286 +
1.2287 + __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
1.2288 + if (shift == 0) {
1.2289 + __ add(dst_ptr, dst_pos, dst_ptr);
1.2290 + } else {
1.2291 + __ sll(dst_pos, shift, tmp);
1.2292 + __ add(dst_ptr, tmp, dst_ptr);
1.2293 + }
1.2294 + __ mov(length, len);
1.2295 + __ load_klass(dst, tmp);
1.2296 +
1.2297 + int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
1.2298 + __ ld_ptr(tmp, ek_offset, super_k);
1.2299 +
1.2300 + int sco_offset = in_bytes(Klass::super_check_offset_offset());
1.2301 + __ lduw(super_k, sco_offset, chk_off);
1.2302 +
1.2303 + __ call_VM_leaf(tmp, copyfunc_addr);
1.2304 +
1.2305 +#ifndef PRODUCT
1.2306 + if (PrintC1Statistics) {
1.2307 + Label failed;
1.2308 + __ br_notnull_short(O0, Assembler::pn, failed);
1.2309 + __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, G1, G3);
1.2310 + __ bind(failed);
1.2311 + }
1.2312 +#endif
1.2313 +
1.2314 + __ br_null(O0, false, Assembler::pt, *stub->continuation());
1.2315 + __ delayed()->xor3(O0, -1, tmp);
1.2316 +
1.2317 +#ifndef PRODUCT
1.2318 + if (PrintC1Statistics) {
1.2319 + __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, G1, G3);
1.2320 + }
1.2321 +#endif
1.2322 +
1.2323 + __ sub(length, tmp, length);
1.2324 + __ add(src_pos, tmp, src_pos);
1.2325 + __ br(Assembler::always, false, Assembler::pt, *stub->entry());
1.2326 + __ delayed()->add(dst_pos, tmp, dst_pos);
1.2327 +
1.2328 + __ bind(cont);
1.2329 + } else {
1.2330 + __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
1.2331 + __ delayed()->nop();
1.2332 + __ bind(cont);
1.2333 + }
1.2334 + }
1.2335 + }
1.2336 +
1.2337 +#ifdef ASSERT
1.2338 + if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
1.2339 + // Sanity check the known type with the incoming class. For the
1.2340 + // primitive case the types must match exactly with src.klass and
1.2341 + // dst.klass each exactly matching the default type. For the
1.2342 + // object array case, if no type check is needed then either the
1.2343 + // dst type is exactly the expected type and the src type is a
1.2344 + // subtype which we can't check or src is the same array as dst
1.2345 + // but not necessarily exactly of type default_type.
1.2346 + Label known_ok, halt;
1.2347 + metadata2reg(op->expected_type()->constant_encoding(), tmp);
1.2348 + if (UseCompressedClassPointers) {
1.2349 + // tmp holds the default type. It currently comes uncompressed after the
1.2350 + // load of a constant, so encode it.
1.2351 + __ encode_klass_not_null(tmp);
1.2352 + // load the raw value of the dst klass, since we will be comparing
1.2353 + // uncompressed values directly.
1.2354 + __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
1.2355 + if (basic_type != T_OBJECT) {
1.2356 + __ cmp(tmp, tmp2);
1.2357 + __ br(Assembler::notEqual, false, Assembler::pn, halt);
1.2358 + // load the raw value of the src klass.
1.2359 + __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2);
1.2360 + __ cmp_and_br_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
1.2361 + } else {
1.2362 + __ cmp(tmp, tmp2);
1.2363 + __ br(Assembler::equal, false, Assembler::pn, known_ok);
1.2364 + __ delayed()->cmp(src, dst);
1.2365 + __ brx(Assembler::equal, false, Assembler::pn, known_ok);
1.2366 + __ delayed()->nop();
1.2367 + }
1.2368 + } else {
1.2369 + __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
1.2370 + if (basic_type != T_OBJECT) {
1.2371 + __ cmp(tmp, tmp2);
1.2372 + __ brx(Assembler::notEqual, false, Assembler::pn, halt);
1.2373 + __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
1.2374 + __ cmp_and_brx_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
1.2375 + } else {
1.2376 + __ cmp(tmp, tmp2);
1.2377 + __ brx(Assembler::equal, false, Assembler::pn, known_ok);
1.2378 + __ delayed()->cmp(src, dst);
1.2379 + __ brx(Assembler::equal, false, Assembler::pn, known_ok);
1.2380 + __ delayed()->nop();
1.2381 + }
1.2382 + }
1.2383 + __ bind(halt);
1.2384 + __ stop("incorrect type information in arraycopy");
1.2385 + __ bind(known_ok);
1.2386 + }
1.2387 +#endif
1.2388 +
1.2389 +#ifndef PRODUCT
1.2390 + if (PrintC1Statistics) {
1.2391 + address counter = Runtime1::arraycopy_count_address(basic_type);
1.2392 + __ inc_counter(counter, G1, G3);
1.2393 + }
1.2394 +#endif
1.2395 +
1.2396 + Register src_ptr = O0;
1.2397 + Register dst_ptr = O1;
1.2398 + Register len = O2;
1.2399 +
1.2400 + __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
1.2401 + if (shift == 0) {
1.2402 + __ add(src_ptr, src_pos, src_ptr);
1.2403 + } else {
1.2404 + __ sll(src_pos, shift, tmp);
1.2405 + __ add(src_ptr, tmp, src_ptr);
1.2406 + }
1.2407 +
1.2408 + __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
1.2409 + if (shift == 0) {
1.2410 + __ add(dst_ptr, dst_pos, dst_ptr);
1.2411 + } else {
1.2412 + __ sll(dst_pos, shift, tmp);
1.2413 + __ add(dst_ptr, tmp, dst_ptr);
1.2414 + }
1.2415 +
1.2416 + bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
1.2417 + bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
1.2418 + const char *name;
1.2419 + address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
1.2420 +
1.2421 + // arraycopy stubs takes a length in number of elements, so don't scale it.
1.2422 + __ mov(length, len);
1.2423 + __ call_VM_leaf(tmp, entry);
1.2424 +
1.2425 + __ bind(*stub->continuation());
1.2426 +}
1.2427 +
1.2428 +
1.2429 +void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
1.2430 + if (dest->is_single_cpu()) {
1.2431 +#ifdef _LP64
1.2432 + if (left->type() == T_OBJECT) {
1.2433 + switch (code) {
1.2434 + case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
1.2435 + case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
1.2436 + case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
1.2437 + default: ShouldNotReachHere();
1.2438 + }
1.2439 + } else
1.2440 +#endif
1.2441 + switch (code) {
1.2442 + case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
1.2443 + case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
1.2444 + case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
1.2445 + default: ShouldNotReachHere();
1.2446 + }
1.2447 + } else {
1.2448 +#ifdef _LP64
1.2449 + switch (code) {
1.2450 + case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
1.2451 + case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
1.2452 + case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
1.2453 + default: ShouldNotReachHere();
1.2454 + }
1.2455 +#else
1.2456 + switch (code) {
1.2457 + case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
1.2458 + case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
1.2459 + case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
1.2460 + default: ShouldNotReachHere();
1.2461 + }
1.2462 +#endif
1.2463 + }
1.2464 +}
1.2465 +
1.2466 +
1.2467 +void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
1.2468 +#ifdef _LP64
1.2469 + if (left->type() == T_OBJECT) {
1.2470 + count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
1.2471 + Register l = left->as_register();
1.2472 + Register d = dest->as_register_lo();
1.2473 + switch (code) {
1.2474 + case lir_shl: __ sllx (l, count, d); break;
1.2475 + case lir_shr: __ srax (l, count, d); break;
1.2476 + case lir_ushr: __ srlx (l, count, d); break;
1.2477 + default: ShouldNotReachHere();
1.2478 + }
1.2479 + return;
1.2480 + }
1.2481 +#endif
1.2482 +
1.2483 + if (dest->is_single_cpu()) {
1.2484 + count = count & 0x1F; // Java spec
1.2485 + switch (code) {
1.2486 + case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
1.2487 + case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
1.2488 + case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
1.2489 + default: ShouldNotReachHere();
1.2490 + }
1.2491 + } else if (dest->is_double_cpu()) {
1.2492 + count = count & 63; // Java spec
1.2493 + switch (code) {
1.2494 + case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
1.2495 + case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
1.2496 + case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
1.2497 + default: ShouldNotReachHere();
1.2498 + }
1.2499 + } else {
1.2500 + ShouldNotReachHere();
1.2501 + }
1.2502 +}
1.2503 +
1.2504 +
1.2505 +void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1.2506 + assert(op->tmp1()->as_register() == G1 &&
1.2507 + op->tmp2()->as_register() == G3 &&
1.2508 + op->tmp3()->as_register() == G4 &&
1.2509 + op->obj()->as_register() == O0 &&
1.2510 + op->klass()->as_register() == G5, "must be");
1.2511 + if (op->init_check()) {
1.2512 + __ ldub(op->klass()->as_register(),
1.2513 + in_bytes(InstanceKlass::init_state_offset()),
1.2514 + op->tmp1()->as_register());
1.2515 + add_debug_info_for_null_check_here(op->stub()->info());
1.2516 + __ cmp(op->tmp1()->as_register(), InstanceKlass::fully_initialized);
1.2517 + __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
1.2518 + __ delayed()->nop();
1.2519 + }
1.2520 + __ allocate_object(op->obj()->as_register(),
1.2521 + op->tmp1()->as_register(),
1.2522 + op->tmp2()->as_register(),
1.2523 + op->tmp3()->as_register(),
1.2524 + op->header_size(),
1.2525 + op->object_size(),
1.2526 + op->klass()->as_register(),
1.2527 + *op->stub()->entry());
1.2528 + __ bind(*op->stub()->continuation());
1.2529 + __ verify_oop(op->obj()->as_register());
1.2530 +}
1.2531 +
1.2532 +
1.2533 +void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1.2534 + assert(op->tmp1()->as_register() == G1 &&
1.2535 + op->tmp2()->as_register() == G3 &&
1.2536 + op->tmp3()->as_register() == G4 &&
1.2537 + op->tmp4()->as_register() == O1 &&
1.2538 + op->klass()->as_register() == G5, "must be");
1.2539 +
1.2540 + LP64_ONLY( __ signx(op->len()->as_register()); )
1.2541 + if (UseSlowPath ||
1.2542 + (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1.2543 + (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1.2544 + __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
1.2545 + __ delayed()->nop();
1.2546 + } else {
1.2547 + __ allocate_array(op->obj()->as_register(),
1.2548 + op->len()->as_register(),
1.2549 + op->tmp1()->as_register(),
1.2550 + op->tmp2()->as_register(),
1.2551 + op->tmp3()->as_register(),
1.2552 + arrayOopDesc::header_size(op->type()),
1.2553 + type2aelembytes(op->type()),
1.2554 + op->klass()->as_register(),
1.2555 + *op->stub()->entry());
1.2556 + }
1.2557 + __ bind(*op->stub()->continuation());
1.2558 +}
1.2559 +
1.2560 +
1.2561 +void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
1.2562 + ciMethodData *md, ciProfileData *data,
1.2563 + Register recv, Register tmp1, Label* update_done) {
1.2564 + uint i;
1.2565 + for (i = 0; i < VirtualCallData::row_limit(); i++) {
1.2566 + Label next_test;
1.2567 + // See if the receiver is receiver[n].
1.2568 + Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
1.2569 + mdo_offset_bias);
1.2570 + __ ld_ptr(receiver_addr, tmp1);
1.2571 + __ verify_klass_ptr(tmp1);
1.2572 + __ cmp_and_brx_short(recv, tmp1, Assembler::notEqual, Assembler::pt, next_test);
1.2573 + Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
1.2574 + mdo_offset_bias);
1.2575 + __ ld_ptr(data_addr, tmp1);
1.2576 + __ add(tmp1, DataLayout::counter_increment, tmp1);
1.2577 + __ st_ptr(tmp1, data_addr);
1.2578 + __ ba(*update_done);
1.2579 + __ delayed()->nop();
1.2580 + __ bind(next_test);
1.2581 + }
1.2582 +
1.2583 + // Didn't find receiver; find next empty slot and fill it in
1.2584 + for (i = 0; i < VirtualCallData::row_limit(); i++) {
1.2585 + Label next_test;
1.2586 + Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
1.2587 + mdo_offset_bias);
1.2588 + __ ld_ptr(recv_addr, tmp1);
1.2589 + __ br_notnull_short(tmp1, Assembler::pt, next_test);
1.2590 + __ st_ptr(recv, recv_addr);
1.2591 + __ set(DataLayout::counter_increment, tmp1);
1.2592 + __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
1.2593 + mdo_offset_bias);
1.2594 + __ ba(*update_done);
1.2595 + __ delayed()->nop();
1.2596 + __ bind(next_test);
1.2597 + }
1.2598 +}
1.2599 +
1.2600 +
1.2601 +void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
1.2602 + ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
1.2603 + md = method->method_data_or_null();
1.2604 + assert(md != NULL, "Sanity");
1.2605 + data = md->bci_to_data(bci);
1.2606 + assert(data != NULL, "need data for checkcast");
1.2607 + assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1.2608 + if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
1.2609 + // The offset is large so bias the mdo by the base of the slot so
1.2610 + // that the ld can use simm13s to reference the slots of the data
1.2611 + mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
1.2612 + }
1.2613 +}
1.2614 +
1.2615 +void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1.2616 + // we always need a stub for the failure case.
1.2617 + CodeStub* stub = op->stub();
1.2618 + Register obj = op->object()->as_register();
1.2619 + Register k_RInfo = op->tmp1()->as_register();
1.2620 + Register klass_RInfo = op->tmp2()->as_register();
1.2621 + Register dst = op->result_opr()->as_register();
1.2622 + Register Rtmp1 = op->tmp3()->as_register();
1.2623 + ciKlass* k = op->klass();
1.2624 +
1.2625 +
1.2626 + if (obj == k_RInfo) {
1.2627 + k_RInfo = klass_RInfo;
1.2628 + klass_RInfo = obj;
1.2629 + }
1.2630 +
1.2631 + ciMethodData* md;
1.2632 + ciProfileData* data;
1.2633 + int mdo_offset_bias = 0;
1.2634 + if (op->should_profile()) {
1.2635 + ciMethod* method = op->profiled_method();
1.2636 + assert(method != NULL, "Should have method");
1.2637 + setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
1.2638 +
1.2639 + Label not_null;
1.2640 + __ br_notnull_short(obj, Assembler::pn, not_null);
1.2641 + Register mdo = k_RInfo;
1.2642 + Register data_val = Rtmp1;
1.2643 + metadata2reg(md->constant_encoding(), mdo);
1.2644 + if (mdo_offset_bias > 0) {
1.2645 + __ set(mdo_offset_bias, data_val);
1.2646 + __ add(mdo, data_val, mdo);
1.2647 + }
1.2648 + Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
1.2649 + __ ldub(flags_addr, data_val);
1.2650 + __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
1.2651 + __ stb(data_val, flags_addr);
1.2652 + __ ba(*obj_is_null);
1.2653 + __ delayed()->nop();
1.2654 + __ bind(not_null);
1.2655 + } else {
1.2656 + __ br_null(obj, false, Assembler::pn, *obj_is_null);
1.2657 + __ delayed()->nop();
1.2658 + }
1.2659 +
1.2660 + Label profile_cast_failure, profile_cast_success;
1.2661 + Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1.2662 + Label *success_target = op->should_profile() ? &profile_cast_success : success;
1.2663 +
1.2664 + // patching may screw with our temporaries on sparc,
1.2665 + // so let's do it before loading the class
1.2666 + if (k->is_loaded()) {
1.2667 + metadata2reg(k->constant_encoding(), k_RInfo);
1.2668 + } else {
1.2669 + klass2reg_with_patching(k_RInfo, op->info_for_patch());
1.2670 + }
1.2671 + assert(obj != k_RInfo, "must be different");
1.2672 +
1.2673 + // get object class
1.2674 + // not a safepoint as obj null check happens earlier
1.2675 + __ load_klass(obj, klass_RInfo);
1.2676 + if (op->fast_check()) {
1.2677 + assert_different_registers(klass_RInfo, k_RInfo);
1.2678 + __ cmp(k_RInfo, klass_RInfo);
1.2679 + __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target);
1.2680 + __ delayed()->nop();
1.2681 + } else {
1.2682 + bool need_slow_path = true;
1.2683 + if (k->is_loaded()) {
1.2684 + if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset()))
1.2685 + need_slow_path = false;
1.2686 + // perform the fast part of the checking logic
1.2687 + __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
1.2688 + (need_slow_path ? success_target : NULL),
1.2689 + failure_target, NULL,
1.2690 + RegisterOrConstant(k->super_check_offset()));
1.2691 + } else {
1.2692 + // perform the fast part of the checking logic
1.2693 + __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target,
1.2694 + failure_target, NULL);
1.2695 + }
1.2696 + if (need_slow_path) {
1.2697 + // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1.2698 + assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
1.2699 + __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1.2700 + __ delayed()->nop();
1.2701 + __ cmp(G3, 0);
1.2702 + __ br(Assembler::equal, false, Assembler::pn, *failure_target);
1.2703 + __ delayed()->nop();
1.2704 + // Fall through to success case
1.2705 + }
1.2706 + }
1.2707 +
1.2708 + if (op->should_profile()) {
1.2709 + Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
1.2710 + assert_different_registers(obj, mdo, recv, tmp1);
1.2711 + __ bind(profile_cast_success);
1.2712 + metadata2reg(md->constant_encoding(), mdo);
1.2713 + if (mdo_offset_bias > 0) {
1.2714 + __ set(mdo_offset_bias, tmp1);
1.2715 + __ add(mdo, tmp1, mdo);
1.2716 + }
1.2717 + __ load_klass(obj, recv);
1.2718 + type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
1.2719 + // Jump over the failure case
1.2720 + __ ba(*success);
1.2721 + __ delayed()->nop();
1.2722 + // Cast failure case
1.2723 + __ bind(profile_cast_failure);
1.2724 + metadata2reg(md->constant_encoding(), mdo);
1.2725 + if (mdo_offset_bias > 0) {
1.2726 + __ set(mdo_offset_bias, tmp1);
1.2727 + __ add(mdo, tmp1, mdo);
1.2728 + }
1.2729 + Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
1.2730 + __ ld_ptr(data_addr, tmp1);
1.2731 + __ sub(tmp1, DataLayout::counter_increment, tmp1);
1.2732 + __ st_ptr(tmp1, data_addr);
1.2733 + __ ba(*failure);
1.2734 + __ delayed()->nop();
1.2735 + }
1.2736 + __ ba(*success);
1.2737 + __ delayed()->nop();
1.2738 +}
1.2739 +
1.2740 +void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1.2741 + LIR_Code code = op->code();
1.2742 + if (code == lir_store_check) {
1.2743 + Register value = op->object()->as_register();
1.2744 + Register array = op->array()->as_register();
1.2745 + Register k_RInfo = op->tmp1()->as_register();
1.2746 + Register klass_RInfo = op->tmp2()->as_register();
1.2747 + Register Rtmp1 = op->tmp3()->as_register();
1.2748 +
1.2749 + __ verify_oop(value);
1.2750 + CodeStub* stub = op->stub();
1.2751 + // check if it needs to be profiled
1.2752 + ciMethodData* md;
1.2753 + ciProfileData* data;
1.2754 + int mdo_offset_bias = 0;
1.2755 + if (op->should_profile()) {
1.2756 + ciMethod* method = op->profiled_method();
1.2757 + assert(method != NULL, "Should have method");
1.2758 + setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
1.2759 + }
1.2760 + Label profile_cast_success, profile_cast_failure, done;
1.2761 + Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1.2762 + Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1.2763 +
1.2764 + if (op->should_profile()) {
1.2765 + Label not_null;
1.2766 + __ br_notnull_short(value, Assembler::pn, not_null);
1.2767 + Register mdo = k_RInfo;
1.2768 + Register data_val = Rtmp1;
1.2769 + metadata2reg(md->constant_encoding(), mdo);
1.2770 + if (mdo_offset_bias > 0) {
1.2771 + __ set(mdo_offset_bias, data_val);
1.2772 + __ add(mdo, data_val, mdo);
1.2773 + }
1.2774 + Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
1.2775 + __ ldub(flags_addr, data_val);
1.2776 + __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
1.2777 + __ stb(data_val, flags_addr);
1.2778 + __ ba_short(done);
1.2779 + __ bind(not_null);
1.2780 + } else {
1.2781 + __ br_null_short(value, Assembler::pn, done);
1.2782 + }
1.2783 + add_debug_info_for_null_check_here(op->info_for_exception());
1.2784 + __ load_klass(array, k_RInfo);
1.2785 + __ load_klass(value, klass_RInfo);
1.2786 +
1.2787 + // get instance klass
1.2788 + __ ld_ptr(Address(k_RInfo, ObjArrayKlass::element_klass_offset()), k_RInfo);
1.2789 + // perform the fast part of the checking logic
1.2790 + __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL);
1.2791 +
1.2792 + // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1.2793 + assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
1.2794 + __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1.2795 + __ delayed()->nop();
1.2796 + __ cmp(G3, 0);
1.2797 + __ br(Assembler::equal, false, Assembler::pn, *failure_target);
1.2798 + __ delayed()->nop();
1.2799 + // fall through to the success case
1.2800 +
1.2801 + if (op->should_profile()) {
1.2802 + Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
1.2803 + assert_different_registers(value, mdo, recv, tmp1);
1.2804 + __ bind(profile_cast_success);
1.2805 + metadata2reg(md->constant_encoding(), mdo);
1.2806 + if (mdo_offset_bias > 0) {
1.2807 + __ set(mdo_offset_bias, tmp1);
1.2808 + __ add(mdo, tmp1, mdo);
1.2809 + }
1.2810 + __ load_klass(value, recv);
1.2811 + type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
1.2812 + __ ba_short(done);
1.2813 + // Cast failure case
1.2814 + __ bind(profile_cast_failure);
1.2815 + metadata2reg(md->constant_encoding(), mdo);
1.2816 + if (mdo_offset_bias > 0) {
1.2817 + __ set(mdo_offset_bias, tmp1);
1.2818 + __ add(mdo, tmp1, mdo);
1.2819 + }
1.2820 + Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
1.2821 + __ ld_ptr(data_addr, tmp1);
1.2822 + __ sub(tmp1, DataLayout::counter_increment, tmp1);
1.2823 + __ st_ptr(tmp1, data_addr);
1.2824 + __ ba(*stub->entry());
1.2825 + __ delayed()->nop();
1.2826 + }
1.2827 + __ bind(done);
1.2828 + } else if (code == lir_checkcast) {
1.2829 + Register obj = op->object()->as_register();
1.2830 + Register dst = op->result_opr()->as_register();
1.2831 + Label success;
1.2832 + emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1.2833 + __ bind(success);
1.2834 + __ mov(obj, dst);
1.2835 + } else if (code == lir_instanceof) {
1.2836 + Register obj = op->object()->as_register();
1.2837 + Register dst = op->result_opr()->as_register();
1.2838 + Label success, failure, done;
1.2839 + emit_typecheck_helper(op, &success, &failure, &failure);
1.2840 + __ bind(failure);
1.2841 + __ set(0, dst);
1.2842 + __ ba_short(done);
1.2843 + __ bind(success);
1.2844 + __ set(1, dst);
1.2845 + __ bind(done);
1.2846 + } else {
1.2847 + ShouldNotReachHere();
1.2848 + }
1.2849 +
1.2850 +}
1.2851 +
1.2852 +
1.2853 +void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1.2854 + if (op->code() == lir_cas_long) {
1.2855 + assert(VM_Version::supports_cx8(), "wrong machine");
1.2856 + Register addr = op->addr()->as_pointer_register();
1.2857 + Register cmp_value_lo = op->cmp_value()->as_register_lo();
1.2858 + Register cmp_value_hi = op->cmp_value()->as_register_hi();
1.2859 + Register new_value_lo = op->new_value()->as_register_lo();
1.2860 + Register new_value_hi = op->new_value()->as_register_hi();
1.2861 + Register t1 = op->tmp1()->as_register();
1.2862 + Register t2 = op->tmp2()->as_register();
1.2863 +#ifdef _LP64
1.2864 + __ mov(cmp_value_lo, t1);
1.2865 + __ mov(new_value_lo, t2);
1.2866 + // perform the compare and swap operation
1.2867 + __ casx(addr, t1, t2);
1.2868 + // generate condition code - if the swap succeeded, t2 ("new value" reg) was
1.2869 + // overwritten with the original value in "addr" and will be equal to t1.
1.2870 + __ cmp(t1, t2);
1.2871 +#else
1.2872 + // move high and low halves of long values into single registers
1.2873 + __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg
1.2874 + __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half
1.2875 + __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value
1.2876 + __ sllx(new_value_hi, 32, t2);
1.2877 + __ srl(new_value_lo, 0, new_value_lo);
1.2878 + __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap
1.2879 + // perform the compare and swap operation
1.2880 + __ casx(addr, t1, t2);
1.2881 + // generate condition code - if the swap succeeded, t2 ("new value" reg) was
1.2882 + // overwritten with the original value in "addr" and will be equal to t1.
1.2883 + // Produce icc flag for 32bit.
1.2884 + __ sub(t1, t2, t2);
1.2885 + __ srlx(t2, 32, t1);
1.2886 + __ orcc(t2, t1, G0);
1.2887 +#endif
1.2888 + } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
1.2889 + Register addr = op->addr()->as_pointer_register();
1.2890 + Register cmp_value = op->cmp_value()->as_register();
1.2891 + Register new_value = op->new_value()->as_register();
1.2892 + Register t1 = op->tmp1()->as_register();
1.2893 + Register t2 = op->tmp2()->as_register();
1.2894 + __ mov(cmp_value, t1);
1.2895 + __ mov(new_value, t2);
1.2896 + if (op->code() == lir_cas_obj) {
1.2897 + if (UseCompressedOops) {
1.2898 + __ encode_heap_oop(t1);
1.2899 + __ encode_heap_oop(t2);
1.2900 + __ cas(addr, t1, t2);
1.2901 + } else {
1.2902 + __ cas_ptr(addr, t1, t2);
1.2903 + }
1.2904 + } else {
1.2905 + __ cas(addr, t1, t2);
1.2906 + }
1.2907 + __ cmp(t1, t2);
1.2908 + } else {
1.2909 + Unimplemented();
1.2910 + }
1.2911 +}
1.2912 +
1.2913 +void LIR_Assembler::set_24bit_FPU() {
1.2914 + Unimplemented();
1.2915 +}
1.2916 +
1.2917 +
1.2918 +void LIR_Assembler::reset_FPU() {
1.2919 + Unimplemented();
1.2920 +}
1.2921 +
1.2922 +
1.2923 +void LIR_Assembler::breakpoint() {
1.2924 + __ breakpoint_trap();
1.2925 +}
1.2926 +
1.2927 +
1.2928 +void LIR_Assembler::push(LIR_Opr opr) {
1.2929 + Unimplemented();
1.2930 +}
1.2931 +
1.2932 +
1.2933 +void LIR_Assembler::pop(LIR_Opr opr) {
1.2934 + Unimplemented();
1.2935 +}
1.2936 +
1.2937 +
1.2938 +void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
1.2939 + Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
1.2940 + Register dst = dst_opr->as_register();
1.2941 + Register reg = mon_addr.base();
1.2942 + int offset = mon_addr.disp();
1.2943 + // compute pointer to BasicLock
1.2944 + if (mon_addr.is_simm13()) {
1.2945 + __ add(reg, offset, dst);
1.2946 + } else {
1.2947 + __ set(offset, dst);
1.2948 + __ add(dst, reg, dst);
1.2949 + }
1.2950 +}
1.2951 +
1.2952 +void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
1.2953 + fatal("CRC32 intrinsic is not implemented on this platform");
1.2954 +}
1.2955 +
1.2956 +void LIR_Assembler::emit_lock(LIR_OpLock* op) {
1.2957 + Register obj = op->obj_opr()->as_register();
1.2958 + Register hdr = op->hdr_opr()->as_register();
1.2959 + Register lock = op->lock_opr()->as_register();
1.2960 +
1.2961 + // obj may not be an oop
1.2962 + if (op->code() == lir_lock) {
1.2963 + MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
1.2964 + if (UseFastLocking) {
1.2965 + assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
1.2966 + // add debug info for NullPointerException only if one is possible
1.2967 + if (op->info() != NULL) {
1.2968 + add_debug_info_for_null_check_here(op->info());
1.2969 + }
1.2970 + __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
1.2971 + } else {
1.2972 + // always do slow locking
1.2973 + // note: the slow locking code could be inlined here, however if we use
1.2974 + // slow locking, speed doesn't matter anyway and this solution is
1.2975 + // simpler and requires less duplicated code - additionally, the
1.2976 + // slow locking code is the same in either case which simplifies
1.2977 + // debugging
1.2978 + __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
1.2979 + __ delayed()->nop();
1.2980 + }
1.2981 + } else {
1.2982 + assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
1.2983 + if (UseFastLocking) {
1.2984 + assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
1.2985 + __ unlock_object(hdr, obj, lock, *op->stub()->entry());
1.2986 + } else {
1.2987 + // always do slow unlocking
1.2988 + // note: the slow unlocking code could be inlined here, however if we use
1.2989 + // slow unlocking, speed doesn't matter anyway and this solution is
1.2990 + // simpler and requires less duplicated code - additionally, the
1.2991 + // slow unlocking code is the same in either case which simplifies
1.2992 + // debugging
1.2993 + __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
1.2994 + __ delayed()->nop();
1.2995 + }
1.2996 + }
1.2997 + __ bind(*op->stub()->continuation());
1.2998 +}
1.2999 +
1.3000 +
1.3001 +void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
1.3002 + ciMethod* method = op->profiled_method();
1.3003 + int bci = op->profiled_bci();
1.3004 + ciMethod* callee = op->profiled_callee();
1.3005 +
1.3006 + // Update counter for all call types
1.3007 + ciMethodData* md = method->method_data_or_null();
1.3008 + assert(md != NULL, "Sanity");
1.3009 + ciProfileData* data = md->bci_to_data(bci);
1.3010 + assert(data->is_CounterData(), "need CounterData for calls");
1.3011 + assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
1.3012 + Register mdo = op->mdo()->as_register();
1.3013 +#ifdef _LP64
1.3014 + assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
1.3015 + Register tmp1 = op->tmp1()->as_register_lo();
1.3016 +#else
1.3017 + assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
1.3018 + Register tmp1 = op->tmp1()->as_register();
1.3019 +#endif
1.3020 + metadata2reg(md->constant_encoding(), mdo);
1.3021 + int mdo_offset_bias = 0;
1.3022 + if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
1.3023 + data->size_in_bytes())) {
1.3024 + // The offset is large so bias the mdo by the base of the slot so
1.3025 + // that the ld can use simm13s to reference the slots of the data
1.3026 + mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
1.3027 + __ set(mdo_offset_bias, O7);
1.3028 + __ add(mdo, O7, mdo);
1.3029 + }
1.3030 +
1.3031 + Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
1.3032 + Bytecodes::Code bc = method->java_code_at_bci(bci);
1.3033 + const bool callee_is_static = callee->is_loaded() && callee->is_static();
1.3034 + // Perform additional virtual call profiling for invokevirtual and
1.3035 + // invokeinterface bytecodes
1.3036 + if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
1.3037 + !callee_is_static && // required for optimized MH invokes
1.3038 + C1ProfileVirtualCalls) {
1.3039 + assert(op->recv()->is_single_cpu(), "recv must be allocated");
1.3040 + Register recv = op->recv()->as_register();
1.3041 + assert_different_registers(mdo, tmp1, recv);
1.3042 + assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
1.3043 + ciKlass* known_klass = op->known_holder();
1.3044 + if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
1.3045 + // We know the type that will be seen at this call site; we can
1.3046 + // statically update the MethodData* rather than needing to do
1.3047 + // dynamic tests on the receiver type
1.3048 +
1.3049 + // NOTE: we should probably put a lock around this search to
1.3050 + // avoid collisions by concurrent compilations
1.3051 + ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
1.3052 + uint i;
1.3053 + for (i = 0; i < VirtualCallData::row_limit(); i++) {
1.3054 + ciKlass* receiver = vc_data->receiver(i);
1.3055 + if (known_klass->equals(receiver)) {
1.3056 + Address data_addr(mdo, md->byte_offset_of_slot(data,
1.3057 + VirtualCallData::receiver_count_offset(i)) -
1.3058 + mdo_offset_bias);
1.3059 + __ ld_ptr(data_addr, tmp1);
1.3060 + __ add(tmp1, DataLayout::counter_increment, tmp1);
1.3061 + __ st_ptr(tmp1, data_addr);
1.3062 + return;
1.3063 + }
1.3064 + }
1.3065 +
1.3066 + // Receiver type not found in profile data; select an empty slot
1.3067 +
1.3068 + // Note that this is less efficient than it should be because it
1.3069 + // always does a write to the receiver part of the
1.3070 + // VirtualCallData rather than just the first time
1.3071 + for (i = 0; i < VirtualCallData::row_limit(); i++) {
1.3072 + ciKlass* receiver = vc_data->receiver(i);
1.3073 + if (receiver == NULL) {
1.3074 + Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
1.3075 + mdo_offset_bias);
1.3076 + metadata2reg(known_klass->constant_encoding(), tmp1);
1.3077 + __ st_ptr(tmp1, recv_addr);
1.3078 + Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
1.3079 + mdo_offset_bias);
1.3080 + __ ld_ptr(data_addr, tmp1);
1.3081 + __ add(tmp1, DataLayout::counter_increment, tmp1);
1.3082 + __ st_ptr(tmp1, data_addr);
1.3083 + return;
1.3084 + }
1.3085 + }
1.3086 + } else {
1.3087 + __ load_klass(recv, recv);
1.3088 + Label update_done;
1.3089 + type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
1.3090 + // Receiver did not match any saved receiver and there is no empty row for it.
1.3091 + // Increment total counter to indicate polymorphic case.
1.3092 + __ ld_ptr(counter_addr, tmp1);
1.3093 + __ add(tmp1, DataLayout::counter_increment, tmp1);
1.3094 + __ st_ptr(tmp1, counter_addr);
1.3095 +
1.3096 + __ bind(update_done);
1.3097 + }
1.3098 + } else {
1.3099 + // Static call
1.3100 + __ ld_ptr(counter_addr, tmp1);
1.3101 + __ add(tmp1, DataLayout::counter_increment, tmp1);
1.3102 + __ st_ptr(tmp1, counter_addr);
1.3103 + }
1.3104 +}
1.3105 +
1.3106 +void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
1.3107 + Register obj = op->obj()->as_register();
1.3108 + Register tmp1 = op->tmp()->as_pointer_register();
1.3109 + Register tmp2 = G1;
1.3110 + Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
1.3111 + ciKlass* exact_klass = op->exact_klass();
1.3112 + intptr_t current_klass = op->current_klass();
1.3113 + bool not_null = op->not_null();
1.3114 + bool no_conflict = op->no_conflict();
1.3115 +
1.3116 + Label update, next, none;
1.3117 +
1.3118 + bool do_null = !not_null;
1.3119 + bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
1.3120 + bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
1.3121 +
1.3122 + assert(do_null || do_update, "why are we here?");
1.3123 + assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
1.3124 +
1.3125 + __ verify_oop(obj);
1.3126 +
1.3127 + if (tmp1 != obj) {
1.3128 + __ mov(obj, tmp1);
1.3129 + }
1.3130 + if (do_null) {
1.3131 + __ br_notnull_short(tmp1, Assembler::pt, update);
1.3132 + if (!TypeEntries::was_null_seen(current_klass)) {
1.3133 + __ ld_ptr(mdo_addr, tmp1);
1.3134 + __ or3(tmp1, TypeEntries::null_seen, tmp1);
1.3135 + __ st_ptr(tmp1, mdo_addr);
1.3136 + }
1.3137 + if (do_update) {
1.3138 + __ ba(next);
1.3139 + __ delayed()->nop();
1.3140 + }
1.3141 +#ifdef ASSERT
1.3142 + } else {
1.3143 + __ br_notnull_short(tmp1, Assembler::pt, update);
1.3144 + __ stop("unexpect null obj");
1.3145 +#endif
1.3146 + }
1.3147 +
1.3148 + __ bind(update);
1.3149 +
1.3150 + if (do_update) {
1.3151 +#ifdef ASSERT
1.3152 + if (exact_klass != NULL) {
1.3153 + Label ok;
1.3154 + __ load_klass(tmp1, tmp1);
1.3155 + metadata2reg(exact_klass->constant_encoding(), tmp2);
1.3156 + __ cmp_and_br_short(tmp1, tmp2, Assembler::equal, Assembler::pt, ok);
1.3157 + __ stop("exact klass and actual klass differ");
1.3158 + __ bind(ok);
1.3159 + }
1.3160 +#endif
1.3161 +
1.3162 + Label do_update;
1.3163 + __ ld_ptr(mdo_addr, tmp2);
1.3164 +
1.3165 + if (!no_conflict) {
1.3166 + if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
1.3167 + if (exact_klass != NULL) {
1.3168 + metadata2reg(exact_klass->constant_encoding(), tmp1);
1.3169 + } else {
1.3170 + __ load_klass(tmp1, tmp1);
1.3171 + }
1.3172 +
1.3173 + __ xor3(tmp1, tmp2, tmp1);
1.3174 + __ btst(TypeEntries::type_klass_mask, tmp1);
1.3175 + // klass seen before, nothing to do. The unknown bit may have been
1.3176 + // set already but no need to check.
1.3177 + __ brx(Assembler::zero, false, Assembler::pt, next);
1.3178 + __ delayed()->
1.3179 +
1.3180 + btst(TypeEntries::type_unknown, tmp1);
1.3181 + // already unknown. Nothing to do anymore.
1.3182 + __ brx(Assembler::notZero, false, Assembler::pt, next);
1.3183 +
1.3184 + if (TypeEntries::is_type_none(current_klass)) {
1.3185 + __ delayed()->btst(TypeEntries::type_mask, tmp2);
1.3186 + __ brx(Assembler::zero, true, Assembler::pt, do_update);
1.3187 + // first time here. Set profile type.
1.3188 + __ delayed()->or3(tmp2, tmp1, tmp2);
1.3189 + } else {
1.3190 + __ delayed()->nop();
1.3191 + }
1.3192 + } else {
1.3193 + assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
1.3194 + ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
1.3195 +
1.3196 + __ btst(TypeEntries::type_unknown, tmp2);
1.3197 + // already unknown. Nothing to do anymore.
1.3198 + __ brx(Assembler::notZero, false, Assembler::pt, next);
1.3199 + __ delayed()->nop();
1.3200 + }
1.3201 +
1.3202 + // different than before. Cannot keep accurate profile.
1.3203 + __ or3(tmp2, TypeEntries::type_unknown, tmp2);
1.3204 + } else {
1.3205 + // There's a single possible klass at this profile point
1.3206 + assert(exact_klass != NULL, "should be");
1.3207 + if (TypeEntries::is_type_none(current_klass)) {
1.3208 + metadata2reg(exact_klass->constant_encoding(), tmp1);
1.3209 + __ xor3(tmp1, tmp2, tmp1);
1.3210 + __ btst(TypeEntries::type_klass_mask, tmp1);
1.3211 + __ brx(Assembler::zero, false, Assembler::pt, next);
1.3212 +#ifdef ASSERT
1.3213 +
1.3214 + {
1.3215 + Label ok;
1.3216 + __ delayed()->btst(TypeEntries::type_mask, tmp2);
1.3217 + __ brx(Assembler::zero, true, Assembler::pt, ok);
1.3218 + __ delayed()->nop();
1.3219 +
1.3220 + __ stop("unexpected profiling mismatch");
1.3221 + __ bind(ok);
1.3222 + }
1.3223 + // first time here. Set profile type.
1.3224 + __ or3(tmp2, tmp1, tmp2);
1.3225 +#else
1.3226 + // first time here. Set profile type.
1.3227 + __ delayed()->or3(tmp2, tmp1, tmp2);
1.3228 +#endif
1.3229 +
1.3230 + } else {
1.3231 + assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
1.3232 + ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
1.3233 +
1.3234 + // already unknown. Nothing to do anymore.
1.3235 + __ btst(TypeEntries::type_unknown, tmp2);
1.3236 + __ brx(Assembler::notZero, false, Assembler::pt, next);
1.3237 + __ delayed()->or3(tmp2, TypeEntries::type_unknown, tmp2);
1.3238 + }
1.3239 + }
1.3240 +
1.3241 + __ bind(do_update);
1.3242 + __ st_ptr(tmp2, mdo_addr);
1.3243 +
1.3244 + __ bind(next);
1.3245 + }
1.3246 +}
1.3247 +
1.3248 +void LIR_Assembler::align_backward_branch_target() {
1.3249 + __ align(OptoLoopAlignment);
1.3250 +}
1.3251 +
1.3252 +
1.3253 +void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
1.3254 + // make sure we are expecting a delay
1.3255 + // this has the side effect of clearing the delay state
1.3256 + // so we can use _masm instead of _masm->delayed() to do the
1.3257 + // code generation.
1.3258 + __ delayed();
1.3259 +
1.3260 + // make sure we only emit one instruction
1.3261 + int offset = code_offset();
1.3262 + op->delay_op()->emit_code(this);
1.3263 +#ifdef ASSERT
1.3264 + if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
1.3265 + op->delay_op()->print();
1.3266 + }
1.3267 + assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
1.3268 + "only one instruction can go in a delay slot");
1.3269 +#endif
1.3270 +
1.3271 + // we may also be emitting the call info for the instruction
1.3272 + // which we are the delay slot of.
1.3273 + CodeEmitInfo* call_info = op->call_info();
1.3274 + if (call_info) {
1.3275 + add_call_info(code_offset(), call_info);
1.3276 + }
1.3277 +
1.3278 + if (VerifyStackAtCalls) {
1.3279 + _masm->sub(FP, SP, O7);
1.3280 + _masm->cmp(O7, initial_frame_size_in_bytes());
1.3281 + _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
1.3282 + }
1.3283 +}
1.3284 +
1.3285 +
1.3286 +void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
1.3287 + assert(left->is_register(), "can only handle registers");
1.3288 +
1.3289 + if (left->is_single_cpu()) {
1.3290 + __ neg(left->as_register(), dest->as_register());
1.3291 + } else if (left->is_single_fpu()) {
1.3292 + __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
1.3293 + } else if (left->is_double_fpu()) {
1.3294 + __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
1.3295 + } else {
1.3296 + assert (left->is_double_cpu(), "Must be a long");
1.3297 + Register Rlow = left->as_register_lo();
1.3298 + Register Rhi = left->as_register_hi();
1.3299 +#ifdef _LP64
1.3300 + __ sub(G0, Rlow, dest->as_register_lo());
1.3301 +#else
1.3302 + __ subcc(G0, Rlow, dest->as_register_lo());
1.3303 + __ subc (G0, Rhi, dest->as_register_hi());
1.3304 +#endif
1.3305 + }
1.3306 +}
1.3307 +
1.3308 +
1.3309 +void LIR_Assembler::fxch(int i) {
1.3310 + Unimplemented();
1.3311 +}
1.3312 +
1.3313 +void LIR_Assembler::fld(int i) {
1.3314 + Unimplemented();
1.3315 +}
1.3316 +
1.3317 +void LIR_Assembler::ffree(int i) {
1.3318 + Unimplemented();
1.3319 +}
1.3320 +
1.3321 +void LIR_Assembler::rt_call(LIR_Opr result, address dest,
1.3322 + const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
1.3323 +
1.3324 + // if tmp is invalid, then the function being called doesn't destroy the thread
1.3325 + if (tmp->is_valid()) {
1.3326 + __ save_thread(tmp->as_register());
1.3327 + }
1.3328 + __ call(dest, relocInfo::runtime_call_type);
1.3329 + __ delayed()->nop();
1.3330 + if (info != NULL) {
1.3331 + add_call_info_here(info);
1.3332 + }
1.3333 + if (tmp->is_valid()) {
1.3334 + __ restore_thread(tmp->as_register());
1.3335 + }
1.3336 +
1.3337 +#ifdef ASSERT
1.3338 + __ verify_thread();
1.3339 +#endif // ASSERT
1.3340 +}
1.3341 +
1.3342 +
1.3343 +void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
1.3344 +#ifdef _LP64
1.3345 + ShouldNotReachHere();
1.3346 +#endif
1.3347 +
1.3348 + NEEDS_CLEANUP;
1.3349 + if (type == T_LONG) {
1.3350 + LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
1.3351 +
1.3352 + // (extended to allow indexed as well as constant displaced for JSR-166)
1.3353 + Register idx = noreg; // contains either constant offset or index
1.3354 +
1.3355 + int disp = mem_addr->disp();
1.3356 + if (mem_addr->index() == LIR_OprFact::illegalOpr) {
1.3357 + if (!Assembler::is_simm13(disp)) {
1.3358 + idx = O7;
1.3359 + __ set(disp, idx);
1.3360 + }
1.3361 + } else {
1.3362 + assert(disp == 0, "not both indexed and disp");
1.3363 + idx = mem_addr->index()->as_register();
1.3364 + }
1.3365 +
1.3366 + int null_check_offset = -1;
1.3367 +
1.3368 + Register base = mem_addr->base()->as_register();
1.3369 + if (src->is_register() && dest->is_address()) {
1.3370 + // G4 is high half, G5 is low half
1.3371 + // clear the top bits of G5, and scale up G4
1.3372 + __ srl (src->as_register_lo(), 0, G5);
1.3373 + __ sllx(src->as_register_hi(), 32, G4);
1.3374 + // combine the two halves into the 64 bits of G4
1.3375 + __ or3(G4, G5, G4);
1.3376 + null_check_offset = __ offset();
1.3377 + if (idx == noreg) {
1.3378 + __ stx(G4, base, disp);
1.3379 + } else {
1.3380 + __ stx(G4, base, idx);
1.3381 + }
1.3382 + } else if (src->is_address() && dest->is_register()) {
1.3383 + null_check_offset = __ offset();
1.3384 + if (idx == noreg) {
1.3385 + __ ldx(base, disp, G5);
1.3386 + } else {
1.3387 + __ ldx(base, idx, G5);
1.3388 + }
1.3389 + __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
1.3390 + __ mov (G5, dest->as_register_lo()); // copy low half into lo
1.3391 + } else {
1.3392 + Unimplemented();
1.3393 + }
1.3394 + if (info != NULL) {
1.3395 + add_debug_info_for_null_check(null_check_offset, info);
1.3396 + }
1.3397 +
1.3398 + } else {
1.3399 + // use normal move for all other volatiles since they don't need
1.3400 + // special handling to remain atomic.
1.3401 + move_op(src, dest, type, lir_patch_none, info, false, false, false);
1.3402 + }
1.3403 +}
1.3404 +
1.3405 +void LIR_Assembler::membar() {
1.3406 + // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
1.3407 + __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
1.3408 +}
1.3409 +
1.3410 +void LIR_Assembler::membar_acquire() {
1.3411 + // no-op on TSO
1.3412 +}
1.3413 +
1.3414 +void LIR_Assembler::membar_release() {
1.3415 + // no-op on TSO
1.3416 +}
1.3417 +
1.3418 +void LIR_Assembler::membar_loadload() {
1.3419 + // no-op
1.3420 + //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
1.3421 +}
1.3422 +
1.3423 +void LIR_Assembler::membar_storestore() {
1.3424 + // no-op
1.3425 + //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
1.3426 +}
1.3427 +
1.3428 +void LIR_Assembler::membar_loadstore() {
1.3429 + // no-op
1.3430 + //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
1.3431 +}
1.3432 +
1.3433 +void LIR_Assembler::membar_storeload() {
1.3434 + __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
1.3435 +}
1.3436 +
1.3437 +
1.3438 +// Pack two sequential registers containing 32 bit values
1.3439 +// into a single 64 bit register.
1.3440 +// src and src->successor() are packed into dst
1.3441 +// src and dst may be the same register.
1.3442 +// Note: src is destroyed
1.3443 +void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
1.3444 + Register rs = src->as_register();
1.3445 + Register rd = dst->as_register_lo();
1.3446 + __ sllx(rs, 32, rs);
1.3447 + __ srl(rs->successor(), 0, rs->successor());
1.3448 + __ or3(rs, rs->successor(), rd);
1.3449 +}
1.3450 +
1.3451 +// Unpack a 64 bit value in a register into
1.3452 +// two sequential registers.
1.3453 +// src is unpacked into dst and dst->successor()
1.3454 +void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
1.3455 + Register rs = src->as_register_lo();
1.3456 + Register rd = dst->as_register_hi();
1.3457 + assert_different_registers(rs, rd, rd->successor());
1.3458 + __ srlx(rs, 32, rd);
1.3459 + __ srl (rs, 0, rd->successor());
1.3460 +}
1.3461 +
1.3462 +
1.3463 +void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
1.3464 + LIR_Address* addr = addr_opr->as_address_ptr();
1.3465 + assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1, "can't handle complex addresses yet");
1.3466 +
1.3467 + if (Assembler::is_simm13(addr->disp())) {
1.3468 + __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register());
1.3469 + } else {
1.3470 + __ set(addr->disp(), G3_scratch);
1.3471 + __ add(addr->base()->as_pointer_register(), G3_scratch, dest->as_pointer_register());
1.3472 + }
1.3473 +}
1.3474 +
1.3475 +
1.3476 +void LIR_Assembler::get_thread(LIR_Opr result_reg) {
1.3477 + assert(result_reg->is_register(), "check");
1.3478 + __ mov(G2_thread, result_reg->as_register());
1.3479 +}
1.3480 +
1.3481 +#ifdef ASSERT
1.3482 +// emit run-time assertion
1.3483 +void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
1.3484 + assert(op->code() == lir_assert, "must be");
1.3485 +
1.3486 + if (op->in_opr1()->is_valid()) {
1.3487 + assert(op->in_opr2()->is_valid(), "both operands must be valid");
1.3488 + comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
1.3489 + } else {
1.3490 + assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
1.3491 + assert(op->condition() == lir_cond_always, "no other conditions allowed");
1.3492 + }
1.3493 +
1.3494 + Label ok;
1.3495 + if (op->condition() != lir_cond_always) {
1.3496 + Assembler::Condition acond;
1.3497 + switch (op->condition()) {
1.3498 + case lir_cond_equal: acond = Assembler::equal; break;
1.3499 + case lir_cond_notEqual: acond = Assembler::notEqual; break;
1.3500 + case lir_cond_less: acond = Assembler::less; break;
1.3501 + case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1.3502 + case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1.3503 + case lir_cond_greater: acond = Assembler::greater; break;
1.3504 + case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1.3505 + case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1.3506 + default: ShouldNotReachHere();
1.3507 + };
1.3508 + __ br(acond, false, Assembler::pt, ok);
1.3509 + __ delayed()->nop();
1.3510 + }
1.3511 + if (op->halt()) {
1.3512 + const char* str = __ code_string(op->msg());
1.3513 + __ stop(str);
1.3514 + } else {
1.3515 + breakpoint();
1.3516 + }
1.3517 + __ bind(ok);
1.3518 +}
1.3519 +#endif
1.3520 +
1.3521 +void LIR_Assembler::peephole(LIR_List* lir) {
1.3522 + LIR_OpList* inst = lir->instructions_list();
1.3523 + for (int i = 0; i < inst->length(); i++) {
1.3524 + LIR_Op* op = inst->at(i);
1.3525 + switch (op->code()) {
1.3526 + case lir_cond_float_branch:
1.3527 + case lir_branch: {
1.3528 + LIR_OpBranch* branch = op->as_OpBranch();
1.3529 + assert(branch->info() == NULL, "shouldn't be state on branches anymore");
1.3530 + LIR_Op* delay_op = NULL;
1.3531 + // we'd like to be able to pull following instructions into
1.3532 + // this slot but we don't know enough to do it safely yet so
1.3533 + // only optimize block to block control flow.
1.3534 + if (LIRFillDelaySlots && branch->block()) {
1.3535 + LIR_Op* prev = inst->at(i - 1);
1.3536 + if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
1.3537 + // swap previous instruction into delay slot
1.3538 + inst->at_put(i - 1, op);
1.3539 + inst->at_put(i, new LIR_OpDelay(prev, op->info()));
1.3540 +#ifndef PRODUCT
1.3541 + if (LIRTracePeephole) {
1.3542 + tty->print_cr("delayed");
1.3543 + inst->at(i - 1)->print();
1.3544 + inst->at(i)->print();
1.3545 + tty->cr();
1.3546 + }
1.3547 +#endif
1.3548 + continue;
1.3549 + }
1.3550 + }
1.3551 +
1.3552 + if (!delay_op) {
1.3553 + delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
1.3554 + }
1.3555 + inst->insert_before(i + 1, delay_op);
1.3556 + break;
1.3557 + }
1.3558 + case lir_static_call:
1.3559 + case lir_virtual_call:
1.3560 + case lir_icvirtual_call:
1.3561 + case lir_optvirtual_call:
1.3562 + case lir_dynamic_call: {
1.3563 + LIR_Op* prev = inst->at(i - 1);
1.3564 + if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
1.3565 + (op->code() != lir_virtual_call ||
1.3566 + !prev->result_opr()->is_single_cpu() ||
1.3567 + prev->result_opr()->as_register() != O0) &&
1.3568 + LIR_Assembler::is_single_instruction(prev)) {
1.3569 + // Only moves without info can be put into the delay slot.
1.3570 + // Also don't allow the setup of the receiver in the delay
1.3571 + // slot for vtable calls.
1.3572 + inst->at_put(i - 1, op);
1.3573 + inst->at_put(i, new LIR_OpDelay(prev, op->info()));
1.3574 +#ifndef PRODUCT
1.3575 + if (LIRTracePeephole) {
1.3576 + tty->print_cr("delayed");
1.3577 + inst->at(i - 1)->print();
1.3578 + inst->at(i)->print();
1.3579 + tty->cr();
1.3580 + }
1.3581 +#endif
1.3582 + } else {
1.3583 + LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
1.3584 + inst->insert_before(i + 1, delay_op);
1.3585 + i++;
1.3586 + }
1.3587 +
1.3588 +#if defined(TIERED) && !defined(_LP64)
1.3589 + // fixup the return value from G1 to O0/O1 for long returns.
1.3590 + // It's done here instead of in LIRGenerator because there's
1.3591 + // such a mismatch between the single reg and double reg
1.3592 + // calling convention.
1.3593 + LIR_OpJavaCall* callop = op->as_OpJavaCall();
1.3594 + if (callop->result_opr() == FrameMap::out_long_opr) {
1.3595 + LIR_OpJavaCall* call;
1.3596 + LIR_OprList* arguments = new LIR_OprList(callop->arguments()->length());
1.3597 + for (int a = 0; a < arguments->length(); a++) {
1.3598 + arguments[a] = callop->arguments()[a];
1.3599 + }
1.3600 + if (op->code() == lir_virtual_call) {
1.3601 + call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
1.3602 + callop->vtable_offset(), arguments, callop->info());
1.3603 + } else {
1.3604 + call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
1.3605 + callop->addr(), arguments, callop->info());
1.3606 + }
1.3607 + inst->at_put(i - 1, call);
1.3608 + inst->insert_before(i + 1, new LIR_Op1(lir_unpack64, FrameMap::g1_long_single_opr, callop->result_opr(),
1.3609 + T_LONG, lir_patch_none, NULL));
1.3610 + }
1.3611 +#endif
1.3612 + break;
1.3613 + }
1.3614 + }
1.3615 + }
1.3616 +}
1.3617 +
1.3618 +void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
1.3619 + LIR_Address* addr = src->as_address_ptr();
1.3620 +
1.3621 + assert(data == dest, "swap uses only 2 operands");
1.3622 + assert (code == lir_xchg, "no xadd on sparc");
1.3623 +
1.3624 + if (data->type() == T_INT) {
1.3625 + __ swap(as_Address(addr), data->as_register());
1.3626 + } else if (data->is_oop()) {
1.3627 + Register obj = data->as_register();
1.3628 + Register narrow = tmp->as_register();
1.3629 +#ifdef _LP64
1.3630 + assert(UseCompressedOops, "swap is 32bit only");
1.3631 + __ encode_heap_oop(obj, narrow);
1.3632 + __ swap(as_Address(addr), narrow);
1.3633 + __ decode_heap_oop(narrow, obj);
1.3634 +#else
1.3635 + __ swap(as_Address(addr), obj);
1.3636 +#endif
1.3637 + } else {
1.3638 + ShouldNotReachHere();
1.3639 + }
1.3640 +}
1.3641 +
1.3642 +#undef __
