1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/src/cpu/sparc/vm/c1_FrameMap_sparc.cpp Wed Apr 27 01:25:04 2016 +0800 1.3 @@ -0,0 +1,439 @@ 1.4 +/* 1.5 + * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. 1.6 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 1.7 + * 1.8 + * This code is free software; you can redistribute it and/or modify it 1.9 + * under the terms of the GNU General Public License version 2 only, as 1.10 + * published by the Free Software Foundation. 1.11 + * 1.12 + * This code is distributed in the hope that it will be useful, but WITHOUT 1.13 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1.14 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 1.15 + * version 2 for more details (a copy is included in the LICENSE file that 1.16 + * accompanied this code). 1.17 + * 1.18 + * You should have received a copy of the GNU General Public License version 1.19 + * 2 along with this work; if not, write to the Free Software Foundation, 1.20 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 1.21 + * 1.22 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 1.23 + * or visit www.oracle.com if you need additional information or have any 1.24 + * questions. 1.25 + * 1.26 + */ 1.27 + 1.28 +#include "precompiled.hpp" 1.29 +#include "c1/c1_FrameMap.hpp" 1.30 +#include "c1/c1_LIR.hpp" 1.31 +#include "runtime/sharedRuntime.hpp" 1.32 +#include "vmreg_sparc.inline.hpp" 1.33 + 1.34 + 1.35 +const int FrameMap::pd_c_runtime_reserved_arg_size = 7; 1.36 + 1.37 + 1.38 +LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool outgoing) { 1.39 + LIR_Opr opr = LIR_OprFact::illegalOpr; 1.40 + VMReg r_1 = reg->first(); 1.41 + VMReg r_2 = reg->second(); 1.42 + if (r_1->is_stack()) { 1.43 + // Convert stack slot to an SP offset 1.44 + // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value 1.45 + // so we must add it in here. 1.46 + int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; 1.47 + opr = LIR_OprFact::address(new LIR_Address(SP_opr, st_off + STACK_BIAS, type)); 1.48 + } else if (r_1->is_Register()) { 1.49 + Register reg = r_1->as_Register(); 1.50 + if (outgoing) { 1.51 + assert(!reg->is_in(), "should be using I regs"); 1.52 + } else { 1.53 + assert(!reg->is_out(), "should be using O regs"); 1.54 + } 1.55 + if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) { 1.56 + opr = as_long_opr(reg); 1.57 + } else if (type == T_OBJECT || type == T_ARRAY) { 1.58 + opr = as_oop_opr(reg); 1.59 + } else if (type == T_METADATA) { 1.60 + opr = as_metadata_opr(reg); 1.61 + } else { 1.62 + opr = as_opr(reg); 1.63 + } 1.64 + } else if (r_1->is_FloatRegister()) { 1.65 + assert(type == T_DOUBLE || type == T_FLOAT, "wrong type"); 1.66 + FloatRegister f = r_1->as_FloatRegister(); 1.67 + if (type == T_DOUBLE) { 1.68 + opr = as_double_opr(f); 1.69 + } else { 1.70 + opr = as_float_opr(f); 1.71 + } 1.72 + } 1.73 + return opr; 1.74 +} 1.75 + 1.76 +// FrameMap 1.77 +//-------------------------------------------------------- 1.78 + 1.79 +FloatRegister FrameMap::_fpu_regs [FrameMap::nof_fpu_regs]; 1.80 + 1.81 +// some useful constant RInfo's: 1.82 +LIR_Opr FrameMap::in_long_opr; 1.83 +LIR_Opr FrameMap::out_long_opr; 1.84 +LIR_Opr FrameMap::g1_long_single_opr; 1.85 + 1.86 +LIR_Opr FrameMap::F0_opr; 1.87 +LIR_Opr FrameMap::F0_double_opr; 1.88 + 1.89 +LIR_Opr FrameMap::G0_opr; 1.90 +LIR_Opr FrameMap::G1_opr; 1.91 +LIR_Opr FrameMap::G2_opr; 1.92 +LIR_Opr FrameMap::G3_opr; 1.93 +LIR_Opr FrameMap::G4_opr; 1.94 +LIR_Opr FrameMap::G5_opr; 1.95 +LIR_Opr FrameMap::G6_opr; 1.96 +LIR_Opr FrameMap::G7_opr; 1.97 +LIR_Opr FrameMap::O0_opr; 1.98 +LIR_Opr FrameMap::O1_opr; 1.99 +LIR_Opr FrameMap::O2_opr; 1.100 +LIR_Opr FrameMap::O3_opr; 1.101 +LIR_Opr FrameMap::O4_opr; 1.102 +LIR_Opr FrameMap::O5_opr; 1.103 +LIR_Opr FrameMap::O6_opr; 1.104 +LIR_Opr FrameMap::O7_opr; 1.105 +LIR_Opr FrameMap::L0_opr; 1.106 +LIR_Opr FrameMap::L1_opr; 1.107 +LIR_Opr FrameMap::L2_opr; 1.108 +LIR_Opr FrameMap::L3_opr; 1.109 +LIR_Opr FrameMap::L4_opr; 1.110 +LIR_Opr FrameMap::L5_opr; 1.111 +LIR_Opr FrameMap::L6_opr; 1.112 +LIR_Opr FrameMap::L7_opr; 1.113 +LIR_Opr FrameMap::I0_opr; 1.114 +LIR_Opr FrameMap::I1_opr; 1.115 +LIR_Opr FrameMap::I2_opr; 1.116 +LIR_Opr FrameMap::I3_opr; 1.117 +LIR_Opr FrameMap::I4_opr; 1.118 +LIR_Opr FrameMap::I5_opr; 1.119 +LIR_Opr FrameMap::I6_opr; 1.120 +LIR_Opr FrameMap::I7_opr; 1.121 + 1.122 +LIR_Opr FrameMap::G0_oop_opr; 1.123 +LIR_Opr FrameMap::G1_oop_opr; 1.124 +LIR_Opr FrameMap::G2_oop_opr; 1.125 +LIR_Opr FrameMap::G3_oop_opr; 1.126 +LIR_Opr FrameMap::G4_oop_opr; 1.127 +LIR_Opr FrameMap::G5_oop_opr; 1.128 +LIR_Opr FrameMap::G6_oop_opr; 1.129 +LIR_Opr FrameMap::G7_oop_opr; 1.130 +LIR_Opr FrameMap::O0_oop_opr; 1.131 +LIR_Opr FrameMap::O1_oop_opr; 1.132 +LIR_Opr FrameMap::O2_oop_opr; 1.133 +LIR_Opr FrameMap::O3_oop_opr; 1.134 +LIR_Opr FrameMap::O4_oop_opr; 1.135 +LIR_Opr FrameMap::O5_oop_opr; 1.136 +LIR_Opr FrameMap::O6_oop_opr; 1.137 +LIR_Opr FrameMap::O7_oop_opr; 1.138 +LIR_Opr FrameMap::L0_oop_opr; 1.139 +LIR_Opr FrameMap::L1_oop_opr; 1.140 +LIR_Opr FrameMap::L2_oop_opr; 1.141 +LIR_Opr FrameMap::L3_oop_opr; 1.142 +LIR_Opr FrameMap::L4_oop_opr; 1.143 +LIR_Opr FrameMap::L5_oop_opr; 1.144 +LIR_Opr FrameMap::L6_oop_opr; 1.145 +LIR_Opr FrameMap::L7_oop_opr; 1.146 +LIR_Opr FrameMap::I0_oop_opr; 1.147 +LIR_Opr FrameMap::I1_oop_opr; 1.148 +LIR_Opr FrameMap::I2_oop_opr; 1.149 +LIR_Opr FrameMap::I3_oop_opr; 1.150 +LIR_Opr FrameMap::I4_oop_opr; 1.151 +LIR_Opr FrameMap::I5_oop_opr; 1.152 +LIR_Opr FrameMap::I6_oop_opr; 1.153 +LIR_Opr FrameMap::I7_oop_opr; 1.154 + 1.155 +LIR_Opr FrameMap::G0_metadata_opr; 1.156 +LIR_Opr FrameMap::G1_metadata_opr; 1.157 +LIR_Opr FrameMap::G2_metadata_opr; 1.158 +LIR_Opr FrameMap::G3_metadata_opr; 1.159 +LIR_Opr FrameMap::G4_metadata_opr; 1.160 +LIR_Opr FrameMap::G5_metadata_opr; 1.161 +LIR_Opr FrameMap::G6_metadata_opr; 1.162 +LIR_Opr FrameMap::G7_metadata_opr; 1.163 +LIR_Opr FrameMap::O0_metadata_opr; 1.164 +LIR_Opr FrameMap::O1_metadata_opr; 1.165 +LIR_Opr FrameMap::O2_metadata_opr; 1.166 +LIR_Opr FrameMap::O3_metadata_opr; 1.167 +LIR_Opr FrameMap::O4_metadata_opr; 1.168 +LIR_Opr FrameMap::O5_metadata_opr; 1.169 +LIR_Opr FrameMap::O6_metadata_opr; 1.170 +LIR_Opr FrameMap::O7_metadata_opr; 1.171 +LIR_Opr FrameMap::L0_metadata_opr; 1.172 +LIR_Opr FrameMap::L1_metadata_opr; 1.173 +LIR_Opr FrameMap::L2_metadata_opr; 1.174 +LIR_Opr FrameMap::L3_metadata_opr; 1.175 +LIR_Opr FrameMap::L4_metadata_opr; 1.176 +LIR_Opr FrameMap::L5_metadata_opr; 1.177 +LIR_Opr FrameMap::L6_metadata_opr; 1.178 +LIR_Opr FrameMap::L7_metadata_opr; 1.179 +LIR_Opr FrameMap::I0_metadata_opr; 1.180 +LIR_Opr FrameMap::I1_metadata_opr; 1.181 +LIR_Opr FrameMap::I2_metadata_opr; 1.182 +LIR_Opr FrameMap::I3_metadata_opr; 1.183 +LIR_Opr FrameMap::I4_metadata_opr; 1.184 +LIR_Opr FrameMap::I5_metadata_opr; 1.185 +LIR_Opr FrameMap::I6_metadata_opr; 1.186 +LIR_Opr FrameMap::I7_metadata_opr; 1.187 + 1.188 +LIR_Opr FrameMap::SP_opr; 1.189 +LIR_Opr FrameMap::FP_opr; 1.190 + 1.191 +LIR_Opr FrameMap::Oexception_opr; 1.192 +LIR_Opr FrameMap::Oissuing_pc_opr; 1.193 + 1.194 +LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, }; 1.195 +LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, }; 1.196 + 1.197 + 1.198 +FloatRegister FrameMap::nr2floatreg (int rnr) { 1.199 + assert(_init_done, "tables not initialized"); 1.200 + debug_only(fpu_range_check(rnr);) 1.201 + return _fpu_regs[rnr]; 1.202 +} 1.203 + 1.204 + 1.205 +// returns true if reg could be smashed by a callee. 1.206 +bool FrameMap::is_caller_save_register (LIR_Opr reg) { 1.207 + if (reg->is_single_fpu() || reg->is_double_fpu()) { return true; } 1.208 + if (reg->is_double_cpu()) { 1.209 + return is_caller_save_register(reg->as_register_lo()) || 1.210 + is_caller_save_register(reg->as_register_hi()); 1.211 + } 1.212 + return is_caller_save_register(reg->as_register()); 1.213 +} 1.214 + 1.215 + 1.216 +NEEDS_CLEANUP // once the new calling convention is enabled, we no 1.217 + // longer need to treat I5, I4 and L0 specially 1.218 +// Because the interpreter destroys caller's I5, I4 and L0, 1.219 +// we must spill them before doing a Java call as we may land in 1.220 +// interpreter. 1.221 +bool FrameMap::is_caller_save_register (Register r) { 1.222 + return (r->is_global() && (r != G0)) || r->is_out(); 1.223 +} 1.224 + 1.225 + 1.226 +void FrameMap::initialize() { 1.227 + assert(!_init_done, "once"); 1.228 + 1.229 + int i=0; 1.230 + // Register usage: 1.231 + // O6: sp 1.232 + // I6: fp 1.233 + // I7: return address 1.234 + // G0: zero 1.235 + // G2: thread 1.236 + // G7: not available 1.237 + // G6: not available 1.238 + /* 0 */ map_register(i++, L0); 1.239 + /* 1 */ map_register(i++, L1); 1.240 + /* 2 */ map_register(i++, L2); 1.241 + /* 3 */ map_register(i++, L3); 1.242 + /* 4 */ map_register(i++, L4); 1.243 + /* 5 */ map_register(i++, L5); 1.244 + /* 6 */ map_register(i++, L6); 1.245 + /* 7 */ map_register(i++, L7); 1.246 + 1.247 + /* 8 */ map_register(i++, I0); 1.248 + /* 9 */ map_register(i++, I1); 1.249 + /* 10 */ map_register(i++, I2); 1.250 + /* 11 */ map_register(i++, I3); 1.251 + /* 12 */ map_register(i++, I4); 1.252 + /* 13 */ map_register(i++, I5); 1.253 + /* 14 */ map_register(i++, O0); 1.254 + /* 15 */ map_register(i++, O1); 1.255 + /* 16 */ map_register(i++, O2); 1.256 + /* 17 */ map_register(i++, O3); 1.257 + /* 18 */ map_register(i++, O4); 1.258 + /* 19 */ map_register(i++, O5); // <- last register visible in RegAlloc (RegAlloc::nof+cpu_regs) 1.259 + /* 20 */ map_register(i++, G1); 1.260 + /* 21 */ map_register(i++, G3); 1.261 + /* 22 */ map_register(i++, G4); 1.262 + /* 23 */ map_register(i++, G5); 1.263 + /* 24 */ map_register(i++, G0); 1.264 + 1.265 + // the following registers are not normally available 1.266 + /* 25 */ map_register(i++, O7); 1.267 + /* 26 */ map_register(i++, G2); 1.268 + /* 27 */ map_register(i++, O6); 1.269 + /* 28 */ map_register(i++, I6); 1.270 + /* 29 */ map_register(i++, I7); 1.271 + /* 30 */ map_register(i++, G6); 1.272 + /* 31 */ map_register(i++, G7); 1.273 + assert(i == nof_cpu_regs, "number of CPU registers"); 1.274 + 1.275 + for (i = 0; i < nof_fpu_regs; i++) { 1.276 + _fpu_regs[i] = as_FloatRegister(i); 1.277 + } 1.278 + 1.279 + _init_done = true; 1.280 + 1.281 + in_long_opr = as_long_opr(I0); 1.282 + out_long_opr = as_long_opr(O0); 1.283 + g1_long_single_opr = as_long_single_opr(G1); 1.284 + 1.285 + G0_opr = as_opr(G0); 1.286 + G1_opr = as_opr(G1); 1.287 + G2_opr = as_opr(G2); 1.288 + G3_opr = as_opr(G3); 1.289 + G4_opr = as_opr(G4); 1.290 + G5_opr = as_opr(G5); 1.291 + G6_opr = as_opr(G6); 1.292 + G7_opr = as_opr(G7); 1.293 + O0_opr = as_opr(O0); 1.294 + O1_opr = as_opr(O1); 1.295 + O2_opr = as_opr(O2); 1.296 + O3_opr = as_opr(O3); 1.297 + O4_opr = as_opr(O4); 1.298 + O5_opr = as_opr(O5); 1.299 + O6_opr = as_opr(O6); 1.300 + O7_opr = as_opr(O7); 1.301 + L0_opr = as_opr(L0); 1.302 + L1_opr = as_opr(L1); 1.303 + L2_opr = as_opr(L2); 1.304 + L3_opr = as_opr(L3); 1.305 + L4_opr = as_opr(L4); 1.306 + L5_opr = as_opr(L5); 1.307 + L6_opr = as_opr(L6); 1.308 + L7_opr = as_opr(L7); 1.309 + I0_opr = as_opr(I0); 1.310 + I1_opr = as_opr(I1); 1.311 + I2_opr = as_opr(I2); 1.312 + I3_opr = as_opr(I3); 1.313 + I4_opr = as_opr(I4); 1.314 + I5_opr = as_opr(I5); 1.315 + I6_opr = as_opr(I6); 1.316 + I7_opr = as_opr(I7); 1.317 + 1.318 + G0_oop_opr = as_oop_opr(G0); 1.319 + G1_oop_opr = as_oop_opr(G1); 1.320 + G2_oop_opr = as_oop_opr(G2); 1.321 + G3_oop_opr = as_oop_opr(G3); 1.322 + G4_oop_opr = as_oop_opr(G4); 1.323 + G5_oop_opr = as_oop_opr(G5); 1.324 + G6_oop_opr = as_oop_opr(G6); 1.325 + G7_oop_opr = as_oop_opr(G7); 1.326 + O0_oop_opr = as_oop_opr(O0); 1.327 + O1_oop_opr = as_oop_opr(O1); 1.328 + O2_oop_opr = as_oop_opr(O2); 1.329 + O3_oop_opr = as_oop_opr(O3); 1.330 + O4_oop_opr = as_oop_opr(O4); 1.331 + O5_oop_opr = as_oop_opr(O5); 1.332 + O6_oop_opr = as_oop_opr(O6); 1.333 + O7_oop_opr = as_oop_opr(O7); 1.334 + L0_oop_opr = as_oop_opr(L0); 1.335 + L1_oop_opr = as_oop_opr(L1); 1.336 + L2_oop_opr = as_oop_opr(L2); 1.337 + L3_oop_opr = as_oop_opr(L3); 1.338 + L4_oop_opr = as_oop_opr(L4); 1.339 + L5_oop_opr = as_oop_opr(L5); 1.340 + L6_oop_opr = as_oop_opr(L6); 1.341 + L7_oop_opr = as_oop_opr(L7); 1.342 + I0_oop_opr = as_oop_opr(I0); 1.343 + I1_oop_opr = as_oop_opr(I1); 1.344 + I2_oop_opr = as_oop_opr(I2); 1.345 + I3_oop_opr = as_oop_opr(I3); 1.346 + I4_oop_opr = as_oop_opr(I4); 1.347 + I5_oop_opr = as_oop_opr(I5); 1.348 + I6_oop_opr = as_oop_opr(I6); 1.349 + I7_oop_opr = as_oop_opr(I7); 1.350 + 1.351 + G0_metadata_opr = as_metadata_opr(G0); 1.352 + G1_metadata_opr = as_metadata_opr(G1); 1.353 + G2_metadata_opr = as_metadata_opr(G2); 1.354 + G3_metadata_opr = as_metadata_opr(G3); 1.355 + G4_metadata_opr = as_metadata_opr(G4); 1.356 + G5_metadata_opr = as_metadata_opr(G5); 1.357 + G6_metadata_opr = as_metadata_opr(G6); 1.358 + G7_metadata_opr = as_metadata_opr(G7); 1.359 + O0_metadata_opr = as_metadata_opr(O0); 1.360 + O1_metadata_opr = as_metadata_opr(O1); 1.361 + O2_metadata_opr = as_metadata_opr(O2); 1.362 + O3_metadata_opr = as_metadata_opr(O3); 1.363 + O4_metadata_opr = as_metadata_opr(O4); 1.364 + O5_metadata_opr = as_metadata_opr(O5); 1.365 + O6_metadata_opr = as_metadata_opr(O6); 1.366 + O7_metadata_opr = as_metadata_opr(O7); 1.367 + L0_metadata_opr = as_metadata_opr(L0); 1.368 + L1_metadata_opr = as_metadata_opr(L1); 1.369 + L2_metadata_opr = as_metadata_opr(L2); 1.370 + L3_metadata_opr = as_metadata_opr(L3); 1.371 + L4_metadata_opr = as_metadata_opr(L4); 1.372 + L5_metadata_opr = as_metadata_opr(L5); 1.373 + L6_metadata_opr = as_metadata_opr(L6); 1.374 + L7_metadata_opr = as_metadata_opr(L7); 1.375 + I0_metadata_opr = as_metadata_opr(I0); 1.376 + I1_metadata_opr = as_metadata_opr(I1); 1.377 + I2_metadata_opr = as_metadata_opr(I2); 1.378 + I3_metadata_opr = as_metadata_opr(I3); 1.379 + I4_metadata_opr = as_metadata_opr(I4); 1.380 + I5_metadata_opr = as_metadata_opr(I5); 1.381 + I6_metadata_opr = as_metadata_opr(I6); 1.382 + I7_metadata_opr = as_metadata_opr(I7); 1.383 + 1.384 + FP_opr = as_pointer_opr(FP); 1.385 + SP_opr = as_pointer_opr(SP); 1.386 + 1.387 + F0_opr = as_float_opr(F0); 1.388 + F0_double_opr = as_double_opr(F0); 1.389 + 1.390 + Oexception_opr = as_oop_opr(Oexception); 1.391 + Oissuing_pc_opr = as_opr(Oissuing_pc); 1.392 + 1.393 + _caller_save_cpu_regs[0] = FrameMap::O0_opr; 1.394 + _caller_save_cpu_regs[1] = FrameMap::O1_opr; 1.395 + _caller_save_cpu_regs[2] = FrameMap::O2_opr; 1.396 + _caller_save_cpu_regs[3] = FrameMap::O3_opr; 1.397 + _caller_save_cpu_regs[4] = FrameMap::O4_opr; 1.398 + _caller_save_cpu_regs[5] = FrameMap::O5_opr; 1.399 + _caller_save_cpu_regs[6] = FrameMap::G1_opr; 1.400 + _caller_save_cpu_regs[7] = FrameMap::G3_opr; 1.401 + _caller_save_cpu_regs[8] = FrameMap::G4_opr; 1.402 + _caller_save_cpu_regs[9] = FrameMap::G5_opr; 1.403 + for (int i = 0; i < nof_caller_save_fpu_regs; i++) { 1.404 + _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i); 1.405 + } 1.406 +} 1.407 + 1.408 + 1.409 +Address FrameMap::make_new_address(ByteSize sp_offset) const { 1.410 + return Address(SP, STACK_BIAS + in_bytes(sp_offset)); 1.411 +} 1.412 + 1.413 + 1.414 +VMReg FrameMap::fpu_regname (int n) { 1.415 + return as_FloatRegister(n)->as_VMReg(); 1.416 +} 1.417 + 1.418 + 1.419 +LIR_Opr FrameMap::stack_pointer() { 1.420 + return SP_opr; 1.421 +} 1.422 + 1.423 + 1.424 +// JSR 292 1.425 +LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() { 1.426 + assert(L7 == L7_mh_SP_save, "must be same register"); 1.427 + return L7_opr; 1.428 +} 1.429 + 1.430 + 1.431 +bool FrameMap::validate_frame() { 1.432 + int max_offset = in_bytes(framesize_in_bytes()); 1.433 + int java_index = 0; 1.434 + for (int i = 0; i < _incoming_arguments->length(); i++) { 1.435 + LIR_Opr opr = _incoming_arguments->at(i); 1.436 + if (opr->is_stack()) { 1.437 + max_offset = MAX2(_argument_locations->at(java_index), max_offset); 1.438 + } 1.439 + java_index += type2size[opr->type()]; 1.440 + } 1.441 + return Assembler::is_simm13(max_offset + STACK_BIAS); 1.442 +}