1.1 --- a/src/cpu/ppc/vm/assembler_ppc.hpp Mon Sep 24 17:18:38 2018 -0400 1.2 +++ b/src/cpu/ppc/vm/assembler_ppc.hpp Thu Sep 22 12:17:24 2016 +0200 1.3 @@ -468,6 +468,10 @@ 1.4 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1), 1.5 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1), 1.6 1.7 + // Vector-Scalar (VSX) instruction support. 1.8 + MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1), 1.9 + MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1), 1.10 + 1.11 // Vector Permute and Formatting 1.12 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ), 1.13 VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ), 1.14 @@ -1938,6 +1942,10 @@ 1.15 inline void mtvscr( VectorRegister b); 1.16 inline void mfvscr( VectorRegister d); 1.17 1.18 + // Vector-Scalar (VSX) instructions. 1.19 + inline void mtvrd( VectorRegister d, Register a); 1.20 + inline void mfvrd( Register a, VectorRegister d); 1.21 + 1.22 // AES (introduced with Power 8) 1.23 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b); 1.24 inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);