src/cpu/x86/vm/assembler_x86.hpp

changeset 797
f8199438385b
parent 791
1ee8caae33af
parent 739
dc7f315e41f7
child 840
2649e5276dd7
     1.1 --- a/src/cpu/x86/vm/assembler_x86.hpp	Thu Sep 04 18:40:43 2008 -0700
     1.2 +++ b/src/cpu/x86/vm/assembler_x86.hpp	Wed Sep 17 16:49:18 2008 +0400
     1.3 @@ -227,9 +227,11 @@
     1.4  #endif // ASSERT
     1.5  
     1.6    // accessors
     1.7 -  bool uses(Register reg) const {
     1.8 -    return _base == reg || _index == reg;
     1.9 -  }
    1.10 +  bool        uses(Register reg) const { return _base == reg || _index == reg; }
    1.11 +  Register    base()             const { return _base;  }
    1.12 +  Register    index()            const { return _index; }
    1.13 +  ScaleFactor scale()            const { return _scale; }
    1.14 +  int         disp()             const { return _disp;  }
    1.15  
    1.16    // Convert the raw encoding form into the form expected by the constructor for
    1.17    // Address.  An index of 4 (rsp) corresponds to having no index, so convert
    1.18 @@ -1310,7 +1312,8 @@
    1.19  // on arguments should also go in here.
    1.20  
    1.21  class MacroAssembler: public Assembler {
    1.22 - friend class LIR_Assembler;
    1.23 +  friend class LIR_Assembler;
    1.24 +  friend class Runtime1;      // as_Address()
    1.25   protected:
    1.26  
    1.27    Address as_Address(AddressLiteral adr);
    1.28 @@ -1453,6 +1456,7 @@
    1.29    // The pointer will be loaded into the thread register.
    1.30    void get_thread(Register thread);
    1.31  
    1.32 +
    1.33    // Support for VM calls
    1.34    //
    1.35    // It is imperative that all calls into the VM are handled via the call_VM macros.
    1.36 @@ -1527,6 +1531,22 @@
    1.37    void store_check(Register obj);                // store check for obj - register is destroyed afterwards
    1.38    void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
    1.39  
    1.40 +  void g1_write_barrier_pre(Register obj,
    1.41 +#ifndef _LP64
    1.42 +                            Register thread,
    1.43 +#endif
    1.44 +                            Register tmp,
    1.45 +                            Register tmp2,
    1.46 +                            bool     tosca_live);
    1.47 +  void g1_write_barrier_post(Register store_addr,
    1.48 +                             Register new_val,
    1.49 +#ifndef _LP64
    1.50 +                             Register thread,
    1.51 +#endif
    1.52 +                             Register tmp,
    1.53 +                             Register tmp2);
    1.54 +
    1.55 +
    1.56    // split store_check(Register obj) to enhance instruction interleaving
    1.57    void store_check_part_1(Register obj);
    1.58    void store_check_part_2(Register obj);

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