1.1 --- a/src/cpu/x86/vm/x86_64.ad Tue Apr 29 19:45:22 2008 -0700
1.2 +++ b/src/cpu/x86/vm/x86_64.ad Wed May 07 08:06:46 2008 -0700
1.3 @@ -8075,6 +8075,18 @@
1.4 ins_pipe(ialu_reg_mem_alu0);
1.5 %}
1.6
1.7 +instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
1.8 +%{
1.9 + match(Set dst (MulHiL src rax));
1.10 + effect(USE_KILL rax, KILL cr);
1.11 +
1.12 + ins_cost(300);
1.13 + format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
1.14 + opcode(0xF7, 0x5); /* Opcode F7 /5 */
1.15 + ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
1.16 + ins_pipe(ialu_reg_reg_alu0);
1.17 +%}
1.18 +
1.19 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
1.20 rFlagsReg cr)
1.21 %{
