1.1 --- a/src/cpu/sparc/vm/sparc.ad Fri Jan 08 22:02:42 2010 -0800
1.2 +++ b/src/cpu/sparc/vm/sparc.ad Sat Jan 09 00:59:35 2010 -0800
1.3 @@ -1,5 +1,5 @@
1.4 //
1.5 -// Copyright 1998-2009 Sun Microsystems, Inc. All Rights Reserved.
1.6 +// Copyright 1998-2010 Sun Microsystems, Inc. All Rights Reserved.
1.7 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.8 //
1.9 // This code is free software; you can redistribute it and/or modify it
1.10 @@ -6668,7 +6668,7 @@
1.11 ins_pipe(ialu_imm);
1.12 %}
1.13
1.14 -instruct cmovII_U_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
1.15 +instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
1.16 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
1.17 ins_cost(150);
1.18 size(4);
1.19 @@ -6677,7 +6677,7 @@
1.20 ins_pipe(ialu_reg);
1.21 %}
1.22
1.23 -instruct cmovII_U_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
1.24 +instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
1.25 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
1.26 ins_cost(140);
1.27 size(4);
1.28 @@ -6723,6 +6723,16 @@
1.29 ins_pipe(ialu_reg);
1.30 %}
1.31
1.32 +// This instruction also works with CmpN so we don't need cmovNN_reg.
1.33 +instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
1.34 + match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
1.35 + ins_cost(150);
1.36 + size(4);
1.37 + format %{ "MOV$cmp $icc,$src,$dst" %}
1.38 + ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
1.39 + ins_pipe(ialu_reg);
1.40 +%}
1.41 +
1.42 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
1.43 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
1.44 ins_cost(150);
1.45 @@ -6760,6 +6770,16 @@
1.46 ins_pipe(ialu_reg);
1.47 %}
1.48
1.49 +instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
1.50 + match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
1.51 + ins_cost(150);
1.52 +
1.53 + size(4);
1.54 + format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
1.55 + ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
1.56 + ins_pipe(ialu_reg);
1.57 +%}
1.58 +
1.59 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
1.60 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
1.61 ins_cost(140);
1.62 @@ -6770,6 +6790,16 @@
1.63 ins_pipe(ialu_imm);
1.64 %}
1.65
1.66 +instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
1.67 + match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
1.68 + ins_cost(140);
1.69 +
1.70 + size(4);
1.71 + format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
1.72 + ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
1.73 + ins_pipe(ialu_imm);
1.74 +%}
1.75 +
1.76 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
1.77 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
1.78 ins_cost(150);
1.79 @@ -6809,6 +6839,17 @@
1.80 ins_pipe(int_conditional_float_move);
1.81 %}
1.82
1.83 +instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
1.84 + match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
1.85 + ins_cost(150);
1.86 +
1.87 + size(4);
1.88 + format %{ "FMOVS$cmp $icc,$src,$dst" %}
1.89 + opcode(0x101);
1.90 + ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
1.91 + ins_pipe(int_conditional_float_move);
1.92 +%}
1.93 +
1.94 // Conditional move,
1.95 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
1.96 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
1.97 @@ -6842,6 +6883,17 @@
1.98 ins_pipe(int_conditional_double_move);
1.99 %}
1.100
1.101 +instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
1.102 + match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
1.103 + ins_cost(150);
1.104 +
1.105 + size(4);
1.106 + format %{ "FMOVD$cmp $icc,$src,$dst" %}
1.107 + opcode(0x102);
1.108 + ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
1.109 + ins_pipe(int_conditional_double_move);
1.110 +%}
1.111 +
1.112 // Conditional move,
1.113 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
1.114 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
1.115 @@ -6881,6 +6933,17 @@
1.116 %}
1.117
1.118
1.119 +instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
1.120 + match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
1.121 + ins_cost(150);
1.122 +
1.123 + size(4);
1.124 + format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
1.125 + ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
1.126 + ins_pipe(ialu_reg);
1.127 +%}
1.128 +
1.129 +
1.130 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
1.131 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
1.132 ins_cost(150);
