1.1 --- a/src/cpu/sparc/vm/assembler_sparc.hpp Mon Nov 26 15:11:55 2012 +0100
1.2 +++ b/src/cpu/sparc/vm/assembler_sparc.hpp Thu Dec 06 09:57:41 2012 -0800
1.3 @@ -25,554 +25,13 @@
1.4 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
1.5 #define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
1.6
1.7 -class BiasedLockingCounters;
1.8 -
1.9 -// <sys/trap.h> promises that the system will not use traps 16-31
1.10 -#define ST_RESERVED_FOR_USER_0 0x10
1.11 -
1.12 -/* Written: David Ungar 4/19/97 */
1.13 -
1.14 -// Contains all the definitions needed for sparc assembly code generation.
1.15 -
1.16 -// Register aliases for parts of the system:
1.17 -
1.18 -// 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe
1.19 -// across context switches in V8+ ABI. Of course, there are no 64 bit regs
1.20 -// in V8 ABI. All 64 bits are preserved in V9 ABI for all registers.
1.21 -
1.22 -// g2-g4 are scratch registers called "application globals". Their
1.23 -// meaning is reserved to the "compilation system"--which means us!
1.24 -// They are are not supposed to be touched by ordinary C code, although
1.25 -// highly-optimized C code might steal them for temps. They are safe
1.26 -// across thread switches, and the ABI requires that they be safe
1.27 -// across function calls.
1.28 -//
1.29 -// g1 and g3 are touched by more modules. V8 allows g1 to be clobbered
1.30 -// across func calls, and V8+ also allows g5 to be clobbered across
1.31 -// func calls. Also, g1 and g5 can get touched while doing shared
1.32 -// library loading.
1.33 -//
1.34 -// We must not touch g7 (it is the thread-self register) and g6 is
1.35 -// reserved for certain tools. g0, of course, is always zero.
1.36 -//
1.37 -// (Sources: SunSoft Compilers Group, thread library engineers.)
1.38 -
1.39 -// %%%% The interpreter should be revisited to reduce global scratch regs.
1.40 -
1.41 -// This global always holds the current JavaThread pointer:
1.42 -
1.43 -REGISTER_DECLARATION(Register, G2_thread , G2);
1.44 -REGISTER_DECLARATION(Register, G6_heapbase , G6);
1.45 -
1.46 -// The following globals are part of the Java calling convention:
1.47 -
1.48 -REGISTER_DECLARATION(Register, G5_method , G5);
1.49 -REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method);
1.50 -REGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method);
1.51 -
1.52 -// The following globals are used for the new C1 & interpreter calling convention:
1.53 -REGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument
1.54 -
1.55 -// This local is used to preserve G2_thread in the interpreter and in stubs:
1.56 -REGISTER_DECLARATION(Register, L7_thread_cache , L7);
1.57 -
1.58 -// These globals are used as scratch registers in the interpreter:
1.59 -
1.60 -REGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch
1.61 -REGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME
1.62 -REGISTER_DECLARATION(Register, G3_scratch , G3);
1.63 -REGISTER_DECLARATION(Register, G4_scratch , G4);
1.64 -
1.65 -// These globals are used as short-lived scratch registers in the compiler:
1.66 -
1.67 -REGISTER_DECLARATION(Register, Gtemp , G5);
1.68 -
1.69 -// JSR 292 fixed register usages:
1.70 -REGISTER_DECLARATION(Register, G5_method_type , G5);
1.71 -REGISTER_DECLARATION(Register, G3_method_handle , G3);
1.72 -REGISTER_DECLARATION(Register, L7_mh_SP_save , L7);
1.73 -
1.74 -// The compiler requires that G5_megamorphic_method is G5_inline_cache_klass,
1.75 -// because a single patchable "set" instruction (NativeMovConstReg,
1.76 -// or NativeMovConstPatching for compiler1) instruction
1.77 -// serves to set up either quantity, depending on whether the compiled
1.78 -// call site is an inline cache or is megamorphic. See the function
1.79 -// CompiledIC::set_to_megamorphic.
1.80 -//
1.81 -// If a inline cache targets an interpreted method, then the
1.82 -// G5 register will be used twice during the call. First,
1.83 -// the call site will be patched to load a compiledICHolder
1.84 -// into G5. (This is an ordered pair of ic_klass, method.)
1.85 -// The c2i adapter will first check the ic_klass, then load
1.86 -// G5_method with the method part of the pair just before
1.87 -// jumping into the interpreter.
1.88 -//
1.89 -// Note that G5_method is only the method-self for the interpreter,
1.90 -// and is logically unrelated to G5_megamorphic_method.
1.91 -//
1.92 -// Invariants on G2_thread (the JavaThread pointer):
1.93 -// - it should not be used for any other purpose anywhere
1.94 -// - it must be re-initialized by StubRoutines::call_stub()
1.95 -// - it must be preserved around every use of call_VM
1.96 -
1.97 -// We can consider using g2/g3/g4 to cache more values than the
1.98 -// JavaThread, such as the card-marking base or perhaps pointers into
1.99 -// Eden. It's something of a waste to use them as scratch temporaries,
1.100 -// since they are not supposed to be volatile. (Of course, if we find
1.101 -// that Java doesn't benefit from application globals, then we can just
1.102 -// use them as ordinary temporaries.)
1.103 -//
1.104 -// Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,
1.105 -// it makes sense to use them routinely for procedure linkage,
1.106 -// whenever the On registers are not applicable. Examples: G5_method,
1.107 -// G5_inline_cache_klass, and a double handful of miscellaneous compiler
1.108 -// stubs. This means that compiler stubs, etc., should be kept to a
1.109 -// maximum of two or three G-register arguments.
1.110 -
1.111 -
1.112 -// stub frames
1.113 -
1.114 -REGISTER_DECLARATION(Register, Lentry_args , L0); // pointer to args passed to callee (interpreter) not stub itself
1.115 -
1.116 -// Interpreter frames
1.117 -
1.118 -#ifdef CC_INTERP
1.119 -REGISTER_DECLARATION(Register, Lstate , L0); // interpreter state object pointer
1.120 -REGISTER_DECLARATION(Register, L1_scratch , L1); // scratch
1.121 -REGISTER_DECLARATION(Register, Lmirror , L1); // mirror (for native methods only)
1.122 -REGISTER_DECLARATION(Register, L2_scratch , L2);
1.123 -REGISTER_DECLARATION(Register, L3_scratch , L3);
1.124 -REGISTER_DECLARATION(Register, L4_scratch , L4);
1.125 -REGISTER_DECLARATION(Register, Lscratch , L5); // C1 uses
1.126 -REGISTER_DECLARATION(Register, Lscratch2 , L6); // C1 uses
1.127 -REGISTER_DECLARATION(Register, L7_scratch , L7); // constant pool cache
1.128 -REGISTER_DECLARATION(Register, O5_savedSP , O5);
1.129 -REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply
1.130 - // a copy SP, so in 64-bit it's a biased value. The bias
1.131 - // is added and removed as needed in the frame code.
1.132 -// Interface to signature handler
1.133 -REGISTER_DECLARATION(Register, Llocals , L7); // pointer to locals for signature handler
1.134 -REGISTER_DECLARATION(Register, Lmethod , L6); // Method* when calling signature handler
1.135 -
1.136 -#else
1.137 -REGISTER_DECLARATION(Register, Lesp , L0); // expression stack pointer
1.138 -REGISTER_DECLARATION(Register, Lbcp , L1); // pointer to next bytecode
1.139 -REGISTER_DECLARATION(Register, Lmethod , L2);
1.140 -REGISTER_DECLARATION(Register, Llocals , L3);
1.141 -REGISTER_DECLARATION(Register, Largs , L3); // pointer to locals for signature handler
1.142 - // must match Llocals in asm interpreter
1.143 -REGISTER_DECLARATION(Register, Lmonitors , L4);
1.144 -REGISTER_DECLARATION(Register, Lbyte_code , L5);
1.145 -// When calling out from the interpreter we record SP so that we can remove any extra stack
1.146 -// space allocated during adapter transitions. This register is only live from the point
1.147 -// of the call until we return.
1.148 -REGISTER_DECLARATION(Register, Llast_SP , L5);
1.149 -REGISTER_DECLARATION(Register, Lscratch , L5);
1.150 -REGISTER_DECLARATION(Register, Lscratch2 , L6);
1.151 -REGISTER_DECLARATION(Register, LcpoolCache , L6); // constant pool cache
1.152 -
1.153 -REGISTER_DECLARATION(Register, O5_savedSP , O5);
1.154 -REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply
1.155 - // a copy SP, so in 64-bit it's a biased value. The bias
1.156 - // is added and removed as needed in the frame code.
1.157 -REGISTER_DECLARATION(Register, IdispatchTables , I4); // Base address of the bytecode dispatch tables
1.158 -REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode
1.159 -REGISTER_DECLARATION(Register, ImethodDataPtr , I2); // Pointer to the current method data
1.160 -#endif /* CC_INTERP */
1.161 -
1.162 -// NOTE: Lscratch2 and LcpoolCache point to the same registers in
1.163 -// the interpreter code. If Lscratch2 needs to be used for some
1.164 -// purpose than LcpoolCache should be restore after that for
1.165 -// the interpreter to work right
1.166 -// (These assignments must be compatible with L7_thread_cache; see above.)
1.167 -
1.168 -// Since Lbcp points into the middle of the method object,
1.169 -// it is temporarily converted into a "bcx" during GC.
1.170 -
1.171 -// Exception processing
1.172 -// These registers are passed into exception handlers.
1.173 -// All exception handlers require the exception object being thrown.
1.174 -// In addition, an nmethod's exception handler must be passed
1.175 -// the address of the call site within the nmethod, to allow
1.176 -// proper selection of the applicable catch block.
1.177 -// (Interpreter frames use their own bcp() for this purpose.)
1.178 -//
1.179 -// The Oissuing_pc value is not always needed. When jumping to a
1.180 -// handler that is known to be interpreted, the Oissuing_pc value can be
1.181 -// omitted. An actual catch block in compiled code receives (from its
1.182 -// nmethod's exception handler) the thrown exception in the Oexception,
1.183 -// but it doesn't need the Oissuing_pc.
1.184 -//
1.185 -// If an exception handler (either interpreted or compiled)
1.186 -// discovers there is no applicable catch block, it updates
1.187 -// the Oissuing_pc to the continuation PC of its own caller,
1.188 -// pops back to that caller's stack frame, and executes that
1.189 -// caller's exception handler. Obviously, this process will
1.190 -// iterate until the control stack is popped back to a method
1.191 -// containing an applicable catch block. A key invariant is
1.192 -// that the Oissuing_pc value is always a value local to
1.193 -// the method whose exception handler is currently executing.
1.194 -//
1.195 -// Note: The issuing PC value is __not__ a raw return address (I7 value).
1.196 -// It is a "return pc", the address __following__ the call.
1.197 -// Raw return addresses are converted to issuing PCs by frame::pc(),
1.198 -// or by stubs. Issuing PCs can be used directly with PC range tables.
1.199 -//
1.200 -REGISTER_DECLARATION(Register, Oexception , O0); // exception being thrown
1.201 -REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from
1.202 -
1.203 -
1.204 -// These must occur after the declarations above
1.205 -#ifndef DONT_USE_REGISTER_DEFINES
1.206 -
1.207 -#define Gthread AS_REGISTER(Register, Gthread)
1.208 -#define Gmethod AS_REGISTER(Register, Gmethod)
1.209 -#define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method)
1.210 -#define Ginline_cache_reg AS_REGISTER(Register, Ginline_cache_reg)
1.211 -#define Gargs AS_REGISTER(Register, Gargs)
1.212 -#define Lthread_cache AS_REGISTER(Register, Lthread_cache)
1.213 -#define Gframe_size AS_REGISTER(Register, Gframe_size)
1.214 -#define Gtemp AS_REGISTER(Register, Gtemp)
1.215 -
1.216 -#ifdef CC_INTERP
1.217 -#define Lstate AS_REGISTER(Register, Lstate)
1.218 -#define Lesp AS_REGISTER(Register, Lesp)
1.219 -#define L1_scratch AS_REGISTER(Register, L1_scratch)
1.220 -#define Lmirror AS_REGISTER(Register, Lmirror)
1.221 -#define L2_scratch AS_REGISTER(Register, L2_scratch)
1.222 -#define L3_scratch AS_REGISTER(Register, L3_scratch)
1.223 -#define L4_scratch AS_REGISTER(Register, L4_scratch)
1.224 -#define Lscratch AS_REGISTER(Register, Lscratch)
1.225 -#define Lscratch2 AS_REGISTER(Register, Lscratch2)
1.226 -#define L7_scratch AS_REGISTER(Register, L7_scratch)
1.227 -#define Ostate AS_REGISTER(Register, Ostate)
1.228 -#else
1.229 -#define Lesp AS_REGISTER(Register, Lesp)
1.230 -#define Lbcp AS_REGISTER(Register, Lbcp)
1.231 -#define Lmethod AS_REGISTER(Register, Lmethod)
1.232 -#define Llocals AS_REGISTER(Register, Llocals)
1.233 -#define Lmonitors AS_REGISTER(Register, Lmonitors)
1.234 -#define Lbyte_code AS_REGISTER(Register, Lbyte_code)
1.235 -#define Lscratch AS_REGISTER(Register, Lscratch)
1.236 -#define Lscratch2 AS_REGISTER(Register, Lscratch2)
1.237 -#define LcpoolCache AS_REGISTER(Register, LcpoolCache)
1.238 -#endif /* ! CC_INTERP */
1.239 -
1.240 -#define Lentry_args AS_REGISTER(Register, Lentry_args)
1.241 -#define I5_savedSP AS_REGISTER(Register, I5_savedSP)
1.242 -#define O5_savedSP AS_REGISTER(Register, O5_savedSP)
1.243 -#define IdispatchAddress AS_REGISTER(Register, IdispatchAddress)
1.244 -#define ImethodDataPtr AS_REGISTER(Register, ImethodDataPtr)
1.245 -#define IdispatchTables AS_REGISTER(Register, IdispatchTables)
1.246 -
1.247 -#define Oexception AS_REGISTER(Register, Oexception)
1.248 -#define Oissuing_pc AS_REGISTER(Register, Oissuing_pc)
1.249 -
1.250 -
1.251 -#endif
1.252 -
1.253 -// Address is an abstraction used to represent a memory location.
1.254 -//
1.255 -// Note: A register location is represented via a Register, not
1.256 -// via an address for efficiency & simplicity reasons.
1.257 -
1.258 -class Address VALUE_OBJ_CLASS_SPEC {
1.259 - private:
1.260 - Register _base; // Base register.
1.261 - RegisterOrConstant _index_or_disp; // Index register or constant displacement.
1.262 - RelocationHolder _rspec;
1.263 -
1.264 - public:
1.265 - Address() : _base(noreg), _index_or_disp(noreg) {}
1.266 -
1.267 - Address(Register base, RegisterOrConstant index_or_disp)
1.268 - : _base(base),
1.269 - _index_or_disp(index_or_disp) {
1.270 - }
1.271 -
1.272 - Address(Register base, Register index)
1.273 - : _base(base),
1.274 - _index_or_disp(index) {
1.275 - }
1.276 -
1.277 - Address(Register base, int disp)
1.278 - : _base(base),
1.279 - _index_or_disp(disp) {
1.280 - }
1.281 -
1.282 -#ifdef ASSERT
1.283 - // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
1.284 - Address(Register base, ByteSize disp)
1.285 - : _base(base),
1.286 - _index_or_disp(in_bytes(disp)) {
1.287 - }
1.288 -#endif
1.289 -
1.290 - // accessors
1.291 - Register base() const { return _base; }
1.292 - Register index() const { return _index_or_disp.as_register(); }
1.293 - int disp() const { return _index_or_disp.as_constant(); }
1.294 -
1.295 - bool has_index() const { return _index_or_disp.is_register(); }
1.296 - bool has_disp() const { return _index_or_disp.is_constant(); }
1.297 -
1.298 - bool uses(Register reg) const { return base() == reg || (has_index() && index() == reg); }
1.299 -
1.300 - const relocInfo::relocType rtype() { return _rspec.type(); }
1.301 - const RelocationHolder& rspec() { return _rspec; }
1.302 -
1.303 - RelocationHolder rspec(int offset) const {
1.304 - return offset == 0 ? _rspec : _rspec.plus(offset);
1.305 - }
1.306 -
1.307 - inline bool is_simm13(int offset = 0); // check disp+offset for overflow
1.308 -
1.309 - Address plus_disp(int plusdisp) const { // bump disp by a small amount
1.310 - assert(_index_or_disp.is_constant(), "must have a displacement");
1.311 - Address a(base(), disp() + plusdisp);
1.312 - return a;
1.313 - }
1.314 - bool is_same_address(Address a) const {
1.315 - // disregard _rspec
1.316 - return base() == a.base() && (has_index() ? index() == a.index() : disp() == a.disp());
1.317 - }
1.318 -
1.319 - Address after_save() const {
1.320 - Address a = (*this);
1.321 - a._base = a._base->after_save();
1.322 - return a;
1.323 - }
1.324 -
1.325 - Address after_restore() const {
1.326 - Address a = (*this);
1.327 - a._base = a._base->after_restore();
1.328 - return a;
1.329 - }
1.330 -
1.331 - // Convert the raw encoding form into the form expected by the
1.332 - // constructor for Address.
1.333 - static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
1.334 -
1.335 - friend class Assembler;
1.336 -};
1.337 -
1.338 -
1.339 -class AddressLiteral VALUE_OBJ_CLASS_SPEC {
1.340 - private:
1.341 - address _address;
1.342 - RelocationHolder _rspec;
1.343 -
1.344 - RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
1.345 - switch (rtype) {
1.346 - case relocInfo::external_word_type:
1.347 - return external_word_Relocation::spec(addr);
1.348 - case relocInfo::internal_word_type:
1.349 - return internal_word_Relocation::spec(addr);
1.350 -#ifdef _LP64
1.351 - case relocInfo::opt_virtual_call_type:
1.352 - return opt_virtual_call_Relocation::spec();
1.353 - case relocInfo::static_call_type:
1.354 - return static_call_Relocation::spec();
1.355 - case relocInfo::runtime_call_type:
1.356 - return runtime_call_Relocation::spec();
1.357 -#endif
1.358 - case relocInfo::none:
1.359 - return RelocationHolder();
1.360 - default:
1.361 - ShouldNotReachHere();
1.362 - return RelocationHolder();
1.363 - }
1.364 - }
1.365 -
1.366 - protected:
1.367 - // creation
1.368 - AddressLiteral() : _address(NULL), _rspec(NULL) {}
1.369 -
1.370 - public:
1.371 - AddressLiteral(address addr, RelocationHolder const& rspec)
1.372 - : _address(addr),
1.373 - _rspec(rspec) {}
1.374 -
1.375 - // Some constructors to avoid casting at the call site.
1.376 - AddressLiteral(jobject obj, RelocationHolder const& rspec)
1.377 - : _address((address) obj),
1.378 - _rspec(rspec) {}
1.379 -
1.380 - AddressLiteral(intptr_t value, RelocationHolder const& rspec)
1.381 - : _address((address) value),
1.382 - _rspec(rspec) {}
1.383 -
1.384 - AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
1.385 - : _address((address) addr),
1.386 - _rspec(rspec_from_rtype(rtype, (address) addr)) {}
1.387 -
1.388 - // Some constructors to avoid casting at the call site.
1.389 - AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none)
1.390 - : _address((address) addr),
1.391 - _rspec(rspec_from_rtype(rtype, (address) addr)) {}
1.392 -
1.393 - AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none)
1.394 - : _address((address) addr),
1.395 - _rspec(rspec_from_rtype(rtype, (address) addr)) {}
1.396 -
1.397 - AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none)
1.398 - : _address((address) addr),
1.399 - _rspec(rspec_from_rtype(rtype, (address) addr)) {}
1.400 -
1.401 - AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none)
1.402 - : _address((address) addr),
1.403 - _rspec(rspec_from_rtype(rtype, (address) addr)) {}
1.404 -
1.405 - AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none)
1.406 - : _address((address) addr),
1.407 - _rspec(rspec_from_rtype(rtype, (address) addr)) {}
1.408 -
1.409 - AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none)
1.410 - : _address((address) addr),
1.411 - _rspec(rspec_from_rtype(rtype, (address) addr)) {}
1.412 -
1.413 -#ifdef _LP64
1.414 - // 32-bit complains about a multiple declaration for int*.
1.415 - AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none)
1.416 - : _address((address) addr),
1.417 - _rspec(rspec_from_rtype(rtype, (address) addr)) {}
1.418 -#endif
1.419 -
1.420 - AddressLiteral(Metadata* addr, relocInfo::relocType rtype = relocInfo::none)
1.421 - : _address((address) addr),
1.422 - _rspec(rspec_from_rtype(rtype, (address) addr)) {}
1.423 -
1.424 - AddressLiteral(Metadata** addr, relocInfo::relocType rtype = relocInfo::none)
1.425 - : _address((address) addr),
1.426 - _rspec(rspec_from_rtype(rtype, (address) addr)) {}
1.427 -
1.428 - AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none)
1.429 - : _address((address) addr),
1.430 - _rspec(rspec_from_rtype(rtype, (address) addr)) {}
1.431 -
1.432 - AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none)
1.433 - : _address((address) addr),
1.434 - _rspec(rspec_from_rtype(rtype, (address) addr)) {}
1.435 -
1.436 - intptr_t value() const { return (intptr_t) _address; }
1.437 - int low10() const;
1.438 -
1.439 - const relocInfo::relocType rtype() const { return _rspec.type(); }
1.440 - const RelocationHolder& rspec() const { return _rspec; }
1.441 -
1.442 - RelocationHolder rspec(int offset) const {
1.443 - return offset == 0 ? _rspec : _rspec.plus(offset);
1.444 - }
1.445 -};
1.446 -
1.447 -// Convenience classes
1.448 -class ExternalAddress: public AddressLiteral {
1.449 - private:
1.450 - static relocInfo::relocType reloc_for_target(address target) {
1.451 - // Sometimes ExternalAddress is used for values which aren't
1.452 - // exactly addresses, like the card table base.
1.453 - // external_word_type can't be used for values in the first page
1.454 - // so just skip the reloc in that case.
1.455 - return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
1.456 - }
1.457 -
1.458 - public:
1.459 - ExternalAddress(address target) : AddressLiteral(target, reloc_for_target( target)) {}
1.460 - ExternalAddress(Metadata** target) : AddressLiteral(target, reloc_for_target((address) target)) {}
1.461 -};
1.462 -
1.463 -inline Address RegisterImpl::address_in_saved_window() const {
1.464 - return (Address(SP, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS));
1.465 -}
1.466 -
1.467 -
1.468 -
1.469 -// Argument is an abstraction used to represent an outgoing
1.470 -// actual argument or an incoming formal parameter, whether
1.471 -// it resides in memory or in a register, in a manner consistent
1.472 -// with the SPARC Application Binary Interface, or ABI. This is
1.473 -// often referred to as the native or C calling convention.
1.474 -
1.475 -class Argument VALUE_OBJ_CLASS_SPEC {
1.476 - private:
1.477 - int _number;
1.478 - bool _is_in;
1.479 -
1.480 - public:
1.481 -#ifdef _LP64
1.482 - enum {
1.483 - n_register_parameters = 6, // only 6 registers may contain integer parameters
1.484 - n_float_register_parameters = 16 // Can have up to 16 floating registers
1.485 - };
1.486 -#else
1.487 - enum {
1.488 - n_register_parameters = 6 // only 6 registers may contain integer parameters
1.489 - };
1.490 -#endif
1.491 -
1.492 - // creation
1.493 - Argument(int number, bool is_in) : _number(number), _is_in(is_in) {}
1.494 -
1.495 - int number() const { return _number; }
1.496 - bool is_in() const { return _is_in; }
1.497 - bool is_out() const { return !is_in(); }
1.498 -
1.499 - Argument successor() const { return Argument(number() + 1, is_in()); }
1.500 - Argument as_in() const { return Argument(number(), true ); }
1.501 - Argument as_out() const { return Argument(number(), false); }
1.502 -
1.503 - // locating register-based arguments:
1.504 - bool is_register() const { return _number < n_register_parameters; }
1.505 -
1.506 -#ifdef _LP64
1.507 - // locating Floating Point register-based arguments:
1.508 - bool is_float_register() const { return _number < n_float_register_parameters; }
1.509 -
1.510 - FloatRegister as_float_register() const {
1.511 - assert(is_float_register(), "must be a register argument");
1.512 - return as_FloatRegister(( number() *2 ) + 1);
1.513 - }
1.514 - FloatRegister as_double_register() const {
1.515 - assert(is_float_register(), "must be a register argument");
1.516 - return as_FloatRegister(( number() *2 ));
1.517 - }
1.518 -#endif
1.519 -
1.520 - Register as_register() const {
1.521 - assert(is_register(), "must be a register argument");
1.522 - return is_in() ? as_iRegister(number()) : as_oRegister(number());
1.523 - }
1.524 -
1.525 - // locating memory-based arguments
1.526 - Address as_address() const {
1.527 - assert(!is_register(), "must be a memory argument");
1.528 - return address_in_frame();
1.529 - }
1.530 -
1.531 - // When applied to a register-based argument, give the corresponding address
1.532 - // into the 6-word area "into which callee may store register arguments"
1.533 - // (This is a different place than the corresponding register-save area location.)
1.534 - Address address_in_frame() const;
1.535 -
1.536 - // debugging
1.537 - const char* name() const;
1.538 -
1.539 - friend class Assembler;
1.540 -};
1.541 -
1.542 +#include "asm/register.hpp"
1.543
1.544 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
1.545 // level; i.e., what you write
1.546 // is what you get. The Assembler is generating code into a CodeBuffer.
1.547
1.548 class Assembler : public AbstractAssembler {
1.549 - protected:
1.550 -
1.551 - static void print_instruction(int inst);
1.552 - static int patched_branch(int dest_pos, int inst, int inst_pos);
1.553 - static int branch_destination(int inst, int pos);
1.554 -
1.555 -
1.556 friend class AbstractAssembler;
1.557 friend class AddressLiteral;
1.558
1.559 @@ -1230,10 +689,7 @@
1.560 // pp 135 (addc was addx in v8)
1.561
1.562 inline void add(Register s1, Register s2, Register d );
1.563 - inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none);
1.564 - inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec);
1.565 - inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
1.566 - inline void add(const Address& a, Register d, int offset = 0);
1.567 + inline void add(Register s1, int simm13a, Register d );
1.568
1.569 void addcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1.570 void addcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.571 @@ -1395,12 +851,9 @@
1.572
1.573 // 171
1.574
1.575 - inline void ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d);
1.576 inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
1.577 inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
1.578
1.579 - inline void ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0);
1.580 -
1.581
1.582 inline void ldfsr( Register s1, Register s2 );
1.583 inline void ldfsr( Register s1, int simm13a);
1.584 @@ -1438,36 +891,9 @@
1.585 inline void lduw( Register s1, int simm13a, Register d);
1.586 inline void ldx( Register s1, Register s2, Register d );
1.587 inline void ldx( Register s1, int simm13a, Register d);
1.588 - inline void ld( Register s1, Register s2, Register d );
1.589 - inline void ld( Register s1, int simm13a, Register d);
1.590 inline void ldd( Register s1, Register s2, Register d );
1.591 inline void ldd( Register s1, int simm13a, Register d);
1.592
1.593 -#ifdef ASSERT
1.594 - // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
1.595 - inline void ld( Register s1, ByteSize simm13a, Register d);
1.596 -#endif
1.597 -
1.598 - inline void ldsb(const Address& a, Register d, int offset = 0);
1.599 - inline void ldsh(const Address& a, Register d, int offset = 0);
1.600 - inline void ldsw(const Address& a, Register d, int offset = 0);
1.601 - inline void ldub(const Address& a, Register d, int offset = 0);
1.602 - inline void lduh(const Address& a, Register d, int offset = 0);
1.603 - inline void lduw(const Address& a, Register d, int offset = 0);
1.604 - inline void ldx( const Address& a, Register d, int offset = 0);
1.605 - inline void ld( const Address& a, Register d, int offset = 0);
1.606 - inline void ldd( const Address& a, Register d, int offset = 0);
1.607 -
1.608 - inline void ldub( Register s1, RegisterOrConstant s2, Register d );
1.609 - inline void ldsb( Register s1, RegisterOrConstant s2, Register d );
1.610 - inline void lduh( Register s1, RegisterOrConstant s2, Register d );
1.611 - inline void ldsh( Register s1, RegisterOrConstant s2, Register d );
1.612 - inline void lduw( Register s1, RegisterOrConstant s2, Register d );
1.613 - inline void ldsw( Register s1, RegisterOrConstant s2, Register d );
1.614 - inline void ldx( Register s1, RegisterOrConstant s2, Register d );
1.615 - inline void ld( Register s1, RegisterOrConstant s2, Register d );
1.616 - inline void ldd( Register s1, RegisterOrConstant s2, Register d );
1.617 -
1.618 // pp 177
1.619
1.620 void ldsba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1.621 @@ -1505,7 +931,6 @@
1.622 void andcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.623 void andn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
1.624 void andn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.625 - void andn( Register s1, RegisterOrConstant s2, Register d);
1.626 void andncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1.627 void andncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.628 void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
1.629 @@ -1584,13 +1009,12 @@
1.630
1.631 // pp 203
1.632
1.633 - void prefetch( Register s1, Register s2, PrefetchFcn f);
1.634 - void prefetch( Register s1, int simm13a, PrefetchFcn f);
1.635 + void prefetch( Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
1.636 + void prefetch( Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
1.637 +
1.638 void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1.639 void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.640
1.641 - inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0);
1.642 -
1.643 // pp 208
1.644
1.645 // not implementing read privileged register
1.646 @@ -1653,10 +1077,8 @@
1.647
1.648 // pp 222
1.649
1.650 - inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2);
1.651 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
1.652 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
1.653 - inline void stf( FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0);
1.654
1.655 inline void stfsr( Register s1, Register s2 );
1.656 inline void stfsr( Register s1, int simm13a);
1.657 @@ -1676,32 +1098,11 @@
1.658 inline void sth( Register d, Register s1, int simm13a);
1.659 inline void stw( Register d, Register s1, Register s2 );
1.660 inline void stw( Register d, Register s1, int simm13a);
1.661 - inline void st( Register d, Register s1, Register s2 );
1.662 - inline void st( Register d, Register s1, int simm13a);
1.663 inline void stx( Register d, Register s1, Register s2 );
1.664 inline void stx( Register d, Register s1, int simm13a);
1.665 inline void std( Register d, Register s1, Register s2 );
1.666 inline void std( Register d, Register s1, int simm13a);
1.667
1.668 -#ifdef ASSERT
1.669 - // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
1.670 - inline void st( Register d, Register s1, ByteSize simm13a);
1.671 -#endif
1.672 -
1.673 - inline void stb( Register d, const Address& a, int offset = 0 );
1.674 - inline void sth( Register d, const Address& a, int offset = 0 );
1.675 - inline void stw( Register d, const Address& a, int offset = 0 );
1.676 - inline void stx( Register d, const Address& a, int offset = 0 );
1.677 - inline void st( Register d, const Address& a, int offset = 0 );
1.678 - inline void std( Register d, const Address& a, int offset = 0 );
1.679 -
1.680 - inline void stb( Register d, Register s1, RegisterOrConstant s2 );
1.681 - inline void sth( Register d, Register s1, RegisterOrConstant s2 );
1.682 - inline void stw( Register d, Register s1, RegisterOrConstant s2 );
1.683 - inline void stx( Register d, Register s1, RegisterOrConstant s2 );
1.684 - inline void std( Register d, Register s1, RegisterOrConstant s2 );
1.685 - inline void st( Register d, Register s1, RegisterOrConstant s2 );
1.686 -
1.687 // pp 177
1.688
1.689 void stba( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1.690 @@ -1731,9 +1132,6 @@
1.691 void sub( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); }
1.692 void sub( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.693
1.694 - // Note: offset is added to s2.
1.695 - inline void sub(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
1.696 -
1.697 void subcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
1.698 void subcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1.699 void subc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); }
1.700 @@ -1745,7 +1143,6 @@
1.701
1.702 inline void swap( Register s1, Register s2, Register d );
1.703 inline void swap( Register s1, int simm13a, Register d);
1.704 - inline void swap( Address& a, Register d, int offset = 0 );
1.705
1.706 // pp 232
1.707
1.708 @@ -1799,879 +1196,12 @@
1.709 void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_long( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
1.710 void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_long( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
1.711
1.712 -
1.713 -
1.714 -
1.715 - // For a given register condition, return the appropriate condition code
1.716 - // Condition (the one you would use to get the same effect after "tst" on
1.717 - // the target register.)
1.718 - Assembler::Condition reg_cond_to_cc_cond(RCondition in);
1.719 -
1.720 -
1.721 // Creation
1.722 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1.723 #ifdef CHECK_DELAY
1.724 delay_state = no_delay;
1.725 #endif
1.726 }
1.727 -
1.728 - // Testing
1.729 -#ifndef PRODUCT
1.730 - void test_v9();
1.731 - void test_v8_onlys();
1.732 -#endif
1.733 };
1.734
1.735 -
1.736 -class RegistersForDebugging : public StackObj {
1.737 - public:
1.738 - intptr_t i[8], l[8], o[8], g[8];
1.739 - float f[32];
1.740 - double d[32];
1.741 -
1.742 - void print(outputStream* s);
1.743 -
1.744 - static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); }
1.745 - static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); }
1.746 - static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); }
1.747 - static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); }
1.748 - static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); }
1.749 - static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); }
1.750 -
1.751 - // gen asm code to save regs
1.752 - static void save_registers(MacroAssembler* a);
1.753 -
1.754 - // restore global registers in case C code disturbed them
1.755 - static void restore_registers(MacroAssembler* a, Register r);
1.756 -
1.757 -
1.758 -};
1.759 -
1.760 -
1.761 -// MacroAssembler extends Assembler by a few frequently used macros.
1.762 -//
1.763 -// Most of the standard SPARC synthetic ops are defined here.
1.764 -// Instructions for which a 'better' code sequence exists depending
1.765 -// on arguments should also go in here.
1.766 -
1.767 -#define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__)
1.768 -#define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__)
1.769 -#define JUMP(a, temp, off) jump(a, temp, off, __FILE__, __LINE__)
1.770 -#define JUMPL(a, temp, d, off) jumpl(a, temp, d, off, __FILE__, __LINE__)
1.771 -
1.772 -
1.773 -class MacroAssembler: public Assembler {
1.774 - protected:
1.775 - // Support for VM calls
1.776 - // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1.777 - // may customize this version by overriding it for its purposes (e.g., to save/restore
1.778 - // additional registers when doing a VM call).
1.779 -#ifdef CC_INTERP
1.780 - #define VIRTUAL
1.781 -#else
1.782 - #define VIRTUAL virtual
1.783 -#endif
1.784 -
1.785 - VIRTUAL void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments);
1.786 -
1.787 - //
1.788 - // It is imperative that all calls into the VM are handled via the call_VM macros.
1.789 - // They make sure that the stack linkage is setup correctly. call_VM's correspond
1.790 - // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1.791 - //
1.792 - // This is the base routine called by the different versions of call_VM. The interpreter
1.793 - // may customize this version by overriding it for its purposes (e.g., to save/restore
1.794 - // additional registers when doing a VM call).
1.795 - //
1.796 - // A non-volatile java_thread_cache register should be specified so
1.797 - // that the G2_thread value can be preserved across the call.
1.798 - // (If java_thread_cache is noreg, then a slow get_thread call
1.799 - // will re-initialize the G2_thread.) call_VM_base returns the register that contains the
1.800 - // thread.
1.801 - //
1.802 - // If no last_java_sp is specified (noreg) than SP will be used instead.
1.803 -
1.804 - virtual void call_VM_base(
1.805 - Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1.806 - Register java_thread_cache, // the thread if computed before ; use noreg otherwise
1.807 - Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1.808 - address entry_point, // the entry point
1.809 - int number_of_arguments, // the number of arguments (w/o thread) to pop after call
1.810 - bool check_exception=true // flag which indicates if exception should be checked
1.811 - );
1.812 -
1.813 - // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1.814 - // The implementation is only non-empty for the InterpreterMacroAssembler,
1.815 - // as only the interpreter handles and ForceEarlyReturn PopFrame requests.
1.816 - virtual void check_and_handle_popframe(Register scratch_reg);
1.817 - virtual void check_and_handle_earlyret(Register scratch_reg);
1.818 -
1.819 - public:
1.820 - MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1.821 -
1.822 - // Support for NULL-checks
1.823 - //
1.824 - // Generates code that causes a NULL OS exception if the content of reg is NULL.
1.825 - // If the accessed location is M[reg + offset] and the offset is known, provide the
1.826 - // offset. No explicit code generation is needed if the offset is within a certain
1.827 - // range (0 <= offset <= page_size).
1.828 - //
1.829 - // %%%%%% Currently not done for SPARC
1.830 -
1.831 - void null_check(Register reg, int offset = -1);
1.832 - static bool needs_explicit_null_check(intptr_t offset);
1.833 -
1.834 - // support for delayed instructions
1.835 - MacroAssembler* delayed() { Assembler::delayed(); return this; }
1.836 -
1.837 - // branches that use right instruction for v8 vs. v9
1.838 - inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1.839 - inline void br( Condition c, bool a, Predict p, Label& L );
1.840 -
1.841 - inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1.842 - inline void fb( Condition c, bool a, Predict p, Label& L );
1.843 -
1.844 - // compares register with zero (32 bit) and branches (V9 and V8 instructions)
1.845 - void cmp_zero_and_br( Condition c, Register s1, Label& L, bool a = false, Predict p = pn );
1.846 - // Compares a pointer register with zero and branches on (not)null.
1.847 - // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
1.848 - void br_null ( Register s1, bool a, Predict p, Label& L );
1.849 - void br_notnull( Register s1, bool a, Predict p, Label& L );
1.850 -
1.851 - //
1.852 - // Compare registers and branch with nop in delay slot or cbcond without delay slot.
1.853 - //
1.854 - // ATTENTION: use these instructions with caution because cbcond instruction
1.855 - // has very short distance: 512 instructions (2Kbyte).
1.856 -
1.857 - // Compare integer (32 bit) values (icc only).
1.858 - void cmp_and_br_short(Register s1, Register s2, Condition c, Predict p, Label& L);
1.859 - void cmp_and_br_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
1.860 - // Platform depending version for pointer compare (icc on !LP64 and xcc on LP64).
1.861 - void cmp_and_brx_short(Register s1, Register s2, Condition c, Predict p, Label& L);
1.862 - void cmp_and_brx_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
1.863 -
1.864 - // Short branch version for compares a pointer pwith zero.
1.865 - void br_null_short ( Register s1, Predict p, Label& L );
1.866 - void br_notnull_short( Register s1, Predict p, Label& L );
1.867 -
1.868 - // unconditional short branch
1.869 - void ba_short(Label& L);
1.870 -
1.871 - inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1.872 - inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
1.873 -
1.874 - // Branch that tests xcc in LP64 and icc in !LP64
1.875 - inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1.876 - inline void brx( Condition c, bool a, Predict p, Label& L );
1.877 -
1.878 - // unconditional branch
1.879 - inline void ba( Label& L );
1.880 -
1.881 - // Branch that tests fp condition codes
1.882 - inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1.883 - inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
1.884 -
1.885 - // get PC the best way
1.886 - inline int get_pc( Register d );
1.887 -
1.888 - // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual)
1.889 - inline void cmp( Register s1, Register s2 ) { subcc( s1, s2, G0 ); }
1.890 - inline void cmp( Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); }
1.891 -
1.892 - inline void jmp( Register s1, Register s2 );
1.893 - inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
1.894 -
1.895 - // Check if the call target is out of wdisp30 range (relative to the code cache)
1.896 - static inline bool is_far_target(address d);
1.897 - inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
1.898 - inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
1.899 - inline void callr( Register s1, Register s2 );
1.900 - inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
1.901 -
1.902 - // Emits nothing on V8
1.903 - inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none );
1.904 - inline void iprefetch( Label& L);
1.905 -
1.906 - inline void tst( Register s ) { orcc( G0, s, G0 ); }
1.907 -
1.908 -#ifdef PRODUCT
1.909 - inline void ret( bool trace = TraceJumps ) { if (trace) {
1.910 - mov(I7, O7); // traceable register
1.911 - JMP(O7, 2 * BytesPerInstWord);
1.912 - } else {
1.913 - jmpl( I7, 2 * BytesPerInstWord, G0 );
1.914 - }
1.915 - }
1.916 -
1.917 - inline void retl( bool trace = TraceJumps ) { if (trace) JMP(O7, 2 * BytesPerInstWord);
1.918 - else jmpl( O7, 2 * BytesPerInstWord, G0 ); }
1.919 -#else
1.920 - void ret( bool trace = TraceJumps );
1.921 - void retl( bool trace = TraceJumps );
1.922 -#endif /* PRODUCT */
1.923 -
1.924 - // Required platform-specific helpers for Label::patch_instructions.
1.925 - // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1.926 - void pd_patch_instruction(address branch, address target);
1.927 -#ifndef PRODUCT
1.928 - static void pd_print_patched_instruction(address branch);
1.929 -#endif
1.930 -
1.931 - // sethi Macro handles optimizations and relocations
1.932 -private:
1.933 - void internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable);
1.934 -public:
1.935 - void sethi(const AddressLiteral& addrlit, Register d);
1.936 - void patchable_sethi(const AddressLiteral& addrlit, Register d);
1.937 -
1.938 - // compute the number of instructions for a sethi/set
1.939 - static int insts_for_sethi( address a, bool worst_case = false );
1.940 - static int worst_case_insts_for_set();
1.941 -
1.942 - // set may be either setsw or setuw (high 32 bits may be zero or sign)
1.943 -private:
1.944 - void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable);
1.945 - static int insts_for_internal_set(intptr_t value);
1.946 -public:
1.947 - void set(const AddressLiteral& addrlit, Register d);
1.948 - void set(intptr_t value, Register d);
1.949 - void set(address addr, Register d, RelocationHolder const& rspec);
1.950 - static int insts_for_set(intptr_t value) { return insts_for_internal_set(value); }
1.951 -
1.952 - void patchable_set(const AddressLiteral& addrlit, Register d);
1.953 - void patchable_set(intptr_t value, Register d);
1.954 - void set64(jlong value, Register d, Register tmp);
1.955 - static int insts_for_set64(jlong value);
1.956 -
1.957 - // sign-extend 32 to 64
1.958 - inline void signx( Register s, Register d ) { sra( s, G0, d); }
1.959 - inline void signx( Register d ) { sra( d, G0, d); }
1.960 -
1.961 - inline void not1( Register s, Register d ) { xnor( s, G0, d ); }
1.962 - inline void not1( Register d ) { xnor( d, G0, d ); }
1.963 -
1.964 - inline void neg( Register s, Register d ) { sub( G0, s, d ); }
1.965 - inline void neg( Register d ) { sub( G0, d, d ); }
1.966 -
1.967 - inline void cas( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); }
1.968 - inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); }
1.969 - // Functions for isolating 64 bit atomic swaps for LP64
1.970 - // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's
1.971 - inline void cas_ptr( Register s1, Register s2, Register d) {
1.972 -#ifdef _LP64
1.973 - casx( s1, s2, d );
1.974 -#else
1.975 - cas( s1, s2, d );
1.976 -#endif
1.977 - }
1.978 -
1.979 - // Functions for isolating 64 bit shifts for LP64
1.980 - inline void sll_ptr( Register s1, Register s2, Register d );
1.981 - inline void sll_ptr( Register s1, int imm6a, Register d );
1.982 - inline void sll_ptr( Register s1, RegisterOrConstant s2, Register d );
1.983 - inline void srl_ptr( Register s1, Register s2, Register d );
1.984 - inline void srl_ptr( Register s1, int imm6a, Register d );
1.985 -
1.986 - // little-endian
1.987 - inline void casl( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); }
1.988 - inline void casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); }
1.989 -
1.990 - inline void inc( Register d, int const13 = 1 ) { add( d, const13, d); }
1.991 - inline void inccc( Register d, int const13 = 1 ) { addcc( d, const13, d); }
1.992 -
1.993 - inline void dec( Register d, int const13 = 1 ) { sub( d, const13, d); }
1.994 - inline void deccc( Register d, int const13 = 1 ) { subcc( d, const13, d); }
1.995 -
1.996 - inline void btst( Register s1, Register s2 ) { andcc( s1, s2, G0 ); }
1.997 - inline void btst( int simm13a, Register s ) { andcc( s, simm13a, G0 ); }
1.998 -
1.999 - inline void bset( Register s1, Register s2 ) { or3( s1, s2, s2 ); }
1.1000 - inline void bset( int simm13a, Register s ) { or3( s, simm13a, s ); }
1.1001 -
1.1002 - inline void bclr( Register s1, Register s2 ) { andn( s1, s2, s2 ); }
1.1003 - inline void bclr( int simm13a, Register s ) { andn( s, simm13a, s ); }
1.1004 -
1.1005 - inline void btog( Register s1, Register s2 ) { xor3( s1, s2, s2 ); }
1.1006 - inline void btog( int simm13a, Register s ) { xor3( s, simm13a, s ); }
1.1007 -
1.1008 - inline void clr( Register d ) { or3( G0, G0, d ); }
1.1009 -
1.1010 - inline void clrb( Register s1, Register s2);
1.1011 - inline void clrh( Register s1, Register s2);
1.1012 - inline void clr( Register s1, Register s2);
1.1013 - inline void clrx( Register s1, Register s2);
1.1014 -
1.1015 - inline void clrb( Register s1, int simm13a);
1.1016 - inline void clrh( Register s1, int simm13a);
1.1017 - inline void clr( Register s1, int simm13a);
1.1018 - inline void clrx( Register s1, int simm13a);
1.1019 -
1.1020 - // copy & clear upper word
1.1021 - inline void clruw( Register s, Register d ) { srl( s, G0, d); }
1.1022 - // clear upper word
1.1023 - inline void clruwu( Register d ) { srl( d, G0, d); }
1.1024 -
1.1025 - // membar psuedo instruction. takes into account target memory model.
1.1026 - inline void membar( Assembler::Membar_mask_bits const7a );
1.1027 -
1.1028 - // returns if membar generates anything.
1.1029 - inline bool membar_has_effect( Assembler::Membar_mask_bits const7a );
1.1030 -
1.1031 - // mov pseudo instructions
1.1032 - inline void mov( Register s, Register d) {
1.1033 - if ( s != d ) or3( G0, s, d);
1.1034 - else assert_not_delayed(); // Put something useful in the delay slot!
1.1035 - }
1.1036 -
1.1037 - inline void mov_or_nop( Register s, Register d) {
1.1038 - if ( s != d ) or3( G0, s, d);
1.1039 - else nop();
1.1040 - }
1.1041 -
1.1042 - inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); }
1.1043 -
1.1044 - // address pseudos: make these names unlike instruction names to avoid confusion
1.1045 - inline intptr_t load_pc_address( Register reg, int bytes_to_skip );
1.1046 - inline void load_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
1.1047 - inline void load_bool_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
1.1048 - inline void load_ptr_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
1.1049 - inline void store_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0);
1.1050 - inline void store_ptr_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0);
1.1051 - inline void jumpl_to(const AddressLiteral& addrlit, Register temp, Register d, int offset = 0);
1.1052 - inline void jump_to(const AddressLiteral& addrlit, Register temp, int offset = 0);
1.1053 - inline void jump_indirect_to(Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0);
1.1054 -
1.1055 - // ring buffer traceable jumps
1.1056 -
1.1057 - void jmp2( Register r1, Register r2, const char* file, int line );
1.1058 - void jmp ( Register r1, int offset, const char* file, int line );
1.1059 -
1.1060 - void jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line);
1.1061 - void jump (const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line);
1.1062 -
1.1063 -
1.1064 - // argument pseudos:
1.1065 -
1.1066 - inline void load_argument( Argument& a, Register d );
1.1067 - inline void store_argument( Register s, Argument& a );
1.1068 - inline void store_ptr_argument( Register s, Argument& a );
1.1069 - inline void store_float_argument( FloatRegister s, Argument& a );
1.1070 - inline void store_double_argument( FloatRegister s, Argument& a );
1.1071 - inline void store_long_argument( Register s, Argument& a );
1.1072 -
1.1073 - // handy macros:
1.1074 -
1.1075 - inline void round_to( Register r, int modulus ) {
1.1076 - assert_not_delayed();
1.1077 - inc( r, modulus - 1 );
1.1078 - and3( r, -modulus, r );
1.1079 - }
1.1080 -
1.1081 - // --------------------------------------------------
1.1082 -
1.1083 - // Functions for isolating 64 bit loads for LP64
1.1084 - // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's
1.1085 - // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's
1.1086 - inline void ld_ptr(Register s1, Register s2, Register d);
1.1087 - inline void ld_ptr(Register s1, int simm13a, Register d);
1.1088 - inline void ld_ptr(Register s1, RegisterOrConstant s2, Register d);
1.1089 - inline void ld_ptr(const Address& a, Register d, int offset = 0);
1.1090 - inline void st_ptr(Register d, Register s1, Register s2);
1.1091 - inline void st_ptr(Register d, Register s1, int simm13a);
1.1092 - inline void st_ptr(Register d, Register s1, RegisterOrConstant s2);
1.1093 - inline void st_ptr(Register d, const Address& a, int offset = 0);
1.1094 -
1.1095 -#ifdef ASSERT
1.1096 - // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
1.1097 - inline void ld_ptr(Register s1, ByteSize simm13a, Register d);
1.1098 - inline void st_ptr(Register d, Register s1, ByteSize simm13a);
1.1099 -#endif
1.1100 -
1.1101 - // ld_long will perform ldd for 32 bit VM's and ldx for 64 bit VM's
1.1102 - // st_long will perform std for 32 bit VM's and stx for 64 bit VM's
1.1103 - inline void ld_long(Register s1, Register s2, Register d);
1.1104 - inline void ld_long(Register s1, int simm13a, Register d);
1.1105 - inline void ld_long(Register s1, RegisterOrConstant s2, Register d);
1.1106 - inline void ld_long(const Address& a, Register d, int offset = 0);
1.1107 - inline void st_long(Register d, Register s1, Register s2);
1.1108 - inline void st_long(Register d, Register s1, int simm13a);
1.1109 - inline void st_long(Register d, Register s1, RegisterOrConstant s2);
1.1110 - inline void st_long(Register d, const Address& a, int offset = 0);
1.1111 -
1.1112 - // Helpers for address formation.
1.1113 - // - They emit only a move if s2 is a constant zero.
1.1114 - // - If dest is a constant and either s1 or s2 is a register, the temp argument is required and becomes the result.
1.1115 - // - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant.
1.1116 - RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
1.1117 - RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
1.1118 - RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
1.1119 -
1.1120 - RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) {
1.1121 - if (is_simm13(src.constant_or_zero()))
1.1122 - return src; // register or short constant
1.1123 - guarantee(temp != noreg, "constant offset overflow");
1.1124 - set(src.as_constant(), temp);
1.1125 - return temp;
1.1126 - }
1.1127 -
1.1128 - // --------------------------------------------------
1.1129 -
1.1130 - public:
1.1131 - // traps as per trap.h (SPARC ABI?)
1.1132 -
1.1133 - void breakpoint_trap();
1.1134 - void breakpoint_trap(Condition c, CC cc);
1.1135 - void flush_windows_trap();
1.1136 - void clean_windows_trap();
1.1137 - void get_psr_trap();
1.1138 - void set_psr_trap();
1.1139 -
1.1140 - // V8/V9 flush_windows
1.1141 - void flush_windows();
1.1142 -
1.1143 - // Support for serializing memory accesses between threads
1.1144 - void serialize_memory(Register thread, Register tmp1, Register tmp2);
1.1145 -
1.1146 - // Stack frame creation/removal
1.1147 - void enter();
1.1148 - void leave();
1.1149 -
1.1150 - // V8/V9 integer multiply
1.1151 - void mult(Register s1, Register s2, Register d);
1.1152 - void mult(Register s1, int simm13a, Register d);
1.1153 -
1.1154 - // V8/V9 read and write of condition codes.
1.1155 - void read_ccr(Register d);
1.1156 - void write_ccr(Register s);
1.1157 -
1.1158 - // Manipulation of C++ bools
1.1159 - // These are idioms to flag the need for care with accessing bools but on
1.1160 - // this platform we assume byte size
1.1161 -
1.1162 - inline void stbool(Register d, const Address& a) { stb(d, a); }
1.1163 - inline void ldbool(const Address& a, Register d) { ldub(a, d); }
1.1164 - inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); }
1.1165 -
1.1166 - // klass oop manipulations if compressed
1.1167 - void load_klass(Register src_oop, Register klass);
1.1168 - void store_klass(Register klass, Register dst_oop);
1.1169 - void store_klass_gap(Register s, Register dst_oop);
1.1170 -
1.1171 - // oop manipulations
1.1172 - void load_heap_oop(const Address& s, Register d);
1.1173 - void load_heap_oop(Register s1, Register s2, Register d);
1.1174 - void load_heap_oop(Register s1, int simm13a, Register d);
1.1175 - void load_heap_oop(Register s1, RegisterOrConstant s2, Register d);
1.1176 - void store_heap_oop(Register d, Register s1, Register s2);
1.1177 - void store_heap_oop(Register d, Register s1, int simm13a);
1.1178 - void store_heap_oop(Register d, const Address& a, int offset = 0);
1.1179 -
1.1180 - void encode_heap_oop(Register src, Register dst);
1.1181 - void encode_heap_oop(Register r) {
1.1182 - encode_heap_oop(r, r);
1.1183 - }
1.1184 - void decode_heap_oop(Register src, Register dst);
1.1185 - void decode_heap_oop(Register r) {
1.1186 - decode_heap_oop(r, r);
1.1187 - }
1.1188 - void encode_heap_oop_not_null(Register r);
1.1189 - void decode_heap_oop_not_null(Register r);
1.1190 - void encode_heap_oop_not_null(Register src, Register dst);
1.1191 - void decode_heap_oop_not_null(Register src, Register dst);
1.1192 -
1.1193 - void encode_klass_not_null(Register r);
1.1194 - void decode_klass_not_null(Register r);
1.1195 - void encode_klass_not_null(Register src, Register dst);
1.1196 - void decode_klass_not_null(Register src, Register dst);
1.1197 -
1.1198 - // Support for managing the JavaThread pointer (i.e.; the reference to
1.1199 - // thread-local information).
1.1200 - void get_thread(); // load G2_thread
1.1201 - void verify_thread(); // verify G2_thread contents
1.1202 - void save_thread (const Register threache); // save to cache
1.1203 - void restore_thread(const Register thread_cache); // restore from cache
1.1204 -
1.1205 - // Support for last Java frame (but use call_VM instead where possible)
1.1206 - void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
1.1207 - void reset_last_Java_frame(void);
1.1208 -
1.1209 - // Call into the VM.
1.1210 - // Passes the thread pointer (in O0) as a prepended argument.
1.1211 - // Makes sure oop return values are visible to the GC.
1.1212 - void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
1.1213 - void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
1.1214 - void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1.1215 - void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1.1216 -
1.1217 - // these overloadings are not presently used on SPARC:
1.1218 - void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
1.1219 - void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
1.1220 - void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1.1221 - void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1.1222 -
1.1223 - void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0);
1.1224 - void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1);
1.1225 - void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2);
1.1226 - void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3);
1.1227 -
1.1228 - void get_vm_result (Register oop_result);
1.1229 - void get_vm_result_2(Register metadata_result);
1.1230 -
1.1231 - // vm result is currently getting hijacked to for oop preservation
1.1232 - void set_vm_result(Register oop_result);
1.1233 -
1.1234 - // Emit the CompiledIC call idiom
1.1235 - void ic_call(address entry, bool emit_delay = true);
1.1236 -
1.1237 - // if call_VM_base was called with check_exceptions=false, then call
1.1238 - // check_and_forward_exception to handle exceptions when it is safe
1.1239 - void check_and_forward_exception(Register scratch_reg);
1.1240 -
1.1241 - private:
1.1242 - // For V8
1.1243 - void read_ccr_trap(Register ccr_save);
1.1244 - void write_ccr_trap(Register ccr_save1, Register scratch1, Register scratch2);
1.1245 -
1.1246 -#ifdef ASSERT
1.1247 - // For V8 debugging. Uses V8 instruction sequence and checks
1.1248 - // result with V9 insturctions rdccr and wrccr.
1.1249 - // Uses Gscatch and Gscatch2
1.1250 - void read_ccr_v8_assert(Register ccr_save);
1.1251 - void write_ccr_v8_assert(Register ccr_save);
1.1252 -#endif // ASSERT
1.1253 -
1.1254 - public:
1.1255 -
1.1256 - // Write to card table for - register is destroyed afterwards.
1.1257 - void card_table_write(jbyte* byte_map_base, Register tmp, Register obj);
1.1258 -
1.1259 - void card_write_barrier_post(Register store_addr, Register new_val, Register tmp);
1.1260 -
1.1261 -#ifndef SERIALGC
1.1262 - // General G1 pre-barrier generator.
1.1263 - void g1_write_barrier_pre(Register obj, Register index, int offset, Register pre_val, Register tmp, bool preserve_o_regs);
1.1264 -
1.1265 - // General G1 post-barrier generator
1.1266 - void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp);
1.1267 -#endif // SERIALGC
1.1268 -
1.1269 - // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1.1270 - void push_fTOS();
1.1271 -
1.1272 - // pops double TOS element from CPU stack and pushes on FPU stack
1.1273 - void pop_fTOS();
1.1274 -
1.1275 - void empty_FPU_stack();
1.1276 -
1.1277 - void push_IU_state();
1.1278 - void pop_IU_state();
1.1279 -
1.1280 - void push_FPU_state();
1.1281 - void pop_FPU_state();
1.1282 -
1.1283 - void push_CPU_state();
1.1284 - void pop_CPU_state();
1.1285 -
1.1286 - // if heap base register is used - reinit it with the correct value
1.1287 - void reinit_heapbase();
1.1288 -
1.1289 - // Debugging
1.1290 - void _verify_oop(Register reg, const char * msg, const char * file, int line);
1.1291 - void _verify_oop_addr(Address addr, const char * msg, const char * file, int line);
1.1292 -
1.1293 - // TODO: verify_method and klass metadata (compare against vptr?)
1.1294 - void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1.1295 - void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1.1296 -
1.1297 -#define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__)
1.1298 -#define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__)
1.1299 -#define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1.1300 -#define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1.1301 -
1.1302 - // only if +VerifyOops
1.1303 - void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1.1304 - // only if +VerifyFPU
1.1305 - void stop(const char* msg); // prints msg, dumps registers and stops execution
1.1306 - void warn(const char* msg); // prints msg, but don't stop
1.1307 - void untested(const char* what = "");
1.1308 - void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
1.1309 - void should_not_reach_here() { stop("should not reach here"); }
1.1310 - void print_CPU_state();
1.1311 -
1.1312 - // oops in code
1.1313 - AddressLiteral allocate_oop_address(jobject obj); // allocate_index
1.1314 - AddressLiteral constant_oop_address(jobject obj); // find_index
1.1315 - inline void set_oop (jobject obj, Register d); // uses allocate_oop_address
1.1316 - inline void set_oop_constant (jobject obj, Register d); // uses constant_oop_address
1.1317 - inline void set_oop (const AddressLiteral& obj_addr, Register d); // same as load_address
1.1318 -
1.1319 - // metadata in code that we have to keep track of
1.1320 - AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index
1.1321 - AddressLiteral constant_metadata_address(Metadata* obj); // find_index
1.1322 - inline void set_metadata (Metadata* obj, Register d); // uses allocate_metadata_address
1.1323 - inline void set_metadata_constant (Metadata* obj, Register d); // uses constant_metadata_address
1.1324 - inline void set_metadata (const AddressLiteral& obj_addr, Register d); // same as load_address
1.1325 -
1.1326 - void set_narrow_oop( jobject obj, Register d );
1.1327 - void set_narrow_klass( Klass* k, Register d );
1.1328 -
1.1329 - // nop padding
1.1330 - void align(int modulus);
1.1331 -
1.1332 - // declare a safepoint
1.1333 - void safepoint();
1.1334 -
1.1335 - // factor out part of stop into subroutine to save space
1.1336 - void stop_subroutine();
1.1337 - // factor out part of verify_oop into subroutine to save space
1.1338 - void verify_oop_subroutine();
1.1339 -
1.1340 - // side-door communication with signalHandler in os_solaris.cpp
1.1341 - static address _verify_oop_implicit_branch[3];
1.1342 -
1.1343 -#ifndef PRODUCT
1.1344 - static void test();
1.1345 -#endif
1.1346 -
1.1347 - int total_frame_size_in_bytes(int extraWords);
1.1348 -
1.1349 - // used when extraWords known statically
1.1350 - void save_frame(int extraWords = 0);
1.1351 - void save_frame_c1(int size_in_bytes);
1.1352 - // make a frame, and simultaneously pass up one or two register value
1.1353 - // into the new register window
1.1354 - void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register());
1.1355 -
1.1356 - // give no. (outgoing) params, calc # of words will need on frame
1.1357 - void calc_mem_param_words(Register Rparam_words, Register Rresult);
1.1358 -
1.1359 - // used to calculate frame size dynamically
1.1360 - // result is in bytes and must be negated for save inst
1.1361 - void calc_frame_size(Register extraWords, Register resultReg);
1.1362 -
1.1363 - // calc and also save
1.1364 - void calc_frame_size_and_save(Register extraWords, Register resultReg);
1.1365 -
1.1366 - static void debug(char* msg, RegistersForDebugging* outWindow);
1.1367 -
1.1368 - // implementations of bytecodes used by both interpreter and compiler
1.1369 -
1.1370 - void lcmp( Register Ra_hi, Register Ra_low,
1.1371 - Register Rb_hi, Register Rb_low,
1.1372 - Register Rresult);
1.1373 -
1.1374 - void lneg( Register Rhi, Register Rlow );
1.1375 -
1.1376 - void lshl( Register Rin_high, Register Rin_low, Register Rcount,
1.1377 - Register Rout_high, Register Rout_low, Register Rtemp );
1.1378 -
1.1379 - void lshr( Register Rin_high, Register Rin_low, Register Rcount,
1.1380 - Register Rout_high, Register Rout_low, Register Rtemp );
1.1381 -
1.1382 - void lushr( Register Rin_high, Register Rin_low, Register Rcount,
1.1383 - Register Rout_high, Register Rout_low, Register Rtemp );
1.1384 -
1.1385 -#ifdef _LP64
1.1386 - void lcmp( Register Ra, Register Rb, Register Rresult);
1.1387 -#endif
1.1388 -
1.1389 - // Load and store values by size and signed-ness
1.1390 - void load_sized_value( Address src, Register dst, size_t size_in_bytes, bool is_signed);
1.1391 - void store_sized_value(Register src, Address dst, size_t size_in_bytes);
1.1392 -
1.1393 - void float_cmp( bool is_float, int unordered_result,
1.1394 - FloatRegister Fa, FloatRegister Fb,
1.1395 - Register Rresult);
1.1396 -
1.1397 - void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
1.1398 - void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { Assembler::fneg(w, sd); }
1.1399 - void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
1.1400 - void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
1.1401 -
1.1402 - void save_all_globals_into_locals();
1.1403 - void restore_globals_from_locals();
1.1404 -
1.1405 - void casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
1.1406 - address lock_addr=0, bool use_call_vm=false);
1.1407 - void cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
1.1408 - address lock_addr=0, bool use_call_vm=false);
1.1409 - void casn (Register addr_reg, Register cmp_reg, Register set_reg) ;
1.1410 -
1.1411 - // These set the icc condition code to equal if the lock succeeded
1.1412 - // and notEqual if it failed and requires a slow case
1.1413 - void compiler_lock_object(Register Roop, Register Rmark, Register Rbox,
1.1414 - Register Rscratch,
1.1415 - BiasedLockingCounters* counters = NULL,
1.1416 - bool try_bias = UseBiasedLocking);
1.1417 - void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox,
1.1418 - Register Rscratch,
1.1419 - bool try_bias = UseBiasedLocking);
1.1420 -
1.1421 - // Biased locking support
1.1422 - // Upon entry, lock_reg must point to the lock record on the stack,
1.1423 - // obj_reg must contain the target object, and mark_reg must contain
1.1424 - // the target object's header.
1.1425 - // Destroys mark_reg if an attempt is made to bias an anonymously
1.1426 - // biased lock. In this case a failure will go either to the slow
1.1427 - // case or fall through with the notEqual condition code set with
1.1428 - // the expectation that the slow case in the runtime will be called.
1.1429 - // In the fall-through case where the CAS-based lock is done,
1.1430 - // mark_reg is not destroyed.
1.1431 - void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg,
1.1432 - Label& done, Label* slow_case = NULL,
1.1433 - BiasedLockingCounters* counters = NULL);
1.1434 - // Upon entry, the base register of mark_addr must contain the oop.
1.1435 - // Destroys temp_reg.
1.1436 -
1.1437 - // If allow_delay_slot_filling is set to true, the next instruction
1.1438 - // emitted after this one will go in an annulled delay slot if the
1.1439 - // biased locking exit case failed.
1.1440 - void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false);
1.1441 -
1.1442 - // allocation
1.1443 - void eden_allocate(
1.1444 - Register obj, // result: pointer to object after successful allocation
1.1445 - Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1.1446 - int con_size_in_bytes, // object size in bytes if known at compile time
1.1447 - Register t1, // temp register
1.1448 - Register t2, // temp register
1.1449 - Label& slow_case // continuation point if fast allocation fails
1.1450 - );
1.1451 - void tlab_allocate(
1.1452 - Register obj, // result: pointer to object after successful allocation
1.1453 - Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1.1454 - int con_size_in_bytes, // object size in bytes if known at compile time
1.1455 - Register t1, // temp register
1.1456 - Label& slow_case // continuation point if fast allocation fails
1.1457 - );
1.1458 - void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
1.1459 - void incr_allocated_bytes(RegisterOrConstant size_in_bytes,
1.1460 - Register t1, Register t2);
1.1461 -
1.1462 - // interface method calling
1.1463 - void lookup_interface_method(Register recv_klass,
1.1464 - Register intf_klass,
1.1465 - RegisterOrConstant itable_index,
1.1466 - Register method_result,
1.1467 - Register temp_reg, Register temp2_reg,
1.1468 - Label& no_such_interface);
1.1469 -
1.1470 - // virtual method calling
1.1471 - void lookup_virtual_method(Register recv_klass,
1.1472 - RegisterOrConstant vtable_index,
1.1473 - Register method_result);
1.1474 -
1.1475 - // Test sub_klass against super_klass, with fast and slow paths.
1.1476 -
1.1477 - // The fast path produces a tri-state answer: yes / no / maybe-slow.
1.1478 - // One of the three labels can be NULL, meaning take the fall-through.
1.1479 - // If super_check_offset is -1, the value is loaded up from super_klass.
1.1480 - // No registers are killed, except temp_reg and temp2_reg.
1.1481 - // If super_check_offset is not -1, temp2_reg is not used and can be noreg.
1.1482 - void check_klass_subtype_fast_path(Register sub_klass,
1.1483 - Register super_klass,
1.1484 - Register temp_reg,
1.1485 - Register temp2_reg,
1.1486 - Label* L_success,
1.1487 - Label* L_failure,
1.1488 - Label* L_slow_path,
1.1489 - RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
1.1490 -
1.1491 - // The rest of the type check; must be wired to a corresponding fast path.
1.1492 - // It does not repeat the fast path logic, so don't use it standalone.
1.1493 - // The temp_reg can be noreg, if no temps are available.
1.1494 - // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
1.1495 - // Updates the sub's secondary super cache as necessary.
1.1496 - void check_klass_subtype_slow_path(Register sub_klass,
1.1497 - Register super_klass,
1.1498 - Register temp_reg,
1.1499 - Register temp2_reg,
1.1500 - Register temp3_reg,
1.1501 - Register temp4_reg,
1.1502 - Label* L_success,
1.1503 - Label* L_failure);
1.1504 -
1.1505 - // Simplified, combined version, good for typical uses.
1.1506 - // Falls through on failure.
1.1507 - void check_klass_subtype(Register sub_klass,
1.1508 - Register super_klass,
1.1509 - Register temp_reg,
1.1510 - Register temp2_reg,
1.1511 - Label& L_success);
1.1512 -
1.1513 - // method handles (JSR 292)
1.1514 - // offset relative to Gargs of argument at tos[arg_slot].
1.1515 - // (arg_slot == 0 means the last argument, not the first).
1.1516 - RegisterOrConstant argument_offset(RegisterOrConstant arg_slot,
1.1517 - Register temp_reg,
1.1518 - int extra_slot_offset = 0);
1.1519 - // Address of Gargs and argument_offset.
1.1520 - Address argument_address(RegisterOrConstant arg_slot,
1.1521 - Register temp_reg = noreg,
1.1522 - int extra_slot_offset = 0);
1.1523 -
1.1524 - // Stack overflow checking
1.1525 -
1.1526 - // Note: this clobbers G3_scratch
1.1527 - void bang_stack_with_offset(int offset) {
1.1528 - // stack grows down, caller passes positive offset
1.1529 - assert(offset > 0, "must bang with negative offset");
1.1530 - set((-offset)+STACK_BIAS, G3_scratch);
1.1531 - st(G0, SP, G3_scratch);
1.1532 - }
1.1533 -
1.1534 - // Writes to stack successive pages until offset reached to check for
1.1535 - // stack overflow + shadow pages. Clobbers tsp and scratch registers.
1.1536 - void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch);
1.1537 -
1.1538 - virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset);
1.1539 -
1.1540 - void verify_tlab();
1.1541 -
1.1542 - Condition negate_condition(Condition cond);
1.1543 -
1.1544 - // Helper functions for statistics gathering.
1.1545 - // Conditionally (non-atomically) increments passed counter address, preserving condition codes.
1.1546 - void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2);
1.1547 - // Unconditional increment.
1.1548 - void inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2);
1.1549 - void inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2);
1.1550 -
1.1551 - // Compare char[] arrays aligned to 4 bytes.
1.1552 - void char_arrays_equals(Register ary1, Register ary2,
1.1553 - Register limit, Register result,
1.1554 - Register chr1, Register chr2, Label& Ldone);
1.1555 - // Use BIS for zeroing
1.1556 - void bis_zeroing(Register to, Register count, Register temp, Label& Ldone);
1.1557 -
1.1558 -#undef VIRTUAL
1.1559 -
1.1560 -};
1.1561 -
1.1562 -/**
1.1563 - * class SkipIfEqual:
1.1564 - *
1.1565 - * Instantiating this class will result in assembly code being output that will
1.1566 - * jump around any code emitted between the creation of the instance and it's
1.1567 - * automatic destruction at the end of a scope block, depending on the value of
1.1568 - * the flag passed to the constructor, which will be checked at run-time.
1.1569 - */
1.1570 -class SkipIfEqual : public StackObj {
1.1571 - private:
1.1572 - MacroAssembler* _masm;
1.1573 - Label _label;
1.1574 -
1.1575 - public:
1.1576 - // 'temp' is a temp register that this object can use (and trash)
1.1577 - SkipIfEqual(MacroAssembler*, Register temp,
1.1578 - const bool* flag_addr, Assembler::Condition condition);
1.1579 - ~SkipIfEqual();
1.1580 -};
1.1581 -
1.1582 -#ifdef ASSERT
1.1583 -// On RISC, there's no benefit to verifying instruction boundaries.
1.1584 -inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1.1585 -#endif
1.1586 -
1.1587 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
