src/cpu/x86/vm/x86_64.ad

changeset 6506
f040cf9fc9c0
parent 6489
50fdb38839eb
parent 6288
984401824c5e
child 6517
a433eb716ce1
     1.1 --- a/src/cpu/x86/vm/x86_64.ad	Thu Jan 30 14:30:01 2014 +0100
     1.2 +++ b/src/cpu/x86/vm/x86_64.ad	Wed Feb 19 20:12:43 2014 -0800
     1.3 @@ -3094,6 +3094,17 @@
     1.4    interface(CONST_INTER);
     1.5  %}
     1.6  
     1.7 +// Int Immediate non-negative
     1.8 +operand immU31()
     1.9 +%{
    1.10 +  predicate(n->get_int() >= 0);
    1.11 +  match(ConI);
    1.12 +
    1.13 +  op_cost(0);
    1.14 +  format %{ %}
    1.15 +  interface(CONST_INTER);
    1.16 +%}
    1.17 +
    1.18  // Constant for long shifts
    1.19  operand immI_32()
    1.20  %{
    1.21 @@ -5050,12 +5061,12 @@
    1.22    ins_pipe(ialu_reg_mem);
    1.23  %}
    1.24  
    1.25 -// Load Integer with a 32-bit mask into Long Register
    1.26 -instruct loadI2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
    1.27 +// Load Integer with a 31-bit mask into Long Register
    1.28 +instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
    1.29    match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
    1.30    effect(KILL cr);
    1.31  
    1.32 -  format %{ "movl    $dst, $mem\t# int & 32-bit mask -> long\n\t"
    1.33 +  format %{ "movl    $dst, $mem\t# int & 31-bit mask -> long\n\t"
    1.34              "andl    $dst, $mask" %}
    1.35    ins_encode %{
    1.36      Register Rdst = $dst$$Register;

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